pci_subr.c revision 1.167
1 /* $NetBSD: pci_subr.c,v 1.167 2017/03/17 08:51:44 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.167 2017/03/17 08:51:44 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdarg.h> 58 #include <stdbool.h> 59 #include <stdio.h> 60 #include <stdlib.h> 61 #include <string.h> 62 #endif 63 64 #include <dev/pci/pcireg.h> 65 #ifdef _KERNEL 66 #include <dev/pci/pcivar.h> 67 #else 68 #include <dev/pci/pci_verbose.h> 69 #include <dev/pci/pcidevs.h> 70 #include <dev/pci/pcidevs_data.h> 71 #endif 72 73 static int pci_conf_find_cap(const pcireg_t *, int, unsigned int, int *); 74 75 /* 76 * Descriptions of known PCI classes and subclasses. 77 * 78 * Subclasses are described in the same way as classes, but have a 79 * NULL subclass pointer. 80 */ 81 struct pci_class { 82 const char *name; 83 u_int val; /* as wide as pci_{,sub}class_t */ 84 const struct pci_class *subclasses; 85 }; 86 87 /* 88 * Class 0x00. 89 * Before rev. 2.0. 90 */ 91 static const struct pci_class pci_subclass_prehistoric[] = { 92 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 93 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 94 { NULL, 0, NULL, }, 95 }; 96 97 /* 98 * Class 0x01. 99 * Mass storage controller 100 */ 101 102 /* ATA programming interface */ 103 static const struct pci_class pci_interface_ata[] = { 104 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 105 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 106 { NULL, 0, NULL, }, 107 }; 108 109 /* SATA programming interface */ 110 static const struct pci_class pci_interface_sata[] = { 111 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 112 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 113 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 114 { NULL, 0, NULL, }, 115 }; 116 117 /* Flash programming interface */ 118 static const struct pci_class pci_interface_nvm[] = { 119 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 120 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 121 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 122 { NULL, 0, NULL, }, 123 }; 124 125 /* Subclasses */ 126 static const struct pci_class pci_subclass_mass_storage[] = { 127 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 128 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 129 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 130 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 131 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 132 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 133 pci_interface_ata, }, 134 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 135 pci_interface_sata, }, 136 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 137 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 138 pci_interface_nvm, }, 139 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 140 { NULL, 0, NULL, }, 141 }; 142 143 /* 144 * Class 0x02. 145 * Network controller. 146 */ 147 static const struct pci_class pci_subclass_network[] = { 148 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 149 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 150 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 151 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 152 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 153 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 154 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 155 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 156 { NULL, 0, NULL, }, 157 }; 158 159 /* 160 * Class 0x03. 161 * Display controller. 162 */ 163 164 /* VGA programming interface */ 165 static const struct pci_class pci_interface_vga[] = { 166 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 167 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 168 { NULL, 0, NULL, }, 169 }; 170 /* Subclasses */ 171 static const struct pci_class pci_subclass_display[] = { 172 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 173 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 174 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 175 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 176 { NULL, 0, NULL, }, 177 }; 178 179 /* 180 * Class 0x04. 181 * Multimedia device. 182 */ 183 static const struct pci_class pci_subclass_multimedia[] = { 184 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 185 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 186 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 187 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 188 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 189 { NULL, 0, NULL, }, 190 }; 191 192 /* 193 * Class 0x05. 194 * Memory controller. 195 */ 196 static const struct pci_class pci_subclass_memory[] = { 197 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 198 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 199 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 200 { NULL, 0, NULL, }, 201 }; 202 203 /* 204 * Class 0x06. 205 * Bridge device. 206 */ 207 208 /* PCI bridge programming interface */ 209 static const struct pci_class pci_interface_pcibridge[] = { 210 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 211 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 212 { NULL, 0, NULL, }, 213 }; 214 215 /* Semi-transparent PCI-to-PCI bridge programming interface */ 216 static const struct pci_class pci_interface_stpci[] = { 217 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 218 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 219 { NULL, 0, NULL, }, 220 }; 221 222 /* Advanced Switching programming interface */ 223 static const struct pci_class pci_interface_advsw[] = { 224 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 225 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 226 { NULL, 0, NULL, }, 227 }; 228 229 /* Subclasses */ 230 static const struct pci_class pci_subclass_bridge[] = { 231 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 232 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 233 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 234 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 235 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 236 pci_interface_pcibridge, }, 237 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 238 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 239 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 240 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 241 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 242 pci_interface_stpci, }, 243 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 244 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 245 pci_interface_advsw, }, 246 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 247 { NULL, 0, NULL, }, 248 }; 249 250 /* 251 * Class 0x07. 252 * Simple communications controller. 253 */ 254 255 /* Serial controller programming interface */ 256 static const struct pci_class pci_interface_serial[] = { 257 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 258 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 259 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 260 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 261 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 262 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 263 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 264 { NULL, 0, NULL, }, 265 }; 266 267 /* Parallel controller programming interface */ 268 static const struct pci_class pci_interface_parallel[] = { 269 { "", PCI_INTERFACE_PARALLEL, NULL,}, 270 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 271 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 272 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 273 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 274 { NULL, 0, NULL,}, 275 }; 276 277 /* Modem programming interface */ 278 static const struct pci_class pci_interface_modem[] = { 279 { "", PCI_INTERFACE_MODEM, NULL,}, 280 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 281 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 282 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 283 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 284 { NULL, 0, NULL,}, 285 }; 286 287 /* Subclasses */ 288 static const struct pci_class pci_subclass_communications[] = { 289 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 290 pci_interface_serial, }, 291 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 292 pci_interface_parallel, }, 293 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 294 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 295 pci_interface_modem, }, 296 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 297 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 298 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 299 { NULL, 0, NULL,}, 300 }; 301 302 /* 303 * Class 0x08. 304 * Base system peripheral. 305 */ 306 307 /* PIC programming interface */ 308 static const struct pci_class pci_interface_pic[] = { 309 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 310 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 311 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 312 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 313 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 314 { NULL, 0, NULL, }, 315 }; 316 317 /* DMA programming interface */ 318 static const struct pci_class pci_interface_dma[] = { 319 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 320 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 321 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 322 { NULL, 0, NULL, }, 323 }; 324 325 /* Timer programming interface */ 326 static const struct pci_class pci_interface_tmr[] = { 327 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 328 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 329 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 330 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 331 { NULL, 0, NULL, }, 332 }; 333 334 /* RTC programming interface */ 335 static const struct pci_class pci_interface_rtc[] = { 336 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 337 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 338 { NULL, 0, NULL, }, 339 }; 340 341 /* Subclasses */ 342 static const struct pci_class pci_subclass_system[] = { 343 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 344 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 345 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 346 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 347 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 348 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 349 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 350 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 351 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 352 { NULL, 0, NULL, }, 353 }; 354 355 /* 356 * Class 0x09. 357 * Input device. 358 */ 359 360 /* Gameport programming interface */ 361 static const struct pci_class pci_interface_game[] = { 362 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 363 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 364 { NULL, 0, NULL, }, 365 }; 366 367 /* Subclasses */ 368 static const struct pci_class pci_subclass_input[] = { 369 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 370 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 371 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 372 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 373 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 374 pci_interface_game, }, 375 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 376 { NULL, 0, NULL, }, 377 }; 378 379 /* 380 * Class 0x0a. 381 * Docking station. 382 */ 383 static const struct pci_class pci_subclass_dock[] = { 384 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 385 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 386 { NULL, 0, NULL, }, 387 }; 388 389 /* 390 * Class 0x0b. 391 * Processor. 392 */ 393 static const struct pci_class pci_subclass_processor[] = { 394 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 395 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 396 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 397 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 398 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 399 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 400 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 401 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 402 { NULL, 0, NULL, }, 403 }; 404 405 /* 406 * Class 0x0c. 407 * Serial bus controller. 408 */ 409 410 /* IEEE1394 programming interface */ 411 static const struct pci_class pci_interface_ieee1394[] = { 412 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 413 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 414 { NULL, 0, NULL,}, 415 }; 416 417 /* USB programming interface */ 418 static const struct pci_class pci_interface_usb[] = { 419 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 420 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 421 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 422 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 423 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 424 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 425 { NULL, 0, NULL, }, 426 }; 427 428 /* IPMI programming interface */ 429 static const struct pci_class pci_interface_ipmi[] = { 430 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 431 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 432 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 433 { NULL, 0, NULL,}, 434 }; 435 436 /* Subclasses */ 437 static const struct pci_class pci_subclass_serialbus[] = { 438 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 439 pci_interface_ieee1394, }, 440 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 441 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 442 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 443 pci_interface_usb, }, 444 /* XXX Fiber Channel/_FIBRECHANNEL */ 445 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 446 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 447 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 448 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 449 pci_interface_ipmi, }, 450 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 451 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 452 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 453 { NULL, 0, NULL, }, 454 }; 455 456 /* 457 * Class 0x0d. 458 * Wireless Controller. 459 */ 460 static const struct pci_class pci_subclass_wireless[] = { 461 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 462 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 463 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 464 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 465 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 466 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 467 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 468 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 469 { NULL, 0, NULL, }, 470 }; 471 472 /* 473 * Class 0x0e. 474 * Intelligent IO controller. 475 */ 476 477 /* Intelligent IO programming interface */ 478 static const struct pci_class pci_interface_i2o[] = { 479 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 480 { NULL, 0, NULL,}, 481 }; 482 483 /* Subclasses */ 484 static const struct pci_class pci_subclass_i2o[] = { 485 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 486 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 487 { NULL, 0, NULL, }, 488 }; 489 490 /* 491 * Class 0x0f. 492 * Satellite communication controller. 493 */ 494 static const struct pci_class pci_subclass_satcom[] = { 495 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 496 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 497 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 498 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 499 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 500 { NULL, 0, NULL, }, 501 }; 502 503 /* 504 * Class 0x10. 505 * Encryption/Decryption controller. 506 */ 507 static const struct pci_class pci_subclass_crypto[] = { 508 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 509 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 510 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 511 { NULL, 0, NULL, }, 512 }; 513 514 /* 515 * Class 0x11. 516 * Data aquuisition and signal processing controller. 517 */ 518 static const struct pci_class pci_subclass_dasp[] = { 519 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 520 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 521 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 522 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 523 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 524 { NULL, 0, NULL, }, 525 }; 526 527 /* List of classes */ 528 static const struct pci_class pci_classes[] = { 529 { "prehistoric", PCI_CLASS_PREHISTORIC, 530 pci_subclass_prehistoric, }, 531 { "mass storage", PCI_CLASS_MASS_STORAGE, 532 pci_subclass_mass_storage, }, 533 { "network", PCI_CLASS_NETWORK, 534 pci_subclass_network, }, 535 { "display", PCI_CLASS_DISPLAY, 536 pci_subclass_display, }, 537 { "multimedia", PCI_CLASS_MULTIMEDIA, 538 pci_subclass_multimedia, }, 539 { "memory", PCI_CLASS_MEMORY, 540 pci_subclass_memory, }, 541 { "bridge", PCI_CLASS_BRIDGE, 542 pci_subclass_bridge, }, 543 { "communications", PCI_CLASS_COMMUNICATIONS, 544 pci_subclass_communications, }, 545 { "system", PCI_CLASS_SYSTEM, 546 pci_subclass_system, }, 547 { "input", PCI_CLASS_INPUT, 548 pci_subclass_input, }, 549 { "dock", PCI_CLASS_DOCK, 550 pci_subclass_dock, }, 551 { "processor", PCI_CLASS_PROCESSOR, 552 pci_subclass_processor, }, 553 { "serial bus", PCI_CLASS_SERIALBUS, 554 pci_subclass_serialbus, }, 555 { "wireless", PCI_CLASS_WIRELESS, 556 pci_subclass_wireless, }, 557 { "I2O", PCI_CLASS_I2O, 558 pci_subclass_i2o, }, 559 { "satellite comm", PCI_CLASS_SATCOM, 560 pci_subclass_satcom, }, 561 { "crypto", PCI_CLASS_CRYPTO, 562 pci_subclass_crypto, }, 563 { "DASP", PCI_CLASS_DASP, 564 pci_subclass_dasp, }, 565 { "processing accelerators", PCI_CLASS_ACCEL, 566 NULL, }, 567 { "non-essential instrumentation", PCI_CLASS_INSTRUMENT, 568 NULL, }, 569 { "undefined", PCI_CLASS_UNDEFINED, 570 NULL, }, 571 { NULL, 0, 572 NULL, }, 573 }; 574 575 DEV_VERBOSE_DEFINE(pci); 576 577 /* 578 * Append a formatted string to dest without writing more than len 579 * characters (including the trailing NUL character). dest and len 580 * are updated for use in subsequent calls to snappendf(). 581 * 582 * Returns 0 on success, a negative value if vnsprintf() fails, or 583 * a positive value if the dest buffer would have overflowed. 584 */ 585 586 static int __printflike(3,4) 587 snappendf(char **dest, size_t *len, const char * restrict fmt, ...) 588 { 589 va_list ap; 590 int count; 591 592 va_start(ap, fmt); 593 count = vsnprintf(*dest, *len, fmt, ap); 594 va_end(ap); 595 596 /* Let vsnprintf() errors bubble up to caller */ 597 if (count < 0 || *len == 0) 598 return count; 599 600 /* Handle overflow */ 601 if ((size_t)count >= *len) { 602 *dest += *len - 1; 603 *len = 1; 604 return 1; 605 } 606 607 /* Update dest & len to point at trailing NUL */ 608 *dest += count; 609 *len -= count; 610 611 return 0; 612 } 613 614 void 615 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 616 size_t l) 617 { 618 pci_class_t class; 619 pci_subclass_t subclass; 620 pci_interface_t interface; 621 pci_revision_t revision; 622 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 623 const struct pci_class *classp, *subclassp, *interfacep; 624 625 class = PCI_CLASS(class_reg); 626 subclass = PCI_SUBCLASS(class_reg); 627 interface = PCI_INTERFACE(class_reg); 628 revision = PCI_REVISION(class_reg); 629 630 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 631 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 632 PCI_PRODUCT(id_reg)); 633 634 classp = pci_classes; 635 while (classp->name != NULL) { 636 if (class == classp->val) 637 break; 638 classp++; 639 } 640 641 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 642 while (subclassp && subclassp->name != NULL) { 643 if (subclass == subclassp->val) 644 break; 645 subclassp++; 646 } 647 648 interfacep = (subclassp && subclassp->name != NULL) ? 649 subclassp->subclasses : NULL; 650 while (interfacep && interfacep->name != NULL) { 651 if (interface == interfacep->val) 652 break; 653 interfacep++; 654 } 655 656 (void)snappendf(&cp, &l, "%s %s", vendor, product); 657 if (showclass) { 658 (void)snappendf(&cp, &l, " ("); 659 if (classp->name == NULL) 660 (void)snappendf(&cp, &l, 661 "class 0x%02x, subclass 0x%02x", 662 class, subclass); 663 else { 664 if (subclassp == NULL || subclassp->name == NULL) 665 (void)snappendf(&cp, &l, 666 "%s, subclass 0x%02x", 667 classp->name, subclass); 668 else 669 (void)snappendf(&cp, &l, "%s %s", 670 subclassp->name, classp->name); 671 } 672 if ((interfacep == NULL) || (interfacep->name == NULL)) { 673 if (interface != 0) 674 (void)snappendf(&cp, &l, ", interface 0x%02x", 675 interface); 676 } else if (strncmp(interfacep->name, "", 1) != 0) 677 (void)snappendf(&cp, &l, ", %s", interfacep->name); 678 if (revision != 0) 679 (void)snappendf(&cp, &l, ", revision 0x%02x", revision); 680 (void)snappendf(&cp, &l, ")"); 681 } 682 } 683 684 #ifdef _KERNEL 685 void 686 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 687 const char *known, int addrev) 688 { 689 char devinfo[256]; 690 691 if (known) { 692 aprint_normal(": %s", known); 693 if (addrev) 694 aprint_normal(" (rev. 0x%02x)", 695 PCI_REVISION(pa->pa_class)); 696 aprint_normal("\n"); 697 } else { 698 pci_devinfo(pa->pa_id, pa->pa_class, 0, 699 devinfo, sizeof(devinfo)); 700 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 701 PCI_REVISION(pa->pa_class)); 702 } 703 if (naive) 704 aprint_naive(": %s\n", naive); 705 else 706 aprint_naive("\n"); 707 } 708 #endif 709 710 /* 711 * Print out most of the PCI configuration registers. Typically used 712 * in a device attach routine like this: 713 * 714 * #ifdef MYDEV_DEBUG 715 * printf("%s: ", device_xname(sc->sc_dev)); 716 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 717 * #endif 718 */ 719 720 #define i2o(i) ((i) * 4) 721 #define o2i(o) ((o) / 4) 722 #define onoff2(str, rval, bit, onstr, offstr) \ 723 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 724 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 725 726 static void 727 pci_conf_print_common( 728 #ifdef _KERNEL 729 pci_chipset_tag_t pc, pcitag_t tag, 730 #endif 731 const pcireg_t *regs) 732 { 733 pci_class_t class; 734 pci_subclass_t subclass; 735 pci_interface_t interface; 736 pci_revision_t revision; 737 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 738 const struct pci_class *classp, *subclassp, *interfacep; 739 const char *name; 740 pcireg_t rval; 741 unsigned int num; 742 743 rval = regs[o2i(PCI_CLASS_REG)]; 744 class = PCI_CLASS(rval); 745 subclass = PCI_SUBCLASS(rval); 746 interface = PCI_INTERFACE(rval); 747 revision = PCI_REVISION(rval); 748 749 rval = regs[o2i(PCI_ID_REG)]; 750 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 751 if (name) 752 printf(" Vendor Name: %s (0x%04x)\n", name, 753 PCI_VENDOR(rval)); 754 else 755 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 756 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 757 PCI_PRODUCT(rval)); 758 if (name) 759 printf(" Device Name: %s (0x%04x)\n", name, 760 PCI_PRODUCT(rval)); 761 else 762 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 763 764 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 765 766 printf(" Command register: 0x%04x\n", rval & 0xffff); 767 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 768 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 769 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 770 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 771 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 772 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 773 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 774 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 775 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 776 onoff("Fast back-to-back transactions", rval, 777 PCI_COMMAND_BACKTOBACK_ENABLE); 778 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 779 780 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 781 onoff("Immediate Readness", rval, PCI_STATUS_IMMD_READNESS); 782 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 783 "inactive"); 784 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 785 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 786 onoff("User Definable Features (UDF) support", rval, 787 PCI_STATUS_UDF_SUPPORT); 788 onoff("Fast back-to-back capable", rval, 789 PCI_STATUS_BACKTOBACK_SUPPORT); 790 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 791 792 printf(" DEVSEL timing: "); 793 switch (rval & PCI_STATUS_DEVSEL_MASK) { 794 case PCI_STATUS_DEVSEL_FAST: 795 printf("fast"); 796 break; 797 case PCI_STATUS_DEVSEL_MEDIUM: 798 printf("medium"); 799 break; 800 case PCI_STATUS_DEVSEL_SLOW: 801 printf("slow"); 802 break; 803 default: 804 printf("unknown/reserved"); /* XXX */ 805 break; 806 } 807 printf(" (0x%x)\n", __SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK)); 808 809 onoff("Slave signaled Target Abort", rval, 810 PCI_STATUS_TARGET_TARGET_ABORT); 811 onoff("Master received Target Abort", rval, 812 PCI_STATUS_MASTER_TARGET_ABORT); 813 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 814 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 815 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 816 817 rval = regs[o2i(PCI_CLASS_REG)]; 818 for (classp = pci_classes; classp->name != NULL; classp++) { 819 if (class == classp->val) 820 break; 821 } 822 823 /* 824 * ECN: Change Root Complex Event Collector Class Code 825 * Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type 826 * in PCIe extend capability to know whether it's RCEC or IOMMU. 827 */ 828 if ((class == PCI_CLASS_SYSTEM) 829 && (subclass == PCI_SUBCLASS_SYSTEM_IOMMU)) { 830 int pcie_capoff; 831 pcireg_t reg; 832 833 if (pci_conf_find_cap(regs, PCI_CAPLISTPTR_REG, 834 PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 835 reg = regs[o2i(pcie_capoff + PCIE_XCAP)]; 836 if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_ROOT_EVNTC) 837 subclass = PCI_SUBCLASS_SYSTEM_RCEC; 838 } 839 } 840 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 841 while (subclassp && subclassp->name != NULL) { 842 if (subclass == subclassp->val) 843 break; 844 subclassp++; 845 } 846 847 interfacep = (subclassp && subclassp->name != NULL) ? 848 subclassp->subclasses : NULL; 849 while (interfacep && interfacep->name != NULL) { 850 if (interface == interfacep->val) 851 break; 852 interfacep++; 853 } 854 855 if (classp->name != NULL) 856 printf(" Class Name: %s (0x%02x)\n", classp->name, class); 857 else 858 printf(" Class ID: 0x%02x\n", class); 859 if (subclassp != NULL && subclassp->name != NULL) 860 printf(" Subclass Name: %s (0x%02x)\n", 861 subclassp->name, PCI_SUBCLASS(rval)); 862 else 863 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 864 if ((interfacep != NULL) && (interfacep->name != NULL) 865 && (strncmp(interfacep->name, "", 1) != 0)) 866 printf(" Interface Name: %s (0x%02x)\n", 867 interfacep->name, interface); 868 else 869 printf(" Interface: 0x%02x\n", interface); 870 printf(" Revision ID: 0x%02x\n", revision); 871 872 rval = regs[o2i(PCI_BHLC_REG)]; 873 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 874 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 875 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 876 PCI_HDRTYPE(rval)); 877 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 878 num = PCI_CACHELINE(rval); 879 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 880 } 881 882 static int 883 pci_conf_print_bar( 884 #ifdef _KERNEL 885 pci_chipset_tag_t pc, pcitag_t tag, 886 #endif 887 const pcireg_t *regs, int reg, const char *name) 888 { 889 int width; 890 pcireg_t rval, rval64h; 891 bool ioen, memen; 892 pcireg_t mask, mask64h = 0; 893 894 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 895 ioen = rval & PCI_COMMAND_IO_ENABLE; 896 memen = rval & PCI_COMMAND_MEM_ENABLE; 897 898 width = 4; 899 /* 900 * Section 6.2.5.1, `Address Maps', tells us that: 901 * 902 * 1) The builtin software should have already mapped the 903 * device in a reasonable way. 904 * 905 * 2) A device which wants 2^n bytes of memory will hardwire 906 * the bottom n bits of the address to 0. As recommended, 907 * we write all 1s and see what we get back. 908 */ 909 910 rval = regs[o2i(reg)]; 911 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 912 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 913 rval64h = regs[o2i(reg + 4)]; 914 width = 8; 915 } else 916 rval64h = 0; 917 918 #ifdef _KERNEL 919 if (rval != 0 && memen) { 920 int s; 921 922 /* 923 * The following sequence seems to make some devices 924 * (e.g. host bus bridges, which don't normally 925 * have their space mapped) very unhappy, to 926 * the point of crashing the system. 927 * 928 * Therefore, if the mapping register is zero to 929 * start out with, don't bother trying. 930 */ 931 s = splhigh(); 932 pci_conf_write(pc, tag, reg, 0xffffffff); 933 mask = pci_conf_read(pc, tag, reg); 934 pci_conf_write(pc, tag, reg, rval); 935 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 936 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 937 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 938 mask64h = pci_conf_read(pc, tag, reg + 4); 939 pci_conf_write(pc, tag, reg + 4, rval64h); 940 } 941 splx(s); 942 } else 943 #endif /* _KERNEL */ 944 { 945 mask = regs[o2i(reg)]; 946 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 947 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) 948 mask64h = regs[o2i(reg + 4)]; 949 } 950 951 printf(" Base address register at 0x%02x", reg); 952 if (name) 953 printf(" (%s)", name); 954 printf("\n "); 955 if (rval == 0) { 956 printf("not implemented\n"); 957 return width; 958 } 959 printf("type: "); 960 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 961 const char *type, *prefetch; 962 963 switch (PCI_MAPREG_MEM_TYPE(rval)) { 964 case PCI_MAPREG_MEM_TYPE_32BIT: 965 type = "32-bit"; 966 break; 967 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 968 type = "32-bit-1M"; 969 break; 970 case PCI_MAPREG_MEM_TYPE_64BIT: 971 type = "64-bit"; 972 break; 973 default: 974 type = "unknown (XXX)"; 975 break; 976 } 977 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 978 prefetch = ""; 979 else 980 prefetch = "non"; 981 printf("%s %sprefetchable memory\n", type, prefetch); 982 switch (PCI_MAPREG_MEM_TYPE(rval)) { 983 case PCI_MAPREG_MEM_TYPE_64BIT: 984 printf(" base: 0x%016llx\n", 985 PCI_MAPREG_MEM64_ADDR( 986 ((((long long) rval64h) << 32) | rval))); 987 printf(" size: 0x%016llx", 988 PCI_MAPREG_MEM64_SIZE( 989 ((((long long) mask64h) << 32) | mask))); 990 if (!memen) 991 printf(", disabled"); 992 printf("\n"); 993 break; 994 case PCI_MAPREG_MEM_TYPE_32BIT: 995 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 996 default: 997 printf(" base: 0x%08x\n", 998 PCI_MAPREG_MEM_ADDR(rval)), 999 printf(" size: 0x%08x", 1000 PCI_MAPREG_MEM_SIZE(mask)); 1001 if (!memen) 1002 printf(", disabled"); 1003 printf("\n"); 1004 break; 1005 } 1006 } else { 1007 printf("%d-bit I/O\n", mask & ~0x0000ffff ? 32 : 16); 1008 printf(" base: 0x%08x\n", PCI_MAPREG_IO_ADDR(rval)); 1009 printf(" size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 1010 if (!ioen) 1011 printf(", disabled"); 1012 printf("\n"); 1013 } 1014 1015 return width; 1016 } 1017 1018 static void 1019 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 1020 { 1021 int off, needaddr, neednl; 1022 1023 needaddr = 1; 1024 neednl = 0; 1025 for (off = first; off < pastlast; off += 4) { 1026 if ((off % 16) == 0 || needaddr) { 1027 printf(" 0x%02x:", off); 1028 needaddr = 0; 1029 } 1030 printf(" 0x%08x", regs[o2i(off)]); 1031 neednl = 1; 1032 if ((off % 16) == 12) { 1033 printf("\n"); 1034 neednl = 0; 1035 } 1036 } 1037 if (neednl) 1038 printf("\n"); 1039 } 1040 1041 static const char * 1042 pci_conf_print_agp_calcycle(uint8_t cal) 1043 { 1044 1045 switch (cal) { 1046 case 0x0: 1047 return "4ms"; 1048 case 0x1: 1049 return "16ms"; 1050 case 0x2: 1051 return "64ms"; 1052 case 0x3: 1053 return "256ms"; 1054 case 0x7: 1055 return "Calibration Cycle Not Needed"; 1056 default: 1057 return "(reserved)"; 1058 } 1059 } 1060 1061 static void 1062 pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3) 1063 { 1064 if (isagp3) { 1065 /* AGP 3.0 */ 1066 if (reg & AGP_MODE_V3_RATE_4x) 1067 printf("x4"); 1068 if (reg & AGP_MODE_V3_RATE_8x) 1069 printf("x8"); 1070 } else { 1071 /* AGP 2.0 */ 1072 if (reg & AGP_MODE_V2_RATE_1x) 1073 printf("x1"); 1074 if (reg & AGP_MODE_V2_RATE_2x) 1075 printf("x2"); 1076 if (reg & AGP_MODE_V2_RATE_4x) 1077 printf("x4"); 1078 } 1079 printf("\n"); 1080 } 1081 1082 static void 1083 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1084 { 1085 pcireg_t rval; 1086 bool isagp3; 1087 1088 printf("\n AGP Capabilities Register\n"); 1089 1090 rval = regs[o2i(capoff)]; 1091 printf(" Revision: %d.%d\n", 1092 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1093 1094 rval = regs[o2i(capoff + PCI_AGP_STATUS)]; 1095 printf(" Status register: 0x%04x\n", rval); 1096 printf(" RQ: %d\n", 1097 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1098 printf(" ARQSZ: %d\n", 1099 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1100 printf(" CAL cycle: %s\n", 1101 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1102 onoff("SBA", rval, AGP_MODE_SBA); 1103 onoff("htrans#", rval, AGP_MODE_HTRANS); 1104 onoff("Over 4G", rval, AGP_MODE_4G); 1105 onoff("Fast Write", rval, AGP_MODE_FW); 1106 onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3); 1107 isagp3 = rval & AGP_MODE_MODE_3; 1108 printf(" Data Rate Support: "); 1109 pci_conf_print_agp_datarate(rval, isagp3); 1110 1111 rval = regs[o2i(capoff + PCI_AGP_COMMAND)]; 1112 printf(" Command register: 0x%08x\n", rval); 1113 printf(" PRQ: %d\n", 1114 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1115 printf(" PARQSZ: %d\n", 1116 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1117 printf(" PCAL cycle: %s\n", 1118 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1119 onoff("SBA", rval, AGP_MODE_SBA); 1120 onoff("AGP", rval, AGP_MODE_AGP); 1121 onoff("Over 4G", rval, AGP_MODE_4G); 1122 onoff("Fast Write", rval, AGP_MODE_FW); 1123 if (isagp3) { 1124 printf(" Data Rate Enable: "); 1125 /* 1126 * The Data Rate Enable bits are used only on 3.0 and the 1127 * Command register has no AGP_MODE_MODE_3 bit, so pass the 1128 * flag to print correctly. 1129 */ 1130 pci_conf_print_agp_datarate(rval, isagp3); 1131 } 1132 } 1133 1134 static const char * 1135 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1136 { 1137 1138 switch ((caps >> 6) & 7) { 1139 case 0: return "self-powered"; 1140 case 1: return "55 mA"; 1141 case 2: return "100 mA"; 1142 case 3: return "160 mA"; 1143 case 4: return "220 mA"; 1144 case 5: return "270 mA"; 1145 case 6: return "320 mA"; 1146 case 7: 1147 default: return "375 mA"; 1148 } 1149 } 1150 1151 static const char * 1152 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1153 { 1154 static const char unk[] = "unknown"; 1155 static const char *pmrev[8] = { 1156 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1157 }; 1158 if (val > 7) 1159 return unk; 1160 return pmrev[val]; 1161 } 1162 1163 static void 1164 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1165 { 1166 uint16_t caps, pmcsr; 1167 pcireg_t reg; 1168 1169 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1170 reg = regs[o2i(capoff + PCI_PMCSR)]; 1171 pmcsr = reg & 0xffff; 1172 1173 printf("\n PCI Power Management Capabilities Register\n"); 1174 1175 printf(" Capabilities register: 0x%04x\n", caps); 1176 printf(" Version: %s\n", 1177 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1178 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1179 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1180 printf(" 3.3V auxiliary current: %s\n", 1181 pci_conf_print_pcipm_cap_aux(caps)); 1182 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1183 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1184 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1185 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1186 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1187 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1188 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1189 1190 printf(" Control/status register: 0x%04x\n", pmcsr); 1191 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1192 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1193 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1194 printf(" PME# assertion: %sabled\n", 1195 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1196 printf(" Data Select: %d\n", 1197 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK)); 1198 printf(" Data Scale: %d\n", 1199 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK)); 1200 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1201 printf(" Bridge Support Extensions register: 0x%02x\n", 1202 (reg >> 16) & 0xff); 1203 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1204 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1205 printf(" Data register: 0x%02x\n", __SHIFTOUT(reg, PCI_PMCSR_DATA)); 1206 1207 } 1208 1209 /* XXX pci_conf_print_vpd_cap */ 1210 /* XXX pci_conf_print_slotid_cap */ 1211 1212 static void 1213 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1214 { 1215 uint32_t ctl, mmc, mme; 1216 1217 regs += o2i(capoff); 1218 ctl = *regs++; 1219 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1220 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1221 1222 printf("\n PCI Message Signaled Interrupt\n"); 1223 1224 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1225 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1226 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1227 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1228 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1229 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1230 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1231 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1232 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP); 1233 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN); 1234 printf(" Message Address %sregister: 0x%08x\n", 1235 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1236 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1237 printf(" Message Address %sregister: 0x%08x\n", 1238 "(upper) ", *regs++); 1239 } 1240 printf(" Message Data register: 0x%04x\n", *regs & 0xffff); 1241 regs++; 1242 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1243 printf(" Vector Mask register: 0x%08x\n", *regs++); 1244 printf(" Vector Pending register: 0x%08x\n", *regs++); 1245 } 1246 } 1247 1248 /* XXX pci_conf_print_cpci_hostwap_cap */ 1249 1250 /* 1251 * For both command register and status register. 1252 * The argument "idx" is index number (0 to 7). 1253 */ 1254 static int 1255 pcix_split_trans(unsigned int idx) 1256 { 1257 static int table[8] = { 1258 1, 2, 3, 4, 8, 12, 16, 32 1259 }; 1260 1261 if (idx >= __arraycount(table)) 1262 return -1; 1263 return table[idx]; 1264 } 1265 1266 static void 1267 pci_conf_print_pcix_cap_2ndbusmode(int num) 1268 { 1269 const char *maxfreq, *maxperiod; 1270 1271 printf(" Mode: "); 1272 if (num <= 0x07) 1273 printf("PCI-X Mode 1\n"); 1274 else if (num <= 0x0b) 1275 printf("PCI-X 266 (Mode 2)\n"); 1276 else 1277 printf("PCI-X 533 (Mode 2)\n"); 1278 1279 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1280 switch (num & 0x03) { 1281 default: 1282 case 0: 1283 maxfreq = "N/A"; 1284 maxperiod = "N/A"; 1285 break; 1286 case 1: 1287 maxfreq = "66MHz"; 1288 maxperiod = "15ns"; 1289 break; 1290 case 2: 1291 maxfreq = "100MHz"; 1292 maxperiod = "10ns"; 1293 break; 1294 case 3: 1295 maxfreq = "133MHz"; 1296 maxperiod = "7.5ns"; 1297 break; 1298 } 1299 printf(" Max Clock Freq: %s\n", maxfreq); 1300 printf(" Min Clock Period: %s\n", maxperiod); 1301 } 1302 1303 static void 1304 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1305 { 1306 pcireg_t reg; 1307 int isbridge; 1308 int i; 1309 1310 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1311 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1312 printf("\n PCI-X %s Capabilities Register\n", 1313 isbridge ? "Bridge" : "Non-bridge"); 1314 1315 reg = regs[o2i(capoff)]; 1316 if (isbridge != 0) { 1317 printf(" Secondary status register: 0x%04x\n", 1318 (reg & 0xffff0000) >> 16); 1319 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1320 onoff("133MHz capable", reg, PCIX_STATUS_133); 1321 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1322 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1323 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1324 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1325 pci_conf_print_pcix_cap_2ndbusmode( 1326 __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1327 printf(" Version: 0x%x\n", 1328 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1329 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1330 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1331 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1332 } else { 1333 printf(" Command register: 0x%04x\n", 1334 (reg & 0xffff0000) >> 16); 1335 onoff("Data Parity Error Recovery", reg, 1336 PCIX_CMD_PERR_RECOVER); 1337 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1338 printf(" Maximum Burst Read Count: %u\n", 1339 PCIX_CMD_BYTECNT(reg)); 1340 printf(" Maximum Split Transactions: %d\n", 1341 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1342 >> PCIX_CMD_SPLTRANS_SHIFT)); 1343 } 1344 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1345 printf(" %sStatus register: 0x%08x\n", 1346 isbridge ? "Bridge " : "", reg); 1347 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1348 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1349 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1350 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1351 onoff("133MHz capable", reg, PCIX_STATUS_133); 1352 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1353 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1354 if (isbridge != 0) { 1355 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1356 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1357 } else { 1358 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1359 "bridge device", "simple device"); 1360 printf(" Designed max memory read byte count: %d\n", 1361 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1362 >> PCIX_STATUS_MAXB_SHIFT)); 1363 printf(" Designed max outstanding split transaction: %d\n", 1364 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1365 >> PCIX_STATUS_MAXST_SHIFT)); 1366 printf(" MAX cumulative Read Size: %u\n", 1367 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1368 onoff("Received split completion error", reg, 1369 PCIX_STATUS_SCERR); 1370 } 1371 onoff("266MHz capable", reg, PCIX_STATUS_266); 1372 onoff("533MHz capable", reg, PCIX_STATUS_533); 1373 1374 if (isbridge == 0) 1375 return; 1376 1377 /* Only for bridge */ 1378 for (i = 0; i < 2; i++) { 1379 reg = regs[o2i(capoff + PCIX_BRIDGE_UP_STCR + (4 * i))]; 1380 printf(" %s split transaction control register: 0x%08x\n", 1381 (i == 0) ? "Upstream" : "Downstream", reg); 1382 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1383 printf(" Commitment Limit: %d\n", 1384 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1385 } 1386 } 1387 1388 /* pci_conf_print_ht_slave_cap */ 1389 /* pci_conf_print_ht_host_cap */ 1390 /* pci_conf_print_ht_switch_cap */ 1391 /* pci_conf_print_ht_intr_cap */ 1392 /* pci_conf_print_ht_revid_cap */ 1393 /* pci_conf_print_ht_unitid_cap */ 1394 /* pci_conf_print_ht_extcnf_cap */ 1395 /* pci_conf_print_ht_addrmap_cap */ 1396 /* pci_conf_print_ht_msimap_cap */ 1397 1398 static void 1399 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1400 { 1401 pcireg_t val; 1402 uint32_t lo, hi; 1403 1404 /* 1405 * Print the rest of the command register bits. Others are 1406 * printed in pci_conf_print_ht_cap(). 1407 */ 1408 val = regs[o2i(capoff + PCI_HT_CMD)]; 1409 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1410 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1411 1412 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1413 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1414 printf(" Address Low register: 0x%08x\n", lo); 1415 printf(" Address high register: 0x%08x\n", hi); 1416 printf(" Address: 0x%016" PRIx64 "\n", 1417 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1418 } 1419 1420 /* pci_conf_print_ht_droute_cap */ 1421 /* pci_conf_print_ht_vcset_cap */ 1422 /* pci_conf_print_ht_retry_cap */ 1423 /* pci_conf_print_ht_x86enc_cap */ 1424 /* pci_conf_print_ht_gen3_cap */ 1425 /* pci_conf_print_ht_fle_cap */ 1426 /* pci_conf_print_ht_pm_cap */ 1427 /* pci_conf_print_ht_hnc_cap */ 1428 1429 static const struct ht_types { 1430 pcireg_t cap; 1431 const char *name; 1432 void (*printfunc)(const pcireg_t *, int); 1433 } ht_captab[] = { 1434 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1435 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1436 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1437 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1438 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1439 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1440 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1441 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1442 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1443 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1444 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1445 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1446 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1447 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1448 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1449 {PCI_HT_CAP_PM, "Power Management", NULL }, 1450 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1451 }; 1452 1453 static void 1454 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1455 { 1456 pcireg_t val, foundcap; 1457 unsigned int off; 1458 1459 val = regs[o2i(capoff + PCI_HT_CMD)]; 1460 1461 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1462 1463 printf(" Command register: 0x%04x\n", val >> 16); 1464 foundcap = PCI_HT_CAP(val); 1465 for (off = 0; off < __arraycount(ht_captab); off++) { 1466 if (ht_captab[off].cap == foundcap) 1467 break; 1468 } 1469 printf(" Capability Type: 0x%02x ", foundcap); 1470 if (off >= __arraycount(ht_captab)) { 1471 printf("(unknown)\n"); 1472 return; 1473 } 1474 printf("(%s)\n", ht_captab[off].name); 1475 if (ht_captab[off].printfunc != NULL) 1476 ht_captab[off].printfunc(regs, capoff); 1477 } 1478 1479 static void 1480 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1481 { 1482 uint16_t caps; 1483 1484 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1485 1486 printf("\n PCI Vendor Specific Capabilities Register\n"); 1487 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1488 } 1489 1490 static void 1491 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1492 { 1493 pcireg_t val; 1494 1495 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1496 1497 printf("\n Debugport Capability Register\n"); 1498 printf(" Debug base Register: 0x%04x\n", 1499 val >> PCI_DEBUG_BASER_SHIFT); 1500 printf(" port offset: 0x%04x\n", 1501 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1502 printf(" BAR number: %u\n", 1503 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1504 } 1505 1506 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1507 /* XXX pci_conf_print_hotplug_cap */ 1508 1509 static void 1510 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1511 { 1512 pcireg_t reg; 1513 1514 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1515 1516 printf("\n Subsystem ID Capability Register\n"); 1517 printf(" Subsystem ID : 0x%08x\n", reg); 1518 } 1519 1520 /* XXX pci_conf_print_agp8_cap */ 1521 /* XXX pci_conf_print_secure_cap */ 1522 1523 static void 1524 pci_print_pcie_L0s_latency(uint32_t val) 1525 { 1526 1527 switch (val) { 1528 case 0x0: 1529 printf("Less than 64ns\n"); 1530 break; 1531 case 0x1: 1532 case 0x2: 1533 case 0x3: 1534 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1535 break; 1536 case 0x4: 1537 printf("512ns to less than 1us\n"); 1538 break; 1539 case 0x5: 1540 printf("1us to less than 2us\n"); 1541 break; 1542 case 0x6: 1543 printf("2us - 4us\n"); 1544 break; 1545 case 0x7: 1546 printf("More than 4us\n"); 1547 break; 1548 } 1549 } 1550 1551 static void 1552 pci_print_pcie_L1_latency(uint32_t val) 1553 { 1554 1555 switch (val) { 1556 case 0x0: 1557 printf("Less than 1us\n"); 1558 break; 1559 case 0x6: 1560 printf("32us - 64us\n"); 1561 break; 1562 case 0x7: 1563 printf("More than 64us\n"); 1564 break; 1565 default: 1566 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1567 break; 1568 } 1569 } 1570 1571 static void 1572 pci_print_pcie_compl_timeout(uint32_t val) 1573 { 1574 1575 switch (val) { 1576 case 0x0: 1577 printf("50us to 50ms\n"); 1578 break; 1579 case 0x5: 1580 printf("16ms to 55ms\n"); 1581 break; 1582 case 0x6: 1583 printf("65ms to 210ms\n"); 1584 break; 1585 case 0x9: 1586 printf("260ms to 900ms\n"); 1587 break; 1588 case 0xa: 1589 printf("1s to 3.5s\n"); 1590 break; 1591 default: 1592 printf("unknown %u value\n", val); 1593 break; 1594 } 1595 } 1596 1597 static const char * const pcie_linkspeeds[] = {"2.5", "2.5", "5.0", "8.0"}; 1598 1599 static void 1600 pci_print_pcie_linkspeed(pcireg_t val) 1601 { 1602 1603 if (val > __arraycount(pcie_linkspeeds)) 1604 printf("unknown value (%u)\n", val); 1605 else 1606 printf("%sGT/s\n", pcie_linkspeeds[val]); 1607 } 1608 1609 static void 1610 pci_print_pcie_linkspeedvector(pcireg_t val) 1611 { 1612 unsigned int i; 1613 1614 /* Start from 0 */ 1615 for (i = 0; i < 16; i++) 1616 if (((val >> i) & 0x01) != 0) { 1617 if (i >= __arraycount(pcie_linkspeeds)) 1618 printf(" unknown vector (0x%x)", 1 << i); 1619 else 1620 printf(" %sGT/s", pcie_linkspeeds[i]); 1621 } 1622 } 1623 1624 static void 1625 pci_print_pcie_link_deemphasis(pcireg_t val) 1626 { 1627 switch (val) { 1628 case 0: 1629 printf("-6dB"); 1630 break; 1631 case 1: 1632 printf("-3.5dB"); 1633 break; 1634 default: 1635 printf("(reserved value)"); 1636 } 1637 } 1638 1639 static void 1640 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1641 { 1642 pcireg_t reg; /* for each register */ 1643 pcireg_t val; /* for each bitfield */ 1644 bool check_link = false; 1645 bool check_slot = false; 1646 bool check_rootport = false; 1647 unsigned int pciever; 1648 unsigned int i; 1649 1650 printf("\n PCI Express Capabilities Register\n"); 1651 /* Capability Register */ 1652 reg = regs[o2i(capoff)]; 1653 printf(" Capability register: 0x%04x\n", reg >> 16); 1654 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1655 printf(" Capability version: %u\n", pciever); 1656 printf(" Device type: "); 1657 switch ((reg & 0x00f00000) >> 20) { 1658 case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */ 1659 printf("PCI Express Endpoint device\n"); 1660 check_link = true; 1661 break; 1662 case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */ 1663 printf("Legacy PCI Express Endpoint device\n"); 1664 check_link = true; 1665 break; 1666 case PCIE_XCAP_TYPE_ROOT: /* 0x4 */ 1667 printf("Root Port of PCI Express Root Complex\n"); 1668 check_link = true; 1669 check_slot = true; 1670 check_rootport = true; 1671 break; 1672 case PCIE_XCAP_TYPE_UP: /* 0x5 */ 1673 printf("Upstream Port of PCI Express Switch\n"); 1674 break; 1675 case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ 1676 printf("Downstream Port of PCI Express Switch\n"); 1677 check_slot = true; 1678 check_rootport = true; 1679 break; 1680 case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ 1681 printf("PCI Express to PCI/PCI-X Bridge\n"); 1682 break; 1683 case PCIE_XCAP_TYPE_PCI2PCIE: /* 0x8 */ 1684 printf("PCI/PCI-X to PCI Express Bridge\n"); 1685 break; 1686 case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */ 1687 printf("Root Complex Integrated Endpoint\n"); 1688 break; 1689 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */ 1690 check_rootport = true; 1691 printf("Root Complex Event Collector\n"); 1692 break; 1693 default: 1694 printf("unknown\n"); 1695 break; 1696 } 1697 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1698 printf(" Interrupt Message Number: 0x%02x\n", 1699 (unsigned int)__SHIFTOUT(reg, PCIE_XCAP_IRQ)); 1700 1701 /* Device Capability Register */ 1702 reg = regs[o2i(capoff + PCIE_DCAP)]; 1703 printf(" Device Capabilities Register: 0x%08x\n", reg); 1704 printf(" Max Payload Size Supported: %u bytes max\n", 1705 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1706 printf(" Phantom Functions Supported: "); 1707 switch (__SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) { 1708 case 0x0: 1709 printf("not available\n"); 1710 break; 1711 case 0x1: 1712 printf("MSB\n"); 1713 break; 1714 case 0x2: 1715 printf("two MSB\n"); 1716 break; 1717 case 0x3: 1718 printf("All three bits\n"); 1719 break; 1720 } 1721 printf(" Extended Tag Field Supported: %dbit\n", 1722 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1723 printf(" Endpoint L0 Acceptable Latency: "); 1724 pci_print_pcie_L0s_latency(__SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY)); 1725 printf(" Endpoint L1 Acceptable Latency: "); 1726 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY)); 1727 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1728 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1729 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1730 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1731 printf(" Captured Slot Power Limit Value: %u\n", 1732 (unsigned int)__SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL)); 1733 printf(" Captured Slot Power Limit Scale: %u\n", 1734 (unsigned int)__SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE)); 1735 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1736 1737 /* Device Control Register */ 1738 reg = regs[o2i(capoff + PCIE_DCSR)]; 1739 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1740 onoff("Correctable Error Reporting Enable", reg, 1741 PCIE_DCSR_ENA_COR_ERR); 1742 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1743 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1744 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1745 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1746 printf(" Max Payload Size: %d byte\n", 1747 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD)); 1748 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1749 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1750 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1751 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1752 printf(" Max Read Request Size: %d byte\n", 1753 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ)); 1754 1755 /* Device Status Register */ 1756 reg = regs[o2i(capoff + PCIE_DCSR)]; 1757 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1758 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1759 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1760 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1761 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1762 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1763 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1764 onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD); 1765 1766 if (check_link) { 1767 /* Link Capability Register */ 1768 reg = regs[o2i(capoff + PCIE_LCAP)]; 1769 printf(" Link Capabilities Register: 0x%08x\n", reg); 1770 printf(" Maximum Link Speed: "); 1771 pci_print_pcie_linkspeed(reg & PCIE_LCAP_MAX_SPEED); 1772 printf(" Maximum Link Width: x%u lanes\n", 1773 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH)); 1774 printf(" Active State PM Support: "); 1775 switch (__SHIFTOUT(reg, PCIE_LCAP_ASPM)) { 1776 case 0x0: 1777 printf("No ASPM support\n"); 1778 break; 1779 case 0x1: 1780 printf("L0s supported\n"); 1781 break; 1782 case 0x2: 1783 printf("L1 supported\n"); 1784 break; 1785 case 0x3: 1786 printf("L0s and L1 supported\n"); 1787 break; 1788 } 1789 printf(" L0 Exit Latency: "); 1790 pci_print_pcie_L0s_latency(__SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT)); 1791 printf(" L1 Exit Latency: "); 1792 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_LCAP_L1_EXIT)); 1793 printf(" Port Number: %u\n", 1794 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_PORT)); 1795 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1796 onoff("Surprise Down Error Report", reg, 1797 PCIE_LCAP_SURPRISE_DOWN); 1798 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1799 onoff("Link BW Notification Capable", reg, 1800 PCIE_LCAP_LINK_BW_NOTIFY); 1801 onoff("ASPM Optionally Compliance", reg, 1802 PCIE_LCAP_ASPM_COMPLIANCE); 1803 1804 /* Link Control Register */ 1805 reg = regs[o2i(capoff + PCIE_LCSR)]; 1806 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1807 printf(" Active State PM Control: "); 1808 switch (reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S)) { 1809 case 0: 1810 printf("disabled\n"); 1811 break; 1812 case 1: 1813 printf("L0s Entry Enabled\n"); 1814 break; 1815 case 2: 1816 printf("L1 Entry Enabled\n"); 1817 break; 1818 case 3: 1819 printf("L0s and L1 Entry Enabled\n"); 1820 break; 1821 } 1822 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1823 "128bytes", "64bytes"); 1824 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1825 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1826 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1827 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1828 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1829 onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD); 1830 onoff("Link Bandwidth Management Interrupt Enable", reg, 1831 PCIE_LCSR_LBMIE); 1832 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1833 PCIE_LCSR_LABIE); 1834 printf(" DRS Signaling Control: "); 1835 switch (__SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) { 1836 case 0: 1837 printf("not reported\n"); 1838 break; 1839 case 1: 1840 printf("Interrupt Enabled\n"); 1841 break; 1842 case 2: 1843 printf("DRS to FRS Signaling Enabled\n"); 1844 break; 1845 default: 1846 printf("reserved\n"); 1847 break; 1848 } 1849 1850 /* Link Status Register */ 1851 reg = regs[o2i(capoff + PCIE_LCSR)]; 1852 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1853 printf(" Negotiated Link Speed: "); 1854 pci_print_pcie_linkspeed(__SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 1855 printf(" Negotiated Link Width: x%u lanes\n", 1856 (unsigned int)__SHIFTOUT(reg, PCIE_LCSR_NLW)); 1857 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1858 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1859 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1860 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1861 onoff("Link Bandwidth Management Status", reg, 1862 PCIE_LCSR_LINK_BW_MGMT); 1863 onoff("Link Autonomous Bandwidth Status", reg, 1864 PCIE_LCSR_LINK_AUTO_BW); 1865 } 1866 1867 if (check_slot == true) { 1868 /* Slot Capability Register */ 1869 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1870 printf(" Slot Capability Register: 0x%08x\n", reg); 1871 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1872 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1873 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1874 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1875 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1876 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1877 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1878 printf(" Slot Power Limit Value: %d\n", 1879 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1880 printf(" Slot Power Limit Scale: %d\n", 1881 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1882 onoff("Electromechanical Interlock Present", reg, 1883 PCIE_SLCAP_EIP); 1884 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1885 printf(" Physical Slot Number: %d\n", 1886 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1887 1888 /* Slot Control Register */ 1889 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1890 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1891 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1892 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1893 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1894 onoff("Presense Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1895 onoff("Command Completed Interrupt Enabled", reg, 1896 PCIE_SLCSR_CCE); 1897 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1898 printf(" Attention Indicator Control: "); 1899 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1900 case 0x0: 1901 printf("reserved\n"); 1902 break; 1903 case 0x1: 1904 printf("on\n"); 1905 break; 1906 case 0x2: 1907 printf("blink\n"); 1908 break; 1909 case 0x3: 1910 printf("off\n"); 1911 break; 1912 } 1913 printf(" Power Indicator Control: "); 1914 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1915 case 0x0: 1916 printf("reserved\n"); 1917 break; 1918 case 0x1: 1919 printf("on\n"); 1920 break; 1921 case 0x2: 1922 printf("blink\n"); 1923 break; 1924 case 0x3: 1925 printf("off\n"); 1926 break; 1927 } 1928 printf(" Power Controller Control: Power %s\n", 1929 reg & PCIE_SLCSR_PCC ? "off" : "on"); 1930 onoff("Electromechanical Interlock Control", 1931 reg, PCIE_SLCSR_EIC); 1932 onoff("Data Link Layer State Changed Enable", reg, 1933 PCIE_SLCSR_DLLSCE); 1934 onoff("Auto Slot Power Limit Disable", reg, 1935 PCIE_SLCSR_AUTOSPLDIS); 1936 1937 /* Slot Status Register */ 1938 printf(" Slot Status Register: 0x%04x\n", reg >> 16); 1939 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1940 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1941 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1942 onoff("Presense Detect Changed", reg, PCIE_SLCSR_PDC); 1943 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1944 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1945 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1946 onoff("Electromechanical Interlock engaged", reg, 1947 PCIE_SLCSR_EIS); 1948 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1949 } 1950 1951 if (check_rootport == true) { 1952 /* Root Control Register */ 1953 reg = regs[o2i(capoff + PCIE_RCR)]; 1954 printf(" Root Control Register: %04x\n", reg & 0xffff); 1955 onoff("SERR on Correctable Error Enable", reg, 1956 PCIE_RCR_SERR_CER); 1957 onoff("SERR on Non-Fatal Error Enable", reg, 1958 PCIE_RCR_SERR_NFER); 1959 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1960 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1961 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1962 1963 /* Root Capability Register */ 1964 printf(" Root Capability Register: 0x%04x\n", 1965 reg >> 16); 1966 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 1967 1968 /* Root Status Register */ 1969 reg = regs[o2i(capoff + PCIE_RSR)]; 1970 printf(" Root Status Register: 0x%08x\n", reg); 1971 printf(" PME Requester ID: 0x%04x\n", 1972 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1973 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1974 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1975 } 1976 1977 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1978 if (pciever < 2) 1979 return; 1980 1981 /* Device Capabilities 2 */ 1982 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1983 printf(" Device Capabilities 2: 0x%08x\n", reg); 1984 printf(" Completion Timeout Ranges Supported: "); 1985 val = reg & PCIE_DCAP2_COMPT_RANGE; 1986 switch (val) { 1987 case 0: 1988 printf("not supported\n"); 1989 break; 1990 default: 1991 for (i = 0; i <= 3; i++) { 1992 if (((val >> i) & 0x01) != 0) 1993 printf("%c", 'A' + i); 1994 } 1995 printf("\n"); 1996 } 1997 onoff("Completion Timeout Disable Supported", reg, 1998 PCIE_DCAP2_COMPT_DIS); 1999 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 2000 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 2001 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 2002 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 2003 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 2004 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 2005 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 2006 printf(" TPH Completer Supported: "); 2007 switch (__SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) { 2008 case 0: 2009 printf("Not supportted\n"); 2010 break; 2011 case 1: 2012 printf("TPH\n"); 2013 break; 2014 case 3: 2015 printf("TPH and Extended TPH\n"); 2016 break; 2017 default: 2018 printf("(reserved value)\n"); 2019 break; 2020 2021 } 2022 printf(" LN System CLS: "); 2023 switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 2024 case 0x0: 2025 printf("Not supported or not in effect\n"); 2026 break; 2027 case 0x1: 2028 printf("64byte cachelines in effect\n"); 2029 break; 2030 case 0x2: 2031 printf("128byte cachelines in effect\n"); 2032 break; 2033 case 0x3: 2034 printf("Reserved\n"); 2035 break; 2036 } 2037 printf(" OBFF Supported: "); 2038 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 2039 case 0x0: 2040 printf("Not supported\n"); 2041 break; 2042 case 0x1: 2043 printf("Message only\n"); 2044 break; 2045 case 0x2: 2046 printf("WAKE# only\n"); 2047 break; 2048 case 0x3: 2049 printf("Both\n"); 2050 break; 2051 } 2052 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 2053 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 2054 val = __SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP); 2055 printf(" Max End-End TLP Prefixes: %u\n", (val == 0) ? 4 : val); 2056 printf(" Emergency Power Reduction Supported: "); 2057 switch (__SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) { 2058 case 0x0: 2059 printf("Not supported\n"); 2060 break; 2061 case 0x1: 2062 printf("Device Specific mechanism\n"); 2063 break; 2064 case 0x2: 2065 printf("Form Factor spec or Device Specific mechanism\n"); 2066 break; 2067 case 0x3: 2068 printf("Reserved\n"); 2069 break; 2070 } 2071 onoff("Emergency Power Reduction Initialization Required", reg, 2072 PCIE_DCAP2_EMGPWRRED_INI); 2073 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 2074 2075 /* Device Control 2 */ 2076 reg = regs[o2i(capoff + PCIE_DCSR2)]; 2077 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 2078 printf(" Completion Timeout Value: "); 2079 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 2080 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 2081 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 2082 onoff("AtomicOp Rquester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 2083 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 2084 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 2085 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 2086 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 2087 onoff("Emergency Power Reduction Request", reg, 2088 PCIE_DCSR2_EMGPWRRED_REQ); 2089 printf(" OBFF: "); 2090 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 2091 case 0x0: 2092 printf("Disabled\n"); 2093 break; 2094 case 0x1: 2095 printf("Enabled with Message Signaling Variation A\n"); 2096 break; 2097 case 0x2: 2098 printf("Enabled with Message Signaling Variation B\n"); 2099 break; 2100 case 0x3: 2101 printf("Enabled using WAKE# signaling\n"); 2102 break; 2103 } 2104 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 2105 2106 if (check_link) { 2107 bool drs_supported = false; 2108 2109 /* Link Capability 2 */ 2110 reg = regs[o2i(capoff + PCIE_LCAP2)]; 2111 /* If the vector is 0, LCAP2 is not implemented */ 2112 if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) { 2113 printf(" Link Capabilities 2: 0x%08x\n", reg); 2114 printf(" Supported Link Speeds Vector:"); 2115 pci_print_pcie_linkspeedvector( 2116 __SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 2117 printf("\n"); 2118 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 2119 printf(" " 2120 "Lower SKP OS Generation Supported Speed Vector:"); 2121 pci_print_pcie_linkspeedvector( 2122 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 2123 printf("\n"); 2124 printf(" " 2125 "Lower SKP OS Reception Supported Speed Vector:"); 2126 pci_print_pcie_linkspeedvector( 2127 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 2128 printf("\n"); 2129 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 2130 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 2131 } 2132 2133 /* Link Control 2 */ 2134 reg = regs[o2i(capoff + PCIE_LCSR2)]; 2135 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 2136 printf(" Target Link Speed: "); 2137 pci_print_pcie_linkspeed(__SHIFTOUT(reg, 2138 PCIE_LCSR2_TGT_LSPEED)); 2139 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 2140 onoff("HW Autonomous Speed Disabled", reg, 2141 PCIE_LCSR2_HW_AS_DIS); 2142 printf(" Selectable De-emphasis: "); 2143 pci_print_pcie_link_deemphasis( 2144 __SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP)); 2145 printf("\n"); 2146 printf(" Transmit Margin: %u\n", 2147 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 2148 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 2149 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 2150 printf(" Compliance Present/De-emphasis: "); 2151 pci_print_pcie_link_deemphasis( 2152 __SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP)); 2153 printf("\n"); 2154 2155 /* Link Status 2 */ 2156 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 2157 printf(" Current De-emphasis Level: "); 2158 pci_print_pcie_link_deemphasis( 2159 __SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL)); 2160 printf("\n"); 2161 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 2162 onoff("Equalization Phase 1 Successful", reg, 2163 PCIE_LCSR2_EQP1_SUC); 2164 onoff("Equalization Phase 2 Successful", reg, 2165 PCIE_LCSR2_EQP2_SUC); 2166 onoff("Equalization Phase 3 Successful", reg, 2167 PCIE_LCSR2_EQP3_SUC); 2168 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 2169 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 2170 if (drs_supported) { 2171 printf(" Downstream Component Presence: "); 2172 switch (__SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 2173 case PCIE_DSCOMPN_DOWN_NOTDETERM: 2174 printf("Link Down - Presence Not" 2175 " Determined\n"); 2176 break; 2177 case PCIE_DSCOMPN_DOWN_NOTPRES: 2178 printf("Link Down - Component Not Present\n"); 2179 break; 2180 case PCIE_DSCOMPN_DOWN_PRES: 2181 printf("Link Down - Component Present\n"); 2182 break; 2183 case PCIE_DSCOMPN_UP_PRES: 2184 printf("Link Up - Component Present\n"); 2185 break; 2186 case PCIE_DSCOMPN_UP_PRES_DRS: 2187 printf("Link Up - Component Present and DRS" 2188 " received\n"); 2189 break; 2190 default: 2191 printf("reserved\n"); 2192 break; 2193 } 2194 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 2195 } 2196 } 2197 2198 /* Slot Capability 2 */ 2199 /* Slot Control 2 */ 2200 /* Slot Status 2 */ 2201 } 2202 2203 static void 2204 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 2205 { 2206 pcireg_t reg; 2207 2208 printf("\n MSI-X Capability Register\n"); 2209 2210 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2211 printf(" Message Control register: 0x%04x\n", 2212 (reg >> 16) & 0xff); 2213 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 2214 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 2215 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 2216 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 2217 printf(" Table offset register: 0x%08x\n", reg); 2218 printf(" Table offset: 0x%08x\n", 2219 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 2220 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 2221 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 2222 printf(" Pending bit array register: 0x%08x\n", reg); 2223 printf(" Pending bit array offset: 0x%08x\n", 2224 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2225 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2226 } 2227 2228 static void 2229 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2230 { 2231 pcireg_t reg; 2232 2233 printf("\n Serial ATA Capability Register\n"); 2234 2235 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2236 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2237 printf(" Revision: %u.%u\n", 2238 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2239 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2240 2241 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2242 2243 printf(" BAR Register: 0x%08x\n", reg); 2244 printf(" Register location: "); 2245 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2246 printf("in config space\n"); 2247 else { 2248 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2249 printf(" BAR offset: 0x%08x\n", 2250 (pcireg_t)__SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2251 } 2252 } 2253 2254 static void 2255 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2256 { 2257 pcireg_t reg; 2258 2259 printf("\n Advanced Features Capability Register\n"); 2260 2261 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2262 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2263 printf(" AF Structure Length: 0x%02x\n", 2264 (pcireg_t)__SHIFTOUT(reg, PCI_AF_LENGTH)); 2265 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2266 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2267 reg = regs[o2i(capoff + PCI_AFCSR)]; 2268 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2269 /* 2270 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2271 * and it's always 0 on read 2272 */ 2273 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2274 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2275 } 2276 2277 static struct { 2278 pcireg_t cap; 2279 const char *name; 2280 void (*printfunc)(const pcireg_t *, int); 2281 } pci_captab[] = { 2282 { PCI_CAP_RESERVED0, "reserved", NULL }, 2283 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2284 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2285 { PCI_CAP_VPD, "VPD", NULL }, 2286 { PCI_CAP_SLOTID, "SlotID", NULL }, 2287 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2288 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2289 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2290 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2291 { PCI_CAP_VENDSPEC, "Vendor-specific", 2292 pci_conf_print_vendspec_cap }, 2293 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2294 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2295 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2296 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2297 pci_conf_print_subsystem_cap }, 2298 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2299 { PCI_CAP_SECURE, "Secure Device", NULL }, 2300 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2301 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2302 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2303 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2304 { PCI_CAP_EA, "Enhanced Allocation", NULL } 2305 }; 2306 2307 static int 2308 pci_conf_find_cap(const pcireg_t *regs, int capoff, unsigned int capid, 2309 int *offsetp) 2310 { 2311 pcireg_t rval; 2312 int off; 2313 2314 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2315 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2316 rval = regs[o2i(off)]; 2317 if (capid == PCI_CAPLIST_CAP(rval)) { 2318 if (offsetp != NULL) 2319 *offsetp = off; 2320 return 1; 2321 } 2322 } 2323 return 0; 2324 } 2325 2326 static void 2327 pci_conf_print_caplist( 2328 #ifdef _KERNEL 2329 pci_chipset_tag_t pc, pcitag_t tag, 2330 #endif 2331 const pcireg_t *regs, int capoff) 2332 { 2333 int off; 2334 pcireg_t foundcap; 2335 pcireg_t rval; 2336 bool foundtable[__arraycount(pci_captab)]; 2337 unsigned int i; 2338 2339 /* Clear table */ 2340 for (i = 0; i < __arraycount(pci_captab); i++) 2341 foundtable[i] = false; 2342 2343 /* Print capability register's offset and the type first */ 2344 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2345 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2346 rval = regs[o2i(off)]; 2347 printf(" Capability register at 0x%02x\n", off); 2348 2349 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2350 foundcap = PCI_CAPLIST_CAP(rval); 2351 if (foundcap < __arraycount(pci_captab)) { 2352 printf("%s)\n", pci_captab[foundcap].name); 2353 /* Mark as found */ 2354 foundtable[foundcap] = true; 2355 } else 2356 printf("unknown)\n"); 2357 } 2358 2359 /* 2360 * And then, print the detail of each capability registers 2361 * in capability value's order. 2362 */ 2363 for (i = 0; i < __arraycount(pci_captab); i++) { 2364 if (foundtable[i] == false) 2365 continue; 2366 2367 /* 2368 * The type was found. Search capability list again and 2369 * print all capabilities that the capabiliy type is 2370 * the same. This is required because some capabilities 2371 * appear multiple times (e.g. HyperTransport capability). 2372 */ 2373 #if 0 2374 if (pci_conf_find_cap(regs, capoff, i, &off)) { 2375 rval = regs[o2i(off)]; 2376 if (pci_captab[i].printfunc != NULL) 2377 pci_captab[i].printfunc(regs, off); 2378 } 2379 #else 2380 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2381 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2382 rval = regs[o2i(off)]; 2383 if ((PCI_CAPLIST_CAP(rval) == i) 2384 && (pci_captab[i].printfunc != NULL)) 2385 pci_captab[i].printfunc(regs, off); 2386 } 2387 #endif 2388 } 2389 } 2390 2391 /* Extended Capability */ 2392 2393 static void 2394 pci_conf_print_aer_cap_uc(pcireg_t reg) 2395 { 2396 2397 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2398 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2399 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2400 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2401 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2402 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2403 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2404 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2405 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2406 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2407 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2408 onoff("Unsupported Request Error", reg, 2409 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2410 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2411 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2412 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2413 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2414 onoff("TLP Prefix Blocked Error", reg, 2415 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2416 onoff("Poisoned TLP Egress Blocked", reg, 2417 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2418 } 2419 2420 static void 2421 pci_conf_print_aer_cap_cor(pcireg_t reg) 2422 { 2423 2424 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2425 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2426 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2427 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2428 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2429 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2430 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2431 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2432 } 2433 2434 static void 2435 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2436 { 2437 2438 printf(" First Error Pointer: 0x%04x\n", 2439 (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2440 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2441 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2442 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2443 onoff("ECRC Check Enab", reg, PCI_AER_ECRC_CHECK_ENABLE); 2444 onoff("Multiple Header Recording Capable", reg, 2445 PCI_AER_MULT_HDR_CAPABLE); 2446 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2447 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2448 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2449 2450 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2451 if (!tlp_prefix_log) 2452 return; 2453 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2454 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2455 } 2456 2457 static void 2458 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2459 { 2460 2461 onoff("Correctable Error Reporting Enable", reg, 2462 PCI_AER_ROOTERR_COR_ENABLE); 2463 onoff("Non-Fatal Error Reporting Enable", reg, 2464 PCI_AER_ROOTERR_NF_ENABLE); 2465 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2466 } 2467 2468 static void 2469 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2470 { 2471 2472 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2473 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2474 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2475 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2476 PCI_AER_ROOTERR_MULTI_UC_ERR); 2477 onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL); 2478 onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR); 2479 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2480 printf(" Advanced Error Interrupt Message Number: 0x%02x\n", 2481 (unsigned int)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2482 } 2483 2484 static void 2485 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2486 { 2487 2488 printf(" Correctable Source ID: 0x%04x\n", 2489 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2490 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2491 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2492 } 2493 2494 static void 2495 pci_conf_print_aer_cap(const pcireg_t *regs, int capoff, int extcapoff) 2496 { 2497 pcireg_t reg; 2498 int pcie_capoff; 2499 int pcie_devtype = -1; 2500 bool tlp_prefix_log = false; 2501 2502 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2503 reg = regs[o2i(pcie_capoff)]; 2504 pcie_devtype = PCIE_XCAP_TYPE(reg); 2505 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2506 if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2507 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2508 /* End-End TLP Prefix Supported */ 2509 if (reg & PCIE_DCAP2_EETLP_PREF) { 2510 tlp_prefix_log = true; 2511 } 2512 } 2513 } 2514 2515 printf("\n Advanced Error Reporting Register\n"); 2516 2517 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2518 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2519 pci_conf_print_aer_cap_uc(reg); 2520 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2521 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2522 pci_conf_print_aer_cap_uc(reg); 2523 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2524 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2525 pci_conf_print_aer_cap_uc(reg); 2526 2527 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2528 printf(" Correctable Error Status register: 0x%08x\n", reg); 2529 pci_conf_print_aer_cap_cor(reg); 2530 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2531 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2532 pci_conf_print_aer_cap_cor(reg); 2533 2534 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2535 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2536 reg); 2537 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2538 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2539 printf(" Header Log register:\n"); 2540 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2541 extcapoff + PCI_AER_ROOTERR_CMD); 2542 2543 switch (pcie_devtype) { 2544 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2545 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2546 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2547 printf(" Root Error Command register: 0x%08x\n", reg); 2548 pci_conf_print_aer_cap_rooterr_cmd(reg); 2549 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2550 printf(" Root Error Status register: 0x%08x\n", reg); 2551 pci_conf_print_aer_cap_rooterr_status(reg); 2552 2553 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2554 printf(" Error Source Identification: 0x%04x\n", reg); 2555 pci_conf_print_aer_cap_errsrc_id(reg); 2556 break; 2557 } 2558 2559 if (tlp_prefix_log) { 2560 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2561 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2562 } 2563 } 2564 2565 static void 2566 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2567 pcireg_t parbsel, int parbsize) 2568 { 2569 pcireg_t reg; 2570 int num = 16 << parbsel; 2571 int num_per_reg = sizeof(pcireg_t) / parbsize; 2572 int i, j; 2573 2574 /* First, dump the table */ 2575 for (i = 0; i < num; i += num_per_reg) { 2576 reg = regs[o2i(off + i / num_per_reg)]; 2577 printf(" %s Arbitration Table: 0x%08x\n", name, reg); 2578 } 2579 /* And then, decode each entry */ 2580 for (i = 0; i < num; i += num_per_reg) { 2581 reg = regs[o2i(off + i / num_per_reg)]; 2582 for (j = 0; j < num_per_reg; j++) 2583 printf(" Phase[%d]: %d\n", j, reg); 2584 } 2585 } 2586 2587 static void 2588 pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2589 { 2590 pcireg_t reg, n; 2591 int parbtab, parbsize; 2592 pcireg_t parbsel; 2593 int varbtab, varbsize; 2594 pcireg_t varbsel; 2595 int i, count; 2596 2597 printf("\n Virtual Channel Register\n"); 2598 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2599 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2600 count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2601 printf(" Extended VC Count: %d\n", count); 2602 n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2603 printf(" Low Priority Extended VC Count: %u\n", n); 2604 n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2605 printf(" Reference Clock: %s\n", 2606 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 2607 parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2608 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2609 2610 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2611 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2612 onoff("Hardware fixed arbitration scheme", 2613 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2614 onoff("WRR arbitration with 32 phases", 2615 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2616 onoff("WRR arbitration with 64 phases", 2617 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2618 onoff("WRR arbitration with 128 phases", 2619 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2620 varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2621 printf(" VC Arbitration Table Offset: 0x%x\n", varbtab); 2622 2623 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2624 printf(" Port VC Control register: 0x%04x\n", reg); 2625 varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2626 printf(" VC Arbitration Select: 0x%x\n", varbsel); 2627 2628 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2629 printf(" Port VC Status register: 0x%04x\n", reg); 2630 onoff("VC Arbitration Table Status", 2631 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 2632 2633 for (i = 0; i < count + 1; i++) { 2634 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 2635 printf(" VC number %d\n", i); 2636 printf(" VC Resource Capability Register: 0x%08x\n", reg); 2637 onoff(" Non-configurable Hardware fixed arbitration scheme", 2638 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 2639 onoff(" WRR arbitration with 32 phases", 2640 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 2641 onoff(" WRR arbitration with 64 phases", 2642 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 2643 onoff(" WRR arbitration with 128 phases", 2644 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 2645 onoff(" Time-based WRR arbitration with 128 phases", 2646 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 2647 onoff(" WRR arbitration with 256 phases", 2648 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 2649 onoff(" Advanced Packet Switching", 2650 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 2651 onoff(" Reject Snoop Transaction", 2652 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 2653 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 2654 printf(" Maximum Time Slots: %d\n", n); 2655 parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S; 2656 printf(" Port Arbitration Table offset: 0x%02x\n", 2657 parbtab); 2658 2659 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 2660 printf(" VC Resource Control Register: 0x%08x\n", reg); 2661 printf(" TC/VC Map: 0x%02x\n", 2662 (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 2663 /* 2664 * The load Port Arbitration Table bit is used to update 2665 * the Port Arbitration logic and it's always 0 on read, so 2666 * we don't print it. 2667 */ 2668 parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 2669 printf(" Port Arbitration Select: 0x%x\n", parbsel); 2670 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 2671 printf(" VC ID %d\n", n); 2672 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 2673 2674 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 2675 printf(" VC Resource Status Register: 0x%08x\n", reg); 2676 onoff(" Port Arbitration Table Status", 2677 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 2678 onoff(" VC Negotiation Pending", 2679 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 2680 2681 if ((parbtab != 0) && (parbsel != 0)) 2682 pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab, 2683 "Port", parbsel, parbsize); 2684 } 2685 2686 varbsize = 8; 2687 if ((varbtab != 0) && (varbsel != 0)) 2688 pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab, 2689 " VC", varbsel, varbsize); 2690 } 2691 2692 static void 2693 pci_conf_print_pwrbdgt_base_power(uint8_t base, unsigned int scale) 2694 { 2695 if (base <= 0xef) { 2696 unsigned int sdiv = 1; 2697 for (unsigned int i = scale; i > 0; i--) 2698 sdiv *= 10; 2699 2700 printf("%u", base / sdiv); 2701 2702 if (scale != 0) { 2703 printf(".%u", base % sdiv); 2704 } 2705 printf ("W\n"); 2706 return; 2707 } 2708 2709 const char *s; 2710 2711 switch (base) { 2712 case 0xf0: 2713 s = "239W < x <= 250W"; 2714 break; 2715 case 0xf1: 2716 s = "250W < x <= 275W"; 2717 break; 2718 case 0xf2: 2719 s = "275W < x <= 300W"; 2720 break; 2721 default: 2722 s = "reserved for above 300W"; 2723 break; 2724 } 2725 printf("%s\n", s); 2726 } 2727 2728 static const char * 2729 pci_conf_print_pwrbdgt_type(uint8_t reg) 2730 { 2731 2732 switch (reg) { 2733 case 0x00: 2734 return "PME Aux"; 2735 case 0x01: 2736 return "Auxilary"; 2737 case 0x02: 2738 return "Idle"; 2739 case 0x03: 2740 return "Sustained"; 2741 case 0x04: 2742 return "Sustained (Emergency Power Reduction)"; 2743 case 0x05: 2744 return "Maximum (Emergency Power Reduction)"; 2745 case 0x07: 2746 return "Maximum"; 2747 default: 2748 return "Unknown"; 2749 } 2750 } 2751 2752 static const char * 2753 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 2754 { 2755 2756 switch (reg) { 2757 case 0x00: 2758 return "Power(12V)"; 2759 case 0x01: 2760 return "Power(3.3V)"; 2761 case 0x02: 2762 return "Power(1.5V or 1.8V)"; 2763 case 0x07: 2764 return "Thermal"; 2765 default: 2766 return "Unknown"; 2767 } 2768 } 2769 2770 static void 2771 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff) 2772 { 2773 pcireg_t reg; 2774 unsigned int scale; 2775 2776 printf("\n Power Budgeting\n"); 2777 2778 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 2779 printf(" Data Select register: 0x%08x\n", reg); 2780 2781 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 2782 printf(" Data register: 0x%08x\n", reg); 2783 scale = __SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE); 2784 printf(" Base Power: "); 2785 pci_conf_print_pwrbdgt_base_power((uint8_t)reg, scale); 2786 printf(" PM Sub State: 0x%hhx\n", 2787 (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 2788 printf(" PM State: D%u\n", 2789 (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 2790 printf(" Type: %s\n", 2791 pci_conf_print_pwrbdgt_type( 2792 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 2793 printf(" Power Rail: %s\n", 2794 pci_conf_print_pwrbdgt_pwrrail( 2795 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 2796 2797 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 2798 printf(" Power Budget Capability register: 0x%08x\n", reg); 2799 onoff("System Allocated", 2800 reg, PCI_PWRBDGT_CAP_SYSALLOC); 2801 } 2802 2803 static const char * 2804 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 2805 { 2806 2807 switch (type) { 2808 case 0x00: 2809 return "Configuration Space Element"; 2810 case 0x01: 2811 return "System Egress Port or internal sink (memory)"; 2812 case 0x02: 2813 return "Internal Root Complex Link"; 2814 default: 2815 return "Unknown"; 2816 } 2817 } 2818 2819 static void 2820 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int capoff, int extcapoff) 2821 { 2822 pcireg_t reg; 2823 unsigned char nent, linktype; 2824 int i; 2825 2826 printf("\n Root Complex Link Declaration\n"); 2827 2828 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 2829 printf(" Element Self Description Register: 0x%08x\n", reg); 2830 printf(" Element Type: %s\n", 2831 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 2832 nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 2833 printf(" Number of Link Entries: %hhu\n", nent); 2834 printf(" Component ID: %hhu\n", 2835 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 2836 printf(" Port Number: %hhu\n", 2837 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 2838 for (i = 0; i < nent; i++) { 2839 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 2840 printf(" Link Entry %d:\n", i + 1); 2841 printf(" Link Description Register: 0x%08x\n", reg); 2842 onoff(" Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID); 2843 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 2844 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 2845 "Configuration Space", "Memory-Mapped Space"); 2846 onoff(" Associated RCRB Header", reg, 2847 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 2848 printf(" Target Component ID: %hhu\n", 2849 (unsigned char)__SHIFTOUT(reg, 2850 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 2851 printf(" Target Port Number: %hhu\n", 2852 (unsigned char)__SHIFTOUT(reg, 2853 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 2854 2855 if (linktype == 0) { 2856 /* Memory-Mapped Space */ 2857 reg = regs[o2i(extcapoff 2858 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 2859 printf(" Link Address Low Register: 0x%08x\n", 2860 reg); 2861 reg = regs[o2i(extcapoff 2862 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 2863 printf(" Link Address High Register: 0x%08x\n", 2864 reg); 2865 } else { 2866 unsigned int nb; 2867 pcireg_t lo, hi; 2868 2869 /* Configuration Space */ 2870 lo = regs[o2i(extcapoff 2871 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 2872 printf(" Configuration Space Low Register: " 2873 "0x%08x\n", lo); 2874 hi = regs[o2i(extcapoff 2875 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 2876 printf(" Configuration Space High Register: " 2877 "0x%08x\n", hi); 2878 nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 2879 printf(" N: %u\n", nb); 2880 printf(" Func: %hhu\n", 2881 (unsigned char)__SHIFTOUT(lo, 2882 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 2883 printf(" Dev: %hhu\n", 2884 (unsigned char)__SHIFTOUT(lo, 2885 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 2886 printf(" Bus: %hhu\n", 2887 (unsigned char)__SHIFTOUT(lo, 2888 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 2889 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 2890 printf(" Configuration Space Base Address: " 2891 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 2892 } 2893 } 2894 } 2895 2896 /* XXX pci_conf_print_rclink_ctl_cap */ 2897 2898 static void 2899 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2900 { 2901 pcireg_t reg; 2902 2903 printf("\n Root Complex Event Collector Association\n"); 2904 2905 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 2906 printf(" Association Bitmap for Root Complex Integrated Devices:" 2907 " 0x%08x\n", reg); 2908 } 2909 2910 /* XXX pci_conf_print_mfvc_cap */ 2911 /* XXX pci_conf_print_vc2_cap */ 2912 /* XXX pci_conf_print_rcrb_cap */ 2913 /* XXX pci_conf_print_vendor_cap */ 2914 /* XXX pci_conf_print_cac_cap */ 2915 2916 static void 2917 pci_conf_print_acs_cap(const pcireg_t *regs, int capoff, int extcapoff) 2918 { 2919 pcireg_t reg, cap, ctl; 2920 unsigned int size, i; 2921 2922 printf("\n Access Control Services\n"); 2923 2924 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 2925 cap = reg & 0xffff; 2926 ctl = reg >> 16; 2927 printf(" ACS Capability register: 0x%08x\n", cap); 2928 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 2929 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 2930 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 2931 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 2932 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 2933 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 2934 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 2935 size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 2936 if (size == 0) 2937 size = 256; 2938 printf(" Egress Control Vector Size: %u\n", size); 2939 printf(" ACS Control register: 0x%08x\n", ctl); 2940 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 2941 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 2942 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 2943 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 2944 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 2945 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 2946 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 2947 2948 /* 2949 * If the P2P Egress Control Capability bit is 0, ignore the Egress 2950 * Control vector. 2951 */ 2952 if ((cap & PCI_ACS_CAP_E) == 0) 2953 return; 2954 for (i = 0; i < size; i += 32) 2955 printf(" Egress Control Vector [%u..%u]: 0x%08x\n", i + 31, 2956 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 2957 } 2958 2959 static void 2960 pci_conf_print_ari_cap(const pcireg_t *regs, int capoff, int extcapoff) 2961 { 2962 pcireg_t reg, cap, ctl; 2963 2964 printf("\n Alternative Routing-ID Interpretation Register\n"); 2965 2966 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2967 cap = reg & 0xffff; 2968 ctl = reg >> 16; 2969 printf(" Capability register: 0x%08x\n", cap); 2970 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 2971 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 2972 printf(" Next Function Number: %u\n", 2973 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 2974 printf(" Control register: 0x%08x\n", ctl); 2975 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 2976 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 2977 printf(" Function Group: %u\n", 2978 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 2979 } 2980 2981 static void 2982 pci_conf_print_ats_cap(const pcireg_t *regs, int capoff, int extcapoff) 2983 { 2984 pcireg_t reg, cap, ctl; 2985 unsigned int num; 2986 2987 printf("\n Address Translation Services\n"); 2988 2989 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2990 cap = reg & 0xffff; 2991 ctl = reg >> 16; 2992 printf(" Capability register: 0x%04x\n", cap); 2993 num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 2994 if (num == 0) 2995 num = 32; 2996 printf(" Invalidate Queue Depth: %u\n", num); 2997 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 2998 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 2999 3000 printf(" Control register: 0x%04x\n", ctl); 3001 printf(" Smallest Translation Unit: %u\n", 3002 (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU)); 3003 onoff("Enable", reg, PCI_ATS_CTL_EN); 3004 } 3005 3006 static void 3007 pci_conf_print_sernum_cap(const pcireg_t *regs, int capoff, int extcapoff) 3008 { 3009 pcireg_t lo, hi; 3010 3011 printf("\n Device Serial Number Register\n"); 3012 3013 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 3014 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 3015 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 3016 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 3017 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 3018 } 3019 3020 static void 3021 pci_conf_print_sriov_cap(const pcireg_t *regs, int capoff, int extcapoff) 3022 { 3023 char buf[sizeof("99999 MB")]; 3024 pcireg_t reg; 3025 pcireg_t total_vfs; 3026 int i; 3027 bool first; 3028 3029 printf("\n Single Root IO Virtualization Register\n"); 3030 3031 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 3032 printf(" Capabilities register: 0x%08x\n", reg); 3033 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 3034 onoff("ARI Capable Hierarchy Preserved", reg, 3035 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 3036 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 3037 printf(" VF Migration Interrupt Message Number: 0x%03x\n", 3038 (pcireg_t)__SHIFTOUT(reg, 3039 PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 3040 } 3041 3042 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 3043 printf(" Control register: 0x%04x\n", reg); 3044 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 3045 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 3046 onoff("VF Migration Interrupt Enable", reg, 3047 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 3048 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 3049 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 3050 3051 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 3052 printf(" Status register: 0x%04x\n", reg); 3053 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 3054 3055 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 3056 printf(" InitialVFs register: 0x%04x\n", reg); 3057 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 3058 printf(" TotalVFs register: 0x%04x\n", reg); 3059 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 3060 printf(" NumVFs register: 0x%04x\n", reg); 3061 3062 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 3063 printf(" Function Dependency Link register: 0x%04x\n", reg); 3064 3065 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 3066 printf(" First VF Offset register: 0x%04x\n", reg); 3067 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 3068 printf(" VF Stride register: 0x%04x\n", reg); 3069 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16; 3070 printf(" Device ID: 0x%04x\n", reg); 3071 3072 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 3073 printf(" Supported Page Sizes register: 0x%08x\n", reg); 3074 printf(" Supported Page Size:"); 3075 for (i = 0, first = true; i < 32; i++) { 3076 if (reg & __BIT(i)) { 3077 #ifdef _KERNEL 3078 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 3079 #else 3080 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 3081 HN_AUTOSCALE, 0); 3082 #endif 3083 printf("%s %s", first ? "" : ",", buf); 3084 first = false; 3085 } 3086 } 3087 printf("\n"); 3088 3089 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 3090 printf(" System Page Sizes register: 0x%08x\n", reg); 3091 printf(" Page Size: "); 3092 if (reg != 0) { 3093 #ifdef _KERNEL 3094 format_bytes(buf, sizeof(buf), 1LL << (ffs(reg) + 12)); 3095 #else 3096 humanize_number(buf, sizeof(buf), 1LL << (ffs(reg) + 12), "B", 3097 HN_AUTOSCALE, 0); 3098 #endif 3099 printf("%s", buf); 3100 } else { 3101 printf("unknown"); 3102 } 3103 printf("\n"); 3104 3105 for (i = 0; i < 6; i++) { 3106 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 3107 printf(" VF BAR%d register: 0x%08x\n", i, reg); 3108 } 3109 3110 if (total_vfs > 0) { 3111 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 3112 printf(" VF Migration State Array Offset register: 0x%08x\n", 3113 reg); 3114 printf(" VF Migration State Offset: 0x%08x\n", 3115 (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 3116 i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 3117 printf(" VF Migration State BIR: "); 3118 if (i >= 0 && i <= 5) { 3119 printf("BAR%d", i); 3120 } else { 3121 printf("unknown BAR (%d)", i); 3122 } 3123 printf("\n"); 3124 } 3125 } 3126 3127 /* XXX pci_conf_print_mriov_cap */ 3128 3129 static void 3130 pci_conf_print_multicast_cap(const pcireg_t *regs, int capoff, int extcapoff) 3131 { 3132 pcireg_t reg, cap, ctl; 3133 pcireg_t regl, regh; 3134 uint64_t addr; 3135 int n; 3136 3137 printf("\n Multicast\n"); 3138 3139 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 3140 cap = reg & 0xffff; 3141 ctl = reg >> 16; 3142 printf(" Capability Register: 0x%04x\n", cap); 3143 printf(" Max Group: %u\n", 3144 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 3145 3146 /* Endpoint Only */ 3147 n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 3148 if (n > 0) 3149 printf(" Windw Size Requested: %d\n", 1 << (n - 1)); 3150 3151 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 3152 3153 printf(" Control Register: 0x%04x\n", ctl); 3154 printf(" Num Group: %u\n", 3155 (unsigned int)__SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 3156 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 3157 3158 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 3159 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 3160 printf(" Base Address Register 0: 0x%08x\n", regl); 3161 printf(" Base Address Register 1: 0x%08x\n", regh); 3162 printf(" Index Position: %u\n", 3163 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 3164 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 3165 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 3166 3167 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 3168 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 3169 printf(" Receive Register 0: 0x%08x\n", regl); 3170 printf(" Receive Register 1: 0x%08x\n", regh); 3171 3172 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 3173 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 3174 printf(" Block All Register 0: 0x%08x\n", regl); 3175 printf(" Block All Register 1: 0x%08x\n", regh); 3176 3177 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 3178 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 3179 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 3180 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 3181 3182 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 3183 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 3184 printf(" Overlay BAR 0: 0x%08x\n", regl); 3185 printf(" Overlay BAR 1: 0x%08x\n", regh); 3186 3187 n = regl & PCI_MCAST_OVERLAYL_SIZE; 3188 printf(" Overlay Size: "); 3189 if (n >= 6) 3190 printf("%d\n", n); 3191 else 3192 printf("off\n"); 3193 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 3194 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 3195 } 3196 3197 static void 3198 pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3199 { 3200 pcireg_t reg, ctl, sta; 3201 3202 printf("\n Page Request\n"); 3203 3204 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 3205 ctl = reg & 0xffff; 3206 sta = reg >> 16; 3207 printf(" Control Register: 0x%04x\n", ctl); 3208 onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E); 3209 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 3210 3211 printf(" Status Register: 0x%04x\n", sta); 3212 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 3213 onoff("Unexpected Page Request Group Index", reg, 3214 PCI_PAGE_REQ_STA_UPRGI); 3215 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 3216 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 3217 3218 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 3219 printf(" Outstanding Page Request Capacity: %u\n", reg); 3220 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 3221 printf(" Outstanding Page Request Allocation: %u\n", reg); 3222 } 3223 3224 /* XXX pci_conf_print_amd_cap */ 3225 3226 #define MEM_PBUFSIZE sizeof("999GB") 3227 3228 static void 3229 pci_conf_print_resizbar_cap(const pcireg_t *regs, int capoff, int extcapoff) 3230 { 3231 pcireg_t cap, ctl; 3232 unsigned int bars, i, n; 3233 char pbuf[MEM_PBUFSIZE]; 3234 3235 printf("\n Resizable BAR\n"); 3236 3237 /* Get Number of Resizable BARs */ 3238 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))]; 3239 bars = __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR); 3240 printf(" Number of Resizable BARs: "); 3241 if (bars <= 6) 3242 printf("%u\n", bars); 3243 else { 3244 printf("incorrect (%u)\n", bars); 3245 return; 3246 } 3247 3248 for (n = 0; n < 6; n++) { 3249 cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))]; 3250 printf(" Capability register(%u): 0x%08x\n", n, cap); 3251 if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0) 3252 continue; /* Not Used */ 3253 printf(" Acceptable BAR sizes:"); 3254 for (i = 4; i <= 23; i++) { 3255 if ((cap & (1 << i)) != 0) { 3256 humanize_number(pbuf, MEM_PBUFSIZE, 3257 (int64_t)1024 * 1024 << (i - 4), "B", 3258 #ifdef _KERNEL 3259 1); 3260 #else 3261 HN_AUTOSCALE, HN_NOSPACE); 3262 #endif 3263 printf(" %s", pbuf); 3264 } 3265 } 3266 printf("\n"); 3267 3268 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))]; 3269 printf(" Control register(%u): 0x%08x\n", n, ctl); 3270 printf(" BAR Index: %u\n", 3271 (unsigned int)__SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX)); 3272 humanize_number(pbuf, MEM_PBUFSIZE, 3273 (int64_t)1024 * 1024 3274 << __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ), 3275 "B", 3276 #ifdef _KERNEL 3277 1); 3278 #else 3279 HN_AUTOSCALE, HN_NOSPACE); 3280 #endif 3281 printf(" BAR Size: %s\n", pbuf); 3282 } 3283 } 3284 3285 static void 3286 pci_conf_print_dpa_cap(const pcireg_t *regs, int capoff, int extcapoff) 3287 { 3288 pcireg_t reg; 3289 unsigned int substmax, i; 3290 3291 printf("\n Dynamic Power Allocation\n"); 3292 3293 reg = regs[o2i(extcapoff + PCI_DPA_CAP)]; 3294 printf(" Capability register: 0x%08x\n", reg); 3295 substmax = __SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX); 3296 printf(" Substate Max: %u\n", substmax); 3297 printf(" Transition Latency Unit: "); 3298 switch (__SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) { 3299 case 0: 3300 printf("1ms\n"); 3301 break; 3302 case 1: 3303 printf("10ms\n"); 3304 break; 3305 case 2: 3306 printf("100ms\n"); 3307 break; 3308 default: 3309 printf("reserved\n"); 3310 break; 3311 } 3312 printf(" Power Allocation Scale: "); 3313 switch (__SHIFTOUT(reg, PCI_DPA_CAP_PAS)) { 3314 case 0: 3315 printf("10.0x\n"); 3316 break; 3317 case 1: 3318 printf("1.0x\n"); 3319 break; 3320 case 2: 3321 printf("0.1x\n"); 3322 break; 3323 case 3: 3324 printf("0.01x\n"); 3325 break; 3326 } 3327 printf(" Transition Latency Value 0: %u\n", 3328 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY0)); 3329 printf(" Transition Latency Value 1: %u\n", 3330 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); 3331 3332 reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; 3333 printf(" Latency Indicatior register: 0x%08x\n", reg); 3334 3335 reg = regs[o2i(extcapoff + PCI_DPA_CS)]; 3336 printf(" Status register: 0x%04x\n", reg & 0xffff); 3337 printf(" Substate Status: 0x%02x\n", 3338 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT)); 3339 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN); 3340 printf(" Control register: 0x%04x\n", reg >> 16); 3341 printf(" Substate Control: 0x%02x\n", 3342 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL)); 3343 3344 for (i = 0; i <= substmax; i++) 3345 printf(" Substate Power Allocation register %d: 0x%02x\n", 3346 i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff)); 3347 } 3348 3349 static const char * 3350 pci_conf_print_tph_req_cap_sttabloc(unsigned char val) 3351 { 3352 3353 switch (val) { 3354 case 0x0: 3355 return "Not Present"; 3356 case 0x1: 3357 return "in the TPH Requester Capability Structure"; 3358 case 0x2: 3359 return "in the MSI-X Table"; 3360 default: 3361 return "Unknown"; 3362 } 3363 } 3364 3365 static void 3366 pci_conf_print_tph_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3367 { 3368 pcireg_t reg; 3369 int size, i, j; 3370 3371 printf("\n TPH Requester Extended Capability\n"); 3372 3373 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3374 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3375 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3376 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3377 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3378 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3379 printf(" ST Table Location: %s\n", 3380 pci_conf_print_tph_req_cap_sttabloc( 3381 (unsigned char)__SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC))); 3382 size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3383 printf(" ST Table Size: %d\n", size); 3384 for (i = 0; i < size ; i += 2) { 3385 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3386 for (j = 0; j < 2 ; j++) { 3387 uint32_t entry = reg; 3388 3389 if (j != 0) 3390 entry >>= 16; 3391 entry &= 0xffff; 3392 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3393 i + j, entry); 3394 } 3395 } 3396 } 3397 3398 static void 3399 pci_conf_print_ltr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3400 { 3401 pcireg_t reg; 3402 3403 printf("\n Latency Tolerance Reporting\n"); 3404 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)] & 0xffff; 3405 printf(" Max Snoop Latency Register: 0x%04x\n", reg); 3406 printf(" Max Snoop LatencyValue: %u\n", 3407 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL)); 3408 printf(" Max Snoop LatencyScale: %uns\n", 3409 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE))); 3410 reg = regs[o2i(extcapoff + PCI_LTR_MAXNOSNOOPLAT)] >> 16; 3411 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg); 3412 printf(" Max No-Snoop LatencyValue: %u\n", 3413 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL)); 3414 printf(" Max No-Snoop LatencyScale: %uns\n", 3415 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE))); 3416 } 3417 3418 static void 3419 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int capoff, int extcapoff) 3420 { 3421 int pcie_capoff; 3422 pcireg_t reg; 3423 int i, maxlinkwidth; 3424 3425 printf("\n Secondary PCI Express Register\n"); 3426 3427 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3428 printf(" Link Control 3 register: 0x%08x\n", reg); 3429 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3430 onoff("Link Equalization Request Interrupt Enable", 3431 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3432 printf(" Enable Lower SKP OS Generation Vector:"); 3433 pci_print_pcie_linkspeedvector( 3434 __SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3435 printf("\n"); 3436 3437 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3438 printf(" Lane Error Status register: 0x%08x\n", reg); 3439 3440 /* Get Max Link Width */ 3441 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)){ 3442 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3443 maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3444 } else { 3445 printf("error: falied to get PCIe capablity\n"); 3446 return; 3447 } 3448 for (i = 0; i < maxlinkwidth; i++) { 3449 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3450 if (i % 2 != 0) 3451 reg >>= 16; 3452 else 3453 reg &= 0xffff; 3454 printf(" Equalization Control Register (Link %d): 0x%04x\n", 3455 i, reg); 3456 printf(" Downstream Port Transmit Preset: 0x%x\n", 3457 (pcireg_t)__SHIFTOUT(reg, 3458 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3459 printf(" Downstream Port Receive Hint: 0x%x\n", 3460 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3461 printf(" Upstream Port Transmit Preset: 0x%x\n", 3462 (pcireg_t)__SHIFTOUT(reg, 3463 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3464 printf(" Upstream Port Receive Hint: 0x%x\n", 3465 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3466 } 3467 } 3468 3469 /* XXX pci_conf_print_pmux_cap */ 3470 3471 static void 3472 pci_conf_print_pasid_cap(const pcireg_t *regs, int capoff, int extcapoff) 3473 { 3474 pcireg_t reg, cap, ctl; 3475 unsigned int num; 3476 3477 printf("\n Process Address Space ID\n"); 3478 3479 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3480 cap = reg & 0xffff; 3481 ctl = reg >> 16; 3482 printf(" PASID Capability Register: 0x%04x\n", cap); 3483 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3484 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3485 num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3486 printf(" Max PASID Width: %u\n", num); 3487 3488 printf(" PASID Control Register: 0x%04x\n", ctl); 3489 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3490 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3491 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3492 } 3493 3494 static void 3495 pci_conf_print_lnr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3496 { 3497 pcireg_t reg, cap, ctl; 3498 unsigned int num; 3499 3500 printf("\n LN Requester\n"); 3501 3502 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3503 cap = reg & 0xffff; 3504 ctl = reg >> 16; 3505 printf(" LNR Capability register: 0x%04x\n", cap); 3506 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 3507 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 3508 num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 3509 printf(" LNR Registration MAX: %u\n", num); 3510 3511 printf(" LNR Control register: 0x%04x\n", ctl); 3512 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 3513 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 3514 num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 3515 printf(" LNR Registration Limit: %u\n", num); 3516 } 3517 3518 /* XXX pci_conf_print_dpc_cap */ 3519 3520 static int 3521 pci_conf_l1pm_cap_tposcale(unsigned char scale) 3522 { 3523 3524 /* Return scale in us */ 3525 switch (scale) { 3526 case 0x0: 3527 return 2; 3528 case 0x1: 3529 return 10; 3530 case 0x2: 3531 return 100; 3532 default: 3533 return -1; 3534 } 3535 } 3536 3537 static void 3538 pci_conf_print_l1pm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3539 { 3540 pcireg_t reg; 3541 int scale, val; 3542 3543 printf("\n L1 PM Substates\n"); 3544 3545 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 3546 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 3547 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 3548 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 3549 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 3550 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 3551 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 3552 printf(" Port Common Mode Restore Time: %uus\n", 3553 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 3554 scale = pci_conf_l1pm_cap_tposcale( 3555 __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 3556 val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 3557 printf(" Port T_POWER_ON: "); 3558 if (scale == -1) 3559 printf("unknown\n"); 3560 else 3561 printf("%dus\n", val * scale); 3562 3563 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 3564 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 3565 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 3566 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 3567 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 3568 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 3569 printf(" Common Mode Restore Time: %uus\n", 3570 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 3571 scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 3572 val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 3573 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 3574 3575 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 3576 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 3577 scale = pci_conf_l1pm_cap_tposcale( 3578 __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 3579 val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 3580 printf(" T_POWER_ON: "); 3581 if (scale == -1) 3582 printf("unknown\n"); 3583 else 3584 printf("%dus\n", val * scale); 3585 } 3586 3587 static void 3588 pci_conf_print_ptm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3589 { 3590 pcireg_t reg; 3591 uint32_t val; 3592 3593 printf("\n Precision Time Management\n"); 3594 3595 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 3596 printf(" PTM Capability register: 0x%08x\n", reg); 3597 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 3598 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 3599 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 3600 printf(" Local Clock Granularity: "); 3601 val = __SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 3602 switch (val) { 3603 case 0: 3604 printf("Not implemented\n"); 3605 break; 3606 case 0xffff: 3607 printf("> 254ns\n"); 3608 break; 3609 default: 3610 printf("%uns\n", val); 3611 break; 3612 } 3613 3614 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 3615 printf(" PTM Control register: 0x%08x\n", reg); 3616 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 3617 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 3618 printf(" Effective Granularity: "); 3619 val = __SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 3620 switch (val) { 3621 case 0: 3622 printf("Unknown\n"); 3623 break; 3624 case 0xffff: 3625 printf("> 254ns\n"); 3626 break; 3627 default: 3628 printf("%uns\n", val); 3629 break; 3630 } 3631 } 3632 3633 /* XXX pci_conf_print_mpcie_cap */ 3634 /* XXX pci_conf_print_frsq_cap */ 3635 /* XXX pci_conf_print_rtr_cap */ 3636 /* XXX pci_conf_print_desigvndsp_cap */ 3637 /* XXX pci_conf_print_vf_resizbar_cap */ 3638 3639 #undef MS 3640 #undef SM 3641 #undef RW 3642 3643 static struct { 3644 pcireg_t cap; 3645 const char *name; 3646 void (*printfunc)(const pcireg_t *, int, int); 3647 } pci_extcaptab[] = { 3648 { 0, "reserved", 3649 NULL }, 3650 { PCI_EXTCAP_AER, "Advanced Error Reporting", 3651 pci_conf_print_aer_cap }, 3652 { PCI_EXTCAP_VC, "Virtual Channel", 3653 pci_conf_print_vc_cap }, 3654 { PCI_EXTCAP_SERNUM, "Device Serial Number", 3655 pci_conf_print_sernum_cap }, 3656 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 3657 pci_conf_print_pwrbdgt_cap }, 3658 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 3659 pci_conf_print_rclink_dcl_cap }, 3660 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 3661 NULL }, 3662 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 3663 pci_conf_print_rcec_assoc_cap }, 3664 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 3665 NULL }, 3666 { PCI_EXTCAP_VC2, "Virtual Channel", 3667 NULL }, 3668 { PCI_EXTCAP_RCRB, "RCRB Header", 3669 NULL }, 3670 { PCI_EXTCAP_VENDOR, "Vendor Unique", 3671 NULL }, 3672 { PCI_EXTCAP_CAC, "Configuration Access Correction", 3673 NULL }, 3674 { PCI_EXTCAP_ACS, "Access Control Services", 3675 pci_conf_print_acs_cap }, 3676 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 3677 pci_conf_print_ari_cap }, 3678 { PCI_EXTCAP_ATS, "Address Translation Services", 3679 pci_conf_print_ats_cap }, 3680 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 3681 pci_conf_print_sriov_cap }, 3682 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 3683 NULL }, 3684 { PCI_EXTCAP_MCAST, "Multicast", 3685 pci_conf_print_multicast_cap }, 3686 { PCI_EXTCAP_PAGE_REQ, "Page Request", 3687 pci_conf_print_page_req_cap }, 3688 { PCI_EXTCAP_AMD, "Reserved for AMD", 3689 NULL }, 3690 { PCI_EXTCAP_RESIZBAR, "Resizable BAR", 3691 pci_conf_print_resizbar_cap }, 3692 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 3693 pci_conf_print_dpa_cap }, 3694 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 3695 pci_conf_print_tph_req_cap }, 3696 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 3697 pci_conf_print_ltr_cap }, 3698 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 3699 pci_conf_print_sec_pcie_cap }, 3700 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 3701 NULL }, 3702 { PCI_EXTCAP_PASID, "Process Address Space ID", 3703 pci_conf_print_pasid_cap }, 3704 { PCI_EXTCAP_LN_REQ, "LN Requester", 3705 pci_conf_print_lnr_cap }, 3706 { PCI_EXTCAP_DPC, "Downstream Port Containment", 3707 NULL }, 3708 { PCI_EXTCAP_L1PM, "L1 PM Substates", 3709 pci_conf_print_l1pm_cap }, 3710 { PCI_EXTCAP_PTM, "Precision Time Management", 3711 pci_conf_print_ptm_cap }, 3712 { PCI_EXTCAP_MPCIE, "M-PCIe", 3713 NULL }, 3714 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 3715 NULL }, 3716 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 3717 NULL }, 3718 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 3719 NULL }, 3720 { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", 3721 NULL }, 3722 }; 3723 3724 static int 3725 pci_conf_find_extcap(const pcireg_t *regs, int capoff, unsigned int capid, 3726 int *offsetp) 3727 { 3728 int off; 3729 pcireg_t rval; 3730 3731 for (off = PCI_EXTCAPLIST_BASE; 3732 off != 0; 3733 off = PCI_EXTCAPLIST_NEXT(rval)) { 3734 rval = regs[o2i(off)]; 3735 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 3736 if (offsetp != NULL) 3737 *offsetp = off; 3738 return 1; 3739 } 3740 } 3741 return 0; 3742 } 3743 3744 static void 3745 pci_conf_print_extcaplist( 3746 #ifdef _KERNEL 3747 pci_chipset_tag_t pc, pcitag_t tag, 3748 #endif 3749 const pcireg_t *regs, int capoff) 3750 { 3751 int off; 3752 pcireg_t foundcap; 3753 pcireg_t rval; 3754 bool foundtable[__arraycount(pci_extcaptab)]; 3755 unsigned int i; 3756 3757 /* Check Extended capability structure */ 3758 off = PCI_EXTCAPLIST_BASE; 3759 rval = regs[o2i(off)]; 3760 if (rval == 0xffffffff || rval == 0) 3761 return; 3762 3763 /* Clear table */ 3764 for (i = 0; i < __arraycount(pci_extcaptab); i++) 3765 foundtable[i] = false; 3766 3767 /* Print extended capability register's offset and the type first */ 3768 for (;;) { 3769 printf(" Extended Capability Register at 0x%02x\n", off); 3770 3771 foundcap = PCI_EXTCAPLIST_CAP(rval); 3772 printf(" type: 0x%04x (", foundcap); 3773 if (foundcap < __arraycount(pci_extcaptab)) { 3774 printf("%s)\n", pci_extcaptab[foundcap].name); 3775 /* Mark as found */ 3776 foundtable[foundcap] = true; 3777 } else 3778 printf("unknown)\n"); 3779 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 3780 3781 off = PCI_EXTCAPLIST_NEXT(rval); 3782 if (off == 0) 3783 break; 3784 else if (off <= PCI_CONF_SIZE) { 3785 printf(" next pointer: 0x%03x (incorrect)\n", off); 3786 return; 3787 } 3788 rval = regs[o2i(off)]; 3789 } 3790 3791 /* 3792 * And then, print the detail of each capability registers 3793 * in capability value's order. 3794 */ 3795 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 3796 if (foundtable[i] == false) 3797 continue; 3798 3799 /* 3800 * The type was found. Search capability list again and 3801 * print all capabilities that the capabiliy type is 3802 * the same. 3803 */ 3804 if (pci_conf_find_extcap(regs, capoff, i, &off) == 0) 3805 continue; 3806 rval = regs[o2i(off)]; 3807 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 3808 || (pci_extcaptab[i].printfunc == NULL)) 3809 continue; 3810 3811 pci_extcaptab[i].printfunc(regs, capoff, off); 3812 3813 } 3814 } 3815 3816 /* Print the Secondary Status Register. */ 3817 static void 3818 pci_conf_print_ssr(pcireg_t rval) 3819 { 3820 pcireg_t devsel; 3821 3822 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 3823 onoff("66 MHz capable", rval, __BIT(5)); 3824 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 3825 onoff("Fast back-to-back capable", rval, __BIT(7)); 3826 onoff("Data parity error detected", rval, __BIT(8)); 3827 3828 printf(" DEVSEL timing: "); 3829 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 3830 switch (devsel) { 3831 case 0: 3832 printf("fast"); 3833 break; 3834 case 1: 3835 printf("medium"); 3836 break; 3837 case 2: 3838 printf("slow"); 3839 break; 3840 default: 3841 printf("unknown/reserved"); /* XXX */ 3842 break; 3843 } 3844 printf(" (0x%x)\n", devsel); 3845 3846 onoff("Signalled target abort", rval, __BIT(11)); 3847 onoff("Received target abort", rval, __BIT(12)); 3848 onoff("Received master abort", rval, __BIT(13)); 3849 onoff("Received system error", rval, __BIT(14)); 3850 onoff("Detected parity error", rval, __BIT(15)); 3851 } 3852 3853 static void 3854 pci_conf_print_type0( 3855 #ifdef _KERNEL 3856 pci_chipset_tag_t pc, pcitag_t tag, 3857 #endif 3858 const pcireg_t *regs) 3859 { 3860 int off, width; 3861 pcireg_t rval; 3862 3863 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 3864 #ifdef _KERNEL 3865 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 3866 #else 3867 width = pci_conf_print_bar(regs, off, NULL); 3868 #endif 3869 } 3870 3871 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 3872 3873 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 3874 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 3875 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 3876 3877 /* XXX */ 3878 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 3879 3880 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3881 printf(" Capability list pointer: 0x%02x\n", 3882 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 3883 else 3884 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 3885 3886 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 3887 3888 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3889 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 3890 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 3891 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 3892 switch (PCI_INTERRUPT_PIN(rval)) { 3893 case PCI_INTERRUPT_PIN_NONE: 3894 printf("(none)"); 3895 break; 3896 case PCI_INTERRUPT_PIN_A: 3897 printf("(pin A)"); 3898 break; 3899 case PCI_INTERRUPT_PIN_B: 3900 printf("(pin B)"); 3901 break; 3902 case PCI_INTERRUPT_PIN_C: 3903 printf("(pin C)"); 3904 break; 3905 case PCI_INTERRUPT_PIN_D: 3906 printf("(pin D)"); 3907 break; 3908 default: 3909 printf("(? ? ?)"); 3910 break; 3911 } 3912 printf("\n"); 3913 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 3914 } 3915 3916 static void 3917 pci_conf_print_type1( 3918 #ifdef _KERNEL 3919 pci_chipset_tag_t pc, pcitag_t tag, 3920 #endif 3921 const pcireg_t *regs) 3922 { 3923 int off, width; 3924 pcireg_t rval; 3925 uint32_t base, limit; 3926 uint32_t base_h, limit_h; 3927 uint64_t pbase, plimit; 3928 int use_upper; 3929 3930 /* 3931 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 3932 * Bridge chip documentation, and may not be correct with 3933 * respect to various standards. (XXX) 3934 */ 3935 3936 for (off = 0x10; off < 0x18; off += width) { 3937 #ifdef _KERNEL 3938 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 3939 #else 3940 width = pci_conf_print_bar(regs, off, NULL); 3941 #endif 3942 } 3943 3944 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 3945 printf(" Primary bus number: 0x%02x\n", 3946 PCI_BRIDGE_BUS_PRIMARY(rval)); 3947 printf(" Secondary bus number: 0x%02x\n", 3948 PCI_BRIDGE_BUS_SECONDARY(rval)); 3949 printf(" Subordinate bus number: 0x%02x\n", 3950 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 3951 printf(" Secondary bus latency timer: 0x%02x\n", 3952 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 3953 3954 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 3955 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 3956 3957 /* I/O region */ 3958 printf(" I/O region:\n"); 3959 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 3960 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 3961 if (PCI_BRIDGE_IO_32BITS(rval)) 3962 use_upper = 1; 3963 else 3964 use_upper = 0; 3965 onoff("32bit I/O", rval, use_upper); 3966 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 3967 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 3968 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 3969 limit |= 0x00000fff; 3970 3971 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 3972 base_h = (rval >> 0) & 0xffff; 3973 limit_h = (rval >> 16) & 0xffff; 3974 printf(" base upper 16 bits register: 0x%04x\n", base_h); 3975 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 3976 3977 if (use_upper == 1) { 3978 base |= base_h << 16; 3979 limit |= limit_h << 16; 3980 } 3981 if (base < limit) { 3982 if (use_upper == 1) 3983 printf(" range: 0x%08x-0x%08x\n", base, limit); 3984 else 3985 printf(" range: 0x%04x-0x%04x\n", base, limit); 3986 } else 3987 printf(" range: not set\n"); 3988 3989 /* Non-prefetchable memory region */ 3990 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 3991 printf(" Memory region:\n"); 3992 printf(" base register: 0x%04x\n", 3993 (rval >> 0) & 0xffff); 3994 printf(" limit register: 0x%04x\n", 3995 (rval >> 16) & 0xffff); 3996 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 3997 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 3998 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 3999 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 4000 if (base < limit) 4001 printf(" range: 0x%08x-0x%08x\n", base, limit); 4002 else 4003 printf(" range: not set\n"); 4004 4005 /* Prefetchable memory region */ 4006 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 4007 printf(" Prefetchable memory region:\n"); 4008 printf(" base register: 0x%04x\n", 4009 (rval >> 0) & 0xffff); 4010 printf(" limit register: 0x%04x\n", 4011 (rval >> 16) & 0xffff); 4012 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 4013 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 4014 printf(" base upper 32 bits register: 0x%08x\n", 4015 base_h); 4016 printf(" limit upper 32 bits register: 0x%08x\n", 4017 limit_h); 4018 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 4019 use_upper = 1; 4020 else 4021 use_upper = 0; 4022 onoff("64bit memory address", rval, use_upper); 4023 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 4024 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 4025 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 4026 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 4027 if (use_upper == 1) { 4028 pbase |= (uint64_t)base_h << 32; 4029 plimit |= (uint64_t)limit_h << 32; 4030 } 4031 if (pbase < plimit) { 4032 if (use_upper == 1) 4033 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 4034 "\n", pbase, plimit); 4035 else 4036 printf(" range: 0x%08x-0x%08x\n", 4037 (uint32_t)pbase, (uint32_t)plimit); 4038 } else 4039 printf(" range: not set\n"); 4040 4041 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4042 printf(" Capability list pointer: 0x%02x\n", 4043 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4044 else 4045 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4046 4047 /* XXX */ 4048 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 4049 4050 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4051 printf(" Interrupt line: 0x%02x\n", 4052 (rval >> 0) & 0xff); 4053 printf(" Interrupt pin: 0x%02x ", 4054 (rval >> 8) & 0xff); 4055 switch ((rval >> 8) & 0xff) { 4056 case PCI_INTERRUPT_PIN_NONE: 4057 printf("(none)"); 4058 break; 4059 case PCI_INTERRUPT_PIN_A: 4060 printf("(pin A)"); 4061 break; 4062 case PCI_INTERRUPT_PIN_B: 4063 printf("(pin B)"); 4064 break; 4065 case PCI_INTERRUPT_PIN_C: 4066 printf("(pin C)"); 4067 break; 4068 case PCI_INTERRUPT_PIN_D: 4069 printf("(pin D)"); 4070 break; 4071 default: 4072 printf("(? ? ?)"); 4073 break; 4074 } 4075 printf("\n"); 4076 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 4077 & PCI_BRIDGE_CONTROL_MASK; 4078 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 4079 onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE); 4080 onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR); 4081 onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA); 4082 onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA); 4083 onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT); 4084 onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR); 4085 onoff("Fast back-to-back capable", rval,PCI_BRIDGE_CONTROL_SECFASTB2B); 4086 } 4087 4088 static void 4089 pci_conf_print_type2( 4090 #ifdef _KERNEL 4091 pci_chipset_tag_t pc, pcitag_t tag, 4092 #endif 4093 const pcireg_t *regs) 4094 { 4095 pcireg_t rval; 4096 4097 /* 4098 * XXX these need to be printed in more detail, need to be 4099 * XXX checked against specs/docs, etc. 4100 * 4101 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 4102 * controller chip documentation, and may not be correct with 4103 * respect to various standards. (XXX) 4104 */ 4105 4106 #ifdef _KERNEL 4107 pci_conf_print_bar(pc, tag, regs, 0x10, 4108 "CardBus socket/ExCA registers"); 4109 #else 4110 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 4111 #endif 4112 4113 /* Capability list pointer and secondary status register */ 4114 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 4115 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4116 printf(" Capability list pointer: 0x%02x\n", 4117 PCI_CAPLIST_PTR(rval)); 4118 else 4119 printf(" Reserved @ 0x14: 0x%04x\n", 4120 (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0))); 4121 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 4122 4123 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4124 printf(" PCI bus number: 0x%02x\n", 4125 (rval >> 0) & 0xff); 4126 printf(" CardBus bus number: 0x%02x\n", 4127 (rval >> 8) & 0xff); 4128 printf(" Subordinate bus number: 0x%02x\n", 4129 (rval >> 16) & 0xff); 4130 printf(" CardBus latency timer: 0x%02x\n", 4131 (rval >> 24) & 0xff); 4132 4133 /* XXX Print more prettily */ 4134 printf(" CardBus memory region 0:\n"); 4135 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 4136 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 4137 printf(" CardBus memory region 1:\n"); 4138 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 4139 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 4140 printf(" CardBus I/O region 0:\n"); 4141 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 4142 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 4143 printf(" CardBus I/O region 1:\n"); 4144 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 4145 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 4146 4147 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4148 printf(" Interrupt line: 0x%02x\n", 4149 (rval >> 0) & 0xff); 4150 printf(" Interrupt pin: 0x%02x ", 4151 (rval >> 8) & 0xff); 4152 switch ((rval >> 8) & 0xff) { 4153 case PCI_INTERRUPT_PIN_NONE: 4154 printf("(none)"); 4155 break; 4156 case PCI_INTERRUPT_PIN_A: 4157 printf("(pin A)"); 4158 break; 4159 case PCI_INTERRUPT_PIN_B: 4160 printf("(pin B)"); 4161 break; 4162 case PCI_INTERRUPT_PIN_C: 4163 printf("(pin C)"); 4164 break; 4165 case PCI_INTERRUPT_PIN_D: 4166 printf("(pin D)"); 4167 break; 4168 default: 4169 printf("(? ? ?)"); 4170 break; 4171 } 4172 printf("\n"); 4173 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 4174 printf(" Bridge control register: 0x%04x\n", rval); 4175 onoff("Parity error response", rval, __BIT(0)); 4176 onoff("SERR# enable", rval, __BIT(1)); 4177 onoff("ISA enable", rval, __BIT(2)); 4178 onoff("VGA enable", rval, __BIT(3)); 4179 onoff("Master abort mode", rval, __BIT(5)); 4180 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 4181 onoff("Functional interrupts routed by ExCA registers", rval, 4182 __BIT(7)); 4183 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 4184 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 4185 onoff("Write posting enable", rval, __BIT(10)); 4186 4187 rval = regs[o2i(0x40)]; 4188 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4189 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4190 4191 #ifdef _KERNEL 4192 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers"); 4193 #else 4194 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 4195 #endif 4196 } 4197 4198 void 4199 pci_conf_print( 4200 #ifdef _KERNEL 4201 pci_chipset_tag_t pc, pcitag_t tag, 4202 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 4203 #else 4204 int pcifd, u_int bus, u_int dev, u_int func 4205 #endif 4206 ) 4207 { 4208 pcireg_t regs[o2i(PCI_EXTCONF_SIZE)]; 4209 int off, capoff, endoff, hdrtype; 4210 const char *type_name; 4211 #ifdef _KERNEL 4212 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 4213 #else 4214 void (*type_printfn)(const pcireg_t *); 4215 #endif 4216 4217 printf("PCI configuration registers:\n"); 4218 4219 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 4220 #ifdef _KERNEL 4221 regs[o2i(off)] = pci_conf_read(pc, tag, off); 4222 #else 4223 if (pcibus_conf_read(pcifd, bus, dev, func, off, 4224 ®s[o2i(off)]) == -1) 4225 regs[o2i(off)] = 0; 4226 #endif 4227 } 4228 4229 /* common header */ 4230 printf(" Common header:\n"); 4231 pci_conf_print_regs(regs, 0, 16); 4232 4233 printf("\n"); 4234 #ifdef _KERNEL 4235 pci_conf_print_common(pc, tag, regs); 4236 #else 4237 pci_conf_print_common(regs); 4238 #endif 4239 printf("\n"); 4240 4241 /* type-dependent header */ 4242 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 4243 switch (hdrtype) { /* XXX make a table, eventually */ 4244 case 0: 4245 /* Standard device header */ 4246 type_name = "\"normal\" device"; 4247 type_printfn = &pci_conf_print_type0; 4248 capoff = PCI_CAPLISTPTR_REG; 4249 endoff = 64; 4250 break; 4251 case 1: 4252 /* PCI-PCI bridge header */ 4253 type_name = "PCI-PCI bridge"; 4254 type_printfn = &pci_conf_print_type1; 4255 capoff = PCI_CAPLISTPTR_REG; 4256 endoff = 64; 4257 break; 4258 case 2: 4259 /* PCI-CardBus bridge header */ 4260 type_name = "PCI-CardBus bridge"; 4261 type_printfn = &pci_conf_print_type2; 4262 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 4263 endoff = 72; 4264 break; 4265 default: 4266 type_name = NULL; 4267 type_printfn = 0; 4268 capoff = -1; 4269 endoff = 64; 4270 break; 4271 } 4272 printf(" Type %d ", hdrtype); 4273 if (type_name != NULL) 4274 printf("(%s) ", type_name); 4275 printf("header:\n"); 4276 pci_conf_print_regs(regs, 16, endoff); 4277 printf("\n"); 4278 if (type_printfn) { 4279 #ifdef _KERNEL 4280 (*type_printfn)(pc, tag, regs); 4281 #else 4282 (*type_printfn)(regs); 4283 #endif 4284 } else 4285 printf(" Don't know how to pretty-print type %d header.\n", 4286 hdrtype); 4287 printf("\n"); 4288 4289 /* capability list, if present */ 4290 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4291 && (capoff > 0)) { 4292 #ifdef _KERNEL 4293 pci_conf_print_caplist(pc, tag, regs, capoff); 4294 #else 4295 pci_conf_print_caplist(regs, capoff); 4296 #endif 4297 printf("\n"); 4298 } 4299 4300 /* device-dependent header */ 4301 printf(" Device-dependent header:\n"); 4302 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 4303 printf("\n"); 4304 #ifdef _KERNEL 4305 if (printfn) 4306 (*printfn)(pc, tag, regs); 4307 else 4308 printf(" Don't know how to pretty-print device-dependent header.\n"); 4309 printf("\n"); 4310 #endif /* _KERNEL */ 4311 4312 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 4313 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 4314 return; 4315 4316 #ifdef _KERNEL 4317 pci_conf_print_extcaplist(pc, tag, regs, capoff); 4318 #else 4319 pci_conf_print_extcaplist(regs, capoff); 4320 #endif 4321 printf("\n"); 4322 4323 /* Extended Configuration Space, if present */ 4324 printf(" Extended Configuration Space:\n"); 4325 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 4326 } 4327
Indexes created Wed Sep 24 05:09:52 GMT 2025