pci_subr.c revision 1.174
1 /* $NetBSD: pci_subr.c,v 1.174 2017/04/18 10:00:26 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.174 2017/04/18 10:00:26 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdarg.h> 58 #include <stdbool.h> 59 #include <stdio.h> 60 #include <stdlib.h> 61 #include <string.h> 62 #endif 63 64 #include <dev/pci/pcireg.h> 65 #ifdef _KERNEL 66 #include <dev/pci/pcivar.h> 67 #else 68 #include <dev/pci/pci_verbose.h> 69 #include <dev/pci/pcidevs.h> 70 #include <dev/pci/pcidevs_data.h> 71 #endif 72 73 static int pci_conf_find_cap(const pcireg_t *, int, unsigned int, int *); 74 75 /* 76 * Descriptions of known PCI classes and subclasses. 77 * 78 * Subclasses are described in the same way as classes, but have a 79 * NULL subclass pointer. 80 */ 81 struct pci_class { 82 const char *name; 83 u_int val; /* as wide as pci_{,sub}class_t */ 84 const struct pci_class *subclasses; 85 }; 86 87 /* 88 * Class 0x00. 89 * Before rev. 2.0. 90 */ 91 static const struct pci_class pci_subclass_prehistoric[] = { 92 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 93 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 94 { NULL, 0, NULL, }, 95 }; 96 97 /* 98 * Class 0x01. 99 * Mass storage controller 100 */ 101 102 /* ATA programming interface */ 103 static const struct pci_class pci_interface_ata[] = { 104 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 105 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 106 { NULL, 0, NULL, }, 107 }; 108 109 /* SATA programming interface */ 110 static const struct pci_class pci_interface_sata[] = { 111 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 112 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 113 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 114 { NULL, 0, NULL, }, 115 }; 116 117 /* Flash programming interface */ 118 static const struct pci_class pci_interface_nvm[] = { 119 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 120 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 121 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 122 { NULL, 0, NULL, }, 123 }; 124 125 /* Subclasses */ 126 static const struct pci_class pci_subclass_mass_storage[] = { 127 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 128 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 129 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 130 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 131 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 132 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 133 pci_interface_ata, }, 134 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 135 pci_interface_sata, }, 136 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 137 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 138 pci_interface_nvm, }, 139 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 140 { NULL, 0, NULL, }, 141 }; 142 143 /* 144 * Class 0x02. 145 * Network controller. 146 */ 147 static const struct pci_class pci_subclass_network[] = { 148 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 149 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 150 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 151 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 152 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 153 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 154 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 155 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 156 { NULL, 0, NULL, }, 157 }; 158 159 /* 160 * Class 0x03. 161 * Display controller. 162 */ 163 164 /* VGA programming interface */ 165 static const struct pci_class pci_interface_vga[] = { 166 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 167 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 168 { NULL, 0, NULL, }, 169 }; 170 /* Subclasses */ 171 static const struct pci_class pci_subclass_display[] = { 172 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 173 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 174 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 175 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 176 { NULL, 0, NULL, }, 177 }; 178 179 /* 180 * Class 0x04. 181 * Multimedia device. 182 */ 183 static const struct pci_class pci_subclass_multimedia[] = { 184 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 185 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 186 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 187 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 188 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 189 { NULL, 0, NULL, }, 190 }; 191 192 /* 193 * Class 0x05. 194 * Memory controller. 195 */ 196 static const struct pci_class pci_subclass_memory[] = { 197 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 198 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 199 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 200 { NULL, 0, NULL, }, 201 }; 202 203 /* 204 * Class 0x06. 205 * Bridge device. 206 */ 207 208 /* PCI bridge programming interface */ 209 static const struct pci_class pci_interface_pcibridge[] = { 210 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 211 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 212 { NULL, 0, NULL, }, 213 }; 214 215 /* Semi-transparent PCI-to-PCI bridge programming interface */ 216 static const struct pci_class pci_interface_stpci[] = { 217 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 218 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 219 { NULL, 0, NULL, }, 220 }; 221 222 /* Advanced Switching programming interface */ 223 static const struct pci_class pci_interface_advsw[] = { 224 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 225 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 226 { NULL, 0, NULL, }, 227 }; 228 229 /* Subclasses */ 230 static const struct pci_class pci_subclass_bridge[] = { 231 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 232 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 233 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 234 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 235 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 236 pci_interface_pcibridge, }, 237 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 238 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 239 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 240 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 241 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 242 pci_interface_stpci, }, 243 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 244 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 245 pci_interface_advsw, }, 246 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 247 { NULL, 0, NULL, }, 248 }; 249 250 /* 251 * Class 0x07. 252 * Simple communications controller. 253 */ 254 255 /* Serial controller programming interface */ 256 static const struct pci_class pci_interface_serial[] = { 257 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 258 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 259 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 260 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 261 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 262 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 263 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 264 { NULL, 0, NULL, }, 265 }; 266 267 /* Parallel controller programming interface */ 268 static const struct pci_class pci_interface_parallel[] = { 269 { "", PCI_INTERFACE_PARALLEL, NULL,}, 270 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 271 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 272 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 273 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 274 { NULL, 0, NULL,}, 275 }; 276 277 /* Modem programming interface */ 278 static const struct pci_class pci_interface_modem[] = { 279 { "", PCI_INTERFACE_MODEM, NULL,}, 280 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 281 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 282 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 283 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 284 { NULL, 0, NULL,}, 285 }; 286 287 /* Subclasses */ 288 static const struct pci_class pci_subclass_communications[] = { 289 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 290 pci_interface_serial, }, 291 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 292 pci_interface_parallel, }, 293 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 294 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 295 pci_interface_modem, }, 296 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 297 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 298 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 299 { NULL, 0, NULL,}, 300 }; 301 302 /* 303 * Class 0x08. 304 * Base system peripheral. 305 */ 306 307 /* PIC programming interface */ 308 static const struct pci_class pci_interface_pic[] = { 309 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 310 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 311 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 312 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 313 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 314 { NULL, 0, NULL, }, 315 }; 316 317 /* DMA programming interface */ 318 static const struct pci_class pci_interface_dma[] = { 319 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 320 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 321 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 322 { NULL, 0, NULL, }, 323 }; 324 325 /* Timer programming interface */ 326 static const struct pci_class pci_interface_tmr[] = { 327 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 328 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 329 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 330 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 331 { NULL, 0, NULL, }, 332 }; 333 334 /* RTC programming interface */ 335 static const struct pci_class pci_interface_rtc[] = { 336 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 337 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 338 { NULL, 0, NULL, }, 339 }; 340 341 /* Subclasses */ 342 static const struct pci_class pci_subclass_system[] = { 343 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 344 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 345 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 346 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 347 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 348 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 349 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 350 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 351 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 352 { NULL, 0, NULL, }, 353 }; 354 355 /* 356 * Class 0x09. 357 * Input device. 358 */ 359 360 /* Gameport programming interface */ 361 static const struct pci_class pci_interface_game[] = { 362 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 363 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 364 { NULL, 0, NULL, }, 365 }; 366 367 /* Subclasses */ 368 static const struct pci_class pci_subclass_input[] = { 369 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 370 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 371 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 372 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 373 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 374 pci_interface_game, }, 375 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 376 { NULL, 0, NULL, }, 377 }; 378 379 /* 380 * Class 0x0a. 381 * Docking station. 382 */ 383 static const struct pci_class pci_subclass_dock[] = { 384 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 385 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 386 { NULL, 0, NULL, }, 387 }; 388 389 /* 390 * Class 0x0b. 391 * Processor. 392 */ 393 static const struct pci_class pci_subclass_processor[] = { 394 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 395 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 396 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 397 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 398 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 399 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 400 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 401 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 402 { NULL, 0, NULL, }, 403 }; 404 405 /* 406 * Class 0x0c. 407 * Serial bus controller. 408 */ 409 410 /* IEEE1394 programming interface */ 411 static const struct pci_class pci_interface_ieee1394[] = { 412 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 413 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 414 { NULL, 0, NULL,}, 415 }; 416 417 /* USB programming interface */ 418 static const struct pci_class pci_interface_usb[] = { 419 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 420 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 421 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 422 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 423 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 424 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 425 { NULL, 0, NULL, }, 426 }; 427 428 /* IPMI programming interface */ 429 static const struct pci_class pci_interface_ipmi[] = { 430 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 431 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 432 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 433 { NULL, 0, NULL,}, 434 }; 435 436 /* Subclasses */ 437 static const struct pci_class pci_subclass_serialbus[] = { 438 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 439 pci_interface_ieee1394, }, 440 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 441 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 442 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 443 pci_interface_usb, }, 444 /* XXX Fiber Channel/_FIBRECHANNEL */ 445 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 446 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 447 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 448 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 449 pci_interface_ipmi, }, 450 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 451 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 452 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 453 { NULL, 0, NULL, }, 454 }; 455 456 /* 457 * Class 0x0d. 458 * Wireless Controller. 459 */ 460 static const struct pci_class pci_subclass_wireless[] = { 461 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 462 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 463 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 464 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 465 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 466 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 467 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 468 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 469 { NULL, 0, NULL, }, 470 }; 471 472 /* 473 * Class 0x0e. 474 * Intelligent IO controller. 475 */ 476 477 /* Intelligent IO programming interface */ 478 static const struct pci_class pci_interface_i2o[] = { 479 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 480 { NULL, 0, NULL,}, 481 }; 482 483 /* Subclasses */ 484 static const struct pci_class pci_subclass_i2o[] = { 485 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 486 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 487 { NULL, 0, NULL, }, 488 }; 489 490 /* 491 * Class 0x0f. 492 * Satellite communication controller. 493 */ 494 static const struct pci_class pci_subclass_satcom[] = { 495 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 496 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 497 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 498 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 499 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 500 { NULL, 0, NULL, }, 501 }; 502 503 /* 504 * Class 0x10. 505 * Encryption/Decryption controller. 506 */ 507 static const struct pci_class pci_subclass_crypto[] = { 508 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 509 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 510 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 511 { NULL, 0, NULL, }, 512 }; 513 514 /* 515 * Class 0x11. 516 * Data aquuisition and signal processing controller. 517 */ 518 static const struct pci_class pci_subclass_dasp[] = { 519 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 520 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 521 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 522 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 523 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 524 { NULL, 0, NULL, }, 525 }; 526 527 /* List of classes */ 528 static const struct pci_class pci_classes[] = { 529 { "prehistoric", PCI_CLASS_PREHISTORIC, 530 pci_subclass_prehistoric, }, 531 { "mass storage", PCI_CLASS_MASS_STORAGE, 532 pci_subclass_mass_storage, }, 533 { "network", PCI_CLASS_NETWORK, 534 pci_subclass_network, }, 535 { "display", PCI_CLASS_DISPLAY, 536 pci_subclass_display, }, 537 { "multimedia", PCI_CLASS_MULTIMEDIA, 538 pci_subclass_multimedia, }, 539 { "memory", PCI_CLASS_MEMORY, 540 pci_subclass_memory, }, 541 { "bridge", PCI_CLASS_BRIDGE, 542 pci_subclass_bridge, }, 543 { "communications", PCI_CLASS_COMMUNICATIONS, 544 pci_subclass_communications, }, 545 { "system", PCI_CLASS_SYSTEM, 546 pci_subclass_system, }, 547 { "input", PCI_CLASS_INPUT, 548 pci_subclass_input, }, 549 { "dock", PCI_CLASS_DOCK, 550 pci_subclass_dock, }, 551 { "processor", PCI_CLASS_PROCESSOR, 552 pci_subclass_processor, }, 553 { "serial bus", PCI_CLASS_SERIALBUS, 554 pci_subclass_serialbus, }, 555 { "wireless", PCI_CLASS_WIRELESS, 556 pci_subclass_wireless, }, 557 { "I2O", PCI_CLASS_I2O, 558 pci_subclass_i2o, }, 559 { "satellite comm", PCI_CLASS_SATCOM, 560 pci_subclass_satcom, }, 561 { "crypto", PCI_CLASS_CRYPTO, 562 pci_subclass_crypto, }, 563 { "DASP", PCI_CLASS_DASP, 564 pci_subclass_dasp, }, 565 { "processing accelerators", PCI_CLASS_ACCEL, 566 NULL, }, 567 { "non-essential instrumentation", PCI_CLASS_INSTRUMENT, 568 NULL, }, 569 { "undefined", PCI_CLASS_UNDEFINED, 570 NULL, }, 571 { NULL, 0, 572 NULL, }, 573 }; 574 575 DEV_VERBOSE_DEFINE(pci); 576 577 /* 578 * Append a formatted string to dest without writing more than len 579 * characters (including the trailing NUL character). dest and len 580 * are updated for use in subsequent calls to snappendf(). 581 * 582 * Returns 0 on success, a negative value if vnsprintf() fails, or 583 * a positive value if the dest buffer would have overflowed. 584 */ 585 586 static int __printflike(3,4) 587 snappendf(char **dest, size_t *len, const char * restrict fmt, ...) 588 { 589 va_list ap; 590 int count; 591 592 va_start(ap, fmt); 593 count = vsnprintf(*dest, *len, fmt, ap); 594 va_end(ap); 595 596 /* Let vsnprintf() errors bubble up to caller */ 597 if (count < 0 || *len == 0) 598 return count; 599 600 /* Handle overflow */ 601 if ((size_t)count >= *len) { 602 *dest += *len - 1; 603 *len = 1; 604 return 1; 605 } 606 607 /* Update dest & len to point at trailing NUL */ 608 *dest += count; 609 *len -= count; 610 611 return 0; 612 } 613 614 void 615 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 616 size_t l) 617 { 618 pci_class_t class; 619 pci_subclass_t subclass; 620 pci_interface_t interface; 621 pci_revision_t revision; 622 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 623 const struct pci_class *classp, *subclassp, *interfacep; 624 625 class = PCI_CLASS(class_reg); 626 subclass = PCI_SUBCLASS(class_reg); 627 interface = PCI_INTERFACE(class_reg); 628 revision = PCI_REVISION(class_reg); 629 630 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 631 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 632 PCI_PRODUCT(id_reg)); 633 634 classp = pci_classes; 635 while (classp->name != NULL) { 636 if (class == classp->val) 637 break; 638 classp++; 639 } 640 641 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 642 while (subclassp && subclassp->name != NULL) { 643 if (subclass == subclassp->val) 644 break; 645 subclassp++; 646 } 647 648 interfacep = (subclassp && subclassp->name != NULL) ? 649 subclassp->subclasses : NULL; 650 while (interfacep && interfacep->name != NULL) { 651 if (interface == interfacep->val) 652 break; 653 interfacep++; 654 } 655 656 (void)snappendf(&cp, &l, "%s %s", vendor, product); 657 if (showclass) { 658 (void)snappendf(&cp, &l, " ("); 659 if (classp->name == NULL) 660 (void)snappendf(&cp, &l, 661 "class 0x%02x, subclass 0x%02x", 662 class, subclass); 663 else { 664 if (subclassp == NULL || subclassp->name == NULL) 665 (void)snappendf(&cp, &l, 666 "%s, subclass 0x%02x", 667 classp->name, subclass); 668 else 669 (void)snappendf(&cp, &l, "%s %s", 670 subclassp->name, classp->name); 671 } 672 if ((interfacep == NULL) || (interfacep->name == NULL)) { 673 if (interface != 0) 674 (void)snappendf(&cp, &l, ", interface 0x%02x", 675 interface); 676 } else if (strncmp(interfacep->name, "", 1) != 0) 677 (void)snappendf(&cp, &l, ", %s", interfacep->name); 678 if (revision != 0) 679 (void)snappendf(&cp, &l, ", revision 0x%02x", revision); 680 (void)snappendf(&cp, &l, ")"); 681 } 682 } 683 684 #ifdef _KERNEL 685 void 686 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 687 const char *known, int addrev) 688 { 689 char devinfo[256]; 690 691 if (known) { 692 aprint_normal(": %s", known); 693 if (addrev) 694 aprint_normal(" (rev. 0x%02x)", 695 PCI_REVISION(pa->pa_class)); 696 aprint_normal("\n"); 697 } else { 698 pci_devinfo(pa->pa_id, pa->pa_class, 0, 699 devinfo, sizeof(devinfo)); 700 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 701 PCI_REVISION(pa->pa_class)); 702 } 703 if (naive) 704 aprint_naive(": %s\n", naive); 705 else 706 aprint_naive("\n"); 707 } 708 #endif 709 710 /* 711 * Print out most of the PCI configuration registers. Typically used 712 * in a device attach routine like this: 713 * 714 * #ifdef MYDEV_DEBUG 715 * printf("%s: ", device_xname(sc->sc_dev)); 716 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 717 * #endif 718 */ 719 720 #define i2o(i) ((i) * 4) 721 #define o2i(o) ((o) / 4) 722 #define onoff2(str, rval, bit, onstr, offstr) \ 723 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 724 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 725 726 static void 727 pci_conf_print_common( 728 #ifdef _KERNEL 729 pci_chipset_tag_t pc, pcitag_t tag, 730 #endif 731 const pcireg_t *regs) 732 { 733 pci_class_t class; 734 pci_subclass_t subclass; 735 pci_interface_t interface; 736 pci_revision_t revision; 737 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 738 const struct pci_class *classp, *subclassp, *interfacep; 739 const char *name; 740 pcireg_t rval; 741 unsigned int num; 742 743 rval = regs[o2i(PCI_CLASS_REG)]; 744 class = PCI_CLASS(rval); 745 subclass = PCI_SUBCLASS(rval); 746 interface = PCI_INTERFACE(rval); 747 revision = PCI_REVISION(rval); 748 749 rval = regs[o2i(PCI_ID_REG)]; 750 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 751 if (name) 752 printf(" Vendor Name: %s (0x%04x)\n", name, 753 PCI_VENDOR(rval)); 754 else 755 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 756 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 757 PCI_PRODUCT(rval)); 758 if (name) 759 printf(" Device Name: %s (0x%04x)\n", name, 760 PCI_PRODUCT(rval)); 761 else 762 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 763 764 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 765 766 printf(" Command register: 0x%04x\n", rval & 0xffff); 767 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 768 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 769 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 770 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 771 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 772 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 773 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 774 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 775 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 776 onoff("Fast back-to-back transactions", rval, 777 PCI_COMMAND_BACKTOBACK_ENABLE); 778 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 779 780 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 781 onoff("Immediate Readiness", rval, PCI_STATUS_IMMD_READNESS); 782 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 783 "inactive"); 784 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 785 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 786 onoff("User Definable Features (UDF) support", rval, 787 PCI_STATUS_UDF_SUPPORT); 788 onoff("Fast back-to-back capable", rval, 789 PCI_STATUS_BACKTOBACK_SUPPORT); 790 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 791 792 printf(" DEVSEL timing: "); 793 switch (rval & PCI_STATUS_DEVSEL_MASK) { 794 case PCI_STATUS_DEVSEL_FAST: 795 printf("fast"); 796 break; 797 case PCI_STATUS_DEVSEL_MEDIUM: 798 printf("medium"); 799 break; 800 case PCI_STATUS_DEVSEL_SLOW: 801 printf("slow"); 802 break; 803 default: 804 printf("unknown/reserved"); /* XXX */ 805 break; 806 } 807 printf(" (0x%x)\n", __SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK)); 808 809 onoff("Slave signaled Target Abort", rval, 810 PCI_STATUS_TARGET_TARGET_ABORT); 811 onoff("Master received Target Abort", rval, 812 PCI_STATUS_MASTER_TARGET_ABORT); 813 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 814 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 815 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 816 817 rval = regs[o2i(PCI_CLASS_REG)]; 818 for (classp = pci_classes; classp->name != NULL; classp++) { 819 if (class == classp->val) 820 break; 821 } 822 823 /* 824 * ECN: Change Root Complex Event Collector Class Code 825 * Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type 826 * in PCIe extend capability to know whether it's RCEC or IOMMU. 827 */ 828 if ((class == PCI_CLASS_SYSTEM) 829 && (subclass == PCI_SUBCLASS_SYSTEM_IOMMU)) { 830 int pcie_capoff; 831 pcireg_t reg; 832 833 if (pci_conf_find_cap(regs, PCI_CAPLISTPTR_REG, 834 PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 835 reg = regs[o2i(pcie_capoff + PCIE_XCAP)]; 836 if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_ROOT_EVNTC) 837 subclass = PCI_SUBCLASS_SYSTEM_RCEC; 838 } 839 } 840 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 841 while (subclassp && subclassp->name != NULL) { 842 if (subclass == subclassp->val) 843 break; 844 subclassp++; 845 } 846 847 interfacep = (subclassp && subclassp->name != NULL) ? 848 subclassp->subclasses : NULL; 849 while (interfacep && interfacep->name != NULL) { 850 if (interface == interfacep->val) 851 break; 852 interfacep++; 853 } 854 855 if (classp->name != NULL) 856 printf(" Class Name: %s (0x%02x)\n", classp->name, class); 857 else 858 printf(" Class ID: 0x%02x\n", class); 859 if (subclassp != NULL && subclassp->name != NULL) 860 printf(" Subclass Name: %s (0x%02x)\n", 861 subclassp->name, PCI_SUBCLASS(rval)); 862 else 863 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 864 if ((interfacep != NULL) && (interfacep->name != NULL) 865 && (strncmp(interfacep->name, "", 1) != 0)) 866 printf(" Interface Name: %s (0x%02x)\n", 867 interfacep->name, interface); 868 else 869 printf(" Interface: 0x%02x\n", interface); 870 printf(" Revision ID: 0x%02x\n", revision); 871 872 rval = regs[o2i(PCI_BHLC_REG)]; 873 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 874 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 875 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 876 PCI_HDRTYPE(rval)); 877 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 878 num = PCI_CACHELINE(rval); 879 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 880 } 881 882 static int 883 pci_conf_print_bar( 884 #ifdef _KERNEL 885 pci_chipset_tag_t pc, pcitag_t tag, 886 #endif 887 const pcireg_t *regs, int reg, const char *name) 888 { 889 int width; 890 pcireg_t rval, rval64h; 891 bool ioen, memen; 892 #ifdef _KERNEL 893 pcireg_t mask, mask64h = 0; 894 #endif 895 896 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 897 ioen = rval & PCI_COMMAND_IO_ENABLE; 898 memen = rval & PCI_COMMAND_MEM_ENABLE; 899 900 width = 4; 901 /* 902 * Section 6.2.5.1, `Address Maps', tells us that: 903 * 904 * 1) The builtin software should have already mapped the 905 * device in a reasonable way. 906 * 907 * 2) A device which wants 2^n bytes of memory will hardwire 908 * the bottom n bits of the address to 0. As recommended, 909 * we write all 1s and see what we get back. 910 */ 911 912 rval = regs[o2i(reg)]; 913 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 914 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 915 rval64h = regs[o2i(reg + 4)]; 916 width = 8; 917 } else 918 rval64h = 0; 919 920 #ifdef _KERNEL 921 if (rval != 0 && memen) { 922 int s; 923 924 /* 925 * The following sequence seems to make some devices 926 * (e.g. host bus bridges, which don't normally 927 * have their space mapped) very unhappy, to 928 * the point of crashing the system. 929 * 930 * Therefore, if the mapping register is zero to 931 * start out with, don't bother trying. 932 */ 933 s = splhigh(); 934 pci_conf_write(pc, tag, reg, 0xffffffff); 935 mask = pci_conf_read(pc, tag, reg); 936 pci_conf_write(pc, tag, reg, rval); 937 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 938 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 939 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 940 mask64h = pci_conf_read(pc, tag, reg + 4); 941 pci_conf_write(pc, tag, reg + 4, rval64h); 942 } 943 splx(s); 944 } else 945 mask = mask64h = 0; 946 #endif /* _KERNEL */ 947 948 printf(" Base address register at 0x%02x", reg); 949 if (name) 950 printf(" (%s)", name); 951 printf("\n "); 952 if (rval == 0) { 953 printf("not implemented\n"); 954 return width; 955 } 956 printf("type: "); 957 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 958 const char *type, *prefetch; 959 960 switch (PCI_MAPREG_MEM_TYPE(rval)) { 961 case PCI_MAPREG_MEM_TYPE_32BIT: 962 type = "32-bit"; 963 break; 964 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 965 type = "32-bit-1M"; 966 break; 967 case PCI_MAPREG_MEM_TYPE_64BIT: 968 type = "64-bit"; 969 break; 970 default: 971 type = "unknown (XXX)"; 972 break; 973 } 974 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 975 prefetch = ""; 976 else 977 prefetch = "non"; 978 printf("%s %sprefetchable memory\n", type, prefetch); 979 switch (PCI_MAPREG_MEM_TYPE(rval)) { 980 case PCI_MAPREG_MEM_TYPE_64BIT: 981 printf(" base: 0x%016llx", 982 PCI_MAPREG_MEM64_ADDR( 983 ((((long long) rval64h) << 32) | rval))); 984 if (!memen) 985 printf(", disabled"); 986 printf("\n"); 987 #ifdef _KERNEL 988 printf(" size: 0x%016llx\n", 989 PCI_MAPREG_MEM64_SIZE( 990 ((((long long) mask64h) << 32) | mask))); 991 #endif 992 break; 993 case PCI_MAPREG_MEM_TYPE_32BIT: 994 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 995 default: 996 printf(" base: 0x%08x", 997 PCI_MAPREG_MEM_ADDR(rval)); 998 if (!memen) 999 printf(", disabled"); 1000 printf("\n"); 1001 #ifdef _KERNEL 1002 printf(" size: 0x%08x\n", 1003 PCI_MAPREG_MEM_SIZE(mask)); 1004 #endif 1005 break; 1006 } 1007 } else { 1008 #ifdef _KERNEL 1009 if (ioen) 1010 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 1011 #endif 1012 printf("I/O\n"); 1013 printf(" base: 0x%08x", PCI_MAPREG_IO_ADDR(rval)); 1014 if (!ioen) 1015 printf(", disabled"); 1016 printf("\n"); 1017 #ifdef _KERNEL 1018 printf(" size: 0x%08x\n", PCI_MAPREG_IO_SIZE(mask)); 1019 #endif 1020 } 1021 1022 return width; 1023 } 1024 1025 static void 1026 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 1027 { 1028 int off, needaddr, neednl; 1029 1030 needaddr = 1; 1031 neednl = 0; 1032 for (off = first; off < pastlast; off += 4) { 1033 if ((off % 16) == 0 || needaddr) { 1034 printf(" 0x%02x:", off); 1035 needaddr = 0; 1036 } 1037 printf(" 0x%08x", regs[o2i(off)]); 1038 neednl = 1; 1039 if ((off % 16) == 12) { 1040 printf("\n"); 1041 neednl = 0; 1042 } 1043 } 1044 if (neednl) 1045 printf("\n"); 1046 } 1047 1048 static const char * 1049 pci_conf_print_agp_calcycle(uint8_t cal) 1050 { 1051 1052 switch (cal) { 1053 case 0x0: 1054 return "4ms"; 1055 case 0x1: 1056 return "16ms"; 1057 case 0x2: 1058 return "64ms"; 1059 case 0x3: 1060 return "256ms"; 1061 case 0x7: 1062 return "Calibration Cycle Not Needed"; 1063 default: 1064 return "(reserved)"; 1065 } 1066 } 1067 1068 static void 1069 pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3) 1070 { 1071 if (isagp3) { 1072 /* AGP 3.0 */ 1073 if (reg & AGP_MODE_V3_RATE_4x) 1074 printf("x4"); 1075 if (reg & AGP_MODE_V3_RATE_8x) 1076 printf("x8"); 1077 } else { 1078 /* AGP 2.0 */ 1079 if (reg & AGP_MODE_V2_RATE_1x) 1080 printf("x1"); 1081 if (reg & AGP_MODE_V2_RATE_2x) 1082 printf("x2"); 1083 if (reg & AGP_MODE_V2_RATE_4x) 1084 printf("x4"); 1085 } 1086 printf("\n"); 1087 } 1088 1089 static void 1090 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1091 { 1092 pcireg_t rval; 1093 bool isagp3; 1094 1095 printf("\n AGP Capabilities Register\n"); 1096 1097 rval = regs[o2i(capoff)]; 1098 printf(" Revision: %d.%d\n", 1099 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1100 1101 rval = regs[o2i(capoff + PCI_AGP_STATUS)]; 1102 printf(" Status register: 0x%04x\n", rval); 1103 printf(" RQ: %d\n", 1104 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1105 printf(" ARQSZ: %d\n", 1106 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1107 printf(" CAL cycle: %s\n", 1108 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1109 onoff("SBA", rval, AGP_MODE_SBA); 1110 onoff("htrans#", rval, AGP_MODE_HTRANS); 1111 onoff("Over 4G", rval, AGP_MODE_4G); 1112 onoff("Fast Write", rval, AGP_MODE_FW); 1113 onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3); 1114 isagp3 = rval & AGP_MODE_MODE_3; 1115 printf(" Data Rate Support: "); 1116 pci_conf_print_agp_datarate(rval, isagp3); 1117 1118 rval = regs[o2i(capoff + PCI_AGP_COMMAND)]; 1119 printf(" Command register: 0x%08x\n", rval); 1120 printf(" PRQ: %d\n", 1121 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1122 printf(" PARQSZ: %d\n", 1123 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1124 printf(" PCAL cycle: %s\n", 1125 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1126 onoff("SBA", rval, AGP_MODE_SBA); 1127 onoff("AGP", rval, AGP_MODE_AGP); 1128 onoff("Over 4G", rval, AGP_MODE_4G); 1129 onoff("Fast Write", rval, AGP_MODE_FW); 1130 if (isagp3) { 1131 printf(" Data Rate Enable: "); 1132 /* 1133 * The Data Rate Enable bits are used only on 3.0 and the 1134 * Command register has no AGP_MODE_MODE_3 bit, so pass the 1135 * flag to print correctly. 1136 */ 1137 pci_conf_print_agp_datarate(rval, isagp3); 1138 } 1139 } 1140 1141 static const char * 1142 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1143 { 1144 1145 switch ((caps >> 6) & 7) { 1146 case 0: return "self-powered"; 1147 case 1: return "55 mA"; 1148 case 2: return "100 mA"; 1149 case 3: return "160 mA"; 1150 case 4: return "220 mA"; 1151 case 5: return "270 mA"; 1152 case 6: return "320 mA"; 1153 case 7: 1154 default: return "375 mA"; 1155 } 1156 } 1157 1158 static const char * 1159 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1160 { 1161 static const char unk[] = "unknown"; 1162 static const char *pmrev[8] = { 1163 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1164 }; 1165 if (val > 7) 1166 return unk; 1167 return pmrev[val]; 1168 } 1169 1170 static void 1171 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1172 { 1173 uint16_t caps, pmcsr; 1174 pcireg_t reg; 1175 1176 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1177 reg = regs[o2i(capoff + PCI_PMCSR)]; 1178 pmcsr = reg & 0xffff; 1179 1180 printf("\n PCI Power Management Capabilities Register\n"); 1181 1182 printf(" Capabilities register: 0x%04x\n", caps); 1183 printf(" Version: %s\n", 1184 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1185 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1186 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1187 printf(" 3.3V auxiliary current: %s\n", 1188 pci_conf_print_pcipm_cap_aux(caps)); 1189 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1190 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1191 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1192 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1193 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1194 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1195 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1196 1197 printf(" Control/status register: 0x%04x\n", pmcsr); 1198 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1199 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1200 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1201 printf(" PME# assertion: %sabled\n", 1202 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1203 printf(" Data Select: %d\n", 1204 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK)); 1205 printf(" Data Scale: %d\n", 1206 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK)); 1207 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1208 printf(" Bridge Support Extensions register: 0x%02x\n", 1209 (reg >> 16) & 0xff); 1210 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1211 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1212 printf(" Data register: 0x%02x\n", __SHIFTOUT(reg, PCI_PMCSR_DATA)); 1213 1214 } 1215 1216 /* XXX pci_conf_print_vpd_cap */ 1217 /* XXX pci_conf_print_slotid_cap */ 1218 1219 static void 1220 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1221 { 1222 uint32_t ctl, mmc, mme; 1223 1224 regs += o2i(capoff); 1225 ctl = *regs++; 1226 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1227 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1228 1229 printf("\n PCI Message Signaled Interrupt\n"); 1230 1231 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1232 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1233 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1234 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1235 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1236 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1237 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1238 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1239 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP); 1240 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN); 1241 printf(" Message Address %sregister: 0x%08x\n", 1242 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1243 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1244 printf(" Message Address %sregister: 0x%08x\n", 1245 "(upper) ", *regs++); 1246 } 1247 printf(" Message Data register: 0x%04x\n", *regs & 0xffff); 1248 regs++; 1249 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1250 printf(" Vector Mask register: 0x%08x\n", *regs++); 1251 printf(" Vector Pending register: 0x%08x\n", *regs++); 1252 } 1253 } 1254 1255 /* XXX pci_conf_print_cpci_hostwap_cap */ 1256 1257 /* 1258 * For both command register and status register. 1259 * The argument "idx" is index number (0 to 7). 1260 */ 1261 static int 1262 pcix_split_trans(unsigned int idx) 1263 { 1264 static int table[8] = { 1265 1, 2, 3, 4, 8, 12, 16, 32 1266 }; 1267 1268 if (idx >= __arraycount(table)) 1269 return -1; 1270 return table[idx]; 1271 } 1272 1273 static void 1274 pci_conf_print_pcix_cap_2ndbusmode(int num) 1275 { 1276 const char *maxfreq, *maxperiod; 1277 1278 printf(" Mode: "); 1279 if (num <= 0x07) 1280 printf("PCI-X Mode 1\n"); 1281 else if (num <= 0x0b) 1282 printf("PCI-X 266 (Mode 2)\n"); 1283 else 1284 printf("PCI-X 533 (Mode 2)\n"); 1285 1286 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1287 switch (num & 0x03) { 1288 default: 1289 case 0: 1290 maxfreq = "N/A"; 1291 maxperiod = "N/A"; 1292 break; 1293 case 1: 1294 maxfreq = "66MHz"; 1295 maxperiod = "15ns"; 1296 break; 1297 case 2: 1298 maxfreq = "100MHz"; 1299 maxperiod = "10ns"; 1300 break; 1301 case 3: 1302 maxfreq = "133MHz"; 1303 maxperiod = "7.5ns"; 1304 break; 1305 } 1306 printf(" Max Clock Freq: %s\n", maxfreq); 1307 printf(" Min Clock Period: %s\n", maxperiod); 1308 } 1309 1310 static void 1311 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1312 { 1313 pcireg_t reg; 1314 int isbridge; 1315 int i; 1316 1317 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1318 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1319 printf("\n PCI-X %s Capabilities Register\n", 1320 isbridge ? "Bridge" : "Non-bridge"); 1321 1322 reg = regs[o2i(capoff)]; 1323 if (isbridge != 0) { 1324 printf(" Secondary status register: 0x%04x\n", 1325 (reg & 0xffff0000) >> 16); 1326 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1327 onoff("133MHz capable", reg, PCIX_STATUS_133); 1328 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1329 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1330 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1331 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1332 pci_conf_print_pcix_cap_2ndbusmode( 1333 __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1334 printf(" Version: 0x%x\n", 1335 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1336 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1337 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1338 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1339 } else { 1340 printf(" Command register: 0x%04x\n", 1341 (reg & 0xffff0000) >> 16); 1342 onoff("Data Parity Error Recovery", reg, 1343 PCIX_CMD_PERR_RECOVER); 1344 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1345 printf(" Maximum Burst Read Count: %u\n", 1346 PCIX_CMD_BYTECNT(reg)); 1347 printf(" Maximum Split Transactions: %d\n", 1348 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1349 >> PCIX_CMD_SPLTRANS_SHIFT)); 1350 } 1351 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1352 printf(" %sStatus register: 0x%08x\n", 1353 isbridge ? "Bridge " : "", reg); 1354 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1355 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1356 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1357 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1358 onoff("133MHz capable", reg, PCIX_STATUS_133); 1359 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1360 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1361 if (isbridge != 0) { 1362 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1363 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1364 } else { 1365 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1366 "bridge device", "simple device"); 1367 printf(" Designed max memory read byte count: %d\n", 1368 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1369 >> PCIX_STATUS_MAXB_SHIFT)); 1370 printf(" Designed max outstanding split transaction: %d\n", 1371 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1372 >> PCIX_STATUS_MAXST_SHIFT)); 1373 printf(" MAX cumulative Read Size: %u\n", 1374 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1375 onoff("Received split completion error", reg, 1376 PCIX_STATUS_SCERR); 1377 } 1378 onoff("266MHz capable", reg, PCIX_STATUS_266); 1379 onoff("533MHz capable", reg, PCIX_STATUS_533); 1380 1381 if (isbridge == 0) 1382 return; 1383 1384 /* Only for bridge */ 1385 for (i = 0; i < 2; i++) { 1386 reg = regs[o2i(capoff + PCIX_BRIDGE_UP_STCR + (4 * i))]; 1387 printf(" %s split transaction control register: 0x%08x\n", 1388 (i == 0) ? "Upstream" : "Downstream", reg); 1389 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1390 printf(" Commitment Limit: %d\n", 1391 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1392 } 1393 } 1394 1395 /* pci_conf_print_ht_slave_cap */ 1396 /* pci_conf_print_ht_host_cap */ 1397 /* pci_conf_print_ht_switch_cap */ 1398 /* pci_conf_print_ht_intr_cap */ 1399 /* pci_conf_print_ht_revid_cap */ 1400 /* pci_conf_print_ht_unitid_cap */ 1401 /* pci_conf_print_ht_extcnf_cap */ 1402 /* pci_conf_print_ht_addrmap_cap */ 1403 /* pci_conf_print_ht_msimap_cap */ 1404 1405 static void 1406 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1407 { 1408 pcireg_t val; 1409 uint32_t lo, hi; 1410 1411 /* 1412 * Print the rest of the command register bits. Others are 1413 * printed in pci_conf_print_ht_cap(). 1414 */ 1415 val = regs[o2i(capoff + PCI_HT_CMD)]; 1416 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1417 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1418 1419 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1420 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1421 printf(" Address Low register: 0x%08x\n", lo); 1422 printf(" Address high register: 0x%08x\n", hi); 1423 printf(" Address: 0x%016" PRIx64 "\n", 1424 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1425 } 1426 1427 /* pci_conf_print_ht_droute_cap */ 1428 /* pci_conf_print_ht_vcset_cap */ 1429 /* pci_conf_print_ht_retry_cap */ 1430 /* pci_conf_print_ht_x86enc_cap */ 1431 /* pci_conf_print_ht_gen3_cap */ 1432 /* pci_conf_print_ht_fle_cap */ 1433 /* pci_conf_print_ht_pm_cap */ 1434 /* pci_conf_print_ht_hnc_cap */ 1435 1436 static const struct ht_types { 1437 pcireg_t cap; 1438 const char *name; 1439 void (*printfunc)(const pcireg_t *, int); 1440 } ht_captab[] = { 1441 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1442 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1443 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1444 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1445 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1446 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1447 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1448 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1449 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1450 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1451 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1452 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1453 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1454 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1455 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1456 {PCI_HT_CAP_PM, "Power Management", NULL }, 1457 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1458 }; 1459 1460 static void 1461 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1462 { 1463 pcireg_t val, foundcap; 1464 unsigned int off; 1465 1466 val = regs[o2i(capoff + PCI_HT_CMD)]; 1467 1468 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1469 1470 printf(" Command register: 0x%04x\n", val >> 16); 1471 foundcap = PCI_HT_CAP(val); 1472 for (off = 0; off < __arraycount(ht_captab); off++) { 1473 if (ht_captab[off].cap == foundcap) 1474 break; 1475 } 1476 printf(" Capability Type: 0x%02x ", foundcap); 1477 if (off >= __arraycount(ht_captab)) { 1478 printf("(unknown)\n"); 1479 return; 1480 } 1481 printf("(%s)\n", ht_captab[off].name); 1482 if (ht_captab[off].printfunc != NULL) 1483 ht_captab[off].printfunc(regs, capoff); 1484 } 1485 1486 static void 1487 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1488 { 1489 uint16_t caps; 1490 1491 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1492 1493 printf("\n PCI Vendor Specific Capabilities Register\n"); 1494 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1495 } 1496 1497 static void 1498 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1499 { 1500 pcireg_t val; 1501 1502 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1503 1504 printf("\n Debugport Capability Register\n"); 1505 printf(" Debug base Register: 0x%04x\n", 1506 val >> PCI_DEBUG_BASER_SHIFT); 1507 printf(" port offset: 0x%04x\n", 1508 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1509 printf(" BAR number: %u\n", 1510 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1511 } 1512 1513 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1514 /* XXX pci_conf_print_hotplug_cap */ 1515 1516 static void 1517 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1518 { 1519 pcireg_t reg; 1520 1521 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1522 1523 printf("\n Subsystem ID Capability Register\n"); 1524 printf(" Subsystem ID : 0x%08x\n", reg); 1525 } 1526 1527 /* XXX pci_conf_print_agp8_cap */ 1528 /* XXX pci_conf_print_secure_cap */ 1529 1530 static void 1531 pci_print_pcie_L0s_latency(uint32_t val) 1532 { 1533 1534 switch (val) { 1535 case 0x0: 1536 printf("Less than 64ns\n"); 1537 break; 1538 case 0x1: 1539 case 0x2: 1540 case 0x3: 1541 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1542 break; 1543 case 0x4: 1544 printf("512ns to less than 1us\n"); 1545 break; 1546 case 0x5: 1547 printf("1us to less than 2us\n"); 1548 break; 1549 case 0x6: 1550 printf("2us - 4us\n"); 1551 break; 1552 case 0x7: 1553 printf("More than 4us\n"); 1554 break; 1555 } 1556 } 1557 1558 static void 1559 pci_print_pcie_L1_latency(uint32_t val) 1560 { 1561 1562 switch (val) { 1563 case 0x0: 1564 printf("Less than 1us\n"); 1565 break; 1566 case 0x6: 1567 printf("32us - 64us\n"); 1568 break; 1569 case 0x7: 1570 printf("More than 64us\n"); 1571 break; 1572 default: 1573 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1574 break; 1575 } 1576 } 1577 1578 static void 1579 pci_print_pcie_compl_timeout(uint32_t val) 1580 { 1581 1582 switch (val) { 1583 case 0x0: 1584 printf("50us to 50ms\n"); 1585 break; 1586 case 0x5: 1587 printf("16ms to 55ms\n"); 1588 break; 1589 case 0x6: 1590 printf("65ms to 210ms\n"); 1591 break; 1592 case 0x9: 1593 printf("260ms to 900ms\n"); 1594 break; 1595 case 0xa: 1596 printf("1s to 3.5s\n"); 1597 break; 1598 default: 1599 printf("unknown %u value\n", val); 1600 break; 1601 } 1602 } 1603 1604 static const char * const pcie_linkspeeds[] = {"2.5", "2.5", "5.0", "8.0"}; 1605 1606 static void 1607 pci_print_pcie_linkspeed(pcireg_t val) 1608 { 1609 1610 if (val > __arraycount(pcie_linkspeeds)) 1611 printf("unknown value (%u)\n", val); 1612 else 1613 printf("%sGT/s\n", pcie_linkspeeds[val]); 1614 } 1615 1616 static void 1617 pci_print_pcie_linkspeedvector(pcireg_t val) 1618 { 1619 unsigned int i; 1620 1621 /* Start from 0 */ 1622 for (i = 0; i < 16; i++) 1623 if (((val >> i) & 0x01) != 0) { 1624 if (i >= __arraycount(pcie_linkspeeds)) 1625 printf(" unknown vector (0x%x)", 1 << i); 1626 else 1627 printf(" %sGT/s", pcie_linkspeeds[i]); 1628 } 1629 } 1630 1631 static void 1632 pci_print_pcie_link_deemphasis(pcireg_t val) 1633 { 1634 switch (val) { 1635 case 0: 1636 printf("-6dB"); 1637 break; 1638 case 1: 1639 printf("-3.5dB"); 1640 break; 1641 default: 1642 printf("(reserved value)"); 1643 } 1644 } 1645 1646 static void 1647 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1648 { 1649 pcireg_t reg; /* for each register */ 1650 pcireg_t val; /* for each bitfield */ 1651 bool check_link = false; 1652 bool check_slot = false; 1653 bool check_rootport = false; 1654 unsigned int pciever; 1655 unsigned int i; 1656 1657 printf("\n PCI Express Capabilities Register\n"); 1658 /* Capability Register */ 1659 reg = regs[o2i(capoff)]; 1660 printf(" Capability register: 0x%04x\n", reg >> 16); 1661 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1662 printf(" Capability version: %u\n", pciever); 1663 printf(" Device type: "); 1664 switch ((reg & 0x00f00000) >> 20) { 1665 case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */ 1666 printf("PCI Express Endpoint device\n"); 1667 check_link = true; 1668 break; 1669 case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */ 1670 printf("Legacy PCI Express Endpoint device\n"); 1671 check_link = true; 1672 break; 1673 case PCIE_XCAP_TYPE_ROOT: /* 0x4 */ 1674 printf("Root Port of PCI Express Root Complex\n"); 1675 check_link = true; 1676 check_slot = true; 1677 check_rootport = true; 1678 break; 1679 case PCIE_XCAP_TYPE_UP: /* 0x5 */ 1680 printf("Upstream Port of PCI Express Switch\n"); 1681 break; 1682 case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ 1683 printf("Downstream Port of PCI Express Switch\n"); 1684 check_slot = true; 1685 check_rootport = true; 1686 break; 1687 case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ 1688 printf("PCI Express to PCI/PCI-X Bridge\n"); 1689 break; 1690 case PCIE_XCAP_TYPE_PCI2PCIE: /* 0x8 */ 1691 printf("PCI/PCI-X to PCI Express Bridge\n"); 1692 break; 1693 case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */ 1694 printf("Root Complex Integrated Endpoint\n"); 1695 break; 1696 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */ 1697 check_rootport = true; 1698 printf("Root Complex Event Collector\n"); 1699 break; 1700 default: 1701 printf("unknown\n"); 1702 break; 1703 } 1704 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1705 printf(" Interrupt Message Number: 0x%02x\n", 1706 (unsigned int)__SHIFTOUT(reg, PCIE_XCAP_IRQ)); 1707 1708 /* Device Capability Register */ 1709 reg = regs[o2i(capoff + PCIE_DCAP)]; 1710 printf(" Device Capabilities Register: 0x%08x\n", reg); 1711 printf(" Max Payload Size Supported: %u bytes max\n", 1712 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1713 printf(" Phantom Functions Supported: "); 1714 switch (__SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) { 1715 case 0x0: 1716 printf("not available\n"); 1717 break; 1718 case 0x1: 1719 printf("MSB\n"); 1720 break; 1721 case 0x2: 1722 printf("two MSB\n"); 1723 break; 1724 case 0x3: 1725 printf("All three bits\n"); 1726 break; 1727 } 1728 printf(" Extended Tag Field Supported: %dbit\n", 1729 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1730 printf(" Endpoint L0 Acceptable Latency: "); 1731 pci_print_pcie_L0s_latency(__SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY)); 1732 printf(" Endpoint L1 Acceptable Latency: "); 1733 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY)); 1734 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1735 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1736 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1737 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1738 printf(" Captured Slot Power Limit Value: %u\n", 1739 (unsigned int)__SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL)); 1740 printf(" Captured Slot Power Limit Scale: %u\n", 1741 (unsigned int)__SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE)); 1742 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1743 1744 /* Device Control Register */ 1745 reg = regs[o2i(capoff + PCIE_DCSR)]; 1746 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1747 onoff("Correctable Error Reporting Enable", reg, 1748 PCIE_DCSR_ENA_COR_ERR); 1749 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1750 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1751 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1752 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1753 printf(" Max Payload Size: %d byte\n", 1754 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD)); 1755 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1756 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1757 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1758 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1759 printf(" Max Read Request Size: %d byte\n", 1760 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ)); 1761 1762 /* Device Status Register */ 1763 reg = regs[o2i(capoff + PCIE_DCSR)]; 1764 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1765 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1766 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1767 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1768 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1769 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1770 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1771 onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD); 1772 1773 if (check_link) { 1774 /* Link Capability Register */ 1775 reg = regs[o2i(capoff + PCIE_LCAP)]; 1776 printf(" Link Capabilities Register: 0x%08x\n", reg); 1777 printf(" Maximum Link Speed: "); 1778 pci_print_pcie_linkspeed(reg & PCIE_LCAP_MAX_SPEED); 1779 printf(" Maximum Link Width: x%u lanes\n", 1780 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH)); 1781 printf(" Active State PM Support: "); 1782 switch (__SHIFTOUT(reg, PCIE_LCAP_ASPM)) { 1783 case 0x0: 1784 printf("No ASPM support\n"); 1785 break; 1786 case 0x1: 1787 printf("L0s supported\n"); 1788 break; 1789 case 0x2: 1790 printf("L1 supported\n"); 1791 break; 1792 case 0x3: 1793 printf("L0s and L1 supported\n"); 1794 break; 1795 } 1796 printf(" L0 Exit Latency: "); 1797 pci_print_pcie_L0s_latency(__SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT)); 1798 printf(" L1 Exit Latency: "); 1799 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_LCAP_L1_EXIT)); 1800 printf(" Port Number: %u\n", 1801 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_PORT)); 1802 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1803 onoff("Surprise Down Error Report", reg, 1804 PCIE_LCAP_SURPRISE_DOWN); 1805 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1806 onoff("Link BW Notification Capable", reg, 1807 PCIE_LCAP_LINK_BW_NOTIFY); 1808 onoff("ASPM Optionally Compliance", reg, 1809 PCIE_LCAP_ASPM_COMPLIANCE); 1810 1811 /* Link Control Register */ 1812 reg = regs[o2i(capoff + PCIE_LCSR)]; 1813 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1814 printf(" Active State PM Control: "); 1815 switch (reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S)) { 1816 case 0: 1817 printf("disabled\n"); 1818 break; 1819 case 1: 1820 printf("L0s Entry Enabled\n"); 1821 break; 1822 case 2: 1823 printf("L1 Entry Enabled\n"); 1824 break; 1825 case 3: 1826 printf("L0s and L1 Entry Enabled\n"); 1827 break; 1828 } 1829 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1830 "128bytes", "64bytes"); 1831 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1832 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1833 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1834 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1835 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1836 onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD); 1837 onoff("Link Bandwidth Management Interrupt Enable", reg, 1838 PCIE_LCSR_LBMIE); 1839 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1840 PCIE_LCSR_LABIE); 1841 printf(" DRS Signaling Control: "); 1842 switch (__SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) { 1843 case 0: 1844 printf("not reported\n"); 1845 break; 1846 case 1: 1847 printf("Interrupt Enabled\n"); 1848 break; 1849 case 2: 1850 printf("DRS to FRS Signaling Enabled\n"); 1851 break; 1852 default: 1853 printf("reserved\n"); 1854 break; 1855 } 1856 1857 /* Link Status Register */ 1858 reg = regs[o2i(capoff + PCIE_LCSR)]; 1859 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1860 printf(" Negotiated Link Speed: "); 1861 pci_print_pcie_linkspeed(__SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 1862 printf(" Negotiated Link Width: x%u lanes\n", 1863 (unsigned int)__SHIFTOUT(reg, PCIE_LCSR_NLW)); 1864 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1865 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1866 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1867 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1868 onoff("Link Bandwidth Management Status", reg, 1869 PCIE_LCSR_LINK_BW_MGMT); 1870 onoff("Link Autonomous Bandwidth Status", reg, 1871 PCIE_LCSR_LINK_AUTO_BW); 1872 } 1873 1874 if (check_slot == true) { 1875 /* Slot Capability Register */ 1876 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1877 printf(" Slot Capability Register: 0x%08x\n", reg); 1878 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1879 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1880 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1881 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1882 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1883 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1884 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1885 printf(" Slot Power Limit Value: %d\n", 1886 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1887 printf(" Slot Power Limit Scale: %d\n", 1888 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1889 onoff("Electromechanical Interlock Present", reg, 1890 PCIE_SLCAP_EIP); 1891 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1892 printf(" Physical Slot Number: %d\n", 1893 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1894 1895 /* Slot Control Register */ 1896 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1897 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1898 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1899 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1900 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1901 onoff("Presence Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1902 onoff("Command Completed Interrupt Enabled", reg, 1903 PCIE_SLCSR_CCE); 1904 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1905 printf(" Attention Indicator Control: "); 1906 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1907 case 0x0: 1908 printf("reserved\n"); 1909 break; 1910 case PCIE_SLCSR_IND_ON: 1911 printf("on\n"); 1912 break; 1913 case PCIE_SLCSR_IND_BLINK: 1914 printf("blink\n"); 1915 break; 1916 case PCIE_SLCSR_IND_OFF: 1917 printf("off\n"); 1918 break; 1919 } 1920 printf(" Power Indicator Control: "); 1921 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1922 case 0x0: 1923 printf("reserved\n"); 1924 break; 1925 case PCIE_SLCSR_IND_ON: 1926 printf("on\n"); 1927 break; 1928 case PCIE_SLCSR_IND_BLINK: 1929 printf("blink\n"); 1930 break; 1931 case PCIE_SLCSR_IND_OFF: 1932 printf("off\n"); 1933 break; 1934 } 1935 printf(" Power Controller Control: Power %s\n", 1936 reg & PCIE_SLCSR_PCC ? "off" : "on"); 1937 onoff("Electromechanical Interlock Control", 1938 reg, PCIE_SLCSR_EIC); 1939 onoff("Data Link Layer State Changed Enable", reg, 1940 PCIE_SLCSR_DLLSCE); 1941 onoff("Auto Slot Power Limit Disable", reg, 1942 PCIE_SLCSR_AUTOSPLDIS); 1943 1944 /* Slot Status Register */ 1945 printf(" Slot Status Register: 0x%04x\n", reg >> 16); 1946 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1947 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1948 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1949 onoff("Presence Detect Changed", reg, PCIE_SLCSR_PDC); 1950 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1951 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1952 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1953 onoff("Electromechanical Interlock engaged", reg, 1954 PCIE_SLCSR_EIS); 1955 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1956 } 1957 1958 if (check_rootport == true) { 1959 /* Root Control Register */ 1960 reg = regs[o2i(capoff + PCIE_RCR)]; 1961 printf(" Root Control Register: %04x\n", reg & 0xffff); 1962 onoff("SERR on Correctable Error Enable", reg, 1963 PCIE_RCR_SERR_CER); 1964 onoff("SERR on Non-Fatal Error Enable", reg, 1965 PCIE_RCR_SERR_NFER); 1966 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1967 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1968 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1969 1970 /* Root Capability Register */ 1971 printf(" Root Capability Register: 0x%04x\n", 1972 reg >> 16); 1973 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 1974 1975 /* Root Status Register */ 1976 reg = regs[o2i(capoff + PCIE_RSR)]; 1977 printf(" Root Status Register: 0x%08x\n", reg); 1978 printf(" PME Requester ID: 0x%04x\n", 1979 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1980 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1981 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1982 } 1983 1984 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1985 if (pciever < 2) 1986 return; 1987 1988 /* Device Capabilities 2 */ 1989 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1990 printf(" Device Capabilities 2: 0x%08x\n", reg); 1991 printf(" Completion Timeout Ranges Supported: "); 1992 val = reg & PCIE_DCAP2_COMPT_RANGE; 1993 switch (val) { 1994 case 0: 1995 printf("not supported\n"); 1996 break; 1997 default: 1998 for (i = 0; i <= 3; i++) { 1999 if (((val >> i) & 0x01) != 0) 2000 printf("%c", 'A' + i); 2001 } 2002 printf("\n"); 2003 } 2004 onoff("Completion Timeout Disable Supported", reg, 2005 PCIE_DCAP2_COMPT_DIS); 2006 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 2007 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 2008 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 2009 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 2010 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 2011 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 2012 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 2013 printf(" TPH Completer Supported: "); 2014 switch (__SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) { 2015 case 0: 2016 printf("Not supported\n"); 2017 break; 2018 case 1: 2019 printf("TPH\n"); 2020 break; 2021 case 3: 2022 printf("TPH and Extended TPH\n"); 2023 break; 2024 default: 2025 printf("(reserved value)\n"); 2026 break; 2027 2028 } 2029 printf(" LN System CLS: "); 2030 switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 2031 case 0x0: 2032 printf("Not supported or not in effect\n"); 2033 break; 2034 case 0x1: 2035 printf("64byte cachelines in effect\n"); 2036 break; 2037 case 0x2: 2038 printf("128byte cachelines in effect\n"); 2039 break; 2040 case 0x3: 2041 printf("Reserved\n"); 2042 break; 2043 } 2044 printf(" OBFF Supported: "); 2045 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 2046 case 0x0: 2047 printf("Not supported\n"); 2048 break; 2049 case 0x1: 2050 printf("Message only\n"); 2051 break; 2052 case 0x2: 2053 printf("WAKE# only\n"); 2054 break; 2055 case 0x3: 2056 printf("Both\n"); 2057 break; 2058 } 2059 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 2060 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 2061 val = __SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP); 2062 printf(" Max End-End TLP Prefixes: %u\n", (val == 0) ? 4 : val); 2063 printf(" Emergency Power Reduction Supported: "); 2064 switch (__SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) { 2065 case 0x0: 2066 printf("Not supported\n"); 2067 break; 2068 case 0x1: 2069 printf("Device Specific mechanism\n"); 2070 break; 2071 case 0x2: 2072 printf("Form Factor spec or Device Specific mechanism\n"); 2073 break; 2074 case 0x3: 2075 printf("Reserved\n"); 2076 break; 2077 } 2078 onoff("Emergency Power Reduction Initialization Required", reg, 2079 PCIE_DCAP2_EMGPWRRED_INI); 2080 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 2081 2082 /* Device Control 2 */ 2083 reg = regs[o2i(capoff + PCIE_DCSR2)]; 2084 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 2085 printf(" Completion Timeout Value: "); 2086 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 2087 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 2088 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 2089 onoff("AtomicOp Requester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 2090 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 2091 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 2092 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 2093 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 2094 onoff("Emergency Power Reduction Request", reg, 2095 PCIE_DCSR2_EMGPWRRED_REQ); 2096 printf(" OBFF: "); 2097 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 2098 case 0x0: 2099 printf("Disabled\n"); 2100 break; 2101 case 0x1: 2102 printf("Enabled with Message Signaling Variation A\n"); 2103 break; 2104 case 0x2: 2105 printf("Enabled with Message Signaling Variation B\n"); 2106 break; 2107 case 0x3: 2108 printf("Enabled using WAKE# signaling\n"); 2109 break; 2110 } 2111 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 2112 2113 if (check_link) { 2114 bool drs_supported = false; 2115 2116 /* Link Capability 2 */ 2117 reg = regs[o2i(capoff + PCIE_LCAP2)]; 2118 /* If the vector is 0, LCAP2 is not implemented */ 2119 if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) { 2120 printf(" Link Capabilities 2: 0x%08x\n", reg); 2121 printf(" Supported Link Speeds Vector:"); 2122 pci_print_pcie_linkspeedvector( 2123 __SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 2124 printf("\n"); 2125 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 2126 printf(" " 2127 "Lower SKP OS Generation Supported Speed Vector:"); 2128 pci_print_pcie_linkspeedvector( 2129 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 2130 printf("\n"); 2131 printf(" " 2132 "Lower SKP OS Reception Supported Speed Vector:"); 2133 pci_print_pcie_linkspeedvector( 2134 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 2135 printf("\n"); 2136 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 2137 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 2138 } 2139 2140 /* Link Control 2 */ 2141 reg = regs[o2i(capoff + PCIE_LCSR2)]; 2142 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 2143 printf(" Target Link Speed: "); 2144 pci_print_pcie_linkspeed(__SHIFTOUT(reg, 2145 PCIE_LCSR2_TGT_LSPEED)); 2146 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 2147 onoff("HW Autonomous Speed Disabled", reg, 2148 PCIE_LCSR2_HW_AS_DIS); 2149 printf(" Selectable De-emphasis: "); 2150 pci_print_pcie_link_deemphasis( 2151 __SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP)); 2152 printf("\n"); 2153 printf(" Transmit Margin: %u\n", 2154 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 2155 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 2156 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 2157 printf(" Compliance Present/De-emphasis: "); 2158 pci_print_pcie_link_deemphasis( 2159 __SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP)); 2160 printf("\n"); 2161 2162 /* Link Status 2 */ 2163 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 2164 printf(" Current De-emphasis Level: "); 2165 pci_print_pcie_link_deemphasis( 2166 __SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL)); 2167 printf("\n"); 2168 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 2169 onoff("Equalization Phase 1 Successful", reg, 2170 PCIE_LCSR2_EQP1_SUC); 2171 onoff("Equalization Phase 2 Successful", reg, 2172 PCIE_LCSR2_EQP2_SUC); 2173 onoff("Equalization Phase 3 Successful", reg, 2174 PCIE_LCSR2_EQP3_SUC); 2175 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 2176 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 2177 if (drs_supported) { 2178 printf(" Downstream Component Presence: "); 2179 switch (__SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 2180 case PCIE_DSCOMPN_DOWN_NOTDETERM: 2181 printf("Link Down - Presence Not" 2182 " Determined\n"); 2183 break; 2184 case PCIE_DSCOMPN_DOWN_NOTPRES: 2185 printf("Link Down - Component Not Present\n"); 2186 break; 2187 case PCIE_DSCOMPN_DOWN_PRES: 2188 printf("Link Down - Component Present\n"); 2189 break; 2190 case PCIE_DSCOMPN_UP_PRES: 2191 printf("Link Up - Component Present\n"); 2192 break; 2193 case PCIE_DSCOMPN_UP_PRES_DRS: 2194 printf("Link Up - Component Present and DRS" 2195 " received\n"); 2196 break; 2197 default: 2198 printf("reserved\n"); 2199 break; 2200 } 2201 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 2202 } 2203 } 2204 2205 /* Slot Capability 2 */ 2206 /* Slot Control 2 */ 2207 /* Slot Status 2 */ 2208 } 2209 2210 static void 2211 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 2212 { 2213 pcireg_t reg; 2214 2215 printf("\n MSI-X Capability Register\n"); 2216 2217 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2218 printf(" Message Control register: 0x%04x\n", 2219 (reg >> 16) & 0xff); 2220 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 2221 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 2222 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 2223 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 2224 printf(" Table offset register: 0x%08x\n", reg); 2225 printf(" Table offset: 0x%08x\n", 2226 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 2227 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 2228 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 2229 printf(" Pending bit array register: 0x%08x\n", reg); 2230 printf(" Pending bit array offset: 0x%08x\n", 2231 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2232 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2233 } 2234 2235 static void 2236 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2237 { 2238 pcireg_t reg; 2239 2240 printf("\n Serial ATA Capability Register\n"); 2241 2242 reg = regs[o2i(capoff + PCI_SATA_REV)]; 2243 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2244 printf(" Revision: %u.%u\n", 2245 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2246 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2247 2248 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2249 2250 printf(" BAR Register: 0x%08x\n", reg); 2251 printf(" Register location: "); 2252 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2253 printf("in config space\n"); 2254 else { 2255 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2256 printf(" BAR offset: 0x%08x\n", 2257 (pcireg_t)__SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2258 } 2259 } 2260 2261 static void 2262 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2263 { 2264 pcireg_t reg; 2265 2266 printf("\n Advanced Features Capability Register\n"); 2267 2268 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2269 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2270 printf(" AF Structure Length: 0x%02x\n", 2271 (pcireg_t)__SHIFTOUT(reg, PCI_AF_LENGTH)); 2272 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2273 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2274 reg = regs[o2i(capoff + PCI_AFCSR)]; 2275 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2276 /* 2277 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2278 * and it's always 0 on read 2279 */ 2280 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2281 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2282 } 2283 2284 static struct { 2285 pcireg_t cap; 2286 const char *name; 2287 void (*printfunc)(const pcireg_t *, int); 2288 } pci_captab[] = { 2289 { PCI_CAP_RESERVED0, "reserved", NULL }, 2290 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2291 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2292 { PCI_CAP_VPD, "VPD", NULL }, 2293 { PCI_CAP_SLOTID, "SlotID", NULL }, 2294 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2295 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2296 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2297 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2298 { PCI_CAP_VENDSPEC, "Vendor-specific", 2299 pci_conf_print_vendspec_cap }, 2300 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2301 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2302 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2303 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2304 pci_conf_print_subsystem_cap }, 2305 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2306 { PCI_CAP_SECURE, "Secure Device", NULL }, 2307 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2308 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2309 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2310 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2311 { PCI_CAP_EA, "Enhanced Allocation", NULL } 2312 }; 2313 2314 static int 2315 pci_conf_find_cap(const pcireg_t *regs, int capoff, unsigned int capid, 2316 int *offsetp) 2317 { 2318 pcireg_t rval; 2319 int off; 2320 2321 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2322 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2323 rval = regs[o2i(off)]; 2324 if (capid == PCI_CAPLIST_CAP(rval)) { 2325 if (offsetp != NULL) 2326 *offsetp = off; 2327 return 1; 2328 } 2329 } 2330 return 0; 2331 } 2332 2333 static void 2334 pci_conf_print_caplist( 2335 #ifdef _KERNEL 2336 pci_chipset_tag_t pc, pcitag_t tag, 2337 #endif 2338 const pcireg_t *regs, int capoff) 2339 { 2340 int off; 2341 pcireg_t foundcap; 2342 pcireg_t rval; 2343 bool foundtable[__arraycount(pci_captab)]; 2344 unsigned int i; 2345 2346 /* Clear table */ 2347 for (i = 0; i < __arraycount(pci_captab); i++) 2348 foundtable[i] = false; 2349 2350 /* Print capability register's offset and the type first */ 2351 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2352 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2353 rval = regs[o2i(off)]; 2354 printf(" Capability register at 0x%02x\n", off); 2355 2356 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2357 foundcap = PCI_CAPLIST_CAP(rval); 2358 if (foundcap < __arraycount(pci_captab)) { 2359 printf("%s)\n", pci_captab[foundcap].name); 2360 /* Mark as found */ 2361 foundtable[foundcap] = true; 2362 } else 2363 printf("unknown)\n"); 2364 } 2365 2366 /* 2367 * And then, print the detail of each capability registers 2368 * in capability value's order. 2369 */ 2370 for (i = 0; i < __arraycount(pci_captab); i++) { 2371 if (foundtable[i] == false) 2372 continue; 2373 2374 /* 2375 * The type was found. Search capability list again and 2376 * print all capabilities that the capabiliy type is 2377 * the same. This is required because some capabilities 2378 * appear multiple times (e.g. HyperTransport capability). 2379 */ 2380 #if 0 2381 if (pci_conf_find_cap(regs, capoff, i, &off)) { 2382 rval = regs[o2i(off)]; 2383 if (pci_captab[i].printfunc != NULL) 2384 pci_captab[i].printfunc(regs, off); 2385 } 2386 #else 2387 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2388 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2389 rval = regs[o2i(off)]; 2390 if ((PCI_CAPLIST_CAP(rval) == i) 2391 && (pci_captab[i].printfunc != NULL)) 2392 pci_captab[i].printfunc(regs, off); 2393 } 2394 #endif 2395 } 2396 } 2397 2398 /* Extended Capability */ 2399 2400 static void 2401 pci_conf_print_aer_cap_uc(pcireg_t reg) 2402 { 2403 2404 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2405 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2406 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2407 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2408 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2409 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2410 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2411 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2412 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2413 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2414 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2415 onoff("Unsupported Request Error", reg, 2416 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2417 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2418 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2419 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2420 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2421 onoff("TLP Prefix Blocked Error", reg, 2422 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2423 onoff("Poisoned TLP Egress Blocked", reg, 2424 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2425 } 2426 2427 static void 2428 pci_conf_print_aer_cap_cor(pcireg_t reg) 2429 { 2430 2431 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2432 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2433 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2434 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2435 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2436 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2437 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2438 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2439 } 2440 2441 static void 2442 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2443 { 2444 2445 printf(" First Error Pointer: 0x%04x\n", 2446 (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2447 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2448 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2449 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2450 onoff("ECRC Check Enable", reg, PCI_AER_ECRC_CHECK_ENABLE); 2451 onoff("Multiple Header Recording Capable", reg, 2452 PCI_AER_MULT_HDR_CAPABLE); 2453 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2454 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2455 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2456 2457 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2458 if (!tlp_prefix_log) 2459 return; 2460 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2461 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2462 } 2463 2464 static void 2465 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2466 { 2467 2468 onoff("Correctable Error Reporting Enable", reg, 2469 PCI_AER_ROOTERR_COR_ENABLE); 2470 onoff("Non-Fatal Error Reporting Enable", reg, 2471 PCI_AER_ROOTERR_NF_ENABLE); 2472 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2473 } 2474 2475 static void 2476 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2477 { 2478 2479 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2480 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2481 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2482 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2483 PCI_AER_ROOTERR_MULTI_UC_ERR); 2484 onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL); 2485 onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR); 2486 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2487 printf(" Advanced Error Interrupt Message Number: 0x%02x\n", 2488 (unsigned int)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2489 } 2490 2491 static void 2492 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2493 { 2494 2495 printf(" Correctable Source ID: 0x%04x\n", 2496 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2497 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2498 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2499 } 2500 2501 static void 2502 pci_conf_print_aer_cap(const pcireg_t *regs, int capoff, int extcapoff) 2503 { 2504 pcireg_t reg; 2505 int pcie_capoff; 2506 int pcie_devtype = -1; 2507 bool tlp_prefix_log = false; 2508 2509 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2510 reg = regs[o2i(pcie_capoff)]; 2511 pcie_devtype = PCIE_XCAP_TYPE(reg); 2512 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2513 if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2514 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2515 /* End-End TLP Prefix Supported */ 2516 if (reg & PCIE_DCAP2_EETLP_PREF) { 2517 tlp_prefix_log = true; 2518 } 2519 } 2520 } 2521 2522 printf("\n Advanced Error Reporting Register\n"); 2523 2524 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2525 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2526 pci_conf_print_aer_cap_uc(reg); 2527 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2528 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2529 pci_conf_print_aer_cap_uc(reg); 2530 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2531 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2532 pci_conf_print_aer_cap_uc(reg); 2533 2534 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2535 printf(" Correctable Error Status register: 0x%08x\n", reg); 2536 pci_conf_print_aer_cap_cor(reg); 2537 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2538 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2539 pci_conf_print_aer_cap_cor(reg); 2540 2541 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2542 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2543 reg); 2544 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2545 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2546 printf(" Header Log register:\n"); 2547 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2548 extcapoff + PCI_AER_ROOTERR_CMD); 2549 2550 switch (pcie_devtype) { 2551 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2552 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2553 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2554 printf(" Root Error Command register: 0x%08x\n", reg); 2555 pci_conf_print_aer_cap_rooterr_cmd(reg); 2556 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2557 printf(" Root Error Status register: 0x%08x\n", reg); 2558 pci_conf_print_aer_cap_rooterr_status(reg); 2559 2560 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2561 printf(" Error Source Identification: 0x%04x\n", reg); 2562 pci_conf_print_aer_cap_errsrc_id(reg); 2563 break; 2564 } 2565 2566 if (tlp_prefix_log) { 2567 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2568 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2569 } 2570 } 2571 2572 static void 2573 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2574 pcireg_t parbsel, int parbsize) 2575 { 2576 pcireg_t reg; 2577 int num = 16 << parbsel; 2578 int num_per_reg = sizeof(pcireg_t) / parbsize; 2579 int i, j; 2580 2581 /* First, dump the table */ 2582 for (i = 0; i < num; i += num_per_reg) { 2583 reg = regs[o2i(off + i / num_per_reg)]; 2584 printf(" %s Arbitration Table: 0x%08x\n", name, reg); 2585 } 2586 /* And then, decode each entry */ 2587 for (i = 0; i < num; i += num_per_reg) { 2588 reg = regs[o2i(off + i / num_per_reg)]; 2589 for (j = 0; j < num_per_reg; j++) 2590 printf(" Phase[%d]: %d\n", j, reg); 2591 } 2592 } 2593 2594 static void 2595 pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2596 { 2597 pcireg_t reg, n; 2598 int parbtab, parbsize; 2599 pcireg_t parbsel; 2600 int varbtab, varbsize; 2601 pcireg_t varbsel; 2602 int i, count; 2603 2604 printf("\n Virtual Channel Register\n"); 2605 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2606 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2607 count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2608 printf(" Extended VC Count: %d\n", count); 2609 n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2610 printf(" Low Priority Extended VC Count: %u\n", n); 2611 n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2612 printf(" Reference Clock: %s\n", 2613 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 2614 parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2615 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2616 2617 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2618 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2619 onoff("Hardware fixed arbitration scheme", 2620 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2621 onoff("WRR arbitration with 32 phases", 2622 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2623 onoff("WRR arbitration with 64 phases", 2624 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2625 onoff("WRR arbitration with 128 phases", 2626 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2627 varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2628 printf(" VC Arbitration Table Offset: 0x%x\n", varbtab); 2629 2630 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2631 printf(" Port VC Control register: 0x%04x\n", reg); 2632 varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2633 printf(" VC Arbitration Select: 0x%x\n", varbsel); 2634 2635 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2636 printf(" Port VC Status register: 0x%04x\n", reg); 2637 onoff("VC Arbitration Table Status", 2638 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 2639 2640 for (i = 0; i < count + 1; i++) { 2641 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 2642 printf(" VC number %d\n", i); 2643 printf(" VC Resource Capability Register: 0x%08x\n", reg); 2644 onoff(" Non-configurable Hardware fixed arbitration scheme", 2645 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 2646 onoff(" WRR arbitration with 32 phases", 2647 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 2648 onoff(" WRR arbitration with 64 phases", 2649 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 2650 onoff(" WRR arbitration with 128 phases", 2651 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 2652 onoff(" Time-based WRR arbitration with 128 phases", 2653 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 2654 onoff(" WRR arbitration with 256 phases", 2655 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 2656 onoff(" Advanced Packet Switching", 2657 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 2658 onoff(" Reject Snoop Transaction", 2659 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 2660 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 2661 printf(" Maximum Time Slots: %d\n", n); 2662 parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S; 2663 printf(" Port Arbitration Table offset: 0x%02x\n", 2664 parbtab); 2665 2666 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 2667 printf(" VC Resource Control Register: 0x%08x\n", reg); 2668 printf(" TC/VC Map: 0x%02x\n", 2669 (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 2670 /* 2671 * The load Port Arbitration Table bit is used to update 2672 * the Port Arbitration logic and it's always 0 on read, so 2673 * we don't print it. 2674 */ 2675 parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 2676 printf(" Port Arbitration Select: 0x%x\n", parbsel); 2677 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 2678 printf(" VC ID: %d\n", n); 2679 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 2680 2681 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 2682 printf(" VC Resource Status Register: 0x%08x\n", reg); 2683 onoff(" Port Arbitration Table Status", 2684 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 2685 onoff(" VC Negotiation Pending", 2686 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 2687 2688 if ((parbtab != 0) && (parbsel != 0)) 2689 pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab, 2690 "Port", parbsel, parbsize); 2691 } 2692 2693 varbsize = 8; 2694 if ((varbtab != 0) && (varbsel != 0)) 2695 pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab, 2696 " VC", varbsel, varbsize); 2697 } 2698 2699 static void 2700 pci_conf_print_pwrbdgt_base_power(uint8_t base, unsigned int scale) 2701 { 2702 if (base <= 0xef) { 2703 unsigned int sdiv = 1; 2704 for (unsigned int i = scale; i > 0; i--) 2705 sdiv *= 10; 2706 2707 printf("%u", base / sdiv); 2708 2709 if (scale != 0) { 2710 printf(".%u", base % sdiv); 2711 } 2712 printf ("W\n"); 2713 return; 2714 } 2715 2716 const char *s; 2717 2718 switch (base) { 2719 case 0xf0: 2720 s = "239W < x <= 250W"; 2721 break; 2722 case 0xf1: 2723 s = "250W < x <= 275W"; 2724 break; 2725 case 0xf2: 2726 s = "275W < x <= 300W"; 2727 break; 2728 default: 2729 s = "reserved for above 300W"; 2730 break; 2731 } 2732 printf("%s\n", s); 2733 } 2734 2735 static const char * 2736 pci_conf_print_pwrbdgt_type(uint8_t reg) 2737 { 2738 2739 switch (reg) { 2740 case 0x00: 2741 return "PME Aux"; 2742 case 0x01: 2743 return "Auxilary"; 2744 case 0x02: 2745 return "Idle"; 2746 case 0x03: 2747 return "Sustained"; 2748 case 0x04: 2749 return "Sustained (Emergency Power Reduction)"; 2750 case 0x05: 2751 return "Maximum (Emergency Power Reduction)"; 2752 case 0x07: 2753 return "Maximum"; 2754 default: 2755 return "Unknown"; 2756 } 2757 } 2758 2759 static const char * 2760 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 2761 { 2762 2763 switch (reg) { 2764 case 0x00: 2765 return "Power(12V)"; 2766 case 0x01: 2767 return "Power(3.3V)"; 2768 case 0x02: 2769 return "Power(1.5V or 1.8V)"; 2770 case 0x07: 2771 return "Thermal"; 2772 default: 2773 return "Unknown"; 2774 } 2775 } 2776 2777 static void 2778 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff) 2779 { 2780 pcireg_t reg; 2781 unsigned int scale; 2782 2783 printf("\n Power Budgeting\n"); 2784 2785 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 2786 printf(" Data Select register: 0x%08x\n", reg); 2787 2788 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 2789 printf(" Data register: 0x%08x\n", reg); 2790 scale = __SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE); 2791 printf(" Base Power: "); 2792 pci_conf_print_pwrbdgt_base_power((uint8_t)reg, scale); 2793 printf(" PM Sub State: 0x%hhx\n", 2794 (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 2795 printf(" PM State: D%u\n", 2796 (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 2797 printf(" Type: %s\n", 2798 pci_conf_print_pwrbdgt_type( 2799 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 2800 printf(" Power Rail: %s\n", 2801 pci_conf_print_pwrbdgt_pwrrail( 2802 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 2803 2804 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 2805 printf(" Power Budget Capability register: 0x%08x\n", reg); 2806 onoff("System Allocated", 2807 reg, PCI_PWRBDGT_CAP_SYSALLOC); 2808 } 2809 2810 static const char * 2811 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 2812 { 2813 2814 switch (type) { 2815 case 0x00: 2816 return "Configuration Space Element"; 2817 case 0x01: 2818 return "System Egress Port or internal sink (memory)"; 2819 case 0x02: 2820 return "Internal Root Complex Link"; 2821 default: 2822 return "Unknown"; 2823 } 2824 } 2825 2826 static void 2827 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int capoff, int extcapoff) 2828 { 2829 pcireg_t reg; 2830 unsigned char nent, linktype; 2831 int i; 2832 2833 printf("\n Root Complex Link Declaration\n"); 2834 2835 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 2836 printf(" Element Self Description Register: 0x%08x\n", reg); 2837 printf(" Element Type: %s\n", 2838 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 2839 nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 2840 printf(" Number of Link Entries: %hhu\n", nent); 2841 printf(" Component ID: %hhu\n", 2842 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 2843 printf(" Port Number: %hhu\n", 2844 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 2845 for (i = 0; i < nent; i++) { 2846 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 2847 printf(" Link Entry %d:\n", i + 1); 2848 printf(" Link Description Register: 0x%08x\n", reg); 2849 onoff(" Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID); 2850 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 2851 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 2852 "Configuration Space", "Memory-Mapped Space"); 2853 onoff(" Associated RCRB Header", reg, 2854 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 2855 printf(" Target Component ID: %hhu\n", 2856 (unsigned char)__SHIFTOUT(reg, 2857 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 2858 printf(" Target Port Number: %hhu\n", 2859 (unsigned char)__SHIFTOUT(reg, 2860 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 2861 2862 if (linktype == 0) { 2863 /* Memory-Mapped Space */ 2864 reg = regs[o2i(extcapoff 2865 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 2866 printf(" Link Address Low Register: 0x%08x\n", 2867 reg); 2868 reg = regs[o2i(extcapoff 2869 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 2870 printf(" Link Address High Register: 0x%08x\n", 2871 reg); 2872 } else { 2873 unsigned int nb; 2874 pcireg_t lo, hi; 2875 2876 /* Configuration Space */ 2877 lo = regs[o2i(extcapoff 2878 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 2879 printf(" Configuration Space Low Register: " 2880 "0x%08x\n", lo); 2881 hi = regs[o2i(extcapoff 2882 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 2883 printf(" Configuration Space High Register: " 2884 "0x%08x\n", hi); 2885 nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 2886 printf(" N: %u\n", nb); 2887 printf(" Func: %hhu\n", 2888 (unsigned char)__SHIFTOUT(lo, 2889 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 2890 printf(" Dev: %hhu\n", 2891 (unsigned char)__SHIFTOUT(lo, 2892 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 2893 printf(" Bus: %hhu\n", 2894 (unsigned char)__SHIFTOUT(lo, 2895 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 2896 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 2897 printf(" Configuration Space Base Address: " 2898 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 2899 } 2900 } 2901 } 2902 2903 /* XXX pci_conf_print_rclink_ctl_cap */ 2904 2905 static void 2906 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2907 { 2908 pcireg_t reg; 2909 2910 printf("\n Root Complex Event Collector Association\n"); 2911 2912 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 2913 printf(" Association Bitmap for Root Complex Integrated Devices:" 2914 " 0x%08x\n", reg); 2915 } 2916 2917 /* XXX pci_conf_print_mfvc_cap */ 2918 /* XXX pci_conf_print_vc2_cap */ 2919 /* XXX pci_conf_print_rcrb_cap */ 2920 /* XXX pci_conf_print_vendor_cap */ 2921 /* XXX pci_conf_print_cac_cap */ 2922 2923 static void 2924 pci_conf_print_acs_cap(const pcireg_t *regs, int capoff, int extcapoff) 2925 { 2926 pcireg_t reg, cap, ctl; 2927 unsigned int size, i; 2928 2929 printf("\n Access Control Services\n"); 2930 2931 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 2932 cap = reg & 0xffff; 2933 ctl = reg >> 16; 2934 printf(" ACS Capability register: 0x%08x\n", cap); 2935 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 2936 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 2937 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 2938 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 2939 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 2940 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 2941 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 2942 size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 2943 if (size == 0) 2944 size = 256; 2945 printf(" Egress Control Vector Size: %u\n", size); 2946 printf(" ACS Control register: 0x%08x\n", ctl); 2947 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 2948 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 2949 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 2950 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 2951 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 2952 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 2953 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 2954 2955 /* 2956 * If the P2P Egress Control Capability bit is 0, ignore the Egress 2957 * Control vector. 2958 */ 2959 if ((cap & PCI_ACS_CAP_E) == 0) 2960 return; 2961 for (i = 0; i < size; i += 32) 2962 printf(" Egress Control Vector [%u..%u]: 0x%08x\n", i + 31, 2963 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 2964 } 2965 2966 static void 2967 pci_conf_print_ari_cap(const pcireg_t *regs, int capoff, int extcapoff) 2968 { 2969 pcireg_t reg, cap, ctl; 2970 2971 printf("\n Alternative Routing-ID Interpretation Register\n"); 2972 2973 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2974 cap = reg & 0xffff; 2975 ctl = reg >> 16; 2976 printf(" Capability register: 0x%08x\n", cap); 2977 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 2978 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 2979 printf(" Next Function Number: %u\n", 2980 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 2981 printf(" Control register: 0x%08x\n", ctl); 2982 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 2983 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 2984 printf(" Function Group: %u\n", 2985 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 2986 } 2987 2988 static void 2989 pci_conf_print_ats_cap(const pcireg_t *regs, int capoff, int extcapoff) 2990 { 2991 pcireg_t reg, cap, ctl; 2992 unsigned int num; 2993 2994 printf("\n Address Translation Services\n"); 2995 2996 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2997 cap = reg & 0xffff; 2998 ctl = reg >> 16; 2999 printf(" Capability register: 0x%04x\n", cap); 3000 num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 3001 if (num == 0) 3002 num = 32; 3003 printf(" Invalidate Queue Depth: %u\n", num); 3004 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 3005 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 3006 3007 printf(" Control register: 0x%04x\n", ctl); 3008 printf(" Smallest Translation Unit: %u\n", 3009 (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU)); 3010 onoff("Enable", reg, PCI_ATS_CTL_EN); 3011 } 3012 3013 static void 3014 pci_conf_print_sernum_cap(const pcireg_t *regs, int capoff, int extcapoff) 3015 { 3016 pcireg_t lo, hi; 3017 3018 printf("\n Device Serial Number Register\n"); 3019 3020 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 3021 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 3022 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 3023 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 3024 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 3025 } 3026 3027 static void 3028 pci_conf_print_sriov_cap(const pcireg_t *regs, int capoff, int extcapoff) 3029 { 3030 char buf[sizeof("99999 MB")]; 3031 pcireg_t reg; 3032 pcireg_t total_vfs; 3033 int i; 3034 bool first; 3035 3036 printf("\n Single Root IO Virtualization Register\n"); 3037 3038 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 3039 printf(" Capabilities register: 0x%08x\n", reg); 3040 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 3041 onoff("ARI Capable Hierarchy Preserved", reg, 3042 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 3043 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 3044 printf(" VF Migration Interrupt Message Number: 0x%03x\n", 3045 (pcireg_t)__SHIFTOUT(reg, 3046 PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 3047 } 3048 3049 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 3050 printf(" Control register: 0x%04x\n", reg); 3051 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 3052 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 3053 onoff("VF Migration Interrupt Enable", reg, 3054 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 3055 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 3056 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 3057 3058 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 3059 printf(" Status register: 0x%04x\n", reg); 3060 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 3061 3062 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 3063 printf(" InitialVFs register: 0x%04x\n", reg); 3064 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 3065 printf(" TotalVFs register: 0x%04x\n", reg); 3066 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 3067 printf(" NumVFs register: 0x%04x\n", reg); 3068 3069 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 3070 printf(" Function Dependency Link register: 0x%04x\n", reg); 3071 3072 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 3073 printf(" First VF Offset register: 0x%04x\n", reg); 3074 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 3075 printf(" VF Stride register: 0x%04x\n", reg); 3076 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16; 3077 printf(" Device ID: 0x%04x\n", reg); 3078 3079 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 3080 printf(" Supported Page Sizes register: 0x%08x\n", reg); 3081 printf(" Supported Page Size:"); 3082 for (i = 0, first = true; i < 32; i++) { 3083 if (reg & __BIT(i)) { 3084 #ifdef _KERNEL 3085 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 3086 #else 3087 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 3088 HN_AUTOSCALE, 0); 3089 #endif 3090 printf("%s %s", first ? "" : ",", buf); 3091 first = false; 3092 } 3093 } 3094 printf("\n"); 3095 3096 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 3097 printf(" System Page Sizes register: 0x%08x\n", reg); 3098 printf(" Page Size: "); 3099 if (reg != 0) { 3100 int bitpos = ffs(reg) -1; 3101 3102 /* Assume only one bit is set. */ 3103 #ifdef _KERNEL 3104 format_bytes(buf, sizeof(buf), 1LL << (bitpos + 12)); 3105 #else 3106 humanize_number(buf, sizeof(buf), 1LL << (bitpos + 12), 3107 "B", HN_AUTOSCALE, 0); 3108 #endif 3109 printf("%s", buf); 3110 } else { 3111 printf("unknown"); 3112 } 3113 printf("\n"); 3114 3115 for (i = 0; i < 6; i++) { 3116 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 3117 printf(" VF BAR%d register: 0x%08x\n", i, reg); 3118 } 3119 3120 if (total_vfs > 0) { 3121 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 3122 printf(" VF Migration State Array Offset register: 0x%08x\n", 3123 reg); 3124 printf(" VF Migration State Offset: 0x%08x\n", 3125 (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 3126 i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 3127 printf(" VF Migration State BIR: "); 3128 if (i >= 0 && i <= 5) { 3129 printf("BAR%d", i); 3130 } else { 3131 printf("unknown BAR (%d)", i); 3132 } 3133 printf("\n"); 3134 } 3135 } 3136 3137 /* XXX pci_conf_print_mriov_cap */ 3138 3139 static void 3140 pci_conf_print_multicast_cap(const pcireg_t *regs, int capoff, int extcapoff) 3141 { 3142 pcireg_t reg, cap, ctl; 3143 pcireg_t regl, regh; 3144 uint64_t addr; 3145 int n; 3146 3147 printf("\n Multicast\n"); 3148 3149 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 3150 cap = reg & 0xffff; 3151 ctl = reg >> 16; 3152 printf(" Capability Register: 0x%04x\n", cap); 3153 printf(" Max Group: %u\n", 3154 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 3155 3156 /* Endpoint Only */ 3157 n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 3158 if (n > 0) 3159 printf(" Windw Size Requested: %d\n", 1 << (n - 1)); 3160 3161 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 3162 3163 printf(" Control Register: 0x%04x\n", ctl); 3164 printf(" Num Group: %u\n", 3165 (unsigned int)__SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 3166 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 3167 3168 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 3169 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 3170 printf(" Base Address Register 0: 0x%08x\n", regl); 3171 printf(" Base Address Register 1: 0x%08x\n", regh); 3172 printf(" Index Position: %u\n", 3173 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 3174 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 3175 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 3176 3177 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 3178 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 3179 printf(" Receive Register 0: 0x%08x\n", regl); 3180 printf(" Receive Register 1: 0x%08x\n", regh); 3181 3182 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 3183 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 3184 printf(" Block All Register 0: 0x%08x\n", regl); 3185 printf(" Block All Register 1: 0x%08x\n", regh); 3186 3187 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 3188 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 3189 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 3190 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 3191 3192 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 3193 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 3194 printf(" Overlay BAR 0: 0x%08x\n", regl); 3195 printf(" Overlay BAR 1: 0x%08x\n", regh); 3196 3197 n = regl & PCI_MCAST_OVERLAYL_SIZE; 3198 printf(" Overlay Size: "); 3199 if (n >= 6) 3200 printf("%d\n", n); 3201 else 3202 printf("off\n"); 3203 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 3204 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 3205 } 3206 3207 static void 3208 pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3209 { 3210 pcireg_t reg, ctl, sta; 3211 3212 printf("\n Page Request\n"); 3213 3214 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 3215 ctl = reg & 0xffff; 3216 sta = reg >> 16; 3217 printf(" Control Register: 0x%04x\n", ctl); 3218 onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E); 3219 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 3220 3221 printf(" Status Register: 0x%04x\n", sta); 3222 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 3223 onoff("Unexpected Page Request Group Index", reg, 3224 PCI_PAGE_REQ_STA_UPRGI); 3225 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 3226 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 3227 3228 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 3229 printf(" Outstanding Page Request Capacity: %u\n", reg); 3230 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 3231 printf(" Outstanding Page Request Allocation: %u\n", reg); 3232 } 3233 3234 /* XXX pci_conf_print_amd_cap */ 3235 3236 #define MEM_PBUFSIZE sizeof("999GB") 3237 3238 static void 3239 pci_conf_print_resizbar_cap(const pcireg_t *regs, int capoff, int extcapoff) 3240 { 3241 pcireg_t cap, ctl; 3242 unsigned int bars, i, n; 3243 char pbuf[MEM_PBUFSIZE]; 3244 3245 printf("\n Resizable BAR\n"); 3246 3247 /* Get Number of Resizable BARs */ 3248 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))]; 3249 bars = __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR); 3250 printf(" Number of Resizable BARs: "); 3251 if (bars <= 6) 3252 printf("%u\n", bars); 3253 else { 3254 printf("incorrect (%u)\n", bars); 3255 return; 3256 } 3257 3258 for (n = 0; n < 6; n++) { 3259 cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))]; 3260 printf(" Capability register(%u): 0x%08x\n", n, cap); 3261 if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0) 3262 continue; /* Not Used */ 3263 printf(" Acceptable BAR sizes:"); 3264 for (i = 4; i <= 23; i++) { 3265 if ((cap & (1 << i)) != 0) { 3266 humanize_number(pbuf, MEM_PBUFSIZE, 3267 (int64_t)1024 * 1024 << (i - 4), "B", 3268 #ifdef _KERNEL 3269 1); 3270 #else 3271 HN_AUTOSCALE, HN_NOSPACE); 3272 #endif 3273 printf(" %s", pbuf); 3274 } 3275 } 3276 printf("\n"); 3277 3278 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))]; 3279 printf(" Control register(%u): 0x%08x\n", n, ctl); 3280 printf(" BAR Index: %u\n", 3281 (unsigned int)__SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX)); 3282 humanize_number(pbuf, MEM_PBUFSIZE, 3283 (int64_t)1024 * 1024 3284 << __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ), 3285 "B", 3286 #ifdef _KERNEL 3287 1); 3288 #else 3289 HN_AUTOSCALE, HN_NOSPACE); 3290 #endif 3291 printf(" BAR Size: %s\n", pbuf); 3292 } 3293 } 3294 3295 static void 3296 pci_conf_print_dpa_cap(const pcireg_t *regs, int capoff, int extcapoff) 3297 { 3298 pcireg_t reg; 3299 unsigned int substmax, i; 3300 3301 printf("\n Dynamic Power Allocation\n"); 3302 3303 reg = regs[o2i(extcapoff + PCI_DPA_CAP)]; 3304 printf(" Capability register: 0x%08x\n", reg); 3305 substmax = __SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX); 3306 printf(" Substate Max: %u\n", substmax); 3307 printf(" Transition Latency Unit: "); 3308 switch (__SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) { 3309 case 0: 3310 printf("1ms\n"); 3311 break; 3312 case 1: 3313 printf("10ms\n"); 3314 break; 3315 case 2: 3316 printf("100ms\n"); 3317 break; 3318 default: 3319 printf("reserved\n"); 3320 break; 3321 } 3322 printf(" Power Allocation Scale: "); 3323 switch (__SHIFTOUT(reg, PCI_DPA_CAP_PAS)) { 3324 case 0: 3325 printf("10.0x\n"); 3326 break; 3327 case 1: 3328 printf("1.0x\n"); 3329 break; 3330 case 2: 3331 printf("0.1x\n"); 3332 break; 3333 case 3: 3334 printf("0.01x\n"); 3335 break; 3336 } 3337 printf(" Transition Latency Value 0: %u\n", 3338 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY0)); 3339 printf(" Transition Latency Value 1: %u\n", 3340 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); 3341 3342 reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; 3343 printf(" Latency Indicatior register: 0x%08x\n", reg); 3344 3345 reg = regs[o2i(extcapoff + PCI_DPA_CS)]; 3346 printf(" Status register: 0x%04x\n", reg & 0xffff); 3347 printf(" Substate Status: 0x%02x\n", 3348 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT)); 3349 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN); 3350 printf(" Control register: 0x%04x\n", reg >> 16); 3351 printf(" Substate Control: 0x%02x\n", 3352 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL)); 3353 3354 for (i = 0; i <= substmax; i++) 3355 printf(" Substate Power Allocation register %d: 0x%02x\n", 3356 i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff)); 3357 } 3358 3359 static const char * 3360 pci_conf_print_tph_req_cap_sttabloc(unsigned char val) 3361 { 3362 3363 switch (val) { 3364 case 0x0: 3365 return "Not Present"; 3366 case 0x1: 3367 return "in the TPH Requester Capability Structure"; 3368 case 0x2: 3369 return "in the MSI-X Table"; 3370 default: 3371 return "Unknown"; 3372 } 3373 } 3374 3375 static void 3376 pci_conf_print_tph_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3377 { 3378 pcireg_t reg; 3379 int size, i, j; 3380 3381 printf("\n TPH Requester Extended Capability\n"); 3382 3383 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3384 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3385 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3386 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3387 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3388 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3389 printf(" ST Table Location: %s\n", 3390 pci_conf_print_tph_req_cap_sttabloc( 3391 (unsigned char)__SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC))); 3392 size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3393 printf(" ST Table Size: %d\n", size); 3394 for (i = 0; i < size ; i += 2) { 3395 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3396 for (j = 0; j < 2 ; j++) { 3397 uint32_t entry = reg; 3398 3399 if (j != 0) 3400 entry >>= 16; 3401 entry &= 0xffff; 3402 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3403 i + j, entry); 3404 } 3405 } 3406 } 3407 3408 static void 3409 pci_conf_print_ltr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3410 { 3411 pcireg_t reg; 3412 3413 printf("\n Latency Tolerance Reporting\n"); 3414 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)] & 0xffff; 3415 printf(" Max Snoop Latency Register: 0x%04x\n", reg); 3416 printf(" Max Snoop LatencyValue: %u\n", 3417 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL)); 3418 printf(" Max Snoop LatencyScale: %uns\n", 3419 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE))); 3420 reg = regs[o2i(extcapoff + PCI_LTR_MAXNOSNOOPLAT)] >> 16; 3421 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg); 3422 printf(" Max No-Snoop LatencyValue: %u\n", 3423 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL)); 3424 printf(" Max No-Snoop LatencyScale: %uns\n", 3425 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE))); 3426 } 3427 3428 static void 3429 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int capoff, int extcapoff) 3430 { 3431 int pcie_capoff; 3432 pcireg_t reg; 3433 int i, maxlinkwidth; 3434 3435 printf("\n Secondary PCI Express Register\n"); 3436 3437 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3438 printf(" Link Control 3 register: 0x%08x\n", reg); 3439 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3440 onoff("Link Equalization Request Interrupt Enable", 3441 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3442 printf(" Enable Lower SKP OS Generation Vector:"); 3443 pci_print_pcie_linkspeedvector( 3444 __SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3445 printf("\n"); 3446 3447 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3448 printf(" Lane Error Status register: 0x%08x\n", reg); 3449 3450 /* Get Max Link Width */ 3451 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)){ 3452 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3453 maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3454 } else { 3455 printf("error: falied to get PCIe capablity\n"); 3456 return; 3457 } 3458 for (i = 0; i < maxlinkwidth; i++) { 3459 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3460 if (i % 2 != 0) 3461 reg >>= 16; 3462 else 3463 reg &= 0xffff; 3464 printf(" Equalization Control Register (Link %d): 0x%04x\n", 3465 i, reg); 3466 printf(" Downstream Port Transmit Preset: 0x%x\n", 3467 (pcireg_t)__SHIFTOUT(reg, 3468 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3469 printf(" Downstream Port Receive Hint: 0x%x\n", 3470 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3471 printf(" Upstream Port Transmit Preset: 0x%x\n", 3472 (pcireg_t)__SHIFTOUT(reg, 3473 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3474 printf(" Upstream Port Receive Hint: 0x%x\n", 3475 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3476 } 3477 } 3478 3479 /* XXX pci_conf_print_pmux_cap */ 3480 3481 static void 3482 pci_conf_print_pasid_cap(const pcireg_t *regs, int capoff, int extcapoff) 3483 { 3484 pcireg_t reg, cap, ctl; 3485 unsigned int num; 3486 3487 printf("\n Process Address Space ID\n"); 3488 3489 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3490 cap = reg & 0xffff; 3491 ctl = reg >> 16; 3492 printf(" PASID Capability Register: 0x%04x\n", cap); 3493 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3494 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3495 num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3496 printf(" Max PASID Width: %u\n", num); 3497 3498 printf(" PASID Control Register: 0x%04x\n", ctl); 3499 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3500 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3501 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3502 } 3503 3504 static void 3505 pci_conf_print_lnr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3506 { 3507 pcireg_t reg, cap, ctl; 3508 unsigned int num; 3509 3510 printf("\n LN Requester\n"); 3511 3512 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3513 cap = reg & 0xffff; 3514 ctl = reg >> 16; 3515 printf(" LNR Capability register: 0x%04x\n", cap); 3516 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 3517 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 3518 num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 3519 printf(" LNR Registration MAX: %u\n", num); 3520 3521 printf(" LNR Control register: 0x%04x\n", ctl); 3522 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 3523 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 3524 num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 3525 printf(" LNR Registration Limit: %u\n", num); 3526 } 3527 3528 /* XXX pci_conf_print_dpc_cap */ 3529 3530 static int 3531 pci_conf_l1pm_cap_tposcale(unsigned char scale) 3532 { 3533 3534 /* Return scale in us */ 3535 switch (scale) { 3536 case 0x0: 3537 return 2; 3538 case 0x1: 3539 return 10; 3540 case 0x2: 3541 return 100; 3542 default: 3543 return -1; 3544 } 3545 } 3546 3547 static void 3548 pci_conf_print_l1pm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3549 { 3550 pcireg_t reg; 3551 int scale, val; 3552 3553 printf("\n L1 PM Substates\n"); 3554 3555 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 3556 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 3557 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 3558 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 3559 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 3560 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 3561 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 3562 printf(" Port Common Mode Restore Time: %uus\n", 3563 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 3564 scale = pci_conf_l1pm_cap_tposcale( 3565 __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 3566 val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 3567 printf(" Port T_POWER_ON: "); 3568 if (scale == -1) 3569 printf("unknown\n"); 3570 else 3571 printf("%dus\n", val * scale); 3572 3573 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 3574 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 3575 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 3576 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 3577 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 3578 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 3579 printf(" Common Mode Restore Time: %uus\n", 3580 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 3581 scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 3582 val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 3583 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 3584 3585 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 3586 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 3587 scale = pci_conf_l1pm_cap_tposcale( 3588 __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 3589 val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 3590 printf(" T_POWER_ON: "); 3591 if (scale == -1) 3592 printf("unknown\n"); 3593 else 3594 printf("%dus\n", val * scale); 3595 } 3596 3597 static void 3598 pci_conf_print_ptm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3599 { 3600 pcireg_t reg; 3601 uint32_t val; 3602 3603 printf("\n Precision Time Management\n"); 3604 3605 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 3606 printf(" PTM Capability register: 0x%08x\n", reg); 3607 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 3608 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 3609 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 3610 printf(" Local Clock Granularity: "); 3611 val = __SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 3612 switch (val) { 3613 case 0: 3614 printf("Not implemented\n"); 3615 break; 3616 case 0xffff: 3617 printf("> 254ns\n"); 3618 break; 3619 default: 3620 printf("%uns\n", val); 3621 break; 3622 } 3623 3624 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 3625 printf(" PTM Control register: 0x%08x\n", reg); 3626 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 3627 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 3628 printf(" Effective Granularity: "); 3629 val = __SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 3630 switch (val) { 3631 case 0: 3632 printf("Unknown\n"); 3633 break; 3634 case 0xffff: 3635 printf("> 254ns\n"); 3636 break; 3637 default: 3638 printf("%uns\n", val); 3639 break; 3640 } 3641 } 3642 3643 /* XXX pci_conf_print_mpcie_cap */ 3644 /* XXX pci_conf_print_frsq_cap */ 3645 /* XXX pci_conf_print_rtr_cap */ 3646 /* XXX pci_conf_print_desigvndsp_cap */ 3647 /* XXX pci_conf_print_vf_resizbar_cap */ 3648 3649 #undef MS 3650 #undef SM 3651 #undef RW 3652 3653 static struct { 3654 pcireg_t cap; 3655 const char *name; 3656 void (*printfunc)(const pcireg_t *, int, int); 3657 } pci_extcaptab[] = { 3658 { 0, "reserved", 3659 NULL }, 3660 { PCI_EXTCAP_AER, "Advanced Error Reporting", 3661 pci_conf_print_aer_cap }, 3662 { PCI_EXTCAP_VC, "Virtual Channel", 3663 pci_conf_print_vc_cap }, 3664 { PCI_EXTCAP_SERNUM, "Device Serial Number", 3665 pci_conf_print_sernum_cap }, 3666 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 3667 pci_conf_print_pwrbdgt_cap }, 3668 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 3669 pci_conf_print_rclink_dcl_cap }, 3670 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 3671 NULL }, 3672 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 3673 pci_conf_print_rcec_assoc_cap }, 3674 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 3675 NULL }, 3676 { PCI_EXTCAP_VC2, "Virtual Channel", 3677 NULL }, 3678 { PCI_EXTCAP_RCRB, "RCRB Header", 3679 NULL }, 3680 { PCI_EXTCAP_VENDOR, "Vendor Unique", 3681 NULL }, 3682 { PCI_EXTCAP_CAC, "Configuration Access Correction", 3683 NULL }, 3684 { PCI_EXTCAP_ACS, "Access Control Services", 3685 pci_conf_print_acs_cap }, 3686 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 3687 pci_conf_print_ari_cap }, 3688 { PCI_EXTCAP_ATS, "Address Translation Services", 3689 pci_conf_print_ats_cap }, 3690 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 3691 pci_conf_print_sriov_cap }, 3692 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 3693 NULL }, 3694 { PCI_EXTCAP_MCAST, "Multicast", 3695 pci_conf_print_multicast_cap }, 3696 { PCI_EXTCAP_PAGE_REQ, "Page Request", 3697 pci_conf_print_page_req_cap }, 3698 { PCI_EXTCAP_AMD, "Reserved for AMD", 3699 NULL }, 3700 { PCI_EXTCAP_RESIZBAR, "Resizable BAR", 3701 pci_conf_print_resizbar_cap }, 3702 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 3703 pci_conf_print_dpa_cap }, 3704 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 3705 pci_conf_print_tph_req_cap }, 3706 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 3707 pci_conf_print_ltr_cap }, 3708 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 3709 pci_conf_print_sec_pcie_cap }, 3710 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 3711 NULL }, 3712 { PCI_EXTCAP_PASID, "Process Address Space ID", 3713 pci_conf_print_pasid_cap }, 3714 { PCI_EXTCAP_LN_REQ, "LN Requester", 3715 pci_conf_print_lnr_cap }, 3716 { PCI_EXTCAP_DPC, "Downstream Port Containment", 3717 NULL }, 3718 { PCI_EXTCAP_L1PM, "L1 PM Substates", 3719 pci_conf_print_l1pm_cap }, 3720 { PCI_EXTCAP_PTM, "Precision Time Management", 3721 pci_conf_print_ptm_cap }, 3722 { PCI_EXTCAP_MPCIE, "M-PCIe", 3723 NULL }, 3724 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 3725 NULL }, 3726 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 3727 NULL }, 3728 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 3729 NULL }, 3730 { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", 3731 NULL }, 3732 }; 3733 3734 static int 3735 pci_conf_find_extcap(const pcireg_t *regs, int capoff, unsigned int capid, 3736 int *offsetp) 3737 { 3738 int off; 3739 pcireg_t rval; 3740 3741 for (off = PCI_EXTCAPLIST_BASE; 3742 off != 0; 3743 off = PCI_EXTCAPLIST_NEXT(rval)) { 3744 rval = regs[o2i(off)]; 3745 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 3746 if (offsetp != NULL) 3747 *offsetp = off; 3748 return 1; 3749 } 3750 } 3751 return 0; 3752 } 3753 3754 static void 3755 pci_conf_print_extcaplist( 3756 #ifdef _KERNEL 3757 pci_chipset_tag_t pc, pcitag_t tag, 3758 #endif 3759 const pcireg_t *regs, int capoff) 3760 { 3761 int off; 3762 pcireg_t foundcap; 3763 pcireg_t rval; 3764 bool foundtable[__arraycount(pci_extcaptab)]; 3765 unsigned int i; 3766 3767 /* Check Extended capability structure */ 3768 off = PCI_EXTCAPLIST_BASE; 3769 rval = regs[o2i(off)]; 3770 if (rval == 0xffffffff || rval == 0) 3771 return; 3772 3773 /* Clear table */ 3774 for (i = 0; i < __arraycount(pci_extcaptab); i++) 3775 foundtable[i] = false; 3776 3777 /* Print extended capability register's offset and the type first */ 3778 for (;;) { 3779 printf(" Extended Capability Register at 0x%02x\n", off); 3780 3781 foundcap = PCI_EXTCAPLIST_CAP(rval); 3782 printf(" type: 0x%04x (", foundcap); 3783 if (foundcap < __arraycount(pci_extcaptab)) { 3784 printf("%s)\n", pci_extcaptab[foundcap].name); 3785 /* Mark as found */ 3786 foundtable[foundcap] = true; 3787 } else 3788 printf("unknown)\n"); 3789 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 3790 3791 off = PCI_EXTCAPLIST_NEXT(rval); 3792 if (off == 0) 3793 break; 3794 else if (off <= PCI_CONF_SIZE) { 3795 printf(" next pointer: 0x%03x (incorrect)\n", off); 3796 return; 3797 } 3798 rval = regs[o2i(off)]; 3799 } 3800 3801 /* 3802 * And then, print the detail of each capability registers 3803 * in capability value's order. 3804 */ 3805 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 3806 if (foundtable[i] == false) 3807 continue; 3808 3809 /* 3810 * The type was found. Search capability list again and 3811 * print all capabilities that the capabiliy type is 3812 * the same. 3813 */ 3814 if (pci_conf_find_extcap(regs, capoff, i, &off) == 0) 3815 continue; 3816 rval = regs[o2i(off)]; 3817 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 3818 || (pci_extcaptab[i].printfunc == NULL)) 3819 continue; 3820 3821 pci_extcaptab[i].printfunc(regs, capoff, off); 3822 3823 } 3824 } 3825 3826 /* Print the Secondary Status Register. */ 3827 static void 3828 pci_conf_print_ssr(pcireg_t rval) 3829 { 3830 pcireg_t devsel; 3831 3832 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 3833 onoff("66 MHz capable", rval, __BIT(5)); 3834 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 3835 onoff("Fast back-to-back capable", rval, __BIT(7)); 3836 onoff("Data parity error detected", rval, __BIT(8)); 3837 3838 printf(" DEVSEL timing: "); 3839 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 3840 switch (devsel) { 3841 case 0: 3842 printf("fast"); 3843 break; 3844 case 1: 3845 printf("medium"); 3846 break; 3847 case 2: 3848 printf("slow"); 3849 break; 3850 default: 3851 printf("unknown/reserved"); /* XXX */ 3852 break; 3853 } 3854 printf(" (0x%x)\n", devsel); 3855 3856 onoff("Signalled target abort", rval, __BIT(11)); 3857 onoff("Received target abort", rval, __BIT(12)); 3858 onoff("Received master abort", rval, __BIT(13)); 3859 onoff("Received system error", rval, __BIT(14)); 3860 onoff("Detected parity error", rval, __BIT(15)); 3861 } 3862 3863 static void 3864 pci_conf_print_type0( 3865 #ifdef _KERNEL 3866 pci_chipset_tag_t pc, pcitag_t tag, 3867 #endif 3868 const pcireg_t *regs) 3869 { 3870 int off, width; 3871 pcireg_t rval; 3872 3873 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 3874 #ifdef _KERNEL 3875 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 3876 #else 3877 width = pci_conf_print_bar(regs, off, NULL); 3878 #endif 3879 } 3880 3881 printf(" Cardbus CIS Pointer: 0x%08x\n", 3882 regs[o2i(PCI_CARDBUS_CIS_REG)]); 3883 3884 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 3885 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 3886 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 3887 3888 /* XXX */ 3889 printf(" Expansion ROM Base Address: 0x%08x\n", 3890 regs[o2i(PCI_MAPREG_ROM)]); 3891 3892 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 3893 printf(" Capability list pointer: 0x%02x\n", 3894 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 3895 else 3896 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 3897 3898 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 3899 3900 rval = regs[o2i(PCI_INTERRUPT_REG)]; 3901 printf(" Maximum Latency: 0x%02x\n", PCI_MAX_LAT(rval)); 3902 printf(" Minimum Grant: 0x%02x\n", PCI_MIN_GNT(rval)); 3903 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 3904 switch (PCI_INTERRUPT_PIN(rval)) { 3905 case PCI_INTERRUPT_PIN_NONE: 3906 printf("(none)"); 3907 break; 3908 case PCI_INTERRUPT_PIN_A: 3909 printf("(pin A)"); 3910 break; 3911 case PCI_INTERRUPT_PIN_B: 3912 printf("(pin B)"); 3913 break; 3914 case PCI_INTERRUPT_PIN_C: 3915 printf("(pin C)"); 3916 break; 3917 case PCI_INTERRUPT_PIN_D: 3918 printf("(pin D)"); 3919 break; 3920 default: 3921 printf("(? ? ?)"); 3922 break; 3923 } 3924 printf("\n"); 3925 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 3926 } 3927 3928 static void 3929 pci_conf_print_type1( 3930 #ifdef _KERNEL 3931 pci_chipset_tag_t pc, pcitag_t tag, 3932 #endif 3933 const pcireg_t *regs) 3934 { 3935 int off, width; 3936 pcireg_t rval; 3937 uint32_t base, limit; 3938 uint32_t base_h, limit_h; 3939 uint64_t pbase, plimit; 3940 int use_upper; 3941 3942 /* 3943 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 3944 * Bridge chip documentation, and may not be correct with 3945 * respect to various standards. (XXX) 3946 */ 3947 3948 for (off = 0x10; off < 0x18; off += width) { 3949 #ifdef _KERNEL 3950 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 3951 #else 3952 width = pci_conf_print_bar(regs, off, NULL); 3953 #endif 3954 } 3955 3956 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 3957 printf(" Primary bus number: 0x%02x\n", 3958 PCI_BRIDGE_BUS_PRIMARY(rval)); 3959 printf(" Secondary bus number: 0x%02x\n", 3960 PCI_BRIDGE_BUS_SECONDARY(rval)); 3961 printf(" Subordinate bus number: 0x%02x\n", 3962 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 3963 printf(" Secondary bus latency timer: 0x%02x\n", 3964 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 3965 3966 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 3967 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 3968 3969 /* I/O region */ 3970 printf(" I/O region:\n"); 3971 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 3972 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 3973 if (PCI_BRIDGE_IO_32BITS(rval)) 3974 use_upper = 1; 3975 else 3976 use_upper = 0; 3977 onoff("32bit I/O", rval, use_upper); 3978 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 3979 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 3980 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 3981 limit |= 0x00000fff; 3982 3983 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 3984 base_h = (rval >> 0) & 0xffff; 3985 limit_h = (rval >> 16) & 0xffff; 3986 printf(" base upper 16 bits register: 0x%04x\n", base_h); 3987 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 3988 3989 if (use_upper == 1) { 3990 base |= base_h << 16; 3991 limit |= limit_h << 16; 3992 } 3993 if (base < limit) { 3994 if (use_upper == 1) 3995 printf(" range: 0x%08x-0x%08x\n", base, limit); 3996 else 3997 printf(" range: 0x%04x-0x%04x\n", base, limit); 3998 } else 3999 printf(" range: not set\n"); 4000 4001 /* Non-prefetchable memory region */ 4002 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 4003 printf(" Memory region:\n"); 4004 printf(" base register: 0x%04x\n", 4005 (rval >> 0) & 0xffff); 4006 printf(" limit register: 0x%04x\n", 4007 (rval >> 16) & 0xffff); 4008 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 4009 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 4010 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 4011 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 4012 if (base < limit) 4013 printf(" range: 0x%08x-0x%08x\n", base, limit); 4014 else 4015 printf(" range: not set\n"); 4016 4017 /* Prefetchable memory region */ 4018 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 4019 printf(" Prefetchable memory region:\n"); 4020 printf(" base register: 0x%04x\n", 4021 (rval >> 0) & 0xffff); 4022 printf(" limit register: 0x%04x\n", 4023 (rval >> 16) & 0xffff); 4024 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 4025 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 4026 printf(" base upper 32 bits register: 0x%08x\n", 4027 base_h); 4028 printf(" limit upper 32 bits register: 0x%08x\n", 4029 limit_h); 4030 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 4031 use_upper = 1; 4032 else 4033 use_upper = 0; 4034 onoff("64bit memory address", rval, use_upper); 4035 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 4036 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 4037 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 4038 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 4039 if (use_upper == 1) { 4040 pbase |= (uint64_t)base_h << 32; 4041 plimit |= (uint64_t)limit_h << 32; 4042 } 4043 if (pbase < plimit) { 4044 if (use_upper == 1) 4045 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 4046 "\n", pbase, plimit); 4047 else 4048 printf(" range: 0x%08x-0x%08x\n", 4049 (uint32_t)pbase, (uint32_t)plimit); 4050 } else 4051 printf(" range: not set\n"); 4052 4053 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4054 printf(" Capability list pointer: 0x%02x\n", 4055 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4056 else 4057 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4058 4059 /* XXX */ 4060 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 4061 4062 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4063 printf(" Interrupt line: 0x%02x\n", 4064 (rval >> 0) & 0xff); 4065 printf(" Interrupt pin: 0x%02x ", 4066 (rval >> 8) & 0xff); 4067 switch ((rval >> 8) & 0xff) { 4068 case PCI_INTERRUPT_PIN_NONE: 4069 printf("(none)"); 4070 break; 4071 case PCI_INTERRUPT_PIN_A: 4072 printf("(pin A)"); 4073 break; 4074 case PCI_INTERRUPT_PIN_B: 4075 printf("(pin B)"); 4076 break; 4077 case PCI_INTERRUPT_PIN_C: 4078 printf("(pin C)"); 4079 break; 4080 case PCI_INTERRUPT_PIN_D: 4081 printf("(pin D)"); 4082 break; 4083 default: 4084 printf("(? ? ?)"); 4085 break; 4086 } 4087 printf("\n"); 4088 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 4089 & PCI_BRIDGE_CONTROL_MASK; 4090 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 4091 onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE); 4092 onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR); 4093 onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA); 4094 onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA); 4095 onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT); 4096 onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR); 4097 onoff("Fast back-to-back capable", rval,PCI_BRIDGE_CONTROL_SECFASTB2B); 4098 } 4099 4100 static void 4101 pci_conf_print_type2( 4102 #ifdef _KERNEL 4103 pci_chipset_tag_t pc, pcitag_t tag, 4104 #endif 4105 const pcireg_t *regs) 4106 { 4107 pcireg_t rval; 4108 4109 /* 4110 * XXX these need to be printed in more detail, need to be 4111 * XXX checked against specs/docs, etc. 4112 * 4113 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 4114 * controller chip documentation, and may not be correct with 4115 * respect to various standards. (XXX) 4116 */ 4117 4118 #ifdef _KERNEL 4119 pci_conf_print_bar(pc, tag, regs, 0x10, 4120 "CardBus socket/ExCA registers"); 4121 #else 4122 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 4123 #endif 4124 4125 /* Capability list pointer and secondary status register */ 4126 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 4127 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4128 printf(" Capability list pointer: 0x%02x\n", 4129 PCI_CAPLIST_PTR(rval)); 4130 else 4131 printf(" Reserved @ 0x14: 0x%04x\n", 4132 (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0))); 4133 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 4134 4135 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4136 printf(" PCI bus number: 0x%02x\n", 4137 (rval >> 0) & 0xff); 4138 printf(" CardBus bus number: 0x%02x\n", 4139 (rval >> 8) & 0xff); 4140 printf(" Subordinate bus number: 0x%02x\n", 4141 (rval >> 16) & 0xff); 4142 printf(" CardBus latency timer: 0x%02x\n", 4143 (rval >> 24) & 0xff); 4144 4145 /* XXX Print more prettily */ 4146 printf(" CardBus memory region 0:\n"); 4147 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 4148 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 4149 printf(" CardBus memory region 1:\n"); 4150 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 4151 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 4152 printf(" CardBus I/O region 0:\n"); 4153 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 4154 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 4155 printf(" CardBus I/O region 1:\n"); 4156 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 4157 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 4158 4159 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4160 printf(" Interrupt line: 0x%02x\n", 4161 (rval >> 0) & 0xff); 4162 printf(" Interrupt pin: 0x%02x ", 4163 (rval >> 8) & 0xff); 4164 switch ((rval >> 8) & 0xff) { 4165 case PCI_INTERRUPT_PIN_NONE: 4166 printf("(none)"); 4167 break; 4168 case PCI_INTERRUPT_PIN_A: 4169 printf("(pin A)"); 4170 break; 4171 case PCI_INTERRUPT_PIN_B: 4172 printf("(pin B)"); 4173 break; 4174 case PCI_INTERRUPT_PIN_C: 4175 printf("(pin C)"); 4176 break; 4177 case PCI_INTERRUPT_PIN_D: 4178 printf("(pin D)"); 4179 break; 4180 default: 4181 printf("(? ? ?)"); 4182 break; 4183 } 4184 printf("\n"); 4185 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> 16) & 0xffff; 4186 printf(" Bridge control register: 0x%04x\n", rval); 4187 onoff("Parity error response", rval, __BIT(0)); 4188 onoff("SERR# enable", rval, __BIT(1)); 4189 onoff("ISA enable", rval, __BIT(2)); 4190 onoff("VGA enable", rval, __BIT(3)); 4191 onoff("Master abort mode", rval, __BIT(5)); 4192 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 4193 onoff("Functional interrupts routed by ExCA registers", rval, 4194 __BIT(7)); 4195 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 4196 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 4197 onoff("Write posting enable", rval, __BIT(10)); 4198 4199 rval = regs[o2i(0x40)]; 4200 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4201 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4202 4203 #ifdef _KERNEL 4204 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers"); 4205 #else 4206 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 4207 #endif 4208 } 4209 4210 void 4211 pci_conf_print( 4212 #ifdef _KERNEL 4213 pci_chipset_tag_t pc, pcitag_t tag, 4214 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 4215 #else 4216 int pcifd, u_int bus, u_int dev, u_int func 4217 #endif 4218 ) 4219 { 4220 pcireg_t regs[o2i(PCI_EXTCONF_SIZE)]; 4221 int off, capoff, endoff, hdrtype; 4222 const char *type_name; 4223 #ifdef _KERNEL 4224 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 4225 #else 4226 void (*type_printfn)(const pcireg_t *); 4227 #endif 4228 4229 printf("PCI configuration registers:\n"); 4230 4231 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 4232 #ifdef _KERNEL 4233 regs[o2i(off)] = pci_conf_read(pc, tag, off); 4234 #else 4235 if (pcibus_conf_read(pcifd, bus, dev, func, off, 4236 ®s[o2i(off)]) == -1) 4237 regs[o2i(off)] = 0; 4238 #endif 4239 } 4240 4241 /* common header */ 4242 printf(" Common header:\n"); 4243 pci_conf_print_regs(regs, 0, 16); 4244 4245 printf("\n"); 4246 #ifdef _KERNEL 4247 pci_conf_print_common(pc, tag, regs); 4248 #else 4249 pci_conf_print_common(regs); 4250 #endif 4251 printf("\n"); 4252 4253 /* type-dependent header */ 4254 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 4255 switch (hdrtype) { /* XXX make a table, eventually */ 4256 case 0: 4257 /* Standard device header */ 4258 type_name = "\"normal\" device"; 4259 type_printfn = &pci_conf_print_type0; 4260 capoff = PCI_CAPLISTPTR_REG; 4261 endoff = 64; 4262 break; 4263 case 1: 4264 /* PCI-PCI bridge header */ 4265 type_name = "PCI-PCI bridge"; 4266 type_printfn = &pci_conf_print_type1; 4267 capoff = PCI_CAPLISTPTR_REG; 4268 endoff = 64; 4269 break; 4270 case 2: 4271 /* PCI-CardBus bridge header */ 4272 type_name = "PCI-CardBus bridge"; 4273 type_printfn = &pci_conf_print_type2; 4274 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 4275 endoff = 72; 4276 break; 4277 default: 4278 type_name = NULL; 4279 type_printfn = 0; 4280 capoff = -1; 4281 endoff = 64; 4282 break; 4283 } 4284 printf(" Type %d ", hdrtype); 4285 if (type_name != NULL) 4286 printf("(%s) ", type_name); 4287 printf("header:\n"); 4288 pci_conf_print_regs(regs, 16, endoff); 4289 printf("\n"); 4290 if (type_printfn) { 4291 #ifdef _KERNEL 4292 (*type_printfn)(pc, tag, regs); 4293 #else 4294 (*type_printfn)(regs); 4295 #endif 4296 } else 4297 printf(" Don't know how to pretty-print type %d header.\n", 4298 hdrtype); 4299 printf("\n"); 4300 4301 /* capability list, if present */ 4302 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4303 && (capoff > 0)) { 4304 #ifdef _KERNEL 4305 pci_conf_print_caplist(pc, tag, regs, capoff); 4306 #else 4307 pci_conf_print_caplist(regs, capoff); 4308 #endif 4309 printf("\n"); 4310 } 4311 4312 /* device-dependent header */ 4313 printf(" Device-dependent header:\n"); 4314 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 4315 printf("\n"); 4316 #ifdef _KERNEL 4317 if (printfn) 4318 (*printfn)(pc, tag, regs); 4319 else 4320 printf(" Don't know how to pretty-print device-dependent header.\n"); 4321 printf("\n"); 4322 #endif /* _KERNEL */ 4323 4324 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 4325 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 4326 return; 4327 4328 #ifdef _KERNEL 4329 pci_conf_print_extcaplist(pc, tag, regs, capoff); 4330 #else 4331 pci_conf_print_extcaplist(regs, capoff); 4332 #endif 4333 printf("\n"); 4334 4335 /* Extended Configuration Space, if present */ 4336 printf(" Extended Configuration Space:\n"); 4337 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 4338 } 4339
Indexes created Tue Sep 23 22:09:46 GMT 2025