pci_subr.c revision 1.182
1 /* $NetBSD: pci_subr.c,v 1.182 2017/05/24 06:51:27 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.182 2017/05/24 06:51:27 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdarg.h> 58 #include <stdbool.h> 59 #include <stdio.h> 60 #include <stdlib.h> 61 #include <string.h> 62 #endif 63 64 #include <dev/pci/pcireg.h> 65 #ifdef _KERNEL 66 #include <dev/pci/pcivar.h> 67 #else 68 #include <dev/pci/pci_verbose.h> 69 #include <dev/pci/pcidevs.h> 70 #include <dev/pci/pcidevs_data.h> 71 #endif 72 73 static int pci_conf_find_cap(const pcireg_t *, int, unsigned int, int *); 74 static void pci_conf_print_pcie_power(uint8_t, unsigned int); 75 76 /* 77 * Descriptions of known PCI classes and subclasses. 78 * 79 * Subclasses are described in the same way as classes, but have a 80 * NULL subclass pointer. 81 */ 82 struct pci_class { 83 const char *name; 84 u_int val; /* as wide as pci_{,sub}class_t */ 85 const struct pci_class *subclasses; 86 }; 87 88 /* 89 * Class 0x00. 90 * Before rev. 2.0. 91 */ 92 static const struct pci_class pci_subclass_prehistoric[] = { 93 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 94 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 95 { NULL, 0, NULL, }, 96 }; 97 98 /* 99 * Class 0x01. 100 * Mass storage controller 101 */ 102 103 /* ATA programming interface */ 104 static const struct pci_class pci_interface_ata[] = { 105 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 106 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 107 { NULL, 0, NULL, }, 108 }; 109 110 /* SATA programming interface */ 111 static const struct pci_class pci_interface_sata[] = { 112 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 113 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 114 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 115 { NULL, 0, NULL, }, 116 }; 117 118 /* Flash programming interface */ 119 static const struct pci_class pci_interface_nvm[] = { 120 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 121 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 122 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 123 { NULL, 0, NULL, }, 124 }; 125 126 /* Subclasses */ 127 static const struct pci_class pci_subclass_mass_storage[] = { 128 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 129 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 130 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 131 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 132 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 133 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 134 pci_interface_ata, }, 135 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 136 pci_interface_sata, }, 137 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 138 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 139 pci_interface_nvm, }, 140 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 141 { NULL, 0, NULL, }, 142 }; 143 144 /* 145 * Class 0x02. 146 * Network controller. 147 */ 148 static const struct pci_class pci_subclass_network[] = { 149 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 150 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 151 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 152 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 153 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 154 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 155 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 156 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 157 { NULL, 0, NULL, }, 158 }; 159 160 /* 161 * Class 0x03. 162 * Display controller. 163 */ 164 165 /* VGA programming interface */ 166 static const struct pci_class pci_interface_vga[] = { 167 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 168 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 169 { NULL, 0, NULL, }, 170 }; 171 /* Subclasses */ 172 static const struct pci_class pci_subclass_display[] = { 173 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 174 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 175 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 176 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 177 { NULL, 0, NULL, }, 178 }; 179 180 /* 181 * Class 0x04. 182 * Multimedia device. 183 */ 184 static const struct pci_class pci_subclass_multimedia[] = { 185 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 186 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 187 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 188 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 189 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 190 { NULL, 0, NULL, }, 191 }; 192 193 /* 194 * Class 0x05. 195 * Memory controller. 196 */ 197 static const struct pci_class pci_subclass_memory[] = { 198 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 199 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 200 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 201 { NULL, 0, NULL, }, 202 }; 203 204 /* 205 * Class 0x06. 206 * Bridge device. 207 */ 208 209 /* PCI bridge programming interface */ 210 static const struct pci_class pci_interface_pcibridge[] = { 211 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 212 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 213 { NULL, 0, NULL, }, 214 }; 215 216 /* Semi-transparent PCI-to-PCI bridge programming interface */ 217 static const struct pci_class pci_interface_stpci[] = { 218 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 219 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 220 { NULL, 0, NULL, }, 221 }; 222 223 /* Advanced Switching programming interface */ 224 static const struct pci_class pci_interface_advsw[] = { 225 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 226 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 227 { NULL, 0, NULL, }, 228 }; 229 230 /* Subclasses */ 231 static const struct pci_class pci_subclass_bridge[] = { 232 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 233 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 234 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 235 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 236 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 237 pci_interface_pcibridge, }, 238 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 239 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 240 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 241 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 242 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 243 pci_interface_stpci, }, 244 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 245 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 246 pci_interface_advsw, }, 247 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 248 { NULL, 0, NULL, }, 249 }; 250 251 /* 252 * Class 0x07. 253 * Simple communications controller. 254 */ 255 256 /* Serial controller programming interface */ 257 static const struct pci_class pci_interface_serial[] = { 258 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 259 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 260 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 261 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 262 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 263 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 264 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 265 { NULL, 0, NULL, }, 266 }; 267 268 /* Parallel controller programming interface */ 269 static const struct pci_class pci_interface_parallel[] = { 270 { "", PCI_INTERFACE_PARALLEL, NULL,}, 271 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 272 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 273 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 274 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 275 { NULL, 0, NULL,}, 276 }; 277 278 /* Modem programming interface */ 279 static const struct pci_class pci_interface_modem[] = { 280 { "", PCI_INTERFACE_MODEM, NULL,}, 281 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 282 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 283 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 284 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 285 { NULL, 0, NULL,}, 286 }; 287 288 /* Subclasses */ 289 static const struct pci_class pci_subclass_communications[] = { 290 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 291 pci_interface_serial, }, 292 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 293 pci_interface_parallel, }, 294 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 295 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 296 pci_interface_modem, }, 297 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 298 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 299 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 300 { NULL, 0, NULL,}, 301 }; 302 303 /* 304 * Class 0x08. 305 * Base system peripheral. 306 */ 307 308 /* PIC programming interface */ 309 static const struct pci_class pci_interface_pic[] = { 310 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 311 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 312 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 313 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 314 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 315 { NULL, 0, NULL, }, 316 }; 317 318 /* DMA programming interface */ 319 static const struct pci_class pci_interface_dma[] = { 320 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 321 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 322 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 323 { NULL, 0, NULL, }, 324 }; 325 326 /* Timer programming interface */ 327 static const struct pci_class pci_interface_tmr[] = { 328 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 329 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 330 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 331 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 332 { NULL, 0, NULL, }, 333 }; 334 335 /* RTC programming interface */ 336 static const struct pci_class pci_interface_rtc[] = { 337 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 338 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 339 { NULL, 0, NULL, }, 340 }; 341 342 /* Subclasses */ 343 static const struct pci_class pci_subclass_system[] = { 344 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 345 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 346 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 347 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 348 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 349 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 350 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 351 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 352 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 353 { NULL, 0, NULL, }, 354 }; 355 356 /* 357 * Class 0x09. 358 * Input device. 359 */ 360 361 /* Gameport programming interface */ 362 static const struct pci_class pci_interface_game[] = { 363 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 364 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 365 { NULL, 0, NULL, }, 366 }; 367 368 /* Subclasses */ 369 static const struct pci_class pci_subclass_input[] = { 370 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 371 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 372 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 373 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 374 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 375 pci_interface_game, }, 376 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 377 { NULL, 0, NULL, }, 378 }; 379 380 /* 381 * Class 0x0a. 382 * Docking station. 383 */ 384 static const struct pci_class pci_subclass_dock[] = { 385 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 386 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 387 { NULL, 0, NULL, }, 388 }; 389 390 /* 391 * Class 0x0b. 392 * Processor. 393 */ 394 static const struct pci_class pci_subclass_processor[] = { 395 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 396 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 397 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 398 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 399 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 400 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 401 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 402 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 403 { NULL, 0, NULL, }, 404 }; 405 406 /* 407 * Class 0x0c. 408 * Serial bus controller. 409 */ 410 411 /* IEEE1394 programming interface */ 412 static const struct pci_class pci_interface_ieee1394[] = { 413 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 414 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 415 { NULL, 0, NULL,}, 416 }; 417 418 /* USB programming interface */ 419 static const struct pci_class pci_interface_usb[] = { 420 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 421 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 422 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 423 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 424 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 425 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 426 { NULL, 0, NULL, }, 427 }; 428 429 /* IPMI programming interface */ 430 static const struct pci_class pci_interface_ipmi[] = { 431 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 432 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 433 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 434 { NULL, 0, NULL,}, 435 }; 436 437 /* Subclasses */ 438 static const struct pci_class pci_subclass_serialbus[] = { 439 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 440 pci_interface_ieee1394, }, 441 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 442 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 443 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 444 pci_interface_usb, }, 445 /* XXX Fiber Channel/_FIBRECHANNEL */ 446 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 447 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 448 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 449 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 450 pci_interface_ipmi, }, 451 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 452 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 453 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 454 { NULL, 0, NULL, }, 455 }; 456 457 /* 458 * Class 0x0d. 459 * Wireless Controller. 460 */ 461 static const struct pci_class pci_subclass_wireless[] = { 462 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 463 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 464 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 465 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 466 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 467 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 468 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 469 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 470 { NULL, 0, NULL, }, 471 }; 472 473 /* 474 * Class 0x0e. 475 * Intelligent IO controller. 476 */ 477 478 /* Intelligent IO programming interface */ 479 static const struct pci_class pci_interface_i2o[] = { 480 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 481 { NULL, 0, NULL,}, 482 }; 483 484 /* Subclasses */ 485 static const struct pci_class pci_subclass_i2o[] = { 486 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 487 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 488 { NULL, 0, NULL, }, 489 }; 490 491 /* 492 * Class 0x0f. 493 * Satellite communication controller. 494 */ 495 static const struct pci_class pci_subclass_satcom[] = { 496 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 497 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 498 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 499 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 500 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 501 { NULL, 0, NULL, }, 502 }; 503 504 /* 505 * Class 0x10. 506 * Encryption/Decryption controller. 507 */ 508 static const struct pci_class pci_subclass_crypto[] = { 509 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 510 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 511 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 512 { NULL, 0, NULL, }, 513 }; 514 515 /* 516 * Class 0x11. 517 * Data aquuisition and signal processing controller. 518 */ 519 static const struct pci_class pci_subclass_dasp[] = { 520 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 521 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 522 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 523 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 524 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 525 { NULL, 0, NULL, }, 526 }; 527 528 /* List of classes */ 529 static const struct pci_class pci_classes[] = { 530 { "prehistoric", PCI_CLASS_PREHISTORIC, 531 pci_subclass_prehistoric, }, 532 { "mass storage", PCI_CLASS_MASS_STORAGE, 533 pci_subclass_mass_storage, }, 534 { "network", PCI_CLASS_NETWORK, 535 pci_subclass_network, }, 536 { "display", PCI_CLASS_DISPLAY, 537 pci_subclass_display, }, 538 { "multimedia", PCI_CLASS_MULTIMEDIA, 539 pci_subclass_multimedia, }, 540 { "memory", PCI_CLASS_MEMORY, 541 pci_subclass_memory, }, 542 { "bridge", PCI_CLASS_BRIDGE, 543 pci_subclass_bridge, }, 544 { "communications", PCI_CLASS_COMMUNICATIONS, 545 pci_subclass_communications, }, 546 { "system", PCI_CLASS_SYSTEM, 547 pci_subclass_system, }, 548 { "input", PCI_CLASS_INPUT, 549 pci_subclass_input, }, 550 { "dock", PCI_CLASS_DOCK, 551 pci_subclass_dock, }, 552 { "processor", PCI_CLASS_PROCESSOR, 553 pci_subclass_processor, }, 554 { "serial bus", PCI_CLASS_SERIALBUS, 555 pci_subclass_serialbus, }, 556 { "wireless", PCI_CLASS_WIRELESS, 557 pci_subclass_wireless, }, 558 { "I2O", PCI_CLASS_I2O, 559 pci_subclass_i2o, }, 560 { "satellite comm", PCI_CLASS_SATCOM, 561 pci_subclass_satcom, }, 562 { "crypto", PCI_CLASS_CRYPTO, 563 pci_subclass_crypto, }, 564 { "DASP", PCI_CLASS_DASP, 565 pci_subclass_dasp, }, 566 { "processing accelerators", PCI_CLASS_ACCEL, 567 NULL, }, 568 { "non-essential instrumentation", PCI_CLASS_INSTRUMENT, 569 NULL, }, 570 { "undefined", PCI_CLASS_UNDEFINED, 571 NULL, }, 572 { NULL, 0, 573 NULL, }, 574 }; 575 576 DEV_VERBOSE_DEFINE(pci); 577 578 /* 579 * Append a formatted string to dest without writing more than len 580 * characters (including the trailing NUL character). dest and len 581 * are updated for use in subsequent calls to snappendf(). 582 * 583 * Returns 0 on success, a negative value if vnsprintf() fails, or 584 * a positive value if the dest buffer would have overflowed. 585 */ 586 587 static int __printflike(3,4) 588 snappendf(char **dest, size_t *len, const char * restrict fmt, ...) 589 { 590 va_list ap; 591 int count; 592 593 va_start(ap, fmt); 594 count = vsnprintf(*dest, *len, fmt, ap); 595 va_end(ap); 596 597 /* Let vsnprintf() errors bubble up to caller */ 598 if (count < 0 || *len == 0) 599 return count; 600 601 /* Handle overflow */ 602 if ((size_t)count >= *len) { 603 *dest += *len - 1; 604 *len = 1; 605 return 1; 606 } 607 608 /* Update dest & len to point at trailing NUL */ 609 *dest += count; 610 *len -= count; 611 612 return 0; 613 } 614 615 void 616 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 617 size_t l) 618 { 619 pci_class_t class; 620 pci_subclass_t subclass; 621 pci_interface_t interface; 622 pci_revision_t revision; 623 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 624 const struct pci_class *classp, *subclassp, *interfacep; 625 626 class = PCI_CLASS(class_reg); 627 subclass = PCI_SUBCLASS(class_reg); 628 interface = PCI_INTERFACE(class_reg); 629 revision = PCI_REVISION(class_reg); 630 631 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 632 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 633 PCI_PRODUCT(id_reg)); 634 635 classp = pci_classes; 636 while (classp->name != NULL) { 637 if (class == classp->val) 638 break; 639 classp++; 640 } 641 642 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 643 while (subclassp && subclassp->name != NULL) { 644 if (subclass == subclassp->val) 645 break; 646 subclassp++; 647 } 648 649 interfacep = (subclassp && subclassp->name != NULL) ? 650 subclassp->subclasses : NULL; 651 while (interfacep && interfacep->name != NULL) { 652 if (interface == interfacep->val) 653 break; 654 interfacep++; 655 } 656 657 (void)snappendf(&cp, &l, "%s %s", vendor, product); 658 if (showclass) { 659 (void)snappendf(&cp, &l, " ("); 660 if (classp->name == NULL) 661 (void)snappendf(&cp, &l, 662 "class 0x%02x, subclass 0x%02x", 663 class, subclass); 664 else { 665 if (subclassp == NULL || subclassp->name == NULL) 666 (void)snappendf(&cp, &l, 667 "%s, subclass 0x%02x", 668 classp->name, subclass); 669 else 670 (void)snappendf(&cp, &l, "%s %s", 671 subclassp->name, classp->name); 672 } 673 if ((interfacep == NULL) || (interfacep->name == NULL)) { 674 if (interface != 0) 675 (void)snappendf(&cp, &l, ", interface 0x%02x", 676 interface); 677 } else if (strncmp(interfacep->name, "", 1) != 0) 678 (void)snappendf(&cp, &l, ", %s", interfacep->name); 679 if (revision != 0) 680 (void)snappendf(&cp, &l, ", revision 0x%02x", revision); 681 (void)snappendf(&cp, &l, ")"); 682 } 683 } 684 685 #ifdef _KERNEL 686 void 687 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 688 const char *known, int addrev) 689 { 690 char devinfo[256]; 691 692 if (known) { 693 aprint_normal(": %s", known); 694 if (addrev) 695 aprint_normal(" (rev. 0x%02x)", 696 PCI_REVISION(pa->pa_class)); 697 aprint_normal("\n"); 698 } else { 699 pci_devinfo(pa->pa_id, pa->pa_class, 0, 700 devinfo, sizeof(devinfo)); 701 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 702 PCI_REVISION(pa->pa_class)); 703 } 704 if (naive) 705 aprint_naive(": %s\n", naive); 706 else 707 aprint_naive("\n"); 708 } 709 #endif 710 711 /* 712 * Print out most of the PCI configuration registers. Typically used 713 * in a device attach routine like this: 714 * 715 * #ifdef MYDEV_DEBUG 716 * printf("%s: ", device_xname(sc->sc_dev)); 717 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 718 * #endif 719 */ 720 721 #define i2o(i) ((i) * 4) 722 #define o2i(o) ((o) / 4) 723 #define onoff2(str, rval, bit, onstr, offstr) \ 724 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 725 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 726 727 static void 728 pci_conf_print_common( 729 #ifdef _KERNEL 730 pci_chipset_tag_t pc, pcitag_t tag, 731 #endif 732 const pcireg_t *regs) 733 { 734 pci_class_t class; 735 pci_subclass_t subclass; 736 pci_interface_t interface; 737 pci_revision_t revision; 738 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 739 const struct pci_class *classp, *subclassp, *interfacep; 740 const char *name; 741 pcireg_t rval; 742 unsigned int num; 743 744 rval = regs[o2i(PCI_CLASS_REG)]; 745 class = PCI_CLASS(rval); 746 subclass = PCI_SUBCLASS(rval); 747 interface = PCI_INTERFACE(rval); 748 revision = PCI_REVISION(rval); 749 750 rval = regs[o2i(PCI_ID_REG)]; 751 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 752 if (name) 753 printf(" Vendor Name: %s (0x%04x)\n", name, 754 PCI_VENDOR(rval)); 755 else 756 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 757 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 758 PCI_PRODUCT(rval)); 759 if (name) 760 printf(" Device Name: %s (0x%04x)\n", name, 761 PCI_PRODUCT(rval)); 762 else 763 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 764 765 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 766 767 printf(" Command register: 0x%04x\n", rval & 0xffff); 768 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 769 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 770 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 771 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 772 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 773 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 774 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 775 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 776 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 777 onoff("Fast back-to-back transactions", rval, 778 PCI_COMMAND_BACKTOBACK_ENABLE); 779 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 780 781 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 782 onoff("Immediate Readiness", rval, PCI_STATUS_IMMD_READNESS); 783 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 784 "inactive"); 785 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 786 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 787 onoff("User Definable Features (UDF) support", rval, 788 PCI_STATUS_UDF_SUPPORT); 789 onoff("Fast back-to-back capable", rval, 790 PCI_STATUS_BACKTOBACK_SUPPORT); 791 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 792 793 printf(" DEVSEL timing: "); 794 switch (rval & PCI_STATUS_DEVSEL_MASK) { 795 case PCI_STATUS_DEVSEL_FAST: 796 printf("fast"); 797 break; 798 case PCI_STATUS_DEVSEL_MEDIUM: 799 printf("medium"); 800 break; 801 case PCI_STATUS_DEVSEL_SLOW: 802 printf("slow"); 803 break; 804 default: 805 printf("unknown/reserved"); /* XXX */ 806 break; 807 } 808 printf(" (0x%x)\n", __SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK)); 809 810 onoff("Slave signaled Target Abort", rval, 811 PCI_STATUS_TARGET_TARGET_ABORT); 812 onoff("Master received Target Abort", rval, 813 PCI_STATUS_MASTER_TARGET_ABORT); 814 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 815 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 816 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 817 818 rval = regs[o2i(PCI_CLASS_REG)]; 819 for (classp = pci_classes; classp->name != NULL; classp++) { 820 if (class == classp->val) 821 break; 822 } 823 824 /* 825 * ECN: Change Root Complex Event Collector Class Code 826 * Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type 827 * in PCIe extend capability to know whether it's RCEC or IOMMU. 828 */ 829 if ((class == PCI_CLASS_SYSTEM) 830 && (subclass == PCI_SUBCLASS_SYSTEM_IOMMU)) { 831 int pcie_capoff; 832 pcireg_t reg; 833 834 if (pci_conf_find_cap(regs, PCI_CAPLISTPTR_REG, 835 PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 836 reg = regs[o2i(pcie_capoff + PCIE_XCAP)]; 837 if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_ROOT_EVNTC) 838 subclass = PCI_SUBCLASS_SYSTEM_RCEC; 839 } 840 } 841 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 842 while (subclassp && subclassp->name != NULL) { 843 if (subclass == subclassp->val) 844 break; 845 subclassp++; 846 } 847 848 interfacep = (subclassp && subclassp->name != NULL) ? 849 subclassp->subclasses : NULL; 850 while (interfacep && interfacep->name != NULL) { 851 if (interface == interfacep->val) 852 break; 853 interfacep++; 854 } 855 856 if (classp->name != NULL) 857 printf(" Class Name: %s (0x%02x)\n", classp->name, class); 858 else 859 printf(" Class ID: 0x%02x\n", class); 860 if (subclassp != NULL && subclassp->name != NULL) 861 printf(" Subclass Name: %s (0x%02x)\n", 862 subclassp->name, PCI_SUBCLASS(rval)); 863 else 864 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 865 if ((interfacep != NULL) && (interfacep->name != NULL) 866 && (strncmp(interfacep->name, "", 1) != 0)) 867 printf(" Interface Name: %s (0x%02x)\n", 868 interfacep->name, interface); 869 else 870 printf(" Interface: 0x%02x\n", interface); 871 printf(" Revision ID: 0x%02x\n", revision); 872 873 rval = regs[o2i(PCI_BHLC_REG)]; 874 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 875 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 876 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 877 PCI_HDRTYPE(rval)); 878 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 879 num = PCI_CACHELINE(rval); 880 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 881 } 882 883 static int 884 pci_conf_print_bar( 885 #ifdef _KERNEL 886 pci_chipset_tag_t pc, pcitag_t tag, 887 #endif 888 const pcireg_t *regs, int reg, const char *name) 889 { 890 int width; 891 pcireg_t rval, rval64h; 892 bool ioen, memen; 893 #ifdef _KERNEL 894 pcireg_t mask, mask64h = 0; 895 #endif 896 897 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 898 ioen = rval & PCI_COMMAND_IO_ENABLE; 899 memen = rval & PCI_COMMAND_MEM_ENABLE; 900 901 width = 4; 902 /* 903 * Section 6.2.5.1, `Address Maps', tells us that: 904 * 905 * 1) The builtin software should have already mapped the 906 * device in a reasonable way. 907 * 908 * 2) A device which wants 2^n bytes of memory will hardwire 909 * the bottom n bits of the address to 0. As recommended, 910 * we write all 1s and see what we get back. 911 */ 912 913 rval = regs[o2i(reg)]; 914 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 915 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 916 rval64h = regs[o2i(reg + 4)]; 917 width = 8; 918 } else 919 rval64h = 0; 920 921 #ifdef _KERNEL 922 if (rval != 0 && memen) { 923 int s; 924 925 /* 926 * The following sequence seems to make some devices 927 * (e.g. host bus bridges, which don't normally 928 * have their space mapped) very unhappy, to 929 * the point of crashing the system. 930 * 931 * Therefore, if the mapping register is zero to 932 * start out with, don't bother trying. 933 */ 934 s = splhigh(); 935 pci_conf_write(pc, tag, reg, 0xffffffff); 936 mask = pci_conf_read(pc, tag, reg); 937 pci_conf_write(pc, tag, reg, rval); 938 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 939 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 940 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 941 mask64h = pci_conf_read(pc, tag, reg + 4); 942 pci_conf_write(pc, tag, reg + 4, rval64h); 943 } 944 splx(s); 945 } else 946 mask = mask64h = 0; 947 #endif /* _KERNEL */ 948 949 printf(" Base address register at 0x%02x", reg); 950 if (name) 951 printf(" (%s)", name); 952 printf("\n "); 953 if (rval == 0) { 954 printf("not implemented\n"); 955 return width; 956 } 957 printf("type: "); 958 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 959 const char *type, *prefetch; 960 961 switch (PCI_MAPREG_MEM_TYPE(rval)) { 962 case PCI_MAPREG_MEM_TYPE_32BIT: 963 type = "32-bit"; 964 break; 965 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 966 type = "32-bit-1M"; 967 break; 968 case PCI_MAPREG_MEM_TYPE_64BIT: 969 type = "64-bit"; 970 break; 971 default: 972 type = "unknown (XXX)"; 973 break; 974 } 975 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 976 prefetch = ""; 977 else 978 prefetch = "non"; 979 printf("%s %sprefetchable memory\n", type, prefetch); 980 switch (PCI_MAPREG_MEM_TYPE(rval)) { 981 case PCI_MAPREG_MEM_TYPE_64BIT: 982 printf(" base: 0x%016llx", 983 PCI_MAPREG_MEM64_ADDR( 984 ((((long long) rval64h) << 32) | rval))); 985 if (!memen) 986 printf(", disabled"); 987 printf("\n"); 988 #ifdef _KERNEL 989 printf(" size: 0x%016llx\n", 990 PCI_MAPREG_MEM64_SIZE( 991 ((((long long) mask64h) << 32) | mask))); 992 #endif 993 break; 994 case PCI_MAPREG_MEM_TYPE_32BIT: 995 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 996 default: 997 printf(" base: 0x%08x", 998 PCI_MAPREG_MEM_ADDR(rval)); 999 if (!memen) 1000 printf(", disabled"); 1001 printf("\n"); 1002 #ifdef _KERNEL 1003 printf(" size: 0x%08x\n", 1004 PCI_MAPREG_MEM_SIZE(mask)); 1005 #endif 1006 break; 1007 } 1008 } else { 1009 #ifdef _KERNEL 1010 if (ioen) 1011 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 1012 #endif 1013 printf("I/O\n"); 1014 printf(" base: 0x%08x", PCI_MAPREG_IO_ADDR(rval)); 1015 if (!ioen) 1016 printf(", disabled"); 1017 printf("\n"); 1018 #ifdef _KERNEL 1019 printf(" size: 0x%08x\n", PCI_MAPREG_IO_SIZE(mask)); 1020 #endif 1021 } 1022 1023 return width; 1024 } 1025 1026 static void 1027 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 1028 { 1029 int off, needaddr, neednl; 1030 1031 needaddr = 1; 1032 neednl = 0; 1033 for (off = first; off < pastlast; off += 4) { 1034 if ((off % 16) == 0 || needaddr) { 1035 printf(" 0x%02x:", off); 1036 needaddr = 0; 1037 } 1038 printf(" 0x%08x", regs[o2i(off)]); 1039 neednl = 1; 1040 if ((off % 16) == 12) { 1041 printf("\n"); 1042 neednl = 0; 1043 } 1044 } 1045 if (neednl) 1046 printf("\n"); 1047 } 1048 1049 static const char * 1050 pci_conf_print_agp_calcycle(uint8_t cal) 1051 { 1052 1053 switch (cal) { 1054 case 0x0: 1055 return "4ms"; 1056 case 0x1: 1057 return "16ms"; 1058 case 0x2: 1059 return "64ms"; 1060 case 0x3: 1061 return "256ms"; 1062 case 0x7: 1063 return "Calibration Cycle Not Needed"; 1064 default: 1065 return "(reserved)"; 1066 } 1067 } 1068 1069 static void 1070 pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3) 1071 { 1072 if (isagp3) { 1073 /* AGP 3.0 */ 1074 if (reg & AGP_MODE_V3_RATE_4x) 1075 printf("x4"); 1076 if (reg & AGP_MODE_V3_RATE_8x) 1077 printf("x8"); 1078 } else { 1079 /* AGP 2.0 */ 1080 if (reg & AGP_MODE_V2_RATE_1x) 1081 printf("x1"); 1082 if (reg & AGP_MODE_V2_RATE_2x) 1083 printf("x2"); 1084 if (reg & AGP_MODE_V2_RATE_4x) 1085 printf("x4"); 1086 } 1087 printf("\n"); 1088 } 1089 1090 static void 1091 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1092 { 1093 pcireg_t rval; 1094 bool isagp3; 1095 1096 printf("\n AGP Capabilities Register\n"); 1097 1098 rval = regs[o2i(capoff)]; 1099 printf(" Revision: %d.%d\n", 1100 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1101 1102 rval = regs[o2i(capoff + PCI_AGP_STATUS)]; 1103 printf(" Status register: 0x%04x\n", rval); 1104 printf(" RQ: %d\n", 1105 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1106 printf(" ARQSZ: %d\n", 1107 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1108 printf(" CAL cycle: %s\n", 1109 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1110 onoff("SBA", rval, AGP_MODE_SBA); 1111 onoff("htrans#", rval, AGP_MODE_HTRANS); 1112 onoff("Over 4G", rval, AGP_MODE_4G); 1113 onoff("Fast Write", rval, AGP_MODE_FW); 1114 onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3); 1115 isagp3 = rval & AGP_MODE_MODE_3; 1116 printf(" Data Rate Support: "); 1117 pci_conf_print_agp_datarate(rval, isagp3); 1118 1119 rval = regs[o2i(capoff + PCI_AGP_COMMAND)]; 1120 printf(" Command register: 0x%08x\n", rval); 1121 printf(" PRQ: %d\n", 1122 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1123 printf(" PARQSZ: %d\n", 1124 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1125 printf(" PCAL cycle: %s\n", 1126 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1127 onoff("SBA", rval, AGP_MODE_SBA); 1128 onoff("AGP", rval, AGP_MODE_AGP); 1129 onoff("Over 4G", rval, AGP_MODE_4G); 1130 onoff("Fast Write", rval, AGP_MODE_FW); 1131 if (isagp3) { 1132 printf(" Data Rate Enable: "); 1133 /* 1134 * The Data Rate Enable bits are used only on 3.0 and the 1135 * Command register has no AGP_MODE_MODE_3 bit, so pass the 1136 * flag to print correctly. 1137 */ 1138 pci_conf_print_agp_datarate(rval, isagp3); 1139 } 1140 } 1141 1142 static const char * 1143 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1144 { 1145 1146 switch ((caps >> 6) & 7) { 1147 case 0: return "self-powered"; 1148 case 1: return "55 mA"; 1149 case 2: return "100 mA"; 1150 case 3: return "160 mA"; 1151 case 4: return "220 mA"; 1152 case 5: return "270 mA"; 1153 case 6: return "320 mA"; 1154 case 7: 1155 default: return "375 mA"; 1156 } 1157 } 1158 1159 static const char * 1160 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1161 { 1162 static const char unk[] = "unknown"; 1163 static const char *pmrev[8] = { 1164 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1165 }; 1166 if (val > 7) 1167 return unk; 1168 return pmrev[val]; 1169 } 1170 1171 static void 1172 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1173 { 1174 uint16_t caps, pmcsr; 1175 pcireg_t reg; 1176 1177 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1178 reg = regs[o2i(capoff + PCI_PMCSR)]; 1179 pmcsr = reg & 0xffff; 1180 1181 printf("\n PCI Power Management Capabilities Register\n"); 1182 1183 printf(" Capabilities register: 0x%04x\n", caps); 1184 printf(" Version: %s\n", 1185 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1186 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1187 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1188 printf(" 3.3V auxiliary current: %s\n", 1189 pci_conf_print_pcipm_cap_aux(caps)); 1190 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1191 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1192 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1193 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1194 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1195 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1196 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1197 1198 printf(" Control/status register: 0x%04x\n", pmcsr); 1199 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1200 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1201 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1202 printf(" PME# assertion: %sabled\n", 1203 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1204 printf(" Data Select: %d\n", 1205 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK)); 1206 printf(" Data Scale: %d\n", 1207 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK)); 1208 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1209 printf(" Bridge Support Extensions register: 0x%02x\n", 1210 (reg >> 16) & 0xff); 1211 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1212 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1213 printf(" Data register: 0x%02x\n", __SHIFTOUT(reg, PCI_PMCSR_DATA)); 1214 1215 } 1216 1217 /* XXX pci_conf_print_vpd_cap */ 1218 /* XXX pci_conf_print_slotid_cap */ 1219 1220 static void 1221 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1222 { 1223 uint32_t ctl, mmc, mme; 1224 1225 regs += o2i(capoff); 1226 ctl = *regs++; 1227 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1228 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1229 1230 printf("\n PCI Message Signaled Interrupt\n"); 1231 1232 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1233 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1234 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1235 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1236 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1237 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1238 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1239 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1240 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP); 1241 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN); 1242 printf(" Message Address %sregister: 0x%08x\n", 1243 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1244 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1245 printf(" Message Address %sregister: 0x%08x\n", 1246 "(upper) ", *regs++); 1247 } 1248 printf(" Message Data register: 0x%04x\n", *regs & 0xffff); 1249 regs++; 1250 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1251 printf(" Vector Mask register: 0x%08x\n", *regs++); 1252 printf(" Vector Pending register: 0x%08x\n", *regs++); 1253 } 1254 } 1255 1256 /* XXX pci_conf_print_cpci_hostwap_cap */ 1257 1258 /* 1259 * For both command register and status register. 1260 * The argument "idx" is index number (0 to 7). 1261 */ 1262 static int 1263 pcix_split_trans(unsigned int idx) 1264 { 1265 static int table[8] = { 1266 1, 2, 3, 4, 8, 12, 16, 32 1267 }; 1268 1269 if (idx >= __arraycount(table)) 1270 return -1; 1271 return table[idx]; 1272 } 1273 1274 static void 1275 pci_conf_print_pcix_cap_2ndbusmode(int num) 1276 { 1277 const char *maxfreq, *maxperiod; 1278 1279 printf(" Mode: "); 1280 if (num <= 0x07) 1281 printf("PCI-X Mode 1\n"); 1282 else if (num <= 0x0b) 1283 printf("PCI-X 266 (Mode 2)\n"); 1284 else 1285 printf("PCI-X 533 (Mode 2)\n"); 1286 1287 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1288 switch (num & 0x03) { 1289 default: 1290 case 0: 1291 maxfreq = "N/A"; 1292 maxperiod = "N/A"; 1293 break; 1294 case 1: 1295 maxfreq = "66MHz"; 1296 maxperiod = "15ns"; 1297 break; 1298 case 2: 1299 maxfreq = "100MHz"; 1300 maxperiod = "10ns"; 1301 break; 1302 case 3: 1303 maxfreq = "133MHz"; 1304 maxperiod = "7.5ns"; 1305 break; 1306 } 1307 printf(" Max Clock Freq: %s\n", maxfreq); 1308 printf(" Min Clock Period: %s\n", maxperiod); 1309 } 1310 1311 static void 1312 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1313 { 1314 pcireg_t reg; 1315 int isbridge; 1316 int i; 1317 1318 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1319 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1320 printf("\n PCI-X %s Capabilities Register\n", 1321 isbridge ? "Bridge" : "Non-bridge"); 1322 1323 reg = regs[o2i(capoff)]; 1324 if (isbridge != 0) { 1325 printf(" Secondary status register: 0x%04x\n", 1326 (reg & 0xffff0000) >> 16); 1327 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1328 onoff("133MHz capable", reg, PCIX_STATUS_133); 1329 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1330 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1331 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1332 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1333 pci_conf_print_pcix_cap_2ndbusmode( 1334 __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1335 printf(" Version: 0x%x\n", 1336 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1337 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1338 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1339 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1340 } else { 1341 printf(" Command register: 0x%04x\n", 1342 (reg & 0xffff0000) >> 16); 1343 onoff("Data Parity Error Recovery", reg, 1344 PCIX_CMD_PERR_RECOVER); 1345 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1346 printf(" Maximum Burst Read Count: %u\n", 1347 PCIX_CMD_BYTECNT(reg)); 1348 printf(" Maximum Split Transactions: %d\n", 1349 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1350 >> PCIX_CMD_SPLTRANS_SHIFT)); 1351 } 1352 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1353 printf(" %sStatus register: 0x%08x\n", 1354 isbridge ? "Bridge " : "", reg); 1355 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1356 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1357 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1358 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1359 onoff("133MHz capable", reg, PCIX_STATUS_133); 1360 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1361 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1362 if (isbridge != 0) { 1363 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1364 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1365 } else { 1366 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1367 "bridge device", "simple device"); 1368 printf(" Designed max memory read byte count: %d\n", 1369 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1370 >> PCIX_STATUS_MAXB_SHIFT)); 1371 printf(" Designed max outstanding split transaction: %d\n", 1372 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1373 >> PCIX_STATUS_MAXST_SHIFT)); 1374 printf(" MAX cumulative Read Size: %u\n", 1375 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1376 onoff("Received split completion error", reg, 1377 PCIX_STATUS_SCERR); 1378 } 1379 onoff("266MHz capable", reg, PCIX_STATUS_266); 1380 onoff("533MHz capable", reg, PCIX_STATUS_533); 1381 1382 if (isbridge == 0) 1383 return; 1384 1385 /* Only for bridge */ 1386 for (i = 0; i < 2; i++) { 1387 reg = regs[o2i(capoff + PCIX_BRIDGE_UP_STCR + (4 * i))]; 1388 printf(" %s split transaction control register: 0x%08x\n", 1389 (i == 0) ? "Upstream" : "Downstream", reg); 1390 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1391 printf(" Commitment Limit: %d\n", 1392 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1393 } 1394 } 1395 1396 /* pci_conf_print_ht_slave_cap */ 1397 /* pci_conf_print_ht_host_cap */ 1398 /* pci_conf_print_ht_switch_cap */ 1399 /* pci_conf_print_ht_intr_cap */ 1400 /* pci_conf_print_ht_revid_cap */ 1401 /* pci_conf_print_ht_unitid_cap */ 1402 /* pci_conf_print_ht_extcnf_cap */ 1403 /* pci_conf_print_ht_addrmap_cap */ 1404 /* pci_conf_print_ht_msimap_cap */ 1405 1406 static void 1407 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1408 { 1409 pcireg_t val; 1410 uint32_t lo, hi; 1411 1412 /* 1413 * Print the rest of the command register bits. Others are 1414 * printed in pci_conf_print_ht_cap(). 1415 */ 1416 val = regs[o2i(capoff + PCI_HT_CMD)]; 1417 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1418 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1419 1420 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1421 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1422 printf(" Address Low register: 0x%08x\n", lo); 1423 printf(" Address high register: 0x%08x\n", hi); 1424 printf(" Address: 0x%016" PRIx64 "\n", 1425 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1426 } 1427 1428 /* pci_conf_print_ht_droute_cap */ 1429 /* pci_conf_print_ht_vcset_cap */ 1430 /* pci_conf_print_ht_retry_cap */ 1431 /* pci_conf_print_ht_x86enc_cap */ 1432 /* pci_conf_print_ht_gen3_cap */ 1433 /* pci_conf_print_ht_fle_cap */ 1434 /* pci_conf_print_ht_pm_cap */ 1435 /* pci_conf_print_ht_hnc_cap */ 1436 1437 static const struct ht_types { 1438 pcireg_t cap; 1439 const char *name; 1440 void (*printfunc)(const pcireg_t *, int); 1441 } ht_captab[] = { 1442 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1443 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1444 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1445 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1446 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1447 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1448 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1449 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1450 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1451 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1452 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1453 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1454 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1455 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1456 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1457 {PCI_HT_CAP_PM, "Power Management", NULL }, 1458 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1459 }; 1460 1461 static void 1462 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1463 { 1464 pcireg_t val, foundcap; 1465 unsigned int off; 1466 1467 val = regs[o2i(capoff + PCI_HT_CMD)]; 1468 1469 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1470 1471 printf(" Command register: 0x%04x\n", val >> 16); 1472 foundcap = PCI_HT_CAP(val); 1473 for (off = 0; off < __arraycount(ht_captab); off++) { 1474 if (ht_captab[off].cap == foundcap) 1475 break; 1476 } 1477 printf(" Capability Type: 0x%02x ", foundcap); 1478 if (off >= __arraycount(ht_captab)) { 1479 printf("(unknown)\n"); 1480 return; 1481 } 1482 printf("(%s)\n", ht_captab[off].name); 1483 if (ht_captab[off].printfunc != NULL) 1484 ht_captab[off].printfunc(regs, capoff); 1485 } 1486 1487 static void 1488 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1489 { 1490 uint16_t caps; 1491 1492 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1493 1494 printf("\n PCI Vendor Specific Capabilities Register\n"); 1495 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1496 } 1497 1498 static void 1499 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1500 { 1501 pcireg_t val; 1502 1503 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1504 1505 printf("\n Debugport Capability Register\n"); 1506 printf(" Debug base Register: 0x%04x\n", 1507 val >> PCI_DEBUG_BASER_SHIFT); 1508 printf(" port offset: 0x%04x\n", 1509 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1510 printf(" BAR number: %u\n", 1511 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1512 } 1513 1514 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1515 /* XXX pci_conf_print_hotplug_cap */ 1516 1517 static void 1518 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1519 { 1520 pcireg_t reg; 1521 1522 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1523 1524 printf("\n Subsystem ID Capability Register\n"); 1525 printf(" Subsystem ID : 0x%08x\n", reg); 1526 } 1527 1528 /* XXX pci_conf_print_agp8_cap */ 1529 /* XXX pci_conf_print_secure_cap */ 1530 1531 static void 1532 pci_print_pcie_L0s_latency(uint32_t val) 1533 { 1534 1535 switch (val) { 1536 case 0x0: 1537 printf("Less than 64ns\n"); 1538 break; 1539 case 0x1: 1540 case 0x2: 1541 case 0x3: 1542 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1543 break; 1544 case 0x4: 1545 printf("512ns to less than 1us\n"); 1546 break; 1547 case 0x5: 1548 printf("1us to less than 2us\n"); 1549 break; 1550 case 0x6: 1551 printf("2us - 4us\n"); 1552 break; 1553 case 0x7: 1554 printf("More than 4us\n"); 1555 break; 1556 } 1557 } 1558 1559 static void 1560 pci_print_pcie_L1_latency(uint32_t val) 1561 { 1562 1563 switch (val) { 1564 case 0x0: 1565 printf("Less than 1us\n"); 1566 break; 1567 case 0x6: 1568 printf("32us - 64us\n"); 1569 break; 1570 case 0x7: 1571 printf("More than 64us\n"); 1572 break; 1573 default: 1574 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1575 break; 1576 } 1577 } 1578 1579 static void 1580 pci_print_pcie_compl_timeout(uint32_t val) 1581 { 1582 1583 switch (val) { 1584 case 0x0: 1585 printf("50us to 50ms\n"); 1586 break; 1587 case 0x5: 1588 printf("16ms to 55ms\n"); 1589 break; 1590 case 0x6: 1591 printf("65ms to 210ms\n"); 1592 break; 1593 case 0x9: 1594 printf("260ms to 900ms\n"); 1595 break; 1596 case 0xa: 1597 printf("1s to 3.5s\n"); 1598 break; 1599 default: 1600 printf("unknown %u value\n", val); 1601 break; 1602 } 1603 } 1604 1605 static const char * const pcie_linkspeeds[] = {"2.5", "2.5", "5.0", "8.0"}; 1606 1607 static void 1608 pci_print_pcie_linkspeed(pcireg_t val) 1609 { 1610 1611 if (val > __arraycount(pcie_linkspeeds)) 1612 printf("unknown value (%u)\n", val); 1613 else 1614 printf("%sGT/s\n", pcie_linkspeeds[val]); 1615 } 1616 1617 static void 1618 pci_print_pcie_linkspeedvector(pcireg_t val) 1619 { 1620 unsigned int i; 1621 1622 /* Start from 0 */ 1623 for (i = 0; i < 16; i++) 1624 if (((val >> i) & 0x01) != 0) { 1625 if (i >= __arraycount(pcie_linkspeeds)) 1626 printf(" unknown vector (0x%x)", 1 << i); 1627 else 1628 printf(" %sGT/s", pcie_linkspeeds[i]); 1629 } 1630 } 1631 1632 static void 1633 pci_print_pcie_link_deemphasis(pcireg_t val) 1634 { 1635 switch (val) { 1636 case 0: 1637 printf("-6dB"); 1638 break; 1639 case 1: 1640 printf("-3.5dB"); 1641 break; 1642 default: 1643 printf("(reserved value)"); 1644 } 1645 } 1646 1647 static void 1648 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1649 { 1650 pcireg_t reg; /* for each register */ 1651 pcireg_t val; /* for each bitfield */ 1652 bool check_link = true; 1653 bool check_slot = false; 1654 bool check_rootport = false; 1655 bool check_upstreamport = false; 1656 unsigned int pciever; 1657 unsigned int i; 1658 1659 printf("\n PCI Express Capabilities Register\n"); 1660 /* Capability Register */ 1661 reg = regs[o2i(capoff)]; 1662 printf(" Capability register: 0x%04x\n", reg >> 16); 1663 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1664 printf(" Capability version: %u\n", pciever); 1665 printf(" Device type: "); 1666 switch ((reg & 0x00f00000) >> 20) { 1667 case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */ 1668 printf("PCI Express Endpoint device\n"); 1669 check_upstreamport = true; 1670 break; 1671 case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */ 1672 printf("Legacy PCI Express Endpoint device\n"); 1673 check_upstreamport = true; 1674 break; 1675 case PCIE_XCAP_TYPE_ROOT: /* 0x4 */ 1676 printf("Root Port of PCI Express Root Complex\n"); 1677 check_slot = true; 1678 check_rootport = true; 1679 break; 1680 case PCIE_XCAP_TYPE_UP: /* 0x5 */ 1681 printf("Upstream Port of PCI Express Switch\n"); 1682 check_upstreamport = true; 1683 break; 1684 case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ 1685 printf("Downstream Port of PCI Express Switch\n"); 1686 check_slot = true; 1687 check_rootport = true; 1688 break; 1689 case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ 1690 printf("PCI Express to PCI/PCI-X Bridge\n"); 1691 check_upstreamport = true; 1692 break; 1693 case PCIE_XCAP_TYPE_PCI2PCIE: /* 0x8 */ 1694 printf("PCI/PCI-X to PCI Express Bridge\n"); 1695 /* Upstream port is not PCIe */ 1696 check_slot = true; 1697 break; 1698 case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */ 1699 printf("Root Complex Integrated Endpoint\n"); 1700 check_link = false; 1701 break; 1702 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */ 1703 printf("Root Complex Event Collector\n"); 1704 check_link = false; 1705 check_rootport = true; 1706 break; 1707 default: 1708 printf("unknown\n"); 1709 break; 1710 } 1711 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1712 printf(" Interrupt Message Number: 0x%02x\n", 1713 (unsigned int)__SHIFTOUT(reg, PCIE_XCAP_IRQ)); 1714 1715 /* Device Capability Register */ 1716 reg = regs[o2i(capoff + PCIE_DCAP)]; 1717 printf(" Device Capabilities Register: 0x%08x\n", reg); 1718 printf(" Max Payload Size Supported: %u bytes max\n", 1719 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1720 printf(" Phantom Functions Supported: "); 1721 switch (__SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) { 1722 case 0x0: 1723 printf("not available\n"); 1724 break; 1725 case 0x1: 1726 printf("MSB\n"); 1727 break; 1728 case 0x2: 1729 printf("two MSB\n"); 1730 break; 1731 case 0x3: 1732 printf("All three bits\n"); 1733 break; 1734 } 1735 printf(" Extended Tag Field Supported: %dbit\n", 1736 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1737 printf(" Endpoint L0 Acceptable Latency: "); 1738 pci_print_pcie_L0s_latency(__SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY)); 1739 printf(" Endpoint L1 Acceptable Latency: "); 1740 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY)); 1741 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1742 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1743 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1744 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1745 if (check_upstreamport) { 1746 printf(" Captured Slot Power Limit: "); 1747 pci_conf_print_pcie_power( 1748 __SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL), 1749 __SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE)); 1750 } 1751 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1752 1753 /* Device Control Register */ 1754 reg = regs[o2i(capoff + PCIE_DCSR)]; 1755 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1756 onoff("Correctable Error Reporting Enable", reg, 1757 PCIE_DCSR_ENA_COR_ERR); 1758 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1759 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1760 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1761 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1762 printf(" Max Payload Size: %d byte\n", 1763 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD)); 1764 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1765 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1766 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1767 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1768 printf(" Max Read Request Size: %d byte\n", 1769 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ)); 1770 1771 /* Device Status Register */ 1772 reg = regs[o2i(capoff + PCIE_DCSR)]; 1773 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1774 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1775 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1776 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1777 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1778 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1779 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1780 onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD); 1781 1782 if (check_link) { 1783 /* Link Capability Register */ 1784 reg = regs[o2i(capoff + PCIE_LCAP)]; 1785 printf(" Link Capabilities Register: 0x%08x\n", reg); 1786 printf(" Maximum Link Speed: "); 1787 pci_print_pcie_linkspeed(reg & PCIE_LCAP_MAX_SPEED); 1788 printf(" Maximum Link Width: x%u lanes\n", 1789 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH)); 1790 printf(" Active State PM Support: "); 1791 switch (__SHIFTOUT(reg, PCIE_LCAP_ASPM)) { 1792 case 0x0: 1793 printf("No ASPM support\n"); 1794 break; 1795 case 0x1: 1796 printf("L0s supported\n"); 1797 break; 1798 case 0x2: 1799 printf("L1 supported\n"); 1800 break; 1801 case 0x3: 1802 printf("L0s and L1 supported\n"); 1803 break; 1804 } 1805 printf(" L0 Exit Latency: "); 1806 pci_print_pcie_L0s_latency(__SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT)); 1807 printf(" L1 Exit Latency: "); 1808 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_LCAP_L1_EXIT)); 1809 printf(" Port Number: %u\n", 1810 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_PORT)); 1811 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1812 onoff("Surprise Down Error Report", reg, 1813 PCIE_LCAP_SURPRISE_DOWN); 1814 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1815 onoff("Link BW Notification Capable", reg, 1816 PCIE_LCAP_LINK_BW_NOTIFY); 1817 onoff("ASPM Optionally Compliance", reg, 1818 PCIE_LCAP_ASPM_COMPLIANCE); 1819 1820 /* Link Control Register */ 1821 reg = regs[o2i(capoff + PCIE_LCSR)]; 1822 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1823 printf(" Active State PM Control: "); 1824 switch (reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S)) { 1825 case 0: 1826 printf("disabled\n"); 1827 break; 1828 case 1: 1829 printf("L0s Entry Enabled\n"); 1830 break; 1831 case 2: 1832 printf("L1 Entry Enabled\n"); 1833 break; 1834 case 3: 1835 printf("L0s and L1 Entry Enabled\n"); 1836 break; 1837 } 1838 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1839 "128bytes", "64bytes"); 1840 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1841 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1842 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1843 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1844 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1845 onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD); 1846 onoff("Link Bandwidth Management Interrupt Enable", reg, 1847 PCIE_LCSR_LBMIE); 1848 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1849 PCIE_LCSR_LABIE); 1850 printf(" DRS Signaling Control: "); 1851 switch (__SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) { 1852 case 0: 1853 printf("not reported\n"); 1854 break; 1855 case 1: 1856 printf("Interrupt Enabled\n"); 1857 break; 1858 case 2: 1859 printf("DRS to FRS Signaling Enabled\n"); 1860 break; 1861 default: 1862 printf("reserved\n"); 1863 break; 1864 } 1865 1866 /* Link Status Register */ 1867 reg = regs[o2i(capoff + PCIE_LCSR)]; 1868 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1869 printf(" Negotiated Link Speed: "); 1870 pci_print_pcie_linkspeed(__SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 1871 printf(" Negotiated Link Width: x%u lanes\n", 1872 (unsigned int)__SHIFTOUT(reg, PCIE_LCSR_NLW)); 1873 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1874 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1875 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1876 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1877 onoff("Link Bandwidth Management Status", reg, 1878 PCIE_LCSR_LINK_BW_MGMT); 1879 onoff("Link Autonomous Bandwidth Status", reg, 1880 PCIE_LCSR_LINK_AUTO_BW); 1881 } 1882 1883 if (check_slot == true) { 1884 /* Slot Capability Register */ 1885 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1886 printf(" Slot Capability Register: 0x%08x\n", reg); 1887 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1888 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1889 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1890 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1891 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1892 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1893 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1894 printf(" Slot Power Limit Value: "); 1895 pci_conf_print_pcie_power(__SHIFTOUT(reg, PCIE_SLCAP_SPLV), 1896 __SHIFTOUT(reg, PCIE_SLCAP_SPLS)); 1897 onoff("Electromechanical Interlock Present", reg, 1898 PCIE_SLCAP_EIP); 1899 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1900 printf(" Physical Slot Number: %d\n", 1901 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1902 1903 /* Slot Control Register */ 1904 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1905 printf(" Slot Control Register: 0x%04x\n", reg & 0xffff); 1906 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1907 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1908 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1909 onoff("Presence Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1910 onoff("Command Completed Interrupt Enabled", reg, 1911 PCIE_SLCSR_CCE); 1912 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1913 printf(" Attention Indicator Control: "); 1914 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1915 case 0x0: 1916 printf("reserved\n"); 1917 break; 1918 case PCIE_SLCSR_IND_ON: 1919 printf("on\n"); 1920 break; 1921 case PCIE_SLCSR_IND_BLINK: 1922 printf("blink\n"); 1923 break; 1924 case PCIE_SLCSR_IND_OFF: 1925 printf("off\n"); 1926 break; 1927 } 1928 printf(" Power Indicator Control: "); 1929 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1930 case 0x0: 1931 printf("reserved\n"); 1932 break; 1933 case PCIE_SLCSR_IND_ON: 1934 printf("on\n"); 1935 break; 1936 case PCIE_SLCSR_IND_BLINK: 1937 printf("blink\n"); 1938 break; 1939 case PCIE_SLCSR_IND_OFF: 1940 printf("off\n"); 1941 break; 1942 } 1943 printf(" Power Controller Control: Power %s\n", 1944 reg & PCIE_SLCSR_PCC ? "off" : "on"); 1945 onoff("Electromechanical Interlock Control", 1946 reg, PCIE_SLCSR_EIC); 1947 onoff("Data Link Layer State Changed Enable", reg, 1948 PCIE_SLCSR_DLLSCE); 1949 onoff("Auto Slot Power Limit Disable", reg, 1950 PCIE_SLCSR_AUTOSPLDIS); 1951 1952 /* Slot Status Register */ 1953 printf(" Slot Status Register: 0x%04x\n", reg >> 16); 1954 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1955 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1956 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1957 onoff("Presence Detect Changed", reg, PCIE_SLCSR_PDC); 1958 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1959 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1960 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1961 onoff("Electromechanical Interlock engaged", reg, 1962 PCIE_SLCSR_EIS); 1963 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1964 } 1965 1966 if (check_rootport == true) { 1967 /* Root Control Register */ 1968 reg = regs[o2i(capoff + PCIE_RCR)]; 1969 printf(" Root Control Register: 0x%04x\n", reg & 0xffff); 1970 onoff("SERR on Correctable Error Enable", reg, 1971 PCIE_RCR_SERR_CER); 1972 onoff("SERR on Non-Fatal Error Enable", reg, 1973 PCIE_RCR_SERR_NFER); 1974 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1975 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1976 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1977 1978 /* Root Capability Register */ 1979 printf(" Root Capability Register: 0x%04x\n", 1980 reg >> 16); 1981 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 1982 1983 /* Root Status Register */ 1984 reg = regs[o2i(capoff + PCIE_RSR)]; 1985 printf(" Root Status Register: 0x%08x\n", reg); 1986 printf(" PME Requester ID: 0x%04x\n", 1987 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1988 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1989 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1990 } 1991 1992 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1993 if (pciever < 2) 1994 return; 1995 1996 /* Device Capabilities 2 */ 1997 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1998 printf(" Device Capabilities 2: 0x%08x\n", reg); 1999 printf(" Completion Timeout Ranges Supported: "); 2000 val = reg & PCIE_DCAP2_COMPT_RANGE; 2001 switch (val) { 2002 case 0: 2003 printf("not supported\n"); 2004 break; 2005 default: 2006 for (i = 0; i <= 3; i++) { 2007 if (((val >> i) & 0x01) != 0) 2008 printf("%c", 'A' + i); 2009 } 2010 printf("\n"); 2011 } 2012 onoff("Completion Timeout Disable Supported", reg, 2013 PCIE_DCAP2_COMPT_DIS); 2014 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 2015 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 2016 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 2017 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 2018 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 2019 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 2020 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 2021 printf(" TPH Completer Supported: "); 2022 switch (__SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) { 2023 case 0: 2024 printf("Not supported\n"); 2025 break; 2026 case 1: 2027 printf("TPH\n"); 2028 break; 2029 case 3: 2030 printf("TPH and Extended TPH\n"); 2031 break; 2032 default: 2033 printf("(reserved value)\n"); 2034 break; 2035 2036 } 2037 printf(" LN System CLS: "); 2038 switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 2039 case 0x0: 2040 printf("Not supported or not in effect\n"); 2041 break; 2042 case 0x1: 2043 printf("64byte cachelines in effect\n"); 2044 break; 2045 case 0x2: 2046 printf("128byte cachelines in effect\n"); 2047 break; 2048 case 0x3: 2049 printf("Reserved\n"); 2050 break; 2051 } 2052 printf(" OBFF Supported: "); 2053 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 2054 case 0x0: 2055 printf("Not supported\n"); 2056 break; 2057 case 0x1: 2058 printf("Message only\n"); 2059 break; 2060 case 0x2: 2061 printf("WAKE# only\n"); 2062 break; 2063 case 0x3: 2064 printf("Both\n"); 2065 break; 2066 } 2067 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 2068 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 2069 val = __SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP); 2070 printf(" Max End-End TLP Prefixes: %u\n", (val == 0) ? 4 : val); 2071 printf(" Emergency Power Reduction Supported: "); 2072 switch (__SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) { 2073 case 0x0: 2074 printf("Not supported\n"); 2075 break; 2076 case 0x1: 2077 printf("Device Specific mechanism\n"); 2078 break; 2079 case 0x2: 2080 printf("Form Factor spec or Device Specific mechanism\n"); 2081 break; 2082 case 0x3: 2083 printf("Reserved\n"); 2084 break; 2085 } 2086 onoff("Emergency Power Reduction Initialization Required", reg, 2087 PCIE_DCAP2_EMGPWRRED_INI); 2088 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 2089 2090 /* Device Control 2 */ 2091 reg = regs[o2i(capoff + PCIE_DCSR2)]; 2092 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 2093 printf(" Completion Timeout Value: "); 2094 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 2095 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 2096 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 2097 onoff("AtomicOp Requester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 2098 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 2099 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 2100 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 2101 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 2102 onoff("Emergency Power Reduction Request", reg, 2103 PCIE_DCSR2_EMGPWRRED_REQ); 2104 printf(" OBFF: "); 2105 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 2106 case 0x0: 2107 printf("Disabled\n"); 2108 break; 2109 case 0x1: 2110 printf("Enabled with Message Signaling Variation A\n"); 2111 break; 2112 case 0x2: 2113 printf("Enabled with Message Signaling Variation B\n"); 2114 break; 2115 case 0x3: 2116 printf("Enabled using WAKE# signaling\n"); 2117 break; 2118 } 2119 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 2120 2121 if (check_link) { 2122 bool drs_supported = false; 2123 2124 /* Link Capability 2 */ 2125 reg = regs[o2i(capoff + PCIE_LCAP2)]; 2126 /* If the vector is 0, LCAP2 is not implemented */ 2127 if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) { 2128 printf(" Link Capabilities 2: 0x%08x\n", reg); 2129 printf(" Supported Link Speeds Vector:"); 2130 pci_print_pcie_linkspeedvector( 2131 __SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 2132 printf("\n"); 2133 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 2134 printf(" " 2135 "Lower SKP OS Generation Supported Speed Vector:"); 2136 pci_print_pcie_linkspeedvector( 2137 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 2138 printf("\n"); 2139 printf(" " 2140 "Lower SKP OS Reception Supported Speed Vector:"); 2141 pci_print_pcie_linkspeedvector( 2142 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 2143 printf("\n"); 2144 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 2145 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 2146 } 2147 2148 /* Link Control 2 */ 2149 reg = regs[o2i(capoff + PCIE_LCSR2)]; 2150 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 2151 printf(" Target Link Speed: "); 2152 pci_print_pcie_linkspeed(__SHIFTOUT(reg, 2153 PCIE_LCSR2_TGT_LSPEED)); 2154 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 2155 onoff("HW Autonomous Speed Disabled", reg, 2156 PCIE_LCSR2_HW_AS_DIS); 2157 printf(" Selectable De-emphasis: "); 2158 pci_print_pcie_link_deemphasis( 2159 __SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP)); 2160 printf("\n"); 2161 printf(" Transmit Margin: %u\n", 2162 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 2163 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 2164 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 2165 printf(" Compliance Present/De-emphasis: "); 2166 pci_print_pcie_link_deemphasis( 2167 __SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP)); 2168 printf("\n"); 2169 2170 /* Link Status 2 */ 2171 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 2172 printf(" Current De-emphasis Level: "); 2173 pci_print_pcie_link_deemphasis( 2174 __SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL)); 2175 printf("\n"); 2176 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 2177 onoff("Equalization Phase 1 Successful", reg, 2178 PCIE_LCSR2_EQP1_SUC); 2179 onoff("Equalization Phase 2 Successful", reg, 2180 PCIE_LCSR2_EQP2_SUC); 2181 onoff("Equalization Phase 3 Successful", reg, 2182 PCIE_LCSR2_EQP3_SUC); 2183 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 2184 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 2185 if (drs_supported) { 2186 printf(" Downstream Component Presence: "); 2187 switch (__SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 2188 case PCIE_DSCOMPN_DOWN_NOTDETERM: 2189 printf("Link Down - Presence Not" 2190 " Determined\n"); 2191 break; 2192 case PCIE_DSCOMPN_DOWN_NOTPRES: 2193 printf("Link Down - Component Not Present\n"); 2194 break; 2195 case PCIE_DSCOMPN_DOWN_PRES: 2196 printf("Link Down - Component Present\n"); 2197 break; 2198 case PCIE_DSCOMPN_UP_PRES: 2199 printf("Link Up - Component Present\n"); 2200 break; 2201 case PCIE_DSCOMPN_UP_PRES_DRS: 2202 printf("Link Up - Component Present and DRS" 2203 " received\n"); 2204 break; 2205 default: 2206 printf("reserved\n"); 2207 break; 2208 } 2209 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 2210 } 2211 } 2212 2213 /* Slot Capability 2 */ 2214 /* Slot Control 2 */ 2215 /* Slot Status 2 */ 2216 } 2217 2218 static void 2219 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 2220 { 2221 pcireg_t reg; 2222 2223 printf("\n MSI-X Capability Register\n"); 2224 2225 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2226 printf(" Message Control register: 0x%04x\n", 2227 (reg >> 16) & 0xff); 2228 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 2229 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 2230 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 2231 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 2232 printf(" Table offset register: 0x%08x\n", reg); 2233 printf(" Table offset: 0x%08x\n", 2234 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 2235 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 2236 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 2237 printf(" Pending bit array register: 0x%08x\n", reg); 2238 printf(" Pending bit array offset: 0x%08x\n", 2239 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2240 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2241 } 2242 2243 static void 2244 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2245 { 2246 pcireg_t reg; 2247 2248 printf("\n Serial ATA Capability Register\n"); 2249 2250 reg = regs[o2i(capoff + PCI_SATA_REV)]; 2251 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2252 printf(" Revision: %u.%u\n", 2253 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2254 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2255 2256 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2257 2258 printf(" BAR Register: 0x%08x\n", reg); 2259 printf(" Register location: "); 2260 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2261 printf("in config space\n"); 2262 else { 2263 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2264 printf(" BAR offset: 0x%08x\n", 2265 (pcireg_t)__SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2266 } 2267 } 2268 2269 static void 2270 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2271 { 2272 pcireg_t reg; 2273 2274 printf("\n Advanced Features Capability Register\n"); 2275 2276 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2277 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2278 printf(" AF Structure Length: 0x%02x\n", 2279 (pcireg_t)__SHIFTOUT(reg, PCI_AF_LENGTH)); 2280 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2281 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2282 reg = regs[o2i(capoff + PCI_AFCSR)]; 2283 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2284 /* 2285 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2286 * and it's always 0 on read 2287 */ 2288 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2289 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2290 } 2291 2292 /* XXX pci_conf_print_ea_cap */ 2293 /* XXX pci_conf_print_fpb_cap */ 2294 2295 static struct { 2296 pcireg_t cap; 2297 const char *name; 2298 void (*printfunc)(const pcireg_t *, int); 2299 } pci_captab[] = { 2300 { PCI_CAP_RESERVED0, "reserved", NULL }, 2301 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2302 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2303 { PCI_CAP_VPD, "VPD", NULL }, 2304 { PCI_CAP_SLOTID, "SlotID", NULL }, 2305 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2306 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2307 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2308 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2309 { PCI_CAP_VENDSPEC, "Vendor-specific", 2310 pci_conf_print_vendspec_cap }, 2311 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2312 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2313 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2314 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2315 pci_conf_print_subsystem_cap }, 2316 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2317 { PCI_CAP_SECURE, "Secure Device", NULL }, 2318 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2319 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2320 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2321 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2322 { PCI_CAP_EA, "Enhanced Allocation", NULL }, 2323 { PCI_CAP_FPB, "Flattening Portal Bridge", NULL } 2324 }; 2325 2326 static int 2327 pci_conf_find_cap(const pcireg_t *regs, int capoff, unsigned int capid, 2328 int *offsetp) 2329 { 2330 pcireg_t rval; 2331 int off; 2332 2333 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2334 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2335 rval = regs[o2i(off)]; 2336 if (capid == PCI_CAPLIST_CAP(rval)) { 2337 if (offsetp != NULL) 2338 *offsetp = off; 2339 return 1; 2340 } 2341 } 2342 return 0; 2343 } 2344 2345 static void 2346 pci_conf_print_caplist( 2347 #ifdef _KERNEL 2348 pci_chipset_tag_t pc, pcitag_t tag, 2349 #endif 2350 const pcireg_t *regs, int capoff) 2351 { 2352 int off; 2353 pcireg_t foundcap; 2354 pcireg_t rval; 2355 bool foundtable[__arraycount(pci_captab)]; 2356 unsigned int i; 2357 2358 /* Clear table */ 2359 for (i = 0; i < __arraycount(pci_captab); i++) 2360 foundtable[i] = false; 2361 2362 /* Print capability register's offset and the type first */ 2363 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2364 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2365 rval = regs[o2i(off)]; 2366 printf(" Capability register at 0x%02x\n", off); 2367 2368 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2369 foundcap = PCI_CAPLIST_CAP(rval); 2370 if (foundcap < __arraycount(pci_captab)) { 2371 printf("%s)\n", pci_captab[foundcap].name); 2372 /* Mark as found */ 2373 foundtable[foundcap] = true; 2374 } else 2375 printf("unknown)\n"); 2376 } 2377 2378 /* 2379 * And then, print the detail of each capability registers 2380 * in capability value's order. 2381 */ 2382 for (i = 0; i < __arraycount(pci_captab); i++) { 2383 if (foundtable[i] == false) 2384 continue; 2385 2386 /* 2387 * The type was found. Search capability list again and 2388 * print all capabilities that the capabiliy type is 2389 * the same. This is required because some capabilities 2390 * appear multiple times (e.g. HyperTransport capability). 2391 */ 2392 #if 0 2393 if (pci_conf_find_cap(regs, capoff, i, &off)) { 2394 rval = regs[o2i(off)]; 2395 if (pci_captab[i].printfunc != NULL) 2396 pci_captab[i].printfunc(regs, off); 2397 } 2398 #else 2399 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2400 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2401 rval = regs[o2i(off)]; 2402 if ((PCI_CAPLIST_CAP(rval) == i) 2403 && (pci_captab[i].printfunc != NULL)) 2404 pci_captab[i].printfunc(regs, off); 2405 } 2406 #endif 2407 } 2408 } 2409 2410 /* Extended Capability */ 2411 2412 static void 2413 pci_conf_print_aer_cap_uc(pcireg_t reg) 2414 { 2415 2416 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2417 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2418 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2419 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2420 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2421 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2422 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2423 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2424 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2425 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2426 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2427 onoff("Unsupported Request Error", reg, 2428 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2429 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2430 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2431 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2432 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2433 onoff("TLP Prefix Blocked Error", reg, 2434 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2435 onoff("Poisoned TLP Egress Blocked", reg, 2436 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2437 } 2438 2439 static void 2440 pci_conf_print_aer_cap_cor(pcireg_t reg) 2441 { 2442 2443 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2444 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2445 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2446 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2447 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2448 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2449 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2450 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2451 } 2452 2453 static void 2454 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2455 { 2456 2457 printf(" First Error Pointer: 0x%04x\n", 2458 (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2459 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2460 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2461 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2462 onoff("ECRC Check Enable", reg, PCI_AER_ECRC_CHECK_ENABLE); 2463 onoff("Multiple Header Recording Capable", reg, 2464 PCI_AER_MULT_HDR_CAPABLE); 2465 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2466 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2467 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2468 2469 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2470 if (!tlp_prefix_log) 2471 return; 2472 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2473 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2474 } 2475 2476 static void 2477 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2478 { 2479 2480 onoff("Correctable Error Reporting Enable", reg, 2481 PCI_AER_ROOTERR_COR_ENABLE); 2482 onoff("Non-Fatal Error Reporting Enable", reg, 2483 PCI_AER_ROOTERR_NF_ENABLE); 2484 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2485 } 2486 2487 static void 2488 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2489 { 2490 2491 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2492 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2493 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2494 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2495 PCI_AER_ROOTERR_MULTI_UC_ERR); 2496 onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL); 2497 onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR); 2498 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2499 printf(" Advanced Error Interrupt Message Number: 0x%02x\n", 2500 (unsigned int)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2501 } 2502 2503 static void 2504 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2505 { 2506 2507 printf(" Correctable Source ID: 0x%04x\n", 2508 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2509 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2510 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2511 } 2512 2513 static void 2514 pci_conf_print_aer_cap(const pcireg_t *regs, int capoff, int extcapoff) 2515 { 2516 pcireg_t reg; 2517 int pcie_capoff; 2518 int pcie_devtype = -1; 2519 bool tlp_prefix_log = false; 2520 2521 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2522 reg = regs[o2i(pcie_capoff)]; 2523 pcie_devtype = PCIE_XCAP_TYPE(reg); 2524 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2525 if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2526 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2527 /* End-End TLP Prefix Supported */ 2528 if (reg & PCIE_DCAP2_EETLP_PREF) { 2529 tlp_prefix_log = true; 2530 } 2531 } 2532 } 2533 2534 printf("\n Advanced Error Reporting Register\n"); 2535 2536 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2537 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2538 pci_conf_print_aer_cap_uc(reg); 2539 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2540 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2541 pci_conf_print_aer_cap_uc(reg); 2542 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2543 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2544 pci_conf_print_aer_cap_uc(reg); 2545 2546 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2547 printf(" Correctable Error Status register: 0x%08x\n", reg); 2548 pci_conf_print_aer_cap_cor(reg); 2549 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2550 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2551 pci_conf_print_aer_cap_cor(reg); 2552 2553 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2554 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2555 reg); 2556 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2557 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2558 printf(" Header Log register:\n"); 2559 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2560 extcapoff + PCI_AER_ROOTERR_CMD); 2561 2562 switch (pcie_devtype) { 2563 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2564 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2565 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2566 printf(" Root Error Command register: 0x%08x\n", reg); 2567 pci_conf_print_aer_cap_rooterr_cmd(reg); 2568 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2569 printf(" Root Error Status register: 0x%08x\n", reg); 2570 pci_conf_print_aer_cap_rooterr_status(reg); 2571 2572 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2573 printf(" Error Source Identification: 0x%04x\n", reg); 2574 pci_conf_print_aer_cap_errsrc_id(reg); 2575 break; 2576 } 2577 2578 if (tlp_prefix_log) { 2579 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2580 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2581 } 2582 } 2583 2584 static void 2585 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2586 pcireg_t parbsel, int parbsize) 2587 { 2588 pcireg_t reg; 2589 int num = 16 << parbsel; 2590 int num_per_reg = sizeof(pcireg_t) / parbsize; 2591 int i, j; 2592 2593 /* First, dump the table */ 2594 for (i = 0; i < num; i += num_per_reg) { 2595 reg = regs[o2i(off + i / num_per_reg)]; 2596 printf(" %s Arbitration Table: 0x%08x\n", name, reg); 2597 } 2598 /* And then, decode each entry */ 2599 for (i = 0; i < num; i += num_per_reg) { 2600 reg = regs[o2i(off + i / num_per_reg)]; 2601 for (j = 0; j < num_per_reg; j++) 2602 printf(" Phase[%d]: %d\n", j, reg); 2603 } 2604 } 2605 2606 static void 2607 pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2608 { 2609 pcireg_t reg, n; 2610 int parbtab, parbsize; 2611 pcireg_t parbsel; 2612 int varbtab, varbsize; 2613 pcireg_t varbsel; 2614 int i, count; 2615 2616 printf("\n Virtual Channel Register\n"); 2617 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2618 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2619 count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2620 printf(" Extended VC Count: %d\n", count); 2621 n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2622 printf(" Low Priority Extended VC Count: %u\n", n); 2623 n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2624 printf(" Reference Clock: %s\n", 2625 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 2626 parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2627 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2628 2629 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2630 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2631 onoff("Hardware fixed arbitration scheme", 2632 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2633 onoff("WRR arbitration with 32 phases", 2634 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2635 onoff("WRR arbitration with 64 phases", 2636 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2637 onoff("WRR arbitration with 128 phases", 2638 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2639 varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2640 printf(" VC Arbitration Table Offset: 0x%x\n", varbtab); 2641 2642 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2643 printf(" Port VC Control register: 0x%04x\n", reg); 2644 varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2645 printf(" VC Arbitration Select: 0x%x\n", varbsel); 2646 2647 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2648 printf(" Port VC Status register: 0x%04x\n", reg); 2649 onoff("VC Arbitration Table Status", 2650 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 2651 2652 for (i = 0; i < count + 1; i++) { 2653 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 2654 printf(" VC number %d\n", i); 2655 printf(" VC Resource Capability Register: 0x%08x\n", reg); 2656 onoff(" Non-configurable Hardware fixed arbitration scheme", 2657 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 2658 onoff(" WRR arbitration with 32 phases", 2659 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 2660 onoff(" WRR arbitration with 64 phases", 2661 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 2662 onoff(" WRR arbitration with 128 phases", 2663 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 2664 onoff(" Time-based WRR arbitration with 128 phases", 2665 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 2666 onoff(" WRR arbitration with 256 phases", 2667 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 2668 onoff(" Advanced Packet Switching", 2669 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 2670 onoff(" Reject Snoop Transaction", 2671 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 2672 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 2673 printf(" Maximum Time Slots: %d\n", n); 2674 parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S; 2675 printf(" Port Arbitration Table offset: 0x%02x\n", 2676 parbtab); 2677 2678 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 2679 printf(" VC Resource Control Register: 0x%08x\n", reg); 2680 printf(" TC/VC Map: 0x%02x\n", 2681 (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 2682 /* 2683 * The load Port Arbitration Table bit is used to update 2684 * the Port Arbitration logic and it's always 0 on read, so 2685 * we don't print it. 2686 */ 2687 parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 2688 printf(" Port Arbitration Select: 0x%x\n", parbsel); 2689 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 2690 printf(" VC ID: %d\n", n); 2691 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 2692 2693 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 2694 printf(" VC Resource Status Register: 0x%08x\n", reg); 2695 onoff(" Port Arbitration Table Status", 2696 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 2697 onoff(" VC Negotiation Pending", 2698 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 2699 2700 if ((parbtab != 0) && (parbsel != 0)) 2701 pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab, 2702 "Port", parbsel, parbsize); 2703 } 2704 2705 varbsize = 8; 2706 if ((varbtab != 0) && (varbsel != 0)) 2707 pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab, 2708 " VC", varbsel, varbsize); 2709 } 2710 2711 /* 2712 * Print Power limit. This encoding is the same among the following registers: 2713 * - The Captured Slot Power Limit in the PCIe Device Capability Register. 2714 * - The Slot Power Limit in the PCIe Slot Capability Register. 2715 * - The Base Power in the Data register of Power Budgeting capability. 2716 */ 2717 static void 2718 pci_conf_print_pcie_power(uint8_t base, unsigned int scale) 2719 { 2720 unsigned int sdiv = 1; 2721 2722 if ((scale == 0) && (base > 0xef)) { 2723 const char *s; 2724 2725 switch (base) { 2726 case 0xf0: 2727 s = "239W < x <= 250W"; 2728 break; 2729 case 0xf1: 2730 s = "250W < x <= 275W"; 2731 break; 2732 case 0xf2: 2733 s = "275W < x <= 300W"; 2734 break; 2735 default: 2736 s = "reserved for above 300W"; 2737 break; 2738 } 2739 printf("%s\n", s); 2740 } 2741 2742 for (unsigned int i = scale; i > 0; i--) 2743 sdiv *= 10; 2744 2745 printf("%u", base / sdiv); 2746 2747 if (scale != 0) { 2748 printf(".%u", base % sdiv); 2749 } 2750 printf ("W\n"); 2751 return; 2752 } 2753 2754 static const char * 2755 pci_conf_print_pwrbdgt_type(uint8_t reg) 2756 { 2757 2758 switch (reg) { 2759 case 0x00: 2760 return "PME Aux"; 2761 case 0x01: 2762 return "Auxilary"; 2763 case 0x02: 2764 return "Idle"; 2765 case 0x03: 2766 return "Sustained"; 2767 case 0x04: 2768 return "Sustained (Emergency Power Reduction)"; 2769 case 0x05: 2770 return "Maximum (Emergency Power Reduction)"; 2771 case 0x07: 2772 return "Maximum"; 2773 default: 2774 return "Unknown"; 2775 } 2776 } 2777 2778 static const char * 2779 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 2780 { 2781 2782 switch (reg) { 2783 case 0x00: 2784 return "Power(12V)"; 2785 case 0x01: 2786 return "Power(3.3V)"; 2787 case 0x02: 2788 return "Power(1.5V or 1.8V)"; 2789 case 0x07: 2790 return "Thermal"; 2791 default: 2792 return "Unknown"; 2793 } 2794 } 2795 2796 static void 2797 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff) 2798 { 2799 pcireg_t reg; 2800 2801 printf("\n Power Budgeting\n"); 2802 2803 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 2804 printf(" Data Select register: 0x%08x\n", reg); 2805 2806 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 2807 printf(" Data register: 0x%08x\n", reg); 2808 printf(" Base Power: "); 2809 pci_conf_print_pcie_power( 2810 __SHIFTOUT(reg, PCI_PWRBDGT_DATA_BASEPWR), 2811 __SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE)); 2812 printf(" PM Sub State: 0x%hhx\n", 2813 (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 2814 printf(" PM State: D%u\n", 2815 (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 2816 printf(" Type: %s\n", 2817 pci_conf_print_pwrbdgt_type( 2818 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 2819 printf(" Power Rail: %s\n", 2820 pci_conf_print_pwrbdgt_pwrrail( 2821 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 2822 2823 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 2824 printf(" Power Budget Capability register: 0x%08x\n", reg); 2825 onoff("System Allocated", 2826 reg, PCI_PWRBDGT_CAP_SYSALLOC); 2827 } 2828 2829 static const char * 2830 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 2831 { 2832 2833 switch (type) { 2834 case 0x00: 2835 return "Configuration Space Element"; 2836 case 0x01: 2837 return "System Egress Port or internal sink (memory)"; 2838 case 0x02: 2839 return "Internal Root Complex Link"; 2840 default: 2841 return "Unknown"; 2842 } 2843 } 2844 2845 static void 2846 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int capoff, int extcapoff) 2847 { 2848 pcireg_t reg; 2849 unsigned char nent, linktype; 2850 int i; 2851 2852 printf("\n Root Complex Link Declaration\n"); 2853 2854 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 2855 printf(" Element Self Description Register: 0x%08x\n", reg); 2856 printf(" Element Type: %s\n", 2857 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 2858 nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 2859 printf(" Number of Link Entries: %hhu\n", nent); 2860 printf(" Component ID: %hhu\n", 2861 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 2862 printf(" Port Number: %hhu\n", 2863 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 2864 for (i = 0; i < nent; i++) { 2865 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 2866 printf(" Link Entry %d:\n", i + 1); 2867 printf(" Link Description Register: 0x%08x\n", reg); 2868 onoff(" Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID); 2869 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 2870 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 2871 "Configuration Space", "Memory-Mapped Space"); 2872 onoff(" Associated RCRB Header", reg, 2873 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 2874 printf(" Target Component ID: %hhu\n", 2875 (unsigned char)__SHIFTOUT(reg, 2876 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 2877 printf(" Target Port Number: %hhu\n", 2878 (unsigned char)__SHIFTOUT(reg, 2879 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 2880 2881 if (linktype == 0) { 2882 /* Memory-Mapped Space */ 2883 reg = regs[o2i(extcapoff 2884 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 2885 printf(" Link Address Low Register: 0x%08x\n", 2886 reg); 2887 reg = regs[o2i(extcapoff 2888 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 2889 printf(" Link Address High Register: 0x%08x\n", 2890 reg); 2891 } else { 2892 unsigned int nb; 2893 pcireg_t lo, hi; 2894 2895 /* Configuration Space */ 2896 lo = regs[o2i(extcapoff 2897 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 2898 printf(" Configuration Space Low Register: " 2899 "0x%08x\n", lo); 2900 hi = regs[o2i(extcapoff 2901 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 2902 printf(" Configuration Space High Register: " 2903 "0x%08x\n", hi); 2904 nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 2905 printf(" N: %u\n", nb); 2906 printf(" Func: %hhu\n", 2907 (unsigned char)__SHIFTOUT(lo, 2908 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 2909 printf(" Dev: %hhu\n", 2910 (unsigned char)__SHIFTOUT(lo, 2911 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 2912 printf(" Bus: %hhu\n", 2913 (unsigned char)__SHIFTOUT(lo, 2914 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 2915 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 2916 printf(" Configuration Space Base Address: " 2917 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 2918 } 2919 } 2920 } 2921 2922 /* XXX pci_conf_print_rclink_ctl_cap */ 2923 2924 static void 2925 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2926 { 2927 pcireg_t reg; 2928 2929 printf("\n Root Complex Event Collector Association\n"); 2930 2931 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 2932 printf(" Association Bitmap for Root Complex Integrated Devices:" 2933 " 0x%08x\n", reg); 2934 } 2935 2936 /* XXX pci_conf_print_mfvc_cap */ 2937 /* XXX pci_conf_print_vc2_cap */ 2938 /* XXX pci_conf_print_rcrb_cap */ 2939 /* XXX pci_conf_print_vendor_cap */ 2940 /* XXX pci_conf_print_cac_cap */ 2941 2942 static void 2943 pci_conf_print_acs_cap(const pcireg_t *regs, int capoff, int extcapoff) 2944 { 2945 pcireg_t reg, cap, ctl; 2946 unsigned int size, i; 2947 2948 printf("\n Access Control Services\n"); 2949 2950 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 2951 cap = reg & 0xffff; 2952 ctl = reg >> 16; 2953 printf(" ACS Capability register: 0x%08x\n", cap); 2954 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 2955 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 2956 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 2957 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 2958 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 2959 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 2960 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 2961 size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 2962 if (size == 0) 2963 size = 256; 2964 printf(" Egress Control Vector Size: %u\n", size); 2965 printf(" ACS Control register: 0x%08x\n", ctl); 2966 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 2967 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 2968 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 2969 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 2970 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 2971 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 2972 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 2973 2974 /* 2975 * If the P2P Egress Control Capability bit is 0, ignore the Egress 2976 * Control vector. 2977 */ 2978 if ((cap & PCI_ACS_CAP_E) == 0) 2979 return; 2980 for (i = 0; i < size; i += 32) 2981 printf(" Egress Control Vector [%u..%u]: 0x%08x\n", i + 31, 2982 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 2983 } 2984 2985 static void 2986 pci_conf_print_ari_cap(const pcireg_t *regs, int capoff, int extcapoff) 2987 { 2988 pcireg_t reg, cap, ctl; 2989 2990 printf("\n Alternative Routing-ID Interpretation Register\n"); 2991 2992 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2993 cap = reg & 0xffff; 2994 ctl = reg >> 16; 2995 printf(" Capability register: 0x%08x\n", cap); 2996 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 2997 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 2998 printf(" Next Function Number: %u\n", 2999 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 3000 printf(" Control register: 0x%08x\n", ctl); 3001 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 3002 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 3003 printf(" Function Group: %u\n", 3004 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 3005 } 3006 3007 static void 3008 pci_conf_print_ats_cap(const pcireg_t *regs, int capoff, int extcapoff) 3009 { 3010 pcireg_t reg, cap, ctl; 3011 unsigned int num; 3012 3013 printf("\n Address Translation Services\n"); 3014 3015 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3016 cap = reg & 0xffff; 3017 ctl = reg >> 16; 3018 printf(" Capability register: 0x%04x\n", cap); 3019 num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 3020 if (num == 0) 3021 num = 32; 3022 printf(" Invalidate Queue Depth: %u\n", num); 3023 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 3024 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 3025 3026 printf(" Control register: 0x%04x\n", ctl); 3027 printf(" Smallest Translation Unit: %u\n", 3028 (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU)); 3029 onoff("Enable", reg, PCI_ATS_CTL_EN); 3030 } 3031 3032 static void 3033 pci_conf_print_sernum_cap(const pcireg_t *regs, int capoff, int extcapoff) 3034 { 3035 pcireg_t lo, hi; 3036 3037 printf("\n Device Serial Number Register\n"); 3038 3039 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 3040 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 3041 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 3042 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 3043 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 3044 } 3045 3046 static void 3047 pci_conf_print_sriov_cap(const pcireg_t *regs, int capoff, int extcapoff) 3048 { 3049 char buf[sizeof("99999 MB")]; 3050 pcireg_t reg; 3051 pcireg_t total_vfs; 3052 int i; 3053 bool first; 3054 3055 printf("\n Single Root IO Virtualization Register\n"); 3056 3057 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 3058 printf(" Capabilities register: 0x%08x\n", reg); 3059 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 3060 onoff("ARI Capable Hierarchy Preserved", reg, 3061 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 3062 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 3063 printf(" VF Migration Interrupt Message Number: 0x%03x\n", 3064 (pcireg_t)__SHIFTOUT(reg, 3065 PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 3066 } 3067 3068 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 3069 printf(" Control register: 0x%04x\n", reg); 3070 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 3071 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 3072 onoff("VF Migration Interrupt Enable", reg, 3073 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 3074 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 3075 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 3076 3077 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 3078 printf(" Status register: 0x%04x\n", reg); 3079 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 3080 3081 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 3082 printf(" InitialVFs register: 0x%04x\n", reg); 3083 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 3084 printf(" TotalVFs register: 0x%04x\n", reg); 3085 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 3086 printf(" NumVFs register: 0x%04x\n", reg); 3087 3088 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 3089 printf(" Function Dependency Link register: 0x%04x\n", reg); 3090 3091 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 3092 printf(" First VF Offset register: 0x%04x\n", reg); 3093 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 3094 printf(" VF Stride register: 0x%04x\n", reg); 3095 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16; 3096 printf(" Device ID: 0x%04x\n", reg); 3097 3098 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 3099 printf(" Supported Page Sizes register: 0x%08x\n", reg); 3100 printf(" Supported Page Size:"); 3101 for (i = 0, first = true; i < 32; i++) { 3102 if (reg & __BIT(i)) { 3103 #ifdef _KERNEL 3104 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 3105 #else 3106 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 3107 HN_AUTOSCALE, 0); 3108 #endif 3109 printf("%s %s", first ? "" : ",", buf); 3110 first = false; 3111 } 3112 } 3113 printf("\n"); 3114 3115 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 3116 printf(" System Page Sizes register: 0x%08x\n", reg); 3117 printf(" Page Size: "); 3118 if (reg != 0) { 3119 int bitpos = ffs(reg) -1; 3120 3121 /* Assume only one bit is set. */ 3122 #ifdef _KERNEL 3123 format_bytes(buf, sizeof(buf), 1LL << (bitpos + 12)); 3124 #else 3125 humanize_number(buf, sizeof(buf), 1LL << (bitpos + 12), 3126 "B", HN_AUTOSCALE, 0); 3127 #endif 3128 printf("%s", buf); 3129 } else { 3130 printf("unknown"); 3131 } 3132 printf("\n"); 3133 3134 for (i = 0; i < 6; i++) { 3135 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 3136 printf(" VF BAR%d register: 0x%08x\n", i, reg); 3137 } 3138 3139 if (total_vfs > 0) { 3140 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 3141 printf(" VF Migration State Array Offset register: 0x%08x\n", 3142 reg); 3143 printf(" VF Migration State Offset: 0x%08x\n", 3144 (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 3145 i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 3146 printf(" VF Migration State BIR: "); 3147 if (i >= 0 && i <= 5) { 3148 printf("BAR%d", i); 3149 } else { 3150 printf("unknown BAR (%d)", i); 3151 } 3152 printf("\n"); 3153 } 3154 } 3155 3156 /* XXX pci_conf_print_mriov_cap */ 3157 3158 static void 3159 pci_conf_print_multicast_cap(const pcireg_t *regs, int capoff, int extcapoff) 3160 { 3161 pcireg_t reg, cap, ctl; 3162 pcireg_t regl, regh; 3163 uint64_t addr; 3164 int n; 3165 3166 printf("\n Multicast\n"); 3167 3168 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 3169 cap = reg & 0xffff; 3170 ctl = reg >> 16; 3171 printf(" Capability Register: 0x%04x\n", cap); 3172 printf(" Max Group: %u\n", 3173 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 3174 3175 /* Endpoint Only */ 3176 n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 3177 if (n > 0) 3178 printf(" Windw Size Requested: %d\n", 1 << (n - 1)); 3179 3180 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 3181 3182 printf(" Control Register: 0x%04x\n", ctl); 3183 printf(" Num Group: %u\n", 3184 (unsigned int)__SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 3185 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 3186 3187 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 3188 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 3189 printf(" Base Address Register 0: 0x%08x\n", regl); 3190 printf(" Base Address Register 1: 0x%08x\n", regh); 3191 printf(" Index Position: %u\n", 3192 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 3193 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 3194 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 3195 3196 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 3197 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 3198 printf(" Receive Register 0: 0x%08x\n", regl); 3199 printf(" Receive Register 1: 0x%08x\n", regh); 3200 3201 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 3202 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 3203 printf(" Block All Register 0: 0x%08x\n", regl); 3204 printf(" Block All Register 1: 0x%08x\n", regh); 3205 3206 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 3207 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 3208 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 3209 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 3210 3211 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 3212 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 3213 printf(" Overlay BAR 0: 0x%08x\n", regl); 3214 printf(" Overlay BAR 1: 0x%08x\n", regh); 3215 3216 n = regl & PCI_MCAST_OVERLAYL_SIZE; 3217 printf(" Overlay Size: "); 3218 if (n >= 6) 3219 printf("%d\n", n); 3220 else 3221 printf("off\n"); 3222 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 3223 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 3224 } 3225 3226 static void 3227 pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3228 { 3229 pcireg_t reg, ctl, sta; 3230 3231 printf("\n Page Request\n"); 3232 3233 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 3234 ctl = reg & 0xffff; 3235 sta = reg >> 16; 3236 printf(" Control Register: 0x%04x\n", ctl); 3237 onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E); 3238 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 3239 3240 printf(" Status Register: 0x%04x\n", sta); 3241 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 3242 onoff("Unexpected Page Request Group Index", reg, 3243 PCI_PAGE_REQ_STA_UPRGI); 3244 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 3245 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 3246 3247 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 3248 printf(" Outstanding Page Request Capacity: %u\n", reg); 3249 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 3250 printf(" Outstanding Page Request Allocation: %u\n", reg); 3251 } 3252 3253 /* XXX pci_conf_print_amd_cap */ 3254 3255 #define MEM_PBUFSIZE sizeof("999GB") 3256 3257 static void 3258 pci_conf_print_resizbar_cap(const pcireg_t *regs, int capoff, int extcapoff) 3259 { 3260 pcireg_t cap, ctl; 3261 unsigned int bars, i, n; 3262 char pbuf[MEM_PBUFSIZE]; 3263 3264 printf("\n Resizable BAR\n"); 3265 3266 /* Get Number of Resizable BARs */ 3267 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))]; 3268 bars = __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR); 3269 printf(" Number of Resizable BARs: "); 3270 if (bars <= 6) 3271 printf("%u\n", bars); 3272 else { 3273 printf("incorrect (%u)\n", bars); 3274 return; 3275 } 3276 3277 for (n = 0; n < 6; n++) { 3278 cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))]; 3279 printf(" Capability register(%u): 0x%08x\n", n, cap); 3280 if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0) 3281 continue; /* Not Used */ 3282 printf(" Acceptable BAR sizes:"); 3283 for (i = 4; i <= 23; i++) { 3284 if ((cap & (1 << i)) != 0) { 3285 humanize_number(pbuf, MEM_PBUFSIZE, 3286 (int64_t)1024 * 1024 << (i - 4), "B", 3287 #ifdef _KERNEL 3288 1); 3289 #else 3290 HN_AUTOSCALE, HN_NOSPACE); 3291 #endif 3292 printf(" %s", pbuf); 3293 } 3294 } 3295 printf("\n"); 3296 3297 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))]; 3298 printf(" Control register(%u): 0x%08x\n", n, ctl); 3299 printf(" BAR Index: %u\n", 3300 (unsigned int)__SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX)); 3301 humanize_number(pbuf, MEM_PBUFSIZE, 3302 (int64_t)1024 * 1024 3303 << __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ), 3304 "B", 3305 #ifdef _KERNEL 3306 1); 3307 #else 3308 HN_AUTOSCALE, HN_NOSPACE); 3309 #endif 3310 printf(" BAR Size: %s\n", pbuf); 3311 } 3312 } 3313 3314 static void 3315 pci_conf_print_dpa_cap(const pcireg_t *regs, int capoff, int extcapoff) 3316 { 3317 pcireg_t reg; 3318 unsigned int substmax, i; 3319 3320 printf("\n Dynamic Power Allocation\n"); 3321 3322 reg = regs[o2i(extcapoff + PCI_DPA_CAP)]; 3323 printf(" Capability register: 0x%08x\n", reg); 3324 substmax = __SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX); 3325 printf(" Substate Max: %u\n", substmax); 3326 printf(" Transition Latency Unit: "); 3327 switch (__SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) { 3328 case 0: 3329 printf("1ms\n"); 3330 break; 3331 case 1: 3332 printf("10ms\n"); 3333 break; 3334 case 2: 3335 printf("100ms\n"); 3336 break; 3337 default: 3338 printf("reserved\n"); 3339 break; 3340 } 3341 printf(" Power Allocation Scale: "); 3342 switch (__SHIFTOUT(reg, PCI_DPA_CAP_PAS)) { 3343 case 0: 3344 printf("10.0x\n"); 3345 break; 3346 case 1: 3347 printf("1.0x\n"); 3348 break; 3349 case 2: 3350 printf("0.1x\n"); 3351 break; 3352 case 3: 3353 printf("0.01x\n"); 3354 break; 3355 } 3356 printf(" Transition Latency Value 0: %u\n", 3357 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY0)); 3358 printf(" Transition Latency Value 1: %u\n", 3359 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); 3360 3361 reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; 3362 printf(" Latency Indicatior register: 0x%08x\n", reg); 3363 3364 reg = regs[o2i(extcapoff + PCI_DPA_CS)]; 3365 printf(" Status register: 0x%04x\n", reg & 0xffff); 3366 printf(" Substate Status: 0x%02x\n", 3367 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT)); 3368 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN); 3369 printf(" Control register: 0x%04x\n", reg >> 16); 3370 printf(" Substate Control: 0x%02x\n", 3371 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL)); 3372 3373 for (i = 0; i <= substmax; i++) 3374 printf(" Substate Power Allocation register %d: 0x%02x\n", 3375 i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff)); 3376 } 3377 3378 static const char * 3379 pci_conf_print_tph_req_cap_sttabloc(unsigned char val) 3380 { 3381 3382 switch (val) { 3383 case 0x0: 3384 return "Not Present"; 3385 case 0x1: 3386 return "in the TPH Requester Capability Structure"; 3387 case 0x2: 3388 return "in the MSI-X Table"; 3389 default: 3390 return "Unknown"; 3391 } 3392 } 3393 3394 static void 3395 pci_conf_print_tph_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3396 { 3397 pcireg_t reg; 3398 int size, i, j; 3399 3400 printf("\n TPH Requester Extended Capability\n"); 3401 3402 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3403 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3404 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3405 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3406 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3407 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3408 printf(" ST Table Location: %s\n", 3409 pci_conf_print_tph_req_cap_sttabloc( 3410 (unsigned char)__SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC))); 3411 size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3412 printf(" ST Table Size: %d\n", size); 3413 3414 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CTL)]; 3415 printf(" TPH Requester Control register: 0x%08x\n", reg); 3416 printf(" ST Mode Select: "); 3417 switch (__SHIFTOUT(reg, PCI_TPH_REQ_CTL_STSEL)) { 3418 case PCI_TPH_REQ_CTL_STSEL_NO: 3419 printf("No ST Mode\n"); 3420 break; 3421 case PCI_TPH_REQ_CTL_STSEL_IV: 3422 printf("Interrupt Vector Mode\n"); 3423 break; 3424 case PCI_TPH_REQ_CTL_STSEL_DS: 3425 printf("Device Specific Mode\n"); 3426 break; 3427 default: 3428 printf("(reserved vaule)\n"); 3429 break; 3430 } 3431 printf(" TPH Requester Enable: "); 3432 switch (__SHIFTOUT(reg, PCI_TPH_REQ_CTL_TPHREQEN)) { 3433 case PCI_TPH_REQ_CTL_TPHREQEN_NO: /* 0x0 */ 3434 printf("Not permitted\n"); 3435 break; 3436 case PCI_TPH_REQ_CTL_TPHREQEN_TPH: 3437 printf("TPH and not Extended TPH\n"); 3438 break; 3439 case PCI_TPH_REQ_CTL_TPHREQEN_ETPH: 3440 printf("TPH and Extended TPH"); 3441 break; 3442 default: 3443 printf("(reserved vaule)\n"); 3444 break; 3445 } 3446 3447 for (i = 0; i < size ; i += 2) { 3448 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3449 for (j = 0; j < 2 ; j++) { 3450 uint32_t entry = reg; 3451 3452 if (j != 0) 3453 entry >>= 16; 3454 entry &= 0xffff; 3455 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3456 i + j, entry); 3457 } 3458 } 3459 } 3460 3461 static void 3462 pci_conf_print_ltr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3463 { 3464 pcireg_t reg; 3465 3466 printf("\n Latency Tolerance Reporting\n"); 3467 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)] & 0xffff; 3468 printf(" Max Snoop Latency Register: 0x%04x\n", reg); 3469 printf(" Max Snoop LatencyValue: %u\n", 3470 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL)); 3471 printf(" Max Snoop LatencyScale: %uns\n", 3472 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE))); 3473 reg = regs[o2i(extcapoff + PCI_LTR_MAXNOSNOOPLAT)] >> 16; 3474 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg); 3475 printf(" Max No-Snoop LatencyValue: %u\n", 3476 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL)); 3477 printf(" Max No-Snoop LatencyScale: %uns\n", 3478 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE))); 3479 } 3480 3481 static void 3482 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int capoff, int extcapoff) 3483 { 3484 int pcie_capoff; 3485 pcireg_t reg; 3486 int i, maxlinkwidth; 3487 3488 printf("\n Secondary PCI Express Register\n"); 3489 3490 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3491 printf(" Link Control 3 register: 0x%08x\n", reg); 3492 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3493 onoff("Link Equalization Request Interrupt Enable", 3494 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3495 printf(" Enable Lower SKP OS Generation Vector:"); 3496 pci_print_pcie_linkspeedvector( 3497 __SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3498 printf("\n"); 3499 3500 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3501 printf(" Lane Error Status register: 0x%08x\n", reg); 3502 3503 /* Get Max Link Width */ 3504 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)){ 3505 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3506 maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3507 } else { 3508 printf("error: falied to get PCIe capablity\n"); 3509 return; 3510 } 3511 for (i = 0; i < maxlinkwidth; i++) { 3512 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3513 if (i % 2 != 0) 3514 reg >>= 16; 3515 else 3516 reg &= 0xffff; 3517 printf(" Equalization Control Register (Link %d): 0x%04x\n", 3518 i, reg); 3519 printf(" Downstream Port Transmit Preset: 0x%x\n", 3520 (pcireg_t)__SHIFTOUT(reg, 3521 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3522 printf(" Downstream Port Receive Hint: 0x%x\n", 3523 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3524 printf(" Upstream Port Transmit Preset: 0x%x\n", 3525 (pcireg_t)__SHIFTOUT(reg, 3526 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3527 printf(" Upstream Port Receive Hint: 0x%x\n", 3528 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3529 } 3530 } 3531 3532 /* XXX pci_conf_print_pmux_cap */ 3533 3534 static void 3535 pci_conf_print_pasid_cap(const pcireg_t *regs, int capoff, int extcapoff) 3536 { 3537 pcireg_t reg, cap, ctl; 3538 unsigned int num; 3539 3540 printf("\n Process Address Space ID\n"); 3541 3542 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3543 cap = reg & 0xffff; 3544 ctl = reg >> 16; 3545 printf(" PASID Capability Register: 0x%04x\n", cap); 3546 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3547 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3548 num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3549 printf(" Max PASID Width: %u\n", num); 3550 3551 printf(" PASID Control Register: 0x%04x\n", ctl); 3552 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3553 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3554 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3555 } 3556 3557 static void 3558 pci_conf_print_lnr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3559 { 3560 pcireg_t reg, cap, ctl; 3561 unsigned int num; 3562 3563 printf("\n LN Requester\n"); 3564 3565 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3566 cap = reg & 0xffff; 3567 ctl = reg >> 16; 3568 printf(" LNR Capability register: 0x%04x\n", cap); 3569 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 3570 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 3571 num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 3572 printf(" LNR Registration MAX: %u\n", num); 3573 3574 printf(" LNR Control register: 0x%04x\n", ctl); 3575 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 3576 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 3577 num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 3578 printf(" LNR Registration Limit: %u\n", num); 3579 } 3580 3581 static void 3582 pci_conf_print_dpc_pio(pcireg_t r) 3583 { 3584 onoff("Cfg Request received UR Completion", r,PCI_DPC_RPPIO_CFGUR_CPL); 3585 onoff("Cfg Request received CA Completion", r,PCI_DPC_RPPIO_CFGCA_CPL); 3586 onoff("Cfg Request Completion Timeout", r, PCI_DPC_RPPIO_CFG_CTO); 3587 onoff("I/O Request received UR Completion", r, PCI_DPC_RPPIO_IOUR_CPL); 3588 onoff("I/O Request received CA Completion", r, PCI_DPC_RPPIO_IOCA_CPL); 3589 onoff("I/O Request Completion Timeout", r, PCI_DPC_RPPIO_IO_CTO); 3590 onoff("Mem Request received UR Completion", r,PCI_DPC_RPPIO_MEMUR_CPL); 3591 onoff("Mem Request received CA Completion", r,PCI_DPC_RPPIO_MEMCA_CPL); 3592 onoff("Mem Request Completion Timeout", r, PCI_DPC_RPPIO_MEM_CTO); 3593 } 3594 3595 static void 3596 pci_conf_print_dpc_cap(const pcireg_t *regs, int capoff, int extcapoff) 3597 { 3598 pcireg_t reg, cap, ctl, stat, errsrc; 3599 const char *trigstr; 3600 bool rpext; 3601 3602 printf("\n Downstream Port Containment\n"); 3603 3604 reg = regs[o2i(extcapoff + PCI_DPC_CCR)]; 3605 cap = reg & 0xffff; 3606 ctl = reg >> 16; 3607 rpext = (reg & PCI_DPCCAP_RPEXT) ? true : false; 3608 printf(" DPC Capability register: 0x%04x\n", cap); 3609 printf(" DPC Interrupt Message Number: %02x\n", 3610 (unsigned int)(cap & PCI_DPCCAP_IMSGN)); 3611 onoff("RP Extensions for DPC", reg, PCI_DPCCAP_RPEXT); 3612 onoff("Poisoned TLP Egress Blocking Supported", reg, 3613 PCI_DPCCAP_POISONTLPEB); 3614 onoff("DPC Software Triggering Supported", reg, PCI_DPCCAP_SWTRIG); 3615 printf(" RP PIO Log Size: %u\n", 3616 (unsigned int)__SHIFTOUT(reg, PCI_DPCCAP_RPPIOLOGSZ)); 3617 onoff("DL_Active ERR_COR Signaling Supported", reg, 3618 PCI_DPCCAP_DLACTECORS); 3619 printf(" DPC Control register: 0x%04x\n", ctl); 3620 switch (__SHIFTOUT(reg, PCI_DPCCTL_TIRGEN)) { 3621 case 0: 3622 trigstr = "disabled"; 3623 break; 3624 case 1: 3625 trigstr = "enabled(ERR_FATAL)"; 3626 break; 3627 case 2: 3628 trigstr = "enabled(ERR_NONFATAL or ERR_FATAL)"; 3629 break; 3630 default: 3631 trigstr = "(reserverd)"; 3632 break; 3633 } 3634 printf(" DPC Trigger Enable: %s\n", trigstr); 3635 printf(" DPC Completion Control: %s Completion Status\n", 3636 (reg & PCI_DPCCTL_COMPCTL) 3637 ? "Unsupported Request(UR)" : "Completer Abort(CA)"); 3638 onoff("DPC Interrupt Enable", reg, PCI_DPCCTL_IE); 3639 onoff("DPC ERR_COR Enable", reg, PCI_DPCCTL_ERRCOREN); 3640 onoff("Poisoned TLP Egress Blocking Enable", reg, 3641 PCI_DPCCTL_POISONTLPEB); 3642 onoff("DPC Software Trigger", reg, PCI_DPCCTL_SWTRIG); 3643 onoff("DL_Active ERR_COR Enable", reg, PCI_DPCCTL_DLACTECOR); 3644 3645 reg = regs[o2i(extcapoff + PCI_DPC_STATESID)]; 3646 stat = reg & 0xffff; 3647 errsrc = reg >> 16; 3648 printf(" DPC Status register: 0x%04x\n", stat); 3649 onoff("DPC Trigger Status", reg, PCI_DPCSTAT_TSTAT); 3650 switch (__SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 3651 case 0: 3652 trigstr = "an unmasked uncorrectable error"; 3653 break; 3654 case 1: 3655 trigstr = "receiving an ERR_NONFATAL"; 3656 break; 3657 case 2: 3658 trigstr = "receiving an ERR_FATAL"; 3659 break; 3660 case 3: 3661 trigstr = "DPC Trigger Reason Extension field"; 3662 break; 3663 } 3664 printf(" DPC Trigger Reason: Due to %s\n", trigstr); 3665 onoff("DPC Interrupt Status", reg, PCI_DPCSTAT_ISTAT); 3666 if (rpext) 3667 onoff("DPC RP Busy", reg, PCI_DPCSTAT_RPBUSY); 3668 switch (__SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 3669 case 0: 3670 trigstr = "Due to RP PIO error"; 3671 break; 3672 case 1: 3673 trigstr = "Due to the DPC Software trigger bit"; 3674 break; 3675 default: 3676 trigstr = "(reserved)"; 3677 break; 3678 } 3679 printf(" DPC Trigger Reason Extension: %s\n", trigstr); 3680 if (rpext) 3681 printf(" RP PIO First Error Pointer: %02x\n", 3682 (unsigned int)__SHIFTOUT(reg, PCI_DPCSTAT_RPPIOFEP)); 3683 printf(" DPC Error Source ID register: 0x%04x\n", errsrc); 3684 3685 if (!rpext) 3686 return; 3687 /* 3688 * All of the following registers are implemented by a device which has 3689 * RP Extensions for DPC 3690 */ 3691 3692 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_STAT)]; 3693 printf(" RP PIO Status Register: 0x%04x\n", reg); 3694 pci_conf_print_dpc_pio(reg); 3695 3696 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_MASK)]; 3697 printf(" RP PIO Mask Register: 0x%04x\n", reg); 3698 pci_conf_print_dpc_pio(reg); 3699 3700 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SEVE)]; 3701 printf(" RP PIO Severity Register: 0x%04x\n", reg); 3702 pci_conf_print_dpc_pio(reg); 3703 3704 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SYSERR)]; 3705 printf(" RP PIO SysError Register: 0x%04x\n", reg); 3706 pci_conf_print_dpc_pio(reg); 3707 3708 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_EXCPT)]; 3709 printf(" RP PIO Exception Register: 0x%04x\n", reg); 3710 pci_conf_print_dpc_pio(reg); 3711 3712 printf(" RP PIO Header Log Register: start from 0x%03x\n", 3713 extcapoff + PCI_DPC_RPPIO_HLOG); 3714 printf(" RP PIO ImpSpec Log Register: start from 0x%03x\n", 3715 extcapoff + PCI_DPC_RPPIO_IMPSLOG); 3716 printf(" RP PIO TPL Prefix Log Register: start from 0x%03x\n", 3717 extcapoff + PCI_DPC_RPPIO_TLPPLOG); 3718 } 3719 3720 3721 static int 3722 pci_conf_l1pm_cap_tposcale(unsigned char scale) 3723 { 3724 3725 /* Return scale in us */ 3726 switch (scale) { 3727 case 0x0: 3728 return 2; 3729 case 0x1: 3730 return 10; 3731 case 0x2: 3732 return 100; 3733 default: 3734 return -1; 3735 } 3736 } 3737 3738 static void 3739 pci_conf_print_l1pm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3740 { 3741 pcireg_t reg; 3742 int scale, val; 3743 3744 printf("\n L1 PM Substates\n"); 3745 3746 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 3747 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 3748 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 3749 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 3750 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 3751 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 3752 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 3753 printf(" Port Common Mode Restore Time: %uus\n", 3754 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 3755 scale = pci_conf_l1pm_cap_tposcale( 3756 __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 3757 val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 3758 printf(" Port T_POWER_ON: "); 3759 if (scale == -1) 3760 printf("unknown\n"); 3761 else 3762 printf("%dus\n", val * scale); 3763 3764 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 3765 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 3766 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 3767 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 3768 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 3769 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 3770 printf(" Common Mode Restore Time: %uus\n", 3771 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 3772 scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 3773 val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 3774 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 3775 3776 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 3777 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 3778 scale = pci_conf_l1pm_cap_tposcale( 3779 __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 3780 val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 3781 printf(" T_POWER_ON: "); 3782 if (scale == -1) 3783 printf("unknown\n"); 3784 else 3785 printf("%dus\n", val * scale); 3786 } 3787 3788 static void 3789 pci_conf_print_ptm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3790 { 3791 pcireg_t reg; 3792 uint32_t val; 3793 3794 printf("\n Precision Time Management\n"); 3795 3796 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 3797 printf(" PTM Capability register: 0x%08x\n", reg); 3798 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 3799 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 3800 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 3801 printf(" Local Clock Granularity: "); 3802 val = __SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 3803 switch (val) { 3804 case 0: 3805 printf("Not implemented\n"); 3806 break; 3807 case 0xffff: 3808 printf("> 254ns\n"); 3809 break; 3810 default: 3811 printf("%uns\n", val); 3812 break; 3813 } 3814 3815 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 3816 printf(" PTM Control register: 0x%08x\n", reg); 3817 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 3818 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 3819 printf(" Effective Granularity: "); 3820 val = __SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 3821 switch (val) { 3822 case 0: 3823 printf("Unknown\n"); 3824 break; 3825 case 0xffff: 3826 printf("> 254ns\n"); 3827 break; 3828 default: 3829 printf("%uns\n", val); 3830 break; 3831 } 3832 } 3833 3834 /* XXX pci_conf_print_mpcie_cap */ 3835 /* XXX pci_conf_print_frsq_cap */ 3836 /* XXX pci_conf_print_rtr_cap */ 3837 /* XXX pci_conf_print_desigvndsp_cap */ 3838 /* XXX pci_conf_print_vf_resizbar_cap */ 3839 /* XXX pci_conf_print_hierarchyid_cap */ 3840 3841 #undef MS 3842 #undef SM 3843 #undef RW 3844 3845 static struct { 3846 pcireg_t cap; 3847 const char *name; 3848 void (*printfunc)(const pcireg_t *, int, int); 3849 } pci_extcaptab[] = { 3850 { 0, "reserved", 3851 NULL }, 3852 { PCI_EXTCAP_AER, "Advanced Error Reporting", 3853 pci_conf_print_aer_cap }, 3854 { PCI_EXTCAP_VC, "Virtual Channel", 3855 pci_conf_print_vc_cap }, 3856 { PCI_EXTCAP_SERNUM, "Device Serial Number", 3857 pci_conf_print_sernum_cap }, 3858 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 3859 pci_conf_print_pwrbdgt_cap }, 3860 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 3861 pci_conf_print_rclink_dcl_cap }, 3862 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 3863 NULL }, 3864 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 3865 pci_conf_print_rcec_assoc_cap }, 3866 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 3867 NULL }, 3868 { PCI_EXTCAP_VC2, "Virtual Channel", 3869 NULL }, 3870 { PCI_EXTCAP_RCRB, "RCRB Header", 3871 NULL }, 3872 { PCI_EXTCAP_VENDOR, "Vendor Unique", 3873 NULL }, 3874 { PCI_EXTCAP_CAC, "Configuration Access Correction", 3875 NULL }, 3876 { PCI_EXTCAP_ACS, "Access Control Services", 3877 pci_conf_print_acs_cap }, 3878 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 3879 pci_conf_print_ari_cap }, 3880 { PCI_EXTCAP_ATS, "Address Translation Services", 3881 pci_conf_print_ats_cap }, 3882 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 3883 pci_conf_print_sriov_cap }, 3884 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 3885 NULL }, 3886 { PCI_EXTCAP_MCAST, "Multicast", 3887 pci_conf_print_multicast_cap }, 3888 { PCI_EXTCAP_PAGE_REQ, "Page Request", 3889 pci_conf_print_page_req_cap }, 3890 { PCI_EXTCAP_AMD, "Reserved for AMD", 3891 NULL }, 3892 { PCI_EXTCAP_RESIZBAR, "Resizable BAR", 3893 pci_conf_print_resizbar_cap }, 3894 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 3895 pci_conf_print_dpa_cap }, 3896 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 3897 pci_conf_print_tph_req_cap }, 3898 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 3899 pci_conf_print_ltr_cap }, 3900 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 3901 pci_conf_print_sec_pcie_cap }, 3902 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 3903 NULL }, 3904 { PCI_EXTCAP_PASID, "Process Address Space ID", 3905 pci_conf_print_pasid_cap }, 3906 { PCI_EXTCAP_LN_REQ, "LN Requester", 3907 pci_conf_print_lnr_cap }, 3908 { PCI_EXTCAP_DPC, "Downstream Port Containment", 3909 pci_conf_print_dpc_cap }, 3910 { PCI_EXTCAP_L1PM, "L1 PM Substates", 3911 pci_conf_print_l1pm_cap }, 3912 { PCI_EXTCAP_PTM, "Precision Time Management", 3913 pci_conf_print_ptm_cap }, 3914 { PCI_EXTCAP_MPCIE, "M-PCIe", 3915 NULL }, 3916 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 3917 NULL }, 3918 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 3919 NULL }, 3920 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 3921 NULL }, 3922 { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", 3923 NULL }, 3924 { PCI_EXTCAP_HIERARCHYID, "Hierarchy ID", 3925 NULL }, 3926 }; 3927 3928 static int 3929 pci_conf_find_extcap(const pcireg_t *regs, int capoff, unsigned int capid, 3930 int *offsetp) 3931 { 3932 int off; 3933 pcireg_t rval; 3934 3935 for (off = PCI_EXTCAPLIST_BASE; 3936 off != 0; 3937 off = PCI_EXTCAPLIST_NEXT(rval)) { 3938 rval = regs[o2i(off)]; 3939 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 3940 if (offsetp != NULL) 3941 *offsetp = off; 3942 return 1; 3943 } 3944 } 3945 return 0; 3946 } 3947 3948 static void 3949 pci_conf_print_extcaplist( 3950 #ifdef _KERNEL 3951 pci_chipset_tag_t pc, pcitag_t tag, 3952 #endif 3953 const pcireg_t *regs, int capoff) 3954 { 3955 int off; 3956 pcireg_t foundcap; 3957 pcireg_t rval; 3958 bool foundtable[__arraycount(pci_extcaptab)]; 3959 unsigned int i; 3960 3961 /* Check Extended capability structure */ 3962 off = PCI_EXTCAPLIST_BASE; 3963 rval = regs[o2i(off)]; 3964 if (rval == 0xffffffff || rval == 0) 3965 return; 3966 3967 /* Clear table */ 3968 for (i = 0; i < __arraycount(pci_extcaptab); i++) 3969 foundtable[i] = false; 3970 3971 /* Print extended capability register's offset and the type first */ 3972 for (;;) { 3973 printf(" Extended Capability Register at 0x%02x\n", off); 3974 3975 foundcap = PCI_EXTCAPLIST_CAP(rval); 3976 printf(" type: 0x%04x (", foundcap); 3977 if (foundcap < __arraycount(pci_extcaptab)) { 3978 printf("%s)\n", pci_extcaptab[foundcap].name); 3979 /* Mark as found */ 3980 foundtable[foundcap] = true; 3981 } else 3982 printf("unknown)\n"); 3983 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 3984 3985 off = PCI_EXTCAPLIST_NEXT(rval); 3986 if (off == 0) 3987 break; 3988 else if (off <= PCI_CONF_SIZE) { 3989 printf(" next pointer: 0x%03x (incorrect)\n", off); 3990 return; 3991 } 3992 rval = regs[o2i(off)]; 3993 } 3994 3995 /* 3996 * And then, print the detail of each capability registers 3997 * in capability value's order. 3998 */ 3999 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 4000 if (foundtable[i] == false) 4001 continue; 4002 4003 /* 4004 * The type was found. Search capability list again and 4005 * print all capabilities that the capabiliy type is 4006 * the same. 4007 */ 4008 if (pci_conf_find_extcap(regs, capoff, i, &off) == 0) 4009 continue; 4010 rval = regs[o2i(off)]; 4011 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 4012 || (pci_extcaptab[i].printfunc == NULL)) 4013 continue; 4014 4015 pci_extcaptab[i].printfunc(regs, capoff, off); 4016 4017 } 4018 } 4019 4020 /* Print the Secondary Status Register. */ 4021 static void 4022 pci_conf_print_ssr(pcireg_t rval) 4023 { 4024 pcireg_t devsel; 4025 4026 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 4027 onoff("66 MHz capable", rval, __BIT(5)); 4028 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 4029 onoff("Fast back-to-back capable", rval, __BIT(7)); 4030 onoff("Data parity error detected", rval, __BIT(8)); 4031 4032 printf(" DEVSEL timing: "); 4033 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 4034 switch (devsel) { 4035 case 0: 4036 printf("fast"); 4037 break; 4038 case 1: 4039 printf("medium"); 4040 break; 4041 case 2: 4042 printf("slow"); 4043 break; 4044 default: 4045 printf("unknown/reserved"); /* XXX */ 4046 break; 4047 } 4048 printf(" (0x%x)\n", devsel); 4049 4050 onoff("Signalled target abort", rval, __BIT(11)); 4051 onoff("Received target abort", rval, __BIT(12)); 4052 onoff("Received master abort", rval, __BIT(13)); 4053 onoff("Received system error", rval, __BIT(14)); 4054 onoff("Detected parity error", rval, __BIT(15)); 4055 } 4056 4057 static void 4058 pci_conf_print_type0( 4059 #ifdef _KERNEL 4060 pci_chipset_tag_t pc, pcitag_t tag, 4061 #endif 4062 const pcireg_t *regs) 4063 { 4064 int off, width; 4065 pcireg_t rval; 4066 4067 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 4068 #ifdef _KERNEL 4069 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4070 #else 4071 width = pci_conf_print_bar(regs, off, NULL); 4072 #endif 4073 } 4074 4075 printf(" Cardbus CIS Pointer: 0x%08x\n", 4076 regs[o2i(PCI_CARDBUS_CIS_REG)]); 4077 4078 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 4079 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4080 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4081 4082 /* XXX */ 4083 printf(" Expansion ROM Base Address: 0x%08x\n", 4084 regs[o2i(PCI_MAPREG_ROM)]); 4085 4086 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4087 printf(" Capability list pointer: 0x%02x\n", 4088 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4089 else 4090 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4091 4092 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 4093 4094 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4095 printf(" Maximum Latency: 0x%02x\n", PCI_MAX_LAT(rval)); 4096 printf(" Minimum Grant: 0x%02x\n", PCI_MIN_GNT(rval)); 4097 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 4098 switch (PCI_INTERRUPT_PIN(rval)) { 4099 case PCI_INTERRUPT_PIN_NONE: 4100 printf("(none)"); 4101 break; 4102 case PCI_INTERRUPT_PIN_A: 4103 printf("(pin A)"); 4104 break; 4105 case PCI_INTERRUPT_PIN_B: 4106 printf("(pin B)"); 4107 break; 4108 case PCI_INTERRUPT_PIN_C: 4109 printf("(pin C)"); 4110 break; 4111 case PCI_INTERRUPT_PIN_D: 4112 printf("(pin D)"); 4113 break; 4114 default: 4115 printf("(? ? ?)"); 4116 break; 4117 } 4118 printf("\n"); 4119 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 4120 } 4121 4122 static void 4123 pci_conf_print_type1( 4124 #ifdef _KERNEL 4125 pci_chipset_tag_t pc, pcitag_t tag, 4126 #endif 4127 const pcireg_t *regs) 4128 { 4129 int off, width; 4130 pcireg_t rval; 4131 uint32_t base, limit; 4132 uint32_t base_h, limit_h; 4133 uint64_t pbase, plimit; 4134 int use_upper; 4135 4136 /* 4137 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 4138 * Bridge chip documentation, and may not be correct with 4139 * respect to various standards. (XXX) 4140 */ 4141 4142 for (off = 0x10; off < 0x18; off += width) { 4143 #ifdef _KERNEL 4144 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4145 #else 4146 width = pci_conf_print_bar(regs, off, NULL); 4147 #endif 4148 } 4149 4150 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4151 printf(" Primary bus number: 0x%02x\n", 4152 PCI_BRIDGE_BUS_PRIMARY(rval)); 4153 printf(" Secondary bus number: 0x%02x\n", 4154 PCI_BRIDGE_BUS_SECONDARY(rval)); 4155 printf(" Subordinate bus number: 0x%02x\n", 4156 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 4157 printf(" Secondary bus latency timer: 0x%02x\n", 4158 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 4159 4160 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 4161 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 4162 4163 /* I/O region */ 4164 printf(" I/O region:\n"); 4165 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 4166 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 4167 if (PCI_BRIDGE_IO_32BITS(rval)) 4168 use_upper = 1; 4169 else 4170 use_upper = 0; 4171 onoff("32bit I/O", rval, use_upper); 4172 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 4173 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 4174 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 4175 limit |= 0x00000fff; 4176 4177 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 4178 base_h = (rval >> 0) & 0xffff; 4179 limit_h = (rval >> 16) & 0xffff; 4180 printf(" base upper 16 bits register: 0x%04x\n", base_h); 4181 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 4182 4183 if (use_upper == 1) { 4184 base |= base_h << 16; 4185 limit |= limit_h << 16; 4186 } 4187 if (base < limit) { 4188 if (use_upper == 1) 4189 printf(" range: 0x%08x-0x%08x\n", base, limit); 4190 else 4191 printf(" range: 0x%04x-0x%04x\n", base, limit); 4192 } else 4193 printf(" range: not set\n"); 4194 4195 /* Non-prefetchable memory region */ 4196 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 4197 printf(" Memory region:\n"); 4198 printf(" base register: 0x%04x\n", 4199 (rval >> 0) & 0xffff); 4200 printf(" limit register: 0x%04x\n", 4201 (rval >> 16) & 0xffff); 4202 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 4203 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 4204 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 4205 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 4206 if (base < limit) 4207 printf(" range: 0x%08x-0x%08x\n", base, limit); 4208 else 4209 printf(" range: not set\n"); 4210 4211 /* Prefetchable memory region */ 4212 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 4213 printf(" Prefetchable memory region:\n"); 4214 printf(" base register: 0x%04x\n", 4215 (rval >> 0) & 0xffff); 4216 printf(" limit register: 0x%04x\n", 4217 (rval >> 16) & 0xffff); 4218 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 4219 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 4220 printf(" base upper 32 bits register: 0x%08x\n", 4221 base_h); 4222 printf(" limit upper 32 bits register: 0x%08x\n", 4223 limit_h); 4224 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 4225 use_upper = 1; 4226 else 4227 use_upper = 0; 4228 onoff("64bit memory address", rval, use_upper); 4229 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 4230 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 4231 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 4232 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 4233 if (use_upper == 1) { 4234 pbase |= (uint64_t)base_h << 32; 4235 plimit |= (uint64_t)limit_h << 32; 4236 } 4237 if (pbase < plimit) { 4238 if (use_upper == 1) 4239 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 4240 "\n", pbase, plimit); 4241 else 4242 printf(" range: 0x%08x-0x%08x\n", 4243 (uint32_t)pbase, (uint32_t)plimit); 4244 } else 4245 printf(" range: not set\n"); 4246 4247 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4248 printf(" Capability list pointer: 0x%02x\n", 4249 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4250 else 4251 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4252 4253 /* XXX */ 4254 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 4255 4256 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4257 printf(" Interrupt line: 0x%02x\n", 4258 (rval >> 0) & 0xff); 4259 printf(" Interrupt pin: 0x%02x ", 4260 (rval >> 8) & 0xff); 4261 switch ((rval >> 8) & 0xff) { 4262 case PCI_INTERRUPT_PIN_NONE: 4263 printf("(none)"); 4264 break; 4265 case PCI_INTERRUPT_PIN_A: 4266 printf("(pin A)"); 4267 break; 4268 case PCI_INTERRUPT_PIN_B: 4269 printf("(pin B)"); 4270 break; 4271 case PCI_INTERRUPT_PIN_C: 4272 printf("(pin C)"); 4273 break; 4274 case PCI_INTERRUPT_PIN_D: 4275 printf("(pin D)"); 4276 break; 4277 default: 4278 printf("(? ? ?)"); 4279 break; 4280 } 4281 printf("\n"); 4282 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 4283 & PCI_BRIDGE_CONTROL_MASK; 4284 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 4285 onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE); 4286 onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR); 4287 onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA); 4288 onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA); 4289 onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT); 4290 onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR); 4291 onoff("Fast back-to-back capable", rval,PCI_BRIDGE_CONTROL_SECFASTB2B); 4292 } 4293 4294 static void 4295 pci_conf_print_type2( 4296 #ifdef _KERNEL 4297 pci_chipset_tag_t pc, pcitag_t tag, 4298 #endif 4299 const pcireg_t *regs) 4300 { 4301 pcireg_t rval; 4302 4303 /* 4304 * XXX these need to be printed in more detail, need to be 4305 * XXX checked against specs/docs, etc. 4306 * 4307 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 4308 * controller chip documentation, and may not be correct with 4309 * respect to various standards. (XXX) 4310 */ 4311 4312 #ifdef _KERNEL 4313 pci_conf_print_bar(pc, tag, regs, 0x10, 4314 "CardBus socket/ExCA registers"); 4315 #else 4316 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 4317 #endif 4318 4319 /* Capability list pointer and secondary status register */ 4320 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 4321 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4322 printf(" Capability list pointer: 0x%02x\n", 4323 PCI_CAPLIST_PTR(rval)); 4324 else 4325 printf(" Reserved @ 0x14: 0x%04x\n", 4326 (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0))); 4327 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 4328 4329 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4330 printf(" PCI bus number: 0x%02x\n", 4331 (rval >> 0) & 0xff); 4332 printf(" CardBus bus number: 0x%02x\n", 4333 (rval >> 8) & 0xff); 4334 printf(" Subordinate bus number: 0x%02x\n", 4335 (rval >> 16) & 0xff); 4336 printf(" CardBus latency timer: 0x%02x\n", 4337 (rval >> 24) & 0xff); 4338 4339 /* XXX Print more prettily */ 4340 printf(" CardBus memory region 0:\n"); 4341 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 4342 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 4343 printf(" CardBus memory region 1:\n"); 4344 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 4345 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 4346 printf(" CardBus I/O region 0:\n"); 4347 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 4348 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 4349 printf(" CardBus I/O region 1:\n"); 4350 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 4351 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 4352 4353 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4354 printf(" Interrupt line: 0x%02x\n", 4355 (rval >> 0) & 0xff); 4356 printf(" Interrupt pin: 0x%02x ", 4357 (rval >> 8) & 0xff); 4358 switch ((rval >> 8) & 0xff) { 4359 case PCI_INTERRUPT_PIN_NONE: 4360 printf("(none)"); 4361 break; 4362 case PCI_INTERRUPT_PIN_A: 4363 printf("(pin A)"); 4364 break; 4365 case PCI_INTERRUPT_PIN_B: 4366 printf("(pin B)"); 4367 break; 4368 case PCI_INTERRUPT_PIN_C: 4369 printf("(pin C)"); 4370 break; 4371 case PCI_INTERRUPT_PIN_D: 4372 printf("(pin D)"); 4373 break; 4374 default: 4375 printf("(? ? ?)"); 4376 break; 4377 } 4378 printf("\n"); 4379 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> 16) & 0xffff; 4380 printf(" Bridge control register: 0x%04x\n", rval); 4381 onoff("Parity error response", rval, __BIT(0)); 4382 onoff("SERR# enable", rval, __BIT(1)); 4383 onoff("ISA enable", rval, __BIT(2)); 4384 onoff("VGA enable", rval, __BIT(3)); 4385 onoff("Master abort mode", rval, __BIT(5)); 4386 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 4387 onoff("Functional interrupts routed by ExCA registers", rval, 4388 __BIT(7)); 4389 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 4390 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 4391 onoff("Write posting enable", rval, __BIT(10)); 4392 4393 rval = regs[o2i(0x40)]; 4394 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4395 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4396 4397 #ifdef _KERNEL 4398 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers"); 4399 #else 4400 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 4401 #endif 4402 } 4403 4404 void 4405 pci_conf_print( 4406 #ifdef _KERNEL 4407 pci_chipset_tag_t pc, pcitag_t tag, 4408 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 4409 #else 4410 int pcifd, u_int bus, u_int dev, u_int func 4411 #endif 4412 ) 4413 { 4414 pcireg_t regs[o2i(PCI_EXTCONF_SIZE)]; 4415 int off, capoff, endoff, hdrtype; 4416 const char *type_name; 4417 #ifdef _KERNEL 4418 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 4419 #else 4420 void (*type_printfn)(const pcireg_t *); 4421 #endif 4422 4423 printf("PCI configuration registers:\n"); 4424 4425 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 4426 #ifdef _KERNEL 4427 regs[o2i(off)] = pci_conf_read(pc, tag, off); 4428 #else 4429 if (pcibus_conf_read(pcifd, bus, dev, func, off, 4430 ®s[o2i(off)]) == -1) 4431 regs[o2i(off)] = 0; 4432 #endif 4433 } 4434 4435 /* common header */ 4436 printf(" Common header:\n"); 4437 pci_conf_print_regs(regs, 0, 16); 4438 4439 printf("\n"); 4440 #ifdef _KERNEL 4441 pci_conf_print_common(pc, tag, regs); 4442 #else 4443 pci_conf_print_common(regs); 4444 #endif 4445 printf("\n"); 4446 4447 /* type-dependent header */ 4448 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 4449 switch (hdrtype) { /* XXX make a table, eventually */ 4450 case 0: 4451 /* Standard device header */ 4452 type_name = "\"normal\" device"; 4453 type_printfn = &pci_conf_print_type0; 4454 capoff = PCI_CAPLISTPTR_REG; 4455 endoff = 64; 4456 break; 4457 case 1: 4458 /* PCI-PCI bridge header */ 4459 type_name = "PCI-PCI bridge"; 4460 type_printfn = &pci_conf_print_type1; 4461 capoff = PCI_CAPLISTPTR_REG; 4462 endoff = 64; 4463 break; 4464 case 2: 4465 /* PCI-CardBus bridge header */ 4466 type_name = "PCI-CardBus bridge"; 4467 type_printfn = &pci_conf_print_type2; 4468 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 4469 endoff = 72; 4470 break; 4471 default: 4472 type_name = NULL; 4473 type_printfn = 0; 4474 capoff = -1; 4475 endoff = 64; 4476 break; 4477 } 4478 printf(" Type %d ", hdrtype); 4479 if (type_name != NULL) 4480 printf("(%s) ", type_name); 4481 printf("header:\n"); 4482 pci_conf_print_regs(regs, 16, endoff); 4483 printf("\n"); 4484 if (type_printfn) { 4485 #ifdef _KERNEL 4486 (*type_printfn)(pc, tag, regs); 4487 #else 4488 (*type_printfn)(regs); 4489 #endif 4490 } else 4491 printf(" Don't know how to pretty-print type %d header.\n", 4492 hdrtype); 4493 printf("\n"); 4494 4495 /* capability list, if present */ 4496 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4497 && (capoff > 0)) { 4498 #ifdef _KERNEL 4499 pci_conf_print_caplist(pc, tag, regs, capoff); 4500 #else 4501 pci_conf_print_caplist(regs, capoff); 4502 #endif 4503 printf("\n"); 4504 } 4505 4506 /* device-dependent header */ 4507 printf(" Device-dependent header:\n"); 4508 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 4509 printf("\n"); 4510 #ifdef _KERNEL 4511 if (printfn) 4512 (*printfn)(pc, tag, regs); 4513 else 4514 printf(" Don't know how to pretty-print device-dependent header.\n"); 4515 printf("\n"); 4516 #endif /* _KERNEL */ 4517 4518 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 4519 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 4520 return; 4521 4522 #ifdef _KERNEL 4523 pci_conf_print_extcaplist(pc, tag, regs, capoff); 4524 #else 4525 pci_conf_print_extcaplist(regs, capoff); 4526 #endif 4527 printf("\n"); 4528 4529 /* Extended Configuration Space, if present */ 4530 printf(" Extended Configuration Space:\n"); 4531 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 4532 } 4533
Indexes created Wed Sep 24 05:09:52 GMT 2025