pci_subr.c revision 1.183
1 /* $NetBSD: pci_subr.c,v 1.183 2017/05/29 07:09:20 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.183 2017/05/29 07:09:20 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdarg.h> 58 #include <stdbool.h> 59 #include <stdio.h> 60 #include <stdlib.h> 61 #include <string.h> 62 #endif 63 64 #include <dev/pci/pcireg.h> 65 #ifdef _KERNEL 66 #include <dev/pci/pcivar.h> 67 #else 68 #include <dev/pci/pci_verbose.h> 69 #include <dev/pci/pcidevs.h> 70 #include <dev/pci/pcidevs_data.h> 71 #endif 72 73 static int pci_conf_find_cap(const pcireg_t *, int, unsigned int, int *); 74 static void pci_conf_print_pcie_power(uint8_t, unsigned int); 75 76 /* 77 * Descriptions of known PCI classes and subclasses. 78 * 79 * Subclasses are described in the same way as classes, but have a 80 * NULL subclass pointer. 81 */ 82 struct pci_class { 83 const char *name; 84 u_int val; /* as wide as pci_{,sub}class_t */ 85 const struct pci_class *subclasses; 86 }; 87 88 /* 89 * Class 0x00. 90 * Before rev. 2.0. 91 */ 92 static const struct pci_class pci_subclass_prehistoric[] = { 93 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 94 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 95 { NULL, 0, NULL, }, 96 }; 97 98 /* 99 * Class 0x01. 100 * Mass storage controller 101 */ 102 103 /* ATA programming interface */ 104 static const struct pci_class pci_interface_ata[] = { 105 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 106 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 107 { NULL, 0, NULL, }, 108 }; 109 110 /* SATA programming interface */ 111 static const struct pci_class pci_interface_sata[] = { 112 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 113 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 114 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 115 { NULL, 0, NULL, }, 116 }; 117 118 /* Flash programming interface */ 119 static const struct pci_class pci_interface_nvm[] = { 120 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 121 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 122 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 123 { NULL, 0, NULL, }, 124 }; 125 126 /* Subclasses */ 127 static const struct pci_class pci_subclass_mass_storage[] = { 128 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 129 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 130 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 131 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 132 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 133 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 134 pci_interface_ata, }, 135 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 136 pci_interface_sata, }, 137 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 138 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 139 pci_interface_nvm, }, 140 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 141 { NULL, 0, NULL, }, 142 }; 143 144 /* 145 * Class 0x02. 146 * Network controller. 147 */ 148 static const struct pci_class pci_subclass_network[] = { 149 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 150 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 151 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 152 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 153 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 154 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 155 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 156 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 157 { NULL, 0, NULL, }, 158 }; 159 160 /* 161 * Class 0x03. 162 * Display controller. 163 */ 164 165 /* VGA programming interface */ 166 static const struct pci_class pci_interface_vga[] = { 167 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 168 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 169 { NULL, 0, NULL, }, 170 }; 171 /* Subclasses */ 172 static const struct pci_class pci_subclass_display[] = { 173 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 174 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 175 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 176 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 177 { NULL, 0, NULL, }, 178 }; 179 180 /* 181 * Class 0x04. 182 * Multimedia device. 183 */ 184 static const struct pci_class pci_subclass_multimedia[] = { 185 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 186 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 187 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 188 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 189 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 190 { NULL, 0, NULL, }, 191 }; 192 193 /* 194 * Class 0x05. 195 * Memory controller. 196 */ 197 static const struct pci_class pci_subclass_memory[] = { 198 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 199 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 200 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 201 { NULL, 0, NULL, }, 202 }; 203 204 /* 205 * Class 0x06. 206 * Bridge device. 207 */ 208 209 /* PCI bridge programming interface */ 210 static const struct pci_class pci_interface_pcibridge[] = { 211 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 212 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 213 { NULL, 0, NULL, }, 214 }; 215 216 /* Semi-transparent PCI-to-PCI bridge programming interface */ 217 static const struct pci_class pci_interface_stpci[] = { 218 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 219 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 220 { NULL, 0, NULL, }, 221 }; 222 223 /* Advanced Switching programming interface */ 224 static const struct pci_class pci_interface_advsw[] = { 225 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 226 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 227 { NULL, 0, NULL, }, 228 }; 229 230 /* Subclasses */ 231 static const struct pci_class pci_subclass_bridge[] = { 232 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 233 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 234 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 235 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 236 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 237 pci_interface_pcibridge, }, 238 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 239 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 240 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 241 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 242 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 243 pci_interface_stpci, }, 244 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 245 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 246 pci_interface_advsw, }, 247 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 248 { NULL, 0, NULL, }, 249 }; 250 251 /* 252 * Class 0x07. 253 * Simple communications controller. 254 */ 255 256 /* Serial controller programming interface */ 257 static const struct pci_class pci_interface_serial[] = { 258 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 259 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 260 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 261 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 262 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 263 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 264 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 265 { NULL, 0, NULL, }, 266 }; 267 268 /* Parallel controller programming interface */ 269 static const struct pci_class pci_interface_parallel[] = { 270 { "", PCI_INTERFACE_PARALLEL, NULL,}, 271 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 272 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 273 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 274 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 275 { NULL, 0, NULL,}, 276 }; 277 278 /* Modem programming interface */ 279 static const struct pci_class pci_interface_modem[] = { 280 { "", PCI_INTERFACE_MODEM, NULL,}, 281 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 282 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 283 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 284 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 285 { NULL, 0, NULL,}, 286 }; 287 288 /* Subclasses */ 289 static const struct pci_class pci_subclass_communications[] = { 290 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 291 pci_interface_serial, }, 292 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 293 pci_interface_parallel, }, 294 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 295 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 296 pci_interface_modem, }, 297 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 298 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 299 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 300 { NULL, 0, NULL,}, 301 }; 302 303 /* 304 * Class 0x08. 305 * Base system peripheral. 306 */ 307 308 /* PIC programming interface */ 309 static const struct pci_class pci_interface_pic[] = { 310 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 311 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 312 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 313 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 314 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 315 { NULL, 0, NULL, }, 316 }; 317 318 /* DMA programming interface */ 319 static const struct pci_class pci_interface_dma[] = { 320 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 321 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 322 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 323 { NULL, 0, NULL, }, 324 }; 325 326 /* Timer programming interface */ 327 static const struct pci_class pci_interface_tmr[] = { 328 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 329 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 330 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 331 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 332 { NULL, 0, NULL, }, 333 }; 334 335 /* RTC programming interface */ 336 static const struct pci_class pci_interface_rtc[] = { 337 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 338 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 339 { NULL, 0, NULL, }, 340 }; 341 342 /* Subclasses */ 343 static const struct pci_class pci_subclass_system[] = { 344 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 345 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 346 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 347 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 348 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 349 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 350 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 351 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 352 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 353 { NULL, 0, NULL, }, 354 }; 355 356 /* 357 * Class 0x09. 358 * Input device. 359 */ 360 361 /* Gameport programming interface */ 362 static const struct pci_class pci_interface_game[] = { 363 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 364 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 365 { NULL, 0, NULL, }, 366 }; 367 368 /* Subclasses */ 369 static const struct pci_class pci_subclass_input[] = { 370 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 371 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 372 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 373 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 374 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 375 pci_interface_game, }, 376 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 377 { NULL, 0, NULL, }, 378 }; 379 380 /* 381 * Class 0x0a. 382 * Docking station. 383 */ 384 static const struct pci_class pci_subclass_dock[] = { 385 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 386 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 387 { NULL, 0, NULL, }, 388 }; 389 390 /* 391 * Class 0x0b. 392 * Processor. 393 */ 394 static const struct pci_class pci_subclass_processor[] = { 395 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 396 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 397 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 398 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 399 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 400 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 401 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 402 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 403 { NULL, 0, NULL, }, 404 }; 405 406 /* 407 * Class 0x0c. 408 * Serial bus controller. 409 */ 410 411 /* IEEE1394 programming interface */ 412 static const struct pci_class pci_interface_ieee1394[] = { 413 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 414 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 415 { NULL, 0, NULL,}, 416 }; 417 418 /* USB programming interface */ 419 static const struct pci_class pci_interface_usb[] = { 420 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 421 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 422 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 423 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 424 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 425 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 426 { NULL, 0, NULL, }, 427 }; 428 429 /* IPMI programming interface */ 430 static const struct pci_class pci_interface_ipmi[] = { 431 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 432 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 433 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 434 { NULL, 0, NULL,}, 435 }; 436 437 /* Subclasses */ 438 static const struct pci_class pci_subclass_serialbus[] = { 439 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 440 pci_interface_ieee1394, }, 441 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 442 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 443 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 444 pci_interface_usb, }, 445 /* XXX Fiber Channel/_FIBRECHANNEL */ 446 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 447 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 448 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 449 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 450 pci_interface_ipmi, }, 451 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 452 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 453 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 454 { NULL, 0, NULL, }, 455 }; 456 457 /* 458 * Class 0x0d. 459 * Wireless Controller. 460 */ 461 static const struct pci_class pci_subclass_wireless[] = { 462 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 463 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 464 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 465 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 466 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 467 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 468 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 469 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 470 { NULL, 0, NULL, }, 471 }; 472 473 /* 474 * Class 0x0e. 475 * Intelligent IO controller. 476 */ 477 478 /* Intelligent IO programming interface */ 479 static const struct pci_class pci_interface_i2o[] = { 480 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 481 { NULL, 0, NULL,}, 482 }; 483 484 /* Subclasses */ 485 static const struct pci_class pci_subclass_i2o[] = { 486 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 487 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 488 { NULL, 0, NULL, }, 489 }; 490 491 /* 492 * Class 0x0f. 493 * Satellite communication controller. 494 */ 495 static const struct pci_class pci_subclass_satcom[] = { 496 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 497 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 498 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 499 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 500 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 501 { NULL, 0, NULL, }, 502 }; 503 504 /* 505 * Class 0x10. 506 * Encryption/Decryption controller. 507 */ 508 static const struct pci_class pci_subclass_crypto[] = { 509 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 510 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 511 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 512 { NULL, 0, NULL, }, 513 }; 514 515 /* 516 * Class 0x11. 517 * Data aquuisition and signal processing controller. 518 */ 519 static const struct pci_class pci_subclass_dasp[] = { 520 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 521 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 522 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 523 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 524 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 525 { NULL, 0, NULL, }, 526 }; 527 528 /* List of classes */ 529 static const struct pci_class pci_classes[] = { 530 { "prehistoric", PCI_CLASS_PREHISTORIC, 531 pci_subclass_prehistoric, }, 532 { "mass storage", PCI_CLASS_MASS_STORAGE, 533 pci_subclass_mass_storage, }, 534 { "network", PCI_CLASS_NETWORK, 535 pci_subclass_network, }, 536 { "display", PCI_CLASS_DISPLAY, 537 pci_subclass_display, }, 538 { "multimedia", PCI_CLASS_MULTIMEDIA, 539 pci_subclass_multimedia, }, 540 { "memory", PCI_CLASS_MEMORY, 541 pci_subclass_memory, }, 542 { "bridge", PCI_CLASS_BRIDGE, 543 pci_subclass_bridge, }, 544 { "communications", PCI_CLASS_COMMUNICATIONS, 545 pci_subclass_communications, }, 546 { "system", PCI_CLASS_SYSTEM, 547 pci_subclass_system, }, 548 { "input", PCI_CLASS_INPUT, 549 pci_subclass_input, }, 550 { "dock", PCI_CLASS_DOCK, 551 pci_subclass_dock, }, 552 { "processor", PCI_CLASS_PROCESSOR, 553 pci_subclass_processor, }, 554 { "serial bus", PCI_CLASS_SERIALBUS, 555 pci_subclass_serialbus, }, 556 { "wireless", PCI_CLASS_WIRELESS, 557 pci_subclass_wireless, }, 558 { "I2O", PCI_CLASS_I2O, 559 pci_subclass_i2o, }, 560 { "satellite comm", PCI_CLASS_SATCOM, 561 pci_subclass_satcom, }, 562 { "crypto", PCI_CLASS_CRYPTO, 563 pci_subclass_crypto, }, 564 { "DASP", PCI_CLASS_DASP, 565 pci_subclass_dasp, }, 566 { "processing accelerators", PCI_CLASS_ACCEL, 567 NULL, }, 568 { "non-essential instrumentation", PCI_CLASS_INSTRUMENT, 569 NULL, }, 570 { "undefined", PCI_CLASS_UNDEFINED, 571 NULL, }, 572 { NULL, 0, 573 NULL, }, 574 }; 575 576 DEV_VERBOSE_DEFINE(pci); 577 578 /* 579 * Append a formatted string to dest without writing more than len 580 * characters (including the trailing NUL character). dest and len 581 * are updated for use in subsequent calls to snappendf(). 582 * 583 * Returns 0 on success, a negative value if vnsprintf() fails, or 584 * a positive value if the dest buffer would have overflowed. 585 */ 586 587 static int __printflike(3,4) 588 snappendf(char **dest, size_t *len, const char * restrict fmt, ...) 589 { 590 va_list ap; 591 int count; 592 593 va_start(ap, fmt); 594 count = vsnprintf(*dest, *len, fmt, ap); 595 va_end(ap); 596 597 /* Let vsnprintf() errors bubble up to caller */ 598 if (count < 0 || *len == 0) 599 return count; 600 601 /* Handle overflow */ 602 if ((size_t)count >= *len) { 603 *dest += *len - 1; 604 *len = 1; 605 return 1; 606 } 607 608 /* Update dest & len to point at trailing NUL */ 609 *dest += count; 610 *len -= count; 611 612 return 0; 613 } 614 615 void 616 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 617 size_t l) 618 { 619 pci_class_t class; 620 pci_subclass_t subclass; 621 pci_interface_t interface; 622 pci_revision_t revision; 623 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 624 const struct pci_class *classp, *subclassp, *interfacep; 625 626 class = PCI_CLASS(class_reg); 627 subclass = PCI_SUBCLASS(class_reg); 628 interface = PCI_INTERFACE(class_reg); 629 revision = PCI_REVISION(class_reg); 630 631 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 632 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 633 PCI_PRODUCT(id_reg)); 634 635 classp = pci_classes; 636 while (classp->name != NULL) { 637 if (class == classp->val) 638 break; 639 classp++; 640 } 641 642 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 643 while (subclassp && subclassp->name != NULL) { 644 if (subclass == subclassp->val) 645 break; 646 subclassp++; 647 } 648 649 interfacep = (subclassp && subclassp->name != NULL) ? 650 subclassp->subclasses : NULL; 651 while (interfacep && interfacep->name != NULL) { 652 if (interface == interfacep->val) 653 break; 654 interfacep++; 655 } 656 657 (void)snappendf(&cp, &l, "%s %s", vendor, product); 658 if (showclass) { 659 (void)snappendf(&cp, &l, " ("); 660 if (classp->name == NULL) 661 (void)snappendf(&cp, &l, 662 "class 0x%02x, subclass 0x%02x", 663 class, subclass); 664 else { 665 if (subclassp == NULL || subclassp->name == NULL) 666 (void)snappendf(&cp, &l, 667 "%s, subclass 0x%02x", 668 classp->name, subclass); 669 else 670 (void)snappendf(&cp, &l, "%s %s", 671 subclassp->name, classp->name); 672 } 673 if ((interfacep == NULL) || (interfacep->name == NULL)) { 674 if (interface != 0) 675 (void)snappendf(&cp, &l, ", interface 0x%02x", 676 interface); 677 } else if (strncmp(interfacep->name, "", 1) != 0) 678 (void)snappendf(&cp, &l, ", %s", interfacep->name); 679 if (revision != 0) 680 (void)snappendf(&cp, &l, ", revision 0x%02x", revision); 681 (void)snappendf(&cp, &l, ")"); 682 } 683 } 684 685 #ifdef _KERNEL 686 void 687 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 688 const char *known, int addrev) 689 { 690 char devinfo[256]; 691 692 if (known) { 693 aprint_normal(": %s", known); 694 if (addrev) 695 aprint_normal(" (rev. 0x%02x)", 696 PCI_REVISION(pa->pa_class)); 697 aprint_normal("\n"); 698 } else { 699 pci_devinfo(pa->pa_id, pa->pa_class, 0, 700 devinfo, sizeof(devinfo)); 701 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 702 PCI_REVISION(pa->pa_class)); 703 } 704 if (naive) 705 aprint_naive(": %s\n", naive); 706 else 707 aprint_naive("\n"); 708 } 709 #endif 710 711 /* 712 * Print out most of the PCI configuration registers. Typically used 713 * in a device attach routine like this: 714 * 715 * #ifdef MYDEV_DEBUG 716 * printf("%s: ", device_xname(sc->sc_dev)); 717 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 718 * #endif 719 */ 720 721 #define i2o(i) ((i) * 4) 722 #define o2i(o) ((o) / 4) 723 #define onoff2(str, rval, bit, onstr, offstr) \ 724 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 725 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 726 727 static void 728 pci_conf_print_common( 729 #ifdef _KERNEL 730 pci_chipset_tag_t pc, pcitag_t tag, 731 #endif 732 const pcireg_t *regs) 733 { 734 pci_class_t class; 735 pci_subclass_t subclass; 736 pci_interface_t interface; 737 pci_revision_t revision; 738 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 739 const struct pci_class *classp, *subclassp, *interfacep; 740 const char *name; 741 pcireg_t rval; 742 unsigned int num; 743 744 rval = regs[o2i(PCI_CLASS_REG)]; 745 class = PCI_CLASS(rval); 746 subclass = PCI_SUBCLASS(rval); 747 interface = PCI_INTERFACE(rval); 748 revision = PCI_REVISION(rval); 749 750 rval = regs[o2i(PCI_ID_REG)]; 751 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 752 if (name) 753 printf(" Vendor Name: %s (0x%04x)\n", name, 754 PCI_VENDOR(rval)); 755 else 756 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 757 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 758 PCI_PRODUCT(rval)); 759 if (name) 760 printf(" Device Name: %s (0x%04x)\n", name, 761 PCI_PRODUCT(rval)); 762 else 763 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 764 765 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 766 767 printf(" Command register: 0x%04x\n", rval & 0xffff); 768 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 769 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 770 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 771 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 772 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 773 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 774 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 775 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 776 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 777 onoff("Fast back-to-back transactions", rval, 778 PCI_COMMAND_BACKTOBACK_ENABLE); 779 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 780 781 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 782 onoff("Immediate Readiness", rval, PCI_STATUS_IMMD_READNESS); 783 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 784 "inactive"); 785 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 786 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 787 onoff("User Definable Features (UDF) support", rval, 788 PCI_STATUS_UDF_SUPPORT); 789 onoff("Fast back-to-back capable", rval, 790 PCI_STATUS_BACKTOBACK_SUPPORT); 791 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 792 793 printf(" DEVSEL timing: "); 794 switch (rval & PCI_STATUS_DEVSEL_MASK) { 795 case PCI_STATUS_DEVSEL_FAST: 796 printf("fast"); 797 break; 798 case PCI_STATUS_DEVSEL_MEDIUM: 799 printf("medium"); 800 break; 801 case PCI_STATUS_DEVSEL_SLOW: 802 printf("slow"); 803 break; 804 default: 805 printf("unknown/reserved"); /* XXX */ 806 break; 807 } 808 printf(" (0x%x)\n", __SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK)); 809 810 onoff("Slave signaled Target Abort", rval, 811 PCI_STATUS_TARGET_TARGET_ABORT); 812 onoff("Master received Target Abort", rval, 813 PCI_STATUS_MASTER_TARGET_ABORT); 814 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 815 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 816 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 817 818 rval = regs[o2i(PCI_CLASS_REG)]; 819 for (classp = pci_classes; classp->name != NULL; classp++) { 820 if (class == classp->val) 821 break; 822 } 823 824 /* 825 * ECN: Change Root Complex Event Collector Class Code 826 * Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type 827 * in PCIe extend capability to know whether it's RCEC or IOMMU. 828 */ 829 if ((class == PCI_CLASS_SYSTEM) 830 && (subclass == PCI_SUBCLASS_SYSTEM_IOMMU)) { 831 int pcie_capoff; 832 pcireg_t reg; 833 834 if (pci_conf_find_cap(regs, PCI_CAPLISTPTR_REG, 835 PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 836 reg = regs[o2i(pcie_capoff + PCIE_XCAP)]; 837 if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_ROOT_EVNTC) 838 subclass = PCI_SUBCLASS_SYSTEM_RCEC; 839 } 840 } 841 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 842 while (subclassp && subclassp->name != NULL) { 843 if (subclass == subclassp->val) 844 break; 845 subclassp++; 846 } 847 848 interfacep = (subclassp && subclassp->name != NULL) ? 849 subclassp->subclasses : NULL; 850 while (interfacep && interfacep->name != NULL) { 851 if (interface == interfacep->val) 852 break; 853 interfacep++; 854 } 855 856 if (classp->name != NULL) 857 printf(" Class Name: %s (0x%02x)\n", classp->name, class); 858 else 859 printf(" Class ID: 0x%02x\n", class); 860 if (subclassp != NULL && subclassp->name != NULL) 861 printf(" Subclass Name: %s (0x%02x)\n", 862 subclassp->name, PCI_SUBCLASS(rval)); 863 else 864 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 865 if ((interfacep != NULL) && (interfacep->name != NULL) 866 && (strncmp(interfacep->name, "", 1) != 0)) 867 printf(" Interface Name: %s (0x%02x)\n", 868 interfacep->name, interface); 869 else 870 printf(" Interface: 0x%02x\n", interface); 871 printf(" Revision ID: 0x%02x\n", revision); 872 873 rval = regs[o2i(PCI_BHLC_REG)]; 874 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 875 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 876 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 877 PCI_HDRTYPE(rval)); 878 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 879 num = PCI_CACHELINE(rval); 880 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 881 } 882 883 static int 884 pci_conf_print_bar( 885 #ifdef _KERNEL 886 pci_chipset_tag_t pc, pcitag_t tag, 887 #endif 888 const pcireg_t *regs, int reg, const char *name) 889 { 890 int width; 891 pcireg_t rval, rval64h; 892 bool ioen, memen; 893 #ifdef _KERNEL 894 pcireg_t mask, mask64h = 0; 895 #endif 896 897 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 898 ioen = rval & PCI_COMMAND_IO_ENABLE; 899 memen = rval & PCI_COMMAND_MEM_ENABLE; 900 901 width = 4; 902 /* 903 * Section 6.2.5.1, `Address Maps', tells us that: 904 * 905 * 1) The builtin software should have already mapped the 906 * device in a reasonable way. 907 * 908 * 2) A device which wants 2^n bytes of memory will hardwire 909 * the bottom n bits of the address to 0. As recommended, 910 * we write all 1s and see what we get back. 911 */ 912 913 rval = regs[o2i(reg)]; 914 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 915 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 916 rval64h = regs[o2i(reg + 4)]; 917 width = 8; 918 } else 919 rval64h = 0; 920 921 #ifdef _KERNEL 922 if (rval != 0 && memen) { 923 int s; 924 925 /* 926 * The following sequence seems to make some devices 927 * (e.g. host bus bridges, which don't normally 928 * have their space mapped) very unhappy, to 929 * the point of crashing the system. 930 * 931 * Therefore, if the mapping register is zero to 932 * start out with, don't bother trying. 933 */ 934 s = splhigh(); 935 pci_conf_write(pc, tag, reg, 0xffffffff); 936 mask = pci_conf_read(pc, tag, reg); 937 pci_conf_write(pc, tag, reg, rval); 938 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 939 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 940 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 941 mask64h = pci_conf_read(pc, tag, reg + 4); 942 pci_conf_write(pc, tag, reg + 4, rval64h); 943 } 944 splx(s); 945 } else 946 mask = mask64h = 0; 947 #endif /* _KERNEL */ 948 949 printf(" Base address register at 0x%02x", reg); 950 if (name) 951 printf(" (%s)", name); 952 printf("\n "); 953 if (rval == 0) { 954 printf("not implemented\n"); 955 return width; 956 } 957 printf("type: "); 958 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 959 const char *type, *prefetch; 960 961 switch (PCI_MAPREG_MEM_TYPE(rval)) { 962 case PCI_MAPREG_MEM_TYPE_32BIT: 963 type = "32-bit"; 964 break; 965 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 966 type = "32-bit-1M"; 967 break; 968 case PCI_MAPREG_MEM_TYPE_64BIT: 969 type = "64-bit"; 970 break; 971 default: 972 type = "unknown (XXX)"; 973 break; 974 } 975 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 976 prefetch = ""; 977 else 978 prefetch = "non"; 979 printf("%s %sprefetchable memory\n", type, prefetch); 980 switch (PCI_MAPREG_MEM_TYPE(rval)) { 981 case PCI_MAPREG_MEM_TYPE_64BIT: 982 printf(" base: 0x%016llx", 983 PCI_MAPREG_MEM64_ADDR( 984 ((((long long) rval64h) << 32) | rval))); 985 if (!memen) 986 printf(", disabled"); 987 printf("\n"); 988 #ifdef _KERNEL 989 printf(" size: 0x%016llx\n", 990 PCI_MAPREG_MEM64_SIZE( 991 ((((long long) mask64h) << 32) | mask))); 992 #endif 993 break; 994 case PCI_MAPREG_MEM_TYPE_32BIT: 995 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 996 default: 997 printf(" base: 0x%08x", 998 PCI_MAPREG_MEM_ADDR(rval)); 999 if (!memen) 1000 printf(", disabled"); 1001 printf("\n"); 1002 #ifdef _KERNEL 1003 printf(" size: 0x%08x\n", 1004 PCI_MAPREG_MEM_SIZE(mask)); 1005 #endif 1006 break; 1007 } 1008 } else { 1009 #ifdef _KERNEL 1010 if (ioen) 1011 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 1012 #endif 1013 printf("I/O\n"); 1014 printf(" base: 0x%08x", PCI_MAPREG_IO_ADDR(rval)); 1015 if (!ioen) 1016 printf(", disabled"); 1017 printf("\n"); 1018 #ifdef _KERNEL 1019 printf(" size: 0x%08x\n", PCI_MAPREG_IO_SIZE(mask)); 1020 #endif 1021 } 1022 1023 return width; 1024 } 1025 1026 static void 1027 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 1028 { 1029 int off, needaddr, neednl; 1030 1031 needaddr = 1; 1032 neednl = 0; 1033 for (off = first; off < pastlast; off += 4) { 1034 if ((off % 16) == 0 || needaddr) { 1035 printf(" 0x%02x:", off); 1036 needaddr = 0; 1037 } 1038 printf(" 0x%08x", regs[o2i(off)]); 1039 neednl = 1; 1040 if ((off % 16) == 12) { 1041 printf("\n"); 1042 neednl = 0; 1043 } 1044 } 1045 if (neednl) 1046 printf("\n"); 1047 } 1048 1049 static const char * 1050 pci_conf_print_agp_calcycle(uint8_t cal) 1051 { 1052 1053 switch (cal) { 1054 case 0x0: 1055 return "4ms"; 1056 case 0x1: 1057 return "16ms"; 1058 case 0x2: 1059 return "64ms"; 1060 case 0x3: 1061 return "256ms"; 1062 case 0x7: 1063 return "Calibration Cycle Not Needed"; 1064 default: 1065 return "(reserved)"; 1066 } 1067 } 1068 1069 static void 1070 pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3) 1071 { 1072 if (isagp3) { 1073 /* AGP 3.0 */ 1074 if (reg & AGP_MODE_V3_RATE_4x) 1075 printf("x4"); 1076 if (reg & AGP_MODE_V3_RATE_8x) 1077 printf("x8"); 1078 } else { 1079 /* AGP 2.0 */ 1080 if (reg & AGP_MODE_V2_RATE_1x) 1081 printf("x1"); 1082 if (reg & AGP_MODE_V2_RATE_2x) 1083 printf("x2"); 1084 if (reg & AGP_MODE_V2_RATE_4x) 1085 printf("x4"); 1086 } 1087 printf("\n"); 1088 } 1089 1090 static void 1091 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1092 { 1093 pcireg_t rval; 1094 bool isagp3; 1095 1096 printf("\n AGP Capabilities Register\n"); 1097 1098 rval = regs[o2i(capoff)]; 1099 printf(" Revision: %d.%d\n", 1100 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1101 1102 rval = regs[o2i(capoff + PCI_AGP_STATUS)]; 1103 printf(" Status register: 0x%04x\n", rval); 1104 printf(" RQ: %d\n", 1105 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1106 printf(" ARQSZ: %d\n", 1107 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1108 printf(" CAL cycle: %s\n", 1109 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1110 onoff("SBA", rval, AGP_MODE_SBA); 1111 onoff("htrans#", rval, AGP_MODE_HTRANS); 1112 onoff("Over 4G", rval, AGP_MODE_4G); 1113 onoff("Fast Write", rval, AGP_MODE_FW); 1114 onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3); 1115 isagp3 = rval & AGP_MODE_MODE_3; 1116 printf(" Data Rate Support: "); 1117 pci_conf_print_agp_datarate(rval, isagp3); 1118 1119 rval = regs[o2i(capoff + PCI_AGP_COMMAND)]; 1120 printf(" Command register: 0x%08x\n", rval); 1121 printf(" PRQ: %d\n", 1122 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1123 printf(" PARQSZ: %d\n", 1124 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1125 printf(" PCAL cycle: %s\n", 1126 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1127 onoff("SBA", rval, AGP_MODE_SBA); 1128 onoff("AGP", rval, AGP_MODE_AGP); 1129 onoff("Over 4G", rval, AGP_MODE_4G); 1130 onoff("Fast Write", rval, AGP_MODE_FW); 1131 if (isagp3) { 1132 printf(" Data Rate Enable: "); 1133 /* 1134 * The Data Rate Enable bits are used only on 3.0 and the 1135 * Command register has no AGP_MODE_MODE_3 bit, so pass the 1136 * flag to print correctly. 1137 */ 1138 pci_conf_print_agp_datarate(rval, isagp3); 1139 } 1140 } 1141 1142 static const char * 1143 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1144 { 1145 1146 switch ((caps >> 6) & 7) { 1147 case 0: return "self-powered"; 1148 case 1: return "55 mA"; 1149 case 2: return "100 mA"; 1150 case 3: return "160 mA"; 1151 case 4: return "220 mA"; 1152 case 5: return "270 mA"; 1153 case 6: return "320 mA"; 1154 case 7: 1155 default: return "375 mA"; 1156 } 1157 } 1158 1159 static const char * 1160 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1161 { 1162 static const char unk[] = "unknown"; 1163 static const char *pmrev[8] = { 1164 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1165 }; 1166 if (val > 7) 1167 return unk; 1168 return pmrev[val]; 1169 } 1170 1171 static void 1172 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1173 { 1174 uint16_t caps, pmcsr; 1175 pcireg_t reg; 1176 1177 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1178 reg = regs[o2i(capoff + PCI_PMCSR)]; 1179 pmcsr = reg & 0xffff; 1180 1181 printf("\n PCI Power Management Capabilities Register\n"); 1182 1183 printf(" Capabilities register: 0x%04x\n", caps); 1184 printf(" Version: %s\n", 1185 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1186 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1187 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1188 printf(" 3.3V auxiliary current: %s\n", 1189 pci_conf_print_pcipm_cap_aux(caps)); 1190 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1191 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1192 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1193 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1194 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1195 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1196 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1197 1198 printf(" Control/status register: 0x%04x\n", pmcsr); 1199 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1200 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1201 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1202 printf(" PME# assertion: %sabled\n", 1203 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1204 printf(" Data Select: %d\n", 1205 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK)); 1206 printf(" Data Scale: %d\n", 1207 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK)); 1208 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1209 printf(" Bridge Support Extensions register: 0x%02x\n", 1210 (reg >> 16) & 0xff); 1211 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1212 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1213 printf(" Data register: 0x%02x\n", __SHIFTOUT(reg, PCI_PMCSR_DATA)); 1214 1215 } 1216 1217 /* XXX pci_conf_print_vpd_cap */ 1218 /* XXX pci_conf_print_slotid_cap */ 1219 1220 static void 1221 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1222 { 1223 uint32_t ctl, mmc, mme; 1224 1225 regs += o2i(capoff); 1226 ctl = *regs++; 1227 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1228 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1229 1230 printf("\n PCI Message Signaled Interrupt\n"); 1231 1232 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1233 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1234 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1235 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1236 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1237 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1238 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1239 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1240 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP); 1241 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN); 1242 printf(" Message Address %sregister: 0x%08x\n", 1243 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1244 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1245 printf(" Message Address %sregister: 0x%08x\n", 1246 "(upper) ", *regs++); 1247 } 1248 printf(" Message Data register: "); 1249 if (ctl & PCI_MSI_CTL_EXTMDATA_CAP) 1250 printf("0x%08x\n", *regs); 1251 else 1252 printf("0x%04x\n", *regs & 0xffff); 1253 regs++; 1254 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1255 printf(" Vector Mask register: 0x%08x\n", *regs++); 1256 printf(" Vector Pending register: 0x%08x\n", *regs++); 1257 } 1258 } 1259 1260 /* XXX pci_conf_print_cpci_hostwap_cap */ 1261 1262 /* 1263 * For both command register and status register. 1264 * The argument "idx" is index number (0 to 7). 1265 */ 1266 static int 1267 pcix_split_trans(unsigned int idx) 1268 { 1269 static int table[8] = { 1270 1, 2, 3, 4, 8, 12, 16, 32 1271 }; 1272 1273 if (idx >= __arraycount(table)) 1274 return -1; 1275 return table[idx]; 1276 } 1277 1278 static void 1279 pci_conf_print_pcix_cap_2ndbusmode(int num) 1280 { 1281 const char *maxfreq, *maxperiod; 1282 1283 printf(" Mode: "); 1284 if (num <= 0x07) 1285 printf("PCI-X Mode 1\n"); 1286 else if (num <= 0x0b) 1287 printf("PCI-X 266 (Mode 2)\n"); 1288 else 1289 printf("PCI-X 533 (Mode 2)\n"); 1290 1291 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1292 switch (num & 0x03) { 1293 default: 1294 case 0: 1295 maxfreq = "N/A"; 1296 maxperiod = "N/A"; 1297 break; 1298 case 1: 1299 maxfreq = "66MHz"; 1300 maxperiod = "15ns"; 1301 break; 1302 case 2: 1303 maxfreq = "100MHz"; 1304 maxperiod = "10ns"; 1305 break; 1306 case 3: 1307 maxfreq = "133MHz"; 1308 maxperiod = "7.5ns"; 1309 break; 1310 } 1311 printf(" Max Clock Freq: %s\n", maxfreq); 1312 printf(" Min Clock Period: %s\n", maxperiod); 1313 } 1314 1315 static void 1316 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1317 { 1318 pcireg_t reg; 1319 int isbridge; 1320 int i; 1321 1322 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1323 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1324 printf("\n PCI-X %s Capabilities Register\n", 1325 isbridge ? "Bridge" : "Non-bridge"); 1326 1327 reg = regs[o2i(capoff)]; 1328 if (isbridge != 0) { 1329 printf(" Secondary status register: 0x%04x\n", 1330 (reg & 0xffff0000) >> 16); 1331 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1332 onoff("133MHz capable", reg, PCIX_STATUS_133); 1333 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1334 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1335 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1336 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1337 pci_conf_print_pcix_cap_2ndbusmode( 1338 __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1339 printf(" Version: 0x%x\n", 1340 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1341 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1342 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1343 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1344 } else { 1345 printf(" Command register: 0x%04x\n", 1346 (reg & 0xffff0000) >> 16); 1347 onoff("Data Parity Error Recovery", reg, 1348 PCIX_CMD_PERR_RECOVER); 1349 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1350 printf(" Maximum Burst Read Count: %u\n", 1351 PCIX_CMD_BYTECNT(reg)); 1352 printf(" Maximum Split Transactions: %d\n", 1353 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1354 >> PCIX_CMD_SPLTRANS_SHIFT)); 1355 } 1356 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1357 printf(" %sStatus register: 0x%08x\n", 1358 isbridge ? "Bridge " : "", reg); 1359 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1360 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1361 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1362 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1363 onoff("133MHz capable", reg, PCIX_STATUS_133); 1364 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1365 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1366 if (isbridge != 0) { 1367 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1368 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1369 } else { 1370 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1371 "bridge device", "simple device"); 1372 printf(" Designed max memory read byte count: %d\n", 1373 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1374 >> PCIX_STATUS_MAXB_SHIFT)); 1375 printf(" Designed max outstanding split transaction: %d\n", 1376 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1377 >> PCIX_STATUS_MAXST_SHIFT)); 1378 printf(" MAX cumulative Read Size: %u\n", 1379 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1380 onoff("Received split completion error", reg, 1381 PCIX_STATUS_SCERR); 1382 } 1383 onoff("266MHz capable", reg, PCIX_STATUS_266); 1384 onoff("533MHz capable", reg, PCIX_STATUS_533); 1385 1386 if (isbridge == 0) 1387 return; 1388 1389 /* Only for bridge */ 1390 for (i = 0; i < 2; i++) { 1391 reg = regs[o2i(capoff + PCIX_BRIDGE_UP_STCR + (4 * i))]; 1392 printf(" %s split transaction control register: 0x%08x\n", 1393 (i == 0) ? "Upstream" : "Downstream", reg); 1394 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1395 printf(" Commitment Limit: %d\n", 1396 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1397 } 1398 } 1399 1400 /* pci_conf_print_ht_slave_cap */ 1401 /* pci_conf_print_ht_host_cap */ 1402 /* pci_conf_print_ht_switch_cap */ 1403 /* pci_conf_print_ht_intr_cap */ 1404 /* pci_conf_print_ht_revid_cap */ 1405 /* pci_conf_print_ht_unitid_cap */ 1406 /* pci_conf_print_ht_extcnf_cap */ 1407 /* pci_conf_print_ht_addrmap_cap */ 1408 /* pci_conf_print_ht_msimap_cap */ 1409 1410 static void 1411 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1412 { 1413 pcireg_t val; 1414 uint32_t lo, hi; 1415 1416 /* 1417 * Print the rest of the command register bits. Others are 1418 * printed in pci_conf_print_ht_cap(). 1419 */ 1420 val = regs[o2i(capoff + PCI_HT_CMD)]; 1421 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1422 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1423 1424 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1425 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1426 printf(" Address Low register: 0x%08x\n", lo); 1427 printf(" Address high register: 0x%08x\n", hi); 1428 printf(" Address: 0x%016" PRIx64 "\n", 1429 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1430 } 1431 1432 /* pci_conf_print_ht_droute_cap */ 1433 /* pci_conf_print_ht_vcset_cap */ 1434 /* pci_conf_print_ht_retry_cap */ 1435 /* pci_conf_print_ht_x86enc_cap */ 1436 /* pci_conf_print_ht_gen3_cap */ 1437 /* pci_conf_print_ht_fle_cap */ 1438 /* pci_conf_print_ht_pm_cap */ 1439 /* pci_conf_print_ht_hnc_cap */ 1440 1441 static const struct ht_types { 1442 pcireg_t cap; 1443 const char *name; 1444 void (*printfunc)(const pcireg_t *, int); 1445 } ht_captab[] = { 1446 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1447 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1448 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1449 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1450 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1451 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1452 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1453 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1454 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1455 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1456 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1457 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1458 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1459 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1460 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1461 {PCI_HT_CAP_PM, "Power Management", NULL }, 1462 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1463 }; 1464 1465 static void 1466 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1467 { 1468 pcireg_t val, foundcap; 1469 unsigned int off; 1470 1471 val = regs[o2i(capoff + PCI_HT_CMD)]; 1472 1473 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1474 1475 printf(" Command register: 0x%04x\n", val >> 16); 1476 foundcap = PCI_HT_CAP(val); 1477 for (off = 0; off < __arraycount(ht_captab); off++) { 1478 if (ht_captab[off].cap == foundcap) 1479 break; 1480 } 1481 printf(" Capability Type: 0x%02x ", foundcap); 1482 if (off >= __arraycount(ht_captab)) { 1483 printf("(unknown)\n"); 1484 return; 1485 } 1486 printf("(%s)\n", ht_captab[off].name); 1487 if (ht_captab[off].printfunc != NULL) 1488 ht_captab[off].printfunc(regs, capoff); 1489 } 1490 1491 static void 1492 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1493 { 1494 uint16_t caps; 1495 1496 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1497 1498 printf("\n PCI Vendor Specific Capabilities Register\n"); 1499 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1500 } 1501 1502 static void 1503 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1504 { 1505 pcireg_t val; 1506 1507 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1508 1509 printf("\n Debugport Capability Register\n"); 1510 printf(" Debug base Register: 0x%04x\n", 1511 val >> PCI_DEBUG_BASER_SHIFT); 1512 printf(" port offset: 0x%04x\n", 1513 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1514 printf(" BAR number: %u\n", 1515 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1516 } 1517 1518 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1519 /* XXX pci_conf_print_hotplug_cap */ 1520 1521 static void 1522 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1523 { 1524 pcireg_t reg; 1525 1526 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1527 1528 printf("\n Subsystem ID Capability Register\n"); 1529 printf(" Subsystem ID : 0x%08x\n", reg); 1530 } 1531 1532 /* XXX pci_conf_print_agp8_cap */ 1533 /* XXX pci_conf_print_secure_cap */ 1534 1535 static void 1536 pci_print_pcie_L0s_latency(uint32_t val) 1537 { 1538 1539 switch (val) { 1540 case 0x0: 1541 printf("Less than 64ns\n"); 1542 break; 1543 case 0x1: 1544 case 0x2: 1545 case 0x3: 1546 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1547 break; 1548 case 0x4: 1549 printf("512ns to less than 1us\n"); 1550 break; 1551 case 0x5: 1552 printf("1us to less than 2us\n"); 1553 break; 1554 case 0x6: 1555 printf("2us - 4us\n"); 1556 break; 1557 case 0x7: 1558 printf("More than 4us\n"); 1559 break; 1560 } 1561 } 1562 1563 static void 1564 pci_print_pcie_L1_latency(uint32_t val) 1565 { 1566 1567 switch (val) { 1568 case 0x0: 1569 printf("Less than 1us\n"); 1570 break; 1571 case 0x6: 1572 printf("32us - 64us\n"); 1573 break; 1574 case 0x7: 1575 printf("More than 64us\n"); 1576 break; 1577 default: 1578 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1579 break; 1580 } 1581 } 1582 1583 static void 1584 pci_print_pcie_compl_timeout(uint32_t val) 1585 { 1586 1587 switch (val) { 1588 case 0x0: 1589 printf("50us to 50ms\n"); 1590 break; 1591 case 0x5: 1592 printf("16ms to 55ms\n"); 1593 break; 1594 case 0x6: 1595 printf("65ms to 210ms\n"); 1596 break; 1597 case 0x9: 1598 printf("260ms to 900ms\n"); 1599 break; 1600 case 0xa: 1601 printf("1s to 3.5s\n"); 1602 break; 1603 default: 1604 printf("unknown %u value\n", val); 1605 break; 1606 } 1607 } 1608 1609 static const char * const pcie_linkspeeds[] = {"2.5", "2.5", "5.0", "8.0"}; 1610 1611 static void 1612 pci_print_pcie_linkspeed(pcireg_t val) 1613 { 1614 1615 if (val > __arraycount(pcie_linkspeeds)) 1616 printf("unknown value (%u)\n", val); 1617 else 1618 printf("%sGT/s\n", pcie_linkspeeds[val]); 1619 } 1620 1621 static void 1622 pci_print_pcie_linkspeedvector(pcireg_t val) 1623 { 1624 unsigned int i; 1625 1626 /* Start from 0 */ 1627 for (i = 0; i < 16; i++) 1628 if (((val >> i) & 0x01) != 0) { 1629 if (i >= __arraycount(pcie_linkspeeds)) 1630 printf(" unknown vector (0x%x)", 1 << i); 1631 else 1632 printf(" %sGT/s", pcie_linkspeeds[i]); 1633 } 1634 } 1635 1636 static void 1637 pci_print_pcie_link_deemphasis(pcireg_t val) 1638 { 1639 switch (val) { 1640 case 0: 1641 printf("-6dB"); 1642 break; 1643 case 1: 1644 printf("-3.5dB"); 1645 break; 1646 default: 1647 printf("(reserved value)"); 1648 } 1649 } 1650 1651 static void 1652 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1653 { 1654 pcireg_t reg; /* for each register */ 1655 pcireg_t val; /* for each bitfield */ 1656 bool check_link = true; 1657 bool check_slot = false; 1658 bool check_rootport = false; 1659 bool check_upstreamport = false; 1660 unsigned int pciever; 1661 unsigned int i; 1662 1663 printf("\n PCI Express Capabilities Register\n"); 1664 /* Capability Register */ 1665 reg = regs[o2i(capoff)]; 1666 printf(" Capability register: 0x%04x\n", reg >> 16); 1667 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1668 printf(" Capability version: %u\n", pciever); 1669 printf(" Device type: "); 1670 switch ((reg & 0x00f00000) >> 20) { 1671 case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */ 1672 printf("PCI Express Endpoint device\n"); 1673 check_upstreamport = true; 1674 break; 1675 case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */ 1676 printf("Legacy PCI Express Endpoint device\n"); 1677 check_upstreamport = true; 1678 break; 1679 case PCIE_XCAP_TYPE_ROOT: /* 0x4 */ 1680 printf("Root Port of PCI Express Root Complex\n"); 1681 check_slot = true; 1682 check_rootport = true; 1683 break; 1684 case PCIE_XCAP_TYPE_UP: /* 0x5 */ 1685 printf("Upstream Port of PCI Express Switch\n"); 1686 check_upstreamport = true; 1687 break; 1688 case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ 1689 printf("Downstream Port of PCI Express Switch\n"); 1690 check_slot = true; 1691 check_rootport = true; 1692 break; 1693 case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ 1694 printf("PCI Express to PCI/PCI-X Bridge\n"); 1695 check_upstreamport = true; 1696 break; 1697 case PCIE_XCAP_TYPE_PCI2PCIE: /* 0x8 */ 1698 printf("PCI/PCI-X to PCI Express Bridge\n"); 1699 /* Upstream port is not PCIe */ 1700 check_slot = true; 1701 break; 1702 case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */ 1703 printf("Root Complex Integrated Endpoint\n"); 1704 check_link = false; 1705 break; 1706 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */ 1707 printf("Root Complex Event Collector\n"); 1708 check_link = false; 1709 check_rootport = true; 1710 break; 1711 default: 1712 printf("unknown\n"); 1713 break; 1714 } 1715 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1716 printf(" Interrupt Message Number: 0x%02x\n", 1717 (unsigned int)__SHIFTOUT(reg, PCIE_XCAP_IRQ)); 1718 1719 /* Device Capability Register */ 1720 reg = regs[o2i(capoff + PCIE_DCAP)]; 1721 printf(" Device Capabilities Register: 0x%08x\n", reg); 1722 printf(" Max Payload Size Supported: %u bytes max\n", 1723 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1724 printf(" Phantom Functions Supported: "); 1725 switch (__SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) { 1726 case 0x0: 1727 printf("not available\n"); 1728 break; 1729 case 0x1: 1730 printf("MSB\n"); 1731 break; 1732 case 0x2: 1733 printf("two MSB\n"); 1734 break; 1735 case 0x3: 1736 printf("All three bits\n"); 1737 break; 1738 } 1739 printf(" Extended Tag Field Supported: %dbit\n", 1740 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1741 printf(" Endpoint L0 Acceptable Latency: "); 1742 pci_print_pcie_L0s_latency(__SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY)); 1743 printf(" Endpoint L1 Acceptable Latency: "); 1744 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY)); 1745 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1746 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1747 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1748 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1749 if (check_upstreamport) { 1750 printf(" Captured Slot Power Limit: "); 1751 pci_conf_print_pcie_power( 1752 __SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL), 1753 __SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE)); 1754 } 1755 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1756 1757 /* Device Control Register */ 1758 reg = regs[o2i(capoff + PCIE_DCSR)]; 1759 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1760 onoff("Correctable Error Reporting Enable", reg, 1761 PCIE_DCSR_ENA_COR_ERR); 1762 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1763 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1764 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1765 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1766 printf(" Max Payload Size: %d byte\n", 1767 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD)); 1768 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1769 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1770 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1771 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1772 printf(" Max Read Request Size: %d byte\n", 1773 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ)); 1774 1775 /* Device Status Register */ 1776 reg = regs[o2i(capoff + PCIE_DCSR)]; 1777 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1778 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1779 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1780 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1781 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1782 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1783 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1784 onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD); 1785 1786 if (check_link) { 1787 /* Link Capability Register */ 1788 reg = regs[o2i(capoff + PCIE_LCAP)]; 1789 printf(" Link Capabilities Register: 0x%08x\n", reg); 1790 printf(" Maximum Link Speed: "); 1791 pci_print_pcie_linkspeed(reg & PCIE_LCAP_MAX_SPEED); 1792 printf(" Maximum Link Width: x%u lanes\n", 1793 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH)); 1794 printf(" Active State PM Support: "); 1795 switch (__SHIFTOUT(reg, PCIE_LCAP_ASPM)) { 1796 case 0x0: 1797 printf("No ASPM support\n"); 1798 break; 1799 case 0x1: 1800 printf("L0s supported\n"); 1801 break; 1802 case 0x2: 1803 printf("L1 supported\n"); 1804 break; 1805 case 0x3: 1806 printf("L0s and L1 supported\n"); 1807 break; 1808 } 1809 printf(" L0 Exit Latency: "); 1810 pci_print_pcie_L0s_latency(__SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT)); 1811 printf(" L1 Exit Latency: "); 1812 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_LCAP_L1_EXIT)); 1813 printf(" Port Number: %u\n", 1814 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_PORT)); 1815 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1816 onoff("Surprise Down Error Report", reg, 1817 PCIE_LCAP_SURPRISE_DOWN); 1818 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1819 onoff("Link BW Notification Capable", reg, 1820 PCIE_LCAP_LINK_BW_NOTIFY); 1821 onoff("ASPM Optionally Compliance", reg, 1822 PCIE_LCAP_ASPM_COMPLIANCE); 1823 1824 /* Link Control Register */ 1825 reg = regs[o2i(capoff + PCIE_LCSR)]; 1826 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1827 printf(" Active State PM Control: "); 1828 switch (reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S)) { 1829 case 0: 1830 printf("disabled\n"); 1831 break; 1832 case 1: 1833 printf("L0s Entry Enabled\n"); 1834 break; 1835 case 2: 1836 printf("L1 Entry Enabled\n"); 1837 break; 1838 case 3: 1839 printf("L0s and L1 Entry Enabled\n"); 1840 break; 1841 } 1842 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1843 "128bytes", "64bytes"); 1844 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1845 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1846 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1847 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1848 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1849 onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD); 1850 onoff("Link Bandwidth Management Interrupt Enable", reg, 1851 PCIE_LCSR_LBMIE); 1852 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1853 PCIE_LCSR_LABIE); 1854 printf(" DRS Signaling Control: "); 1855 switch (__SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) { 1856 case 0: 1857 printf("not reported\n"); 1858 break; 1859 case 1: 1860 printf("Interrupt Enabled\n"); 1861 break; 1862 case 2: 1863 printf("DRS to FRS Signaling Enabled\n"); 1864 break; 1865 default: 1866 printf("reserved\n"); 1867 break; 1868 } 1869 1870 /* Link Status Register */ 1871 reg = regs[o2i(capoff + PCIE_LCSR)]; 1872 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1873 printf(" Negotiated Link Speed: "); 1874 pci_print_pcie_linkspeed(__SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 1875 printf(" Negotiated Link Width: x%u lanes\n", 1876 (unsigned int)__SHIFTOUT(reg, PCIE_LCSR_NLW)); 1877 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1878 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1879 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1880 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1881 onoff("Link Bandwidth Management Status", reg, 1882 PCIE_LCSR_LINK_BW_MGMT); 1883 onoff("Link Autonomous Bandwidth Status", reg, 1884 PCIE_LCSR_LINK_AUTO_BW); 1885 } 1886 1887 if (check_slot == true) { 1888 /* Slot Capability Register */ 1889 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1890 printf(" Slot Capability Register: 0x%08x\n", reg); 1891 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1892 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1893 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1894 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1895 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1896 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1897 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1898 printf(" Slot Power Limit Value: "); 1899 pci_conf_print_pcie_power(__SHIFTOUT(reg, PCIE_SLCAP_SPLV), 1900 __SHIFTOUT(reg, PCIE_SLCAP_SPLS)); 1901 onoff("Electromechanical Interlock Present", reg, 1902 PCIE_SLCAP_EIP); 1903 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1904 printf(" Physical Slot Number: %d\n", 1905 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1906 1907 /* Slot Control Register */ 1908 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1909 printf(" Slot Control Register: 0x%04x\n", reg & 0xffff); 1910 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1911 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1912 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1913 onoff("Presence Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1914 onoff("Command Completed Interrupt Enabled", reg, 1915 PCIE_SLCSR_CCE); 1916 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1917 printf(" Attention Indicator Control: "); 1918 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1919 case 0x0: 1920 printf("reserved\n"); 1921 break; 1922 case PCIE_SLCSR_IND_ON: 1923 printf("on\n"); 1924 break; 1925 case PCIE_SLCSR_IND_BLINK: 1926 printf("blink\n"); 1927 break; 1928 case PCIE_SLCSR_IND_OFF: 1929 printf("off\n"); 1930 break; 1931 } 1932 printf(" Power Indicator Control: "); 1933 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1934 case 0x0: 1935 printf("reserved\n"); 1936 break; 1937 case PCIE_SLCSR_IND_ON: 1938 printf("on\n"); 1939 break; 1940 case PCIE_SLCSR_IND_BLINK: 1941 printf("blink\n"); 1942 break; 1943 case PCIE_SLCSR_IND_OFF: 1944 printf("off\n"); 1945 break; 1946 } 1947 printf(" Power Controller Control: Power %s\n", 1948 reg & PCIE_SLCSR_PCC ? "off" : "on"); 1949 onoff("Electromechanical Interlock Control", 1950 reg, PCIE_SLCSR_EIC); 1951 onoff("Data Link Layer State Changed Enable", reg, 1952 PCIE_SLCSR_DLLSCE); 1953 onoff("Auto Slot Power Limit Disable", reg, 1954 PCIE_SLCSR_AUTOSPLDIS); 1955 1956 /* Slot Status Register */ 1957 printf(" Slot Status Register: 0x%04x\n", reg >> 16); 1958 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1959 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1960 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1961 onoff("Presence Detect Changed", reg, PCIE_SLCSR_PDC); 1962 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1963 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1964 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1965 onoff("Electromechanical Interlock engaged", reg, 1966 PCIE_SLCSR_EIS); 1967 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 1968 } 1969 1970 if (check_rootport == true) { 1971 /* Root Control Register */ 1972 reg = regs[o2i(capoff + PCIE_RCR)]; 1973 printf(" Root Control Register: 0x%04x\n", reg & 0xffff); 1974 onoff("SERR on Correctable Error Enable", reg, 1975 PCIE_RCR_SERR_CER); 1976 onoff("SERR on Non-Fatal Error Enable", reg, 1977 PCIE_RCR_SERR_NFER); 1978 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 1979 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 1980 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 1981 1982 /* Root Capability Register */ 1983 printf(" Root Capability Register: 0x%04x\n", 1984 reg >> 16); 1985 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 1986 1987 /* Root Status Register */ 1988 reg = regs[o2i(capoff + PCIE_RSR)]; 1989 printf(" Root Status Register: 0x%08x\n", reg); 1990 printf(" PME Requester ID: 0x%04x\n", 1991 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1992 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 1993 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 1994 } 1995 1996 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1997 if (pciever < 2) 1998 return; 1999 2000 /* Device Capabilities 2 */ 2001 reg = regs[o2i(capoff + PCIE_DCAP2)]; 2002 printf(" Device Capabilities 2: 0x%08x\n", reg); 2003 printf(" Completion Timeout Ranges Supported: "); 2004 val = reg & PCIE_DCAP2_COMPT_RANGE; 2005 switch (val) { 2006 case 0: 2007 printf("not supported\n"); 2008 break; 2009 default: 2010 for (i = 0; i <= 3; i++) { 2011 if (((val >> i) & 0x01) != 0) 2012 printf("%c", 'A' + i); 2013 } 2014 printf("\n"); 2015 } 2016 onoff("Completion Timeout Disable Supported", reg, 2017 PCIE_DCAP2_COMPT_DIS); 2018 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 2019 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 2020 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 2021 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 2022 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 2023 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 2024 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 2025 printf(" TPH Completer Supported: "); 2026 switch (__SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) { 2027 case 0: 2028 printf("Not supported\n"); 2029 break; 2030 case 1: 2031 printf("TPH\n"); 2032 break; 2033 case 3: 2034 printf("TPH and Extended TPH\n"); 2035 break; 2036 default: 2037 printf("(reserved value)\n"); 2038 break; 2039 2040 } 2041 printf(" LN System CLS: "); 2042 switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 2043 case 0x0: 2044 printf("Not supported or not in effect\n"); 2045 break; 2046 case 0x1: 2047 printf("64byte cachelines in effect\n"); 2048 break; 2049 case 0x2: 2050 printf("128byte cachelines in effect\n"); 2051 break; 2052 case 0x3: 2053 printf("Reserved\n"); 2054 break; 2055 } 2056 printf(" OBFF Supported: "); 2057 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 2058 case 0x0: 2059 printf("Not supported\n"); 2060 break; 2061 case 0x1: 2062 printf("Message only\n"); 2063 break; 2064 case 0x2: 2065 printf("WAKE# only\n"); 2066 break; 2067 case 0x3: 2068 printf("Both\n"); 2069 break; 2070 } 2071 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 2072 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 2073 val = __SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP); 2074 printf(" Max End-End TLP Prefixes: %u\n", (val == 0) ? 4 : val); 2075 printf(" Emergency Power Reduction Supported: "); 2076 switch (__SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) { 2077 case 0x0: 2078 printf("Not supported\n"); 2079 break; 2080 case 0x1: 2081 printf("Device Specific mechanism\n"); 2082 break; 2083 case 0x2: 2084 printf("Form Factor spec or Device Specific mechanism\n"); 2085 break; 2086 case 0x3: 2087 printf("Reserved\n"); 2088 break; 2089 } 2090 onoff("Emergency Power Reduction Initialization Required", reg, 2091 PCIE_DCAP2_EMGPWRRED_INI); 2092 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 2093 2094 /* Device Control 2 */ 2095 reg = regs[o2i(capoff + PCIE_DCSR2)]; 2096 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 2097 printf(" Completion Timeout Value: "); 2098 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 2099 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 2100 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 2101 onoff("AtomicOp Requester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 2102 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 2103 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 2104 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 2105 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 2106 onoff("Emergency Power Reduction Request", reg, 2107 PCIE_DCSR2_EMGPWRRED_REQ); 2108 printf(" OBFF: "); 2109 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 2110 case 0x0: 2111 printf("Disabled\n"); 2112 break; 2113 case 0x1: 2114 printf("Enabled with Message Signaling Variation A\n"); 2115 break; 2116 case 0x2: 2117 printf("Enabled with Message Signaling Variation B\n"); 2118 break; 2119 case 0x3: 2120 printf("Enabled using WAKE# signaling\n"); 2121 break; 2122 } 2123 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 2124 2125 if (check_link) { 2126 bool drs_supported = false; 2127 2128 /* Link Capability 2 */ 2129 reg = regs[o2i(capoff + PCIE_LCAP2)]; 2130 /* If the vector is 0, LCAP2 is not implemented */ 2131 if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) { 2132 printf(" Link Capabilities 2: 0x%08x\n", reg); 2133 printf(" Supported Link Speeds Vector:"); 2134 pci_print_pcie_linkspeedvector( 2135 __SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 2136 printf("\n"); 2137 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 2138 printf(" " 2139 "Lower SKP OS Generation Supported Speed Vector:"); 2140 pci_print_pcie_linkspeedvector( 2141 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 2142 printf("\n"); 2143 printf(" " 2144 "Lower SKP OS Reception Supported Speed Vector:"); 2145 pci_print_pcie_linkspeedvector( 2146 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 2147 printf("\n"); 2148 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 2149 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 2150 } 2151 2152 /* Link Control 2 */ 2153 reg = regs[o2i(capoff + PCIE_LCSR2)]; 2154 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 2155 printf(" Target Link Speed: "); 2156 pci_print_pcie_linkspeed(__SHIFTOUT(reg, 2157 PCIE_LCSR2_TGT_LSPEED)); 2158 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 2159 onoff("HW Autonomous Speed Disabled", reg, 2160 PCIE_LCSR2_HW_AS_DIS); 2161 printf(" Selectable De-emphasis: "); 2162 pci_print_pcie_link_deemphasis( 2163 __SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP)); 2164 printf("\n"); 2165 printf(" Transmit Margin: %u\n", 2166 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 2167 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 2168 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 2169 printf(" Compliance Present/De-emphasis: "); 2170 pci_print_pcie_link_deemphasis( 2171 __SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP)); 2172 printf("\n"); 2173 2174 /* Link Status 2 */ 2175 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 2176 printf(" Current De-emphasis Level: "); 2177 pci_print_pcie_link_deemphasis( 2178 __SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL)); 2179 printf("\n"); 2180 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 2181 onoff("Equalization Phase 1 Successful", reg, 2182 PCIE_LCSR2_EQP1_SUC); 2183 onoff("Equalization Phase 2 Successful", reg, 2184 PCIE_LCSR2_EQP2_SUC); 2185 onoff("Equalization Phase 3 Successful", reg, 2186 PCIE_LCSR2_EQP3_SUC); 2187 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 2188 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 2189 if (drs_supported) { 2190 printf(" Downstream Component Presence: "); 2191 switch (__SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 2192 case PCIE_DSCOMPN_DOWN_NOTDETERM: 2193 printf("Link Down - Presence Not" 2194 " Determined\n"); 2195 break; 2196 case PCIE_DSCOMPN_DOWN_NOTPRES: 2197 printf("Link Down - Component Not Present\n"); 2198 break; 2199 case PCIE_DSCOMPN_DOWN_PRES: 2200 printf("Link Down - Component Present\n"); 2201 break; 2202 case PCIE_DSCOMPN_UP_PRES: 2203 printf("Link Up - Component Present\n"); 2204 break; 2205 case PCIE_DSCOMPN_UP_PRES_DRS: 2206 printf("Link Up - Component Present and DRS" 2207 " received\n"); 2208 break; 2209 default: 2210 printf("reserved\n"); 2211 break; 2212 } 2213 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 2214 } 2215 } 2216 2217 /* Slot Capability 2 */ 2218 /* Slot Control 2 */ 2219 /* Slot Status 2 */ 2220 } 2221 2222 static void 2223 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 2224 { 2225 pcireg_t reg; 2226 2227 printf("\n MSI-X Capability Register\n"); 2228 2229 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2230 printf(" Message Control register: 0x%04x\n", 2231 (reg >> 16) & 0xff); 2232 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 2233 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 2234 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 2235 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 2236 printf(" Table offset register: 0x%08x\n", reg); 2237 printf(" Table offset: 0x%08x\n", 2238 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 2239 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 2240 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 2241 printf(" Pending bit array register: 0x%08x\n", reg); 2242 printf(" Pending bit array offset: 0x%08x\n", 2243 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2244 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2245 } 2246 2247 static void 2248 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2249 { 2250 pcireg_t reg; 2251 2252 printf("\n Serial ATA Capability Register\n"); 2253 2254 reg = regs[o2i(capoff + PCI_SATA_REV)]; 2255 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2256 printf(" Revision: %u.%u\n", 2257 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2258 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2259 2260 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2261 2262 printf(" BAR Register: 0x%08x\n", reg); 2263 printf(" Register location: "); 2264 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2265 printf("in config space\n"); 2266 else { 2267 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2268 printf(" BAR offset: 0x%08x\n", 2269 (pcireg_t)__SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2270 } 2271 } 2272 2273 static void 2274 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2275 { 2276 pcireg_t reg; 2277 2278 printf("\n Advanced Features Capability Register\n"); 2279 2280 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2281 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2282 printf(" AF Structure Length: 0x%02x\n", 2283 (pcireg_t)__SHIFTOUT(reg, PCI_AF_LENGTH)); 2284 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2285 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2286 reg = regs[o2i(capoff + PCI_AFCSR)]; 2287 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2288 /* 2289 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2290 * and it's always 0 on read 2291 */ 2292 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2293 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2294 } 2295 2296 /* XXX pci_conf_print_ea_cap */ 2297 /* XXX pci_conf_print_fpb_cap */ 2298 2299 static struct { 2300 pcireg_t cap; 2301 const char *name; 2302 void (*printfunc)(const pcireg_t *, int); 2303 } pci_captab[] = { 2304 { PCI_CAP_RESERVED0, "reserved", NULL }, 2305 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2306 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2307 { PCI_CAP_VPD, "VPD", NULL }, 2308 { PCI_CAP_SLOTID, "SlotID", NULL }, 2309 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2310 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2311 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2312 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2313 { PCI_CAP_VENDSPEC, "Vendor-specific", 2314 pci_conf_print_vendspec_cap }, 2315 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2316 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2317 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2318 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2319 pci_conf_print_subsystem_cap }, 2320 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2321 { PCI_CAP_SECURE, "Secure Device", NULL }, 2322 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2323 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2324 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2325 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2326 { PCI_CAP_EA, "Enhanced Allocation", NULL }, 2327 { PCI_CAP_FPB, "Flattening Portal Bridge", NULL } 2328 }; 2329 2330 static int 2331 pci_conf_find_cap(const pcireg_t *regs, int capoff, unsigned int capid, 2332 int *offsetp) 2333 { 2334 pcireg_t rval; 2335 int off; 2336 2337 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2338 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2339 rval = regs[o2i(off)]; 2340 if (capid == PCI_CAPLIST_CAP(rval)) { 2341 if (offsetp != NULL) 2342 *offsetp = off; 2343 return 1; 2344 } 2345 } 2346 return 0; 2347 } 2348 2349 static void 2350 pci_conf_print_caplist( 2351 #ifdef _KERNEL 2352 pci_chipset_tag_t pc, pcitag_t tag, 2353 #endif 2354 const pcireg_t *regs, int capoff) 2355 { 2356 int off; 2357 pcireg_t foundcap; 2358 pcireg_t rval; 2359 bool foundtable[__arraycount(pci_captab)]; 2360 unsigned int i; 2361 2362 /* Clear table */ 2363 for (i = 0; i < __arraycount(pci_captab); i++) 2364 foundtable[i] = false; 2365 2366 /* Print capability register's offset and the type first */ 2367 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2368 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2369 rval = regs[o2i(off)]; 2370 printf(" Capability register at 0x%02x\n", off); 2371 2372 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2373 foundcap = PCI_CAPLIST_CAP(rval); 2374 if (foundcap < __arraycount(pci_captab)) { 2375 printf("%s)\n", pci_captab[foundcap].name); 2376 /* Mark as found */ 2377 foundtable[foundcap] = true; 2378 } else 2379 printf("unknown)\n"); 2380 } 2381 2382 /* 2383 * And then, print the detail of each capability registers 2384 * in capability value's order. 2385 */ 2386 for (i = 0; i < __arraycount(pci_captab); i++) { 2387 if (foundtable[i] == false) 2388 continue; 2389 2390 /* 2391 * The type was found. Search capability list again and 2392 * print all capabilities that the capabiliy type is 2393 * the same. This is required because some capabilities 2394 * appear multiple times (e.g. HyperTransport capability). 2395 */ 2396 #if 0 2397 if (pci_conf_find_cap(regs, capoff, i, &off)) { 2398 rval = regs[o2i(off)]; 2399 if (pci_captab[i].printfunc != NULL) 2400 pci_captab[i].printfunc(regs, off); 2401 } 2402 #else 2403 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2404 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2405 rval = regs[o2i(off)]; 2406 if ((PCI_CAPLIST_CAP(rval) == i) 2407 && (pci_captab[i].printfunc != NULL)) 2408 pci_captab[i].printfunc(regs, off); 2409 } 2410 #endif 2411 } 2412 } 2413 2414 /* Extended Capability */ 2415 2416 static void 2417 pci_conf_print_aer_cap_uc(pcireg_t reg) 2418 { 2419 2420 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2421 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2422 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2423 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2424 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2425 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2426 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2427 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2428 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2429 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2430 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2431 onoff("Unsupported Request Error", reg, 2432 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2433 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2434 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2435 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2436 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2437 onoff("TLP Prefix Blocked Error", reg, 2438 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2439 onoff("Poisoned TLP Egress Blocked", reg, 2440 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2441 } 2442 2443 static void 2444 pci_conf_print_aer_cap_cor(pcireg_t reg) 2445 { 2446 2447 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2448 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2449 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2450 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2451 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2452 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2453 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2454 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2455 } 2456 2457 static void 2458 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2459 { 2460 2461 printf(" First Error Pointer: 0x%04x\n", 2462 (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2463 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2464 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2465 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2466 onoff("ECRC Check Enable", reg, PCI_AER_ECRC_CHECK_ENABLE); 2467 onoff("Multiple Header Recording Capable", reg, 2468 PCI_AER_MULT_HDR_CAPABLE); 2469 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2470 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2471 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2472 2473 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2474 if (!tlp_prefix_log) 2475 return; 2476 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2477 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2478 } 2479 2480 static void 2481 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2482 { 2483 2484 onoff("Correctable Error Reporting Enable", reg, 2485 PCI_AER_ROOTERR_COR_ENABLE); 2486 onoff("Non-Fatal Error Reporting Enable", reg, 2487 PCI_AER_ROOTERR_NF_ENABLE); 2488 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2489 } 2490 2491 static void 2492 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2493 { 2494 2495 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2496 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2497 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2498 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2499 PCI_AER_ROOTERR_MULTI_UC_ERR); 2500 onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL); 2501 onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR); 2502 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2503 printf(" Advanced Error Interrupt Message Number: 0x%02x\n", 2504 (unsigned int)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2505 } 2506 2507 static void 2508 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2509 { 2510 2511 printf(" Correctable Source ID: 0x%04x\n", 2512 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2513 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2514 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2515 } 2516 2517 static void 2518 pci_conf_print_aer_cap(const pcireg_t *regs, int capoff, int extcapoff) 2519 { 2520 pcireg_t reg; 2521 int pcie_capoff; 2522 int pcie_devtype = -1; 2523 bool tlp_prefix_log = false; 2524 2525 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2526 reg = regs[o2i(pcie_capoff)]; 2527 pcie_devtype = PCIE_XCAP_TYPE(reg); 2528 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2529 if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2530 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2531 /* End-End TLP Prefix Supported */ 2532 if (reg & PCIE_DCAP2_EETLP_PREF) { 2533 tlp_prefix_log = true; 2534 } 2535 } 2536 } 2537 2538 printf("\n Advanced Error Reporting Register\n"); 2539 2540 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2541 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2542 pci_conf_print_aer_cap_uc(reg); 2543 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2544 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2545 pci_conf_print_aer_cap_uc(reg); 2546 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2547 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2548 pci_conf_print_aer_cap_uc(reg); 2549 2550 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2551 printf(" Correctable Error Status register: 0x%08x\n", reg); 2552 pci_conf_print_aer_cap_cor(reg); 2553 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2554 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2555 pci_conf_print_aer_cap_cor(reg); 2556 2557 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2558 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2559 reg); 2560 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2561 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2562 printf(" Header Log register:\n"); 2563 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2564 extcapoff + PCI_AER_ROOTERR_CMD); 2565 2566 switch (pcie_devtype) { 2567 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2568 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2569 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2570 printf(" Root Error Command register: 0x%08x\n", reg); 2571 pci_conf_print_aer_cap_rooterr_cmd(reg); 2572 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2573 printf(" Root Error Status register: 0x%08x\n", reg); 2574 pci_conf_print_aer_cap_rooterr_status(reg); 2575 2576 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2577 printf(" Error Source Identification: 0x%04x\n", reg); 2578 pci_conf_print_aer_cap_errsrc_id(reg); 2579 break; 2580 } 2581 2582 if (tlp_prefix_log) { 2583 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2584 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2585 } 2586 } 2587 2588 static void 2589 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2590 pcireg_t parbsel, int parbsize) 2591 { 2592 pcireg_t reg; 2593 int num = 16 << parbsel; 2594 int num_per_reg = sizeof(pcireg_t) / parbsize; 2595 int i, j; 2596 2597 /* First, dump the table */ 2598 for (i = 0; i < num; i += num_per_reg) { 2599 reg = regs[o2i(off + i / num_per_reg)]; 2600 printf(" %s Arbitration Table: 0x%08x\n", name, reg); 2601 } 2602 /* And then, decode each entry */ 2603 for (i = 0; i < num; i += num_per_reg) { 2604 reg = regs[o2i(off + i / num_per_reg)]; 2605 for (j = 0; j < num_per_reg; j++) 2606 printf(" Phase[%d]: %d\n", j, reg); 2607 } 2608 } 2609 2610 static void 2611 pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2612 { 2613 pcireg_t reg, n; 2614 int parbtab, parbsize; 2615 pcireg_t parbsel; 2616 int varbtab, varbsize; 2617 pcireg_t varbsel; 2618 int i, count; 2619 2620 printf("\n Virtual Channel Register\n"); 2621 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2622 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2623 count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2624 printf(" Extended VC Count: %d\n", count); 2625 n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2626 printf(" Low Priority Extended VC Count: %u\n", n); 2627 n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2628 printf(" Reference Clock: %s\n", 2629 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 2630 parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2631 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2632 2633 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2634 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2635 onoff("Hardware fixed arbitration scheme", 2636 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2637 onoff("WRR arbitration with 32 phases", 2638 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2639 onoff("WRR arbitration with 64 phases", 2640 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2641 onoff("WRR arbitration with 128 phases", 2642 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2643 varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2644 printf(" VC Arbitration Table Offset: 0x%x\n", varbtab); 2645 2646 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2647 printf(" Port VC Control register: 0x%04x\n", reg); 2648 varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2649 printf(" VC Arbitration Select: 0x%x\n", varbsel); 2650 2651 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2652 printf(" Port VC Status register: 0x%04x\n", reg); 2653 onoff("VC Arbitration Table Status", 2654 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 2655 2656 for (i = 0; i < count + 1; i++) { 2657 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 2658 printf(" VC number %d\n", i); 2659 printf(" VC Resource Capability Register: 0x%08x\n", reg); 2660 onoff(" Non-configurable Hardware fixed arbitration scheme", 2661 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 2662 onoff(" WRR arbitration with 32 phases", 2663 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 2664 onoff(" WRR arbitration with 64 phases", 2665 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 2666 onoff(" WRR arbitration with 128 phases", 2667 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 2668 onoff(" Time-based WRR arbitration with 128 phases", 2669 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 2670 onoff(" WRR arbitration with 256 phases", 2671 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 2672 onoff(" Advanced Packet Switching", 2673 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 2674 onoff(" Reject Snoop Transaction", 2675 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 2676 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 2677 printf(" Maximum Time Slots: %d\n", n); 2678 parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S; 2679 printf(" Port Arbitration Table offset: 0x%02x\n", 2680 parbtab); 2681 2682 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 2683 printf(" VC Resource Control Register: 0x%08x\n", reg); 2684 printf(" TC/VC Map: 0x%02x\n", 2685 (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 2686 /* 2687 * The load Port Arbitration Table bit is used to update 2688 * the Port Arbitration logic and it's always 0 on read, so 2689 * we don't print it. 2690 */ 2691 parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 2692 printf(" Port Arbitration Select: 0x%x\n", parbsel); 2693 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 2694 printf(" VC ID: %d\n", n); 2695 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 2696 2697 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 2698 printf(" VC Resource Status Register: 0x%08x\n", reg); 2699 onoff(" Port Arbitration Table Status", 2700 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 2701 onoff(" VC Negotiation Pending", 2702 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 2703 2704 if ((parbtab != 0) && (parbsel != 0)) 2705 pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab, 2706 "Port", parbsel, parbsize); 2707 } 2708 2709 varbsize = 8; 2710 if ((varbtab != 0) && (varbsel != 0)) 2711 pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab, 2712 " VC", varbsel, varbsize); 2713 } 2714 2715 /* 2716 * Print Power limit. This encoding is the same among the following registers: 2717 * - The Captured Slot Power Limit in the PCIe Device Capability Register. 2718 * - The Slot Power Limit in the PCIe Slot Capability Register. 2719 * - The Base Power in the Data register of Power Budgeting capability. 2720 */ 2721 static void 2722 pci_conf_print_pcie_power(uint8_t base, unsigned int scale) 2723 { 2724 unsigned int sdiv = 1; 2725 2726 if ((scale == 0) && (base > 0xef)) { 2727 const char *s; 2728 2729 switch (base) { 2730 case 0xf0: 2731 s = "239W < x <= 250W"; 2732 break; 2733 case 0xf1: 2734 s = "250W < x <= 275W"; 2735 break; 2736 case 0xf2: 2737 s = "275W < x <= 300W"; 2738 break; 2739 default: 2740 s = "reserved for above 300W"; 2741 break; 2742 } 2743 printf("%s\n", s); 2744 } 2745 2746 for (unsigned int i = scale; i > 0; i--) 2747 sdiv *= 10; 2748 2749 printf("%u", base / sdiv); 2750 2751 if (scale != 0) { 2752 printf(".%u", base % sdiv); 2753 } 2754 printf ("W\n"); 2755 return; 2756 } 2757 2758 static const char * 2759 pci_conf_print_pwrbdgt_type(uint8_t reg) 2760 { 2761 2762 switch (reg) { 2763 case 0x00: 2764 return "PME Aux"; 2765 case 0x01: 2766 return "Auxilary"; 2767 case 0x02: 2768 return "Idle"; 2769 case 0x03: 2770 return "Sustained"; 2771 case 0x04: 2772 return "Sustained (Emergency Power Reduction)"; 2773 case 0x05: 2774 return "Maximum (Emergency Power Reduction)"; 2775 case 0x07: 2776 return "Maximum"; 2777 default: 2778 return "Unknown"; 2779 } 2780 } 2781 2782 static const char * 2783 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 2784 { 2785 2786 switch (reg) { 2787 case 0x00: 2788 return "Power(12V)"; 2789 case 0x01: 2790 return "Power(3.3V)"; 2791 case 0x02: 2792 return "Power(1.5V or 1.8V)"; 2793 case 0x07: 2794 return "Thermal"; 2795 default: 2796 return "Unknown"; 2797 } 2798 } 2799 2800 static void 2801 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff) 2802 { 2803 pcireg_t reg; 2804 2805 printf("\n Power Budgeting\n"); 2806 2807 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 2808 printf(" Data Select register: 0x%08x\n", reg); 2809 2810 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 2811 printf(" Data register: 0x%08x\n", reg); 2812 printf(" Base Power: "); 2813 pci_conf_print_pcie_power( 2814 __SHIFTOUT(reg, PCI_PWRBDGT_DATA_BASEPWR), 2815 __SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE)); 2816 printf(" PM Sub State: 0x%hhx\n", 2817 (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 2818 printf(" PM State: D%u\n", 2819 (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 2820 printf(" Type: %s\n", 2821 pci_conf_print_pwrbdgt_type( 2822 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 2823 printf(" Power Rail: %s\n", 2824 pci_conf_print_pwrbdgt_pwrrail( 2825 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 2826 2827 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 2828 printf(" Power Budget Capability register: 0x%08x\n", reg); 2829 onoff("System Allocated", 2830 reg, PCI_PWRBDGT_CAP_SYSALLOC); 2831 } 2832 2833 static const char * 2834 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 2835 { 2836 2837 switch (type) { 2838 case 0x00: 2839 return "Configuration Space Element"; 2840 case 0x01: 2841 return "System Egress Port or internal sink (memory)"; 2842 case 0x02: 2843 return "Internal Root Complex Link"; 2844 default: 2845 return "Unknown"; 2846 } 2847 } 2848 2849 static void 2850 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int capoff, int extcapoff) 2851 { 2852 pcireg_t reg; 2853 unsigned char nent, linktype; 2854 int i; 2855 2856 printf("\n Root Complex Link Declaration\n"); 2857 2858 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 2859 printf(" Element Self Description Register: 0x%08x\n", reg); 2860 printf(" Element Type: %s\n", 2861 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 2862 nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 2863 printf(" Number of Link Entries: %hhu\n", nent); 2864 printf(" Component ID: %hhu\n", 2865 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 2866 printf(" Port Number: %hhu\n", 2867 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 2868 for (i = 0; i < nent; i++) { 2869 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 2870 printf(" Link Entry %d:\n", i + 1); 2871 printf(" Link Description Register: 0x%08x\n", reg); 2872 onoff(" Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID); 2873 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 2874 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 2875 "Configuration Space", "Memory-Mapped Space"); 2876 onoff(" Associated RCRB Header", reg, 2877 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 2878 printf(" Target Component ID: %hhu\n", 2879 (unsigned char)__SHIFTOUT(reg, 2880 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 2881 printf(" Target Port Number: %hhu\n", 2882 (unsigned char)__SHIFTOUT(reg, 2883 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 2884 2885 if (linktype == 0) { 2886 /* Memory-Mapped Space */ 2887 reg = regs[o2i(extcapoff 2888 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 2889 printf(" Link Address Low Register: 0x%08x\n", 2890 reg); 2891 reg = regs[o2i(extcapoff 2892 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 2893 printf(" Link Address High Register: 0x%08x\n", 2894 reg); 2895 } else { 2896 unsigned int nb; 2897 pcireg_t lo, hi; 2898 2899 /* Configuration Space */ 2900 lo = regs[o2i(extcapoff 2901 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 2902 printf(" Configuration Space Low Register: " 2903 "0x%08x\n", lo); 2904 hi = regs[o2i(extcapoff 2905 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 2906 printf(" Configuration Space High Register: " 2907 "0x%08x\n", hi); 2908 nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 2909 printf(" N: %u\n", nb); 2910 printf(" Func: %hhu\n", 2911 (unsigned char)__SHIFTOUT(lo, 2912 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 2913 printf(" Dev: %hhu\n", 2914 (unsigned char)__SHIFTOUT(lo, 2915 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 2916 printf(" Bus: %hhu\n", 2917 (unsigned char)__SHIFTOUT(lo, 2918 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 2919 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 2920 printf(" Configuration Space Base Address: " 2921 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 2922 } 2923 } 2924 } 2925 2926 /* XXX pci_conf_print_rclink_ctl_cap */ 2927 2928 static void 2929 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2930 { 2931 pcireg_t reg; 2932 2933 printf("\n Root Complex Event Collector Association\n"); 2934 2935 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 2936 printf(" Association Bitmap for Root Complex Integrated Devices:" 2937 " 0x%08x\n", reg); 2938 } 2939 2940 /* XXX pci_conf_print_mfvc_cap */ 2941 /* XXX pci_conf_print_vc2_cap */ 2942 /* XXX pci_conf_print_rcrb_cap */ 2943 /* XXX pci_conf_print_vendor_cap */ 2944 /* XXX pci_conf_print_cac_cap */ 2945 2946 static void 2947 pci_conf_print_acs_cap(const pcireg_t *regs, int capoff, int extcapoff) 2948 { 2949 pcireg_t reg, cap, ctl; 2950 unsigned int size, i; 2951 2952 printf("\n Access Control Services\n"); 2953 2954 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 2955 cap = reg & 0xffff; 2956 ctl = reg >> 16; 2957 printf(" ACS Capability register: 0x%08x\n", cap); 2958 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 2959 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 2960 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 2961 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 2962 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 2963 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 2964 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 2965 size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 2966 if (size == 0) 2967 size = 256; 2968 printf(" Egress Control Vector Size: %u\n", size); 2969 printf(" ACS Control register: 0x%08x\n", ctl); 2970 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 2971 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 2972 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 2973 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 2974 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 2975 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 2976 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 2977 2978 /* 2979 * If the P2P Egress Control Capability bit is 0, ignore the Egress 2980 * Control vector. 2981 */ 2982 if ((cap & PCI_ACS_CAP_E) == 0) 2983 return; 2984 for (i = 0; i < size; i += 32) 2985 printf(" Egress Control Vector [%u..%u]: 0x%08x\n", i + 31, 2986 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 2987 } 2988 2989 static void 2990 pci_conf_print_ari_cap(const pcireg_t *regs, int capoff, int extcapoff) 2991 { 2992 pcireg_t reg, cap, ctl; 2993 2994 printf("\n Alternative Routing-ID Interpretation Register\n"); 2995 2996 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 2997 cap = reg & 0xffff; 2998 ctl = reg >> 16; 2999 printf(" Capability register: 0x%08x\n", cap); 3000 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 3001 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 3002 printf(" Next Function Number: %u\n", 3003 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 3004 printf(" Control register: 0x%08x\n", ctl); 3005 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 3006 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 3007 printf(" Function Group: %u\n", 3008 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 3009 } 3010 3011 static void 3012 pci_conf_print_ats_cap(const pcireg_t *regs, int capoff, int extcapoff) 3013 { 3014 pcireg_t reg, cap, ctl; 3015 unsigned int num; 3016 3017 printf("\n Address Translation Services\n"); 3018 3019 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3020 cap = reg & 0xffff; 3021 ctl = reg >> 16; 3022 printf(" Capability register: 0x%04x\n", cap); 3023 num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 3024 if (num == 0) 3025 num = 32; 3026 printf(" Invalidate Queue Depth: %u\n", num); 3027 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 3028 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 3029 3030 printf(" Control register: 0x%04x\n", ctl); 3031 printf(" Smallest Translation Unit: %u\n", 3032 (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU)); 3033 onoff("Enable", reg, PCI_ATS_CTL_EN); 3034 } 3035 3036 static void 3037 pci_conf_print_sernum_cap(const pcireg_t *regs, int capoff, int extcapoff) 3038 { 3039 pcireg_t lo, hi; 3040 3041 printf("\n Device Serial Number Register\n"); 3042 3043 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 3044 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 3045 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 3046 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 3047 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 3048 } 3049 3050 static void 3051 pci_conf_print_sriov_cap(const pcireg_t *regs, int capoff, int extcapoff) 3052 { 3053 char buf[sizeof("99999 MB")]; 3054 pcireg_t reg; 3055 pcireg_t total_vfs; 3056 int i; 3057 bool first; 3058 3059 printf("\n Single Root IO Virtualization Register\n"); 3060 3061 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 3062 printf(" Capabilities register: 0x%08x\n", reg); 3063 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 3064 onoff("ARI Capable Hierarchy Preserved", reg, 3065 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 3066 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 3067 printf(" VF Migration Interrupt Message Number: 0x%03x\n", 3068 (pcireg_t)__SHIFTOUT(reg, 3069 PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 3070 } 3071 3072 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 3073 printf(" Control register: 0x%04x\n", reg); 3074 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 3075 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 3076 onoff("VF Migration Interrupt Enable", reg, 3077 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 3078 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 3079 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 3080 3081 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 3082 printf(" Status register: 0x%04x\n", reg); 3083 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 3084 3085 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 3086 printf(" InitialVFs register: 0x%04x\n", reg); 3087 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 3088 printf(" TotalVFs register: 0x%04x\n", reg); 3089 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 3090 printf(" NumVFs register: 0x%04x\n", reg); 3091 3092 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 3093 printf(" Function Dependency Link register: 0x%04x\n", reg); 3094 3095 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 3096 printf(" First VF Offset register: 0x%04x\n", reg); 3097 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 3098 printf(" VF Stride register: 0x%04x\n", reg); 3099 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16; 3100 printf(" Device ID: 0x%04x\n", reg); 3101 3102 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 3103 printf(" Supported Page Sizes register: 0x%08x\n", reg); 3104 printf(" Supported Page Size:"); 3105 for (i = 0, first = true; i < 32; i++) { 3106 if (reg & __BIT(i)) { 3107 #ifdef _KERNEL 3108 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 3109 #else 3110 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 3111 HN_AUTOSCALE, 0); 3112 #endif 3113 printf("%s %s", first ? "" : ",", buf); 3114 first = false; 3115 } 3116 } 3117 printf("\n"); 3118 3119 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 3120 printf(" System Page Sizes register: 0x%08x\n", reg); 3121 printf(" Page Size: "); 3122 if (reg != 0) { 3123 int bitpos = ffs(reg) -1; 3124 3125 /* Assume only one bit is set. */ 3126 #ifdef _KERNEL 3127 format_bytes(buf, sizeof(buf), 1LL << (bitpos + 12)); 3128 #else 3129 humanize_number(buf, sizeof(buf), 1LL << (bitpos + 12), 3130 "B", HN_AUTOSCALE, 0); 3131 #endif 3132 printf("%s", buf); 3133 } else { 3134 printf("unknown"); 3135 } 3136 printf("\n"); 3137 3138 for (i = 0; i < 6; i++) { 3139 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 3140 printf(" VF BAR%d register: 0x%08x\n", i, reg); 3141 } 3142 3143 if (total_vfs > 0) { 3144 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 3145 printf(" VF Migration State Array Offset register: 0x%08x\n", 3146 reg); 3147 printf(" VF Migration State Offset: 0x%08x\n", 3148 (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 3149 i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 3150 printf(" VF Migration State BIR: "); 3151 if (i >= 0 && i <= 5) { 3152 printf("BAR%d", i); 3153 } else { 3154 printf("unknown BAR (%d)", i); 3155 } 3156 printf("\n"); 3157 } 3158 } 3159 3160 /* XXX pci_conf_print_mriov_cap */ 3161 3162 static void 3163 pci_conf_print_multicast_cap(const pcireg_t *regs, int capoff, int extcapoff) 3164 { 3165 pcireg_t reg, cap, ctl; 3166 pcireg_t regl, regh; 3167 uint64_t addr; 3168 int n; 3169 3170 printf("\n Multicast\n"); 3171 3172 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 3173 cap = reg & 0xffff; 3174 ctl = reg >> 16; 3175 printf(" Capability Register: 0x%04x\n", cap); 3176 printf(" Max Group: %u\n", 3177 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 3178 3179 /* Endpoint Only */ 3180 n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 3181 if (n > 0) 3182 printf(" Windw Size Requested: %d\n", 1 << (n - 1)); 3183 3184 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 3185 3186 printf(" Control Register: 0x%04x\n", ctl); 3187 printf(" Num Group: %u\n", 3188 (unsigned int)__SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 3189 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 3190 3191 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 3192 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 3193 printf(" Base Address Register 0: 0x%08x\n", regl); 3194 printf(" Base Address Register 1: 0x%08x\n", regh); 3195 printf(" Index Position: %u\n", 3196 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 3197 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 3198 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 3199 3200 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 3201 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 3202 printf(" Receive Register 0: 0x%08x\n", regl); 3203 printf(" Receive Register 1: 0x%08x\n", regh); 3204 3205 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 3206 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 3207 printf(" Block All Register 0: 0x%08x\n", regl); 3208 printf(" Block All Register 1: 0x%08x\n", regh); 3209 3210 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 3211 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 3212 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 3213 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 3214 3215 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 3216 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 3217 printf(" Overlay BAR 0: 0x%08x\n", regl); 3218 printf(" Overlay BAR 1: 0x%08x\n", regh); 3219 3220 n = regl & PCI_MCAST_OVERLAYL_SIZE; 3221 printf(" Overlay Size: "); 3222 if (n >= 6) 3223 printf("%d\n", n); 3224 else 3225 printf("off\n"); 3226 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 3227 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 3228 } 3229 3230 static void 3231 pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3232 { 3233 pcireg_t reg, ctl, sta; 3234 3235 printf("\n Page Request\n"); 3236 3237 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 3238 ctl = reg & 0xffff; 3239 sta = reg >> 16; 3240 printf(" Control Register: 0x%04x\n", ctl); 3241 onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E); 3242 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 3243 3244 printf(" Status Register: 0x%04x\n", sta); 3245 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 3246 onoff("Unexpected Page Request Group Index", reg, 3247 PCI_PAGE_REQ_STA_UPRGI); 3248 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 3249 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 3250 3251 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 3252 printf(" Outstanding Page Request Capacity: %u\n", reg); 3253 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 3254 printf(" Outstanding Page Request Allocation: %u\n", reg); 3255 } 3256 3257 /* XXX pci_conf_print_amd_cap */ 3258 3259 #define MEM_PBUFSIZE sizeof("999GB") 3260 3261 static void 3262 pci_conf_print_resizbar_cap(const pcireg_t *regs, int capoff, int extcapoff) 3263 { 3264 pcireg_t cap, ctl; 3265 unsigned int bars, i, n; 3266 char pbuf[MEM_PBUFSIZE]; 3267 3268 printf("\n Resizable BAR\n"); 3269 3270 /* Get Number of Resizable BARs */ 3271 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))]; 3272 bars = __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR); 3273 printf(" Number of Resizable BARs: "); 3274 if (bars <= 6) 3275 printf("%u\n", bars); 3276 else { 3277 printf("incorrect (%u)\n", bars); 3278 return; 3279 } 3280 3281 for (n = 0; n < 6; n++) { 3282 cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))]; 3283 printf(" Capability register(%u): 0x%08x\n", n, cap); 3284 if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0) 3285 continue; /* Not Used */ 3286 printf(" Acceptable BAR sizes:"); 3287 for (i = 4; i <= 23; i++) { 3288 if ((cap & (1 << i)) != 0) { 3289 humanize_number(pbuf, MEM_PBUFSIZE, 3290 (int64_t)1024 * 1024 << (i - 4), "B", 3291 #ifdef _KERNEL 3292 1); 3293 #else 3294 HN_AUTOSCALE, HN_NOSPACE); 3295 #endif 3296 printf(" %s", pbuf); 3297 } 3298 } 3299 printf("\n"); 3300 3301 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))]; 3302 printf(" Control register(%u): 0x%08x\n", n, ctl); 3303 printf(" BAR Index: %u\n", 3304 (unsigned int)__SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX)); 3305 humanize_number(pbuf, MEM_PBUFSIZE, 3306 (int64_t)1024 * 1024 3307 << __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ), 3308 "B", 3309 #ifdef _KERNEL 3310 1); 3311 #else 3312 HN_AUTOSCALE, HN_NOSPACE); 3313 #endif 3314 printf(" BAR Size: %s\n", pbuf); 3315 } 3316 } 3317 3318 static void 3319 pci_conf_print_dpa_cap(const pcireg_t *regs, int capoff, int extcapoff) 3320 { 3321 pcireg_t reg; 3322 unsigned int substmax, i; 3323 3324 printf("\n Dynamic Power Allocation\n"); 3325 3326 reg = regs[o2i(extcapoff + PCI_DPA_CAP)]; 3327 printf(" Capability register: 0x%08x\n", reg); 3328 substmax = __SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX); 3329 printf(" Substate Max: %u\n", substmax); 3330 printf(" Transition Latency Unit: "); 3331 switch (__SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) { 3332 case 0: 3333 printf("1ms\n"); 3334 break; 3335 case 1: 3336 printf("10ms\n"); 3337 break; 3338 case 2: 3339 printf("100ms\n"); 3340 break; 3341 default: 3342 printf("reserved\n"); 3343 break; 3344 } 3345 printf(" Power Allocation Scale: "); 3346 switch (__SHIFTOUT(reg, PCI_DPA_CAP_PAS)) { 3347 case 0: 3348 printf("10.0x\n"); 3349 break; 3350 case 1: 3351 printf("1.0x\n"); 3352 break; 3353 case 2: 3354 printf("0.1x\n"); 3355 break; 3356 case 3: 3357 printf("0.01x\n"); 3358 break; 3359 } 3360 printf(" Transition Latency Value 0: %u\n", 3361 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY0)); 3362 printf(" Transition Latency Value 1: %u\n", 3363 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); 3364 3365 reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; 3366 printf(" Latency Indicatior register: 0x%08x\n", reg); 3367 3368 reg = regs[o2i(extcapoff + PCI_DPA_CS)]; 3369 printf(" Status register: 0x%04x\n", reg & 0xffff); 3370 printf(" Substate Status: 0x%02x\n", 3371 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT)); 3372 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN); 3373 printf(" Control register: 0x%04x\n", reg >> 16); 3374 printf(" Substate Control: 0x%02x\n", 3375 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL)); 3376 3377 for (i = 0; i <= substmax; i++) 3378 printf(" Substate Power Allocation register %d: 0x%02x\n", 3379 i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff)); 3380 } 3381 3382 static const char * 3383 pci_conf_print_tph_req_cap_sttabloc(unsigned char val) 3384 { 3385 3386 switch (val) { 3387 case 0x0: 3388 return "Not Present"; 3389 case 0x1: 3390 return "in the TPH Requester Capability Structure"; 3391 case 0x2: 3392 return "in the MSI-X Table"; 3393 default: 3394 return "Unknown"; 3395 } 3396 } 3397 3398 static void 3399 pci_conf_print_tph_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3400 { 3401 pcireg_t reg; 3402 int size, i, j; 3403 3404 printf("\n TPH Requester Extended Capability\n"); 3405 3406 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3407 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3408 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3409 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3410 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3411 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3412 printf(" ST Table Location: %s\n", 3413 pci_conf_print_tph_req_cap_sttabloc( 3414 (unsigned char)__SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC))); 3415 size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3416 printf(" ST Table Size: %d\n", size); 3417 3418 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CTL)]; 3419 printf(" TPH Requester Control register: 0x%08x\n", reg); 3420 printf(" ST Mode Select: "); 3421 switch (__SHIFTOUT(reg, PCI_TPH_REQ_CTL_STSEL)) { 3422 case PCI_TPH_REQ_CTL_STSEL_NO: 3423 printf("No ST Mode\n"); 3424 break; 3425 case PCI_TPH_REQ_CTL_STSEL_IV: 3426 printf("Interrupt Vector Mode\n"); 3427 break; 3428 case PCI_TPH_REQ_CTL_STSEL_DS: 3429 printf("Device Specific Mode\n"); 3430 break; 3431 default: 3432 printf("(reserved vaule)\n"); 3433 break; 3434 } 3435 printf(" TPH Requester Enable: "); 3436 switch (__SHIFTOUT(reg, PCI_TPH_REQ_CTL_TPHREQEN)) { 3437 case PCI_TPH_REQ_CTL_TPHREQEN_NO: /* 0x0 */ 3438 printf("Not permitted\n"); 3439 break; 3440 case PCI_TPH_REQ_CTL_TPHREQEN_TPH: 3441 printf("TPH and not Extended TPH\n"); 3442 break; 3443 case PCI_TPH_REQ_CTL_TPHREQEN_ETPH: 3444 printf("TPH and Extended TPH"); 3445 break; 3446 default: 3447 printf("(reserved vaule)\n"); 3448 break; 3449 } 3450 3451 for (i = 0; i < size ; i += 2) { 3452 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3453 for (j = 0; j < 2 ; j++) { 3454 uint32_t entry = reg; 3455 3456 if (j != 0) 3457 entry >>= 16; 3458 entry &= 0xffff; 3459 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3460 i + j, entry); 3461 } 3462 } 3463 } 3464 3465 static void 3466 pci_conf_print_ltr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3467 { 3468 pcireg_t reg; 3469 3470 printf("\n Latency Tolerance Reporting\n"); 3471 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)] & 0xffff; 3472 printf(" Max Snoop Latency Register: 0x%04x\n", reg); 3473 printf(" Max Snoop LatencyValue: %u\n", 3474 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL)); 3475 printf(" Max Snoop LatencyScale: %uns\n", 3476 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE))); 3477 reg = regs[o2i(extcapoff + PCI_LTR_MAXNOSNOOPLAT)] >> 16; 3478 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg); 3479 printf(" Max No-Snoop LatencyValue: %u\n", 3480 (pcireg_t)__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL)); 3481 printf(" Max No-Snoop LatencyScale: %uns\n", 3482 PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE))); 3483 } 3484 3485 static void 3486 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int capoff, int extcapoff) 3487 { 3488 int pcie_capoff; 3489 pcireg_t reg; 3490 int i, maxlinkwidth; 3491 3492 printf("\n Secondary PCI Express Register\n"); 3493 3494 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3495 printf(" Link Control 3 register: 0x%08x\n", reg); 3496 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3497 onoff("Link Equalization Request Interrupt Enable", 3498 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3499 printf(" Enable Lower SKP OS Generation Vector:"); 3500 pci_print_pcie_linkspeedvector( 3501 __SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3502 printf("\n"); 3503 3504 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3505 printf(" Lane Error Status register: 0x%08x\n", reg); 3506 3507 /* Get Max Link Width */ 3508 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)){ 3509 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3510 maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3511 } else { 3512 printf("error: falied to get PCIe capablity\n"); 3513 return; 3514 } 3515 for (i = 0; i < maxlinkwidth; i++) { 3516 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3517 if (i % 2 != 0) 3518 reg >>= 16; 3519 else 3520 reg &= 0xffff; 3521 printf(" Equalization Control Register (Link %d): 0x%04x\n", 3522 i, reg); 3523 printf(" Downstream Port Transmit Preset: 0x%x\n", 3524 (pcireg_t)__SHIFTOUT(reg, 3525 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3526 printf(" Downstream Port Receive Hint: 0x%x\n", 3527 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3528 printf(" Upstream Port Transmit Preset: 0x%x\n", 3529 (pcireg_t)__SHIFTOUT(reg, 3530 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3531 printf(" Upstream Port Receive Hint: 0x%x\n", 3532 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3533 } 3534 } 3535 3536 /* XXX pci_conf_print_pmux_cap */ 3537 3538 static void 3539 pci_conf_print_pasid_cap(const pcireg_t *regs, int capoff, int extcapoff) 3540 { 3541 pcireg_t reg, cap, ctl; 3542 unsigned int num; 3543 3544 printf("\n Process Address Space ID\n"); 3545 3546 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3547 cap = reg & 0xffff; 3548 ctl = reg >> 16; 3549 printf(" PASID Capability Register: 0x%04x\n", cap); 3550 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3551 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3552 num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3553 printf(" Max PASID Width: %u\n", num); 3554 3555 printf(" PASID Control Register: 0x%04x\n", ctl); 3556 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3557 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3558 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3559 } 3560 3561 static void 3562 pci_conf_print_lnr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3563 { 3564 pcireg_t reg, cap, ctl; 3565 unsigned int num; 3566 3567 printf("\n LN Requester\n"); 3568 3569 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3570 cap = reg & 0xffff; 3571 ctl = reg >> 16; 3572 printf(" LNR Capability register: 0x%04x\n", cap); 3573 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 3574 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 3575 num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 3576 printf(" LNR Registration MAX: %u\n", num); 3577 3578 printf(" LNR Control register: 0x%04x\n", ctl); 3579 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 3580 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 3581 num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 3582 printf(" LNR Registration Limit: %u\n", num); 3583 } 3584 3585 static void 3586 pci_conf_print_dpc_pio(pcireg_t r) 3587 { 3588 onoff("Cfg Request received UR Completion", r,PCI_DPC_RPPIO_CFGUR_CPL); 3589 onoff("Cfg Request received CA Completion", r,PCI_DPC_RPPIO_CFGCA_CPL); 3590 onoff("Cfg Request Completion Timeout", r, PCI_DPC_RPPIO_CFG_CTO); 3591 onoff("I/O Request received UR Completion", r, PCI_DPC_RPPIO_IOUR_CPL); 3592 onoff("I/O Request received CA Completion", r, PCI_DPC_RPPIO_IOCA_CPL); 3593 onoff("I/O Request Completion Timeout", r, PCI_DPC_RPPIO_IO_CTO); 3594 onoff("Mem Request received UR Completion", r,PCI_DPC_RPPIO_MEMUR_CPL); 3595 onoff("Mem Request received CA Completion", r,PCI_DPC_RPPIO_MEMCA_CPL); 3596 onoff("Mem Request Completion Timeout", r, PCI_DPC_RPPIO_MEM_CTO); 3597 } 3598 3599 static void 3600 pci_conf_print_dpc_cap(const pcireg_t *regs, int capoff, int extcapoff) 3601 { 3602 pcireg_t reg, cap, ctl, stat, errsrc; 3603 const char *trigstr; 3604 bool rpext; 3605 3606 printf("\n Downstream Port Containment\n"); 3607 3608 reg = regs[o2i(extcapoff + PCI_DPC_CCR)]; 3609 cap = reg & 0xffff; 3610 ctl = reg >> 16; 3611 rpext = (reg & PCI_DPCCAP_RPEXT) ? true : false; 3612 printf(" DPC Capability register: 0x%04x\n", cap); 3613 printf(" DPC Interrupt Message Number: %02x\n", 3614 (unsigned int)(cap & PCI_DPCCAP_IMSGN)); 3615 onoff("RP Extensions for DPC", reg, PCI_DPCCAP_RPEXT); 3616 onoff("Poisoned TLP Egress Blocking Supported", reg, 3617 PCI_DPCCAP_POISONTLPEB); 3618 onoff("DPC Software Triggering Supported", reg, PCI_DPCCAP_SWTRIG); 3619 printf(" RP PIO Log Size: %u\n", 3620 (unsigned int)__SHIFTOUT(reg, PCI_DPCCAP_RPPIOLOGSZ)); 3621 onoff("DL_Active ERR_COR Signaling Supported", reg, 3622 PCI_DPCCAP_DLACTECORS); 3623 printf(" DPC Control register: 0x%04x\n", ctl); 3624 switch (__SHIFTOUT(reg, PCI_DPCCTL_TIRGEN)) { 3625 case 0: 3626 trigstr = "disabled"; 3627 break; 3628 case 1: 3629 trigstr = "enabled(ERR_FATAL)"; 3630 break; 3631 case 2: 3632 trigstr = "enabled(ERR_NONFATAL or ERR_FATAL)"; 3633 break; 3634 default: 3635 trigstr = "(reserverd)"; 3636 break; 3637 } 3638 printf(" DPC Trigger Enable: %s\n", trigstr); 3639 printf(" DPC Completion Control: %s Completion Status\n", 3640 (reg & PCI_DPCCTL_COMPCTL) 3641 ? "Unsupported Request(UR)" : "Completer Abort(CA)"); 3642 onoff("DPC Interrupt Enable", reg, PCI_DPCCTL_IE); 3643 onoff("DPC ERR_COR Enable", reg, PCI_DPCCTL_ERRCOREN); 3644 onoff("Poisoned TLP Egress Blocking Enable", reg, 3645 PCI_DPCCTL_POISONTLPEB); 3646 onoff("DPC Software Trigger", reg, PCI_DPCCTL_SWTRIG); 3647 onoff("DL_Active ERR_COR Enable", reg, PCI_DPCCTL_DLACTECOR); 3648 3649 reg = regs[o2i(extcapoff + PCI_DPC_STATESID)]; 3650 stat = reg & 0xffff; 3651 errsrc = reg >> 16; 3652 printf(" DPC Status register: 0x%04x\n", stat); 3653 onoff("DPC Trigger Status", reg, PCI_DPCSTAT_TSTAT); 3654 switch (__SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 3655 case 0: 3656 trigstr = "an unmasked uncorrectable error"; 3657 break; 3658 case 1: 3659 trigstr = "receiving an ERR_NONFATAL"; 3660 break; 3661 case 2: 3662 trigstr = "receiving an ERR_FATAL"; 3663 break; 3664 case 3: 3665 trigstr = "DPC Trigger Reason Extension field"; 3666 break; 3667 } 3668 printf(" DPC Trigger Reason: Due to %s\n", trigstr); 3669 onoff("DPC Interrupt Status", reg, PCI_DPCSTAT_ISTAT); 3670 if (rpext) 3671 onoff("DPC RP Busy", reg, PCI_DPCSTAT_RPBUSY); 3672 switch (__SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 3673 case 0: 3674 trigstr = "Due to RP PIO error"; 3675 break; 3676 case 1: 3677 trigstr = "Due to the DPC Software trigger bit"; 3678 break; 3679 default: 3680 trigstr = "(reserved)"; 3681 break; 3682 } 3683 printf(" DPC Trigger Reason Extension: %s\n", trigstr); 3684 if (rpext) 3685 printf(" RP PIO First Error Pointer: %02x\n", 3686 (unsigned int)__SHIFTOUT(reg, PCI_DPCSTAT_RPPIOFEP)); 3687 printf(" DPC Error Source ID register: 0x%04x\n", errsrc); 3688 3689 if (!rpext) 3690 return; 3691 /* 3692 * All of the following registers are implemented by a device which has 3693 * RP Extensions for DPC 3694 */ 3695 3696 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_STAT)]; 3697 printf(" RP PIO Status Register: 0x%04x\n", reg); 3698 pci_conf_print_dpc_pio(reg); 3699 3700 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_MASK)]; 3701 printf(" RP PIO Mask Register: 0x%04x\n", reg); 3702 pci_conf_print_dpc_pio(reg); 3703 3704 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SEVE)]; 3705 printf(" RP PIO Severity Register: 0x%04x\n", reg); 3706 pci_conf_print_dpc_pio(reg); 3707 3708 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SYSERR)]; 3709 printf(" RP PIO SysError Register: 0x%04x\n", reg); 3710 pci_conf_print_dpc_pio(reg); 3711 3712 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_EXCPT)]; 3713 printf(" RP PIO Exception Register: 0x%04x\n", reg); 3714 pci_conf_print_dpc_pio(reg); 3715 3716 printf(" RP PIO Header Log Register: start from 0x%03x\n", 3717 extcapoff + PCI_DPC_RPPIO_HLOG); 3718 printf(" RP PIO ImpSpec Log Register: start from 0x%03x\n", 3719 extcapoff + PCI_DPC_RPPIO_IMPSLOG); 3720 printf(" RP PIO TPL Prefix Log Register: start from 0x%03x\n", 3721 extcapoff + PCI_DPC_RPPIO_TLPPLOG); 3722 } 3723 3724 3725 static int 3726 pci_conf_l1pm_cap_tposcale(unsigned char scale) 3727 { 3728 3729 /* Return scale in us */ 3730 switch (scale) { 3731 case 0x0: 3732 return 2; 3733 case 0x1: 3734 return 10; 3735 case 0x2: 3736 return 100; 3737 default: 3738 return -1; 3739 } 3740 } 3741 3742 static void 3743 pci_conf_print_l1pm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3744 { 3745 pcireg_t reg; 3746 int scale, val; 3747 3748 printf("\n L1 PM Substates\n"); 3749 3750 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 3751 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 3752 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 3753 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 3754 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 3755 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 3756 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 3757 printf(" Port Common Mode Restore Time: %uus\n", 3758 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 3759 scale = pci_conf_l1pm_cap_tposcale( 3760 __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 3761 val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 3762 printf(" Port T_POWER_ON: "); 3763 if (scale == -1) 3764 printf("unknown\n"); 3765 else 3766 printf("%dus\n", val * scale); 3767 3768 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 3769 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 3770 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 3771 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 3772 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 3773 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 3774 printf(" Common Mode Restore Time: %uus\n", 3775 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 3776 scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 3777 val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 3778 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 3779 3780 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 3781 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 3782 scale = pci_conf_l1pm_cap_tposcale( 3783 __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 3784 val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 3785 printf(" T_POWER_ON: "); 3786 if (scale == -1) 3787 printf("unknown\n"); 3788 else 3789 printf("%dus\n", val * scale); 3790 } 3791 3792 static void 3793 pci_conf_print_ptm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3794 { 3795 pcireg_t reg; 3796 uint32_t val; 3797 3798 printf("\n Precision Time Management\n"); 3799 3800 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 3801 printf(" PTM Capability register: 0x%08x\n", reg); 3802 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 3803 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 3804 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 3805 printf(" Local Clock Granularity: "); 3806 val = __SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 3807 switch (val) { 3808 case 0: 3809 printf("Not implemented\n"); 3810 break; 3811 case 0xffff: 3812 printf("> 254ns\n"); 3813 break; 3814 default: 3815 printf("%uns\n", val); 3816 break; 3817 } 3818 3819 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 3820 printf(" PTM Control register: 0x%08x\n", reg); 3821 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 3822 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 3823 printf(" Effective Granularity: "); 3824 val = __SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 3825 switch (val) { 3826 case 0: 3827 printf("Unknown\n"); 3828 break; 3829 case 0xffff: 3830 printf("> 254ns\n"); 3831 break; 3832 default: 3833 printf("%uns\n", val); 3834 break; 3835 } 3836 } 3837 3838 /* XXX pci_conf_print_mpcie_cap */ 3839 /* XXX pci_conf_print_frsq_cap */ 3840 /* XXX pci_conf_print_rtr_cap */ 3841 /* XXX pci_conf_print_desigvndsp_cap */ 3842 /* XXX pci_conf_print_vf_resizbar_cap */ 3843 /* XXX pci_conf_print_hierarchyid_cap */ 3844 3845 #undef MS 3846 #undef SM 3847 #undef RW 3848 3849 static struct { 3850 pcireg_t cap; 3851 const char *name; 3852 void (*printfunc)(const pcireg_t *, int, int); 3853 } pci_extcaptab[] = { 3854 { 0, "reserved", 3855 NULL }, 3856 { PCI_EXTCAP_AER, "Advanced Error Reporting", 3857 pci_conf_print_aer_cap }, 3858 { PCI_EXTCAP_VC, "Virtual Channel", 3859 pci_conf_print_vc_cap }, 3860 { PCI_EXTCAP_SERNUM, "Device Serial Number", 3861 pci_conf_print_sernum_cap }, 3862 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 3863 pci_conf_print_pwrbdgt_cap }, 3864 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 3865 pci_conf_print_rclink_dcl_cap }, 3866 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 3867 NULL }, 3868 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 3869 pci_conf_print_rcec_assoc_cap }, 3870 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 3871 NULL }, 3872 { PCI_EXTCAP_VC2, "Virtual Channel", 3873 NULL }, 3874 { PCI_EXTCAP_RCRB, "RCRB Header", 3875 NULL }, 3876 { PCI_EXTCAP_VENDOR, "Vendor Unique", 3877 NULL }, 3878 { PCI_EXTCAP_CAC, "Configuration Access Correction", 3879 NULL }, 3880 { PCI_EXTCAP_ACS, "Access Control Services", 3881 pci_conf_print_acs_cap }, 3882 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 3883 pci_conf_print_ari_cap }, 3884 { PCI_EXTCAP_ATS, "Address Translation Services", 3885 pci_conf_print_ats_cap }, 3886 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 3887 pci_conf_print_sriov_cap }, 3888 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 3889 NULL }, 3890 { PCI_EXTCAP_MCAST, "Multicast", 3891 pci_conf_print_multicast_cap }, 3892 { PCI_EXTCAP_PAGE_REQ, "Page Request", 3893 pci_conf_print_page_req_cap }, 3894 { PCI_EXTCAP_AMD, "Reserved for AMD", 3895 NULL }, 3896 { PCI_EXTCAP_RESIZBAR, "Resizable BAR", 3897 pci_conf_print_resizbar_cap }, 3898 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 3899 pci_conf_print_dpa_cap }, 3900 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 3901 pci_conf_print_tph_req_cap }, 3902 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 3903 pci_conf_print_ltr_cap }, 3904 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 3905 pci_conf_print_sec_pcie_cap }, 3906 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 3907 NULL }, 3908 { PCI_EXTCAP_PASID, "Process Address Space ID", 3909 pci_conf_print_pasid_cap }, 3910 { PCI_EXTCAP_LN_REQ, "LN Requester", 3911 pci_conf_print_lnr_cap }, 3912 { PCI_EXTCAP_DPC, "Downstream Port Containment", 3913 pci_conf_print_dpc_cap }, 3914 { PCI_EXTCAP_L1PM, "L1 PM Substates", 3915 pci_conf_print_l1pm_cap }, 3916 { PCI_EXTCAP_PTM, "Precision Time Management", 3917 pci_conf_print_ptm_cap }, 3918 { PCI_EXTCAP_MPCIE, "M-PCIe", 3919 NULL }, 3920 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 3921 NULL }, 3922 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 3923 NULL }, 3924 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 3925 NULL }, 3926 { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", 3927 NULL }, 3928 { PCI_EXTCAP_HIERARCHYID, "Hierarchy ID", 3929 NULL }, 3930 }; 3931 3932 static int 3933 pci_conf_find_extcap(const pcireg_t *regs, int capoff, unsigned int capid, 3934 int *offsetp) 3935 { 3936 int off; 3937 pcireg_t rval; 3938 3939 for (off = PCI_EXTCAPLIST_BASE; 3940 off != 0; 3941 off = PCI_EXTCAPLIST_NEXT(rval)) { 3942 rval = regs[o2i(off)]; 3943 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 3944 if (offsetp != NULL) 3945 *offsetp = off; 3946 return 1; 3947 } 3948 } 3949 return 0; 3950 } 3951 3952 static void 3953 pci_conf_print_extcaplist( 3954 #ifdef _KERNEL 3955 pci_chipset_tag_t pc, pcitag_t tag, 3956 #endif 3957 const pcireg_t *regs, int capoff) 3958 { 3959 int off; 3960 pcireg_t foundcap; 3961 pcireg_t rval; 3962 bool foundtable[__arraycount(pci_extcaptab)]; 3963 unsigned int i; 3964 3965 /* Check Extended capability structure */ 3966 off = PCI_EXTCAPLIST_BASE; 3967 rval = regs[o2i(off)]; 3968 if (rval == 0xffffffff || rval == 0) 3969 return; 3970 3971 /* Clear table */ 3972 for (i = 0; i < __arraycount(pci_extcaptab); i++) 3973 foundtable[i] = false; 3974 3975 /* Print extended capability register's offset and the type first */ 3976 for (;;) { 3977 printf(" Extended Capability Register at 0x%02x\n", off); 3978 3979 foundcap = PCI_EXTCAPLIST_CAP(rval); 3980 printf(" type: 0x%04x (", foundcap); 3981 if (foundcap < __arraycount(pci_extcaptab)) { 3982 printf("%s)\n", pci_extcaptab[foundcap].name); 3983 /* Mark as found */ 3984 foundtable[foundcap] = true; 3985 } else 3986 printf("unknown)\n"); 3987 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 3988 3989 off = PCI_EXTCAPLIST_NEXT(rval); 3990 if (off == 0) 3991 break; 3992 else if (off <= PCI_CONF_SIZE) { 3993 printf(" next pointer: 0x%03x (incorrect)\n", off); 3994 return; 3995 } 3996 rval = regs[o2i(off)]; 3997 } 3998 3999 /* 4000 * And then, print the detail of each capability registers 4001 * in capability value's order. 4002 */ 4003 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 4004 if (foundtable[i] == false) 4005 continue; 4006 4007 /* 4008 * The type was found. Search capability list again and 4009 * print all capabilities that the capabiliy type is 4010 * the same. 4011 */ 4012 if (pci_conf_find_extcap(regs, capoff, i, &off) == 0) 4013 continue; 4014 rval = regs[o2i(off)]; 4015 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 4016 || (pci_extcaptab[i].printfunc == NULL)) 4017 continue; 4018 4019 pci_extcaptab[i].printfunc(regs, capoff, off); 4020 4021 } 4022 } 4023 4024 /* Print the Secondary Status Register. */ 4025 static void 4026 pci_conf_print_ssr(pcireg_t rval) 4027 { 4028 pcireg_t devsel; 4029 4030 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 4031 onoff("66 MHz capable", rval, __BIT(5)); 4032 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 4033 onoff("Fast back-to-back capable", rval, __BIT(7)); 4034 onoff("Data parity error detected", rval, __BIT(8)); 4035 4036 printf(" DEVSEL timing: "); 4037 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 4038 switch (devsel) { 4039 case 0: 4040 printf("fast"); 4041 break; 4042 case 1: 4043 printf("medium"); 4044 break; 4045 case 2: 4046 printf("slow"); 4047 break; 4048 default: 4049 printf("unknown/reserved"); /* XXX */ 4050 break; 4051 } 4052 printf(" (0x%x)\n", devsel); 4053 4054 onoff("Signalled target abort", rval, __BIT(11)); 4055 onoff("Received target abort", rval, __BIT(12)); 4056 onoff("Received master abort", rval, __BIT(13)); 4057 onoff("Received system error", rval, __BIT(14)); 4058 onoff("Detected parity error", rval, __BIT(15)); 4059 } 4060 4061 static void 4062 pci_conf_print_type0( 4063 #ifdef _KERNEL 4064 pci_chipset_tag_t pc, pcitag_t tag, 4065 #endif 4066 const pcireg_t *regs) 4067 { 4068 int off, width; 4069 pcireg_t rval; 4070 4071 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 4072 #ifdef _KERNEL 4073 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4074 #else 4075 width = pci_conf_print_bar(regs, off, NULL); 4076 #endif 4077 } 4078 4079 printf(" Cardbus CIS Pointer: 0x%08x\n", 4080 regs[o2i(PCI_CARDBUS_CIS_REG)]); 4081 4082 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 4083 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4084 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4085 4086 /* XXX */ 4087 printf(" Expansion ROM Base Address: 0x%08x\n", 4088 regs[o2i(PCI_MAPREG_ROM)]); 4089 4090 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4091 printf(" Capability list pointer: 0x%02x\n", 4092 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4093 else 4094 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4095 4096 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 4097 4098 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4099 printf(" Maximum Latency: 0x%02x\n", PCI_MAX_LAT(rval)); 4100 printf(" Minimum Grant: 0x%02x\n", PCI_MIN_GNT(rval)); 4101 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 4102 switch (PCI_INTERRUPT_PIN(rval)) { 4103 case PCI_INTERRUPT_PIN_NONE: 4104 printf("(none)"); 4105 break; 4106 case PCI_INTERRUPT_PIN_A: 4107 printf("(pin A)"); 4108 break; 4109 case PCI_INTERRUPT_PIN_B: 4110 printf("(pin B)"); 4111 break; 4112 case PCI_INTERRUPT_PIN_C: 4113 printf("(pin C)"); 4114 break; 4115 case PCI_INTERRUPT_PIN_D: 4116 printf("(pin D)"); 4117 break; 4118 default: 4119 printf("(? ? ?)"); 4120 break; 4121 } 4122 printf("\n"); 4123 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 4124 } 4125 4126 static void 4127 pci_conf_print_type1( 4128 #ifdef _KERNEL 4129 pci_chipset_tag_t pc, pcitag_t tag, 4130 #endif 4131 const pcireg_t *regs) 4132 { 4133 int off, width; 4134 pcireg_t rval; 4135 uint32_t base, limit; 4136 uint32_t base_h, limit_h; 4137 uint64_t pbase, plimit; 4138 int use_upper; 4139 4140 /* 4141 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 4142 * Bridge chip documentation, and may not be correct with 4143 * respect to various standards. (XXX) 4144 */ 4145 4146 for (off = 0x10; off < 0x18; off += width) { 4147 #ifdef _KERNEL 4148 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4149 #else 4150 width = pci_conf_print_bar(regs, off, NULL); 4151 #endif 4152 } 4153 4154 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4155 printf(" Primary bus number: 0x%02x\n", 4156 PCI_BRIDGE_BUS_PRIMARY(rval)); 4157 printf(" Secondary bus number: 0x%02x\n", 4158 PCI_BRIDGE_BUS_SECONDARY(rval)); 4159 printf(" Subordinate bus number: 0x%02x\n", 4160 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 4161 printf(" Secondary bus latency timer: 0x%02x\n", 4162 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 4163 4164 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 4165 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 4166 4167 /* I/O region */ 4168 printf(" I/O region:\n"); 4169 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 4170 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 4171 if (PCI_BRIDGE_IO_32BITS(rval)) 4172 use_upper = 1; 4173 else 4174 use_upper = 0; 4175 onoff("32bit I/O", rval, use_upper); 4176 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 4177 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 4178 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 4179 limit |= 0x00000fff; 4180 4181 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 4182 base_h = (rval >> 0) & 0xffff; 4183 limit_h = (rval >> 16) & 0xffff; 4184 printf(" base upper 16 bits register: 0x%04x\n", base_h); 4185 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 4186 4187 if (use_upper == 1) { 4188 base |= base_h << 16; 4189 limit |= limit_h << 16; 4190 } 4191 if (base < limit) { 4192 if (use_upper == 1) 4193 printf(" range: 0x%08x-0x%08x\n", base, limit); 4194 else 4195 printf(" range: 0x%04x-0x%04x\n", base, limit); 4196 } else 4197 printf(" range: not set\n"); 4198 4199 /* Non-prefetchable memory region */ 4200 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 4201 printf(" Memory region:\n"); 4202 printf(" base register: 0x%04x\n", 4203 (rval >> 0) & 0xffff); 4204 printf(" limit register: 0x%04x\n", 4205 (rval >> 16) & 0xffff); 4206 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 4207 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 4208 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 4209 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 4210 if (base < limit) 4211 printf(" range: 0x%08x-0x%08x\n", base, limit); 4212 else 4213 printf(" range: not set\n"); 4214 4215 /* Prefetchable memory region */ 4216 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 4217 printf(" Prefetchable memory region:\n"); 4218 printf(" base register: 0x%04x\n", 4219 (rval >> 0) & 0xffff); 4220 printf(" limit register: 0x%04x\n", 4221 (rval >> 16) & 0xffff); 4222 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 4223 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 4224 printf(" base upper 32 bits register: 0x%08x\n", 4225 base_h); 4226 printf(" limit upper 32 bits register: 0x%08x\n", 4227 limit_h); 4228 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 4229 use_upper = 1; 4230 else 4231 use_upper = 0; 4232 onoff("64bit memory address", rval, use_upper); 4233 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 4234 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 4235 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 4236 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 4237 if (use_upper == 1) { 4238 pbase |= (uint64_t)base_h << 32; 4239 plimit |= (uint64_t)limit_h << 32; 4240 } 4241 if (pbase < plimit) { 4242 if (use_upper == 1) 4243 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 4244 "\n", pbase, plimit); 4245 else 4246 printf(" range: 0x%08x-0x%08x\n", 4247 (uint32_t)pbase, (uint32_t)plimit); 4248 } else 4249 printf(" range: not set\n"); 4250 4251 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4252 printf(" Capability list pointer: 0x%02x\n", 4253 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4254 else 4255 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4256 4257 /* XXX */ 4258 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 4259 4260 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4261 printf(" Interrupt line: 0x%02x\n", 4262 (rval >> 0) & 0xff); 4263 printf(" Interrupt pin: 0x%02x ", 4264 (rval >> 8) & 0xff); 4265 switch ((rval >> 8) & 0xff) { 4266 case PCI_INTERRUPT_PIN_NONE: 4267 printf("(none)"); 4268 break; 4269 case PCI_INTERRUPT_PIN_A: 4270 printf("(pin A)"); 4271 break; 4272 case PCI_INTERRUPT_PIN_B: 4273 printf("(pin B)"); 4274 break; 4275 case PCI_INTERRUPT_PIN_C: 4276 printf("(pin C)"); 4277 break; 4278 case PCI_INTERRUPT_PIN_D: 4279 printf("(pin D)"); 4280 break; 4281 default: 4282 printf("(? ? ?)"); 4283 break; 4284 } 4285 printf("\n"); 4286 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 4287 & PCI_BRIDGE_CONTROL_MASK; 4288 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 4289 onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE); 4290 onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR); 4291 onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA); 4292 onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA); 4293 onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT); 4294 onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR); 4295 onoff("Fast back-to-back capable", rval,PCI_BRIDGE_CONTROL_SECFASTB2B); 4296 } 4297 4298 static void 4299 pci_conf_print_type2( 4300 #ifdef _KERNEL 4301 pci_chipset_tag_t pc, pcitag_t tag, 4302 #endif 4303 const pcireg_t *regs) 4304 { 4305 pcireg_t rval; 4306 4307 /* 4308 * XXX these need to be printed in more detail, need to be 4309 * XXX checked against specs/docs, etc. 4310 * 4311 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 4312 * controller chip documentation, and may not be correct with 4313 * respect to various standards. (XXX) 4314 */ 4315 4316 #ifdef _KERNEL 4317 pci_conf_print_bar(pc, tag, regs, 0x10, 4318 "CardBus socket/ExCA registers"); 4319 #else 4320 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 4321 #endif 4322 4323 /* Capability list pointer and secondary status register */ 4324 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 4325 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4326 printf(" Capability list pointer: 0x%02x\n", 4327 PCI_CAPLIST_PTR(rval)); 4328 else 4329 printf(" Reserved @ 0x14: 0x%04x\n", 4330 (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0))); 4331 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 4332 4333 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4334 printf(" PCI bus number: 0x%02x\n", 4335 (rval >> 0) & 0xff); 4336 printf(" CardBus bus number: 0x%02x\n", 4337 (rval >> 8) & 0xff); 4338 printf(" Subordinate bus number: 0x%02x\n", 4339 (rval >> 16) & 0xff); 4340 printf(" CardBus latency timer: 0x%02x\n", 4341 (rval >> 24) & 0xff); 4342 4343 /* XXX Print more prettily */ 4344 printf(" CardBus memory region 0:\n"); 4345 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 4346 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 4347 printf(" CardBus memory region 1:\n"); 4348 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 4349 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 4350 printf(" CardBus I/O region 0:\n"); 4351 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 4352 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 4353 printf(" CardBus I/O region 1:\n"); 4354 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 4355 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 4356 4357 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4358 printf(" Interrupt line: 0x%02x\n", 4359 (rval >> 0) & 0xff); 4360 printf(" Interrupt pin: 0x%02x ", 4361 (rval >> 8) & 0xff); 4362 switch ((rval >> 8) & 0xff) { 4363 case PCI_INTERRUPT_PIN_NONE: 4364 printf("(none)"); 4365 break; 4366 case PCI_INTERRUPT_PIN_A: 4367 printf("(pin A)"); 4368 break; 4369 case PCI_INTERRUPT_PIN_B: 4370 printf("(pin B)"); 4371 break; 4372 case PCI_INTERRUPT_PIN_C: 4373 printf("(pin C)"); 4374 break; 4375 case PCI_INTERRUPT_PIN_D: 4376 printf("(pin D)"); 4377 break; 4378 default: 4379 printf("(? ? ?)"); 4380 break; 4381 } 4382 printf("\n"); 4383 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> 16) & 0xffff; 4384 printf(" Bridge control register: 0x%04x\n", rval); 4385 onoff("Parity error response", rval, __BIT(0)); 4386 onoff("SERR# enable", rval, __BIT(1)); 4387 onoff("ISA enable", rval, __BIT(2)); 4388 onoff("VGA enable", rval, __BIT(3)); 4389 onoff("Master abort mode", rval, __BIT(5)); 4390 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 4391 onoff("Functional interrupts routed by ExCA registers", rval, 4392 __BIT(7)); 4393 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 4394 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 4395 onoff("Write posting enable", rval, __BIT(10)); 4396 4397 rval = regs[o2i(0x40)]; 4398 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4399 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4400 4401 #ifdef _KERNEL 4402 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers"); 4403 #else 4404 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 4405 #endif 4406 } 4407 4408 void 4409 pci_conf_print( 4410 #ifdef _KERNEL 4411 pci_chipset_tag_t pc, pcitag_t tag, 4412 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 4413 #else 4414 int pcifd, u_int bus, u_int dev, u_int func 4415 #endif 4416 ) 4417 { 4418 pcireg_t regs[o2i(PCI_EXTCONF_SIZE)]; 4419 int off, capoff, endoff, hdrtype; 4420 const char *type_name; 4421 #ifdef _KERNEL 4422 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 4423 #else 4424 void (*type_printfn)(const pcireg_t *); 4425 #endif 4426 4427 printf("PCI configuration registers:\n"); 4428 4429 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 4430 #ifdef _KERNEL 4431 regs[o2i(off)] = pci_conf_read(pc, tag, off); 4432 #else 4433 if (pcibus_conf_read(pcifd, bus, dev, func, off, 4434 ®s[o2i(off)]) == -1) 4435 regs[o2i(off)] = 0; 4436 #endif 4437 } 4438 4439 /* common header */ 4440 printf(" Common header:\n"); 4441 pci_conf_print_regs(regs, 0, 16); 4442 4443 printf("\n"); 4444 #ifdef _KERNEL 4445 pci_conf_print_common(pc, tag, regs); 4446 #else 4447 pci_conf_print_common(regs); 4448 #endif 4449 printf("\n"); 4450 4451 /* type-dependent header */ 4452 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 4453 switch (hdrtype) { /* XXX make a table, eventually */ 4454 case 0: 4455 /* Standard device header */ 4456 type_name = "\"normal\" device"; 4457 type_printfn = &pci_conf_print_type0; 4458 capoff = PCI_CAPLISTPTR_REG; 4459 endoff = 64; 4460 break; 4461 case 1: 4462 /* PCI-PCI bridge header */ 4463 type_name = "PCI-PCI bridge"; 4464 type_printfn = &pci_conf_print_type1; 4465 capoff = PCI_CAPLISTPTR_REG; 4466 endoff = 64; 4467 break; 4468 case 2: 4469 /* PCI-CardBus bridge header */ 4470 type_name = "PCI-CardBus bridge"; 4471 type_printfn = &pci_conf_print_type2; 4472 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 4473 endoff = 72; 4474 break; 4475 default: 4476 type_name = NULL; 4477 type_printfn = 0; 4478 capoff = -1; 4479 endoff = 64; 4480 break; 4481 } 4482 printf(" Type %d ", hdrtype); 4483 if (type_name != NULL) 4484 printf("(%s) ", type_name); 4485 printf("header:\n"); 4486 pci_conf_print_regs(regs, 16, endoff); 4487 printf("\n"); 4488 if (type_printfn) { 4489 #ifdef _KERNEL 4490 (*type_printfn)(pc, tag, regs); 4491 #else 4492 (*type_printfn)(regs); 4493 #endif 4494 } else 4495 printf(" Don't know how to pretty-print type %d header.\n", 4496 hdrtype); 4497 printf("\n"); 4498 4499 /* capability list, if present */ 4500 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4501 && (capoff > 0)) { 4502 #ifdef _KERNEL 4503 pci_conf_print_caplist(pc, tag, regs, capoff); 4504 #else 4505 pci_conf_print_caplist(regs, capoff); 4506 #endif 4507 printf("\n"); 4508 } 4509 4510 /* device-dependent header */ 4511 printf(" Device-dependent header:\n"); 4512 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 4513 printf("\n"); 4514 #ifdef _KERNEL 4515 if (printfn) 4516 (*printfn)(pc, tag, regs); 4517 else 4518 printf(" Don't know how to pretty-print device-dependent header.\n"); 4519 printf("\n"); 4520 #endif /* _KERNEL */ 4521 4522 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 4523 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 4524 return; 4525 4526 #ifdef _KERNEL 4527 pci_conf_print_extcaplist(pc, tag, regs, capoff); 4528 #else 4529 pci_conf_print_extcaplist(regs, capoff); 4530 #endif 4531 printf("\n"); 4532 4533 /* Extended Configuration Space, if present */ 4534 printf(" Extended Configuration Space:\n"); 4535 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 4536 } 4537
Indexes created Tue Sep 23 21:09:50 GMT 2025