pci_subr.c revision 1.191
1 /* $NetBSD: pci_subr.c,v 1.191 2017/10/05 06:14:30 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.191 2017/10/05 06:14:30 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdarg.h> 58 #include <stdbool.h> 59 #include <stdio.h> 60 #include <stdlib.h> 61 #include <string.h> 62 #endif 63 64 #include <dev/pci/pcireg.h> 65 #ifdef _KERNEL 66 #include <dev/pci/pcivar.h> 67 #else 68 #include <dev/pci/pci_verbose.h> 69 #include <dev/pci/pcidevs.h> 70 #include <dev/pci/pcidevs_data.h> 71 #endif 72 73 static int pci_conf_find_cap(const pcireg_t *, int, unsigned int, int *); 74 static void pci_conf_print_pcie_power(uint8_t, unsigned int); 75 76 /* 77 * Descriptions of known PCI classes and subclasses. 78 * 79 * Subclasses are described in the same way as classes, but have a 80 * NULL subclass pointer. 81 */ 82 struct pci_class { 83 const char *name; 84 u_int val; /* as wide as pci_{,sub}class_t */ 85 const struct pci_class *subclasses; 86 }; 87 88 /* 89 * Class 0x00. 90 * Before rev. 2.0. 91 */ 92 static const struct pci_class pci_subclass_prehistoric[] = { 93 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 94 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 95 { NULL, 0, NULL, }, 96 }; 97 98 /* 99 * Class 0x01. 100 * Mass storage controller 101 */ 102 103 /* ATA programming interface */ 104 static const struct pci_class pci_interface_ata[] = { 105 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 106 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 107 { NULL, 0, NULL, }, 108 }; 109 110 /* SATA programming interface */ 111 static const struct pci_class pci_interface_sata[] = { 112 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 113 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 114 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 115 { NULL, 0, NULL, }, 116 }; 117 118 /* Flash programming interface */ 119 static const struct pci_class pci_interface_nvm[] = { 120 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 121 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 122 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 123 { NULL, 0, NULL, }, 124 }; 125 126 /* Subclasses */ 127 static const struct pci_class pci_subclass_mass_storage[] = { 128 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 129 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 130 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 131 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 132 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 133 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 134 pci_interface_ata, }, 135 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 136 pci_interface_sata, }, 137 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 138 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 139 pci_interface_nvm, }, 140 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 141 { NULL, 0, NULL, }, 142 }; 143 144 /* 145 * Class 0x02. 146 * Network controller. 147 */ 148 static const struct pci_class pci_subclass_network[] = { 149 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 150 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 151 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 152 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 153 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 154 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 155 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 156 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 157 { NULL, 0, NULL, }, 158 }; 159 160 /* 161 * Class 0x03. 162 * Display controller. 163 */ 164 165 /* VGA programming interface */ 166 static const struct pci_class pci_interface_vga[] = { 167 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 168 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 169 { NULL, 0, NULL, }, 170 }; 171 /* Subclasses */ 172 static const struct pci_class pci_subclass_display[] = { 173 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 174 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 175 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 176 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 177 { NULL, 0, NULL, }, 178 }; 179 180 /* 181 * Class 0x04. 182 * Multimedia device. 183 */ 184 static const struct pci_class pci_subclass_multimedia[] = { 185 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 186 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 187 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 188 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 189 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 190 { NULL, 0, NULL, }, 191 }; 192 193 /* 194 * Class 0x05. 195 * Memory controller. 196 */ 197 static const struct pci_class pci_subclass_memory[] = { 198 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 199 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 200 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 201 { NULL, 0, NULL, }, 202 }; 203 204 /* 205 * Class 0x06. 206 * Bridge device. 207 */ 208 209 /* PCI bridge programming interface */ 210 static const struct pci_class pci_interface_pcibridge[] = { 211 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 212 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 213 { NULL, 0, NULL, }, 214 }; 215 216 /* Semi-transparent PCI-to-PCI bridge programming interface */ 217 static const struct pci_class pci_interface_stpci[] = { 218 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 219 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 220 { NULL, 0, NULL, }, 221 }; 222 223 /* Advanced Switching programming interface */ 224 static const struct pci_class pci_interface_advsw[] = { 225 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 226 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 227 { NULL, 0, NULL, }, 228 }; 229 230 /* Subclasses */ 231 static const struct pci_class pci_subclass_bridge[] = { 232 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 233 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 234 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 235 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 236 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 237 pci_interface_pcibridge, }, 238 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 239 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 240 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 241 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 242 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 243 pci_interface_stpci, }, 244 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 245 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 246 pci_interface_advsw, }, 247 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 248 { NULL, 0, NULL, }, 249 }; 250 251 /* 252 * Class 0x07. 253 * Simple communications controller. 254 */ 255 256 /* Serial controller programming interface */ 257 static const struct pci_class pci_interface_serial[] = { 258 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 259 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 260 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 261 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 262 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 263 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 264 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 265 { NULL, 0, NULL, }, 266 }; 267 268 /* Parallel controller programming interface */ 269 static const struct pci_class pci_interface_parallel[] = { 270 { "", PCI_INTERFACE_PARALLEL, NULL,}, 271 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 272 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 273 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 274 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 275 { NULL, 0, NULL,}, 276 }; 277 278 /* Modem programming interface */ 279 static const struct pci_class pci_interface_modem[] = { 280 { "", PCI_INTERFACE_MODEM, NULL,}, 281 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 282 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 283 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 284 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 285 { NULL, 0, NULL,}, 286 }; 287 288 /* Subclasses */ 289 static const struct pci_class pci_subclass_communications[] = { 290 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 291 pci_interface_serial, }, 292 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 293 pci_interface_parallel, }, 294 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 295 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 296 pci_interface_modem, }, 297 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 298 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 299 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 300 { NULL, 0, NULL,}, 301 }; 302 303 /* 304 * Class 0x08. 305 * Base system peripheral. 306 */ 307 308 /* PIC programming interface */ 309 static const struct pci_class pci_interface_pic[] = { 310 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 311 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 312 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 313 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 314 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 315 { NULL, 0, NULL, }, 316 }; 317 318 /* DMA programming interface */ 319 static const struct pci_class pci_interface_dma[] = { 320 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 321 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 322 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 323 { NULL, 0, NULL, }, 324 }; 325 326 /* Timer programming interface */ 327 static const struct pci_class pci_interface_tmr[] = { 328 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 329 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 330 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 331 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 332 { NULL, 0, NULL, }, 333 }; 334 335 /* RTC programming interface */ 336 static const struct pci_class pci_interface_rtc[] = { 337 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 338 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 339 { NULL, 0, NULL, }, 340 }; 341 342 /* Subclasses */ 343 static const struct pci_class pci_subclass_system[] = { 344 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 345 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 346 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 347 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 348 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 349 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 350 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 351 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 352 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 353 { NULL, 0, NULL, }, 354 }; 355 356 /* 357 * Class 0x09. 358 * Input device. 359 */ 360 361 /* Gameport programming interface */ 362 static const struct pci_class pci_interface_game[] = { 363 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 364 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 365 { NULL, 0, NULL, }, 366 }; 367 368 /* Subclasses */ 369 static const struct pci_class pci_subclass_input[] = { 370 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 371 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 372 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 373 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 374 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 375 pci_interface_game, }, 376 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 377 { NULL, 0, NULL, }, 378 }; 379 380 /* 381 * Class 0x0a. 382 * Docking station. 383 */ 384 static const struct pci_class pci_subclass_dock[] = { 385 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 386 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 387 { NULL, 0, NULL, }, 388 }; 389 390 /* 391 * Class 0x0b. 392 * Processor. 393 */ 394 static const struct pci_class pci_subclass_processor[] = { 395 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 396 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 397 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 398 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 399 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 400 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 401 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 402 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 403 { NULL, 0, NULL, }, 404 }; 405 406 /* 407 * Class 0x0c. 408 * Serial bus controller. 409 */ 410 411 /* IEEE1394 programming interface */ 412 static const struct pci_class pci_interface_ieee1394[] = { 413 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 414 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 415 { NULL, 0, NULL,}, 416 }; 417 418 /* USB programming interface */ 419 static const struct pci_class pci_interface_usb[] = { 420 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 421 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 422 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 423 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 424 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 425 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 426 { NULL, 0, NULL, }, 427 }; 428 429 /* IPMI programming interface */ 430 static const struct pci_class pci_interface_ipmi[] = { 431 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 432 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 433 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 434 { NULL, 0, NULL,}, 435 }; 436 437 /* Subclasses */ 438 static const struct pci_class pci_subclass_serialbus[] = { 439 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 440 pci_interface_ieee1394, }, 441 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 442 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 443 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 444 pci_interface_usb, }, 445 /* XXX Fiber Channel/_FIBRECHANNEL */ 446 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 447 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 448 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 449 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 450 pci_interface_ipmi, }, 451 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 452 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 453 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 454 { NULL, 0, NULL, }, 455 }; 456 457 /* 458 * Class 0x0d. 459 * Wireless Controller. 460 */ 461 static const struct pci_class pci_subclass_wireless[] = { 462 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 463 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 464 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 465 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 466 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 467 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 468 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 469 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 470 { NULL, 0, NULL, }, 471 }; 472 473 /* 474 * Class 0x0e. 475 * Intelligent IO controller. 476 */ 477 478 /* Intelligent IO programming interface */ 479 static const struct pci_class pci_interface_i2o[] = { 480 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 481 { NULL, 0, NULL,}, 482 }; 483 484 /* Subclasses */ 485 static const struct pci_class pci_subclass_i2o[] = { 486 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 487 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 488 { NULL, 0, NULL, }, 489 }; 490 491 /* 492 * Class 0x0f. 493 * Satellite communication controller. 494 */ 495 static const struct pci_class pci_subclass_satcom[] = { 496 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 497 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 498 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 499 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 500 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 501 { NULL, 0, NULL, }, 502 }; 503 504 /* 505 * Class 0x10. 506 * Encryption/Decryption controller. 507 */ 508 static const struct pci_class pci_subclass_crypto[] = { 509 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 510 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 511 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 512 { NULL, 0, NULL, }, 513 }; 514 515 /* 516 * Class 0x11. 517 * Data aquuisition and signal processing controller. 518 */ 519 static const struct pci_class pci_subclass_dasp[] = { 520 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 521 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 522 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 523 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 524 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 525 { NULL, 0, NULL, }, 526 }; 527 528 /* List of classes */ 529 static const struct pci_class pci_classes[] = { 530 { "prehistoric", PCI_CLASS_PREHISTORIC, 531 pci_subclass_prehistoric, }, 532 { "mass storage", PCI_CLASS_MASS_STORAGE, 533 pci_subclass_mass_storage, }, 534 { "network", PCI_CLASS_NETWORK, 535 pci_subclass_network, }, 536 { "display", PCI_CLASS_DISPLAY, 537 pci_subclass_display, }, 538 { "multimedia", PCI_CLASS_MULTIMEDIA, 539 pci_subclass_multimedia, }, 540 { "memory", PCI_CLASS_MEMORY, 541 pci_subclass_memory, }, 542 { "bridge", PCI_CLASS_BRIDGE, 543 pci_subclass_bridge, }, 544 { "communications", PCI_CLASS_COMMUNICATIONS, 545 pci_subclass_communications, }, 546 { "system", PCI_CLASS_SYSTEM, 547 pci_subclass_system, }, 548 { "input", PCI_CLASS_INPUT, 549 pci_subclass_input, }, 550 { "dock", PCI_CLASS_DOCK, 551 pci_subclass_dock, }, 552 { "processor", PCI_CLASS_PROCESSOR, 553 pci_subclass_processor, }, 554 { "serial bus", PCI_CLASS_SERIALBUS, 555 pci_subclass_serialbus, }, 556 { "wireless", PCI_CLASS_WIRELESS, 557 pci_subclass_wireless, }, 558 { "I2O", PCI_CLASS_I2O, 559 pci_subclass_i2o, }, 560 { "satellite comm", PCI_CLASS_SATCOM, 561 pci_subclass_satcom, }, 562 { "crypto", PCI_CLASS_CRYPTO, 563 pci_subclass_crypto, }, 564 { "DASP", PCI_CLASS_DASP, 565 pci_subclass_dasp, }, 566 { "processing accelerators", PCI_CLASS_ACCEL, 567 NULL, }, 568 { "non-essential instrumentation", PCI_CLASS_INSTRUMENT, 569 NULL, }, 570 { "undefined", PCI_CLASS_UNDEFINED, 571 NULL, }, 572 { NULL, 0, 573 NULL, }, 574 }; 575 576 DEV_VERBOSE_DEFINE(pci); 577 578 /* 579 * Append a formatted string to dest without writing more than len 580 * characters (including the trailing NUL character). dest and len 581 * are updated for use in subsequent calls to snappendf(). 582 * 583 * Returns 0 on success, a negative value if vnsprintf() fails, or 584 * a positive value if the dest buffer would have overflowed. 585 */ 586 587 static int __printflike(3,4) 588 snappendf(char **dest, size_t *len, const char * restrict fmt, ...) 589 { 590 va_list ap; 591 int count; 592 593 va_start(ap, fmt); 594 count = vsnprintf(*dest, *len, fmt, ap); 595 va_end(ap); 596 597 /* Let vsnprintf() errors bubble up to caller */ 598 if (count < 0 || *len == 0) 599 return count; 600 601 /* Handle overflow */ 602 if ((size_t)count >= *len) { 603 *dest += *len - 1; 604 *len = 1; 605 return 1; 606 } 607 608 /* Update dest & len to point at trailing NUL */ 609 *dest += count; 610 *len -= count; 611 612 return 0; 613 } 614 615 void 616 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 617 size_t l) 618 { 619 pci_class_t class; 620 pci_subclass_t subclass; 621 pci_interface_t interface; 622 pci_revision_t revision; 623 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 624 const struct pci_class *classp, *subclassp, *interfacep; 625 626 class = PCI_CLASS(class_reg); 627 subclass = PCI_SUBCLASS(class_reg); 628 interface = PCI_INTERFACE(class_reg); 629 revision = PCI_REVISION(class_reg); 630 631 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 632 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 633 PCI_PRODUCT(id_reg)); 634 635 classp = pci_classes; 636 while (classp->name != NULL) { 637 if (class == classp->val) 638 break; 639 classp++; 640 } 641 642 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 643 while (subclassp && subclassp->name != NULL) { 644 if (subclass == subclassp->val) 645 break; 646 subclassp++; 647 } 648 649 interfacep = (subclassp && subclassp->name != NULL) ? 650 subclassp->subclasses : NULL; 651 while (interfacep && interfacep->name != NULL) { 652 if (interface == interfacep->val) 653 break; 654 interfacep++; 655 } 656 657 (void)snappendf(&cp, &l, "%s %s", vendor, product); 658 if (showclass) { 659 (void)snappendf(&cp, &l, " ("); 660 if (classp->name == NULL) 661 (void)snappendf(&cp, &l, 662 "class 0x%02x, subclass 0x%02x", 663 class, subclass); 664 else { 665 if (subclassp == NULL || subclassp->name == NULL) 666 (void)snappendf(&cp, &l, 667 "%s, subclass 0x%02x", 668 classp->name, subclass); 669 else 670 (void)snappendf(&cp, &l, "%s %s", 671 subclassp->name, classp->name); 672 } 673 if ((interfacep == NULL) || (interfacep->name == NULL)) { 674 if (interface != 0) 675 (void)snappendf(&cp, &l, ", interface 0x%02x", 676 interface); 677 } else if (strncmp(interfacep->name, "", 1) != 0) 678 (void)snappendf(&cp, &l, ", %s", interfacep->name); 679 if (revision != 0) 680 (void)snappendf(&cp, &l, ", revision 0x%02x", revision); 681 (void)snappendf(&cp, &l, ")"); 682 } 683 } 684 685 #ifdef _KERNEL 686 void 687 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 688 const char *known, int addrev) 689 { 690 char devinfo[256]; 691 692 if (known) { 693 aprint_normal(": %s", known); 694 if (addrev) 695 aprint_normal(" (rev. 0x%02x)", 696 PCI_REVISION(pa->pa_class)); 697 aprint_normal("\n"); 698 } else { 699 pci_devinfo(pa->pa_id, pa->pa_class, 0, 700 devinfo, sizeof(devinfo)); 701 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 702 PCI_REVISION(pa->pa_class)); 703 } 704 if (naive) 705 aprint_naive(": %s\n", naive); 706 else 707 aprint_naive("\n"); 708 } 709 #endif 710 711 /* 712 * Print out most of the PCI configuration registers. Typically used 713 * in a device attach routine like this: 714 * 715 * #ifdef MYDEV_DEBUG 716 * printf("%s: ", device_xname(sc->sc_dev)); 717 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 718 * #endif 719 */ 720 721 #define i2o(i) ((i) * 4) 722 #define o2i(o) ((o) / 4) 723 #define onoff2(str, rval, bit, onstr, offstr) \ 724 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 725 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 726 727 static void 728 pci_conf_print_common( 729 #ifdef _KERNEL 730 pci_chipset_tag_t pc, pcitag_t tag, 731 #endif 732 const pcireg_t *regs) 733 { 734 pci_class_t class; 735 pci_subclass_t subclass; 736 pci_interface_t interface; 737 pci_revision_t revision; 738 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 739 const struct pci_class *classp, *subclassp, *interfacep; 740 const char *name; 741 pcireg_t rval; 742 unsigned int num; 743 744 rval = regs[o2i(PCI_CLASS_REG)]; 745 class = PCI_CLASS(rval); 746 subclass = PCI_SUBCLASS(rval); 747 interface = PCI_INTERFACE(rval); 748 revision = PCI_REVISION(rval); 749 750 rval = regs[o2i(PCI_ID_REG)]; 751 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 752 if (name) 753 printf(" Vendor Name: %s (0x%04x)\n", name, 754 PCI_VENDOR(rval)); 755 else 756 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 757 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 758 PCI_PRODUCT(rval)); 759 if (name) 760 printf(" Device Name: %s (0x%04x)\n", name, 761 PCI_PRODUCT(rval)); 762 else 763 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 764 765 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 766 767 printf(" Command register: 0x%04x\n", rval & 0xffff); 768 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 769 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 770 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 771 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 772 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 773 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 774 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 775 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 776 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 777 onoff("Fast back-to-back transactions", rval, 778 PCI_COMMAND_BACKTOBACK_ENABLE); 779 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 780 781 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 782 onoff("Immediate Readiness", rval, PCI_STATUS_IMMD_READNESS); 783 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 784 "inactive"); 785 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 786 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 787 onoff("User Definable Features (UDF) support", rval, 788 PCI_STATUS_UDF_SUPPORT); 789 onoff("Fast back-to-back capable", rval, 790 PCI_STATUS_BACKTOBACK_SUPPORT); 791 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 792 793 printf(" DEVSEL timing: "); 794 switch (rval & PCI_STATUS_DEVSEL_MASK) { 795 case PCI_STATUS_DEVSEL_FAST: 796 printf("fast"); 797 break; 798 case PCI_STATUS_DEVSEL_MEDIUM: 799 printf("medium"); 800 break; 801 case PCI_STATUS_DEVSEL_SLOW: 802 printf("slow"); 803 break; 804 default: 805 printf("unknown/reserved"); /* XXX */ 806 break; 807 } 808 printf(" (0x%x)\n", __SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK)); 809 810 onoff("Slave signaled Target Abort", rval, 811 PCI_STATUS_TARGET_TARGET_ABORT); 812 onoff("Master received Target Abort", rval, 813 PCI_STATUS_MASTER_TARGET_ABORT); 814 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 815 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 816 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 817 818 rval = regs[o2i(PCI_CLASS_REG)]; 819 for (classp = pci_classes; classp->name != NULL; classp++) { 820 if (class == classp->val) 821 break; 822 } 823 824 /* 825 * ECN: Change Root Complex Event Collector Class Code 826 * Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type 827 * in PCIe extend capability to know whether it's RCEC or IOMMU. 828 */ 829 if ((class == PCI_CLASS_SYSTEM) 830 && (subclass == PCI_SUBCLASS_SYSTEM_IOMMU)) { 831 int pcie_capoff; 832 pcireg_t reg; 833 834 if (pci_conf_find_cap(regs, PCI_CAPLISTPTR_REG, 835 PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 836 reg = regs[o2i(pcie_capoff + PCIE_XCAP)]; 837 if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_ROOT_EVNTC) 838 subclass = PCI_SUBCLASS_SYSTEM_RCEC; 839 } 840 } 841 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 842 while (subclassp && subclassp->name != NULL) { 843 if (subclass == subclassp->val) 844 break; 845 subclassp++; 846 } 847 848 interfacep = (subclassp && subclassp->name != NULL) ? 849 subclassp->subclasses : NULL; 850 while (interfacep && interfacep->name != NULL) { 851 if (interface == interfacep->val) 852 break; 853 interfacep++; 854 } 855 856 if (classp->name != NULL) 857 printf(" Class Name: %s (0x%02x)\n", classp->name, class); 858 else 859 printf(" Class ID: 0x%02x\n", class); 860 if (subclassp != NULL && subclassp->name != NULL) 861 printf(" Subclass Name: %s (0x%02x)\n", 862 subclassp->name, PCI_SUBCLASS(rval)); 863 else 864 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 865 if ((interfacep != NULL) && (interfacep->name != NULL) 866 && (strncmp(interfacep->name, "", 1) != 0)) 867 printf(" Interface Name: %s (0x%02x)\n", 868 interfacep->name, interface); 869 else 870 printf(" Interface: 0x%02x\n", interface); 871 printf(" Revision ID: 0x%02x\n", revision); 872 873 rval = regs[o2i(PCI_BHLC_REG)]; 874 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 875 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 876 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 877 PCI_HDRTYPE(rval)); 878 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 879 num = PCI_CACHELINE(rval); 880 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 881 } 882 883 static int 884 pci_conf_print_bar( 885 #ifdef _KERNEL 886 pci_chipset_tag_t pc, pcitag_t tag, 887 #endif 888 const pcireg_t *regs, int reg, const char *name) 889 { 890 int width; 891 pcireg_t rval, rval64h; 892 bool ioen, memen; 893 #ifdef _KERNEL 894 pcireg_t mask, mask64h = 0; 895 #endif 896 897 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 898 ioen = rval & PCI_COMMAND_IO_ENABLE; 899 memen = rval & PCI_COMMAND_MEM_ENABLE; 900 901 width = 4; 902 /* 903 * Section 6.2.5.1, `Address Maps', tells us that: 904 * 905 * 1) The builtin software should have already mapped the 906 * device in a reasonable way. 907 * 908 * 2) A device which wants 2^n bytes of memory will hardwire 909 * the bottom n bits of the address to 0. As recommended, 910 * we write all 1s and see what we get back. 911 */ 912 913 rval = regs[o2i(reg)]; 914 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 915 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 916 rval64h = regs[o2i(reg + 4)]; 917 width = 8; 918 } else 919 rval64h = 0; 920 921 #ifdef _KERNEL 922 if (rval != 0 && memen) { 923 int s; 924 925 /* 926 * The following sequence seems to make some devices 927 * (e.g. host bus bridges, which don't normally 928 * have their space mapped) very unhappy, to 929 * the point of crashing the system. 930 * 931 * Therefore, if the mapping register is zero to 932 * start out with, don't bother trying. 933 */ 934 s = splhigh(); 935 pci_conf_write(pc, tag, reg, 0xffffffff); 936 mask = pci_conf_read(pc, tag, reg); 937 pci_conf_write(pc, tag, reg, rval); 938 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 939 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 940 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 941 mask64h = pci_conf_read(pc, tag, reg + 4); 942 pci_conf_write(pc, tag, reg + 4, rval64h); 943 } 944 splx(s); 945 } else 946 mask = mask64h = 0; 947 #endif /* _KERNEL */ 948 949 printf(" Base address register at 0x%02x", reg); 950 if (name) 951 printf(" (%s)", name); 952 printf("\n "); 953 if (rval == 0) { 954 printf("not implemented\n"); 955 return width; 956 } 957 printf("type: "); 958 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 959 const char *type, *prefetch; 960 961 switch (PCI_MAPREG_MEM_TYPE(rval)) { 962 case PCI_MAPREG_MEM_TYPE_32BIT: 963 type = "32-bit"; 964 break; 965 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 966 type = "32-bit-1M"; 967 break; 968 case PCI_MAPREG_MEM_TYPE_64BIT: 969 type = "64-bit"; 970 break; 971 default: 972 type = "unknown (XXX)"; 973 break; 974 } 975 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 976 prefetch = ""; 977 else 978 prefetch = "non"; 979 printf("%s %sprefetchable memory\n", type, prefetch); 980 switch (PCI_MAPREG_MEM_TYPE(rval)) { 981 case PCI_MAPREG_MEM_TYPE_64BIT: 982 printf(" base: 0x%016llx", 983 PCI_MAPREG_MEM64_ADDR( 984 ((((long long) rval64h) << 32) | rval))); 985 if (!memen) 986 printf(", disabled"); 987 printf("\n"); 988 #ifdef _KERNEL 989 printf(" size: 0x%016llx\n", 990 PCI_MAPREG_MEM64_SIZE( 991 ((((long long) mask64h) << 32) | mask))); 992 #endif 993 break; 994 case PCI_MAPREG_MEM_TYPE_32BIT: 995 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 996 default: 997 printf(" base: 0x%08x", 998 PCI_MAPREG_MEM_ADDR(rval)); 999 if (!memen) 1000 printf(", disabled"); 1001 printf("\n"); 1002 #ifdef _KERNEL 1003 printf(" size: 0x%08x\n", 1004 PCI_MAPREG_MEM_SIZE(mask)); 1005 #endif 1006 break; 1007 } 1008 } else { 1009 #ifdef _KERNEL 1010 if (ioen) 1011 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 1012 #endif 1013 printf("I/O\n"); 1014 printf(" base: 0x%08x", PCI_MAPREG_IO_ADDR(rval)); 1015 if (!ioen) 1016 printf(", disabled"); 1017 printf("\n"); 1018 #ifdef _KERNEL 1019 printf(" size: 0x%08x\n", PCI_MAPREG_IO_SIZE(mask)); 1020 #endif 1021 } 1022 1023 return width; 1024 } 1025 1026 static void 1027 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 1028 { 1029 int off, needaddr, neednl; 1030 1031 needaddr = 1; 1032 neednl = 0; 1033 for (off = first; off < pastlast; off += 4) { 1034 if ((off % 16) == 0 || needaddr) { 1035 printf(" 0x%02x:", off); 1036 needaddr = 0; 1037 } 1038 printf(" 0x%08x", regs[o2i(off)]); 1039 neednl = 1; 1040 if ((off % 16) == 12) { 1041 printf("\n"); 1042 neednl = 0; 1043 } 1044 } 1045 if (neednl) 1046 printf("\n"); 1047 } 1048 1049 static const char * 1050 pci_conf_print_agp_calcycle(uint8_t cal) 1051 { 1052 1053 switch (cal) { 1054 case 0x0: 1055 return "4ms"; 1056 case 0x1: 1057 return "16ms"; 1058 case 0x2: 1059 return "64ms"; 1060 case 0x3: 1061 return "256ms"; 1062 case 0x7: 1063 return "Calibration Cycle Not Needed"; 1064 default: 1065 return "(reserved)"; 1066 } 1067 } 1068 1069 static void 1070 pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3) 1071 { 1072 if (isagp3) { 1073 /* AGP 3.0 */ 1074 if (reg & AGP_MODE_V3_RATE_4x) 1075 printf("x4"); 1076 if (reg & AGP_MODE_V3_RATE_8x) 1077 printf("x8"); 1078 } else { 1079 /* AGP 2.0 */ 1080 if (reg & AGP_MODE_V2_RATE_1x) 1081 printf("x1"); 1082 if (reg & AGP_MODE_V2_RATE_2x) 1083 printf("x2"); 1084 if (reg & AGP_MODE_V2_RATE_4x) 1085 printf("x4"); 1086 } 1087 printf("\n"); 1088 } 1089 1090 static void 1091 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1092 { 1093 pcireg_t rval; 1094 bool isagp3; 1095 1096 printf("\n AGP Capabilities Register\n"); 1097 1098 rval = regs[o2i(capoff)]; 1099 printf(" Revision: %d.%d\n", 1100 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1101 1102 rval = regs[o2i(capoff + PCI_AGP_STATUS)]; 1103 printf(" Status register: 0x%04x\n", rval); 1104 printf(" RQ: %d\n", 1105 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1106 printf(" ARQSZ: %d\n", 1107 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1108 printf(" CAL cycle: %s\n", 1109 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1110 onoff("SBA", rval, AGP_MODE_SBA); 1111 onoff("htrans#", rval, AGP_MODE_HTRANS); 1112 onoff("Over 4G", rval, AGP_MODE_4G); 1113 onoff("Fast Write", rval, AGP_MODE_FW); 1114 onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3); 1115 isagp3 = rval & AGP_MODE_MODE_3; 1116 printf(" Data Rate Support: "); 1117 pci_conf_print_agp_datarate(rval, isagp3); 1118 1119 rval = regs[o2i(capoff + PCI_AGP_COMMAND)]; 1120 printf(" Command register: 0x%08x\n", rval); 1121 printf(" PRQ: %d\n", 1122 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1123 printf(" PARQSZ: %d\n", 1124 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1125 printf(" PCAL cycle: %s\n", 1126 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1127 onoff("SBA", rval, AGP_MODE_SBA); 1128 onoff("AGP", rval, AGP_MODE_AGP); 1129 onoff("Over 4G", rval, AGP_MODE_4G); 1130 onoff("Fast Write", rval, AGP_MODE_FW); 1131 if (isagp3) { 1132 printf(" Data Rate Enable: "); 1133 /* 1134 * The Data Rate Enable bits are used only on 3.0 and the 1135 * Command register has no AGP_MODE_MODE_3 bit, so pass the 1136 * flag to print correctly. 1137 */ 1138 pci_conf_print_agp_datarate(rval, isagp3); 1139 } 1140 } 1141 1142 static const char * 1143 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1144 { 1145 1146 switch ((caps >> 6) & 7) { 1147 case 0: return "self-powered"; 1148 case 1: return "55 mA"; 1149 case 2: return "100 mA"; 1150 case 3: return "160 mA"; 1151 case 4: return "220 mA"; 1152 case 5: return "270 mA"; 1153 case 6: return "320 mA"; 1154 case 7: 1155 default: return "375 mA"; 1156 } 1157 } 1158 1159 static const char * 1160 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1161 { 1162 static const char unk[] = "unknown"; 1163 static const char *pmrev[8] = { 1164 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1165 }; 1166 if (val > 7) 1167 return unk; 1168 return pmrev[val]; 1169 } 1170 1171 static void 1172 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1173 { 1174 uint16_t caps, pmcsr; 1175 pcireg_t reg; 1176 1177 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1178 reg = regs[o2i(capoff + PCI_PMCSR)]; 1179 pmcsr = reg & 0xffff; 1180 1181 printf("\n PCI Power Management Capabilities Register\n"); 1182 1183 printf(" Capabilities register: 0x%04x\n", caps); 1184 printf(" Version: %s\n", 1185 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1186 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1187 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1188 printf(" 3.3V auxiliary current: %s\n", 1189 pci_conf_print_pcipm_cap_aux(caps)); 1190 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1191 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1192 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1193 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1194 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1195 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1196 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1197 1198 printf(" Control/status register: 0x%04x\n", pmcsr); 1199 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1200 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1201 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1202 printf(" PME# assertion: %sabled\n", 1203 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1204 printf(" Data Select: %d\n", 1205 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK)); 1206 printf(" Data Scale: %d\n", 1207 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK)); 1208 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1209 printf(" Bridge Support Extensions register: 0x%02x\n", 1210 (reg >> 16) & 0xff); 1211 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1212 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1213 printf(" Data register: 0x%02x\n", __SHIFTOUT(reg, PCI_PMCSR_DATA)); 1214 1215 } 1216 1217 /* XXX pci_conf_print_vpd_cap */ 1218 /* XXX pci_conf_print_slotid_cap */ 1219 1220 static void 1221 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1222 { 1223 uint32_t ctl, mmc, mme; 1224 1225 regs += o2i(capoff); 1226 ctl = *regs++; 1227 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1228 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1229 1230 printf("\n PCI Message Signaled Interrupt\n"); 1231 1232 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1233 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1234 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1235 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1236 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1237 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1238 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1239 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1240 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP); 1241 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN); 1242 printf(" Message Address %sregister: 0x%08x\n", 1243 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1244 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1245 printf(" Message Address %sregister: 0x%08x\n", 1246 "(upper) ", *regs++); 1247 } 1248 printf(" Message Data register: "); 1249 if (ctl & PCI_MSI_CTL_EXTMDATA_CAP) 1250 printf("0x%08x\n", *regs); 1251 else 1252 printf("0x%04x\n", *regs & 0xffff); 1253 regs++; 1254 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1255 printf(" Vector Mask register: 0x%08x\n", *regs++); 1256 printf(" Vector Pending register: 0x%08x\n", *regs++); 1257 } 1258 } 1259 1260 /* XXX pci_conf_print_cpci_hostwap_cap */ 1261 1262 /* 1263 * For both command register and status register. 1264 * The argument "idx" is index number (0 to 7). 1265 */ 1266 static int 1267 pcix_split_trans(unsigned int idx) 1268 { 1269 static int table[8] = { 1270 1, 2, 3, 4, 8, 12, 16, 32 1271 }; 1272 1273 if (idx >= __arraycount(table)) 1274 return -1; 1275 return table[idx]; 1276 } 1277 1278 static void 1279 pci_conf_print_pcix_cap_2ndbusmode(int num) 1280 { 1281 const char *maxfreq, *maxperiod; 1282 1283 printf(" Mode: "); 1284 if (num <= 0x07) 1285 printf("PCI-X Mode 1\n"); 1286 else if (num <= 0x0b) 1287 printf("PCI-X 266 (Mode 2)\n"); 1288 else 1289 printf("PCI-X 533 (Mode 2)\n"); 1290 1291 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1292 switch (num & 0x03) { 1293 default: 1294 case 0: 1295 maxfreq = "N/A"; 1296 maxperiod = "N/A"; 1297 break; 1298 case 1: 1299 maxfreq = "66MHz"; 1300 maxperiod = "15ns"; 1301 break; 1302 case 2: 1303 maxfreq = "100MHz"; 1304 maxperiod = "10ns"; 1305 break; 1306 case 3: 1307 maxfreq = "133MHz"; 1308 maxperiod = "7.5ns"; 1309 break; 1310 } 1311 printf(" Max Clock Freq: %s\n", maxfreq); 1312 printf(" Min Clock Period: %s\n", maxperiod); 1313 } 1314 1315 static void 1316 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1317 { 1318 pcireg_t reg; 1319 int isbridge; 1320 int i; 1321 1322 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1323 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1324 printf("\n PCI-X %s Capabilities Register\n", 1325 isbridge ? "Bridge" : "Non-bridge"); 1326 1327 reg = regs[o2i(capoff)]; 1328 if (isbridge != 0) { 1329 printf(" Secondary status register: 0x%04x\n", 1330 (reg & 0xffff0000) >> 16); 1331 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1332 onoff("133MHz capable", reg, PCIX_STATUS_133); 1333 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1334 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1335 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1336 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1337 pci_conf_print_pcix_cap_2ndbusmode( 1338 __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1339 printf(" Version: 0x%x\n", 1340 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1341 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1342 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1343 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1344 } else { 1345 printf(" Command register: 0x%04x\n", 1346 (reg & 0xffff0000) >> 16); 1347 onoff("Data Parity Error Recovery", reg, 1348 PCIX_CMD_PERR_RECOVER); 1349 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1350 printf(" Maximum Burst Read Count: %u\n", 1351 PCIX_CMD_BYTECNT(reg)); 1352 printf(" Maximum Split Transactions: %d\n", 1353 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1354 >> PCIX_CMD_SPLTRANS_SHIFT)); 1355 } 1356 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1357 printf(" %sStatus register: 0x%08x\n", 1358 isbridge ? "Bridge " : "", reg); 1359 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1360 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1361 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1362 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1363 onoff("133MHz capable", reg, PCIX_STATUS_133); 1364 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1365 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1366 if (isbridge != 0) { 1367 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1368 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1369 } else { 1370 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1371 "bridge device", "simple device"); 1372 printf(" Designed max memory read byte count: %d\n", 1373 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1374 >> PCIX_STATUS_MAXB_SHIFT)); 1375 printf(" Designed max outstanding split transaction: %d\n", 1376 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1377 >> PCIX_STATUS_MAXST_SHIFT)); 1378 printf(" MAX cumulative Read Size: %u\n", 1379 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1380 onoff("Received split completion error", reg, 1381 PCIX_STATUS_SCERR); 1382 } 1383 onoff("266MHz capable", reg, PCIX_STATUS_266); 1384 onoff("533MHz capable", reg, PCIX_STATUS_533); 1385 1386 if (isbridge == 0) 1387 return; 1388 1389 /* Only for bridge */ 1390 for (i = 0; i < 2; i++) { 1391 reg = regs[o2i(capoff + PCIX_BRIDGE_UP_STCR + (4 * i))]; 1392 printf(" %s split transaction control register: 0x%08x\n", 1393 (i == 0) ? "Upstream" : "Downstream", reg); 1394 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1395 printf(" Commitment Limit: %d\n", 1396 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1397 } 1398 } 1399 1400 /* pci_conf_print_ht_slave_cap */ 1401 /* pci_conf_print_ht_host_cap */ 1402 /* pci_conf_print_ht_switch_cap */ 1403 /* pci_conf_print_ht_intr_cap */ 1404 /* pci_conf_print_ht_revid_cap */ 1405 /* pci_conf_print_ht_unitid_cap */ 1406 /* pci_conf_print_ht_extcnf_cap */ 1407 /* pci_conf_print_ht_addrmap_cap */ 1408 /* pci_conf_print_ht_msimap_cap */ 1409 1410 static void 1411 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1412 { 1413 pcireg_t val; 1414 uint32_t lo, hi; 1415 1416 /* 1417 * Print the rest of the command register bits. Others are 1418 * printed in pci_conf_print_ht_cap(). 1419 */ 1420 val = regs[o2i(capoff + PCI_HT_CMD)]; 1421 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1422 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1423 1424 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1425 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1426 printf(" Address Low register: 0x%08x\n", lo); 1427 printf(" Address high register: 0x%08x\n", hi); 1428 printf(" Address: 0x%016" PRIx64 "\n", 1429 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1430 } 1431 1432 /* pci_conf_print_ht_droute_cap */ 1433 /* pci_conf_print_ht_vcset_cap */ 1434 /* pci_conf_print_ht_retry_cap */ 1435 /* pci_conf_print_ht_x86enc_cap */ 1436 /* pci_conf_print_ht_gen3_cap */ 1437 /* pci_conf_print_ht_fle_cap */ 1438 /* pci_conf_print_ht_pm_cap */ 1439 /* pci_conf_print_ht_hnc_cap */ 1440 1441 static const struct ht_types { 1442 pcireg_t cap; 1443 const char *name; 1444 void (*printfunc)(const pcireg_t *, int); 1445 } ht_captab[] = { 1446 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1447 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1448 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1449 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1450 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1451 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1452 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1453 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1454 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1455 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1456 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1457 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1458 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1459 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1460 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1461 {PCI_HT_CAP_PM, "Power Management", NULL }, 1462 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1463 }; 1464 1465 static void 1466 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1467 { 1468 pcireg_t val, foundcap; 1469 unsigned int off; 1470 1471 val = regs[o2i(capoff + PCI_HT_CMD)]; 1472 1473 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1474 1475 printf(" Command register: 0x%04x\n", val >> 16); 1476 foundcap = PCI_HT_CAP(val); 1477 for (off = 0; off < __arraycount(ht_captab); off++) { 1478 if (ht_captab[off].cap == foundcap) 1479 break; 1480 } 1481 printf(" Capability Type: 0x%02x ", foundcap); 1482 if (off >= __arraycount(ht_captab)) { 1483 printf("(unknown)\n"); 1484 return; 1485 } 1486 printf("(%s)\n", ht_captab[off].name); 1487 if (ht_captab[off].printfunc != NULL) 1488 ht_captab[off].printfunc(regs, capoff); 1489 } 1490 1491 static void 1492 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1493 { 1494 uint16_t caps; 1495 1496 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1497 1498 printf("\n PCI Vendor Specific Capabilities Register\n"); 1499 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1500 } 1501 1502 static void 1503 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1504 { 1505 pcireg_t val; 1506 1507 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1508 1509 printf("\n Debugport Capability Register\n"); 1510 printf(" Debug base Register: 0x%04x\n", 1511 val >> PCI_DEBUG_BASER_SHIFT); 1512 printf(" port offset: 0x%04x\n", 1513 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1514 printf(" BAR number: %u\n", 1515 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1516 } 1517 1518 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1519 /* XXX pci_conf_print_hotplug_cap */ 1520 1521 static void 1522 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1523 { 1524 pcireg_t reg; 1525 1526 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1527 1528 printf("\n Subsystem ID Capability Register\n"); 1529 printf(" Subsystem ID : 0x%08x\n", reg); 1530 } 1531 1532 /* XXX pci_conf_print_agp8_cap */ 1533 /* XXX pci_conf_print_secure_cap */ 1534 1535 static void 1536 pci_print_pcie_L0s_latency(uint32_t val) 1537 { 1538 1539 switch (val) { 1540 case 0x0: 1541 printf("Less than 64ns\n"); 1542 break; 1543 case 0x1: 1544 case 0x2: 1545 case 0x3: 1546 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1547 break; 1548 case 0x4: 1549 printf("512ns to less than 1us\n"); 1550 break; 1551 case 0x5: 1552 printf("1us to less than 2us\n"); 1553 break; 1554 case 0x6: 1555 printf("2us - 4us\n"); 1556 break; 1557 case 0x7: 1558 printf("More than 4us\n"); 1559 break; 1560 } 1561 } 1562 1563 static void 1564 pci_print_pcie_L1_latency(uint32_t val) 1565 { 1566 1567 switch (val) { 1568 case 0x0: 1569 printf("Less than 1us\n"); 1570 break; 1571 case 0x6: 1572 printf("32us - 64us\n"); 1573 break; 1574 case 0x7: 1575 printf("More than 64us\n"); 1576 break; 1577 default: 1578 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1579 break; 1580 } 1581 } 1582 1583 static void 1584 pci_print_pcie_compl_timeout(uint32_t val) 1585 { 1586 1587 switch (val) { 1588 case 0x0: 1589 printf("50us to 50ms\n"); 1590 break; 1591 case 0x5: 1592 printf("16ms to 55ms\n"); 1593 break; 1594 case 0x6: 1595 printf("65ms to 210ms\n"); 1596 break; 1597 case 0x9: 1598 printf("260ms to 900ms\n"); 1599 break; 1600 case 0xa: 1601 printf("1s to 3.5s\n"); 1602 break; 1603 default: 1604 printf("unknown %u value\n", val); 1605 break; 1606 } 1607 } 1608 1609 static const char * const pcie_linkspeeds[] = {"2.5", "5.0", "8.0"}; 1610 1611 /* 1612 * Print link speed. This function is used for the following register bits: 1613 * Maximum Link Speed in LCAP 1614 * Current Link Speed in LCSR 1615 * Target Link Speed in LCSR2 1616 * All of above bitfield's values start from 1. 1617 * For LCSR2, 0 is allowed for a device which supports 2.5GT/s only (and 1618 * this check also works for devices which compliant to versions of the base 1619 * specification prior to 3.0. 1620 */ 1621 static void 1622 pci_print_pcie_linkspeed(int regnum, pcireg_t val) 1623 { 1624 1625 if ((regnum == PCIE_LCSR2) && (val == 0)) 1626 printf("2.5GT/s\n"); 1627 else if ((val < 1) || (val > __arraycount(pcie_linkspeeds))) 1628 printf("unknown value (%u)\n", val); 1629 else 1630 printf("%sGT/s\n", pcie_linkspeeds[val - 1]); 1631 } 1632 1633 /* 1634 * Print link speed "vector". 1635 * This function is used for the following register bits: 1636 * Supported Link Speeds Vector in LCAP2 1637 * Lower SKP OS Generation Supported Speed Vector in LCAP2 1638 * Lower SKP OS Reception Supported Speed Vector in LCAP2 1639 * Enable Lower SKP OS Generation Vector in LCTL3 1640 * All of above bitfield's values start from 0. 1641 */ 1642 static void 1643 pci_print_pcie_linkspeedvector(pcireg_t val) 1644 { 1645 unsigned int i; 1646 1647 /* Start from 0 */ 1648 for (i = 0; i < 16; i++) 1649 if (((val >> i) & 0x01) != 0) { 1650 if (i >= __arraycount(pcie_linkspeeds)) 1651 printf(" unknown vector (0x%x)", 1 << i); 1652 else 1653 printf(" %sGT/s", pcie_linkspeeds[i]); 1654 } 1655 } 1656 1657 static void 1658 pci_print_pcie_link_deemphasis(pcireg_t val) 1659 { 1660 switch (val) { 1661 case 0: 1662 printf("-6dB"); 1663 break; 1664 case 1: 1665 printf("-3.5dB"); 1666 break; 1667 default: 1668 printf("(reserved value)"); 1669 } 1670 } 1671 1672 static void 1673 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1674 { 1675 pcireg_t reg; /* for each register */ 1676 pcireg_t val; /* for each bitfield */ 1677 bool check_link = true; 1678 bool check_slot = false; 1679 bool check_rootport = false; 1680 bool check_upstreamport = false; 1681 unsigned int pciever; 1682 unsigned int i; 1683 1684 printf("\n PCI Express Capabilities Register\n"); 1685 /* Capability Register */ 1686 reg = regs[o2i(capoff)]; 1687 printf(" Capability register: 0x%04x\n", reg >> 16); 1688 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1689 printf(" Capability version: %u\n", pciever); 1690 printf(" Device type: "); 1691 switch ((reg & 0x00f00000) >> 20) { 1692 case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */ 1693 printf("PCI Express Endpoint device\n"); 1694 check_upstreamport = true; 1695 break; 1696 case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */ 1697 printf("Legacy PCI Express Endpoint device\n"); 1698 check_upstreamport = true; 1699 break; 1700 case PCIE_XCAP_TYPE_ROOT: /* 0x4 */ 1701 printf("Root Port of PCI Express Root Complex\n"); 1702 check_slot = true; 1703 check_rootport = true; 1704 break; 1705 case PCIE_XCAP_TYPE_UP: /* 0x5 */ 1706 printf("Upstream Port of PCI Express Switch\n"); 1707 check_upstreamport = true; 1708 break; 1709 case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ 1710 printf("Downstream Port of PCI Express Switch\n"); 1711 check_slot = true; 1712 check_rootport = true; 1713 break; 1714 case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ 1715 printf("PCI Express to PCI/PCI-X Bridge\n"); 1716 check_upstreamport = true; 1717 break; 1718 case PCIE_XCAP_TYPE_PCI2PCIE: /* 0x8 */ 1719 printf("PCI/PCI-X to PCI Express Bridge\n"); 1720 /* Upstream port is not PCIe */ 1721 check_slot = true; 1722 break; 1723 case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */ 1724 printf("Root Complex Integrated Endpoint\n"); 1725 check_link = false; 1726 break; 1727 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */ 1728 printf("Root Complex Event Collector\n"); 1729 check_link = false; 1730 check_rootport = true; 1731 break; 1732 default: 1733 printf("unknown\n"); 1734 break; 1735 } 1736 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1737 printf(" Interrupt Message Number: 0x%02x\n", 1738 (unsigned int)__SHIFTOUT(reg, PCIE_XCAP_IRQ)); 1739 1740 /* Device Capability Register */ 1741 reg = regs[o2i(capoff + PCIE_DCAP)]; 1742 printf(" Device Capabilities Register: 0x%08x\n", reg); 1743 printf(" Max Payload Size Supported: %u bytes max\n", 1744 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1745 printf(" Phantom Functions Supported: "); 1746 switch (__SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) { 1747 case 0x0: 1748 printf("not available\n"); 1749 break; 1750 case 0x1: 1751 printf("MSB\n"); 1752 break; 1753 case 0x2: 1754 printf("two MSB\n"); 1755 break; 1756 case 0x3: 1757 printf("All three bits\n"); 1758 break; 1759 } 1760 printf(" Extended Tag Field Supported: %dbit\n", 1761 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1762 printf(" Endpoint L0 Acceptable Latency: "); 1763 pci_print_pcie_L0s_latency(__SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY)); 1764 printf(" Endpoint L1 Acceptable Latency: "); 1765 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY)); 1766 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1767 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1768 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1769 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1770 if (check_upstreamport) { 1771 printf(" Captured Slot Power Limit: "); 1772 pci_conf_print_pcie_power( 1773 __SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL), 1774 __SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE)); 1775 } 1776 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1777 1778 /* Device Control Register */ 1779 reg = regs[o2i(capoff + PCIE_DCSR)]; 1780 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1781 onoff("Correctable Error Reporting Enable", reg, 1782 PCIE_DCSR_ENA_COR_ERR); 1783 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1784 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1785 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1786 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1787 printf(" Max Payload Size: %d byte\n", 1788 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD)); 1789 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1790 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1791 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1792 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1793 printf(" Max Read Request Size: %d byte\n", 1794 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ)); 1795 1796 /* Device Status Register */ 1797 reg = regs[o2i(capoff + PCIE_DCSR)]; 1798 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1799 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1800 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1801 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1802 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1803 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1804 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1805 onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD); 1806 1807 if (check_link) { 1808 /* Link Capability Register */ 1809 reg = regs[o2i(capoff + PCIE_LCAP)]; 1810 printf(" Link Capabilities Register: 0x%08x\n", reg); 1811 printf(" Maximum Link Speed: "); 1812 pci_print_pcie_linkspeed(PCIE_LCAP, reg & PCIE_LCAP_MAX_SPEED); 1813 printf(" Maximum Link Width: x%u lanes\n", 1814 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH)); 1815 printf(" Active State PM Support: "); 1816 switch (__SHIFTOUT(reg, PCIE_LCAP_ASPM)) { 1817 case 0x0: 1818 printf("No ASPM support\n"); 1819 break; 1820 case 0x1: 1821 printf("L0s supported\n"); 1822 break; 1823 case 0x2: 1824 printf("L1 supported\n"); 1825 break; 1826 case 0x3: 1827 printf("L0s and L1 supported\n"); 1828 break; 1829 } 1830 printf(" L0 Exit Latency: "); 1831 pci_print_pcie_L0s_latency(__SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT)); 1832 printf(" L1 Exit Latency: "); 1833 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_LCAP_L1_EXIT)); 1834 printf(" Port Number: %u\n", 1835 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_PORT)); 1836 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1837 onoff("Surprise Down Error Report", reg, 1838 PCIE_LCAP_SURPRISE_DOWN); 1839 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1840 onoff("Link BW Notification Capable", reg, 1841 PCIE_LCAP_LINK_BW_NOTIFY); 1842 onoff("ASPM Optionally Compliance", reg, 1843 PCIE_LCAP_ASPM_COMPLIANCE); 1844 1845 /* Link Control Register */ 1846 reg = regs[o2i(capoff + PCIE_LCSR)]; 1847 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1848 printf(" Active State PM Control: "); 1849 switch (reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S)) { 1850 case 0: 1851 printf("disabled\n"); 1852 break; 1853 case 1: 1854 printf("L0s Entry Enabled\n"); 1855 break; 1856 case 2: 1857 printf("L1 Entry Enabled\n"); 1858 break; 1859 case 3: 1860 printf("L0s and L1 Entry Enabled\n"); 1861 break; 1862 } 1863 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1864 "128bytes", "64bytes"); 1865 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1866 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1867 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1868 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1869 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1870 onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD); 1871 onoff("Link Bandwidth Management Interrupt Enable", reg, 1872 PCIE_LCSR_LBMIE); 1873 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1874 PCIE_LCSR_LABIE); 1875 printf(" DRS Signaling Control: "); 1876 switch (__SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) { 1877 case 0: 1878 printf("not reported\n"); 1879 break; 1880 case 1: 1881 printf("Interrupt Enabled\n"); 1882 break; 1883 case 2: 1884 printf("DRS to FRS Signaling Enabled\n"); 1885 break; 1886 default: 1887 printf("reserved\n"); 1888 break; 1889 } 1890 1891 /* Link Status Register */ 1892 reg = regs[o2i(capoff + PCIE_LCSR)]; 1893 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1894 printf(" Negotiated Link Speed: "); 1895 pci_print_pcie_linkspeed(PCIE_LCSR, 1896 __SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 1897 printf(" Negotiated Link Width: x%u lanes\n", 1898 (unsigned int)__SHIFTOUT(reg, PCIE_LCSR_NLW)); 1899 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1900 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1901 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1902 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1903 onoff("Link Bandwidth Management Status", reg, 1904 PCIE_LCSR_LINK_BW_MGMT); 1905 onoff("Link Autonomous Bandwidth Status", reg, 1906 PCIE_LCSR_LINK_AUTO_BW); 1907 } 1908 1909 if (check_slot == true) { 1910 pcireg_t slcap; 1911 1912 /* Slot Capability Register */ 1913 slcap = reg = regs[o2i(capoff + PCIE_SLCAP)]; 1914 printf(" Slot Capability Register: 0x%08x\n", reg); 1915 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1916 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1917 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 1918 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 1919 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 1920 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 1921 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 1922 printf(" Slot Power Limit Value: "); 1923 pci_conf_print_pcie_power(__SHIFTOUT(reg, PCIE_SLCAP_SPLV), 1924 __SHIFTOUT(reg, PCIE_SLCAP_SPLS)); 1925 onoff("Electromechanical Interlock Present", reg, 1926 PCIE_SLCAP_EIP); 1927 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 1928 printf(" Physical Slot Number: %d\n", 1929 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1930 1931 /* Slot Control Register */ 1932 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1933 printf(" Slot Control Register: 0x%04x\n", reg & 0xffff); 1934 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 1935 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 1936 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 1937 onoff("Presence Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 1938 onoff("Command Completed Interrupt Enabled", reg, 1939 PCIE_SLCSR_CCE); 1940 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 1941 /* 1942 * For Attention Indicator Control and Power Indicator Control, 1943 * it's allowed to be a read only value 0 if corresponding 1944 * capability register bit is 0. 1945 */ 1946 if (slcap & PCIE_SLCAP_AIP) { 1947 printf(" Attention Indicator Control: "); 1948 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1949 case 0x0: 1950 printf("reserved\n"); 1951 break; 1952 case PCIE_SLCSR_IND_ON: 1953 printf("on\n"); 1954 break; 1955 case PCIE_SLCSR_IND_BLINK: 1956 printf("blink\n"); 1957 break; 1958 case PCIE_SLCSR_IND_OFF: 1959 printf("off\n"); 1960 break; 1961 } 1962 } 1963 if (slcap & PCIE_SLCAP_PIP) { 1964 printf(" Power Indicator Control: "); 1965 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1966 case 0x0: 1967 printf("reserved\n"); 1968 break; 1969 case PCIE_SLCSR_IND_ON: 1970 printf("on\n"); 1971 break; 1972 case PCIE_SLCSR_IND_BLINK: 1973 printf("blink\n"); 1974 break; 1975 case PCIE_SLCSR_IND_OFF: 1976 printf("off\n"); 1977 break; 1978 } 1979 } 1980 printf(" Power Controller Control: Power %s\n", 1981 reg & PCIE_SLCSR_PCC ? "off" : "on"); 1982 onoff("Electromechanical Interlock Control", 1983 reg, PCIE_SLCSR_EIC); 1984 onoff("Data Link Layer State Changed Enable", reg, 1985 PCIE_SLCSR_DLLSCE); 1986 onoff("Auto Slot Power Limit Disable", reg, 1987 PCIE_SLCSR_AUTOSPLDIS); 1988 1989 /* Slot Status Register */ 1990 printf(" Slot Status Register: 0x%04x\n", reg >> 16); 1991 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 1992 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 1993 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 1994 onoff("Presence Detect Changed", reg, PCIE_SLCSR_PDC); 1995 onoff("Command Completed", reg, PCIE_SLCSR_CC); 1996 onoff("MRL Open", reg, PCIE_SLCSR_MS); 1997 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 1998 onoff("Electromechanical Interlock engaged", reg, 1999 PCIE_SLCSR_EIS); 2000 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 2001 } 2002 2003 if (check_rootport == true) { 2004 /* Root Control Register */ 2005 reg = regs[o2i(capoff + PCIE_RCR)]; 2006 printf(" Root Control Register: 0x%04x\n", reg & 0xffff); 2007 onoff("SERR on Correctable Error Enable", reg, 2008 PCIE_RCR_SERR_CER); 2009 onoff("SERR on Non-Fatal Error Enable", reg, 2010 PCIE_RCR_SERR_NFER); 2011 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 2012 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 2013 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 2014 2015 /* Root Capability Register */ 2016 printf(" Root Capability Register: 0x%04x\n", 2017 reg >> 16); 2018 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 2019 2020 /* Root Status Register */ 2021 reg = regs[o2i(capoff + PCIE_RSR)]; 2022 printf(" Root Status Register: 0x%08x\n", reg); 2023 printf(" PME Requester ID: 0x%04x\n", 2024 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 2025 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 2026 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 2027 } 2028 2029 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2030 if (pciever < 2) 2031 return; 2032 2033 /* Device Capabilities 2 */ 2034 reg = regs[o2i(capoff + PCIE_DCAP2)]; 2035 printf(" Device Capabilities 2: 0x%08x\n", reg); 2036 printf(" Completion Timeout Ranges Supported: "); 2037 val = reg & PCIE_DCAP2_COMPT_RANGE; 2038 switch (val) { 2039 case 0: 2040 printf("not supported\n"); 2041 break; 2042 default: 2043 for (i = 0; i <= 3; i++) { 2044 if (((val >> i) & 0x01) != 0) 2045 printf("%c", 'A' + i); 2046 } 2047 printf("\n"); 2048 } 2049 onoff("Completion Timeout Disable Supported", reg, 2050 PCIE_DCAP2_COMPT_DIS); 2051 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 2052 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 2053 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 2054 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 2055 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 2056 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 2057 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 2058 printf(" TPH Completer Supported: "); 2059 switch (__SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) { 2060 case 0: 2061 printf("Not supported\n"); 2062 break; 2063 case 1: 2064 printf("TPH\n"); 2065 break; 2066 case 3: 2067 printf("TPH and Extended TPH\n"); 2068 break; 2069 default: 2070 printf("(reserved value)\n"); 2071 break; 2072 2073 } 2074 printf(" LN System CLS: "); 2075 switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 2076 case 0x0: 2077 printf("Not supported or not in effect\n"); 2078 break; 2079 case 0x1: 2080 printf("64byte cachelines in effect\n"); 2081 break; 2082 case 0x2: 2083 printf("128byte cachelines in effect\n"); 2084 break; 2085 case 0x3: 2086 printf("Reserved\n"); 2087 break; 2088 } 2089 printf(" OBFF Supported: "); 2090 switch (__SHIFTOUT(reg, PCIE_DCAP2_OBFF)) { 2091 case 0x0: 2092 printf("Not supported\n"); 2093 break; 2094 case 0x1: 2095 printf("Message only\n"); 2096 break; 2097 case 0x2: 2098 printf("WAKE# only\n"); 2099 break; 2100 case 0x3: 2101 printf("Both\n"); 2102 break; 2103 } 2104 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 2105 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 2106 val = __SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP); 2107 printf(" Max End-End TLP Prefixes: %u\n", (val == 0) ? 4 : val); 2108 printf(" Emergency Power Reduction Supported: "); 2109 switch (__SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) { 2110 case 0x0: 2111 printf("Not supported\n"); 2112 break; 2113 case 0x1: 2114 printf("Device Specific mechanism\n"); 2115 break; 2116 case 0x2: 2117 printf("Form Factor spec or Device Specific mechanism\n"); 2118 break; 2119 case 0x3: 2120 printf("Reserved\n"); 2121 break; 2122 } 2123 onoff("Emergency Power Reduction Initialization Required", reg, 2124 PCIE_DCAP2_EMGPWRRED_INI); 2125 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 2126 2127 /* Device Control 2 */ 2128 reg = regs[o2i(capoff + PCIE_DCSR2)]; 2129 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 2130 printf(" Completion Timeout Value: "); 2131 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 2132 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 2133 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 2134 onoff("AtomicOp Requester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 2135 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 2136 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 2137 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 2138 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 2139 onoff("Emergency Power Reduction Request", reg, 2140 PCIE_DCSR2_EMGPWRRED_REQ); 2141 printf(" OBFF: "); 2142 switch (__SHIFTOUT(reg, PCIE_DCSR2_OBFF_EN)) { 2143 case 0x0: 2144 printf("Disabled\n"); 2145 break; 2146 case 0x1: 2147 printf("Enabled with Message Signaling Variation A\n"); 2148 break; 2149 case 0x2: 2150 printf("Enabled with Message Signaling Variation B\n"); 2151 break; 2152 case 0x3: 2153 printf("Enabled using WAKE# signaling\n"); 2154 break; 2155 } 2156 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 2157 2158 if (check_link) { 2159 bool drs_supported = false; 2160 2161 /* Link Capability 2 */ 2162 reg = regs[o2i(capoff + PCIE_LCAP2)]; 2163 /* If the vector is 0, LCAP2 is not implemented */ 2164 if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) { 2165 printf(" Link Capabilities 2: 0x%08x\n", reg); 2166 printf(" Supported Link Speeds Vector:"); 2167 pci_print_pcie_linkspeedvector( 2168 __SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 2169 printf("\n"); 2170 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 2171 printf(" " 2172 "Lower SKP OS Generation Supported Speed Vector:"); 2173 pci_print_pcie_linkspeedvector( 2174 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 2175 printf("\n"); 2176 printf(" " 2177 "Lower SKP OS Reception Supported Speed Vector:"); 2178 pci_print_pcie_linkspeedvector( 2179 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 2180 printf("\n"); 2181 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 2182 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 2183 } 2184 2185 /* Link Control 2 */ 2186 reg = regs[o2i(capoff + PCIE_LCSR2)]; 2187 /* If the vector is 0, LCAP2 is not implemented */ 2188 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 2189 printf(" Target Link Speed: "); 2190 pci_print_pcie_linkspeed(PCIE_LCSR2, 2191 __SHIFTOUT(reg, PCIE_LCSR2_TGT_LSPEED)); 2192 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 2193 onoff("HW Autonomous Speed Disabled", reg, 2194 PCIE_LCSR2_HW_AS_DIS); 2195 printf(" Selectable De-emphasis: "); 2196 pci_print_pcie_link_deemphasis( 2197 __SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP)); 2198 printf("\n"); 2199 printf(" Transmit Margin: %u\n", 2200 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 2201 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 2202 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 2203 printf(" Compliance Present/De-emphasis: "); 2204 pci_print_pcie_link_deemphasis( 2205 __SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP)); 2206 printf("\n"); 2207 2208 /* Link Status 2 */ 2209 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 2210 printf(" Current De-emphasis Level: "); 2211 pci_print_pcie_link_deemphasis( 2212 __SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL)); 2213 printf("\n"); 2214 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 2215 onoff("Equalization Phase 1 Successful", reg, 2216 PCIE_LCSR2_EQP1_SUC); 2217 onoff("Equalization Phase 2 Successful", reg, 2218 PCIE_LCSR2_EQP2_SUC); 2219 onoff("Equalization Phase 3 Successful", reg, 2220 PCIE_LCSR2_EQP3_SUC); 2221 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 2222 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 2223 if (drs_supported) { 2224 printf(" Downstream Component Presence: "); 2225 switch (__SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 2226 case PCIE_DSCOMPN_DOWN_NOTDETERM: 2227 printf("Link Down - Presence Not" 2228 " Determined\n"); 2229 break; 2230 case PCIE_DSCOMPN_DOWN_NOTPRES: 2231 printf("Link Down - Component Not Present\n"); 2232 break; 2233 case PCIE_DSCOMPN_DOWN_PRES: 2234 printf("Link Down - Component Present\n"); 2235 break; 2236 case PCIE_DSCOMPN_UP_PRES: 2237 printf("Link Up - Component Present\n"); 2238 break; 2239 case PCIE_DSCOMPN_UP_PRES_DRS: 2240 printf("Link Up - Component Present and DRS" 2241 " received\n"); 2242 break; 2243 default: 2244 printf("reserved\n"); 2245 break; 2246 } 2247 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 2248 } 2249 } 2250 2251 /* Slot Capability 2 */ 2252 /* Slot Control 2 */ 2253 /* Slot Status 2 */ 2254 } 2255 2256 static void 2257 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 2258 { 2259 pcireg_t reg; 2260 2261 printf("\n MSI-X Capability Register\n"); 2262 2263 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2264 printf(" Message Control register: 0x%04x\n", 2265 (reg >> 16) & 0xff); 2266 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 2267 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 2268 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 2269 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 2270 printf(" Table offset register: 0x%08x\n", reg); 2271 printf(" Table offset: 0x%08x\n", 2272 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 2273 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 2274 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 2275 printf(" Pending bit array register: 0x%08x\n", reg); 2276 printf(" Pending bit array offset: 0x%08x\n", 2277 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2278 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2279 } 2280 2281 static void 2282 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2283 { 2284 pcireg_t reg; 2285 2286 printf("\n Serial ATA Capability Register\n"); 2287 2288 reg = regs[o2i(capoff + PCI_SATA_REV)]; 2289 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2290 printf(" Revision: %u.%u\n", 2291 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2292 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2293 2294 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2295 2296 printf(" BAR Register: 0x%08x\n", reg); 2297 printf(" Register location: "); 2298 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2299 printf("in config space\n"); 2300 else { 2301 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2302 printf(" BAR offset: 0x%08x\n", 2303 (pcireg_t)__SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2304 } 2305 } 2306 2307 static void 2308 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2309 { 2310 pcireg_t reg; 2311 2312 printf("\n Advanced Features Capability Register\n"); 2313 2314 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2315 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2316 printf(" AF Structure Length: 0x%02x\n", 2317 (pcireg_t)__SHIFTOUT(reg, PCI_AF_LENGTH)); 2318 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2319 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2320 reg = regs[o2i(capoff + PCI_AFCSR)]; 2321 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2322 /* 2323 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2324 * and it's always 0 on read 2325 */ 2326 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2327 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2328 } 2329 2330 /* XXX pci_conf_print_ea_cap */ 2331 /* XXX pci_conf_print_fpb_cap */ 2332 2333 static struct { 2334 pcireg_t cap; 2335 const char *name; 2336 void (*printfunc)(const pcireg_t *, int); 2337 } pci_captab[] = { 2338 { PCI_CAP_RESERVED0, "reserved", NULL }, 2339 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2340 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2341 { PCI_CAP_VPD, "VPD", NULL }, 2342 { PCI_CAP_SLOTID, "SlotID", NULL }, 2343 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2344 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2345 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2346 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2347 { PCI_CAP_VENDSPEC, "Vendor-specific", 2348 pci_conf_print_vendspec_cap }, 2349 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2350 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2351 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2352 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2353 pci_conf_print_subsystem_cap }, 2354 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2355 { PCI_CAP_SECURE, "Secure Device", NULL }, 2356 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2357 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2358 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2359 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2360 { PCI_CAP_EA, "Enhanced Allocation", NULL }, 2361 { PCI_CAP_FPB, "Flattening Portal Bridge", NULL } 2362 }; 2363 2364 static int 2365 pci_conf_find_cap(const pcireg_t *regs, int capoff, unsigned int capid, 2366 int *offsetp) 2367 { 2368 pcireg_t rval; 2369 int off; 2370 2371 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2372 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2373 rval = regs[o2i(off)]; 2374 if (capid == PCI_CAPLIST_CAP(rval)) { 2375 if (offsetp != NULL) 2376 *offsetp = off; 2377 return 1; 2378 } 2379 } 2380 return 0; 2381 } 2382 2383 static void 2384 pci_conf_print_caplist( 2385 #ifdef _KERNEL 2386 pci_chipset_tag_t pc, pcitag_t tag, 2387 #endif 2388 const pcireg_t *regs, int capoff) 2389 { 2390 int off; 2391 pcireg_t foundcap; 2392 pcireg_t rval; 2393 bool foundtable[__arraycount(pci_captab)]; 2394 unsigned int i; 2395 2396 /* Clear table */ 2397 for (i = 0; i < __arraycount(pci_captab); i++) 2398 foundtable[i] = false; 2399 2400 /* Print capability register's offset and the type first */ 2401 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2402 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2403 rval = regs[o2i(off)]; 2404 printf(" Capability register at 0x%02x\n", off); 2405 2406 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2407 foundcap = PCI_CAPLIST_CAP(rval); 2408 if (foundcap < __arraycount(pci_captab)) { 2409 printf("%s)\n", pci_captab[foundcap].name); 2410 /* Mark as found */ 2411 foundtable[foundcap] = true; 2412 } else 2413 printf("unknown)\n"); 2414 } 2415 2416 /* 2417 * And then, print the detail of each capability registers 2418 * in capability value's order. 2419 */ 2420 for (i = 0; i < __arraycount(pci_captab); i++) { 2421 if (foundtable[i] == false) 2422 continue; 2423 2424 /* 2425 * The type was found. Search capability list again and 2426 * print all capabilities that the capabiliy type is 2427 * the same. This is required because some capabilities 2428 * appear multiple times (e.g. HyperTransport capability). 2429 */ 2430 #if 0 2431 if (pci_conf_find_cap(regs, capoff, i, &off)) { 2432 rval = regs[o2i(off)]; 2433 if (pci_captab[i].printfunc != NULL) 2434 pci_captab[i].printfunc(regs, off); 2435 } 2436 #else 2437 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2438 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2439 rval = regs[o2i(off)]; 2440 if ((PCI_CAPLIST_CAP(rval) == i) 2441 && (pci_captab[i].printfunc != NULL)) 2442 pci_captab[i].printfunc(regs, off); 2443 } 2444 #endif 2445 } 2446 } 2447 2448 /* Extended Capability */ 2449 2450 static void 2451 pci_conf_print_aer_cap_uc(pcireg_t reg) 2452 { 2453 2454 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2455 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2456 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2457 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2458 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2459 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2460 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2461 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2462 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2463 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2464 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2465 onoff("Unsupported Request Error", reg, 2466 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2467 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2468 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2469 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2470 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2471 onoff("TLP Prefix Blocked Error", reg, 2472 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2473 onoff("Poisoned TLP Egress Blocked", reg, 2474 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2475 } 2476 2477 static void 2478 pci_conf_print_aer_cap_cor(pcireg_t reg) 2479 { 2480 2481 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2482 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2483 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2484 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2485 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2486 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2487 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2488 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2489 } 2490 2491 static void 2492 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2493 { 2494 2495 printf(" First Error Pointer: 0x%04x\n", 2496 (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2497 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2498 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2499 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2500 onoff("ECRC Check Enable", reg, PCI_AER_ECRC_CHECK_ENABLE); 2501 onoff("Multiple Header Recording Capable", reg, 2502 PCI_AER_MULT_HDR_CAPABLE); 2503 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2504 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2505 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2506 2507 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2508 if (!tlp_prefix_log) 2509 return; 2510 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2511 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2512 } 2513 2514 static void 2515 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2516 { 2517 2518 onoff("Correctable Error Reporting Enable", reg, 2519 PCI_AER_ROOTERR_COR_ENABLE); 2520 onoff("Non-Fatal Error Reporting Enable", reg, 2521 PCI_AER_ROOTERR_NF_ENABLE); 2522 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2523 } 2524 2525 static void 2526 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2527 { 2528 2529 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2530 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2531 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2532 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2533 PCI_AER_ROOTERR_MULTI_UC_ERR); 2534 onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL); 2535 onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR); 2536 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2537 printf(" Advanced Error Interrupt Message Number: 0x%02x\n", 2538 (unsigned int)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2539 } 2540 2541 static void 2542 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2543 { 2544 2545 printf(" Correctable Source ID: 0x%04x\n", 2546 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2547 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2548 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2549 } 2550 2551 static void 2552 pci_conf_print_aer_cap(const pcireg_t *regs, int capoff, int extcapoff) 2553 { 2554 pcireg_t reg; 2555 int pcie_capoff; 2556 int pcie_devtype = -1; 2557 bool tlp_prefix_log = false; 2558 2559 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2560 reg = regs[o2i(pcie_capoff)]; 2561 pcie_devtype = PCIE_XCAP_TYPE(reg); 2562 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2563 if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2564 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2565 /* End-End TLP Prefix Supported */ 2566 if (reg & PCIE_DCAP2_EETLP_PREF) { 2567 tlp_prefix_log = true; 2568 } 2569 } 2570 } 2571 2572 printf("\n Advanced Error Reporting Register\n"); 2573 2574 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2575 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2576 pci_conf_print_aer_cap_uc(reg); 2577 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2578 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2579 pci_conf_print_aer_cap_uc(reg); 2580 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2581 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2582 pci_conf_print_aer_cap_uc(reg); 2583 2584 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2585 printf(" Correctable Error Status register: 0x%08x\n", reg); 2586 pci_conf_print_aer_cap_cor(reg); 2587 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2588 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2589 pci_conf_print_aer_cap_cor(reg); 2590 2591 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2592 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2593 reg); 2594 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2595 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2596 printf(" Header Log register:\n"); 2597 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2598 extcapoff + PCI_AER_ROOTERR_CMD); 2599 2600 switch (pcie_devtype) { 2601 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2602 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2603 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2604 printf(" Root Error Command register: 0x%08x\n", reg); 2605 pci_conf_print_aer_cap_rooterr_cmd(reg); 2606 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2607 printf(" Root Error Status register: 0x%08x\n", reg); 2608 pci_conf_print_aer_cap_rooterr_status(reg); 2609 2610 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2611 printf(" Error Source Identification: 0x%04x\n", reg); 2612 pci_conf_print_aer_cap_errsrc_id(reg); 2613 break; 2614 } 2615 2616 if (tlp_prefix_log) { 2617 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2618 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2619 } 2620 } 2621 2622 static void 2623 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2624 pcireg_t parbsel, int parbsize) 2625 { 2626 pcireg_t reg; 2627 int num = 16 << parbsel; 2628 int num_per_reg = sizeof(pcireg_t) / parbsize; 2629 int i, j; 2630 2631 /* First, dump the table */ 2632 for (i = 0; i < num; i += num_per_reg) { 2633 reg = regs[o2i(off + i / num_per_reg)]; 2634 printf(" %s Arbitration Table: 0x%08x\n", name, reg); 2635 } 2636 /* And then, decode each entry */ 2637 for (i = 0; i < num; i += num_per_reg) { 2638 reg = regs[o2i(off + i / num_per_reg)]; 2639 for (j = 0; j < num_per_reg; j++) 2640 printf(" Phase[%d]: %d\n", j, reg); 2641 } 2642 } 2643 2644 static void 2645 pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2646 { 2647 pcireg_t reg, n; 2648 int parbtab, parbsize; 2649 pcireg_t parbsel; 2650 int varbtab, varbsize; 2651 pcireg_t varbsel; 2652 int i, count; 2653 2654 printf("\n Virtual Channel Register\n"); 2655 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2656 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2657 count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2658 printf(" Extended VC Count: %d\n", count); 2659 n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2660 printf(" Low Priority Extended VC Count: %u\n", n); 2661 n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2662 printf(" Reference Clock: %s\n", 2663 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 2664 parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2665 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2666 2667 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2668 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2669 onoff("Hardware fixed arbitration scheme", 2670 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2671 onoff("WRR arbitration with 32 phases", 2672 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2673 onoff("WRR arbitration with 64 phases", 2674 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2675 onoff("WRR arbitration with 128 phases", 2676 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2677 varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2678 printf(" VC Arbitration Table Offset: 0x%x\n", varbtab); 2679 2680 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2681 printf(" Port VC Control register: 0x%04x\n", reg); 2682 varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2683 printf(" VC Arbitration Select: 0x%x\n", varbsel); 2684 2685 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2686 printf(" Port VC Status register: 0x%04x\n", reg); 2687 onoff("VC Arbitration Table Status", 2688 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 2689 2690 for (i = 0; i < count + 1; i++) { 2691 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 2692 printf(" VC number %d\n", i); 2693 printf(" VC Resource Capability Register: 0x%08x\n", reg); 2694 onoff(" Non-configurable Hardware fixed arbitration scheme", 2695 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 2696 onoff(" WRR arbitration with 32 phases", 2697 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 2698 onoff(" WRR arbitration with 64 phases", 2699 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 2700 onoff(" WRR arbitration with 128 phases", 2701 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 2702 onoff(" Time-based WRR arbitration with 128 phases", 2703 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 2704 onoff(" WRR arbitration with 256 phases", 2705 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 2706 onoff(" Advanced Packet Switching", 2707 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 2708 onoff(" Reject Snoop Transaction", 2709 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 2710 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 2711 printf(" Maximum Time Slots: %d\n", n); 2712 parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S; 2713 printf(" Port Arbitration Table offset: 0x%02x\n", 2714 parbtab); 2715 2716 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 2717 printf(" VC Resource Control Register: 0x%08x\n", reg); 2718 printf(" TC/VC Map: 0x%02x\n", 2719 (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 2720 /* 2721 * The load Port Arbitration Table bit is used to update 2722 * the Port Arbitration logic and it's always 0 on read, so 2723 * we don't print it. 2724 */ 2725 parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 2726 printf(" Port Arbitration Select: 0x%x\n", parbsel); 2727 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 2728 printf(" VC ID: %d\n", n); 2729 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 2730 2731 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 2732 printf(" VC Resource Status Register: 0x%08x\n", reg); 2733 onoff(" Port Arbitration Table Status", 2734 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 2735 onoff(" VC Negotiation Pending", 2736 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 2737 2738 if ((parbtab != 0) && (parbsel != 0)) 2739 pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab, 2740 "Port", parbsel, parbsize); 2741 } 2742 2743 varbsize = 8; 2744 if ((varbtab != 0) && (varbsel != 0)) 2745 pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab, 2746 " VC", varbsel, varbsize); 2747 } 2748 2749 /* 2750 * Print Power limit. This encoding is the same among the following registers: 2751 * - The Captured Slot Power Limit in the PCIe Device Capability Register. 2752 * - The Slot Power Limit in the PCIe Slot Capability Register. 2753 * - The Base Power in the Data register of Power Budgeting capability. 2754 */ 2755 static void 2756 pci_conf_print_pcie_power(uint8_t base, unsigned int scale) 2757 { 2758 unsigned int sdiv = 1; 2759 2760 if ((scale == 0) && (base > 0xef)) { 2761 const char *s; 2762 2763 switch (base) { 2764 case 0xf0: 2765 s = "239W < x <= 250W"; 2766 break; 2767 case 0xf1: 2768 s = "250W < x <= 275W"; 2769 break; 2770 case 0xf2: 2771 s = "275W < x <= 300W"; 2772 break; 2773 default: 2774 s = "reserved for above 300W"; 2775 break; 2776 } 2777 printf("%s\n", s); 2778 return; 2779 } 2780 2781 for (unsigned int i = scale; i > 0; i--) 2782 sdiv *= 10; 2783 2784 printf("%u", base / sdiv); 2785 2786 if (scale != 0) { 2787 printf(".%u", base % sdiv); 2788 } 2789 printf ("W\n"); 2790 return; 2791 } 2792 2793 static const char * 2794 pci_conf_print_pwrbdgt_type(uint8_t reg) 2795 { 2796 2797 switch (reg) { 2798 case 0x00: 2799 return "PME Aux"; 2800 case 0x01: 2801 return "Auxilary"; 2802 case 0x02: 2803 return "Idle"; 2804 case 0x03: 2805 return "Sustained"; 2806 case 0x04: 2807 return "Sustained (Emergency Power Reduction)"; 2808 case 0x05: 2809 return "Maximum (Emergency Power Reduction)"; 2810 case 0x07: 2811 return "Maximum"; 2812 default: 2813 return "Unknown"; 2814 } 2815 } 2816 2817 static const char * 2818 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 2819 { 2820 2821 switch (reg) { 2822 case 0x00: 2823 return "Power(12V)"; 2824 case 0x01: 2825 return "Power(3.3V)"; 2826 case 0x02: 2827 return "Power(1.5V or 1.8V)"; 2828 case 0x07: 2829 return "Thermal"; 2830 default: 2831 return "Unknown"; 2832 } 2833 } 2834 2835 static void 2836 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff) 2837 { 2838 pcireg_t reg; 2839 2840 printf("\n Power Budgeting\n"); 2841 2842 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 2843 printf(" Data Select register: 0x%08x\n", reg); 2844 2845 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 2846 printf(" Data register: 0x%08x\n", reg); 2847 printf(" Base Power: "); 2848 pci_conf_print_pcie_power( 2849 __SHIFTOUT(reg, PCI_PWRBDGT_DATA_BASEPWR), 2850 __SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE)); 2851 printf(" PM Sub State: 0x%hhx\n", 2852 (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 2853 printf(" PM State: D%u\n", 2854 (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 2855 printf(" Type: %s\n", 2856 pci_conf_print_pwrbdgt_type( 2857 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 2858 printf(" Power Rail: %s\n", 2859 pci_conf_print_pwrbdgt_pwrrail( 2860 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 2861 2862 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 2863 printf(" Power Budget Capability register: 0x%08x\n", reg); 2864 onoff("System Allocated", 2865 reg, PCI_PWRBDGT_CAP_SYSALLOC); 2866 } 2867 2868 static const char * 2869 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 2870 { 2871 2872 switch (type) { 2873 case 0x00: 2874 return "Configuration Space Element"; 2875 case 0x01: 2876 return "System Egress Port or internal sink (memory)"; 2877 case 0x02: 2878 return "Internal Root Complex Link"; 2879 default: 2880 return "Unknown"; 2881 } 2882 } 2883 2884 static void 2885 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int capoff, int extcapoff) 2886 { 2887 pcireg_t reg; 2888 unsigned char nent, linktype; 2889 int i; 2890 2891 printf("\n Root Complex Link Declaration\n"); 2892 2893 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 2894 printf(" Element Self Description Register: 0x%08x\n", reg); 2895 printf(" Element Type: %s\n", 2896 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 2897 nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 2898 printf(" Number of Link Entries: %hhu\n", nent); 2899 printf(" Component ID: %hhu\n", 2900 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 2901 printf(" Port Number: %hhu\n", 2902 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 2903 for (i = 0; i < nent; i++) { 2904 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 2905 printf(" Link Entry %d:\n", i + 1); 2906 printf(" Link Description Register: 0x%08x\n", reg); 2907 onoff(" Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID); 2908 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 2909 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 2910 "Configuration Space", "Memory-Mapped Space"); 2911 onoff(" Associated RCRB Header", reg, 2912 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 2913 printf(" Target Component ID: %hhu\n", 2914 (unsigned char)__SHIFTOUT(reg, 2915 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 2916 printf(" Target Port Number: %hhu\n", 2917 (unsigned char)__SHIFTOUT(reg, 2918 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 2919 2920 if (linktype == 0) { 2921 /* Memory-Mapped Space */ 2922 reg = regs[o2i(extcapoff 2923 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 2924 printf(" Link Address Low Register: 0x%08x\n", 2925 reg); 2926 reg = regs[o2i(extcapoff 2927 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 2928 printf(" Link Address High Register: 0x%08x\n", 2929 reg); 2930 } else { 2931 unsigned int nb; 2932 pcireg_t lo, hi; 2933 2934 /* Configuration Space */ 2935 lo = regs[o2i(extcapoff 2936 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 2937 printf(" Configuration Space Low Register: " 2938 "0x%08x\n", lo); 2939 hi = regs[o2i(extcapoff 2940 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 2941 printf(" Configuration Space High Register: " 2942 "0x%08x\n", hi); 2943 nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 2944 printf(" N: %u\n", nb); 2945 printf(" Func: %hhu\n", 2946 (unsigned char)__SHIFTOUT(lo, 2947 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 2948 printf(" Dev: %hhu\n", 2949 (unsigned char)__SHIFTOUT(lo, 2950 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 2951 printf(" Bus: %hhu\n", 2952 (unsigned char)__SHIFTOUT(lo, 2953 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 2954 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 2955 printf(" Configuration Space Base Address: " 2956 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 2957 } 2958 } 2959 } 2960 2961 /* XXX pci_conf_print_rclink_ctl_cap */ 2962 2963 static void 2964 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2965 { 2966 pcireg_t reg; 2967 2968 printf("\n Root Complex Event Collector Association\n"); 2969 2970 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 2971 printf(" Association Bitmap for Root Complex Integrated Devices:" 2972 " 0x%08x\n", reg); 2973 } 2974 2975 /* XXX pci_conf_print_mfvc_cap */ 2976 /* XXX pci_conf_print_vc2_cap */ 2977 /* XXX pci_conf_print_rcrb_cap */ 2978 /* XXX pci_conf_print_vendor_cap */ 2979 /* XXX pci_conf_print_cac_cap */ 2980 2981 static void 2982 pci_conf_print_acs_cap(const pcireg_t *regs, int capoff, int extcapoff) 2983 { 2984 pcireg_t reg, cap, ctl; 2985 unsigned int size, i; 2986 2987 printf("\n Access Control Services\n"); 2988 2989 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 2990 cap = reg & 0xffff; 2991 ctl = reg >> 16; 2992 printf(" ACS Capability register: 0x%08x\n", cap); 2993 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 2994 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 2995 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 2996 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 2997 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 2998 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 2999 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 3000 size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 3001 if (size == 0) 3002 size = 256; 3003 printf(" Egress Control Vector Size: %u\n", size); 3004 printf(" ACS Control register: 0x%08x\n", ctl); 3005 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 3006 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 3007 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 3008 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 3009 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 3010 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 3011 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 3012 3013 /* 3014 * If the P2P Egress Control Capability bit is 0, ignore the Egress 3015 * Control vector. 3016 */ 3017 if ((cap & PCI_ACS_CAP_E) == 0) 3018 return; 3019 for (i = 0; i < size; i += 32) 3020 printf(" Egress Control Vector [%u..%u]: 0x%08x\n", i + 31, 3021 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 3022 } 3023 3024 static void 3025 pci_conf_print_ari_cap(const pcireg_t *regs, int capoff, int extcapoff) 3026 { 3027 pcireg_t reg, cap, ctl; 3028 3029 printf("\n Alternative Routing-ID Interpretation Register\n"); 3030 3031 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3032 cap = reg & 0xffff; 3033 ctl = reg >> 16; 3034 printf(" Capability register: 0x%08x\n", cap); 3035 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 3036 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 3037 printf(" Next Function Number: %u\n", 3038 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 3039 printf(" Control register: 0x%08x\n", ctl); 3040 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 3041 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 3042 printf(" Function Group: %u\n", 3043 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 3044 } 3045 3046 static void 3047 pci_conf_print_ats_cap(const pcireg_t *regs, int capoff, int extcapoff) 3048 { 3049 pcireg_t reg, cap, ctl; 3050 unsigned int num; 3051 3052 printf("\n Address Translation Services\n"); 3053 3054 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3055 cap = reg & 0xffff; 3056 ctl = reg >> 16; 3057 printf(" Capability register: 0x%04x\n", cap); 3058 num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 3059 if (num == 0) 3060 num = 32; 3061 printf(" Invalidate Queue Depth: %u\n", num); 3062 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 3063 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 3064 3065 printf(" Control register: 0x%04x\n", ctl); 3066 printf(" Smallest Translation Unit: %u\n", 3067 (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU)); 3068 onoff("Enable", reg, PCI_ATS_CTL_EN); 3069 } 3070 3071 static void 3072 pci_conf_print_sernum_cap(const pcireg_t *regs, int capoff, int extcapoff) 3073 { 3074 pcireg_t lo, hi; 3075 3076 printf("\n Device Serial Number Register\n"); 3077 3078 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 3079 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 3080 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 3081 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 3082 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 3083 } 3084 3085 static void 3086 pci_conf_print_sriov_cap(const pcireg_t *regs, int capoff, int extcapoff) 3087 { 3088 char buf[sizeof("99999 MB")]; 3089 pcireg_t reg; 3090 pcireg_t total_vfs; 3091 int i; 3092 bool first; 3093 3094 printf("\n Single Root IO Virtualization Register\n"); 3095 3096 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 3097 printf(" Capabilities register: 0x%08x\n", reg); 3098 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 3099 onoff("ARI Capable Hierarchy Preserved", reg, 3100 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 3101 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 3102 printf(" VF Migration Interrupt Message Number: 0x%03x\n", 3103 (pcireg_t)__SHIFTOUT(reg, 3104 PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 3105 } 3106 3107 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 3108 printf(" Control register: 0x%04x\n", reg); 3109 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 3110 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 3111 onoff("VF Migration Interrupt Enable", reg, 3112 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 3113 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 3114 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 3115 3116 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 3117 printf(" Status register: 0x%04x\n", reg); 3118 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 3119 3120 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 3121 printf(" InitialVFs register: 0x%04x\n", reg); 3122 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 3123 printf(" TotalVFs register: 0x%04x\n", reg); 3124 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 3125 printf(" NumVFs register: 0x%04x\n", reg); 3126 3127 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 3128 printf(" Function Dependency Link register: 0x%04x\n", reg); 3129 3130 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 3131 printf(" First VF Offset register: 0x%04x\n", reg); 3132 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 3133 printf(" VF Stride register: 0x%04x\n", reg); 3134 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16; 3135 printf(" Device ID: 0x%04x\n", reg); 3136 3137 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 3138 printf(" Supported Page Sizes register: 0x%08x\n", reg); 3139 printf(" Supported Page Size:"); 3140 for (i = 0, first = true; i < 32; i++) { 3141 if (reg & __BIT(i)) { 3142 #ifdef _KERNEL 3143 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 3144 #else 3145 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 3146 HN_AUTOSCALE, 0); 3147 #endif 3148 printf("%s %s", first ? "" : ",", buf); 3149 first = false; 3150 } 3151 } 3152 printf("\n"); 3153 3154 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 3155 printf(" System Page Sizes register: 0x%08x\n", reg); 3156 printf(" Page Size: "); 3157 if (reg != 0) { 3158 int bitpos = ffs(reg) -1; 3159 3160 /* Assume only one bit is set. */ 3161 #ifdef _KERNEL 3162 format_bytes(buf, sizeof(buf), 1LL << (bitpos + 12)); 3163 #else 3164 humanize_number(buf, sizeof(buf), 1LL << (bitpos + 12), 3165 "B", HN_AUTOSCALE, 0); 3166 #endif 3167 printf("%s", buf); 3168 } else { 3169 printf("unknown"); 3170 } 3171 printf("\n"); 3172 3173 for (i = 0; i < 6; i++) { 3174 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 3175 printf(" VF BAR%d register: 0x%08x\n", i, reg); 3176 } 3177 3178 if (total_vfs > 0) { 3179 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 3180 printf(" VF Migration State Array Offset register: 0x%08x\n", 3181 reg); 3182 printf(" VF Migration State Offset: 0x%08x\n", 3183 (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 3184 i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 3185 printf(" VF Migration State BIR: "); 3186 if (i >= 0 && i <= 5) { 3187 printf("BAR%d", i); 3188 } else { 3189 printf("unknown BAR (%d)", i); 3190 } 3191 printf("\n"); 3192 } 3193 } 3194 3195 /* XXX pci_conf_print_mriov_cap */ 3196 3197 static void 3198 pci_conf_print_multicast_cap(const pcireg_t *regs, int capoff, int extcapoff) 3199 { 3200 pcireg_t reg, cap, ctl; 3201 pcireg_t regl, regh; 3202 uint64_t addr; 3203 int n; 3204 3205 printf("\n Multicast\n"); 3206 3207 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 3208 cap = reg & 0xffff; 3209 ctl = reg >> 16; 3210 printf(" Capability Register: 0x%04x\n", cap); 3211 printf(" Max Group: %u\n", 3212 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 3213 3214 /* Endpoint Only */ 3215 n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 3216 if (n > 0) 3217 printf(" Windw Size Requested: %d\n", 1 << (n - 1)); 3218 3219 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 3220 3221 printf(" Control Register: 0x%04x\n", ctl); 3222 printf(" Num Group: %u\n", 3223 (unsigned int)__SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 3224 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 3225 3226 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 3227 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 3228 printf(" Base Address Register 0: 0x%08x\n", regl); 3229 printf(" Base Address Register 1: 0x%08x\n", regh); 3230 printf(" Index Position: %u\n", 3231 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 3232 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 3233 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 3234 3235 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 3236 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 3237 printf(" Receive Register 0: 0x%08x\n", regl); 3238 printf(" Receive Register 1: 0x%08x\n", regh); 3239 3240 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 3241 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 3242 printf(" Block All Register 0: 0x%08x\n", regl); 3243 printf(" Block All Register 1: 0x%08x\n", regh); 3244 3245 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 3246 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 3247 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 3248 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 3249 3250 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 3251 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 3252 printf(" Overlay BAR 0: 0x%08x\n", regl); 3253 printf(" Overlay BAR 1: 0x%08x\n", regh); 3254 3255 n = regl & PCI_MCAST_OVERLAYL_SIZE; 3256 printf(" Overlay Size: "); 3257 if (n >= 6) 3258 printf("%d\n", n); 3259 else 3260 printf("off\n"); 3261 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 3262 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 3263 } 3264 3265 static void 3266 pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3267 { 3268 pcireg_t reg, ctl, sta; 3269 3270 printf("\n Page Request\n"); 3271 3272 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 3273 ctl = reg & 0xffff; 3274 sta = reg >> 16; 3275 printf(" Control Register: 0x%04x\n", ctl); 3276 onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E); 3277 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 3278 3279 printf(" Status Register: 0x%04x\n", sta); 3280 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 3281 onoff("Unexpected Page Request Group Index", reg, 3282 PCI_PAGE_REQ_STA_UPRGI); 3283 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 3284 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 3285 3286 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 3287 printf(" Outstanding Page Request Capacity: %u\n", reg); 3288 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 3289 printf(" Outstanding Page Request Allocation: %u\n", reg); 3290 } 3291 3292 /* XXX pci_conf_print_amd_cap */ 3293 3294 #define MEM_PBUFSIZE sizeof("999GB") 3295 3296 static void 3297 pci_conf_print_resizbar_cap(const pcireg_t *regs, int capoff, int extcapoff) 3298 { 3299 pcireg_t cap, ctl; 3300 unsigned int bars, i, n; 3301 char pbuf[MEM_PBUFSIZE]; 3302 3303 printf("\n Resizable BAR\n"); 3304 3305 /* Get Number of Resizable BARs */ 3306 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))]; 3307 bars = __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR); 3308 printf(" Number of Resizable BARs: "); 3309 if (bars <= 6) 3310 printf("%u\n", bars); 3311 else { 3312 printf("incorrect (%u)\n", bars); 3313 return; 3314 } 3315 3316 for (n = 0; n < 6; n++) { 3317 cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))]; 3318 printf(" Capability register(%u): 0x%08x\n", n, cap); 3319 if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0) 3320 continue; /* Not Used */ 3321 printf(" Acceptable BAR sizes:"); 3322 for (i = 4; i <= 23; i++) { 3323 if ((cap & (1 << i)) != 0) { 3324 humanize_number(pbuf, MEM_PBUFSIZE, 3325 (int64_t)1024 * 1024 << (i - 4), "B", 3326 #ifdef _KERNEL 3327 1); 3328 #else 3329 HN_AUTOSCALE, HN_NOSPACE); 3330 #endif 3331 printf(" %s", pbuf); 3332 } 3333 } 3334 printf("\n"); 3335 3336 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))]; 3337 printf(" Control register(%u): 0x%08x\n", n, ctl); 3338 printf(" BAR Index: %u\n", 3339 (unsigned int)__SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX)); 3340 humanize_number(pbuf, MEM_PBUFSIZE, 3341 (int64_t)1024 * 1024 3342 << __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ), 3343 "B", 3344 #ifdef _KERNEL 3345 1); 3346 #else 3347 HN_AUTOSCALE, HN_NOSPACE); 3348 #endif 3349 printf(" BAR Size: %s\n", pbuf); 3350 } 3351 } 3352 3353 static void 3354 pci_conf_print_dpa_cap(const pcireg_t *regs, int capoff, int extcapoff) 3355 { 3356 pcireg_t reg; 3357 unsigned int substmax, i; 3358 3359 printf("\n Dynamic Power Allocation\n"); 3360 3361 reg = regs[o2i(extcapoff + PCI_DPA_CAP)]; 3362 printf(" Capability register: 0x%08x\n", reg); 3363 substmax = __SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX); 3364 printf(" Substate Max: %u\n", substmax); 3365 printf(" Transition Latency Unit: "); 3366 switch (__SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) { 3367 case 0: 3368 printf("1ms\n"); 3369 break; 3370 case 1: 3371 printf("10ms\n"); 3372 break; 3373 case 2: 3374 printf("100ms\n"); 3375 break; 3376 default: 3377 printf("reserved\n"); 3378 break; 3379 } 3380 printf(" Power Allocation Scale: "); 3381 switch (__SHIFTOUT(reg, PCI_DPA_CAP_PAS)) { 3382 case 0: 3383 printf("10.0x\n"); 3384 break; 3385 case 1: 3386 printf("1.0x\n"); 3387 break; 3388 case 2: 3389 printf("0.1x\n"); 3390 break; 3391 case 3: 3392 printf("0.01x\n"); 3393 break; 3394 } 3395 printf(" Transition Latency Value 0: %u\n", 3396 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY0)); 3397 printf(" Transition Latency Value 1: %u\n", 3398 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); 3399 3400 reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; 3401 printf(" Latency Indicatior register: 0x%08x\n", reg); 3402 3403 reg = regs[o2i(extcapoff + PCI_DPA_CS)]; 3404 printf(" Status register: 0x%04x\n", reg & 0xffff); 3405 printf(" Substate Status: 0x%02x\n", 3406 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT)); 3407 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN); 3408 printf(" Control register: 0x%04x\n", reg >> 16); 3409 printf(" Substate Control: 0x%02x\n", 3410 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL)); 3411 3412 for (i = 0; i <= substmax; i++) 3413 printf(" Substate Power Allocation register %d: 0x%02x\n", 3414 i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff)); 3415 } 3416 3417 static const char * 3418 pci_conf_print_tph_req_cap_sttabloc(unsigned char val) 3419 { 3420 3421 switch (val) { 3422 case 0x0: 3423 return "Not Present"; 3424 case 0x1: 3425 return "in the TPH Requester Capability Structure"; 3426 case 0x2: 3427 return "in the MSI-X Table"; 3428 default: 3429 return "Unknown"; 3430 } 3431 } 3432 3433 static void 3434 pci_conf_print_tph_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3435 { 3436 pcireg_t reg; 3437 int size, i, j; 3438 3439 printf("\n TPH Requester Extended Capability\n"); 3440 3441 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3442 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3443 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3444 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3445 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3446 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3447 printf(" ST Table Location: %s\n", 3448 pci_conf_print_tph_req_cap_sttabloc( 3449 (unsigned char)__SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC))); 3450 size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3451 printf(" ST Table Size: %d\n", size); 3452 3453 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CTL)]; 3454 printf(" TPH Requester Control register: 0x%08x\n", reg); 3455 printf(" ST Mode Select: "); 3456 switch (__SHIFTOUT(reg, PCI_TPH_REQ_CTL_STSEL)) { 3457 case PCI_TPH_REQ_CTL_STSEL_NO: 3458 printf("No ST Mode\n"); 3459 break; 3460 case PCI_TPH_REQ_CTL_STSEL_IV: 3461 printf("Interrupt Vector Mode\n"); 3462 break; 3463 case PCI_TPH_REQ_CTL_STSEL_DS: 3464 printf("Device Specific Mode\n"); 3465 break; 3466 default: 3467 printf("(reserved vaule)\n"); 3468 break; 3469 } 3470 printf(" TPH Requester Enable: "); 3471 switch (__SHIFTOUT(reg, PCI_TPH_REQ_CTL_TPHREQEN)) { 3472 case PCI_TPH_REQ_CTL_TPHREQEN_NO: /* 0x0 */ 3473 printf("Not permitted\n"); 3474 break; 3475 case PCI_TPH_REQ_CTL_TPHREQEN_TPH: 3476 printf("TPH and not Extended TPH\n"); 3477 break; 3478 case PCI_TPH_REQ_CTL_TPHREQEN_ETPH: 3479 printf("TPH and Extended TPH"); 3480 break; 3481 default: 3482 printf("(reserved vaule)\n"); 3483 break; 3484 } 3485 3486 for (i = 0; i < size ; i += 2) { 3487 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3488 for (j = 0; j < 2 ; j++) { 3489 uint32_t entry = reg; 3490 3491 if (j != 0) 3492 entry >>= 16; 3493 entry &= 0xffff; 3494 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3495 i + j, entry); 3496 } 3497 } 3498 } 3499 3500 static void 3501 pci_conf_print_ltr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3502 { 3503 pcireg_t reg; 3504 3505 printf("\n Latency Tolerance Reporting\n"); 3506 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)]; 3507 printf(" Max Snoop Latency Register: 0x%04x\n", reg & 0xffff); 3508 printf(" Max Snoop Latency: %juns\n", 3509 (uintmax_t)(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL) 3510 * PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE)))); 3511 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg >> 16); 3512 printf(" Max No-Snoop Latency: %juns\n", 3513 (uintmax_t)(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL) 3514 * PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE)))); 3515 } 3516 3517 static void 3518 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int capoff, int extcapoff) 3519 { 3520 int pcie_capoff; 3521 pcireg_t reg; 3522 int i, maxlinkwidth; 3523 3524 printf("\n Secondary PCI Express Register\n"); 3525 3526 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3527 printf(" Link Control 3 register: 0x%08x\n", reg); 3528 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3529 onoff("Link Equalization Request Interrupt Enable", 3530 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3531 printf(" Enable Lower SKP OS Generation Vector:"); 3532 pci_print_pcie_linkspeedvector( 3533 __SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3534 printf("\n"); 3535 3536 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3537 printf(" Lane Error Status register: 0x%08x\n", reg); 3538 3539 /* Get Max Link Width */ 3540 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)){ 3541 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3542 maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3543 } else { 3544 printf("error: falied to get PCIe capablity\n"); 3545 return; 3546 } 3547 for (i = 0; i < maxlinkwidth; i++) { 3548 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3549 if (i % 2 != 0) 3550 reg >>= 16; 3551 else 3552 reg &= 0xffff; 3553 printf(" Equalization Control Register (Link %d): 0x%04x\n", 3554 i, reg); 3555 printf(" Downstream Port Transmit Preset: 0x%x\n", 3556 (pcireg_t)__SHIFTOUT(reg, 3557 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3558 printf(" Downstream Port Receive Hint: 0x%x\n", 3559 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3560 printf(" Upstream Port Transmit Preset: 0x%x\n", 3561 (pcireg_t)__SHIFTOUT(reg, 3562 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3563 printf(" Upstream Port Receive Hint: 0x%x\n", 3564 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3565 } 3566 } 3567 3568 /* XXX pci_conf_print_pmux_cap */ 3569 3570 static void 3571 pci_conf_print_pasid_cap(const pcireg_t *regs, int capoff, int extcapoff) 3572 { 3573 pcireg_t reg, cap, ctl; 3574 unsigned int num; 3575 3576 printf("\n Process Address Space ID\n"); 3577 3578 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3579 cap = reg & 0xffff; 3580 ctl = reg >> 16; 3581 printf(" PASID Capability Register: 0x%04x\n", cap); 3582 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3583 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3584 num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3585 printf(" Max PASID Width: %u\n", num); 3586 3587 printf(" PASID Control Register: 0x%04x\n", ctl); 3588 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3589 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3590 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3591 } 3592 3593 static void 3594 pci_conf_print_lnr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3595 { 3596 pcireg_t reg, cap, ctl; 3597 unsigned int num; 3598 3599 printf("\n LN Requester\n"); 3600 3601 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3602 cap = reg & 0xffff; 3603 ctl = reg >> 16; 3604 printf(" LNR Capability register: 0x%04x\n", cap); 3605 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 3606 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 3607 num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 3608 printf(" LNR Registration MAX: %u\n", num); 3609 3610 printf(" LNR Control register: 0x%04x\n", ctl); 3611 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 3612 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 3613 num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 3614 printf(" LNR Registration Limit: %u\n", num); 3615 } 3616 3617 static void 3618 pci_conf_print_dpc_pio(pcireg_t r) 3619 { 3620 onoff("Cfg Request received UR Completion", r,PCI_DPC_RPPIO_CFGUR_CPL); 3621 onoff("Cfg Request received CA Completion", r,PCI_DPC_RPPIO_CFGCA_CPL); 3622 onoff("Cfg Request Completion Timeout", r, PCI_DPC_RPPIO_CFG_CTO); 3623 onoff("I/O Request received UR Completion", r, PCI_DPC_RPPIO_IOUR_CPL); 3624 onoff("I/O Request received CA Completion", r, PCI_DPC_RPPIO_IOCA_CPL); 3625 onoff("I/O Request Completion Timeout", r, PCI_DPC_RPPIO_IO_CTO); 3626 onoff("Mem Request received UR Completion", r,PCI_DPC_RPPIO_MEMUR_CPL); 3627 onoff("Mem Request received CA Completion", r,PCI_DPC_RPPIO_MEMCA_CPL); 3628 onoff("Mem Request Completion Timeout", r, PCI_DPC_RPPIO_MEM_CTO); 3629 } 3630 3631 static void 3632 pci_conf_print_dpc_cap(const pcireg_t *regs, int capoff, int extcapoff) 3633 { 3634 pcireg_t reg, cap, ctl, stat, errsrc; 3635 const char *trigstr; 3636 bool rpext; 3637 3638 printf("\n Downstream Port Containment\n"); 3639 3640 reg = regs[o2i(extcapoff + PCI_DPC_CCR)]; 3641 cap = reg & 0xffff; 3642 ctl = reg >> 16; 3643 rpext = (reg & PCI_DPCCAP_RPEXT) ? true : false; 3644 printf(" DPC Capability register: 0x%04x\n", cap); 3645 printf(" DPC Interrupt Message Number: %02x\n", 3646 (unsigned int)(cap & PCI_DPCCAP_IMSGN)); 3647 onoff("RP Extensions for DPC", reg, PCI_DPCCAP_RPEXT); 3648 onoff("Poisoned TLP Egress Blocking Supported", reg, 3649 PCI_DPCCAP_POISONTLPEB); 3650 onoff("DPC Software Triggering Supported", reg, PCI_DPCCAP_SWTRIG); 3651 printf(" RP PIO Log Size: %u\n", 3652 (unsigned int)__SHIFTOUT(reg, PCI_DPCCAP_RPPIOLOGSZ)); 3653 onoff("DL_Active ERR_COR Signaling Supported", reg, 3654 PCI_DPCCAP_DLACTECORS); 3655 printf(" DPC Control register: 0x%04x\n", ctl); 3656 switch (__SHIFTOUT(reg, PCI_DPCCTL_TIRGEN)) { 3657 case 0: 3658 trigstr = "disabled"; 3659 break; 3660 case 1: 3661 trigstr = "enabled(ERR_FATAL)"; 3662 break; 3663 case 2: 3664 trigstr = "enabled(ERR_NONFATAL or ERR_FATAL)"; 3665 break; 3666 default: 3667 trigstr = "(reserverd)"; 3668 break; 3669 } 3670 printf(" DPC Trigger Enable: %s\n", trigstr); 3671 printf(" DPC Completion Control: %s Completion Status\n", 3672 (reg & PCI_DPCCTL_COMPCTL) 3673 ? "Unsupported Request(UR)" : "Completer Abort(CA)"); 3674 onoff("DPC Interrupt Enable", reg, PCI_DPCCTL_IE); 3675 onoff("DPC ERR_COR Enable", reg, PCI_DPCCTL_ERRCOREN); 3676 onoff("Poisoned TLP Egress Blocking Enable", reg, 3677 PCI_DPCCTL_POISONTLPEB); 3678 onoff("DPC Software Trigger", reg, PCI_DPCCTL_SWTRIG); 3679 onoff("DL_Active ERR_COR Enable", reg, PCI_DPCCTL_DLACTECOR); 3680 3681 reg = regs[o2i(extcapoff + PCI_DPC_STATESID)]; 3682 stat = reg & 0xffff; 3683 errsrc = reg >> 16; 3684 printf(" DPC Status register: 0x%04x\n", stat); 3685 onoff("DPC Trigger Status", reg, PCI_DPCSTAT_TSTAT); 3686 switch (__SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 3687 case 0: 3688 trigstr = "an unmasked uncorrectable error"; 3689 break; 3690 case 1: 3691 trigstr = "receiving an ERR_NONFATAL"; 3692 break; 3693 case 2: 3694 trigstr = "receiving an ERR_FATAL"; 3695 break; 3696 case 3: 3697 trigstr = "DPC Trigger Reason Extension field"; 3698 break; 3699 } 3700 printf(" DPC Trigger Reason: Due to %s\n", trigstr); 3701 onoff("DPC Interrupt Status", reg, PCI_DPCSTAT_ISTAT); 3702 if (rpext) 3703 onoff("DPC RP Busy", reg, PCI_DPCSTAT_RPBUSY); 3704 switch (__SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 3705 case 0: 3706 trigstr = "Due to RP PIO error"; 3707 break; 3708 case 1: 3709 trigstr = "Due to the DPC Software trigger bit"; 3710 break; 3711 default: 3712 trigstr = "(reserved)"; 3713 break; 3714 } 3715 printf(" DPC Trigger Reason Extension: %s\n", trigstr); 3716 if (rpext) 3717 printf(" RP PIO First Error Pointer: %02x\n", 3718 (unsigned int)__SHIFTOUT(reg, PCI_DPCSTAT_RPPIOFEP)); 3719 printf(" DPC Error Source ID register: 0x%04x\n", errsrc); 3720 3721 if (!rpext) 3722 return; 3723 /* 3724 * All of the following registers are implemented by a device which has 3725 * RP Extensions for DPC 3726 */ 3727 3728 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_STAT)]; 3729 printf(" RP PIO Status Register: 0x%04x\n", reg); 3730 pci_conf_print_dpc_pio(reg); 3731 3732 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_MASK)]; 3733 printf(" RP PIO Mask Register: 0x%04x\n", reg); 3734 pci_conf_print_dpc_pio(reg); 3735 3736 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SEVE)]; 3737 printf(" RP PIO Severity Register: 0x%04x\n", reg); 3738 pci_conf_print_dpc_pio(reg); 3739 3740 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SYSERR)]; 3741 printf(" RP PIO SysError Register: 0x%04x\n", reg); 3742 pci_conf_print_dpc_pio(reg); 3743 3744 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_EXCPT)]; 3745 printf(" RP PIO Exception Register: 0x%04x\n", reg); 3746 pci_conf_print_dpc_pio(reg); 3747 3748 printf(" RP PIO Header Log Register: start from 0x%03x\n", 3749 extcapoff + PCI_DPC_RPPIO_HLOG); 3750 printf(" RP PIO ImpSpec Log Register: start from 0x%03x\n", 3751 extcapoff + PCI_DPC_RPPIO_IMPSLOG); 3752 printf(" RP PIO TPL Prefix Log Register: start from 0x%03x\n", 3753 extcapoff + PCI_DPC_RPPIO_TLPPLOG); 3754 } 3755 3756 3757 static int 3758 pci_conf_l1pm_cap_tposcale(unsigned char scale) 3759 { 3760 3761 /* Return scale in us */ 3762 switch (scale) { 3763 case 0x0: 3764 return 2; 3765 case 0x1: 3766 return 10; 3767 case 0x2: 3768 return 100; 3769 default: 3770 return -1; 3771 } 3772 } 3773 3774 static void 3775 pci_conf_print_l1pm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3776 { 3777 pcireg_t reg; 3778 int scale, val; 3779 3780 printf("\n L1 PM Substates\n"); 3781 3782 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 3783 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 3784 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 3785 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 3786 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 3787 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 3788 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 3789 printf(" Port Common Mode Restore Time: %uus\n", 3790 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 3791 scale = pci_conf_l1pm_cap_tposcale( 3792 __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 3793 val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 3794 printf(" Port T_POWER_ON: "); 3795 if (scale == -1) 3796 printf("unknown\n"); 3797 else 3798 printf("%dus\n", val * scale); 3799 3800 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 3801 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 3802 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 3803 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 3804 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 3805 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 3806 printf(" Common Mode Restore Time: %uus\n", 3807 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 3808 scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 3809 val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 3810 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 3811 3812 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 3813 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 3814 scale = pci_conf_l1pm_cap_tposcale( 3815 __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 3816 val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 3817 printf(" T_POWER_ON: "); 3818 if (scale == -1) 3819 printf("unknown\n"); 3820 else 3821 printf("%dus\n", val * scale); 3822 } 3823 3824 static void 3825 pci_conf_print_ptm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3826 { 3827 pcireg_t reg; 3828 uint32_t val; 3829 3830 printf("\n Precision Time Management\n"); 3831 3832 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 3833 printf(" PTM Capability register: 0x%08x\n", reg); 3834 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 3835 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 3836 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 3837 printf(" Local Clock Granularity: "); 3838 val = __SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 3839 switch (val) { 3840 case 0: 3841 printf("Not implemented\n"); 3842 break; 3843 case 0xffff: 3844 printf("> 254ns\n"); 3845 break; 3846 default: 3847 printf("%uns\n", val); 3848 break; 3849 } 3850 3851 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 3852 printf(" PTM Control register: 0x%08x\n", reg); 3853 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 3854 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 3855 printf(" Effective Granularity: "); 3856 val = __SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 3857 switch (val) { 3858 case 0: 3859 printf("Unknown\n"); 3860 break; 3861 case 0xffff: 3862 printf("> 254ns\n"); 3863 break; 3864 default: 3865 printf("%uns\n", val); 3866 break; 3867 } 3868 } 3869 3870 /* XXX pci_conf_print_mpcie_cap */ 3871 /* XXX pci_conf_print_frsq_cap */ 3872 /* XXX pci_conf_print_rtr_cap */ 3873 /* XXX pci_conf_print_desigvndsp_cap */ 3874 /* XXX pci_conf_print_vf_resizbar_cap */ 3875 /* XXX pci_conf_print_hierarchyid_cap */ 3876 /* XXX pci_conf_print_npem_cap */ 3877 3878 #undef MS 3879 #undef SM 3880 #undef RW 3881 3882 static struct { 3883 pcireg_t cap; 3884 const char *name; 3885 void (*printfunc)(const pcireg_t *, int, int); 3886 } pci_extcaptab[] = { 3887 { 0, "reserved", 3888 NULL }, 3889 { PCI_EXTCAP_AER, "Advanced Error Reporting", 3890 pci_conf_print_aer_cap }, 3891 { PCI_EXTCAP_VC, "Virtual Channel", 3892 pci_conf_print_vc_cap }, 3893 { PCI_EXTCAP_SERNUM, "Device Serial Number", 3894 pci_conf_print_sernum_cap }, 3895 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 3896 pci_conf_print_pwrbdgt_cap }, 3897 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 3898 pci_conf_print_rclink_dcl_cap }, 3899 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 3900 NULL }, 3901 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 3902 pci_conf_print_rcec_assoc_cap }, 3903 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 3904 NULL }, 3905 { PCI_EXTCAP_VC2, "Virtual Channel", 3906 NULL }, 3907 { PCI_EXTCAP_RCRB, "RCRB Header", 3908 NULL }, 3909 { PCI_EXTCAP_VENDOR, "Vendor Unique", 3910 NULL }, 3911 { PCI_EXTCAP_CAC, "Configuration Access Correction", 3912 NULL }, 3913 { PCI_EXTCAP_ACS, "Access Control Services", 3914 pci_conf_print_acs_cap }, 3915 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 3916 pci_conf_print_ari_cap }, 3917 { PCI_EXTCAP_ATS, "Address Translation Services", 3918 pci_conf_print_ats_cap }, 3919 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 3920 pci_conf_print_sriov_cap }, 3921 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 3922 NULL }, 3923 { PCI_EXTCAP_MCAST, "Multicast", 3924 pci_conf_print_multicast_cap }, 3925 { PCI_EXTCAP_PAGE_REQ, "Page Request", 3926 pci_conf_print_page_req_cap }, 3927 { PCI_EXTCAP_AMD, "Reserved for AMD", 3928 NULL }, 3929 { PCI_EXTCAP_RESIZBAR, "Resizable BAR", 3930 pci_conf_print_resizbar_cap }, 3931 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 3932 pci_conf_print_dpa_cap }, 3933 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 3934 pci_conf_print_tph_req_cap }, 3935 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 3936 pci_conf_print_ltr_cap }, 3937 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 3938 pci_conf_print_sec_pcie_cap }, 3939 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 3940 NULL }, 3941 { PCI_EXTCAP_PASID, "Process Address Space ID", 3942 pci_conf_print_pasid_cap }, 3943 { PCI_EXTCAP_LNR, "LN Requester", 3944 pci_conf_print_lnr_cap }, 3945 { PCI_EXTCAP_DPC, "Downstream Port Containment", 3946 pci_conf_print_dpc_cap }, 3947 { PCI_EXTCAP_L1PM, "L1 PM Substates", 3948 pci_conf_print_l1pm_cap }, 3949 { PCI_EXTCAP_PTM, "Precision Time Management", 3950 pci_conf_print_ptm_cap }, 3951 { PCI_EXTCAP_MPCIE, "M-PCIe", 3952 NULL }, 3953 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 3954 NULL }, 3955 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 3956 NULL }, 3957 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 3958 NULL }, 3959 { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", 3960 NULL }, 3961 { PCI_EXTCAP_HIERARCHYID, "Hierarchy ID", 3962 NULL }, 3963 { PCI_EXTCAP_NPEM, "Native PCIe Enclosure Management", 3964 NULL }, 3965 }; 3966 3967 static int 3968 pci_conf_find_extcap(const pcireg_t *regs, int capoff, unsigned int capid, 3969 int *offsetp) 3970 { 3971 int off; 3972 pcireg_t rval; 3973 3974 for (off = PCI_EXTCAPLIST_BASE; 3975 off != 0; 3976 off = PCI_EXTCAPLIST_NEXT(rval)) { 3977 rval = regs[o2i(off)]; 3978 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 3979 if (offsetp != NULL) 3980 *offsetp = off; 3981 return 1; 3982 } 3983 } 3984 return 0; 3985 } 3986 3987 static void 3988 pci_conf_print_extcaplist( 3989 #ifdef _KERNEL 3990 pci_chipset_tag_t pc, pcitag_t tag, 3991 #endif 3992 const pcireg_t *regs, int capoff) 3993 { 3994 int off; 3995 pcireg_t foundcap; 3996 pcireg_t rval; 3997 bool foundtable[__arraycount(pci_extcaptab)]; 3998 unsigned int i; 3999 4000 /* Check Extended capability structure */ 4001 off = PCI_EXTCAPLIST_BASE; 4002 rval = regs[o2i(off)]; 4003 if (rval == 0xffffffff || rval == 0) 4004 return; 4005 4006 /* Clear table */ 4007 for (i = 0; i < __arraycount(pci_extcaptab); i++) 4008 foundtable[i] = false; 4009 4010 /* Print extended capability register's offset and the type first */ 4011 for (;;) { 4012 printf(" Extended Capability Register at 0x%02x\n", off); 4013 4014 foundcap = PCI_EXTCAPLIST_CAP(rval); 4015 printf(" type: 0x%04x (", foundcap); 4016 if (foundcap < __arraycount(pci_extcaptab)) { 4017 printf("%s)\n", pci_extcaptab[foundcap].name); 4018 /* Mark as found */ 4019 foundtable[foundcap] = true; 4020 } else 4021 printf("unknown)\n"); 4022 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 4023 4024 off = PCI_EXTCAPLIST_NEXT(rval); 4025 if (off == 0) 4026 break; 4027 else if (off <= PCI_CONF_SIZE) { 4028 printf(" next pointer: 0x%03x (incorrect)\n", off); 4029 return; 4030 } 4031 rval = regs[o2i(off)]; 4032 } 4033 4034 /* 4035 * And then, print the detail of each capability registers 4036 * in capability value's order. 4037 */ 4038 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 4039 if (foundtable[i] == false) 4040 continue; 4041 4042 /* 4043 * The type was found. Search capability list again and 4044 * print all capabilities that the capabiliy type is 4045 * the same. 4046 */ 4047 if (pci_conf_find_extcap(regs, capoff, i, &off) == 0) 4048 continue; 4049 rval = regs[o2i(off)]; 4050 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 4051 || (pci_extcaptab[i].printfunc == NULL)) 4052 continue; 4053 4054 pci_extcaptab[i].printfunc(regs, capoff, off); 4055 4056 } 4057 } 4058 4059 /* Print the Secondary Status Register. */ 4060 static void 4061 pci_conf_print_ssr(pcireg_t rval) 4062 { 4063 pcireg_t devsel; 4064 4065 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 4066 onoff("66 MHz capable", rval, __BIT(5)); 4067 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 4068 onoff("Fast back-to-back capable", rval, __BIT(7)); 4069 onoff("Data parity error detected", rval, __BIT(8)); 4070 4071 printf(" DEVSEL timing: "); 4072 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 4073 switch (devsel) { 4074 case 0: 4075 printf("fast"); 4076 break; 4077 case 1: 4078 printf("medium"); 4079 break; 4080 case 2: 4081 printf("slow"); 4082 break; 4083 default: 4084 printf("unknown/reserved"); /* XXX */ 4085 break; 4086 } 4087 printf(" (0x%x)\n", devsel); 4088 4089 onoff("Signalled target abort", rval, __BIT(11)); 4090 onoff("Received target abort", rval, __BIT(12)); 4091 onoff("Received master abort", rval, __BIT(13)); 4092 onoff("Received system error", rval, __BIT(14)); 4093 onoff("Detected parity error", rval, __BIT(15)); 4094 } 4095 4096 static void 4097 pci_conf_print_type0( 4098 #ifdef _KERNEL 4099 pci_chipset_tag_t pc, pcitag_t tag, 4100 #endif 4101 const pcireg_t *regs) 4102 { 4103 int off, width; 4104 pcireg_t rval; 4105 const char *str; 4106 4107 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 4108 #ifdef _KERNEL 4109 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4110 #else 4111 width = pci_conf_print_bar(regs, off, NULL); 4112 #endif 4113 } 4114 4115 printf(" Cardbus CIS Pointer: 0x%08x\n", 4116 regs[o2i(PCI_CARDBUS_CIS_REG)]); 4117 4118 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 4119 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4120 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4121 4122 rval = regs[o2i(PCI_MAPREG_ROM)]; 4123 printf(" Expansion ROM Base Address Register: 0x%08x\n", rval); 4124 printf(" base: 0x%08x\n", (uint32_t)PCI_MAPREG_ROM_ADDR(rval)); 4125 onoff("Expansion ROM Enable", rval, PCI_MAPREG_ROM_ENABLE); 4126 printf(" Validation Status: "); 4127 switch (__SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_STAT)) { 4128 case PCI_MAPREG_ROM_VSTAT_NOTSUPP: 4129 str = "Validation not supported"; 4130 break; 4131 case PCI_MAPREG_ROM_VSTAT_INPROG: 4132 str = "Validation in Progress"; 4133 break; 4134 case PCI_MAPREG_ROM_VSTAT_VPASS: 4135 str = "Validation Pass. " 4136 "Valid contents, trust test was not performed"; 4137 break; 4138 case PCI_MAPREG_ROM_VSTAT_VPASSTRUST: 4139 str = "Validation Pass. Valid and trusted contents"; 4140 break; 4141 case PCI_MAPREG_ROM_VSTAT_VFAIL: 4142 str = "Validation Fail. Invalid contents"; 4143 break; 4144 case PCI_MAPREG_ROM_VSTAT_VFAILUNTRUST: 4145 str = "Validation Fail. Valid but untrusted contents"; 4146 break; 4147 case PCI_MAPREG_ROM_VSTAT_WPASS: 4148 str = "Warning Pass. Validation passed with warning. " 4149 "Valid contents, trust test was not performed"; 4150 break; 4151 case PCI_MAPREG_ROM_VSTAT_WPASSTRUST: 4152 str = "Warning Pass. Validation passed with warning. " 4153 "Valid and trusted contents"; 4154 break; 4155 } 4156 printf("%s\n", str); 4157 printf(" Validation Details: 0x%x\n", 4158 (uint32_t)__SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_DETAIL)); 4159 4160 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4161 printf(" Capability list pointer: 0x%02x\n", 4162 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4163 else 4164 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4165 4166 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 4167 4168 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4169 printf(" Maximum Latency: 0x%02x\n", PCI_MAX_LAT(rval)); 4170 printf(" Minimum Grant: 0x%02x\n", PCI_MIN_GNT(rval)); 4171 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 4172 switch (PCI_INTERRUPT_PIN(rval)) { 4173 case PCI_INTERRUPT_PIN_NONE: 4174 printf("(none)"); 4175 break; 4176 case PCI_INTERRUPT_PIN_A: 4177 printf("(pin A)"); 4178 break; 4179 case PCI_INTERRUPT_PIN_B: 4180 printf("(pin B)"); 4181 break; 4182 case PCI_INTERRUPT_PIN_C: 4183 printf("(pin C)"); 4184 break; 4185 case PCI_INTERRUPT_PIN_D: 4186 printf("(pin D)"); 4187 break; 4188 default: 4189 printf("(? ? ?)"); 4190 break; 4191 } 4192 printf("\n"); 4193 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 4194 } 4195 4196 static void 4197 pci_conf_print_type1( 4198 #ifdef _KERNEL 4199 pci_chipset_tag_t pc, pcitag_t tag, 4200 #endif 4201 const pcireg_t *regs) 4202 { 4203 int off, width; 4204 pcireg_t rval; 4205 uint32_t base, limit; 4206 uint32_t base_h, limit_h; 4207 uint64_t pbase, plimit; 4208 int use_upper; 4209 4210 /* 4211 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 4212 * Bridge chip documentation, and may not be correct with 4213 * respect to various standards. (XXX) 4214 */ 4215 4216 for (off = 0x10; off < 0x18; off += width) { 4217 #ifdef _KERNEL 4218 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4219 #else 4220 width = pci_conf_print_bar(regs, off, NULL); 4221 #endif 4222 } 4223 4224 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4225 printf(" Primary bus number: 0x%02x\n", 4226 PCI_BRIDGE_BUS_PRIMARY(rval)); 4227 printf(" Secondary bus number: 0x%02x\n", 4228 PCI_BRIDGE_BUS_SECONDARY(rval)); 4229 printf(" Subordinate bus number: 0x%02x\n", 4230 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 4231 printf(" Secondary bus latency timer: 0x%02x\n", 4232 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 4233 4234 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 4235 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 4236 4237 /* I/O region */ 4238 printf(" I/O region:\n"); 4239 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 4240 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 4241 if (PCI_BRIDGE_IO_32BITS(rval)) 4242 use_upper = 1; 4243 else 4244 use_upper = 0; 4245 onoff("32bit I/O", rval, use_upper); 4246 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 4247 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 4248 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 4249 limit |= 0x00000fff; 4250 4251 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 4252 base_h = (rval >> 0) & 0xffff; 4253 limit_h = (rval >> 16) & 0xffff; 4254 printf(" base upper 16 bits register: 0x%04x\n", base_h); 4255 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 4256 4257 if (use_upper == 1) { 4258 base |= base_h << 16; 4259 limit |= limit_h << 16; 4260 } 4261 if (base < limit) { 4262 if (use_upper == 1) 4263 printf(" range: 0x%08x-0x%08x\n", base, limit); 4264 else 4265 printf(" range: 0x%04x-0x%04x\n", base, limit); 4266 } else 4267 printf(" range: not set\n"); 4268 4269 /* Non-prefetchable memory region */ 4270 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 4271 printf(" Memory region:\n"); 4272 printf(" base register: 0x%04x\n", 4273 (rval >> 0) & 0xffff); 4274 printf(" limit register: 0x%04x\n", 4275 (rval >> 16) & 0xffff); 4276 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 4277 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 4278 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 4279 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 4280 if (base < limit) 4281 printf(" range: 0x%08x-0x%08x\n", base, limit); 4282 else 4283 printf(" range: not set\n"); 4284 4285 /* Prefetchable memory region */ 4286 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 4287 printf(" Prefetchable memory region:\n"); 4288 printf(" base register: 0x%04x\n", 4289 (rval >> 0) & 0xffff); 4290 printf(" limit register: 0x%04x\n", 4291 (rval >> 16) & 0xffff); 4292 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 4293 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 4294 printf(" base upper 32 bits register: 0x%08x\n", 4295 base_h); 4296 printf(" limit upper 32 bits register: 0x%08x\n", 4297 limit_h); 4298 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 4299 use_upper = 1; 4300 else 4301 use_upper = 0; 4302 onoff("64bit memory address", rval, use_upper); 4303 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 4304 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 4305 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 4306 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 4307 if (use_upper == 1) { 4308 pbase |= (uint64_t)base_h << 32; 4309 plimit |= (uint64_t)limit_h << 32; 4310 } 4311 if (pbase < plimit) { 4312 if (use_upper == 1) 4313 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 4314 "\n", pbase, plimit); 4315 else 4316 printf(" range: 0x%08x-0x%08x\n", 4317 (uint32_t)pbase, (uint32_t)plimit); 4318 } else 4319 printf(" range: not set\n"); 4320 4321 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4322 printf(" Capability list pointer: 0x%02x\n", 4323 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4324 else 4325 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4326 4327 /* XXX */ 4328 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 4329 4330 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4331 printf(" Interrupt line: 0x%02x\n", 4332 (rval >> 0) & 0xff); 4333 printf(" Interrupt pin: 0x%02x ", 4334 (rval >> 8) & 0xff); 4335 switch ((rval >> 8) & 0xff) { 4336 case PCI_INTERRUPT_PIN_NONE: 4337 printf("(none)"); 4338 break; 4339 case PCI_INTERRUPT_PIN_A: 4340 printf("(pin A)"); 4341 break; 4342 case PCI_INTERRUPT_PIN_B: 4343 printf("(pin B)"); 4344 break; 4345 case PCI_INTERRUPT_PIN_C: 4346 printf("(pin C)"); 4347 break; 4348 case PCI_INTERRUPT_PIN_D: 4349 printf("(pin D)"); 4350 break; 4351 default: 4352 printf("(? ? ?)"); 4353 break; 4354 } 4355 printf("\n"); 4356 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 4357 & PCI_BRIDGE_CONTROL_MASK; 4358 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 4359 onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE); 4360 onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR); 4361 onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA); 4362 onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA); 4363 onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT); 4364 onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR); 4365 onoff("Fast back-to-back capable", rval,PCI_BRIDGE_CONTROL_SECFASTB2B); 4366 } 4367 4368 static void 4369 pci_conf_print_type2( 4370 #ifdef _KERNEL 4371 pci_chipset_tag_t pc, pcitag_t tag, 4372 #endif 4373 const pcireg_t *regs) 4374 { 4375 pcireg_t rval; 4376 4377 /* 4378 * XXX these need to be printed in more detail, need to be 4379 * XXX checked against specs/docs, etc. 4380 * 4381 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 4382 * controller chip documentation, and may not be correct with 4383 * respect to various standards. (XXX) 4384 */ 4385 4386 #ifdef _KERNEL 4387 pci_conf_print_bar(pc, tag, regs, 0x10, 4388 "CardBus socket/ExCA registers"); 4389 #else 4390 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 4391 #endif 4392 4393 /* Capability list pointer and secondary status register */ 4394 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 4395 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4396 printf(" Capability list pointer: 0x%02x\n", 4397 PCI_CAPLIST_PTR(rval)); 4398 else 4399 printf(" Reserved @ 0x14: 0x%04x\n", 4400 (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0))); 4401 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 4402 4403 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4404 printf(" PCI bus number: 0x%02x\n", 4405 (rval >> 0) & 0xff); 4406 printf(" CardBus bus number: 0x%02x\n", 4407 (rval >> 8) & 0xff); 4408 printf(" Subordinate bus number: 0x%02x\n", 4409 (rval >> 16) & 0xff); 4410 printf(" CardBus latency timer: 0x%02x\n", 4411 (rval >> 24) & 0xff); 4412 4413 /* XXX Print more prettily */ 4414 printf(" CardBus memory region 0:\n"); 4415 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 4416 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 4417 printf(" CardBus memory region 1:\n"); 4418 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 4419 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 4420 printf(" CardBus I/O region 0:\n"); 4421 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 4422 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 4423 printf(" CardBus I/O region 1:\n"); 4424 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 4425 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 4426 4427 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4428 printf(" Interrupt line: 0x%02x\n", 4429 (rval >> 0) & 0xff); 4430 printf(" Interrupt pin: 0x%02x ", 4431 (rval >> 8) & 0xff); 4432 switch ((rval >> 8) & 0xff) { 4433 case PCI_INTERRUPT_PIN_NONE: 4434 printf("(none)"); 4435 break; 4436 case PCI_INTERRUPT_PIN_A: 4437 printf("(pin A)"); 4438 break; 4439 case PCI_INTERRUPT_PIN_B: 4440 printf("(pin B)"); 4441 break; 4442 case PCI_INTERRUPT_PIN_C: 4443 printf("(pin C)"); 4444 break; 4445 case PCI_INTERRUPT_PIN_D: 4446 printf("(pin D)"); 4447 break; 4448 default: 4449 printf("(? ? ?)"); 4450 break; 4451 } 4452 printf("\n"); 4453 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> 16) & 0xffff; 4454 printf(" Bridge control register: 0x%04x\n", rval); 4455 onoff("Parity error response", rval, __BIT(0)); 4456 onoff("SERR# enable", rval, __BIT(1)); 4457 onoff("ISA enable", rval, __BIT(2)); 4458 onoff("VGA enable", rval, __BIT(3)); 4459 onoff("Master abort mode", rval, __BIT(5)); 4460 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 4461 onoff("Functional interrupts routed by ExCA registers", rval, 4462 __BIT(7)); 4463 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 4464 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 4465 onoff("Write posting enable", rval, __BIT(10)); 4466 4467 rval = regs[o2i(0x40)]; 4468 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4469 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4470 4471 #ifdef _KERNEL 4472 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers"); 4473 #else 4474 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 4475 #endif 4476 } 4477 4478 void 4479 pci_conf_print( 4480 #ifdef _KERNEL 4481 pci_chipset_tag_t pc, pcitag_t tag, 4482 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 4483 #else 4484 int pcifd, u_int bus, u_int dev, u_int func 4485 #endif 4486 ) 4487 { 4488 pcireg_t regs[o2i(PCI_EXTCONF_SIZE)]; 4489 int off, capoff, endoff, hdrtype; 4490 const char *type_name; 4491 #ifdef _KERNEL 4492 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 4493 #else 4494 void (*type_printfn)(const pcireg_t *); 4495 #endif 4496 4497 printf("PCI configuration registers:\n"); 4498 4499 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 4500 #ifdef _KERNEL 4501 regs[o2i(off)] = pci_conf_read(pc, tag, off); 4502 #else 4503 if (pcibus_conf_read(pcifd, bus, dev, func, off, 4504 ®s[o2i(off)]) == -1) 4505 regs[o2i(off)] = 0; 4506 #endif 4507 } 4508 4509 /* common header */ 4510 printf(" Common header:\n"); 4511 pci_conf_print_regs(regs, 0, 16); 4512 4513 printf("\n"); 4514 #ifdef _KERNEL 4515 pci_conf_print_common(pc, tag, regs); 4516 #else 4517 pci_conf_print_common(regs); 4518 #endif 4519 printf("\n"); 4520 4521 /* type-dependent header */ 4522 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 4523 switch (hdrtype) { /* XXX make a table, eventually */ 4524 case 0: 4525 /* Standard device header */ 4526 type_name = "\"normal\" device"; 4527 type_printfn = &pci_conf_print_type0; 4528 capoff = PCI_CAPLISTPTR_REG; 4529 endoff = 64; 4530 break; 4531 case 1: 4532 /* PCI-PCI bridge header */ 4533 type_name = "PCI-PCI bridge"; 4534 type_printfn = &pci_conf_print_type1; 4535 capoff = PCI_CAPLISTPTR_REG; 4536 endoff = 64; 4537 break; 4538 case 2: 4539 /* PCI-CardBus bridge header */ 4540 type_name = "PCI-CardBus bridge"; 4541 type_printfn = &pci_conf_print_type2; 4542 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 4543 endoff = 72; 4544 break; 4545 default: 4546 type_name = NULL; 4547 type_printfn = 0; 4548 capoff = -1; 4549 endoff = 64; 4550 break; 4551 } 4552 printf(" Type %d ", hdrtype); 4553 if (type_name != NULL) 4554 printf("(%s) ", type_name); 4555 printf("header:\n"); 4556 pci_conf_print_regs(regs, 16, endoff); 4557 printf("\n"); 4558 if (type_printfn) { 4559 #ifdef _KERNEL 4560 (*type_printfn)(pc, tag, regs); 4561 #else 4562 (*type_printfn)(regs); 4563 #endif 4564 } else 4565 printf(" Don't know how to pretty-print type %d header.\n", 4566 hdrtype); 4567 printf("\n"); 4568 4569 /* capability list, if present */ 4570 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4571 && (capoff > 0)) { 4572 #ifdef _KERNEL 4573 pci_conf_print_caplist(pc, tag, regs, capoff); 4574 #else 4575 pci_conf_print_caplist(regs, capoff); 4576 #endif 4577 printf("\n"); 4578 } 4579 4580 /* device-dependent header */ 4581 printf(" Device-dependent header:\n"); 4582 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 4583 printf("\n"); 4584 #ifdef _KERNEL 4585 if (printfn) 4586 (*printfn)(pc, tag, regs); 4587 else 4588 printf(" Don't know how to pretty-print device-dependent header.\n"); 4589 printf("\n"); 4590 #endif /* _KERNEL */ 4591 4592 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 4593 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 4594 return; 4595 4596 #ifdef _KERNEL 4597 pci_conf_print_extcaplist(pc, tag, regs, capoff); 4598 #else 4599 pci_conf_print_extcaplist(regs, capoff); 4600 #endif 4601 printf("\n"); 4602 4603 /* Extended Configuration Space, if present */ 4604 printf(" Extended Configuration Space:\n"); 4605 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 4606 } 4607
Indexes created Wed Sep 24 14:09:57 GMT 2025