pci_subr.c revision 1.192
1 /* $NetBSD: pci_subr.c,v 1.192 2017/10/10 03:11:01 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.192 2017/10/10 03:11:01 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdarg.h> 58 #include <stdbool.h> 59 #include <stdio.h> 60 #include <stdlib.h> 61 #include <string.h> 62 #endif 63 64 #include <dev/pci/pcireg.h> 65 #ifdef _KERNEL 66 #include <dev/pci/pcivar.h> 67 #else 68 #include <dev/pci/pci_verbose.h> 69 #include <dev/pci/pcidevs.h> 70 #include <dev/pci/pcidevs_data.h> 71 #endif 72 73 static int pci_conf_find_cap(const pcireg_t *, int, unsigned int, int *); 74 static void pci_conf_print_pcie_power(uint8_t, unsigned int); 75 76 /* 77 * Descriptions of known PCI classes and subclasses. 78 * 79 * Subclasses are described in the same way as classes, but have a 80 * NULL subclass pointer. 81 */ 82 struct pci_class { 83 const char *name; 84 u_int val; /* as wide as pci_{,sub}class_t */ 85 const struct pci_class *subclasses; 86 }; 87 88 /* 89 * Class 0x00. 90 * Before rev. 2.0. 91 */ 92 static const struct pci_class pci_subclass_prehistoric[] = { 93 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 94 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 95 { NULL, 0, NULL, }, 96 }; 97 98 /* 99 * Class 0x01. 100 * Mass storage controller 101 */ 102 103 /* ATA programming interface */ 104 static const struct pci_class pci_interface_ata[] = { 105 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 106 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 107 { NULL, 0, NULL, }, 108 }; 109 110 /* SATA programming interface */ 111 static const struct pci_class pci_interface_sata[] = { 112 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 113 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 114 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 115 { NULL, 0, NULL, }, 116 }; 117 118 /* Flash programming interface */ 119 static const struct pci_class pci_interface_nvm[] = { 120 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 121 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 122 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 123 { NULL, 0, NULL, }, 124 }; 125 126 /* Subclasses */ 127 static const struct pci_class pci_subclass_mass_storage[] = { 128 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 129 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 130 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 131 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 132 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 133 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 134 pci_interface_ata, }, 135 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 136 pci_interface_sata, }, 137 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 138 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 139 pci_interface_nvm, }, 140 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 141 { NULL, 0, NULL, }, 142 }; 143 144 /* 145 * Class 0x02. 146 * Network controller. 147 */ 148 static const struct pci_class pci_subclass_network[] = { 149 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 150 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 151 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 152 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 153 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 154 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 155 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 156 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 157 { NULL, 0, NULL, }, 158 }; 159 160 /* 161 * Class 0x03. 162 * Display controller. 163 */ 164 165 /* VGA programming interface */ 166 static const struct pci_class pci_interface_vga[] = { 167 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 168 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 169 { NULL, 0, NULL, }, 170 }; 171 /* Subclasses */ 172 static const struct pci_class pci_subclass_display[] = { 173 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 174 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 175 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 176 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 177 { NULL, 0, NULL, }, 178 }; 179 180 /* 181 * Class 0x04. 182 * Multimedia device. 183 */ 184 static const struct pci_class pci_subclass_multimedia[] = { 185 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 186 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 187 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 188 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 189 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 190 { NULL, 0, NULL, }, 191 }; 192 193 /* 194 * Class 0x05. 195 * Memory controller. 196 */ 197 static const struct pci_class pci_subclass_memory[] = { 198 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 199 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 200 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 201 { NULL, 0, NULL, }, 202 }; 203 204 /* 205 * Class 0x06. 206 * Bridge device. 207 */ 208 209 /* PCI bridge programming interface */ 210 static const struct pci_class pci_interface_pcibridge[] = { 211 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 212 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 213 { NULL, 0, NULL, }, 214 }; 215 216 /* Semi-transparent PCI-to-PCI bridge programming interface */ 217 static const struct pci_class pci_interface_stpci[] = { 218 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 219 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 220 { NULL, 0, NULL, }, 221 }; 222 223 /* Advanced Switching programming interface */ 224 static const struct pci_class pci_interface_advsw[] = { 225 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 226 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 227 { NULL, 0, NULL, }, 228 }; 229 230 /* Subclasses */ 231 static const struct pci_class pci_subclass_bridge[] = { 232 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 233 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 234 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 235 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 236 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 237 pci_interface_pcibridge, }, 238 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 239 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 240 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 241 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 242 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 243 pci_interface_stpci, }, 244 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 245 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 246 pci_interface_advsw, }, 247 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 248 { NULL, 0, NULL, }, 249 }; 250 251 /* 252 * Class 0x07. 253 * Simple communications controller. 254 */ 255 256 /* Serial controller programming interface */ 257 static const struct pci_class pci_interface_serial[] = { 258 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 259 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 260 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 261 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 262 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 263 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 264 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 265 { NULL, 0, NULL, }, 266 }; 267 268 /* Parallel controller programming interface */ 269 static const struct pci_class pci_interface_parallel[] = { 270 { "", PCI_INTERFACE_PARALLEL, NULL,}, 271 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 272 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 273 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 274 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 275 { NULL, 0, NULL,}, 276 }; 277 278 /* Modem programming interface */ 279 static const struct pci_class pci_interface_modem[] = { 280 { "", PCI_INTERFACE_MODEM, NULL,}, 281 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 282 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 283 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 284 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 285 { NULL, 0, NULL,}, 286 }; 287 288 /* Subclasses */ 289 static const struct pci_class pci_subclass_communications[] = { 290 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 291 pci_interface_serial, }, 292 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 293 pci_interface_parallel, }, 294 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 295 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 296 pci_interface_modem, }, 297 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 298 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 299 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 300 { NULL, 0, NULL,}, 301 }; 302 303 /* 304 * Class 0x08. 305 * Base system peripheral. 306 */ 307 308 /* PIC programming interface */ 309 static const struct pci_class pci_interface_pic[] = { 310 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 311 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 312 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 313 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 314 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 315 { NULL, 0, NULL, }, 316 }; 317 318 /* DMA programming interface */ 319 static const struct pci_class pci_interface_dma[] = { 320 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 321 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 322 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 323 { NULL, 0, NULL, }, 324 }; 325 326 /* Timer programming interface */ 327 static const struct pci_class pci_interface_tmr[] = { 328 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 329 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 330 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 331 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 332 { NULL, 0, NULL, }, 333 }; 334 335 /* RTC programming interface */ 336 static const struct pci_class pci_interface_rtc[] = { 337 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 338 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 339 { NULL, 0, NULL, }, 340 }; 341 342 /* Subclasses */ 343 static const struct pci_class pci_subclass_system[] = { 344 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 345 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 346 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 347 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 348 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 349 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 350 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 351 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 352 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 353 { NULL, 0, NULL, }, 354 }; 355 356 /* 357 * Class 0x09. 358 * Input device. 359 */ 360 361 /* Gameport programming interface */ 362 static const struct pci_class pci_interface_game[] = { 363 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 364 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 365 { NULL, 0, NULL, }, 366 }; 367 368 /* Subclasses */ 369 static const struct pci_class pci_subclass_input[] = { 370 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 371 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 372 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 373 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 374 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 375 pci_interface_game, }, 376 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 377 { NULL, 0, NULL, }, 378 }; 379 380 /* 381 * Class 0x0a. 382 * Docking station. 383 */ 384 static const struct pci_class pci_subclass_dock[] = { 385 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 386 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 387 { NULL, 0, NULL, }, 388 }; 389 390 /* 391 * Class 0x0b. 392 * Processor. 393 */ 394 static const struct pci_class pci_subclass_processor[] = { 395 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 396 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 397 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 398 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 399 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 400 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 401 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 402 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 403 { NULL, 0, NULL, }, 404 }; 405 406 /* 407 * Class 0x0c. 408 * Serial bus controller. 409 */ 410 411 /* IEEE1394 programming interface */ 412 static const struct pci_class pci_interface_ieee1394[] = { 413 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 414 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 415 { NULL, 0, NULL,}, 416 }; 417 418 /* USB programming interface */ 419 static const struct pci_class pci_interface_usb[] = { 420 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 421 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 422 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 423 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 424 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 425 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 426 { NULL, 0, NULL, }, 427 }; 428 429 /* IPMI programming interface */ 430 static const struct pci_class pci_interface_ipmi[] = { 431 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 432 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 433 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 434 { NULL, 0, NULL,}, 435 }; 436 437 /* Subclasses */ 438 static const struct pci_class pci_subclass_serialbus[] = { 439 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 440 pci_interface_ieee1394, }, 441 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 442 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 443 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 444 pci_interface_usb, }, 445 /* XXX Fiber Channel/_FIBRECHANNEL */ 446 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 447 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 448 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 449 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 450 pci_interface_ipmi, }, 451 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 452 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 453 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 454 { NULL, 0, NULL, }, 455 }; 456 457 /* 458 * Class 0x0d. 459 * Wireless Controller. 460 */ 461 static const struct pci_class pci_subclass_wireless[] = { 462 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 463 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 464 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 465 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 466 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 467 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 468 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 469 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 470 { NULL, 0, NULL, }, 471 }; 472 473 /* 474 * Class 0x0e. 475 * Intelligent IO controller. 476 */ 477 478 /* Intelligent IO programming interface */ 479 static const struct pci_class pci_interface_i2o[] = { 480 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 481 { NULL, 0, NULL,}, 482 }; 483 484 /* Subclasses */ 485 static const struct pci_class pci_subclass_i2o[] = { 486 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 487 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 488 { NULL, 0, NULL, }, 489 }; 490 491 /* 492 * Class 0x0f. 493 * Satellite communication controller. 494 */ 495 static const struct pci_class pci_subclass_satcom[] = { 496 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 497 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 498 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 499 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 500 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 501 { NULL, 0, NULL, }, 502 }; 503 504 /* 505 * Class 0x10. 506 * Encryption/Decryption controller. 507 */ 508 static const struct pci_class pci_subclass_crypto[] = { 509 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 510 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 511 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 512 { NULL, 0, NULL, }, 513 }; 514 515 /* 516 * Class 0x11. 517 * Data aquuisition and signal processing controller. 518 */ 519 static const struct pci_class pci_subclass_dasp[] = { 520 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 521 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 522 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 523 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 524 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 525 { NULL, 0, NULL, }, 526 }; 527 528 /* List of classes */ 529 static const struct pci_class pci_classes[] = { 530 { "prehistoric", PCI_CLASS_PREHISTORIC, 531 pci_subclass_prehistoric, }, 532 { "mass storage", PCI_CLASS_MASS_STORAGE, 533 pci_subclass_mass_storage, }, 534 { "network", PCI_CLASS_NETWORK, 535 pci_subclass_network, }, 536 { "display", PCI_CLASS_DISPLAY, 537 pci_subclass_display, }, 538 { "multimedia", PCI_CLASS_MULTIMEDIA, 539 pci_subclass_multimedia, }, 540 { "memory", PCI_CLASS_MEMORY, 541 pci_subclass_memory, }, 542 { "bridge", PCI_CLASS_BRIDGE, 543 pci_subclass_bridge, }, 544 { "communications", PCI_CLASS_COMMUNICATIONS, 545 pci_subclass_communications, }, 546 { "system", PCI_CLASS_SYSTEM, 547 pci_subclass_system, }, 548 { "input", PCI_CLASS_INPUT, 549 pci_subclass_input, }, 550 { "dock", PCI_CLASS_DOCK, 551 pci_subclass_dock, }, 552 { "processor", PCI_CLASS_PROCESSOR, 553 pci_subclass_processor, }, 554 { "serial bus", PCI_CLASS_SERIALBUS, 555 pci_subclass_serialbus, }, 556 { "wireless", PCI_CLASS_WIRELESS, 557 pci_subclass_wireless, }, 558 { "I2O", PCI_CLASS_I2O, 559 pci_subclass_i2o, }, 560 { "satellite comm", PCI_CLASS_SATCOM, 561 pci_subclass_satcom, }, 562 { "crypto", PCI_CLASS_CRYPTO, 563 pci_subclass_crypto, }, 564 { "DASP", PCI_CLASS_DASP, 565 pci_subclass_dasp, }, 566 { "processing accelerators", PCI_CLASS_ACCEL, 567 NULL, }, 568 { "non-essential instrumentation", PCI_CLASS_INSTRUMENT, 569 NULL, }, 570 { "undefined", PCI_CLASS_UNDEFINED, 571 NULL, }, 572 { NULL, 0, 573 NULL, }, 574 }; 575 576 DEV_VERBOSE_DEFINE(pci); 577 578 /* 579 * Append a formatted string to dest without writing more than len 580 * characters (including the trailing NUL character). dest and len 581 * are updated for use in subsequent calls to snappendf(). 582 * 583 * Returns 0 on success, a negative value if vnsprintf() fails, or 584 * a positive value if the dest buffer would have overflowed. 585 */ 586 587 static int __printflike(3,4) 588 snappendf(char **dest, size_t *len, const char * restrict fmt, ...) 589 { 590 va_list ap; 591 int count; 592 593 va_start(ap, fmt); 594 count = vsnprintf(*dest, *len, fmt, ap); 595 va_end(ap); 596 597 /* Let vsnprintf() errors bubble up to caller */ 598 if (count < 0 || *len == 0) 599 return count; 600 601 /* Handle overflow */ 602 if ((size_t)count >= *len) { 603 *dest += *len - 1; 604 *len = 1; 605 return 1; 606 } 607 608 /* Update dest & len to point at trailing NUL */ 609 *dest += count; 610 *len -= count; 611 612 return 0; 613 } 614 615 void 616 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 617 size_t l) 618 { 619 pci_class_t class; 620 pci_subclass_t subclass; 621 pci_interface_t interface; 622 pci_revision_t revision; 623 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 624 const struct pci_class *classp, *subclassp, *interfacep; 625 626 class = PCI_CLASS(class_reg); 627 subclass = PCI_SUBCLASS(class_reg); 628 interface = PCI_INTERFACE(class_reg); 629 revision = PCI_REVISION(class_reg); 630 631 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 632 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 633 PCI_PRODUCT(id_reg)); 634 635 classp = pci_classes; 636 while (classp->name != NULL) { 637 if (class == classp->val) 638 break; 639 classp++; 640 } 641 642 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 643 while (subclassp && subclassp->name != NULL) { 644 if (subclass == subclassp->val) 645 break; 646 subclassp++; 647 } 648 649 interfacep = (subclassp && subclassp->name != NULL) ? 650 subclassp->subclasses : NULL; 651 while (interfacep && interfacep->name != NULL) { 652 if (interface == interfacep->val) 653 break; 654 interfacep++; 655 } 656 657 (void)snappendf(&cp, &l, "%s %s", vendor, product); 658 if (showclass) { 659 (void)snappendf(&cp, &l, " ("); 660 if (classp->name == NULL) 661 (void)snappendf(&cp, &l, 662 "class 0x%02x, subclass 0x%02x", 663 class, subclass); 664 else { 665 if (subclassp == NULL || subclassp->name == NULL) 666 (void)snappendf(&cp, &l, 667 "%s, subclass 0x%02x", 668 classp->name, subclass); 669 else 670 (void)snappendf(&cp, &l, "%s %s", 671 subclassp->name, classp->name); 672 } 673 if ((interfacep == NULL) || (interfacep->name == NULL)) { 674 if (interface != 0) 675 (void)snappendf(&cp, &l, ", interface 0x%02x", 676 interface); 677 } else if (strncmp(interfacep->name, "", 1) != 0) 678 (void)snappendf(&cp, &l, ", %s", interfacep->name); 679 if (revision != 0) 680 (void)snappendf(&cp, &l, ", revision 0x%02x", revision); 681 (void)snappendf(&cp, &l, ")"); 682 } 683 } 684 685 #ifdef _KERNEL 686 void 687 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 688 const char *known, int addrev) 689 { 690 char devinfo[256]; 691 692 if (known) { 693 aprint_normal(": %s", known); 694 if (addrev) 695 aprint_normal(" (rev. 0x%02x)", 696 PCI_REVISION(pa->pa_class)); 697 aprint_normal("\n"); 698 } else { 699 pci_devinfo(pa->pa_id, pa->pa_class, 0, 700 devinfo, sizeof(devinfo)); 701 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 702 PCI_REVISION(pa->pa_class)); 703 } 704 if (naive) 705 aprint_naive(": %s\n", naive); 706 else 707 aprint_naive("\n"); 708 } 709 #endif 710 711 /* 712 * Print out most of the PCI configuration registers. Typically used 713 * in a device attach routine like this: 714 * 715 * #ifdef MYDEV_DEBUG 716 * printf("%s: ", device_xname(sc->sc_dev)); 717 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 718 * #endif 719 */ 720 721 #define i2o(i) ((i) * 4) 722 #define o2i(o) ((o) / 4) 723 #define onoff2(str, rval, bit, onstr, offstr) \ 724 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 725 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 726 727 static void 728 pci_conf_print_common( 729 #ifdef _KERNEL 730 pci_chipset_tag_t pc, pcitag_t tag, 731 #endif 732 const pcireg_t *regs) 733 { 734 pci_class_t class; 735 pci_subclass_t subclass; 736 pci_interface_t interface; 737 pci_revision_t revision; 738 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 739 const struct pci_class *classp, *subclassp, *interfacep; 740 const char *name; 741 pcireg_t rval; 742 unsigned int num; 743 744 rval = regs[o2i(PCI_CLASS_REG)]; 745 class = PCI_CLASS(rval); 746 subclass = PCI_SUBCLASS(rval); 747 interface = PCI_INTERFACE(rval); 748 revision = PCI_REVISION(rval); 749 750 rval = regs[o2i(PCI_ID_REG)]; 751 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 752 if (name) 753 printf(" Vendor Name: %s (0x%04x)\n", name, 754 PCI_VENDOR(rval)); 755 else 756 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 757 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 758 PCI_PRODUCT(rval)); 759 if (name) 760 printf(" Device Name: %s (0x%04x)\n", name, 761 PCI_PRODUCT(rval)); 762 else 763 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 764 765 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 766 767 printf(" Command register: 0x%04x\n", rval & 0xffff); 768 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 769 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 770 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 771 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 772 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 773 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 774 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 775 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 776 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 777 onoff("Fast back-to-back transactions", rval, 778 PCI_COMMAND_BACKTOBACK_ENABLE); 779 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 780 781 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 782 onoff("Immediate Readiness", rval, PCI_STATUS_IMMD_READNESS); 783 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 784 "inactive"); 785 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 786 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 787 onoff("User Definable Features (UDF) support", rval, 788 PCI_STATUS_UDF_SUPPORT); 789 onoff("Fast back-to-back capable", rval, 790 PCI_STATUS_BACKTOBACK_SUPPORT); 791 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 792 793 printf(" DEVSEL timing: "); 794 switch (rval & PCI_STATUS_DEVSEL_MASK) { 795 case PCI_STATUS_DEVSEL_FAST: 796 printf("fast"); 797 break; 798 case PCI_STATUS_DEVSEL_MEDIUM: 799 printf("medium"); 800 break; 801 case PCI_STATUS_DEVSEL_SLOW: 802 printf("slow"); 803 break; 804 default: 805 printf("unknown/reserved"); /* XXX */ 806 break; 807 } 808 printf(" (0x%x)\n", __SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK)); 809 810 onoff("Slave signaled Target Abort", rval, 811 PCI_STATUS_TARGET_TARGET_ABORT); 812 onoff("Master received Target Abort", rval, 813 PCI_STATUS_MASTER_TARGET_ABORT); 814 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 815 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 816 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 817 818 rval = regs[o2i(PCI_CLASS_REG)]; 819 for (classp = pci_classes; classp->name != NULL; classp++) { 820 if (class == classp->val) 821 break; 822 } 823 824 /* 825 * ECN: Change Root Complex Event Collector Class Code 826 * Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type 827 * in PCIe extend capability to know whether it's RCEC or IOMMU. 828 */ 829 if ((class == PCI_CLASS_SYSTEM) 830 && (subclass == PCI_SUBCLASS_SYSTEM_IOMMU)) { 831 int pcie_capoff; 832 pcireg_t reg; 833 834 if (pci_conf_find_cap(regs, PCI_CAPLISTPTR_REG, 835 PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 836 reg = regs[o2i(pcie_capoff + PCIE_XCAP)]; 837 if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_ROOT_EVNTC) 838 subclass = PCI_SUBCLASS_SYSTEM_RCEC; 839 } 840 } 841 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 842 while (subclassp && subclassp->name != NULL) { 843 if (subclass == subclassp->val) 844 break; 845 subclassp++; 846 } 847 848 interfacep = (subclassp && subclassp->name != NULL) ? 849 subclassp->subclasses : NULL; 850 while (interfacep && interfacep->name != NULL) { 851 if (interface == interfacep->val) 852 break; 853 interfacep++; 854 } 855 856 if (classp->name != NULL) 857 printf(" Class Name: %s (0x%02x)\n", classp->name, class); 858 else 859 printf(" Class ID: 0x%02x\n", class); 860 if (subclassp != NULL && subclassp->name != NULL) 861 printf(" Subclass Name: %s (0x%02x)\n", 862 subclassp->name, PCI_SUBCLASS(rval)); 863 else 864 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 865 if ((interfacep != NULL) && (interfacep->name != NULL) 866 && (strncmp(interfacep->name, "", 1) != 0)) 867 printf(" Interface Name: %s (0x%02x)\n", 868 interfacep->name, interface); 869 else 870 printf(" Interface: 0x%02x\n", interface); 871 printf(" Revision ID: 0x%02x\n", revision); 872 873 rval = regs[o2i(PCI_BHLC_REG)]; 874 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 875 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 876 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 877 PCI_HDRTYPE(rval)); 878 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 879 num = PCI_CACHELINE(rval); 880 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 881 } 882 883 static int 884 pci_conf_print_bar( 885 #ifdef _KERNEL 886 pci_chipset_tag_t pc, pcitag_t tag, 887 #endif 888 const pcireg_t *regs, int reg, const char *name) 889 { 890 int width; 891 pcireg_t rval, rval64h; 892 bool ioen, memen; 893 #ifdef _KERNEL 894 pcireg_t mask, mask64h = 0; 895 #endif 896 897 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 898 ioen = rval & PCI_COMMAND_IO_ENABLE; 899 memen = rval & PCI_COMMAND_MEM_ENABLE; 900 901 width = 4; 902 /* 903 * Section 6.2.5.1, `Address Maps', tells us that: 904 * 905 * 1) The builtin software should have already mapped the 906 * device in a reasonable way. 907 * 908 * 2) A device which wants 2^n bytes of memory will hardwire 909 * the bottom n bits of the address to 0. As recommended, 910 * we write all 1s and see what we get back. 911 */ 912 913 rval = regs[o2i(reg)]; 914 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 915 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 916 rval64h = regs[o2i(reg + 4)]; 917 width = 8; 918 } else 919 rval64h = 0; 920 921 #ifdef _KERNEL 922 if (rval != 0 && memen) { 923 int s; 924 925 /* 926 * The following sequence seems to make some devices 927 * (e.g. host bus bridges, which don't normally 928 * have their space mapped) very unhappy, to 929 * the point of crashing the system. 930 * 931 * Therefore, if the mapping register is zero to 932 * start out with, don't bother trying. 933 */ 934 s = splhigh(); 935 pci_conf_write(pc, tag, reg, 0xffffffff); 936 mask = pci_conf_read(pc, tag, reg); 937 pci_conf_write(pc, tag, reg, rval); 938 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 939 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 940 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 941 mask64h = pci_conf_read(pc, tag, reg + 4); 942 pci_conf_write(pc, tag, reg + 4, rval64h); 943 } 944 splx(s); 945 } else 946 mask = mask64h = 0; 947 #endif /* _KERNEL */ 948 949 printf(" Base address register at 0x%02x", reg); 950 if (name) 951 printf(" (%s)", name); 952 printf("\n "); 953 if (rval == 0) { 954 printf("not implemented\n"); 955 return width; 956 } 957 printf("type: "); 958 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 959 const char *type, *prefetch; 960 961 switch (PCI_MAPREG_MEM_TYPE(rval)) { 962 case PCI_MAPREG_MEM_TYPE_32BIT: 963 type = "32-bit"; 964 break; 965 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 966 type = "32-bit-1M"; 967 break; 968 case PCI_MAPREG_MEM_TYPE_64BIT: 969 type = "64-bit"; 970 break; 971 default: 972 type = "unknown (XXX)"; 973 break; 974 } 975 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 976 prefetch = ""; 977 else 978 prefetch = "non"; 979 printf("%s %sprefetchable memory\n", type, prefetch); 980 switch (PCI_MAPREG_MEM_TYPE(rval)) { 981 case PCI_MAPREG_MEM_TYPE_64BIT: 982 printf(" base: 0x%016llx", 983 PCI_MAPREG_MEM64_ADDR( 984 ((((long long) rval64h) << 32) | rval))); 985 if (!memen) 986 printf(", disabled"); 987 printf("\n"); 988 #ifdef _KERNEL 989 printf(" size: 0x%016llx\n", 990 PCI_MAPREG_MEM64_SIZE( 991 ((((long long) mask64h) << 32) | mask))); 992 #endif 993 break; 994 case PCI_MAPREG_MEM_TYPE_32BIT: 995 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 996 default: 997 printf(" base: 0x%08x", 998 PCI_MAPREG_MEM_ADDR(rval)); 999 if (!memen) 1000 printf(", disabled"); 1001 printf("\n"); 1002 #ifdef _KERNEL 1003 printf(" size: 0x%08x\n", 1004 PCI_MAPREG_MEM_SIZE(mask)); 1005 #endif 1006 break; 1007 } 1008 } else { 1009 #ifdef _KERNEL 1010 if (ioen) 1011 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 1012 #endif 1013 printf("I/O\n"); 1014 printf(" base: 0x%08x", PCI_MAPREG_IO_ADDR(rval)); 1015 if (!ioen) 1016 printf(", disabled"); 1017 printf("\n"); 1018 #ifdef _KERNEL 1019 printf(" size: 0x%08x\n", PCI_MAPREG_IO_SIZE(mask)); 1020 #endif 1021 } 1022 1023 return width; 1024 } 1025 1026 static void 1027 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 1028 { 1029 int off, needaddr, neednl; 1030 1031 needaddr = 1; 1032 neednl = 0; 1033 for (off = first; off < pastlast; off += 4) { 1034 if ((off % 16) == 0 || needaddr) { 1035 printf(" 0x%02x:", off); 1036 needaddr = 0; 1037 } 1038 printf(" 0x%08x", regs[o2i(off)]); 1039 neednl = 1; 1040 if ((off % 16) == 12) { 1041 printf("\n"); 1042 neednl = 0; 1043 } 1044 } 1045 if (neednl) 1046 printf("\n"); 1047 } 1048 1049 static const char * 1050 pci_conf_print_agp_calcycle(uint8_t cal) 1051 { 1052 1053 switch (cal) { 1054 case 0x0: 1055 return "4ms"; 1056 case 0x1: 1057 return "16ms"; 1058 case 0x2: 1059 return "64ms"; 1060 case 0x3: 1061 return "256ms"; 1062 case 0x7: 1063 return "Calibration Cycle Not Needed"; 1064 default: 1065 return "(reserved)"; 1066 } 1067 } 1068 1069 static void 1070 pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3) 1071 { 1072 if (isagp3) { 1073 /* AGP 3.0 */ 1074 if (reg & AGP_MODE_V3_RATE_4x) 1075 printf("x4"); 1076 if (reg & AGP_MODE_V3_RATE_8x) 1077 printf("x8"); 1078 } else { 1079 /* AGP 2.0 */ 1080 if (reg & AGP_MODE_V2_RATE_1x) 1081 printf("x1"); 1082 if (reg & AGP_MODE_V2_RATE_2x) 1083 printf("x2"); 1084 if (reg & AGP_MODE_V2_RATE_4x) 1085 printf("x4"); 1086 } 1087 printf("\n"); 1088 } 1089 1090 static void 1091 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1092 { 1093 pcireg_t rval; 1094 bool isagp3; 1095 1096 printf("\n AGP Capabilities Register\n"); 1097 1098 rval = regs[o2i(capoff)]; 1099 printf(" Revision: %d.%d\n", 1100 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1101 1102 rval = regs[o2i(capoff + PCI_AGP_STATUS)]; 1103 printf(" Status register: 0x%04x\n", rval); 1104 printf(" RQ: %d\n", 1105 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1106 printf(" ARQSZ: %d\n", 1107 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1108 printf(" CAL cycle: %s\n", 1109 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1110 onoff("SBA", rval, AGP_MODE_SBA); 1111 onoff("htrans#", rval, AGP_MODE_HTRANS); 1112 onoff("Over 4G", rval, AGP_MODE_4G); 1113 onoff("Fast Write", rval, AGP_MODE_FW); 1114 onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3); 1115 isagp3 = rval & AGP_MODE_MODE_3; 1116 printf(" Data Rate Support: "); 1117 pci_conf_print_agp_datarate(rval, isagp3); 1118 1119 rval = regs[o2i(capoff + PCI_AGP_COMMAND)]; 1120 printf(" Command register: 0x%08x\n", rval); 1121 printf(" PRQ: %d\n", 1122 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1123 printf(" PARQSZ: %d\n", 1124 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1125 printf(" PCAL cycle: %s\n", 1126 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1127 onoff("SBA", rval, AGP_MODE_SBA); 1128 onoff("AGP", rval, AGP_MODE_AGP); 1129 onoff("Over 4G", rval, AGP_MODE_4G); 1130 onoff("Fast Write", rval, AGP_MODE_FW); 1131 if (isagp3) { 1132 printf(" Data Rate Enable: "); 1133 /* 1134 * The Data Rate Enable bits are used only on 3.0 and the 1135 * Command register has no AGP_MODE_MODE_3 bit, so pass the 1136 * flag to print correctly. 1137 */ 1138 pci_conf_print_agp_datarate(rval, isagp3); 1139 } 1140 } 1141 1142 static const char * 1143 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1144 { 1145 1146 switch ((caps >> 6) & 7) { 1147 case 0: return "self-powered"; 1148 case 1: return "55 mA"; 1149 case 2: return "100 mA"; 1150 case 3: return "160 mA"; 1151 case 4: return "220 mA"; 1152 case 5: return "270 mA"; 1153 case 6: return "320 mA"; 1154 case 7: 1155 default: return "375 mA"; 1156 } 1157 } 1158 1159 static const char * 1160 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1161 { 1162 static const char unk[] = "unknown"; 1163 static const char *pmrev[8] = { 1164 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1165 }; 1166 if (val > 7) 1167 return unk; 1168 return pmrev[val]; 1169 } 1170 1171 static void 1172 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1173 { 1174 uint16_t caps, pmcsr; 1175 pcireg_t reg; 1176 1177 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1178 reg = regs[o2i(capoff + PCI_PMCSR)]; 1179 pmcsr = reg & 0xffff; 1180 1181 printf("\n PCI Power Management Capabilities Register\n"); 1182 1183 printf(" Capabilities register: 0x%04x\n", caps); 1184 printf(" Version: %s\n", 1185 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1186 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1187 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1188 printf(" 3.3V auxiliary current: %s\n", 1189 pci_conf_print_pcipm_cap_aux(caps)); 1190 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1191 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1192 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1193 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1194 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1195 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1196 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1197 1198 printf(" Control/status register: 0x%04x\n", pmcsr); 1199 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1200 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1201 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1202 printf(" PME# assertion: %sabled\n", 1203 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1204 printf(" Data Select: %d\n", 1205 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK)); 1206 printf(" Data Scale: %d\n", 1207 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK)); 1208 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1209 printf(" Bridge Support Extensions register: 0x%02x\n", 1210 (reg >> 16) & 0xff); 1211 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1212 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1213 printf(" Data register: 0x%02x\n", __SHIFTOUT(reg, PCI_PMCSR_DATA)); 1214 1215 } 1216 1217 /* XXX pci_conf_print_vpd_cap */ 1218 /* XXX pci_conf_print_slotid_cap */ 1219 1220 static void 1221 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1222 { 1223 uint32_t ctl, mmc, mme; 1224 1225 regs += o2i(capoff); 1226 ctl = *regs++; 1227 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1228 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1229 1230 printf("\n PCI Message Signaled Interrupt\n"); 1231 1232 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1233 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1234 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1235 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1236 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1237 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1238 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1239 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1240 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP); 1241 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN); 1242 printf(" Message Address %sregister: 0x%08x\n", 1243 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1244 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1245 printf(" Message Address %sregister: 0x%08x\n", 1246 "(upper) ", *regs++); 1247 } 1248 printf(" Message Data register: "); 1249 if (ctl & PCI_MSI_CTL_EXTMDATA_CAP) 1250 printf("0x%08x\n", *regs); 1251 else 1252 printf("0x%04x\n", *regs & 0xffff); 1253 regs++; 1254 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1255 printf(" Vector Mask register: 0x%08x\n", *regs++); 1256 printf(" Vector Pending register: 0x%08x\n", *regs++); 1257 } 1258 } 1259 1260 /* XXX pci_conf_print_cpci_hostwap_cap */ 1261 1262 /* 1263 * For both command register and status register. 1264 * The argument "idx" is index number (0 to 7). 1265 */ 1266 static int 1267 pcix_split_trans(unsigned int idx) 1268 { 1269 static int table[8] = { 1270 1, 2, 3, 4, 8, 12, 16, 32 1271 }; 1272 1273 if (idx >= __arraycount(table)) 1274 return -1; 1275 return table[idx]; 1276 } 1277 1278 static void 1279 pci_conf_print_pcix_cap_2ndbusmode(int num) 1280 { 1281 const char *maxfreq, *maxperiod; 1282 1283 printf(" Mode: "); 1284 if (num <= 0x07) 1285 printf("PCI-X Mode 1\n"); 1286 else if (num <= 0x0b) 1287 printf("PCI-X 266 (Mode 2)\n"); 1288 else 1289 printf("PCI-X 533 (Mode 2)\n"); 1290 1291 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1292 switch (num & 0x03) { 1293 default: 1294 case 0: 1295 maxfreq = "N/A"; 1296 maxperiod = "N/A"; 1297 break; 1298 case 1: 1299 maxfreq = "66MHz"; 1300 maxperiod = "15ns"; 1301 break; 1302 case 2: 1303 maxfreq = "100MHz"; 1304 maxperiod = "10ns"; 1305 break; 1306 case 3: 1307 maxfreq = "133MHz"; 1308 maxperiod = "7.5ns"; 1309 break; 1310 } 1311 printf(" Max Clock Freq: %s\n", maxfreq); 1312 printf(" Min Clock Period: %s\n", maxperiod); 1313 } 1314 1315 static void 1316 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1317 { 1318 pcireg_t reg; 1319 int isbridge; 1320 int i; 1321 1322 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1323 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1324 printf("\n PCI-X %s Capabilities Register\n", 1325 isbridge ? "Bridge" : "Non-bridge"); 1326 1327 reg = regs[o2i(capoff)]; 1328 if (isbridge != 0) { 1329 printf(" Secondary status register: 0x%04x\n", 1330 (reg & 0xffff0000) >> 16); 1331 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1332 onoff("133MHz capable", reg, PCIX_STATUS_133); 1333 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1334 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1335 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1336 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1337 pci_conf_print_pcix_cap_2ndbusmode( 1338 __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1339 printf(" Version: 0x%x\n", 1340 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1341 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1342 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1343 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1344 } else { 1345 printf(" Command register: 0x%04x\n", 1346 (reg & 0xffff0000) >> 16); 1347 onoff("Data Parity Error Recovery", reg, 1348 PCIX_CMD_PERR_RECOVER); 1349 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1350 printf(" Maximum Burst Read Count: %u\n", 1351 PCIX_CMD_BYTECNT(reg)); 1352 printf(" Maximum Split Transactions: %d\n", 1353 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1354 >> PCIX_CMD_SPLTRANS_SHIFT)); 1355 } 1356 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1357 printf(" %sStatus register: 0x%08x\n", 1358 isbridge ? "Bridge " : "", reg); 1359 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1360 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1361 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1362 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1363 onoff("133MHz capable", reg, PCIX_STATUS_133); 1364 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1365 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1366 if (isbridge != 0) { 1367 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1368 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1369 } else { 1370 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1371 "bridge device", "simple device"); 1372 printf(" Designed max memory read byte count: %d\n", 1373 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1374 >> PCIX_STATUS_MAXB_SHIFT)); 1375 printf(" Designed max outstanding split transaction: %d\n", 1376 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1377 >> PCIX_STATUS_MAXST_SHIFT)); 1378 printf(" MAX cumulative Read Size: %u\n", 1379 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1380 onoff("Received split completion error", reg, 1381 PCIX_STATUS_SCERR); 1382 } 1383 onoff("266MHz capable", reg, PCIX_STATUS_266); 1384 onoff("533MHz capable", reg, PCIX_STATUS_533); 1385 1386 if (isbridge == 0) 1387 return; 1388 1389 /* Only for bridge */ 1390 for (i = 0; i < 2; i++) { 1391 reg = regs[o2i(capoff + PCIX_BRIDGE_UP_STCR + (4 * i))]; 1392 printf(" %s split transaction control register: 0x%08x\n", 1393 (i == 0) ? "Upstream" : "Downstream", reg); 1394 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1395 printf(" Commitment Limit: %d\n", 1396 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1397 } 1398 } 1399 1400 /* pci_conf_print_ht_slave_cap */ 1401 /* pci_conf_print_ht_host_cap */ 1402 /* pci_conf_print_ht_switch_cap */ 1403 /* pci_conf_print_ht_intr_cap */ 1404 /* pci_conf_print_ht_revid_cap */ 1405 /* pci_conf_print_ht_unitid_cap */ 1406 /* pci_conf_print_ht_extcnf_cap */ 1407 /* pci_conf_print_ht_addrmap_cap */ 1408 /* pci_conf_print_ht_msimap_cap */ 1409 1410 static void 1411 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1412 { 1413 pcireg_t val; 1414 uint32_t lo, hi; 1415 1416 /* 1417 * Print the rest of the command register bits. Others are 1418 * printed in pci_conf_print_ht_cap(). 1419 */ 1420 val = regs[o2i(capoff + PCI_HT_CMD)]; 1421 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1422 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1423 1424 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1425 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1426 printf(" Address Low register: 0x%08x\n", lo); 1427 printf(" Address high register: 0x%08x\n", hi); 1428 printf(" Address: 0x%016" PRIx64 "\n", 1429 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1430 } 1431 1432 /* pci_conf_print_ht_droute_cap */ 1433 /* pci_conf_print_ht_vcset_cap */ 1434 /* pci_conf_print_ht_retry_cap */ 1435 /* pci_conf_print_ht_x86enc_cap */ 1436 /* pci_conf_print_ht_gen3_cap */ 1437 /* pci_conf_print_ht_fle_cap */ 1438 /* pci_conf_print_ht_pm_cap */ 1439 /* pci_conf_print_ht_hnc_cap */ 1440 1441 static const struct ht_types { 1442 pcireg_t cap; 1443 const char *name; 1444 void (*printfunc)(const pcireg_t *, int); 1445 } ht_captab[] = { 1446 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1447 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1448 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1449 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1450 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1451 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1452 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1453 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1454 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1455 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1456 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1457 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1458 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1459 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1460 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1461 {PCI_HT_CAP_PM, "Power Management", NULL }, 1462 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1463 }; 1464 1465 static void 1466 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1467 { 1468 pcireg_t val, foundcap; 1469 unsigned int off; 1470 1471 val = regs[o2i(capoff + PCI_HT_CMD)]; 1472 1473 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1474 1475 printf(" Command register: 0x%04x\n", val >> 16); 1476 foundcap = PCI_HT_CAP(val); 1477 for (off = 0; off < __arraycount(ht_captab); off++) { 1478 if (ht_captab[off].cap == foundcap) 1479 break; 1480 } 1481 printf(" Capability Type: 0x%02x ", foundcap); 1482 if (off >= __arraycount(ht_captab)) { 1483 printf("(unknown)\n"); 1484 return; 1485 } 1486 printf("(%s)\n", ht_captab[off].name); 1487 if (ht_captab[off].printfunc != NULL) 1488 ht_captab[off].printfunc(regs, capoff); 1489 } 1490 1491 static void 1492 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1493 { 1494 uint16_t caps; 1495 1496 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1497 1498 printf("\n PCI Vendor Specific Capabilities Register\n"); 1499 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1500 } 1501 1502 static void 1503 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1504 { 1505 pcireg_t val; 1506 1507 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1508 1509 printf("\n Debugport Capability Register\n"); 1510 printf(" Debug base Register: 0x%04x\n", 1511 val >> PCI_DEBUG_BASER_SHIFT); 1512 printf(" port offset: 0x%04x\n", 1513 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1514 printf(" BAR number: %u\n", 1515 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1516 } 1517 1518 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1519 /* XXX pci_conf_print_hotplug_cap */ 1520 1521 static void 1522 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1523 { 1524 pcireg_t reg; 1525 1526 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1527 1528 printf("\n Subsystem ID Capability Register\n"); 1529 printf(" Subsystem ID : 0x%08x\n", reg); 1530 } 1531 1532 /* XXX pci_conf_print_agp8_cap */ 1533 static void 1534 pci_conf_print_secure_cap(const pcireg_t *regs, int capoff) 1535 { 1536 pcireg_t reg, reg2, val; 1537 bool havemisc1; 1538 1539 printf("\n Secure Capability Register\n"); 1540 reg = regs[o2i(capoff + PCI_SECURE_CAP)]; 1541 val = __SHIFTOUT(reg, PCI_SECURE_CAP_TYPE); 1542 printf(" Capability block type: "); 1543 /* I know IOMMU Only */ 1544 if (val == PCI_SECURE_CAP_TYPE_IOMMU) 1545 printf("IOMMU\n"); 1546 else { 1547 printf("0x%x(unknown)\n", val); 1548 return; 1549 } 1550 1551 val = __SHIFTOUT(reg, PCI_SECURE_CAP_REV); 1552 printf(" Capability revision: 0x%02x", val); 1553 if (val == PCI_SECURE_CAP_REV_IOMMU) 1554 printf("IOMMU\n"); 1555 else { 1556 printf("(unknown)\n"); 1557 return; 1558 } 1559 onoff("IOTLB support", reg, PCI_SECURE_CAP_IOTLBSUP); 1560 onoff("HyperTransport tunnel translation support", reg, 1561 PCI_SECURE_CAP_HTTUNNEL); 1562 onoff("Not present table entries cahced", reg, PCI_SECURE_CAP_NPCACHE); 1563 onoff("IOMMU Extended Feature Register support", reg, 1564 PCI_SECURE_CAP_EFRSUP); 1565 onoff("IOMMU Miscellaneous Information Register 1", reg, 1566 PCI_SECURE_CAP_EXT); 1567 havemisc1 = reg & PCI_SECURE_CAP_EXT; 1568 1569 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_BAL)]; 1570 printf(" Base Address Low Register: 0x%08x\n", reg); 1571 onoff("Enable", reg, PCI_SECURE_IOMMU_BAL_EN); 1572 reg2 = regs[o2i(capoff + PCI_SECURE_IOMMU_BAH)]; 1573 printf(" Base Address High Register: 0x%08x\n", reg2); 1574 printf(" Base Address : 0x%016" PRIx64 "\n", 1575 ((uint64_t)reg2 << 32) 1576 | (reg & (PCI_SECURE_IOMMU_BAL_H | PCI_SECURE_IOMMU_BAL_L))); 1577 1578 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_RANGE)]; 1579 printf(" IOMMU Range Register: 0x%08x\n", reg); 1580 printf(" HyperTransport UnitID: 0x%02x\n", 1581 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_UNITID)); 1582 onoff("Range valid", reg, PCI_SECURE_IOMMU_RANGE_RNGVALID); 1583 printf(" Device range bus number: 0x%02x\n", 1584 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_BUSNUM)); 1585 printf(" First device: 0x%04x\n", 1586 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_FIRSTDEV)); 1587 printf(" Last device: 0x%04x\n", 1588 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_LASTDEV)); 1589 1590 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC0)]; 1591 printf(" Miscellaneous Information Register 0: 0x%08x\n", reg); 1592 printf(" MSI Message number: 0x%04x\n", 1593 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MSINUM)); 1594 val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_GVASIZE); 1595 printf(" Guest Virtual Address size: "); 1596 if (val == PCI_SECURE_IOMMU_MISC0_GVASIZE_48B) 1597 printf("48bits\n"); 1598 else 1599 printf("0x%x(unknown)\n", val); 1600 val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_PASIZE); 1601 printf(" Physical Address size: %dbits\n", val); 1602 val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_VASIZE); 1603 printf(" Virtual Address size: %dbits\n", val); 1604 onoff("ATS response address range reserved", reg, 1605 PCI_SECURE_IOMMU_MISC0_ATSRESV); 1606 printf(" Peripheral Page Request MSI Message number: 0x%02x\n", 1607 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MISNPPR)); 1608 1609 if (!havemisc1) 1610 return; 1611 1612 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC1)]; 1613 printf(" Miscellaneous Information Register 1: 0x%08x\n", reg); 1614 printf(" MSI Message number (GA): 0x%02x\n", 1615 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC1_MSINUM)); 1616 } 1617 1618 static void 1619 pci_print_pcie_L0s_latency(uint32_t val) 1620 { 1621 1622 switch (val) { 1623 case 0x0: 1624 printf("Less than 64ns\n"); 1625 break; 1626 case 0x1: 1627 case 0x2: 1628 case 0x3: 1629 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1630 break; 1631 case 0x4: 1632 printf("512ns to less than 1us\n"); 1633 break; 1634 case 0x5: 1635 printf("1us to less than 2us\n"); 1636 break; 1637 case 0x6: 1638 printf("2us - 4us\n"); 1639 break; 1640 case 0x7: 1641 printf("More than 4us\n"); 1642 break; 1643 } 1644 } 1645 1646 static void 1647 pci_print_pcie_L1_latency(uint32_t val) 1648 { 1649 1650 switch (val) { 1651 case 0x0: 1652 printf("Less than 1us\n"); 1653 break; 1654 case 0x6: 1655 printf("32us - 64us\n"); 1656 break; 1657 case 0x7: 1658 printf("More than 64us\n"); 1659 break; 1660 default: 1661 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1662 break; 1663 } 1664 } 1665 1666 static void 1667 pci_print_pcie_compl_timeout(uint32_t val) 1668 { 1669 1670 switch (val) { 1671 case 0x0: 1672 printf("50us to 50ms\n"); 1673 break; 1674 case 0x5: 1675 printf("16ms to 55ms\n"); 1676 break; 1677 case 0x6: 1678 printf("65ms to 210ms\n"); 1679 break; 1680 case 0x9: 1681 printf("260ms to 900ms\n"); 1682 break; 1683 case 0xa: 1684 printf("1s to 3.5s\n"); 1685 break; 1686 default: 1687 printf("unknown %u value\n", val); 1688 break; 1689 } 1690 } 1691 1692 static const char * const pcie_linkspeeds[] = {"2.5", "5.0", "8.0"}; 1693 1694 /* 1695 * Print link speed. This function is used for the following register bits: 1696 * Maximum Link Speed in LCAP 1697 * Current Link Speed in LCSR 1698 * Target Link Speed in LCSR2 1699 * All of above bitfield's values start from 1. 1700 * For LCSR2, 0 is allowed for a device which supports 2.5GT/s only (and 1701 * this check also works for devices which compliant to versions of the base 1702 * specification prior to 3.0. 1703 */ 1704 static void 1705 pci_print_pcie_linkspeed(int regnum, pcireg_t val) 1706 { 1707 1708 if ((regnum == PCIE_LCSR2) && (val == 0)) 1709 printf("2.5GT/s\n"); 1710 else if ((val < 1) || (val > __arraycount(pcie_linkspeeds))) 1711 printf("unknown value (%u)\n", val); 1712 else 1713 printf("%sGT/s\n", pcie_linkspeeds[val - 1]); 1714 } 1715 1716 /* 1717 * Print link speed "vector". 1718 * This function is used for the following register bits: 1719 * Supported Link Speeds Vector in LCAP2 1720 * Lower SKP OS Generation Supported Speed Vector in LCAP2 1721 * Lower SKP OS Reception Supported Speed Vector in LCAP2 1722 * Enable Lower SKP OS Generation Vector in LCTL3 1723 * All of above bitfield's values start from 0. 1724 */ 1725 static void 1726 pci_print_pcie_linkspeedvector(pcireg_t val) 1727 { 1728 unsigned int i; 1729 1730 /* Start from 0 */ 1731 for (i = 0; i < 16; i++) 1732 if (((val >> i) & 0x01) != 0) { 1733 if (i >= __arraycount(pcie_linkspeeds)) 1734 printf(" unknown vector (0x%x)", 1 << i); 1735 else 1736 printf(" %sGT/s", pcie_linkspeeds[i]); 1737 } 1738 } 1739 1740 static void 1741 pci_print_pcie_link_deemphasis(pcireg_t val) 1742 { 1743 switch (val) { 1744 case 0: 1745 printf("-6dB"); 1746 break; 1747 case 1: 1748 printf("-3.5dB"); 1749 break; 1750 default: 1751 printf("(reserved value)"); 1752 } 1753 } 1754 1755 static void 1756 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1757 { 1758 pcireg_t reg; /* for each register */ 1759 pcireg_t val; /* for each bitfield */ 1760 bool check_link = true; 1761 bool check_slot = false; 1762 bool check_rootport = false; 1763 bool check_upstreamport = false; 1764 unsigned int pciever; 1765 unsigned int i; 1766 1767 printf("\n PCI Express Capabilities Register\n"); 1768 /* Capability Register */ 1769 reg = regs[o2i(capoff)]; 1770 printf(" Capability register: 0x%04x\n", reg >> 16); 1771 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1772 printf(" Capability version: %u\n", pciever); 1773 printf(" Device type: "); 1774 switch ((reg & 0x00f00000) >> 20) { 1775 case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */ 1776 printf("PCI Express Endpoint device\n"); 1777 check_upstreamport = true; 1778 break; 1779 case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */ 1780 printf("Legacy PCI Express Endpoint device\n"); 1781 check_upstreamport = true; 1782 break; 1783 case PCIE_XCAP_TYPE_ROOT: /* 0x4 */ 1784 printf("Root Port of PCI Express Root Complex\n"); 1785 check_slot = true; 1786 check_rootport = true; 1787 break; 1788 case PCIE_XCAP_TYPE_UP: /* 0x5 */ 1789 printf("Upstream Port of PCI Express Switch\n"); 1790 check_upstreamport = true; 1791 break; 1792 case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ 1793 printf("Downstream Port of PCI Express Switch\n"); 1794 check_slot = true; 1795 check_rootport = true; 1796 break; 1797 case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ 1798 printf("PCI Express to PCI/PCI-X Bridge\n"); 1799 check_upstreamport = true; 1800 break; 1801 case PCIE_XCAP_TYPE_PCI2PCIE: /* 0x8 */ 1802 printf("PCI/PCI-X to PCI Express Bridge\n"); 1803 /* Upstream port is not PCIe */ 1804 check_slot = true; 1805 break; 1806 case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */ 1807 printf("Root Complex Integrated Endpoint\n"); 1808 check_link = false; 1809 break; 1810 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */ 1811 printf("Root Complex Event Collector\n"); 1812 check_link = false; 1813 check_rootport = true; 1814 break; 1815 default: 1816 printf("unknown\n"); 1817 break; 1818 } 1819 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1820 printf(" Interrupt Message Number: 0x%02x\n", 1821 (unsigned int)__SHIFTOUT(reg, PCIE_XCAP_IRQ)); 1822 1823 /* Device Capability Register */ 1824 reg = regs[o2i(capoff + PCIE_DCAP)]; 1825 printf(" Device Capabilities Register: 0x%08x\n", reg); 1826 printf(" Max Payload Size Supported: %u bytes max\n", 1827 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1828 printf(" Phantom Functions Supported: "); 1829 switch (__SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) { 1830 case 0x0: 1831 printf("not available\n"); 1832 break; 1833 case 0x1: 1834 printf("MSB\n"); 1835 break; 1836 case 0x2: 1837 printf("two MSB\n"); 1838 break; 1839 case 0x3: 1840 printf("All three bits\n"); 1841 break; 1842 } 1843 printf(" Extended Tag Field Supported: %dbit\n", 1844 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1845 printf(" Endpoint L0 Acceptable Latency: "); 1846 pci_print_pcie_L0s_latency(__SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY)); 1847 printf(" Endpoint L1 Acceptable Latency: "); 1848 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY)); 1849 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1850 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1851 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1852 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1853 if (check_upstreamport) { 1854 printf(" Captured Slot Power Limit: "); 1855 pci_conf_print_pcie_power( 1856 __SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL), 1857 __SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE)); 1858 } 1859 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1860 1861 /* Device Control Register */ 1862 reg = regs[o2i(capoff + PCIE_DCSR)]; 1863 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1864 onoff("Correctable Error Reporting Enable", reg, 1865 PCIE_DCSR_ENA_COR_ERR); 1866 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1867 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1868 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1869 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1870 printf(" Max Payload Size: %d byte\n", 1871 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD)); 1872 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1873 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1874 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1875 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1876 printf(" Max Read Request Size: %d byte\n", 1877 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ)); 1878 1879 /* Device Status Register */ 1880 reg = regs[o2i(capoff + PCIE_DCSR)]; 1881 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1882 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1883 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1884 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1885 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1886 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1887 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1888 onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD); 1889 1890 if (check_link) { 1891 /* Link Capability Register */ 1892 reg = regs[o2i(capoff + PCIE_LCAP)]; 1893 printf(" Link Capabilities Register: 0x%08x\n", reg); 1894 printf(" Maximum Link Speed: "); 1895 pci_print_pcie_linkspeed(PCIE_LCAP, reg & PCIE_LCAP_MAX_SPEED); 1896 printf(" Maximum Link Width: x%u lanes\n", 1897 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH)); 1898 printf(" Active State PM Support: "); 1899 switch (__SHIFTOUT(reg, PCIE_LCAP_ASPM)) { 1900 case 0x0: 1901 printf("No ASPM support\n"); 1902 break; 1903 case 0x1: 1904 printf("L0s supported\n"); 1905 break; 1906 case 0x2: 1907 printf("L1 supported\n"); 1908 break; 1909 case 0x3: 1910 printf("L0s and L1 supported\n"); 1911 break; 1912 } 1913 printf(" L0 Exit Latency: "); 1914 pci_print_pcie_L0s_latency(__SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT)); 1915 printf(" L1 Exit Latency: "); 1916 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_LCAP_L1_EXIT)); 1917 printf(" Port Number: %u\n", 1918 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_PORT)); 1919 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1920 onoff("Surprise Down Error Report", reg, 1921 PCIE_LCAP_SURPRISE_DOWN); 1922 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1923 onoff("Link BW Notification Capable", reg, 1924 PCIE_LCAP_LINK_BW_NOTIFY); 1925 onoff("ASPM Optionally Compliance", reg, 1926 PCIE_LCAP_ASPM_COMPLIANCE); 1927 1928 /* Link Control Register */ 1929 reg = regs[o2i(capoff + PCIE_LCSR)]; 1930 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1931 printf(" Active State PM Control: "); 1932 switch (reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S)) { 1933 case 0: 1934 printf("disabled\n"); 1935 break; 1936 case 1: 1937 printf("L0s Entry Enabled\n"); 1938 break; 1939 case 2: 1940 printf("L1 Entry Enabled\n"); 1941 break; 1942 case 3: 1943 printf("L0s and L1 Entry Enabled\n"); 1944 break; 1945 } 1946 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1947 "128bytes", "64bytes"); 1948 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1949 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1950 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1951 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1952 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1953 onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD); 1954 onoff("Link Bandwidth Management Interrupt Enable", reg, 1955 PCIE_LCSR_LBMIE); 1956 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1957 PCIE_LCSR_LABIE); 1958 printf(" DRS Signaling Control: "); 1959 switch (__SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) { 1960 case 0: 1961 printf("not reported\n"); 1962 break; 1963 case 1: 1964 printf("Interrupt Enabled\n"); 1965 break; 1966 case 2: 1967 printf("DRS to FRS Signaling Enabled\n"); 1968 break; 1969 default: 1970 printf("reserved\n"); 1971 break; 1972 } 1973 1974 /* Link Status Register */ 1975 reg = regs[o2i(capoff + PCIE_LCSR)]; 1976 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1977 printf(" Negotiated Link Speed: "); 1978 pci_print_pcie_linkspeed(PCIE_LCSR, 1979 __SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 1980 printf(" Negotiated Link Width: x%u lanes\n", 1981 (unsigned int)__SHIFTOUT(reg, PCIE_LCSR_NLW)); 1982 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1983 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1984 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1985 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1986 onoff("Link Bandwidth Management Status", reg, 1987 PCIE_LCSR_LINK_BW_MGMT); 1988 onoff("Link Autonomous Bandwidth Status", reg, 1989 PCIE_LCSR_LINK_AUTO_BW); 1990 } 1991 1992 if (check_slot == true) { 1993 pcireg_t slcap; 1994 1995 /* Slot Capability Register */ 1996 slcap = reg = regs[o2i(capoff + PCIE_SLCAP)]; 1997 printf(" Slot Capability Register: 0x%08x\n", reg); 1998 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1999 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 2000 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 2001 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 2002 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 2003 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 2004 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 2005 printf(" Slot Power Limit Value: "); 2006 pci_conf_print_pcie_power(__SHIFTOUT(reg, PCIE_SLCAP_SPLV), 2007 __SHIFTOUT(reg, PCIE_SLCAP_SPLS)); 2008 onoff("Electromechanical Interlock Present", reg, 2009 PCIE_SLCAP_EIP); 2010 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 2011 printf(" Physical Slot Number: %d\n", 2012 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 2013 2014 /* Slot Control Register */ 2015 reg = regs[o2i(capoff + PCIE_SLCSR)]; 2016 printf(" Slot Control Register: 0x%04x\n", reg & 0xffff); 2017 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 2018 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 2019 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 2020 onoff("Presence Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 2021 onoff("Command Completed Interrupt Enabled", reg, 2022 PCIE_SLCSR_CCE); 2023 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 2024 /* 2025 * For Attention Indicator Control and Power Indicator Control, 2026 * it's allowed to be a read only value 0 if corresponding 2027 * capability register bit is 0. 2028 */ 2029 if (slcap & PCIE_SLCAP_AIP) { 2030 printf(" Attention Indicator Control: "); 2031 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 2032 case 0x0: 2033 printf("reserved\n"); 2034 break; 2035 case PCIE_SLCSR_IND_ON: 2036 printf("on\n"); 2037 break; 2038 case PCIE_SLCSR_IND_BLINK: 2039 printf("blink\n"); 2040 break; 2041 case PCIE_SLCSR_IND_OFF: 2042 printf("off\n"); 2043 break; 2044 } 2045 } 2046 if (slcap & PCIE_SLCAP_PIP) { 2047 printf(" Power Indicator Control: "); 2048 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 2049 case 0x0: 2050 printf("reserved\n"); 2051 break; 2052 case PCIE_SLCSR_IND_ON: 2053 printf("on\n"); 2054 break; 2055 case PCIE_SLCSR_IND_BLINK: 2056 printf("blink\n"); 2057 break; 2058 case PCIE_SLCSR_IND_OFF: 2059 printf("off\n"); 2060 break; 2061 } 2062 } 2063 printf(" Power Controller Control: Power %s\n", 2064 reg & PCIE_SLCSR_PCC ? "off" : "on"); 2065 onoff("Electromechanical Interlock Control", 2066 reg, PCIE_SLCSR_EIC); 2067 onoff("Data Link Layer State Changed Enable", reg, 2068 PCIE_SLCSR_DLLSCE); 2069 onoff("Auto Slot Power Limit Disable", reg, 2070 PCIE_SLCSR_AUTOSPLDIS); 2071 2072 /* Slot Status Register */ 2073 printf(" Slot Status Register: 0x%04x\n", reg >> 16); 2074 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 2075 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 2076 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 2077 onoff("Presence Detect Changed", reg, PCIE_SLCSR_PDC); 2078 onoff("Command Completed", reg, PCIE_SLCSR_CC); 2079 onoff("MRL Open", reg, PCIE_SLCSR_MS); 2080 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 2081 onoff("Electromechanical Interlock engaged", reg, 2082 PCIE_SLCSR_EIS); 2083 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 2084 } 2085 2086 if (check_rootport == true) { 2087 /* Root Control Register */ 2088 reg = regs[o2i(capoff + PCIE_RCR)]; 2089 printf(" Root Control Register: 0x%04x\n", reg & 0xffff); 2090 onoff("SERR on Correctable Error Enable", reg, 2091 PCIE_RCR_SERR_CER); 2092 onoff("SERR on Non-Fatal Error Enable", reg, 2093 PCIE_RCR_SERR_NFER); 2094 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 2095 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 2096 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 2097 2098 /* Root Capability Register */ 2099 printf(" Root Capability Register: 0x%04x\n", 2100 reg >> 16); 2101 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 2102 2103 /* Root Status Register */ 2104 reg = regs[o2i(capoff + PCIE_RSR)]; 2105 printf(" Root Status Register: 0x%08x\n", reg); 2106 printf(" PME Requester ID: 0x%04x\n", 2107 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 2108 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 2109 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 2110 } 2111 2112 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2113 if (pciever < 2) 2114 return; 2115 2116 /* Device Capabilities 2 */ 2117 reg = regs[o2i(capoff + PCIE_DCAP2)]; 2118 printf(" Device Capabilities 2: 0x%08x\n", reg); 2119 printf(" Completion Timeout Ranges Supported: "); 2120 val = reg & PCIE_DCAP2_COMPT_RANGE; 2121 switch (val) { 2122 case 0: 2123 printf("not supported\n"); 2124 break; 2125 default: 2126 for (i = 0; i <= 3; i++) { 2127 if (((val >> i) & 0x01) != 0) 2128 printf("%c", 'A' + i); 2129 } 2130 printf("\n"); 2131 } 2132 onoff("Completion Timeout Disable Supported", reg, 2133 PCIE_DCAP2_COMPT_DIS); 2134 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 2135 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 2136 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 2137 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 2138 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 2139 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 2140 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 2141 printf(" TPH Completer Supported: "); 2142 switch (__SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) { 2143 case 0: 2144 printf("Not supported\n"); 2145 break; 2146 case 1: 2147 printf("TPH\n"); 2148 break; 2149 case 3: 2150 printf("TPH and Extended TPH\n"); 2151 break; 2152 default: 2153 printf("(reserved value)\n"); 2154 break; 2155 2156 } 2157 printf(" LN System CLS: "); 2158 switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 2159 case 0x0: 2160 printf("Not supported or not in effect\n"); 2161 break; 2162 case 0x1: 2163 printf("64byte cachelines in effect\n"); 2164 break; 2165 case 0x2: 2166 printf("128byte cachelines in effect\n"); 2167 break; 2168 case 0x3: 2169 printf("Reserved\n"); 2170 break; 2171 } 2172 printf(" OBFF Supported: "); 2173 switch (__SHIFTOUT(reg, PCIE_DCAP2_OBFF)) { 2174 case 0x0: 2175 printf("Not supported\n"); 2176 break; 2177 case 0x1: 2178 printf("Message only\n"); 2179 break; 2180 case 0x2: 2181 printf("WAKE# only\n"); 2182 break; 2183 case 0x3: 2184 printf("Both\n"); 2185 break; 2186 } 2187 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 2188 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 2189 val = __SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP); 2190 printf(" Max End-End TLP Prefixes: %u\n", (val == 0) ? 4 : val); 2191 printf(" Emergency Power Reduction Supported: "); 2192 switch (__SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) { 2193 case 0x0: 2194 printf("Not supported\n"); 2195 break; 2196 case 0x1: 2197 printf("Device Specific mechanism\n"); 2198 break; 2199 case 0x2: 2200 printf("Form Factor spec or Device Specific mechanism\n"); 2201 break; 2202 case 0x3: 2203 printf("Reserved\n"); 2204 break; 2205 } 2206 onoff("Emergency Power Reduction Initialization Required", reg, 2207 PCIE_DCAP2_EMGPWRRED_INI); 2208 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 2209 2210 /* Device Control 2 */ 2211 reg = regs[o2i(capoff + PCIE_DCSR2)]; 2212 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 2213 printf(" Completion Timeout Value: "); 2214 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 2215 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 2216 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 2217 onoff("AtomicOp Requester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 2218 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 2219 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 2220 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 2221 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 2222 onoff("Emergency Power Reduction Request", reg, 2223 PCIE_DCSR2_EMGPWRRED_REQ); 2224 printf(" OBFF: "); 2225 switch (__SHIFTOUT(reg, PCIE_DCSR2_OBFF_EN)) { 2226 case 0x0: 2227 printf("Disabled\n"); 2228 break; 2229 case 0x1: 2230 printf("Enabled with Message Signaling Variation A\n"); 2231 break; 2232 case 0x2: 2233 printf("Enabled with Message Signaling Variation B\n"); 2234 break; 2235 case 0x3: 2236 printf("Enabled using WAKE# signaling\n"); 2237 break; 2238 } 2239 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 2240 2241 if (check_link) { 2242 bool drs_supported = false; 2243 2244 /* Link Capability 2 */ 2245 reg = regs[o2i(capoff + PCIE_LCAP2)]; 2246 /* If the vector is 0, LCAP2 is not implemented */ 2247 if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) { 2248 printf(" Link Capabilities 2: 0x%08x\n", reg); 2249 printf(" Supported Link Speeds Vector:"); 2250 pci_print_pcie_linkspeedvector( 2251 __SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 2252 printf("\n"); 2253 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 2254 printf(" " 2255 "Lower SKP OS Generation Supported Speed Vector:"); 2256 pci_print_pcie_linkspeedvector( 2257 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 2258 printf("\n"); 2259 printf(" " 2260 "Lower SKP OS Reception Supported Speed Vector:"); 2261 pci_print_pcie_linkspeedvector( 2262 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 2263 printf("\n"); 2264 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 2265 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 2266 } 2267 2268 /* Link Control 2 */ 2269 reg = regs[o2i(capoff + PCIE_LCSR2)]; 2270 /* If the vector is 0, LCAP2 is not implemented */ 2271 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 2272 printf(" Target Link Speed: "); 2273 pci_print_pcie_linkspeed(PCIE_LCSR2, 2274 __SHIFTOUT(reg, PCIE_LCSR2_TGT_LSPEED)); 2275 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 2276 onoff("HW Autonomous Speed Disabled", reg, 2277 PCIE_LCSR2_HW_AS_DIS); 2278 printf(" Selectable De-emphasis: "); 2279 pci_print_pcie_link_deemphasis( 2280 __SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP)); 2281 printf("\n"); 2282 printf(" Transmit Margin: %u\n", 2283 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 2284 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 2285 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 2286 printf(" Compliance Present/De-emphasis: "); 2287 pci_print_pcie_link_deemphasis( 2288 __SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP)); 2289 printf("\n"); 2290 2291 /* Link Status 2 */ 2292 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 2293 printf(" Current De-emphasis Level: "); 2294 pci_print_pcie_link_deemphasis( 2295 __SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL)); 2296 printf("\n"); 2297 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 2298 onoff("Equalization Phase 1 Successful", reg, 2299 PCIE_LCSR2_EQP1_SUC); 2300 onoff("Equalization Phase 2 Successful", reg, 2301 PCIE_LCSR2_EQP2_SUC); 2302 onoff("Equalization Phase 3 Successful", reg, 2303 PCIE_LCSR2_EQP3_SUC); 2304 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 2305 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 2306 if (drs_supported) { 2307 printf(" Downstream Component Presence: "); 2308 switch (__SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 2309 case PCIE_DSCOMPN_DOWN_NOTDETERM: 2310 printf("Link Down - Presence Not" 2311 " Determined\n"); 2312 break; 2313 case PCIE_DSCOMPN_DOWN_NOTPRES: 2314 printf("Link Down - Component Not Present\n"); 2315 break; 2316 case PCIE_DSCOMPN_DOWN_PRES: 2317 printf("Link Down - Component Present\n"); 2318 break; 2319 case PCIE_DSCOMPN_UP_PRES: 2320 printf("Link Up - Component Present\n"); 2321 break; 2322 case PCIE_DSCOMPN_UP_PRES_DRS: 2323 printf("Link Up - Component Present and DRS" 2324 " received\n"); 2325 break; 2326 default: 2327 printf("reserved\n"); 2328 break; 2329 } 2330 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 2331 } 2332 } 2333 2334 /* Slot Capability 2 */ 2335 /* Slot Control 2 */ 2336 /* Slot Status 2 */ 2337 } 2338 2339 static void 2340 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 2341 { 2342 pcireg_t reg; 2343 2344 printf("\n MSI-X Capability Register\n"); 2345 2346 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2347 printf(" Message Control register: 0x%04x\n", 2348 (reg >> 16) & 0xff); 2349 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 2350 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 2351 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 2352 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 2353 printf(" Table offset register: 0x%08x\n", reg); 2354 printf(" Table offset: 0x%08x\n", 2355 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 2356 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 2357 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 2358 printf(" Pending bit array register: 0x%08x\n", reg); 2359 printf(" Pending bit array offset: 0x%08x\n", 2360 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2361 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2362 } 2363 2364 static void 2365 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2366 { 2367 pcireg_t reg; 2368 2369 printf("\n Serial ATA Capability Register\n"); 2370 2371 reg = regs[o2i(capoff + PCI_SATA_REV)]; 2372 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2373 printf(" Revision: %u.%u\n", 2374 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2375 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2376 2377 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2378 2379 printf(" BAR Register: 0x%08x\n", reg); 2380 printf(" Register location: "); 2381 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2382 printf("in config space\n"); 2383 else { 2384 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2385 printf(" BAR offset: 0x%08x\n", 2386 (pcireg_t)__SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2387 } 2388 } 2389 2390 static void 2391 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2392 { 2393 pcireg_t reg; 2394 2395 printf("\n Advanced Features Capability Register\n"); 2396 2397 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2398 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2399 printf(" AF Structure Length: 0x%02x\n", 2400 (pcireg_t)__SHIFTOUT(reg, PCI_AF_LENGTH)); 2401 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2402 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2403 reg = regs[o2i(capoff + PCI_AFCSR)]; 2404 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2405 /* 2406 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2407 * and it's always 0 on read 2408 */ 2409 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2410 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2411 } 2412 2413 /* XXX pci_conf_print_ea_cap */ 2414 /* XXX pci_conf_print_fpb_cap */ 2415 2416 static struct { 2417 pcireg_t cap; 2418 const char *name; 2419 void (*printfunc)(const pcireg_t *, int); 2420 } pci_captab[] = { 2421 { PCI_CAP_RESERVED0, "reserved", NULL }, 2422 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2423 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2424 { PCI_CAP_VPD, "VPD", NULL }, 2425 { PCI_CAP_SLOTID, "SlotID", NULL }, 2426 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2427 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2428 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2429 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2430 { PCI_CAP_VENDSPEC, "Vendor-specific", 2431 pci_conf_print_vendspec_cap }, 2432 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2433 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2434 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2435 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2436 pci_conf_print_subsystem_cap }, 2437 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2438 { PCI_CAP_SECURE, "Secure Device", pci_conf_print_secure_cap }, 2439 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2440 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2441 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2442 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2443 { PCI_CAP_EA, "Enhanced Allocation", NULL }, 2444 { PCI_CAP_FPB, "Flattening Portal Bridge", NULL } 2445 }; 2446 2447 static int 2448 pci_conf_find_cap(const pcireg_t *regs, int capoff, unsigned int capid, 2449 int *offsetp) 2450 { 2451 pcireg_t rval; 2452 int off; 2453 2454 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2455 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2456 rval = regs[o2i(off)]; 2457 if (capid == PCI_CAPLIST_CAP(rval)) { 2458 if (offsetp != NULL) 2459 *offsetp = off; 2460 return 1; 2461 } 2462 } 2463 return 0; 2464 } 2465 2466 static void 2467 pci_conf_print_caplist( 2468 #ifdef _KERNEL 2469 pci_chipset_tag_t pc, pcitag_t tag, 2470 #endif 2471 const pcireg_t *regs, int capoff) 2472 { 2473 int off; 2474 pcireg_t foundcap; 2475 pcireg_t rval; 2476 bool foundtable[__arraycount(pci_captab)]; 2477 unsigned int i; 2478 2479 /* Clear table */ 2480 for (i = 0; i < __arraycount(pci_captab); i++) 2481 foundtable[i] = false; 2482 2483 /* Print capability register's offset and the type first */ 2484 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2485 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2486 rval = regs[o2i(off)]; 2487 printf(" Capability register at 0x%02x\n", off); 2488 2489 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2490 foundcap = PCI_CAPLIST_CAP(rval); 2491 if (foundcap < __arraycount(pci_captab)) { 2492 printf("%s)\n", pci_captab[foundcap].name); 2493 /* Mark as found */ 2494 foundtable[foundcap] = true; 2495 } else 2496 printf("unknown)\n"); 2497 } 2498 2499 /* 2500 * And then, print the detail of each capability registers 2501 * in capability value's order. 2502 */ 2503 for (i = 0; i < __arraycount(pci_captab); i++) { 2504 if (foundtable[i] == false) 2505 continue; 2506 2507 /* 2508 * The type was found. Search capability list again and 2509 * print all capabilities that the capabiliy type is 2510 * the same. This is required because some capabilities 2511 * appear multiple times (e.g. HyperTransport capability). 2512 */ 2513 #if 0 2514 if (pci_conf_find_cap(regs, capoff, i, &off)) { 2515 rval = regs[o2i(off)]; 2516 if (pci_captab[i].printfunc != NULL) 2517 pci_captab[i].printfunc(regs, off); 2518 } 2519 #else 2520 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2521 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2522 rval = regs[o2i(off)]; 2523 if ((PCI_CAPLIST_CAP(rval) == i) 2524 && (pci_captab[i].printfunc != NULL)) 2525 pci_captab[i].printfunc(regs, off); 2526 } 2527 #endif 2528 } 2529 } 2530 2531 /* Extended Capability */ 2532 2533 static void 2534 pci_conf_print_aer_cap_uc(pcireg_t reg) 2535 { 2536 2537 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2538 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2539 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2540 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2541 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2542 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2543 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2544 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2545 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2546 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2547 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2548 onoff("Unsupported Request Error", reg, 2549 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2550 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2551 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2552 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2553 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2554 onoff("TLP Prefix Blocked Error", reg, 2555 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2556 onoff("Poisoned TLP Egress Blocked", reg, 2557 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2558 } 2559 2560 static void 2561 pci_conf_print_aer_cap_cor(pcireg_t reg) 2562 { 2563 2564 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2565 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2566 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2567 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2568 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2569 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2570 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2571 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2572 } 2573 2574 static void 2575 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2576 { 2577 2578 printf(" First Error Pointer: 0x%04x\n", 2579 (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2580 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2581 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2582 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2583 onoff("ECRC Check Enable", reg, PCI_AER_ECRC_CHECK_ENABLE); 2584 onoff("Multiple Header Recording Capable", reg, 2585 PCI_AER_MULT_HDR_CAPABLE); 2586 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2587 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2588 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2589 2590 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2591 if (!tlp_prefix_log) 2592 return; 2593 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2594 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2595 } 2596 2597 static void 2598 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2599 { 2600 2601 onoff("Correctable Error Reporting Enable", reg, 2602 PCI_AER_ROOTERR_COR_ENABLE); 2603 onoff("Non-Fatal Error Reporting Enable", reg, 2604 PCI_AER_ROOTERR_NF_ENABLE); 2605 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2606 } 2607 2608 static void 2609 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2610 { 2611 2612 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2613 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2614 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2615 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2616 PCI_AER_ROOTERR_MULTI_UC_ERR); 2617 onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL); 2618 onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR); 2619 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2620 printf(" Advanced Error Interrupt Message Number: 0x%02x\n", 2621 (unsigned int)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2622 } 2623 2624 static void 2625 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2626 { 2627 2628 printf(" Correctable Source ID: 0x%04x\n", 2629 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2630 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2631 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2632 } 2633 2634 static void 2635 pci_conf_print_aer_cap(const pcireg_t *regs, int capoff, int extcapoff) 2636 { 2637 pcireg_t reg; 2638 int pcie_capoff; 2639 int pcie_devtype = -1; 2640 bool tlp_prefix_log = false; 2641 2642 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2643 reg = regs[o2i(pcie_capoff)]; 2644 pcie_devtype = PCIE_XCAP_TYPE(reg); 2645 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2646 if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2647 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2648 /* End-End TLP Prefix Supported */ 2649 if (reg & PCIE_DCAP2_EETLP_PREF) { 2650 tlp_prefix_log = true; 2651 } 2652 } 2653 } 2654 2655 printf("\n Advanced Error Reporting Register\n"); 2656 2657 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2658 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2659 pci_conf_print_aer_cap_uc(reg); 2660 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2661 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2662 pci_conf_print_aer_cap_uc(reg); 2663 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2664 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2665 pci_conf_print_aer_cap_uc(reg); 2666 2667 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2668 printf(" Correctable Error Status register: 0x%08x\n", reg); 2669 pci_conf_print_aer_cap_cor(reg); 2670 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2671 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2672 pci_conf_print_aer_cap_cor(reg); 2673 2674 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2675 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2676 reg); 2677 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2678 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2679 printf(" Header Log register:\n"); 2680 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2681 extcapoff + PCI_AER_ROOTERR_CMD); 2682 2683 switch (pcie_devtype) { 2684 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2685 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2686 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2687 printf(" Root Error Command register: 0x%08x\n", reg); 2688 pci_conf_print_aer_cap_rooterr_cmd(reg); 2689 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2690 printf(" Root Error Status register: 0x%08x\n", reg); 2691 pci_conf_print_aer_cap_rooterr_status(reg); 2692 2693 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2694 printf(" Error Source Identification: 0x%04x\n", reg); 2695 pci_conf_print_aer_cap_errsrc_id(reg); 2696 break; 2697 } 2698 2699 if (tlp_prefix_log) { 2700 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2701 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2702 } 2703 } 2704 2705 static void 2706 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2707 pcireg_t parbsel, int parbsize) 2708 { 2709 pcireg_t reg; 2710 int num = 16 << parbsel; 2711 int num_per_reg = sizeof(pcireg_t) / parbsize; 2712 int i, j; 2713 2714 /* First, dump the table */ 2715 for (i = 0; i < num; i += num_per_reg) { 2716 reg = regs[o2i(off + i / num_per_reg)]; 2717 printf(" %s Arbitration Table: 0x%08x\n", name, reg); 2718 } 2719 /* And then, decode each entry */ 2720 for (i = 0; i < num; i += num_per_reg) { 2721 reg = regs[o2i(off + i / num_per_reg)]; 2722 for (j = 0; j < num_per_reg; j++) 2723 printf(" Phase[%d]: %d\n", j, reg); 2724 } 2725 } 2726 2727 static void 2728 pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2729 { 2730 pcireg_t reg, n; 2731 int parbtab, parbsize; 2732 pcireg_t parbsel; 2733 int varbtab, varbsize; 2734 pcireg_t varbsel; 2735 int i, count; 2736 2737 printf("\n Virtual Channel Register\n"); 2738 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2739 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2740 count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2741 printf(" Extended VC Count: %d\n", count); 2742 n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2743 printf(" Low Priority Extended VC Count: %u\n", n); 2744 n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2745 printf(" Reference Clock: %s\n", 2746 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 2747 parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2748 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2749 2750 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2751 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2752 onoff("Hardware fixed arbitration scheme", 2753 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2754 onoff("WRR arbitration with 32 phases", 2755 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2756 onoff("WRR arbitration with 64 phases", 2757 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2758 onoff("WRR arbitration with 128 phases", 2759 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2760 varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2761 printf(" VC Arbitration Table Offset: 0x%x\n", varbtab); 2762 2763 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2764 printf(" Port VC Control register: 0x%04x\n", reg); 2765 varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2766 printf(" VC Arbitration Select: 0x%x\n", varbsel); 2767 2768 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2769 printf(" Port VC Status register: 0x%04x\n", reg); 2770 onoff("VC Arbitration Table Status", 2771 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 2772 2773 for (i = 0; i < count + 1; i++) { 2774 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 2775 printf(" VC number %d\n", i); 2776 printf(" VC Resource Capability Register: 0x%08x\n", reg); 2777 onoff(" Non-configurable Hardware fixed arbitration scheme", 2778 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 2779 onoff(" WRR arbitration with 32 phases", 2780 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 2781 onoff(" WRR arbitration with 64 phases", 2782 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 2783 onoff(" WRR arbitration with 128 phases", 2784 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 2785 onoff(" Time-based WRR arbitration with 128 phases", 2786 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 2787 onoff(" WRR arbitration with 256 phases", 2788 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 2789 onoff(" Advanced Packet Switching", 2790 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 2791 onoff(" Reject Snoop Transaction", 2792 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 2793 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 2794 printf(" Maximum Time Slots: %d\n", n); 2795 parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S; 2796 printf(" Port Arbitration Table offset: 0x%02x\n", 2797 parbtab); 2798 2799 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 2800 printf(" VC Resource Control Register: 0x%08x\n", reg); 2801 printf(" TC/VC Map: 0x%02x\n", 2802 (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 2803 /* 2804 * The load Port Arbitration Table bit is used to update 2805 * the Port Arbitration logic and it's always 0 on read, so 2806 * we don't print it. 2807 */ 2808 parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 2809 printf(" Port Arbitration Select: 0x%x\n", parbsel); 2810 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 2811 printf(" VC ID: %d\n", n); 2812 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 2813 2814 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 2815 printf(" VC Resource Status Register: 0x%08x\n", reg); 2816 onoff(" Port Arbitration Table Status", 2817 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 2818 onoff(" VC Negotiation Pending", 2819 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 2820 2821 if ((parbtab != 0) && (parbsel != 0)) 2822 pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab, 2823 "Port", parbsel, parbsize); 2824 } 2825 2826 varbsize = 8; 2827 if ((varbtab != 0) && (varbsel != 0)) 2828 pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab, 2829 " VC", varbsel, varbsize); 2830 } 2831 2832 /* 2833 * Print Power limit. This encoding is the same among the following registers: 2834 * - The Captured Slot Power Limit in the PCIe Device Capability Register. 2835 * - The Slot Power Limit in the PCIe Slot Capability Register. 2836 * - The Base Power in the Data register of Power Budgeting capability. 2837 */ 2838 static void 2839 pci_conf_print_pcie_power(uint8_t base, unsigned int scale) 2840 { 2841 unsigned int sdiv = 1; 2842 2843 if ((scale == 0) && (base > 0xef)) { 2844 const char *s; 2845 2846 switch (base) { 2847 case 0xf0: 2848 s = "239W < x <= 250W"; 2849 break; 2850 case 0xf1: 2851 s = "250W < x <= 275W"; 2852 break; 2853 case 0xf2: 2854 s = "275W < x <= 300W"; 2855 break; 2856 default: 2857 s = "reserved for above 300W"; 2858 break; 2859 } 2860 printf("%s\n", s); 2861 return; 2862 } 2863 2864 for (unsigned int i = scale; i > 0; i--) 2865 sdiv *= 10; 2866 2867 printf("%u", base / sdiv); 2868 2869 if (scale != 0) { 2870 printf(".%u", base % sdiv); 2871 } 2872 printf ("W\n"); 2873 return; 2874 } 2875 2876 static const char * 2877 pci_conf_print_pwrbdgt_type(uint8_t reg) 2878 { 2879 2880 switch (reg) { 2881 case 0x00: 2882 return "PME Aux"; 2883 case 0x01: 2884 return "Auxilary"; 2885 case 0x02: 2886 return "Idle"; 2887 case 0x03: 2888 return "Sustained"; 2889 case 0x04: 2890 return "Sustained (Emergency Power Reduction)"; 2891 case 0x05: 2892 return "Maximum (Emergency Power Reduction)"; 2893 case 0x07: 2894 return "Maximum"; 2895 default: 2896 return "Unknown"; 2897 } 2898 } 2899 2900 static const char * 2901 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 2902 { 2903 2904 switch (reg) { 2905 case 0x00: 2906 return "Power(12V)"; 2907 case 0x01: 2908 return "Power(3.3V)"; 2909 case 0x02: 2910 return "Power(1.5V or 1.8V)"; 2911 case 0x07: 2912 return "Thermal"; 2913 default: 2914 return "Unknown"; 2915 } 2916 } 2917 2918 static void 2919 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff) 2920 { 2921 pcireg_t reg; 2922 2923 printf("\n Power Budgeting\n"); 2924 2925 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 2926 printf(" Data Select register: 0x%08x\n", reg); 2927 2928 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 2929 printf(" Data register: 0x%08x\n", reg); 2930 printf(" Base Power: "); 2931 pci_conf_print_pcie_power( 2932 __SHIFTOUT(reg, PCI_PWRBDGT_DATA_BASEPWR), 2933 __SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE)); 2934 printf(" PM Sub State: 0x%hhx\n", 2935 (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 2936 printf(" PM State: D%u\n", 2937 (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 2938 printf(" Type: %s\n", 2939 pci_conf_print_pwrbdgt_type( 2940 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 2941 printf(" Power Rail: %s\n", 2942 pci_conf_print_pwrbdgt_pwrrail( 2943 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 2944 2945 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 2946 printf(" Power Budget Capability register: 0x%08x\n", reg); 2947 onoff("System Allocated", 2948 reg, PCI_PWRBDGT_CAP_SYSALLOC); 2949 } 2950 2951 static const char * 2952 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 2953 { 2954 2955 switch (type) { 2956 case 0x00: 2957 return "Configuration Space Element"; 2958 case 0x01: 2959 return "System Egress Port or internal sink (memory)"; 2960 case 0x02: 2961 return "Internal Root Complex Link"; 2962 default: 2963 return "Unknown"; 2964 } 2965 } 2966 2967 static void 2968 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int capoff, int extcapoff) 2969 { 2970 pcireg_t reg; 2971 unsigned char nent, linktype; 2972 int i; 2973 2974 printf("\n Root Complex Link Declaration\n"); 2975 2976 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 2977 printf(" Element Self Description Register: 0x%08x\n", reg); 2978 printf(" Element Type: %s\n", 2979 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 2980 nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 2981 printf(" Number of Link Entries: %hhu\n", nent); 2982 printf(" Component ID: %hhu\n", 2983 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 2984 printf(" Port Number: %hhu\n", 2985 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 2986 for (i = 0; i < nent; i++) { 2987 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 2988 printf(" Link Entry %d:\n", i + 1); 2989 printf(" Link Description Register: 0x%08x\n", reg); 2990 onoff(" Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID); 2991 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 2992 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 2993 "Configuration Space", "Memory-Mapped Space"); 2994 onoff(" Associated RCRB Header", reg, 2995 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 2996 printf(" Target Component ID: %hhu\n", 2997 (unsigned char)__SHIFTOUT(reg, 2998 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 2999 printf(" Target Port Number: %hhu\n", 3000 (unsigned char)__SHIFTOUT(reg, 3001 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 3002 3003 if (linktype == 0) { 3004 /* Memory-Mapped Space */ 3005 reg = regs[o2i(extcapoff 3006 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 3007 printf(" Link Address Low Register: 0x%08x\n", 3008 reg); 3009 reg = regs[o2i(extcapoff 3010 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 3011 printf(" Link Address High Register: 0x%08x\n", 3012 reg); 3013 } else { 3014 unsigned int nb; 3015 pcireg_t lo, hi; 3016 3017 /* Configuration Space */ 3018 lo = regs[o2i(extcapoff 3019 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 3020 printf(" Configuration Space Low Register: " 3021 "0x%08x\n", lo); 3022 hi = regs[o2i(extcapoff 3023 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 3024 printf(" Configuration Space High Register: " 3025 "0x%08x\n", hi); 3026 nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 3027 printf(" N: %u\n", nb); 3028 printf(" Func: %hhu\n", 3029 (unsigned char)__SHIFTOUT(lo, 3030 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 3031 printf(" Dev: %hhu\n", 3032 (unsigned char)__SHIFTOUT(lo, 3033 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 3034 printf(" Bus: %hhu\n", 3035 (unsigned char)__SHIFTOUT(lo, 3036 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 3037 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 3038 printf(" Configuration Space Base Address: " 3039 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 3040 } 3041 } 3042 } 3043 3044 /* XXX pci_conf_print_rclink_ctl_cap */ 3045 3046 static void 3047 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int capoff, int extcapoff) 3048 { 3049 pcireg_t reg; 3050 3051 printf("\n Root Complex Event Collector Association\n"); 3052 3053 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 3054 printf(" Association Bitmap for Root Complex Integrated Devices:" 3055 " 0x%08x\n", reg); 3056 } 3057 3058 /* XXX pci_conf_print_mfvc_cap */ 3059 /* XXX pci_conf_print_vc2_cap */ 3060 /* XXX pci_conf_print_rcrb_cap */ 3061 /* XXX pci_conf_print_vendor_cap */ 3062 /* XXX pci_conf_print_cac_cap */ 3063 3064 static void 3065 pci_conf_print_acs_cap(const pcireg_t *regs, int capoff, int extcapoff) 3066 { 3067 pcireg_t reg, cap, ctl; 3068 unsigned int size, i; 3069 3070 printf("\n Access Control Services\n"); 3071 3072 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 3073 cap = reg & 0xffff; 3074 ctl = reg >> 16; 3075 printf(" ACS Capability register: 0x%08x\n", cap); 3076 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 3077 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 3078 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 3079 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 3080 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 3081 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 3082 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 3083 size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 3084 if (size == 0) 3085 size = 256; 3086 printf(" Egress Control Vector Size: %u\n", size); 3087 printf(" ACS Control register: 0x%08x\n", ctl); 3088 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 3089 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 3090 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 3091 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 3092 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 3093 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 3094 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 3095 3096 /* 3097 * If the P2P Egress Control Capability bit is 0, ignore the Egress 3098 * Control vector. 3099 */ 3100 if ((cap & PCI_ACS_CAP_E) == 0) 3101 return; 3102 for (i = 0; i < size; i += 32) 3103 printf(" Egress Control Vector [%u..%u]: 0x%08x\n", i + 31, 3104 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 3105 } 3106 3107 static void 3108 pci_conf_print_ari_cap(const pcireg_t *regs, int capoff, int extcapoff) 3109 { 3110 pcireg_t reg, cap, ctl; 3111 3112 printf("\n Alternative Routing-ID Interpretation Register\n"); 3113 3114 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3115 cap = reg & 0xffff; 3116 ctl = reg >> 16; 3117 printf(" Capability register: 0x%08x\n", cap); 3118 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 3119 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 3120 printf(" Next Function Number: %u\n", 3121 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 3122 printf(" Control register: 0x%08x\n", ctl); 3123 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 3124 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 3125 printf(" Function Group: %u\n", 3126 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 3127 } 3128 3129 static void 3130 pci_conf_print_ats_cap(const pcireg_t *regs, int capoff, int extcapoff) 3131 { 3132 pcireg_t reg, cap, ctl; 3133 unsigned int num; 3134 3135 printf("\n Address Translation Services\n"); 3136 3137 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3138 cap = reg & 0xffff; 3139 ctl = reg >> 16; 3140 printf(" Capability register: 0x%04x\n", cap); 3141 num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 3142 if (num == 0) 3143 num = 32; 3144 printf(" Invalidate Queue Depth: %u\n", num); 3145 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 3146 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 3147 3148 printf(" Control register: 0x%04x\n", ctl); 3149 printf(" Smallest Translation Unit: %u\n", 3150 (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU)); 3151 onoff("Enable", reg, PCI_ATS_CTL_EN); 3152 } 3153 3154 static void 3155 pci_conf_print_sernum_cap(const pcireg_t *regs, int capoff, int extcapoff) 3156 { 3157 pcireg_t lo, hi; 3158 3159 printf("\n Device Serial Number Register\n"); 3160 3161 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 3162 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 3163 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 3164 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 3165 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 3166 } 3167 3168 static void 3169 pci_conf_print_sriov_cap(const pcireg_t *regs, int capoff, int extcapoff) 3170 { 3171 char buf[sizeof("99999 MB")]; 3172 pcireg_t reg; 3173 pcireg_t total_vfs; 3174 int i; 3175 bool first; 3176 3177 printf("\n Single Root IO Virtualization Register\n"); 3178 3179 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 3180 printf(" Capabilities register: 0x%08x\n", reg); 3181 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 3182 onoff("ARI Capable Hierarchy Preserved", reg, 3183 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 3184 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 3185 printf(" VF Migration Interrupt Message Number: 0x%03x\n", 3186 (pcireg_t)__SHIFTOUT(reg, 3187 PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 3188 } 3189 3190 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 3191 printf(" Control register: 0x%04x\n", reg); 3192 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 3193 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 3194 onoff("VF Migration Interrupt Enable", reg, 3195 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 3196 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 3197 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 3198 3199 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 3200 printf(" Status register: 0x%04x\n", reg); 3201 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 3202 3203 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 3204 printf(" InitialVFs register: 0x%04x\n", reg); 3205 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 3206 printf(" TotalVFs register: 0x%04x\n", reg); 3207 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 3208 printf(" NumVFs register: 0x%04x\n", reg); 3209 3210 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 3211 printf(" Function Dependency Link register: 0x%04x\n", reg); 3212 3213 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 3214 printf(" First VF Offset register: 0x%04x\n", reg); 3215 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 3216 printf(" VF Stride register: 0x%04x\n", reg); 3217 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16; 3218 printf(" Device ID: 0x%04x\n", reg); 3219 3220 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 3221 printf(" Supported Page Sizes register: 0x%08x\n", reg); 3222 printf(" Supported Page Size:"); 3223 for (i = 0, first = true; i < 32; i++) { 3224 if (reg & __BIT(i)) { 3225 #ifdef _KERNEL 3226 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 3227 #else 3228 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 3229 HN_AUTOSCALE, 0); 3230 #endif 3231 printf("%s %s", first ? "" : ",", buf); 3232 first = false; 3233 } 3234 } 3235 printf("\n"); 3236 3237 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 3238 printf(" System Page Sizes register: 0x%08x\n", reg); 3239 printf(" Page Size: "); 3240 if (reg != 0) { 3241 int bitpos = ffs(reg) -1; 3242 3243 /* Assume only one bit is set. */ 3244 #ifdef _KERNEL 3245 format_bytes(buf, sizeof(buf), 1LL << (bitpos + 12)); 3246 #else 3247 humanize_number(buf, sizeof(buf), 1LL << (bitpos + 12), 3248 "B", HN_AUTOSCALE, 0); 3249 #endif 3250 printf("%s", buf); 3251 } else { 3252 printf("unknown"); 3253 } 3254 printf("\n"); 3255 3256 for (i = 0; i < 6; i++) { 3257 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 3258 printf(" VF BAR%d register: 0x%08x\n", i, reg); 3259 } 3260 3261 if (total_vfs > 0) { 3262 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 3263 printf(" VF Migration State Array Offset register: 0x%08x\n", 3264 reg); 3265 printf(" VF Migration State Offset: 0x%08x\n", 3266 (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 3267 i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 3268 printf(" VF Migration State BIR: "); 3269 if (i >= 0 && i <= 5) { 3270 printf("BAR%d", i); 3271 } else { 3272 printf("unknown BAR (%d)", i); 3273 } 3274 printf("\n"); 3275 } 3276 } 3277 3278 /* XXX pci_conf_print_mriov_cap */ 3279 3280 static void 3281 pci_conf_print_multicast_cap(const pcireg_t *regs, int capoff, int extcapoff) 3282 { 3283 pcireg_t reg, cap, ctl; 3284 pcireg_t regl, regh; 3285 uint64_t addr; 3286 int n; 3287 3288 printf("\n Multicast\n"); 3289 3290 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 3291 cap = reg & 0xffff; 3292 ctl = reg >> 16; 3293 printf(" Capability Register: 0x%04x\n", cap); 3294 printf(" Max Group: %u\n", 3295 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 3296 3297 /* Endpoint Only */ 3298 n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 3299 if (n > 0) 3300 printf(" Windw Size Requested: %d\n", 1 << (n - 1)); 3301 3302 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 3303 3304 printf(" Control Register: 0x%04x\n", ctl); 3305 printf(" Num Group: %u\n", 3306 (unsigned int)__SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 3307 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 3308 3309 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 3310 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 3311 printf(" Base Address Register 0: 0x%08x\n", regl); 3312 printf(" Base Address Register 1: 0x%08x\n", regh); 3313 printf(" Index Position: %u\n", 3314 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 3315 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 3316 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 3317 3318 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 3319 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 3320 printf(" Receive Register 0: 0x%08x\n", regl); 3321 printf(" Receive Register 1: 0x%08x\n", regh); 3322 3323 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 3324 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 3325 printf(" Block All Register 0: 0x%08x\n", regl); 3326 printf(" Block All Register 1: 0x%08x\n", regh); 3327 3328 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 3329 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 3330 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 3331 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 3332 3333 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 3334 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 3335 printf(" Overlay BAR 0: 0x%08x\n", regl); 3336 printf(" Overlay BAR 1: 0x%08x\n", regh); 3337 3338 n = regl & PCI_MCAST_OVERLAYL_SIZE; 3339 printf(" Overlay Size: "); 3340 if (n >= 6) 3341 printf("%d\n", n); 3342 else 3343 printf("off\n"); 3344 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 3345 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 3346 } 3347 3348 static void 3349 pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3350 { 3351 pcireg_t reg, ctl, sta; 3352 3353 printf("\n Page Request\n"); 3354 3355 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 3356 ctl = reg & 0xffff; 3357 sta = reg >> 16; 3358 printf(" Control Register: 0x%04x\n", ctl); 3359 onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E); 3360 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 3361 3362 printf(" Status Register: 0x%04x\n", sta); 3363 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 3364 onoff("Unexpected Page Request Group Index", reg, 3365 PCI_PAGE_REQ_STA_UPRGI); 3366 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 3367 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 3368 3369 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 3370 printf(" Outstanding Page Request Capacity: %u\n", reg); 3371 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 3372 printf(" Outstanding Page Request Allocation: %u\n", reg); 3373 } 3374 3375 /* XXX pci_conf_print_amd_cap */ 3376 3377 #define MEM_PBUFSIZE sizeof("999GB") 3378 3379 static void 3380 pci_conf_print_resizbar_cap(const pcireg_t *regs, int capoff, int extcapoff) 3381 { 3382 pcireg_t cap, ctl; 3383 unsigned int bars, i, n; 3384 char pbuf[MEM_PBUFSIZE]; 3385 3386 printf("\n Resizable BAR\n"); 3387 3388 /* Get Number of Resizable BARs */ 3389 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))]; 3390 bars = __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR); 3391 printf(" Number of Resizable BARs: "); 3392 if (bars <= 6) 3393 printf("%u\n", bars); 3394 else { 3395 printf("incorrect (%u)\n", bars); 3396 return; 3397 } 3398 3399 for (n = 0; n < 6; n++) { 3400 cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))]; 3401 printf(" Capability register(%u): 0x%08x\n", n, cap); 3402 if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0) 3403 continue; /* Not Used */ 3404 printf(" Acceptable BAR sizes:"); 3405 for (i = 4; i <= 23; i++) { 3406 if ((cap & (1 << i)) != 0) { 3407 humanize_number(pbuf, MEM_PBUFSIZE, 3408 (int64_t)1024 * 1024 << (i - 4), "B", 3409 #ifdef _KERNEL 3410 1); 3411 #else 3412 HN_AUTOSCALE, HN_NOSPACE); 3413 #endif 3414 printf(" %s", pbuf); 3415 } 3416 } 3417 printf("\n"); 3418 3419 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))]; 3420 printf(" Control register(%u): 0x%08x\n", n, ctl); 3421 printf(" BAR Index: %u\n", 3422 (unsigned int)__SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX)); 3423 humanize_number(pbuf, MEM_PBUFSIZE, 3424 (int64_t)1024 * 1024 3425 << __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ), 3426 "B", 3427 #ifdef _KERNEL 3428 1); 3429 #else 3430 HN_AUTOSCALE, HN_NOSPACE); 3431 #endif 3432 printf(" BAR Size: %s\n", pbuf); 3433 } 3434 } 3435 3436 static void 3437 pci_conf_print_dpa_cap(const pcireg_t *regs, int capoff, int extcapoff) 3438 { 3439 pcireg_t reg; 3440 unsigned int substmax, i; 3441 3442 printf("\n Dynamic Power Allocation\n"); 3443 3444 reg = regs[o2i(extcapoff + PCI_DPA_CAP)]; 3445 printf(" Capability register: 0x%08x\n", reg); 3446 substmax = __SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX); 3447 printf(" Substate Max: %u\n", substmax); 3448 printf(" Transition Latency Unit: "); 3449 switch (__SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) { 3450 case 0: 3451 printf("1ms\n"); 3452 break; 3453 case 1: 3454 printf("10ms\n"); 3455 break; 3456 case 2: 3457 printf("100ms\n"); 3458 break; 3459 default: 3460 printf("reserved\n"); 3461 break; 3462 } 3463 printf(" Power Allocation Scale: "); 3464 switch (__SHIFTOUT(reg, PCI_DPA_CAP_PAS)) { 3465 case 0: 3466 printf("10.0x\n"); 3467 break; 3468 case 1: 3469 printf("1.0x\n"); 3470 break; 3471 case 2: 3472 printf("0.1x\n"); 3473 break; 3474 case 3: 3475 printf("0.01x\n"); 3476 break; 3477 } 3478 printf(" Transition Latency Value 0: %u\n", 3479 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY0)); 3480 printf(" Transition Latency Value 1: %u\n", 3481 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); 3482 3483 reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; 3484 printf(" Latency Indicatior register: 0x%08x\n", reg); 3485 3486 reg = regs[o2i(extcapoff + PCI_DPA_CS)]; 3487 printf(" Status register: 0x%04x\n", reg & 0xffff); 3488 printf(" Substate Status: 0x%02x\n", 3489 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT)); 3490 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN); 3491 printf(" Control register: 0x%04x\n", reg >> 16); 3492 printf(" Substate Control: 0x%02x\n", 3493 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL)); 3494 3495 for (i = 0; i <= substmax; i++) 3496 printf(" Substate Power Allocation register %d: 0x%02x\n", 3497 i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff)); 3498 } 3499 3500 static const char * 3501 pci_conf_print_tph_req_cap_sttabloc(unsigned char val) 3502 { 3503 3504 switch (val) { 3505 case 0x0: 3506 return "Not Present"; 3507 case 0x1: 3508 return "in the TPH Requester Capability Structure"; 3509 case 0x2: 3510 return "in the MSI-X Table"; 3511 default: 3512 return "Unknown"; 3513 } 3514 } 3515 3516 static void 3517 pci_conf_print_tph_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3518 { 3519 pcireg_t reg; 3520 int size, i, j; 3521 3522 printf("\n TPH Requester Extended Capability\n"); 3523 3524 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3525 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3526 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3527 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3528 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3529 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3530 printf(" ST Table Location: %s\n", 3531 pci_conf_print_tph_req_cap_sttabloc( 3532 (unsigned char)__SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC))); 3533 size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3534 printf(" ST Table Size: %d\n", size); 3535 3536 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CTL)]; 3537 printf(" TPH Requester Control register: 0x%08x\n", reg); 3538 printf(" ST Mode Select: "); 3539 switch (__SHIFTOUT(reg, PCI_TPH_REQ_CTL_STSEL)) { 3540 case PCI_TPH_REQ_CTL_STSEL_NO: 3541 printf("No ST Mode\n"); 3542 break; 3543 case PCI_TPH_REQ_CTL_STSEL_IV: 3544 printf("Interrupt Vector Mode\n"); 3545 break; 3546 case PCI_TPH_REQ_CTL_STSEL_DS: 3547 printf("Device Specific Mode\n"); 3548 break; 3549 default: 3550 printf("(reserved vaule)\n"); 3551 break; 3552 } 3553 printf(" TPH Requester Enable: "); 3554 switch (__SHIFTOUT(reg, PCI_TPH_REQ_CTL_TPHREQEN)) { 3555 case PCI_TPH_REQ_CTL_TPHREQEN_NO: /* 0x0 */ 3556 printf("Not permitted\n"); 3557 break; 3558 case PCI_TPH_REQ_CTL_TPHREQEN_TPH: 3559 printf("TPH and not Extended TPH\n"); 3560 break; 3561 case PCI_TPH_REQ_CTL_TPHREQEN_ETPH: 3562 printf("TPH and Extended TPH"); 3563 break; 3564 default: 3565 printf("(reserved vaule)\n"); 3566 break; 3567 } 3568 3569 for (i = 0; i < size ; i += 2) { 3570 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3571 for (j = 0; j < 2 ; j++) { 3572 uint32_t entry = reg; 3573 3574 if (j != 0) 3575 entry >>= 16; 3576 entry &= 0xffff; 3577 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3578 i + j, entry); 3579 } 3580 } 3581 } 3582 3583 static void 3584 pci_conf_print_ltr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3585 { 3586 pcireg_t reg; 3587 3588 printf("\n Latency Tolerance Reporting\n"); 3589 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)]; 3590 printf(" Max Snoop Latency Register: 0x%04x\n", reg & 0xffff); 3591 printf(" Max Snoop Latency: %juns\n", 3592 (uintmax_t)(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL) 3593 * PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE)))); 3594 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg >> 16); 3595 printf(" Max No-Snoop Latency: %juns\n", 3596 (uintmax_t)(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL) 3597 * PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE)))); 3598 } 3599 3600 static void 3601 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int capoff, int extcapoff) 3602 { 3603 int pcie_capoff; 3604 pcireg_t reg; 3605 int i, maxlinkwidth; 3606 3607 printf("\n Secondary PCI Express Register\n"); 3608 3609 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3610 printf(" Link Control 3 register: 0x%08x\n", reg); 3611 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3612 onoff("Link Equalization Request Interrupt Enable", 3613 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3614 printf(" Enable Lower SKP OS Generation Vector:"); 3615 pci_print_pcie_linkspeedvector( 3616 __SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3617 printf("\n"); 3618 3619 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3620 printf(" Lane Error Status register: 0x%08x\n", reg); 3621 3622 /* Get Max Link Width */ 3623 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)){ 3624 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3625 maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3626 } else { 3627 printf("error: falied to get PCIe capablity\n"); 3628 return; 3629 } 3630 for (i = 0; i < maxlinkwidth; i++) { 3631 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3632 if (i % 2 != 0) 3633 reg >>= 16; 3634 else 3635 reg &= 0xffff; 3636 printf(" Equalization Control Register (Link %d): 0x%04x\n", 3637 i, reg); 3638 printf(" Downstream Port Transmit Preset: 0x%x\n", 3639 (pcireg_t)__SHIFTOUT(reg, 3640 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3641 printf(" Downstream Port Receive Hint: 0x%x\n", 3642 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3643 printf(" Upstream Port Transmit Preset: 0x%x\n", 3644 (pcireg_t)__SHIFTOUT(reg, 3645 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3646 printf(" Upstream Port Receive Hint: 0x%x\n", 3647 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3648 } 3649 } 3650 3651 /* XXX pci_conf_print_pmux_cap */ 3652 3653 static void 3654 pci_conf_print_pasid_cap(const pcireg_t *regs, int capoff, int extcapoff) 3655 { 3656 pcireg_t reg, cap, ctl; 3657 unsigned int num; 3658 3659 printf("\n Process Address Space ID\n"); 3660 3661 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3662 cap = reg & 0xffff; 3663 ctl = reg >> 16; 3664 printf(" PASID Capability Register: 0x%04x\n", cap); 3665 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3666 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3667 num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3668 printf(" Max PASID Width: %u\n", num); 3669 3670 printf(" PASID Control Register: 0x%04x\n", ctl); 3671 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3672 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3673 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3674 } 3675 3676 static void 3677 pci_conf_print_lnr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3678 { 3679 pcireg_t reg, cap, ctl; 3680 unsigned int num; 3681 3682 printf("\n LN Requester\n"); 3683 3684 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3685 cap = reg & 0xffff; 3686 ctl = reg >> 16; 3687 printf(" LNR Capability register: 0x%04x\n", cap); 3688 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 3689 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 3690 num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 3691 printf(" LNR Registration MAX: %u\n", num); 3692 3693 printf(" LNR Control register: 0x%04x\n", ctl); 3694 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 3695 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 3696 num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 3697 printf(" LNR Registration Limit: %u\n", num); 3698 } 3699 3700 static void 3701 pci_conf_print_dpc_pio(pcireg_t r) 3702 { 3703 onoff("Cfg Request received UR Completion", r,PCI_DPC_RPPIO_CFGUR_CPL); 3704 onoff("Cfg Request received CA Completion", r,PCI_DPC_RPPIO_CFGCA_CPL); 3705 onoff("Cfg Request Completion Timeout", r, PCI_DPC_RPPIO_CFG_CTO); 3706 onoff("I/O Request received UR Completion", r, PCI_DPC_RPPIO_IOUR_CPL); 3707 onoff("I/O Request received CA Completion", r, PCI_DPC_RPPIO_IOCA_CPL); 3708 onoff("I/O Request Completion Timeout", r, PCI_DPC_RPPIO_IO_CTO); 3709 onoff("Mem Request received UR Completion", r,PCI_DPC_RPPIO_MEMUR_CPL); 3710 onoff("Mem Request received CA Completion", r,PCI_DPC_RPPIO_MEMCA_CPL); 3711 onoff("Mem Request Completion Timeout", r, PCI_DPC_RPPIO_MEM_CTO); 3712 } 3713 3714 static void 3715 pci_conf_print_dpc_cap(const pcireg_t *regs, int capoff, int extcapoff) 3716 { 3717 pcireg_t reg, cap, ctl, stat, errsrc; 3718 const char *trigstr; 3719 bool rpext; 3720 3721 printf("\n Downstream Port Containment\n"); 3722 3723 reg = regs[o2i(extcapoff + PCI_DPC_CCR)]; 3724 cap = reg & 0xffff; 3725 ctl = reg >> 16; 3726 rpext = (reg & PCI_DPCCAP_RPEXT) ? true : false; 3727 printf(" DPC Capability register: 0x%04x\n", cap); 3728 printf(" DPC Interrupt Message Number: %02x\n", 3729 (unsigned int)(cap & PCI_DPCCAP_IMSGN)); 3730 onoff("RP Extensions for DPC", reg, PCI_DPCCAP_RPEXT); 3731 onoff("Poisoned TLP Egress Blocking Supported", reg, 3732 PCI_DPCCAP_POISONTLPEB); 3733 onoff("DPC Software Triggering Supported", reg, PCI_DPCCAP_SWTRIG); 3734 printf(" RP PIO Log Size: %u\n", 3735 (unsigned int)__SHIFTOUT(reg, PCI_DPCCAP_RPPIOLOGSZ)); 3736 onoff("DL_Active ERR_COR Signaling Supported", reg, 3737 PCI_DPCCAP_DLACTECORS); 3738 printf(" DPC Control register: 0x%04x\n", ctl); 3739 switch (__SHIFTOUT(reg, PCI_DPCCTL_TIRGEN)) { 3740 case 0: 3741 trigstr = "disabled"; 3742 break; 3743 case 1: 3744 trigstr = "enabled(ERR_FATAL)"; 3745 break; 3746 case 2: 3747 trigstr = "enabled(ERR_NONFATAL or ERR_FATAL)"; 3748 break; 3749 default: 3750 trigstr = "(reserverd)"; 3751 break; 3752 } 3753 printf(" DPC Trigger Enable: %s\n", trigstr); 3754 printf(" DPC Completion Control: %s Completion Status\n", 3755 (reg & PCI_DPCCTL_COMPCTL) 3756 ? "Unsupported Request(UR)" : "Completer Abort(CA)"); 3757 onoff("DPC Interrupt Enable", reg, PCI_DPCCTL_IE); 3758 onoff("DPC ERR_COR Enable", reg, PCI_DPCCTL_ERRCOREN); 3759 onoff("Poisoned TLP Egress Blocking Enable", reg, 3760 PCI_DPCCTL_POISONTLPEB); 3761 onoff("DPC Software Trigger", reg, PCI_DPCCTL_SWTRIG); 3762 onoff("DL_Active ERR_COR Enable", reg, PCI_DPCCTL_DLACTECOR); 3763 3764 reg = regs[o2i(extcapoff + PCI_DPC_STATESID)]; 3765 stat = reg & 0xffff; 3766 errsrc = reg >> 16; 3767 printf(" DPC Status register: 0x%04x\n", stat); 3768 onoff("DPC Trigger Status", reg, PCI_DPCSTAT_TSTAT); 3769 switch (__SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 3770 case 0: 3771 trigstr = "an unmasked uncorrectable error"; 3772 break; 3773 case 1: 3774 trigstr = "receiving an ERR_NONFATAL"; 3775 break; 3776 case 2: 3777 trigstr = "receiving an ERR_FATAL"; 3778 break; 3779 case 3: 3780 trigstr = "DPC Trigger Reason Extension field"; 3781 break; 3782 } 3783 printf(" DPC Trigger Reason: Due to %s\n", trigstr); 3784 onoff("DPC Interrupt Status", reg, PCI_DPCSTAT_ISTAT); 3785 if (rpext) 3786 onoff("DPC RP Busy", reg, PCI_DPCSTAT_RPBUSY); 3787 switch (__SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 3788 case 0: 3789 trigstr = "Due to RP PIO error"; 3790 break; 3791 case 1: 3792 trigstr = "Due to the DPC Software trigger bit"; 3793 break; 3794 default: 3795 trigstr = "(reserved)"; 3796 break; 3797 } 3798 printf(" DPC Trigger Reason Extension: %s\n", trigstr); 3799 if (rpext) 3800 printf(" RP PIO First Error Pointer: %02x\n", 3801 (unsigned int)__SHIFTOUT(reg, PCI_DPCSTAT_RPPIOFEP)); 3802 printf(" DPC Error Source ID register: 0x%04x\n", errsrc); 3803 3804 if (!rpext) 3805 return; 3806 /* 3807 * All of the following registers are implemented by a device which has 3808 * RP Extensions for DPC 3809 */ 3810 3811 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_STAT)]; 3812 printf(" RP PIO Status Register: 0x%04x\n", reg); 3813 pci_conf_print_dpc_pio(reg); 3814 3815 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_MASK)]; 3816 printf(" RP PIO Mask Register: 0x%04x\n", reg); 3817 pci_conf_print_dpc_pio(reg); 3818 3819 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SEVE)]; 3820 printf(" RP PIO Severity Register: 0x%04x\n", reg); 3821 pci_conf_print_dpc_pio(reg); 3822 3823 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SYSERR)]; 3824 printf(" RP PIO SysError Register: 0x%04x\n", reg); 3825 pci_conf_print_dpc_pio(reg); 3826 3827 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_EXCPT)]; 3828 printf(" RP PIO Exception Register: 0x%04x\n", reg); 3829 pci_conf_print_dpc_pio(reg); 3830 3831 printf(" RP PIO Header Log Register: start from 0x%03x\n", 3832 extcapoff + PCI_DPC_RPPIO_HLOG); 3833 printf(" RP PIO ImpSpec Log Register: start from 0x%03x\n", 3834 extcapoff + PCI_DPC_RPPIO_IMPSLOG); 3835 printf(" RP PIO TPL Prefix Log Register: start from 0x%03x\n", 3836 extcapoff + PCI_DPC_RPPIO_TLPPLOG); 3837 } 3838 3839 3840 static int 3841 pci_conf_l1pm_cap_tposcale(unsigned char scale) 3842 { 3843 3844 /* Return scale in us */ 3845 switch (scale) { 3846 case 0x0: 3847 return 2; 3848 case 0x1: 3849 return 10; 3850 case 0x2: 3851 return 100; 3852 default: 3853 return -1; 3854 } 3855 } 3856 3857 static void 3858 pci_conf_print_l1pm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3859 { 3860 pcireg_t reg; 3861 int scale, val; 3862 3863 printf("\n L1 PM Substates\n"); 3864 3865 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 3866 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 3867 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 3868 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 3869 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 3870 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 3871 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 3872 printf(" Port Common Mode Restore Time: %uus\n", 3873 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 3874 scale = pci_conf_l1pm_cap_tposcale( 3875 __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 3876 val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 3877 printf(" Port T_POWER_ON: "); 3878 if (scale == -1) 3879 printf("unknown\n"); 3880 else 3881 printf("%dus\n", val * scale); 3882 3883 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 3884 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 3885 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 3886 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 3887 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 3888 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 3889 printf(" Common Mode Restore Time: %uus\n", 3890 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 3891 scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 3892 val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 3893 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 3894 3895 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 3896 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 3897 scale = pci_conf_l1pm_cap_tposcale( 3898 __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 3899 val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 3900 printf(" T_POWER_ON: "); 3901 if (scale == -1) 3902 printf("unknown\n"); 3903 else 3904 printf("%dus\n", val * scale); 3905 } 3906 3907 static void 3908 pci_conf_print_ptm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3909 { 3910 pcireg_t reg; 3911 uint32_t val; 3912 3913 printf("\n Precision Time Management\n"); 3914 3915 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 3916 printf(" PTM Capability register: 0x%08x\n", reg); 3917 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 3918 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 3919 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 3920 printf(" Local Clock Granularity: "); 3921 val = __SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 3922 switch (val) { 3923 case 0: 3924 printf("Not implemented\n"); 3925 break; 3926 case 0xffff: 3927 printf("> 254ns\n"); 3928 break; 3929 default: 3930 printf("%uns\n", val); 3931 break; 3932 } 3933 3934 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 3935 printf(" PTM Control register: 0x%08x\n", reg); 3936 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 3937 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 3938 printf(" Effective Granularity: "); 3939 val = __SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 3940 switch (val) { 3941 case 0: 3942 printf("Unknown\n"); 3943 break; 3944 case 0xffff: 3945 printf("> 254ns\n"); 3946 break; 3947 default: 3948 printf("%uns\n", val); 3949 break; 3950 } 3951 } 3952 3953 /* XXX pci_conf_print_mpcie_cap */ 3954 /* XXX pci_conf_print_frsq_cap */ 3955 /* XXX pci_conf_print_rtr_cap */ 3956 /* XXX pci_conf_print_desigvndsp_cap */ 3957 /* XXX pci_conf_print_vf_resizbar_cap */ 3958 /* XXX pci_conf_print_hierarchyid_cap */ 3959 /* XXX pci_conf_print_npem_cap */ 3960 3961 #undef MS 3962 #undef SM 3963 #undef RW 3964 3965 static struct { 3966 pcireg_t cap; 3967 const char *name; 3968 void (*printfunc)(const pcireg_t *, int, int); 3969 } pci_extcaptab[] = { 3970 { 0, "reserved", 3971 NULL }, 3972 { PCI_EXTCAP_AER, "Advanced Error Reporting", 3973 pci_conf_print_aer_cap }, 3974 { PCI_EXTCAP_VC, "Virtual Channel", 3975 pci_conf_print_vc_cap }, 3976 { PCI_EXTCAP_SERNUM, "Device Serial Number", 3977 pci_conf_print_sernum_cap }, 3978 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 3979 pci_conf_print_pwrbdgt_cap }, 3980 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 3981 pci_conf_print_rclink_dcl_cap }, 3982 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 3983 NULL }, 3984 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 3985 pci_conf_print_rcec_assoc_cap }, 3986 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 3987 NULL }, 3988 { PCI_EXTCAP_VC2, "Virtual Channel", 3989 NULL }, 3990 { PCI_EXTCAP_RCRB, "RCRB Header", 3991 NULL }, 3992 { PCI_EXTCAP_VENDOR, "Vendor Unique", 3993 NULL }, 3994 { PCI_EXTCAP_CAC, "Configuration Access Correction", 3995 NULL }, 3996 { PCI_EXTCAP_ACS, "Access Control Services", 3997 pci_conf_print_acs_cap }, 3998 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 3999 pci_conf_print_ari_cap }, 4000 { PCI_EXTCAP_ATS, "Address Translation Services", 4001 pci_conf_print_ats_cap }, 4002 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 4003 pci_conf_print_sriov_cap }, 4004 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 4005 NULL }, 4006 { PCI_EXTCAP_MCAST, "Multicast", 4007 pci_conf_print_multicast_cap }, 4008 { PCI_EXTCAP_PAGE_REQ, "Page Request", 4009 pci_conf_print_page_req_cap }, 4010 { PCI_EXTCAP_AMD, "Reserved for AMD", 4011 NULL }, 4012 { PCI_EXTCAP_RESIZBAR, "Resizable BAR", 4013 pci_conf_print_resizbar_cap }, 4014 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 4015 pci_conf_print_dpa_cap }, 4016 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 4017 pci_conf_print_tph_req_cap }, 4018 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 4019 pci_conf_print_ltr_cap }, 4020 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 4021 pci_conf_print_sec_pcie_cap }, 4022 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 4023 NULL }, 4024 { PCI_EXTCAP_PASID, "Process Address Space ID", 4025 pci_conf_print_pasid_cap }, 4026 { PCI_EXTCAP_LNR, "LN Requester", 4027 pci_conf_print_lnr_cap }, 4028 { PCI_EXTCAP_DPC, "Downstream Port Containment", 4029 pci_conf_print_dpc_cap }, 4030 { PCI_EXTCAP_L1PM, "L1 PM Substates", 4031 pci_conf_print_l1pm_cap }, 4032 { PCI_EXTCAP_PTM, "Precision Time Management", 4033 pci_conf_print_ptm_cap }, 4034 { PCI_EXTCAP_MPCIE, "M-PCIe", 4035 NULL }, 4036 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 4037 NULL }, 4038 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 4039 NULL }, 4040 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 4041 NULL }, 4042 { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", 4043 NULL }, 4044 { PCI_EXTCAP_HIERARCHYID, "Hierarchy ID", 4045 NULL }, 4046 { PCI_EXTCAP_NPEM, "Native PCIe Enclosure Management", 4047 NULL }, 4048 }; 4049 4050 static int 4051 pci_conf_find_extcap(const pcireg_t *regs, int capoff, unsigned int capid, 4052 int *offsetp) 4053 { 4054 int off; 4055 pcireg_t rval; 4056 4057 for (off = PCI_EXTCAPLIST_BASE; 4058 off != 0; 4059 off = PCI_EXTCAPLIST_NEXT(rval)) { 4060 rval = regs[o2i(off)]; 4061 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 4062 if (offsetp != NULL) 4063 *offsetp = off; 4064 return 1; 4065 } 4066 } 4067 return 0; 4068 } 4069 4070 static void 4071 pci_conf_print_extcaplist( 4072 #ifdef _KERNEL 4073 pci_chipset_tag_t pc, pcitag_t tag, 4074 #endif 4075 const pcireg_t *regs, int capoff) 4076 { 4077 int off; 4078 pcireg_t foundcap; 4079 pcireg_t rval; 4080 bool foundtable[__arraycount(pci_extcaptab)]; 4081 unsigned int i; 4082 4083 /* Check Extended capability structure */ 4084 off = PCI_EXTCAPLIST_BASE; 4085 rval = regs[o2i(off)]; 4086 if (rval == 0xffffffff || rval == 0) 4087 return; 4088 4089 /* Clear table */ 4090 for (i = 0; i < __arraycount(pci_extcaptab); i++) 4091 foundtable[i] = false; 4092 4093 /* Print extended capability register's offset and the type first */ 4094 for (;;) { 4095 printf(" Extended Capability Register at 0x%02x\n", off); 4096 4097 foundcap = PCI_EXTCAPLIST_CAP(rval); 4098 printf(" type: 0x%04x (", foundcap); 4099 if (foundcap < __arraycount(pci_extcaptab)) { 4100 printf("%s)\n", pci_extcaptab[foundcap].name); 4101 /* Mark as found */ 4102 foundtable[foundcap] = true; 4103 } else 4104 printf("unknown)\n"); 4105 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 4106 4107 off = PCI_EXTCAPLIST_NEXT(rval); 4108 if (off == 0) 4109 break; 4110 else if (off <= PCI_CONF_SIZE) { 4111 printf(" next pointer: 0x%03x (incorrect)\n", off); 4112 return; 4113 } 4114 rval = regs[o2i(off)]; 4115 } 4116 4117 /* 4118 * And then, print the detail of each capability registers 4119 * in capability value's order. 4120 */ 4121 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 4122 if (foundtable[i] == false) 4123 continue; 4124 4125 /* 4126 * The type was found. Search capability list again and 4127 * print all capabilities that the capabiliy type is 4128 * the same. 4129 */ 4130 if (pci_conf_find_extcap(regs, capoff, i, &off) == 0) 4131 continue; 4132 rval = regs[o2i(off)]; 4133 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 4134 || (pci_extcaptab[i].printfunc == NULL)) 4135 continue; 4136 4137 pci_extcaptab[i].printfunc(regs, capoff, off); 4138 4139 } 4140 } 4141 4142 /* Print the Secondary Status Register. */ 4143 static void 4144 pci_conf_print_ssr(pcireg_t rval) 4145 { 4146 pcireg_t devsel; 4147 4148 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 4149 onoff("66 MHz capable", rval, __BIT(5)); 4150 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 4151 onoff("Fast back-to-back capable", rval, __BIT(7)); 4152 onoff("Data parity error detected", rval, __BIT(8)); 4153 4154 printf(" DEVSEL timing: "); 4155 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 4156 switch (devsel) { 4157 case 0: 4158 printf("fast"); 4159 break; 4160 case 1: 4161 printf("medium"); 4162 break; 4163 case 2: 4164 printf("slow"); 4165 break; 4166 default: 4167 printf("unknown/reserved"); /* XXX */ 4168 break; 4169 } 4170 printf(" (0x%x)\n", devsel); 4171 4172 onoff("Signalled target abort", rval, __BIT(11)); 4173 onoff("Received target abort", rval, __BIT(12)); 4174 onoff("Received master abort", rval, __BIT(13)); 4175 onoff("Received system error", rval, __BIT(14)); 4176 onoff("Detected parity error", rval, __BIT(15)); 4177 } 4178 4179 static void 4180 pci_conf_print_type0( 4181 #ifdef _KERNEL 4182 pci_chipset_tag_t pc, pcitag_t tag, 4183 #endif 4184 const pcireg_t *regs) 4185 { 4186 int off, width; 4187 pcireg_t rval; 4188 const char *str; 4189 4190 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 4191 #ifdef _KERNEL 4192 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4193 #else 4194 width = pci_conf_print_bar(regs, off, NULL); 4195 #endif 4196 } 4197 4198 printf(" Cardbus CIS Pointer: 0x%08x\n", 4199 regs[o2i(PCI_CARDBUS_CIS_REG)]); 4200 4201 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 4202 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4203 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4204 4205 rval = regs[o2i(PCI_MAPREG_ROM)]; 4206 printf(" Expansion ROM Base Address Register: 0x%08x\n", rval); 4207 printf(" base: 0x%08x\n", (uint32_t)PCI_MAPREG_ROM_ADDR(rval)); 4208 onoff("Expansion ROM Enable", rval, PCI_MAPREG_ROM_ENABLE); 4209 printf(" Validation Status: "); 4210 switch (__SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_STAT)) { 4211 case PCI_MAPREG_ROM_VSTAT_NOTSUPP: 4212 str = "Validation not supported"; 4213 break; 4214 case PCI_MAPREG_ROM_VSTAT_INPROG: 4215 str = "Validation in Progress"; 4216 break; 4217 case PCI_MAPREG_ROM_VSTAT_VPASS: 4218 str = "Validation Pass. " 4219 "Valid contents, trust test was not performed"; 4220 break; 4221 case PCI_MAPREG_ROM_VSTAT_VPASSTRUST: 4222 str = "Validation Pass. Valid and trusted contents"; 4223 break; 4224 case PCI_MAPREG_ROM_VSTAT_VFAIL: 4225 str = "Validation Fail. Invalid contents"; 4226 break; 4227 case PCI_MAPREG_ROM_VSTAT_VFAILUNTRUST: 4228 str = "Validation Fail. Valid but untrusted contents"; 4229 break; 4230 case PCI_MAPREG_ROM_VSTAT_WPASS: 4231 str = "Warning Pass. Validation passed with warning. " 4232 "Valid contents, trust test was not performed"; 4233 break; 4234 case PCI_MAPREG_ROM_VSTAT_WPASSTRUST: 4235 str = "Warning Pass. Validation passed with warning. " 4236 "Valid and trusted contents"; 4237 break; 4238 } 4239 printf("%s\n", str); 4240 printf(" Validation Details: 0x%x\n", 4241 (uint32_t)__SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_DETAIL)); 4242 4243 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4244 printf(" Capability list pointer: 0x%02x\n", 4245 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4246 else 4247 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4248 4249 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 4250 4251 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4252 printf(" Maximum Latency: 0x%02x\n", PCI_MAX_LAT(rval)); 4253 printf(" Minimum Grant: 0x%02x\n", PCI_MIN_GNT(rval)); 4254 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 4255 switch (PCI_INTERRUPT_PIN(rval)) { 4256 case PCI_INTERRUPT_PIN_NONE: 4257 printf("(none)"); 4258 break; 4259 case PCI_INTERRUPT_PIN_A: 4260 printf("(pin A)"); 4261 break; 4262 case PCI_INTERRUPT_PIN_B: 4263 printf("(pin B)"); 4264 break; 4265 case PCI_INTERRUPT_PIN_C: 4266 printf("(pin C)"); 4267 break; 4268 case PCI_INTERRUPT_PIN_D: 4269 printf("(pin D)"); 4270 break; 4271 default: 4272 printf("(? ? ?)"); 4273 break; 4274 } 4275 printf("\n"); 4276 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 4277 } 4278 4279 static void 4280 pci_conf_print_type1( 4281 #ifdef _KERNEL 4282 pci_chipset_tag_t pc, pcitag_t tag, 4283 #endif 4284 const pcireg_t *regs) 4285 { 4286 int off, width; 4287 pcireg_t rval; 4288 uint32_t base, limit; 4289 uint32_t base_h, limit_h; 4290 uint64_t pbase, plimit; 4291 int use_upper; 4292 4293 /* 4294 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 4295 * Bridge chip documentation, and may not be correct with 4296 * respect to various standards. (XXX) 4297 */ 4298 4299 for (off = 0x10; off < 0x18; off += width) { 4300 #ifdef _KERNEL 4301 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4302 #else 4303 width = pci_conf_print_bar(regs, off, NULL); 4304 #endif 4305 } 4306 4307 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4308 printf(" Primary bus number: 0x%02x\n", 4309 PCI_BRIDGE_BUS_PRIMARY(rval)); 4310 printf(" Secondary bus number: 0x%02x\n", 4311 PCI_BRIDGE_BUS_SECONDARY(rval)); 4312 printf(" Subordinate bus number: 0x%02x\n", 4313 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 4314 printf(" Secondary bus latency timer: 0x%02x\n", 4315 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 4316 4317 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 4318 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 4319 4320 /* I/O region */ 4321 printf(" I/O region:\n"); 4322 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 4323 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 4324 if (PCI_BRIDGE_IO_32BITS(rval)) 4325 use_upper = 1; 4326 else 4327 use_upper = 0; 4328 onoff("32bit I/O", rval, use_upper); 4329 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 4330 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 4331 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 4332 limit |= 0x00000fff; 4333 4334 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 4335 base_h = (rval >> 0) & 0xffff; 4336 limit_h = (rval >> 16) & 0xffff; 4337 printf(" base upper 16 bits register: 0x%04x\n", base_h); 4338 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 4339 4340 if (use_upper == 1) { 4341 base |= base_h << 16; 4342 limit |= limit_h << 16; 4343 } 4344 if (base < limit) { 4345 if (use_upper == 1) 4346 printf(" range: 0x%08x-0x%08x\n", base, limit); 4347 else 4348 printf(" range: 0x%04x-0x%04x\n", base, limit); 4349 } else 4350 printf(" range: not set\n"); 4351 4352 /* Non-prefetchable memory region */ 4353 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 4354 printf(" Memory region:\n"); 4355 printf(" base register: 0x%04x\n", 4356 (rval >> 0) & 0xffff); 4357 printf(" limit register: 0x%04x\n", 4358 (rval >> 16) & 0xffff); 4359 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 4360 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 4361 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 4362 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 4363 if (base < limit) 4364 printf(" range: 0x%08x-0x%08x\n", base, limit); 4365 else 4366 printf(" range: not set\n"); 4367 4368 /* Prefetchable memory region */ 4369 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 4370 printf(" Prefetchable memory region:\n"); 4371 printf(" base register: 0x%04x\n", 4372 (rval >> 0) & 0xffff); 4373 printf(" limit register: 0x%04x\n", 4374 (rval >> 16) & 0xffff); 4375 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 4376 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 4377 printf(" base upper 32 bits register: 0x%08x\n", 4378 base_h); 4379 printf(" limit upper 32 bits register: 0x%08x\n", 4380 limit_h); 4381 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 4382 use_upper = 1; 4383 else 4384 use_upper = 0; 4385 onoff("64bit memory address", rval, use_upper); 4386 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 4387 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 4388 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 4389 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 4390 if (use_upper == 1) { 4391 pbase |= (uint64_t)base_h << 32; 4392 plimit |= (uint64_t)limit_h << 32; 4393 } 4394 if (pbase < plimit) { 4395 if (use_upper == 1) 4396 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 4397 "\n", pbase, plimit); 4398 else 4399 printf(" range: 0x%08x-0x%08x\n", 4400 (uint32_t)pbase, (uint32_t)plimit); 4401 } else 4402 printf(" range: not set\n"); 4403 4404 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4405 printf(" Capability list pointer: 0x%02x\n", 4406 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4407 else 4408 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4409 4410 /* XXX */ 4411 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 4412 4413 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4414 printf(" Interrupt line: 0x%02x\n", 4415 (rval >> 0) & 0xff); 4416 printf(" Interrupt pin: 0x%02x ", 4417 (rval >> 8) & 0xff); 4418 switch ((rval >> 8) & 0xff) { 4419 case PCI_INTERRUPT_PIN_NONE: 4420 printf("(none)"); 4421 break; 4422 case PCI_INTERRUPT_PIN_A: 4423 printf("(pin A)"); 4424 break; 4425 case PCI_INTERRUPT_PIN_B: 4426 printf("(pin B)"); 4427 break; 4428 case PCI_INTERRUPT_PIN_C: 4429 printf("(pin C)"); 4430 break; 4431 case PCI_INTERRUPT_PIN_D: 4432 printf("(pin D)"); 4433 break; 4434 default: 4435 printf("(? ? ?)"); 4436 break; 4437 } 4438 printf("\n"); 4439 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 4440 & PCI_BRIDGE_CONTROL_MASK; 4441 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 4442 onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE); 4443 onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR); 4444 onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA); 4445 onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA); 4446 onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT); 4447 onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR); 4448 onoff("Fast back-to-back capable", rval,PCI_BRIDGE_CONTROL_SECFASTB2B); 4449 } 4450 4451 static void 4452 pci_conf_print_type2( 4453 #ifdef _KERNEL 4454 pci_chipset_tag_t pc, pcitag_t tag, 4455 #endif 4456 const pcireg_t *regs) 4457 { 4458 pcireg_t rval; 4459 4460 /* 4461 * XXX these need to be printed in more detail, need to be 4462 * XXX checked against specs/docs, etc. 4463 * 4464 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 4465 * controller chip documentation, and may not be correct with 4466 * respect to various standards. (XXX) 4467 */ 4468 4469 #ifdef _KERNEL 4470 pci_conf_print_bar(pc, tag, regs, 0x10, 4471 "CardBus socket/ExCA registers"); 4472 #else 4473 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 4474 #endif 4475 4476 /* Capability list pointer and secondary status register */ 4477 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 4478 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4479 printf(" Capability list pointer: 0x%02x\n", 4480 PCI_CAPLIST_PTR(rval)); 4481 else 4482 printf(" Reserved @ 0x14: 0x%04x\n", 4483 (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0))); 4484 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 4485 4486 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4487 printf(" PCI bus number: 0x%02x\n", 4488 (rval >> 0) & 0xff); 4489 printf(" CardBus bus number: 0x%02x\n", 4490 (rval >> 8) & 0xff); 4491 printf(" Subordinate bus number: 0x%02x\n", 4492 (rval >> 16) & 0xff); 4493 printf(" CardBus latency timer: 0x%02x\n", 4494 (rval >> 24) & 0xff); 4495 4496 /* XXX Print more prettily */ 4497 printf(" CardBus memory region 0:\n"); 4498 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 4499 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 4500 printf(" CardBus memory region 1:\n"); 4501 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 4502 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 4503 printf(" CardBus I/O region 0:\n"); 4504 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 4505 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 4506 printf(" CardBus I/O region 1:\n"); 4507 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 4508 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 4509 4510 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4511 printf(" Interrupt line: 0x%02x\n", 4512 (rval >> 0) & 0xff); 4513 printf(" Interrupt pin: 0x%02x ", 4514 (rval >> 8) & 0xff); 4515 switch ((rval >> 8) & 0xff) { 4516 case PCI_INTERRUPT_PIN_NONE: 4517 printf("(none)"); 4518 break; 4519 case PCI_INTERRUPT_PIN_A: 4520 printf("(pin A)"); 4521 break; 4522 case PCI_INTERRUPT_PIN_B: 4523 printf("(pin B)"); 4524 break; 4525 case PCI_INTERRUPT_PIN_C: 4526 printf("(pin C)"); 4527 break; 4528 case PCI_INTERRUPT_PIN_D: 4529 printf("(pin D)"); 4530 break; 4531 default: 4532 printf("(? ? ?)"); 4533 break; 4534 } 4535 printf("\n"); 4536 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> 16) & 0xffff; 4537 printf(" Bridge control register: 0x%04x\n", rval); 4538 onoff("Parity error response", rval, __BIT(0)); 4539 onoff("SERR# enable", rval, __BIT(1)); 4540 onoff("ISA enable", rval, __BIT(2)); 4541 onoff("VGA enable", rval, __BIT(3)); 4542 onoff("Master abort mode", rval, __BIT(5)); 4543 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 4544 onoff("Functional interrupts routed by ExCA registers", rval, 4545 __BIT(7)); 4546 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 4547 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 4548 onoff("Write posting enable", rval, __BIT(10)); 4549 4550 rval = regs[o2i(0x40)]; 4551 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4552 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4553 4554 #ifdef _KERNEL 4555 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers"); 4556 #else 4557 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 4558 #endif 4559 } 4560 4561 void 4562 pci_conf_print( 4563 #ifdef _KERNEL 4564 pci_chipset_tag_t pc, pcitag_t tag, 4565 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 4566 #else 4567 int pcifd, u_int bus, u_int dev, u_int func 4568 #endif 4569 ) 4570 { 4571 pcireg_t regs[o2i(PCI_EXTCONF_SIZE)]; 4572 int off, capoff, endoff, hdrtype; 4573 const char *type_name; 4574 #ifdef _KERNEL 4575 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 4576 #else 4577 void (*type_printfn)(const pcireg_t *); 4578 #endif 4579 4580 printf("PCI configuration registers:\n"); 4581 4582 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 4583 #ifdef _KERNEL 4584 regs[o2i(off)] = pci_conf_read(pc, tag, off); 4585 #else 4586 if (pcibus_conf_read(pcifd, bus, dev, func, off, 4587 ®s[o2i(off)]) == -1) 4588 regs[o2i(off)] = 0; 4589 #endif 4590 } 4591 4592 /* common header */ 4593 printf(" Common header:\n"); 4594 pci_conf_print_regs(regs, 0, 16); 4595 4596 printf("\n"); 4597 #ifdef _KERNEL 4598 pci_conf_print_common(pc, tag, regs); 4599 #else 4600 pci_conf_print_common(regs); 4601 #endif 4602 printf("\n"); 4603 4604 /* type-dependent header */ 4605 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 4606 switch (hdrtype) { /* XXX make a table, eventually */ 4607 case 0: 4608 /* Standard device header */ 4609 type_name = "\"normal\" device"; 4610 type_printfn = &pci_conf_print_type0; 4611 capoff = PCI_CAPLISTPTR_REG; 4612 endoff = 64; 4613 break; 4614 case 1: 4615 /* PCI-PCI bridge header */ 4616 type_name = "PCI-PCI bridge"; 4617 type_printfn = &pci_conf_print_type1; 4618 capoff = PCI_CAPLISTPTR_REG; 4619 endoff = 64; 4620 break; 4621 case 2: 4622 /* PCI-CardBus bridge header */ 4623 type_name = "PCI-CardBus bridge"; 4624 type_printfn = &pci_conf_print_type2; 4625 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 4626 endoff = 72; 4627 break; 4628 default: 4629 type_name = NULL; 4630 type_printfn = 0; 4631 capoff = -1; 4632 endoff = 64; 4633 break; 4634 } 4635 printf(" Type %d ", hdrtype); 4636 if (type_name != NULL) 4637 printf("(%s) ", type_name); 4638 printf("header:\n"); 4639 pci_conf_print_regs(regs, 16, endoff); 4640 printf("\n"); 4641 if (type_printfn) { 4642 #ifdef _KERNEL 4643 (*type_printfn)(pc, tag, regs); 4644 #else 4645 (*type_printfn)(regs); 4646 #endif 4647 } else 4648 printf(" Don't know how to pretty-print type %d header.\n", 4649 hdrtype); 4650 printf("\n"); 4651 4652 /* capability list, if present */ 4653 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4654 && (capoff > 0)) { 4655 #ifdef _KERNEL 4656 pci_conf_print_caplist(pc, tag, regs, capoff); 4657 #else 4658 pci_conf_print_caplist(regs, capoff); 4659 #endif 4660 printf("\n"); 4661 } 4662 4663 /* device-dependent header */ 4664 printf(" Device-dependent header:\n"); 4665 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 4666 printf("\n"); 4667 #ifdef _KERNEL 4668 if (printfn) 4669 (*printfn)(pc, tag, regs); 4670 else 4671 printf(" Don't know how to pretty-print device-dependent header.\n"); 4672 printf("\n"); 4673 #endif /* _KERNEL */ 4674 4675 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 4676 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 4677 return; 4678 4679 #ifdef _KERNEL 4680 pci_conf_print_extcaplist(pc, tag, regs, capoff); 4681 #else 4682 pci_conf_print_extcaplist(regs, capoff); 4683 #endif 4684 printf("\n"); 4685 4686 /* Extended Configuration Space, if present */ 4687 printf(" Extended Configuration Space:\n"); 4688 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 4689 } 4690
Indexes created Fri Sep 26 20:09:58 GMT 2025