pci_subr.c revision 1.197
1 /* $NetBSD: pci_subr.c,v 1.197 2017/12/18 04:48:28 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.197 2017/12/18 04:48:28 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdarg.h> 58 #include <stdbool.h> 59 #include <stdio.h> 60 #include <stdlib.h> 61 #include <string.h> 62 #endif 63 64 #include <dev/pci/pcireg.h> 65 #ifdef _KERNEL 66 #include <dev/pci/pcivar.h> 67 #else 68 #include <dev/pci/pci_verbose.h> 69 #include <dev/pci/pcidevs.h> 70 #include <dev/pci/pcidevs_data.h> 71 #endif 72 73 static int pci_conf_find_cap(const pcireg_t *, int, unsigned int, int *); 74 static void pci_conf_print_pcie_power(uint8_t, unsigned int); 75 76 /* 77 * Descriptions of known PCI classes and subclasses. 78 * 79 * Subclasses are described in the same way as classes, but have a 80 * NULL subclass pointer. 81 */ 82 struct pci_class { 83 const char *name; 84 u_int val; /* as wide as pci_{,sub}class_t */ 85 const struct pci_class *subclasses; 86 }; 87 88 /* 89 * Class 0x00. 90 * Before rev. 2.0. 91 */ 92 static const struct pci_class pci_subclass_prehistoric[] = { 93 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 94 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 95 { NULL, 0, NULL, }, 96 }; 97 98 /* 99 * Class 0x01. 100 * Mass storage controller 101 */ 102 103 /* ATA programming interface */ 104 static const struct pci_class pci_interface_ata[] = { 105 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 106 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 107 { NULL, 0, NULL, }, 108 }; 109 110 /* SATA programming interface */ 111 static const struct pci_class pci_interface_sata[] = { 112 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 113 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 114 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 115 { NULL, 0, NULL, }, 116 }; 117 118 /* Flash programming interface */ 119 static const struct pci_class pci_interface_nvm[] = { 120 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 121 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 122 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 123 { NULL, 0, NULL, }, 124 }; 125 126 /* Subclasses */ 127 static const struct pci_class pci_subclass_mass_storage[] = { 128 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 129 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 130 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 131 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 132 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 133 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 134 pci_interface_ata, }, 135 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 136 pci_interface_sata, }, 137 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 138 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 139 pci_interface_nvm, }, 140 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 141 { NULL, 0, NULL, }, 142 }; 143 144 /* 145 * Class 0x02. 146 * Network controller. 147 */ 148 static const struct pci_class pci_subclass_network[] = { 149 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 150 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 151 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 152 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 153 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 154 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 155 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 156 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 157 { NULL, 0, NULL, }, 158 }; 159 160 /* 161 * Class 0x03. 162 * Display controller. 163 */ 164 165 /* VGA programming interface */ 166 static const struct pci_class pci_interface_vga[] = { 167 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 168 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 169 { NULL, 0, NULL, }, 170 }; 171 /* Subclasses */ 172 static const struct pci_class pci_subclass_display[] = { 173 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 174 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 175 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 176 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 177 { NULL, 0, NULL, }, 178 }; 179 180 /* 181 * Class 0x04. 182 * Multimedia device. 183 */ 184 static const struct pci_class pci_subclass_multimedia[] = { 185 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 186 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 187 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 188 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 189 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 190 { NULL, 0, NULL, }, 191 }; 192 193 /* 194 * Class 0x05. 195 * Memory controller. 196 */ 197 static const struct pci_class pci_subclass_memory[] = { 198 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 199 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 200 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 201 { NULL, 0, NULL, }, 202 }; 203 204 /* 205 * Class 0x06. 206 * Bridge device. 207 */ 208 209 /* PCI bridge programming interface */ 210 static const struct pci_class pci_interface_pcibridge[] = { 211 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 212 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 213 { NULL, 0, NULL, }, 214 }; 215 216 /* Semi-transparent PCI-to-PCI bridge programming interface */ 217 static const struct pci_class pci_interface_stpci[] = { 218 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 219 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 220 { NULL, 0, NULL, }, 221 }; 222 223 /* Advanced Switching programming interface */ 224 static const struct pci_class pci_interface_advsw[] = { 225 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 226 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 227 { NULL, 0, NULL, }, 228 }; 229 230 /* Subclasses */ 231 static const struct pci_class pci_subclass_bridge[] = { 232 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 233 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 234 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 235 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 236 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 237 pci_interface_pcibridge, }, 238 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 239 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 240 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 241 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 242 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 243 pci_interface_stpci, }, 244 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 245 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 246 pci_interface_advsw, }, 247 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 248 { NULL, 0, NULL, }, 249 }; 250 251 /* 252 * Class 0x07. 253 * Simple communications controller. 254 */ 255 256 /* Serial controller programming interface */ 257 static const struct pci_class pci_interface_serial[] = { 258 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 259 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 260 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 261 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 262 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 263 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 264 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 265 { NULL, 0, NULL, }, 266 }; 267 268 /* Parallel controller programming interface */ 269 static const struct pci_class pci_interface_parallel[] = { 270 { "", PCI_INTERFACE_PARALLEL, NULL,}, 271 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 272 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 273 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 274 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 275 { NULL, 0, NULL,}, 276 }; 277 278 /* Modem programming interface */ 279 static const struct pci_class pci_interface_modem[] = { 280 { "", PCI_INTERFACE_MODEM, NULL,}, 281 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 282 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 283 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 284 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 285 { NULL, 0, NULL,}, 286 }; 287 288 /* Subclasses */ 289 static const struct pci_class pci_subclass_communications[] = { 290 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 291 pci_interface_serial, }, 292 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 293 pci_interface_parallel, }, 294 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 295 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 296 pci_interface_modem, }, 297 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 298 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 299 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 300 { NULL, 0, NULL,}, 301 }; 302 303 /* 304 * Class 0x08. 305 * Base system peripheral. 306 */ 307 308 /* PIC programming interface */ 309 static const struct pci_class pci_interface_pic[] = { 310 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 311 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 312 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 313 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 314 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 315 { NULL, 0, NULL, }, 316 }; 317 318 /* DMA programming interface */ 319 static const struct pci_class pci_interface_dma[] = { 320 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 321 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 322 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 323 { NULL, 0, NULL, }, 324 }; 325 326 /* Timer programming interface */ 327 static const struct pci_class pci_interface_tmr[] = { 328 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 329 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 330 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 331 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 332 { NULL, 0, NULL, }, 333 }; 334 335 /* RTC programming interface */ 336 static const struct pci_class pci_interface_rtc[] = { 337 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 338 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 339 { NULL, 0, NULL, }, 340 }; 341 342 /* Subclasses */ 343 static const struct pci_class pci_subclass_system[] = { 344 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 345 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 346 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 347 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 348 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 349 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 350 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 351 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 352 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 353 { NULL, 0, NULL, }, 354 }; 355 356 /* 357 * Class 0x09. 358 * Input device. 359 */ 360 361 /* Gameport programming interface */ 362 static const struct pci_class pci_interface_game[] = { 363 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 364 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 365 { NULL, 0, NULL, }, 366 }; 367 368 /* Subclasses */ 369 static const struct pci_class pci_subclass_input[] = { 370 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 371 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 372 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 373 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 374 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 375 pci_interface_game, }, 376 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 377 { NULL, 0, NULL, }, 378 }; 379 380 /* 381 * Class 0x0a. 382 * Docking station. 383 */ 384 static const struct pci_class pci_subclass_dock[] = { 385 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 386 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 387 { NULL, 0, NULL, }, 388 }; 389 390 /* 391 * Class 0x0b. 392 * Processor. 393 */ 394 static const struct pci_class pci_subclass_processor[] = { 395 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 396 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 397 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 398 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 399 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 400 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 401 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 402 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 403 { NULL, 0, NULL, }, 404 }; 405 406 /* 407 * Class 0x0c. 408 * Serial bus controller. 409 */ 410 411 /* IEEE1394 programming interface */ 412 static const struct pci_class pci_interface_ieee1394[] = { 413 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 414 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 415 { NULL, 0, NULL,}, 416 }; 417 418 /* USB programming interface */ 419 static const struct pci_class pci_interface_usb[] = { 420 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 421 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 422 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 423 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 424 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 425 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 426 { NULL, 0, NULL, }, 427 }; 428 429 /* IPMI programming interface */ 430 static const struct pci_class pci_interface_ipmi[] = { 431 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,}, 432 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,}, 433 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,}, 434 { NULL, 0, NULL,}, 435 }; 436 437 /* Subclasses */ 438 static const struct pci_class pci_subclass_serialbus[] = { 439 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 440 pci_interface_ieee1394, }, 441 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 442 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 443 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 444 pci_interface_usb, }, 445 /* XXX Fiber Channel/_FIBRECHANNEL */ 446 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 447 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 448 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 449 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 450 pci_interface_ipmi, }, 451 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 452 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 453 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 454 { NULL, 0, NULL, }, 455 }; 456 457 /* 458 * Class 0x0d. 459 * Wireless Controller. 460 */ 461 static const struct pci_class pci_subclass_wireless[] = { 462 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 463 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 464 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 465 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 466 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 467 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 468 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 469 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 470 { NULL, 0, NULL, }, 471 }; 472 473 /* 474 * Class 0x0e. 475 * Intelligent IO controller. 476 */ 477 478 /* Intelligent IO programming interface */ 479 static const struct pci_class pci_interface_i2o[] = { 480 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,}, 481 { NULL, 0, NULL,}, 482 }; 483 484 /* Subclasses */ 485 static const struct pci_class pci_subclass_i2o[] = { 486 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 487 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 488 { NULL, 0, NULL, }, 489 }; 490 491 /* 492 * Class 0x0f. 493 * Satellite communication controller. 494 */ 495 static const struct pci_class pci_subclass_satcom[] = { 496 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 497 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 498 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 499 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 500 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 501 { NULL, 0, NULL, }, 502 }; 503 504 /* 505 * Class 0x10. 506 * Encryption/Decryption controller. 507 */ 508 static const struct pci_class pci_subclass_crypto[] = { 509 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 510 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 511 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 512 { NULL, 0, NULL, }, 513 }; 514 515 /* 516 * Class 0x11. 517 * Data aquuisition and signal processing controller. 518 */ 519 static const struct pci_class pci_subclass_dasp[] = { 520 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 521 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 522 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 523 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 524 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 525 { NULL, 0, NULL, }, 526 }; 527 528 /* List of classes */ 529 static const struct pci_class pci_classes[] = { 530 { "prehistoric", PCI_CLASS_PREHISTORIC, 531 pci_subclass_prehistoric, }, 532 { "mass storage", PCI_CLASS_MASS_STORAGE, 533 pci_subclass_mass_storage, }, 534 { "network", PCI_CLASS_NETWORK, 535 pci_subclass_network, }, 536 { "display", PCI_CLASS_DISPLAY, 537 pci_subclass_display, }, 538 { "multimedia", PCI_CLASS_MULTIMEDIA, 539 pci_subclass_multimedia, }, 540 { "memory", PCI_CLASS_MEMORY, 541 pci_subclass_memory, }, 542 { "bridge", PCI_CLASS_BRIDGE, 543 pci_subclass_bridge, }, 544 { "communications", PCI_CLASS_COMMUNICATIONS, 545 pci_subclass_communications, }, 546 { "system", PCI_CLASS_SYSTEM, 547 pci_subclass_system, }, 548 { "input", PCI_CLASS_INPUT, 549 pci_subclass_input, }, 550 { "dock", PCI_CLASS_DOCK, 551 pci_subclass_dock, }, 552 { "processor", PCI_CLASS_PROCESSOR, 553 pci_subclass_processor, }, 554 { "serial bus", PCI_CLASS_SERIALBUS, 555 pci_subclass_serialbus, }, 556 { "wireless", PCI_CLASS_WIRELESS, 557 pci_subclass_wireless, }, 558 { "I2O", PCI_CLASS_I2O, 559 pci_subclass_i2o, }, 560 { "satellite comm", PCI_CLASS_SATCOM, 561 pci_subclass_satcom, }, 562 { "crypto", PCI_CLASS_CRYPTO, 563 pci_subclass_crypto, }, 564 { "DASP", PCI_CLASS_DASP, 565 pci_subclass_dasp, }, 566 { "processing accelerators", PCI_CLASS_ACCEL, 567 NULL, }, 568 { "non-essential instrumentation", PCI_CLASS_INSTRUMENT, 569 NULL, }, 570 { "undefined", PCI_CLASS_UNDEFINED, 571 NULL, }, 572 { NULL, 0, 573 NULL, }, 574 }; 575 576 DEV_VERBOSE_DEFINE(pci); 577 578 /* 579 * Append a formatted string to dest without writing more than len 580 * characters (including the trailing NUL character). dest and len 581 * are updated for use in subsequent calls to snappendf(). 582 * 583 * Returns 0 on success, a negative value if vnsprintf() fails, or 584 * a positive value if the dest buffer would have overflowed. 585 */ 586 587 static int __printflike(3,4) 588 snappendf(char **dest, size_t *len, const char * restrict fmt, ...) 589 { 590 va_list ap; 591 int count; 592 593 va_start(ap, fmt); 594 count = vsnprintf(*dest, *len, fmt, ap); 595 va_end(ap); 596 597 /* Let vsnprintf() errors bubble up to caller */ 598 if (count < 0 || *len == 0) 599 return count; 600 601 /* Handle overflow */ 602 if ((size_t)count >= *len) { 603 *dest += *len - 1; 604 *len = 1; 605 return 1; 606 } 607 608 /* Update dest & len to point at trailing NUL */ 609 *dest += count; 610 *len -= count; 611 612 return 0; 613 } 614 615 void 616 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 617 size_t l) 618 { 619 pci_class_t class; 620 pci_subclass_t subclass; 621 pci_interface_t interface; 622 pci_revision_t revision; 623 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 624 const struct pci_class *classp, *subclassp, *interfacep; 625 626 class = PCI_CLASS(class_reg); 627 subclass = PCI_SUBCLASS(class_reg); 628 interface = PCI_INTERFACE(class_reg); 629 revision = PCI_REVISION(class_reg); 630 631 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 632 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 633 PCI_PRODUCT(id_reg)); 634 635 classp = pci_classes; 636 while (classp->name != NULL) { 637 if (class == classp->val) 638 break; 639 classp++; 640 } 641 642 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 643 while (subclassp && subclassp->name != NULL) { 644 if (subclass == subclassp->val) 645 break; 646 subclassp++; 647 } 648 649 interfacep = (subclassp && subclassp->name != NULL) ? 650 subclassp->subclasses : NULL; 651 while (interfacep && interfacep->name != NULL) { 652 if (interface == interfacep->val) 653 break; 654 interfacep++; 655 } 656 657 (void)snappendf(&cp, &l, "%s %s", vendor, product); 658 if (showclass) { 659 (void)snappendf(&cp, &l, " ("); 660 if (classp->name == NULL) 661 (void)snappendf(&cp, &l, 662 "class 0x%02x, subclass 0x%02x", 663 class, subclass); 664 else { 665 if (subclassp == NULL || subclassp->name == NULL) 666 (void)snappendf(&cp, &l, 667 "%s, subclass 0x%02x", 668 classp->name, subclass); 669 else 670 (void)snappendf(&cp, &l, "%s %s", 671 subclassp->name, classp->name); 672 } 673 if ((interfacep == NULL) || (interfacep->name == NULL)) { 674 if (interface != 0) 675 (void)snappendf(&cp, &l, ", interface 0x%02x", 676 interface); 677 } else if (strncmp(interfacep->name, "", 1) != 0) 678 (void)snappendf(&cp, &l, ", %s", interfacep->name); 679 if (revision != 0) 680 (void)snappendf(&cp, &l, ", revision 0x%02x", revision); 681 (void)snappendf(&cp, &l, ")"); 682 } 683 } 684 685 #ifdef _KERNEL 686 void 687 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 688 const char *known, int addrev) 689 { 690 char devinfo[256]; 691 692 if (known) { 693 aprint_normal(": %s", known); 694 if (addrev) 695 aprint_normal(" (rev. 0x%02x)", 696 PCI_REVISION(pa->pa_class)); 697 aprint_normal("\n"); 698 } else { 699 pci_devinfo(pa->pa_id, pa->pa_class, 0, 700 devinfo, sizeof(devinfo)); 701 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 702 PCI_REVISION(pa->pa_class)); 703 } 704 if (naive) 705 aprint_naive(": %s\n", naive); 706 else 707 aprint_naive("\n"); 708 } 709 #endif 710 711 /* 712 * Print out most of the PCI configuration registers. Typically used 713 * in a device attach routine like this: 714 * 715 * #ifdef MYDEV_DEBUG 716 * printf("%s: ", device_xname(sc->sc_dev)); 717 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 718 * #endif 719 */ 720 721 #define i2o(i) ((i) * 4) 722 #define o2i(o) ((o) / 4) 723 #define onoff2(str, rval, bit, onstr, offstr) \ 724 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 725 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 726 727 static void 728 pci_conf_print_common( 729 #ifdef _KERNEL 730 pci_chipset_tag_t pc, pcitag_t tag, 731 #endif 732 const pcireg_t *regs) 733 { 734 pci_class_t class; 735 pci_subclass_t subclass; 736 pci_interface_t interface; 737 pci_revision_t revision; 738 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 739 const struct pci_class *classp, *subclassp, *interfacep; 740 const char *name; 741 pcireg_t rval; 742 unsigned int num; 743 744 rval = regs[o2i(PCI_CLASS_REG)]; 745 class = PCI_CLASS(rval); 746 subclass = PCI_SUBCLASS(rval); 747 interface = PCI_INTERFACE(rval); 748 revision = PCI_REVISION(rval); 749 750 rval = regs[o2i(PCI_ID_REG)]; 751 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 752 if (name) 753 printf(" Vendor Name: %s (0x%04x)\n", name, 754 PCI_VENDOR(rval)); 755 else 756 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 757 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 758 PCI_PRODUCT(rval)); 759 if (name) 760 printf(" Device Name: %s (0x%04x)\n", name, 761 PCI_PRODUCT(rval)); 762 else 763 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 764 765 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 766 767 printf(" Command register: 0x%04x\n", rval & 0xffff); 768 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 769 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 770 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 771 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 772 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 773 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 774 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 775 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 776 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 777 onoff("Fast back-to-back transactions", rval, 778 PCI_COMMAND_BACKTOBACK_ENABLE); 779 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 780 781 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 782 onoff("Immediate Readiness", rval, PCI_STATUS_IMMD_READNESS); 783 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 784 "inactive"); 785 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 786 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 787 onoff("User Definable Features (UDF) support", rval, 788 PCI_STATUS_UDF_SUPPORT); 789 onoff("Fast back-to-back capable", rval, 790 PCI_STATUS_BACKTOBACK_SUPPORT); 791 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 792 793 printf(" DEVSEL timing: "); 794 switch (rval & PCI_STATUS_DEVSEL_MASK) { 795 case PCI_STATUS_DEVSEL_FAST: 796 printf("fast"); 797 break; 798 case PCI_STATUS_DEVSEL_MEDIUM: 799 printf("medium"); 800 break; 801 case PCI_STATUS_DEVSEL_SLOW: 802 printf("slow"); 803 break; 804 default: 805 printf("unknown/reserved"); /* XXX */ 806 break; 807 } 808 printf(" (0x%x)\n", __SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK)); 809 810 onoff("Slave signaled Target Abort", rval, 811 PCI_STATUS_TARGET_TARGET_ABORT); 812 onoff("Master received Target Abort", rval, 813 PCI_STATUS_MASTER_TARGET_ABORT); 814 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 815 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 816 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 817 818 rval = regs[o2i(PCI_CLASS_REG)]; 819 for (classp = pci_classes; classp->name != NULL; classp++) { 820 if (class == classp->val) 821 break; 822 } 823 824 /* 825 * ECN: Change Root Complex Event Collector Class Code 826 * Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type 827 * in PCIe extend capability to know whether it's RCEC or IOMMU. 828 */ 829 if ((class == PCI_CLASS_SYSTEM) 830 && (subclass == PCI_SUBCLASS_SYSTEM_IOMMU)) { 831 int pcie_capoff; 832 pcireg_t reg; 833 834 if (pci_conf_find_cap(regs, PCI_CAPLISTPTR_REG, 835 PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 836 reg = regs[o2i(pcie_capoff + PCIE_XCAP)]; 837 if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_ROOT_EVNTC) 838 subclass = PCI_SUBCLASS_SYSTEM_RCEC; 839 } 840 } 841 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 842 while (subclassp && subclassp->name != NULL) { 843 if (subclass == subclassp->val) 844 break; 845 subclassp++; 846 } 847 848 interfacep = (subclassp && subclassp->name != NULL) ? 849 subclassp->subclasses : NULL; 850 while (interfacep && interfacep->name != NULL) { 851 if (interface == interfacep->val) 852 break; 853 interfacep++; 854 } 855 856 if (classp->name != NULL) 857 printf(" Class Name: %s (0x%02x)\n", classp->name, class); 858 else 859 printf(" Class ID: 0x%02x\n", class); 860 if (subclassp != NULL && subclassp->name != NULL) 861 printf(" Subclass Name: %s (0x%02x)\n", 862 subclassp->name, PCI_SUBCLASS(rval)); 863 else 864 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 865 if ((interfacep != NULL) && (interfacep->name != NULL) 866 && (strncmp(interfacep->name, "", 1) != 0)) 867 printf(" Interface Name: %s (0x%02x)\n", 868 interfacep->name, interface); 869 else 870 printf(" Interface: 0x%02x\n", interface); 871 printf(" Revision ID: 0x%02x\n", revision); 872 873 rval = regs[o2i(PCI_BHLC_REG)]; 874 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 875 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 876 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 877 PCI_HDRTYPE(rval)); 878 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 879 num = PCI_CACHELINE(rval); 880 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 881 } 882 883 static int 884 pci_conf_print_bar( 885 #ifdef _KERNEL 886 pci_chipset_tag_t pc, pcitag_t tag, 887 #endif 888 const pcireg_t *regs, int reg, const char *name) 889 { 890 int width; 891 pcireg_t rval, rval64h; 892 bool ioen, memen; 893 #ifdef _KERNEL 894 pcireg_t mask, mask64h = 0; 895 #endif 896 897 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 898 ioen = rval & PCI_COMMAND_IO_ENABLE; 899 memen = rval & PCI_COMMAND_MEM_ENABLE; 900 901 width = 4; 902 /* 903 * Section 6.2.5.1, `Address Maps', tells us that: 904 * 905 * 1) The builtin software should have already mapped the 906 * device in a reasonable way. 907 * 908 * 2) A device which wants 2^n bytes of memory will hardwire 909 * the bottom n bits of the address to 0. As recommended, 910 * we write all 1s and see what we get back. 911 */ 912 913 rval = regs[o2i(reg)]; 914 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 915 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 916 rval64h = regs[o2i(reg + 4)]; 917 width = 8; 918 } else 919 rval64h = 0; 920 921 #ifdef _KERNEL 922 if (rval != 0 && memen) { 923 int s; 924 925 /* 926 * The following sequence seems to make some devices 927 * (e.g. host bus bridges, which don't normally 928 * have their space mapped) very unhappy, to 929 * the point of crashing the system. 930 * 931 * Therefore, if the mapping register is zero to 932 * start out with, don't bother trying. 933 */ 934 s = splhigh(); 935 pci_conf_write(pc, tag, reg, 0xffffffff); 936 mask = pci_conf_read(pc, tag, reg); 937 pci_conf_write(pc, tag, reg, rval); 938 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 939 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 940 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 941 mask64h = pci_conf_read(pc, tag, reg + 4); 942 pci_conf_write(pc, tag, reg + 4, rval64h); 943 } 944 splx(s); 945 } else 946 mask = mask64h = 0; 947 #endif /* _KERNEL */ 948 949 printf(" Base address register at 0x%02x", reg); 950 if (name) 951 printf(" (%s)", name); 952 printf("\n "); 953 if (rval == 0) { 954 printf("not implemented\n"); 955 return width; 956 } 957 printf("type: "); 958 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 959 const char *type, *prefetch; 960 961 switch (PCI_MAPREG_MEM_TYPE(rval)) { 962 case PCI_MAPREG_MEM_TYPE_32BIT: 963 type = "32-bit"; 964 break; 965 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 966 type = "32-bit-1M"; 967 break; 968 case PCI_MAPREG_MEM_TYPE_64BIT: 969 type = "64-bit"; 970 break; 971 default: 972 type = "unknown (XXX)"; 973 break; 974 } 975 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 976 prefetch = ""; 977 else 978 prefetch = "non"; 979 printf("%s %sprefetchable memory\n", type, prefetch); 980 switch (PCI_MAPREG_MEM_TYPE(rval)) { 981 case PCI_MAPREG_MEM_TYPE_64BIT: 982 printf(" base: 0x%016llx", 983 PCI_MAPREG_MEM64_ADDR( 984 ((((long long) rval64h) << 32) | rval))); 985 if (!memen) 986 printf(", disabled"); 987 printf("\n"); 988 #ifdef _KERNEL 989 printf(" size: 0x%016llx\n", 990 PCI_MAPREG_MEM64_SIZE( 991 ((((long long) mask64h) << 32) | mask))); 992 #endif 993 break; 994 case PCI_MAPREG_MEM_TYPE_32BIT: 995 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 996 default: 997 printf(" base: 0x%08x", 998 PCI_MAPREG_MEM_ADDR(rval)); 999 if (!memen) 1000 printf(", disabled"); 1001 printf("\n"); 1002 #ifdef _KERNEL 1003 printf(" size: 0x%08x\n", 1004 PCI_MAPREG_MEM_SIZE(mask)); 1005 #endif 1006 break; 1007 } 1008 } else { 1009 #ifdef _KERNEL 1010 if (ioen) 1011 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 1012 #endif 1013 printf("I/O\n"); 1014 printf(" base: 0x%08x", PCI_MAPREG_IO_ADDR(rval)); 1015 if (!ioen) 1016 printf(", disabled"); 1017 printf("\n"); 1018 #ifdef _KERNEL 1019 printf(" size: 0x%08x\n", PCI_MAPREG_IO_SIZE(mask)); 1020 #endif 1021 } 1022 1023 return width; 1024 } 1025 1026 static void 1027 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 1028 { 1029 int off, needaddr, neednl; 1030 1031 needaddr = 1; 1032 neednl = 0; 1033 for (off = first; off < pastlast; off += 4) { 1034 if ((off % 16) == 0 || needaddr) { 1035 printf(" 0x%02x:", off); 1036 needaddr = 0; 1037 } 1038 printf(" 0x%08x", regs[o2i(off)]); 1039 neednl = 1; 1040 if ((off % 16) == 12) { 1041 printf("\n"); 1042 neednl = 0; 1043 } 1044 } 1045 if (neednl) 1046 printf("\n"); 1047 } 1048 1049 static const char * 1050 pci_conf_print_agp_calcycle(uint8_t cal) 1051 { 1052 1053 switch (cal) { 1054 case 0x0: 1055 return "4ms"; 1056 case 0x1: 1057 return "16ms"; 1058 case 0x2: 1059 return "64ms"; 1060 case 0x3: 1061 return "256ms"; 1062 case 0x7: 1063 return "Calibration Cycle Not Needed"; 1064 default: 1065 return "(reserved)"; 1066 } 1067 } 1068 1069 static void 1070 pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3) 1071 { 1072 if (isagp3) { 1073 /* AGP 3.0 */ 1074 if (reg & AGP_MODE_V3_RATE_4x) 1075 printf("x4"); 1076 if (reg & AGP_MODE_V3_RATE_8x) 1077 printf("x8"); 1078 } else { 1079 /* AGP 2.0 */ 1080 if (reg & AGP_MODE_V2_RATE_1x) 1081 printf("x1"); 1082 if (reg & AGP_MODE_V2_RATE_2x) 1083 printf("x2"); 1084 if (reg & AGP_MODE_V2_RATE_4x) 1085 printf("x4"); 1086 } 1087 printf("\n"); 1088 } 1089 1090 static void 1091 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1092 { 1093 pcireg_t rval; 1094 bool isagp3; 1095 1096 printf("\n AGP Capabilities Register\n"); 1097 1098 rval = regs[o2i(capoff)]; 1099 printf(" Revision: %d.%d\n", 1100 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1101 1102 rval = regs[o2i(capoff + PCI_AGP_STATUS)]; 1103 printf(" Status register: 0x%04x\n", rval); 1104 printf(" RQ: %d\n", 1105 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1106 printf(" ARQSZ: %d\n", 1107 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1108 printf(" CAL cycle: %s\n", 1109 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1110 onoff("SBA", rval, AGP_MODE_SBA); 1111 onoff("htrans#", rval, AGP_MODE_HTRANS); 1112 onoff("Over 4G", rval, AGP_MODE_4G); 1113 onoff("Fast Write", rval, AGP_MODE_FW); 1114 onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3); 1115 isagp3 = rval & AGP_MODE_MODE_3; 1116 printf(" Data Rate Support: "); 1117 pci_conf_print_agp_datarate(rval, isagp3); 1118 1119 rval = regs[o2i(capoff + PCI_AGP_COMMAND)]; 1120 printf(" Command register: 0x%08x\n", rval); 1121 printf(" PRQ: %d\n", 1122 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1123 printf(" PARQSZ: %d\n", 1124 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1125 printf(" PCAL cycle: %s\n", 1126 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1127 onoff("SBA", rval, AGP_MODE_SBA); 1128 onoff("AGP", rval, AGP_MODE_AGP); 1129 onoff("Over 4G", rval, AGP_MODE_4G); 1130 onoff("Fast Write", rval, AGP_MODE_FW); 1131 if (isagp3) { 1132 printf(" Data Rate Enable: "); 1133 /* 1134 * The Data Rate Enable bits are used only on 3.0 and the 1135 * Command register has no AGP_MODE_MODE_3 bit, so pass the 1136 * flag to print correctly. 1137 */ 1138 pci_conf_print_agp_datarate(rval, isagp3); 1139 } 1140 } 1141 1142 static const char * 1143 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1144 { 1145 1146 switch ((caps >> 6) & 7) { 1147 case 0: return "self-powered"; 1148 case 1: return "55 mA"; 1149 case 2: return "100 mA"; 1150 case 3: return "160 mA"; 1151 case 4: return "220 mA"; 1152 case 5: return "270 mA"; 1153 case 6: return "320 mA"; 1154 case 7: 1155 default: return "375 mA"; 1156 } 1157 } 1158 1159 static const char * 1160 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1161 { 1162 static const char unk[] = "unknown"; 1163 static const char *pmrev[8] = { 1164 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1165 }; 1166 if (val > 7) 1167 return unk; 1168 return pmrev[val]; 1169 } 1170 1171 static void 1172 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1173 { 1174 uint16_t caps, pmcsr; 1175 pcireg_t reg; 1176 1177 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1178 reg = regs[o2i(capoff + PCI_PMCSR)]; 1179 pmcsr = reg & 0xffff; 1180 1181 printf("\n PCI Power Management Capabilities Register\n"); 1182 1183 printf(" Capabilities register: 0x%04x\n", caps); 1184 printf(" Version: %s\n", 1185 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1186 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1187 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1188 printf(" 3.3V auxiliary current: %s\n", 1189 pci_conf_print_pcipm_cap_aux(caps)); 1190 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1191 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1192 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1193 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1194 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1195 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1196 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1197 1198 printf(" Control/status register: 0x%04x\n", pmcsr); 1199 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1200 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1201 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1202 printf(" PME# assertion: %sabled\n", 1203 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1204 printf(" Data Select: %d\n", 1205 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK)); 1206 printf(" Data Scale: %d\n", 1207 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK)); 1208 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1209 printf(" Bridge Support Extensions register: 0x%02x\n", 1210 (reg >> 16) & 0xff); 1211 onoff("B2/B3 support", reg, PCI_PMCSR_B2B3_SUPPORT); 1212 onoff("Bus Power/Clock Control Enable", reg, PCI_PMCSR_BPCC_EN); 1213 printf(" Data register: 0x%02x\n", __SHIFTOUT(reg, PCI_PMCSR_DATA)); 1214 1215 } 1216 1217 /* XXX pci_conf_print_vpd_cap */ 1218 /* XXX pci_conf_print_slotid_cap */ 1219 1220 static void 1221 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1222 { 1223 uint32_t ctl, mmc, mme; 1224 1225 regs += o2i(capoff); 1226 ctl = *regs++; 1227 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1228 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1229 1230 printf("\n PCI Message Signaled Interrupt\n"); 1231 1232 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1233 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1234 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1235 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1236 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1237 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1238 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1239 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1240 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP); 1241 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN); 1242 printf(" Message Address %sregister: 0x%08x\n", 1243 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1244 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1245 printf(" Message Address %sregister: 0x%08x\n", 1246 "(upper) ", *regs++); 1247 } 1248 printf(" Message Data register: "); 1249 if (ctl & PCI_MSI_CTL_EXTMDATA_CAP) 1250 printf("0x%08x\n", *regs); 1251 else 1252 printf("0x%04x\n", *regs & 0xffff); 1253 regs++; 1254 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1255 printf(" Vector Mask register: 0x%08x\n", *regs++); 1256 printf(" Vector Pending register: 0x%08x\n", *regs++); 1257 } 1258 } 1259 1260 /* XXX pci_conf_print_cpci_hostwap_cap */ 1261 1262 /* 1263 * For both command register and status register. 1264 * The argument "idx" is index number (0 to 7). 1265 */ 1266 static int 1267 pcix_split_trans(unsigned int idx) 1268 { 1269 static int table[8] = { 1270 1, 2, 3, 4, 8, 12, 16, 32 1271 }; 1272 1273 if (idx >= __arraycount(table)) 1274 return -1; 1275 return table[idx]; 1276 } 1277 1278 static void 1279 pci_conf_print_pcix_cap_2ndbusmode(int num) 1280 { 1281 const char *maxfreq, *maxperiod; 1282 1283 printf(" Mode: "); 1284 if (num <= 0x07) 1285 printf("PCI-X Mode 1\n"); 1286 else if (num <= 0x0b) 1287 printf("PCI-X 266 (Mode 2)\n"); 1288 else 1289 printf("PCI-X 533 (Mode 2)\n"); 1290 1291 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1292 switch (num & 0x03) { 1293 default: 1294 case 0: 1295 maxfreq = "N/A"; 1296 maxperiod = "N/A"; 1297 break; 1298 case 1: 1299 maxfreq = "66MHz"; 1300 maxperiod = "15ns"; 1301 break; 1302 case 2: 1303 maxfreq = "100MHz"; 1304 maxperiod = "10ns"; 1305 break; 1306 case 3: 1307 maxfreq = "133MHz"; 1308 maxperiod = "7.5ns"; 1309 break; 1310 } 1311 printf(" Max Clock Freq: %s\n", maxfreq); 1312 printf(" Min Clock Period: %s\n", maxperiod); 1313 } 1314 1315 static void 1316 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1317 { 1318 pcireg_t reg; 1319 int isbridge; 1320 int i; 1321 1322 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1323 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1324 printf("\n PCI-X %s Capabilities Register\n", 1325 isbridge ? "Bridge" : "Non-bridge"); 1326 1327 reg = regs[o2i(capoff)]; 1328 if (isbridge != 0) { 1329 printf(" Secondary status register: 0x%04x\n", 1330 (reg & 0xffff0000) >> 16); 1331 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1332 onoff("133MHz capable", reg, PCIX_STATUS_133); 1333 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1334 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1335 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1336 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1337 pci_conf_print_pcix_cap_2ndbusmode( 1338 __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1339 printf(" Version: 0x%x\n", 1340 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1341 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1342 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1343 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1344 } else { 1345 printf(" Command register: 0x%04x\n", 1346 (reg & 0xffff0000) >> 16); 1347 onoff("Data Parity Error Recovery", reg, 1348 PCIX_CMD_PERR_RECOVER); 1349 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1350 printf(" Maximum Burst Read Count: %u\n", 1351 PCIX_CMD_BYTECNT(reg)); 1352 printf(" Maximum Split Transactions: %d\n", 1353 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1354 >> PCIX_CMD_SPLTRANS_SHIFT)); 1355 } 1356 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1357 printf(" %sStatus register: 0x%08x\n", 1358 isbridge ? "Bridge " : "", reg); 1359 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1360 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1361 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1362 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1363 onoff("133MHz capable", reg, PCIX_STATUS_133); 1364 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1365 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1366 if (isbridge != 0) { 1367 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1368 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1369 } else { 1370 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1371 "bridge device", "simple device"); 1372 printf(" Designed max memory read byte count: %d\n", 1373 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1374 >> PCIX_STATUS_MAXB_SHIFT)); 1375 printf(" Designed max outstanding split transaction: %d\n", 1376 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1377 >> PCIX_STATUS_MAXST_SHIFT)); 1378 printf(" MAX cumulative Read Size: %u\n", 1379 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1380 onoff("Received split completion error", reg, 1381 PCIX_STATUS_SCERR); 1382 } 1383 onoff("266MHz capable", reg, PCIX_STATUS_266); 1384 onoff("533MHz capable", reg, PCIX_STATUS_533); 1385 1386 if (isbridge == 0) 1387 return; 1388 1389 /* Only for bridge */ 1390 for (i = 0; i < 2; i++) { 1391 reg = regs[o2i(capoff + PCIX_BRIDGE_UP_STCR + (4 * i))]; 1392 printf(" %s split transaction control register: 0x%08x\n", 1393 (i == 0) ? "Upstream" : "Downstream", reg); 1394 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1395 printf(" Commitment Limit: %d\n", 1396 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1397 } 1398 } 1399 1400 /* pci_conf_print_ht_slave_cap */ 1401 /* pci_conf_print_ht_host_cap */ 1402 /* pci_conf_print_ht_switch_cap */ 1403 /* pci_conf_print_ht_intr_cap */ 1404 /* pci_conf_print_ht_revid_cap */ 1405 /* pci_conf_print_ht_unitid_cap */ 1406 /* pci_conf_print_ht_extcnf_cap */ 1407 /* pci_conf_print_ht_addrmap_cap */ 1408 /* pci_conf_print_ht_msimap_cap */ 1409 1410 static void 1411 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1412 { 1413 pcireg_t val; 1414 uint32_t lo, hi; 1415 1416 /* 1417 * Print the rest of the command register bits. Others are 1418 * printed in pci_conf_print_ht_cap(). 1419 */ 1420 val = regs[o2i(capoff + PCI_HT_CMD)]; 1421 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1422 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1423 1424 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1425 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1426 printf(" Address Low register: 0x%08x\n", lo); 1427 printf(" Address high register: 0x%08x\n", hi); 1428 printf(" Address: 0x%016" PRIx64 "\n", 1429 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1430 } 1431 1432 /* pci_conf_print_ht_droute_cap */ 1433 /* pci_conf_print_ht_vcset_cap */ 1434 /* pci_conf_print_ht_retry_cap */ 1435 /* pci_conf_print_ht_x86enc_cap */ 1436 /* pci_conf_print_ht_gen3_cap */ 1437 /* pci_conf_print_ht_fle_cap */ 1438 /* pci_conf_print_ht_pm_cap */ 1439 /* pci_conf_print_ht_hnc_cap */ 1440 1441 static const struct ht_types { 1442 pcireg_t cap; 1443 const char *name; 1444 void (*printfunc)(const pcireg_t *, int); 1445 } ht_captab[] = { 1446 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1447 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1448 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1449 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1450 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1451 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1452 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1453 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1454 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1455 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1456 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1457 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1458 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1459 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1460 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1461 {PCI_HT_CAP_PM, "Power Management", NULL }, 1462 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1463 }; 1464 1465 static void 1466 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1467 { 1468 pcireg_t val, foundcap; 1469 unsigned int off; 1470 1471 val = regs[o2i(capoff + PCI_HT_CMD)]; 1472 1473 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1474 1475 printf(" Command register: 0x%04x\n", val >> 16); 1476 foundcap = PCI_HT_CAP(val); 1477 for (off = 0; off < __arraycount(ht_captab); off++) { 1478 if (ht_captab[off].cap == foundcap) 1479 break; 1480 } 1481 printf(" Capability Type: 0x%02x ", foundcap); 1482 if (off >= __arraycount(ht_captab)) { 1483 printf("(unknown)\n"); 1484 return; 1485 } 1486 printf("(%s)\n", ht_captab[off].name); 1487 if (ht_captab[off].printfunc != NULL) 1488 ht_captab[off].printfunc(regs, capoff); 1489 } 1490 1491 static void 1492 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1493 { 1494 uint16_t caps; 1495 1496 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1497 1498 printf("\n PCI Vendor Specific Capabilities Register\n"); 1499 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1500 } 1501 1502 static void 1503 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1504 { 1505 pcireg_t val; 1506 1507 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1508 1509 printf("\n Debugport Capability Register\n"); 1510 printf(" Debug base Register: 0x%04x\n", 1511 val >> PCI_DEBUG_BASER_SHIFT); 1512 printf(" port offset: 0x%04x\n", 1513 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1514 printf(" BAR number: %u\n", 1515 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1516 } 1517 1518 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1519 /* XXX pci_conf_print_hotplug_cap */ 1520 1521 static void 1522 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1523 { 1524 pcireg_t reg; 1525 1526 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1527 1528 printf("\n Subsystem ID Capability Register\n"); 1529 printf(" Subsystem ID : 0x%08x\n", reg); 1530 } 1531 1532 /* XXX pci_conf_print_agp8_cap */ 1533 static void 1534 pci_conf_print_secure_cap(const pcireg_t *regs, int capoff) 1535 { 1536 pcireg_t reg, reg2, val; 1537 bool havemisc1; 1538 1539 printf("\n Secure Capability Register\n"); 1540 reg = regs[o2i(capoff + PCI_SECURE_CAP)]; 1541 printf(" Capability Register: 0x%04x\n", reg >> 16); 1542 val = __SHIFTOUT(reg, PCI_SECURE_CAP_TYPE); 1543 printf(" Capability block type: "); 1544 /* I know IOMMU Only */ 1545 if (val == PCI_SECURE_CAP_TYPE_IOMMU) 1546 printf("IOMMU\n"); 1547 else { 1548 printf("0x%x(unknown)\n", val); 1549 return; 1550 } 1551 1552 val = __SHIFTOUT(reg, PCI_SECURE_CAP_REV); 1553 printf(" Capability revision: 0x%02x ", val); 1554 if (val == PCI_SECURE_CAP_REV_IOMMU) 1555 printf("(IOMMU)\n"); 1556 else { 1557 printf("(unknown)\n"); 1558 return; 1559 } 1560 onoff("IOTLB support", reg, PCI_SECURE_CAP_IOTLBSUP); 1561 onoff("HyperTransport tunnel translation support", reg, 1562 PCI_SECURE_CAP_HTTUNNEL); 1563 onoff("Not present table entries cached", reg, PCI_SECURE_CAP_NPCACHE); 1564 onoff("IOMMU Extended Feature Register support", reg, 1565 PCI_SECURE_CAP_EFRSUP); 1566 onoff("IOMMU Miscellaneous Information Register 1", reg, 1567 PCI_SECURE_CAP_EXT); 1568 havemisc1 = reg & PCI_SECURE_CAP_EXT; 1569 1570 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_BAL)]; 1571 printf(" Base Address Low Register: 0x%08x\n", reg); 1572 onoff("Enable", reg, PCI_SECURE_IOMMU_BAL_EN); 1573 reg2 = regs[o2i(capoff + PCI_SECURE_IOMMU_BAH)]; 1574 printf(" Base Address High Register: 0x%08x\n", reg2); 1575 printf(" Base Address : 0x%016" PRIx64 "\n", 1576 ((uint64_t)reg2 << 32) 1577 | (reg & (PCI_SECURE_IOMMU_BAL_H | PCI_SECURE_IOMMU_BAL_L))); 1578 1579 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_RANGE)]; 1580 printf(" IOMMU Range Register: 0x%08x\n", reg); 1581 printf(" HyperTransport UnitID: 0x%02x\n", 1582 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_UNITID)); 1583 onoff("Range valid", reg, PCI_SECURE_IOMMU_RANGE_RNGVALID); 1584 printf(" Device range bus number: 0x%02x\n", 1585 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_BUSNUM)); 1586 printf(" First device: 0x%04x\n", 1587 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_FIRSTDEV)); 1588 printf(" Last device: 0x%04x\n", 1589 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_LASTDEV)); 1590 1591 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC0)]; 1592 printf(" Miscellaneous Information Register 0: 0x%08x\n", reg); 1593 printf(" MSI Message number: 0x%02x\n", 1594 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MSINUM)); 1595 val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_GVASIZE); 1596 printf(" Guest Virtual Address size: "); 1597 if (val == PCI_SECURE_IOMMU_MISC0_GVASIZE_48B) 1598 printf("48bits\n"); 1599 else 1600 printf("0x%x(unknown)\n", val); 1601 val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_PASIZE); 1602 printf(" Physical Address size: %dbits\n", val); 1603 val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_VASIZE); 1604 printf(" Virtual Address size: %dbits\n", val); 1605 onoff("ATS response address range reserved", reg, 1606 PCI_SECURE_IOMMU_MISC0_ATSRESV); 1607 printf(" Peripheral Page Request MSI Message number: 0x%02x\n", 1608 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MISNPPR)); 1609 1610 if (!havemisc1) 1611 return; 1612 1613 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC1)]; 1614 printf(" Miscellaneous Information Register 1: 0x%08x\n", reg); 1615 printf(" MSI Message number (GA): 0x%02x\n", 1616 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC1_MSINUM)); 1617 } 1618 1619 static void 1620 pci_print_pcie_L0s_latency(uint32_t val) 1621 { 1622 1623 switch (val) { 1624 case 0x0: 1625 printf("Less than 64ns\n"); 1626 break; 1627 case 0x1: 1628 case 0x2: 1629 case 0x3: 1630 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1631 break; 1632 case 0x4: 1633 printf("512ns to less than 1us\n"); 1634 break; 1635 case 0x5: 1636 printf("1us to less than 2us\n"); 1637 break; 1638 case 0x6: 1639 printf("2us - 4us\n"); 1640 break; 1641 case 0x7: 1642 printf("More than 4us\n"); 1643 break; 1644 } 1645 } 1646 1647 static void 1648 pci_print_pcie_L1_latency(uint32_t val) 1649 { 1650 1651 switch (val) { 1652 case 0x0: 1653 printf("Less than 1us\n"); 1654 break; 1655 case 0x6: 1656 printf("32us - 64us\n"); 1657 break; 1658 case 0x7: 1659 printf("More than 64us\n"); 1660 break; 1661 default: 1662 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1663 break; 1664 } 1665 } 1666 1667 static void 1668 pci_print_pcie_compl_timeout(uint32_t val) 1669 { 1670 1671 switch (val) { 1672 case 0x0: 1673 printf("50us to 50ms\n"); 1674 break; 1675 case 0x5: 1676 printf("16ms to 55ms\n"); 1677 break; 1678 case 0x6: 1679 printf("65ms to 210ms\n"); 1680 break; 1681 case 0x9: 1682 printf("260ms to 900ms\n"); 1683 break; 1684 case 0xa: 1685 printf("1s to 3.5s\n"); 1686 break; 1687 default: 1688 printf("unknown %u value\n", val); 1689 break; 1690 } 1691 } 1692 1693 static const char * const pcie_linkspeeds[] = {"2.5", "5.0", "8.0"}; 1694 1695 /* 1696 * Print link speed. This function is used for the following register bits: 1697 * Maximum Link Speed in LCAP 1698 * Current Link Speed in LCSR 1699 * Target Link Speed in LCSR2 1700 * All of above bitfield's values start from 1. 1701 * For LCSR2, 0 is allowed for a device which supports 2.5GT/s only (and 1702 * this check also works for devices which compliant to versions of the base 1703 * specification prior to 3.0. 1704 */ 1705 static void 1706 pci_print_pcie_linkspeed(int regnum, pcireg_t val) 1707 { 1708 1709 if ((regnum == PCIE_LCSR2) && (val == 0)) 1710 printf("2.5GT/s\n"); 1711 else if ((val < 1) || (val > __arraycount(pcie_linkspeeds))) 1712 printf("unknown value (%u)\n", val); 1713 else 1714 printf("%sGT/s\n", pcie_linkspeeds[val - 1]); 1715 } 1716 1717 /* 1718 * Print link speed "vector". 1719 * This function is used for the following register bits: 1720 * Supported Link Speeds Vector in LCAP2 1721 * Lower SKP OS Generation Supported Speed Vector in LCAP2 1722 * Lower SKP OS Reception Supported Speed Vector in LCAP2 1723 * Enable Lower SKP OS Generation Vector in LCTL3 1724 * All of above bitfield's values start from 0. 1725 */ 1726 static void 1727 pci_print_pcie_linkspeedvector(pcireg_t val) 1728 { 1729 unsigned int i; 1730 1731 /* Start from 0 */ 1732 for (i = 0; i < 16; i++) 1733 if (((val >> i) & 0x01) != 0) { 1734 if (i >= __arraycount(pcie_linkspeeds)) 1735 printf(" unknown vector (0x%x)", 1 << i); 1736 else 1737 printf(" %sGT/s", pcie_linkspeeds[i]); 1738 } 1739 } 1740 1741 static void 1742 pci_print_pcie_link_deemphasis(pcireg_t val) 1743 { 1744 switch (val) { 1745 case 0: 1746 printf("-6dB"); 1747 break; 1748 case 1: 1749 printf("-3.5dB"); 1750 break; 1751 default: 1752 printf("(reserved value)"); 1753 } 1754 } 1755 1756 static void 1757 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1758 { 1759 pcireg_t reg; /* for each register */ 1760 pcireg_t val; /* for each bitfield */ 1761 bool check_link = true; 1762 bool check_slot = false; 1763 bool check_rootport = false; 1764 bool check_upstreamport = false; 1765 unsigned int pciever; 1766 unsigned int i; 1767 1768 printf("\n PCI Express Capabilities Register\n"); 1769 /* Capability Register */ 1770 reg = regs[o2i(capoff)]; 1771 printf(" Capability register: 0x%04x\n", reg >> 16); 1772 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 1773 printf(" Capability version: %u\n", pciever); 1774 printf(" Device type: "); 1775 switch ((reg & 0x00f00000) >> 20) { 1776 case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */ 1777 printf("PCI Express Endpoint device\n"); 1778 check_upstreamport = true; 1779 break; 1780 case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */ 1781 printf("Legacy PCI Express Endpoint device\n"); 1782 check_upstreamport = true; 1783 break; 1784 case PCIE_XCAP_TYPE_ROOT: /* 0x4 */ 1785 printf("Root Port of PCI Express Root Complex\n"); 1786 check_slot = true; 1787 check_rootport = true; 1788 break; 1789 case PCIE_XCAP_TYPE_UP: /* 0x5 */ 1790 printf("Upstream Port of PCI Express Switch\n"); 1791 check_upstreamport = true; 1792 break; 1793 case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ 1794 printf("Downstream Port of PCI Express Switch\n"); 1795 check_slot = true; 1796 check_rootport = true; 1797 break; 1798 case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ 1799 printf("PCI Express to PCI/PCI-X Bridge\n"); 1800 check_upstreamport = true; 1801 break; 1802 case PCIE_XCAP_TYPE_PCI2PCIE: /* 0x8 */ 1803 printf("PCI/PCI-X to PCI Express Bridge\n"); 1804 /* Upstream port is not PCIe */ 1805 check_slot = true; 1806 break; 1807 case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */ 1808 printf("Root Complex Integrated Endpoint\n"); 1809 check_link = false; 1810 break; 1811 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */ 1812 printf("Root Complex Event Collector\n"); 1813 check_link = false; 1814 check_rootport = true; 1815 break; 1816 default: 1817 printf("unknown\n"); 1818 break; 1819 } 1820 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1821 printf(" Interrupt Message Number: 0x%02x\n", 1822 (unsigned int)__SHIFTOUT(reg, PCIE_XCAP_IRQ)); 1823 1824 /* Device Capability Register */ 1825 reg = regs[o2i(capoff + PCIE_DCAP)]; 1826 printf(" Device Capabilities Register: 0x%08x\n", reg); 1827 printf(" Max Payload Size Supported: %u bytes max\n", 1828 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1829 printf(" Phantom Functions Supported: "); 1830 switch (__SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) { 1831 case 0x0: 1832 printf("not available\n"); 1833 break; 1834 case 0x1: 1835 printf("MSB\n"); 1836 break; 1837 case 0x2: 1838 printf("two MSB\n"); 1839 break; 1840 case 0x3: 1841 printf("All three bits\n"); 1842 break; 1843 } 1844 printf(" Extended Tag Field Supported: %dbit\n", 1845 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1846 printf(" Endpoint L0 Acceptable Latency: "); 1847 pci_print_pcie_L0s_latency(__SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY)); 1848 printf(" Endpoint L1 Acceptable Latency: "); 1849 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY)); 1850 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1851 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1852 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1853 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1854 if (check_upstreamport) { 1855 printf(" Captured Slot Power Limit: "); 1856 pci_conf_print_pcie_power( 1857 __SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL), 1858 __SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE)); 1859 } 1860 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1861 1862 /* Device Control Register */ 1863 reg = regs[o2i(capoff + PCIE_DCSR)]; 1864 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1865 onoff("Correctable Error Reporting Enable", reg, 1866 PCIE_DCSR_ENA_COR_ERR); 1867 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1868 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1869 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1870 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1871 printf(" Max Payload Size: %d byte\n", 1872 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD)); 1873 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1874 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1875 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1876 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1877 printf(" Max Read Request Size: %d byte\n", 1878 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ)); 1879 1880 /* Device Status Register */ 1881 reg = regs[o2i(capoff + PCIE_DCSR)]; 1882 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1883 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1884 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1885 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1886 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1887 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1888 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1889 onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD); 1890 1891 if (check_link) { 1892 /* Link Capability Register */ 1893 reg = regs[o2i(capoff + PCIE_LCAP)]; 1894 printf(" Link Capabilities Register: 0x%08x\n", reg); 1895 printf(" Maximum Link Speed: "); 1896 pci_print_pcie_linkspeed(PCIE_LCAP, reg & PCIE_LCAP_MAX_SPEED); 1897 printf(" Maximum Link Width: x%u lanes\n", 1898 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH)); 1899 printf(" Active State PM Support: "); 1900 switch (__SHIFTOUT(reg, PCIE_LCAP_ASPM)) { 1901 case 0x0: 1902 printf("No ASPM support\n"); 1903 break; 1904 case 0x1: 1905 printf("L0s supported\n"); 1906 break; 1907 case 0x2: 1908 printf("L1 supported\n"); 1909 break; 1910 case 0x3: 1911 printf("L0s and L1 supported\n"); 1912 break; 1913 } 1914 printf(" L0 Exit Latency: "); 1915 pci_print_pcie_L0s_latency(__SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT)); 1916 printf(" L1 Exit Latency: "); 1917 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_LCAP_L1_EXIT)); 1918 printf(" Port Number: %u\n", 1919 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_PORT)); 1920 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1921 onoff("Surprise Down Error Report", reg, 1922 PCIE_LCAP_SURPRISE_DOWN); 1923 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1924 onoff("Link BW Notification Capable", reg, 1925 PCIE_LCAP_LINK_BW_NOTIFY); 1926 onoff("ASPM Optionally Compliance", reg, 1927 PCIE_LCAP_ASPM_COMPLIANCE); 1928 1929 /* Link Control Register */ 1930 reg = regs[o2i(capoff + PCIE_LCSR)]; 1931 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1932 printf(" Active State PM Control: "); 1933 switch (reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S)) { 1934 case 0: 1935 printf("disabled\n"); 1936 break; 1937 case 1: 1938 printf("L0s Entry Enabled\n"); 1939 break; 1940 case 2: 1941 printf("L1 Entry Enabled\n"); 1942 break; 1943 case 3: 1944 printf("L0s and L1 Entry Enabled\n"); 1945 break; 1946 } 1947 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1948 "128bytes", "64bytes"); 1949 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1950 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1951 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1952 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1953 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1954 onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD); 1955 onoff("Link Bandwidth Management Interrupt Enable", reg, 1956 PCIE_LCSR_LBMIE); 1957 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1958 PCIE_LCSR_LABIE); 1959 printf(" DRS Signaling Control: "); 1960 switch (__SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) { 1961 case 0: 1962 printf("not reported\n"); 1963 break; 1964 case 1: 1965 printf("Interrupt Enabled\n"); 1966 break; 1967 case 2: 1968 printf("DRS to FRS Signaling Enabled\n"); 1969 break; 1970 default: 1971 printf("reserved\n"); 1972 break; 1973 } 1974 1975 /* Link Status Register */ 1976 reg = regs[o2i(capoff + PCIE_LCSR)]; 1977 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1978 printf(" Negotiated Link Speed: "); 1979 pci_print_pcie_linkspeed(PCIE_LCSR, 1980 __SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 1981 printf(" Negotiated Link Width: x%u lanes\n", 1982 (unsigned int)__SHIFTOUT(reg, PCIE_LCSR_NLW)); 1983 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1984 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1985 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1986 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1987 onoff("Link Bandwidth Management Status", reg, 1988 PCIE_LCSR_LINK_BW_MGMT); 1989 onoff("Link Autonomous Bandwidth Status", reg, 1990 PCIE_LCSR_LINK_AUTO_BW); 1991 } 1992 1993 if (check_slot == true) { 1994 pcireg_t slcap; 1995 1996 /* Slot Capability Register */ 1997 slcap = reg = regs[o2i(capoff + PCIE_SLCAP)]; 1998 printf(" Slot Capability Register: 0x%08x\n", reg); 1999 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 2000 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 2001 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 2002 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 2003 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 2004 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 2005 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 2006 printf(" Slot Power Limit Value: "); 2007 pci_conf_print_pcie_power(__SHIFTOUT(reg, PCIE_SLCAP_SPLV), 2008 __SHIFTOUT(reg, PCIE_SLCAP_SPLS)); 2009 onoff("Electromechanical Interlock Present", reg, 2010 PCIE_SLCAP_EIP); 2011 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 2012 printf(" Physical Slot Number: %d\n", 2013 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 2014 2015 /* Slot Control Register */ 2016 reg = regs[o2i(capoff + PCIE_SLCSR)]; 2017 printf(" Slot Control Register: 0x%04x\n", reg & 0xffff); 2018 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 2019 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 2020 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 2021 onoff("Presence Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 2022 onoff("Command Completed Interrupt Enabled", reg, 2023 PCIE_SLCSR_CCE); 2024 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 2025 /* 2026 * For Attention Indicator Control and Power Indicator Control, 2027 * it's allowed to be a read only value 0 if corresponding 2028 * capability register bit is 0. 2029 */ 2030 if (slcap & PCIE_SLCAP_AIP) { 2031 printf(" Attention Indicator Control: "); 2032 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 2033 case 0x0: 2034 printf("reserved\n"); 2035 break; 2036 case PCIE_SLCSR_IND_ON: 2037 printf("on\n"); 2038 break; 2039 case PCIE_SLCSR_IND_BLINK: 2040 printf("blink\n"); 2041 break; 2042 case PCIE_SLCSR_IND_OFF: 2043 printf("off\n"); 2044 break; 2045 } 2046 } 2047 if (slcap & PCIE_SLCAP_PIP) { 2048 printf(" Power Indicator Control: "); 2049 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 2050 case 0x0: 2051 printf("reserved\n"); 2052 break; 2053 case PCIE_SLCSR_IND_ON: 2054 printf("on\n"); 2055 break; 2056 case PCIE_SLCSR_IND_BLINK: 2057 printf("blink\n"); 2058 break; 2059 case PCIE_SLCSR_IND_OFF: 2060 printf("off\n"); 2061 break; 2062 } 2063 } 2064 printf(" Power Controller Control: Power %s\n", 2065 reg & PCIE_SLCSR_PCC ? "off" : "on"); 2066 onoff("Electromechanical Interlock Control", 2067 reg, PCIE_SLCSR_EIC); 2068 onoff("Data Link Layer State Changed Enable", reg, 2069 PCIE_SLCSR_DLLSCE); 2070 onoff("Auto Slot Power Limit Disable", reg, 2071 PCIE_SLCSR_AUTOSPLDIS); 2072 2073 /* Slot Status Register */ 2074 printf(" Slot Status Register: 0x%04x\n", reg >> 16); 2075 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 2076 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 2077 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 2078 onoff("Presence Detect Changed", reg, PCIE_SLCSR_PDC); 2079 onoff("Command Completed", reg, PCIE_SLCSR_CC); 2080 onoff("MRL Open", reg, PCIE_SLCSR_MS); 2081 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 2082 onoff("Electromechanical Interlock engaged", reg, 2083 PCIE_SLCSR_EIS); 2084 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 2085 } 2086 2087 if (check_rootport == true) { 2088 /* Root Control Register */ 2089 reg = regs[o2i(capoff + PCIE_RCR)]; 2090 printf(" Root Control Register: 0x%04x\n", reg & 0xffff); 2091 onoff("SERR on Correctable Error Enable", reg, 2092 PCIE_RCR_SERR_CER); 2093 onoff("SERR on Non-Fatal Error Enable", reg, 2094 PCIE_RCR_SERR_NFER); 2095 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 2096 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 2097 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 2098 2099 /* Root Capability Register */ 2100 printf(" Root Capability Register: 0x%04x\n", 2101 reg >> 16); 2102 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 2103 2104 /* Root Status Register */ 2105 reg = regs[o2i(capoff + PCIE_RSR)]; 2106 printf(" Root Status Register: 0x%08x\n", reg); 2107 printf(" PME Requester ID: 0x%04x\n", 2108 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 2109 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 2110 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 2111 } 2112 2113 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2114 if (pciever < 2) 2115 return; 2116 2117 /* Device Capabilities 2 */ 2118 reg = regs[o2i(capoff + PCIE_DCAP2)]; 2119 printf(" Device Capabilities 2: 0x%08x\n", reg); 2120 printf(" Completion Timeout Ranges Supported: "); 2121 val = reg & PCIE_DCAP2_COMPT_RANGE; 2122 switch (val) { 2123 case 0: 2124 printf("not supported\n"); 2125 break; 2126 default: 2127 for (i = 0; i <= 3; i++) { 2128 if (((val >> i) & 0x01) != 0) 2129 printf("%c", 'A' + i); 2130 } 2131 printf("\n"); 2132 } 2133 onoff("Completion Timeout Disable Supported", reg, 2134 PCIE_DCAP2_COMPT_DIS); 2135 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 2136 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 2137 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 2138 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 2139 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 2140 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 2141 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 2142 printf(" TPH Completer Supported: "); 2143 switch (__SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) { 2144 case 0: 2145 printf("Not supported\n"); 2146 break; 2147 case 1: 2148 printf("TPH\n"); 2149 break; 2150 case 3: 2151 printf("TPH and Extended TPH\n"); 2152 break; 2153 default: 2154 printf("(reserved value)\n"); 2155 break; 2156 2157 } 2158 printf(" LN System CLS: "); 2159 switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 2160 case 0x0: 2161 printf("Not supported or not in effect\n"); 2162 break; 2163 case 0x1: 2164 printf("64byte cachelines in effect\n"); 2165 break; 2166 case 0x2: 2167 printf("128byte cachelines in effect\n"); 2168 break; 2169 case 0x3: 2170 printf("Reserved\n"); 2171 break; 2172 } 2173 printf(" OBFF Supported: "); 2174 switch (__SHIFTOUT(reg, PCIE_DCAP2_OBFF)) { 2175 case 0x0: 2176 printf("Not supported\n"); 2177 break; 2178 case 0x1: 2179 printf("Message only\n"); 2180 break; 2181 case 0x2: 2182 printf("WAKE# only\n"); 2183 break; 2184 case 0x3: 2185 printf("Both\n"); 2186 break; 2187 } 2188 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 2189 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 2190 val = __SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP); 2191 printf(" Max End-End TLP Prefixes: %u\n", (val == 0) ? 4 : val); 2192 printf(" Emergency Power Reduction Supported: "); 2193 switch (__SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) { 2194 case 0x0: 2195 printf("Not supported\n"); 2196 break; 2197 case 0x1: 2198 printf("Device Specific mechanism\n"); 2199 break; 2200 case 0x2: 2201 printf("Form Factor spec or Device Specific mechanism\n"); 2202 break; 2203 case 0x3: 2204 printf("Reserved\n"); 2205 break; 2206 } 2207 onoff("Emergency Power Reduction Initialization Required", reg, 2208 PCIE_DCAP2_EMGPWRRED_INI); 2209 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 2210 2211 /* Device Control 2 */ 2212 reg = regs[o2i(capoff + PCIE_DCSR2)]; 2213 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 2214 printf(" Completion Timeout Value: "); 2215 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 2216 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 2217 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 2218 onoff("AtomicOp Requester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 2219 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 2220 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 2221 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 2222 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 2223 onoff("Emergency Power Reduction Request", reg, 2224 PCIE_DCSR2_EMGPWRRED_REQ); 2225 printf(" OBFF: "); 2226 switch (__SHIFTOUT(reg, PCIE_DCSR2_OBFF_EN)) { 2227 case 0x0: 2228 printf("Disabled\n"); 2229 break; 2230 case 0x1: 2231 printf("Enabled with Message Signaling Variation A\n"); 2232 break; 2233 case 0x2: 2234 printf("Enabled with Message Signaling Variation B\n"); 2235 break; 2236 case 0x3: 2237 printf("Enabled using WAKE# signaling\n"); 2238 break; 2239 } 2240 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 2241 2242 if (check_link) { 2243 bool drs_supported = false; 2244 2245 /* Link Capability 2 */ 2246 reg = regs[o2i(capoff + PCIE_LCAP2)]; 2247 /* If the vector is 0, LCAP2 is not implemented */ 2248 if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) { 2249 printf(" Link Capabilities 2: 0x%08x\n", reg); 2250 printf(" Supported Link Speeds Vector:"); 2251 pci_print_pcie_linkspeedvector( 2252 __SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 2253 printf("\n"); 2254 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 2255 printf(" " 2256 "Lower SKP OS Generation Supported Speed Vector:"); 2257 pci_print_pcie_linkspeedvector( 2258 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 2259 printf("\n"); 2260 printf(" " 2261 "Lower SKP OS Reception Supported Speed Vector:"); 2262 pci_print_pcie_linkspeedvector( 2263 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 2264 printf("\n"); 2265 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 2266 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 2267 } 2268 2269 /* Link Control 2 */ 2270 reg = regs[o2i(capoff + PCIE_LCSR2)]; 2271 /* If the vector is 0, LCAP2 is not implemented */ 2272 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 2273 printf(" Target Link Speed: "); 2274 pci_print_pcie_linkspeed(PCIE_LCSR2, 2275 __SHIFTOUT(reg, PCIE_LCSR2_TGT_LSPEED)); 2276 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 2277 onoff("HW Autonomous Speed Disabled", reg, 2278 PCIE_LCSR2_HW_AS_DIS); 2279 printf(" Selectable De-emphasis: "); 2280 pci_print_pcie_link_deemphasis( 2281 __SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP)); 2282 printf("\n"); 2283 printf(" Transmit Margin: %u\n", 2284 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 2285 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 2286 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 2287 printf(" Compliance Present/De-emphasis: "); 2288 pci_print_pcie_link_deemphasis( 2289 __SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP)); 2290 printf("\n"); 2291 2292 /* Link Status 2 */ 2293 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 2294 printf(" Current De-emphasis Level: "); 2295 pci_print_pcie_link_deemphasis( 2296 __SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL)); 2297 printf("\n"); 2298 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 2299 onoff("Equalization Phase 1 Successful", reg, 2300 PCIE_LCSR2_EQP1_SUC); 2301 onoff("Equalization Phase 2 Successful", reg, 2302 PCIE_LCSR2_EQP2_SUC); 2303 onoff("Equalization Phase 3 Successful", reg, 2304 PCIE_LCSR2_EQP3_SUC); 2305 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 2306 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 2307 if (drs_supported) { 2308 printf(" Downstream Component Presence: "); 2309 switch (__SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 2310 case PCIE_DSCOMPN_DOWN_NOTDETERM: 2311 printf("Link Down - Presence Not" 2312 " Determined\n"); 2313 break; 2314 case PCIE_DSCOMPN_DOWN_NOTPRES: 2315 printf("Link Down - Component Not Present\n"); 2316 break; 2317 case PCIE_DSCOMPN_DOWN_PRES: 2318 printf("Link Down - Component Present\n"); 2319 break; 2320 case PCIE_DSCOMPN_UP_PRES: 2321 printf("Link Up - Component Present\n"); 2322 break; 2323 case PCIE_DSCOMPN_UP_PRES_DRS: 2324 printf("Link Up - Component Present and DRS" 2325 " received\n"); 2326 break; 2327 default: 2328 printf("reserved\n"); 2329 break; 2330 } 2331 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 2332 } 2333 } 2334 2335 /* Slot Capability 2 */ 2336 /* Slot Control 2 */ 2337 /* Slot Status 2 */ 2338 } 2339 2340 static void 2341 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 2342 { 2343 pcireg_t reg; 2344 2345 printf("\n MSI-X Capability Register\n"); 2346 2347 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2348 printf(" Message Control register: 0x%04x\n", 2349 (reg >> 16) & 0xff); 2350 printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg)); 2351 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 2352 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 2353 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 2354 printf(" Table offset register: 0x%08x\n", reg); 2355 printf(" Table offset: 0x%08x\n", 2356 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 2357 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 2358 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 2359 printf(" Pending bit array register: 0x%08x\n", reg); 2360 printf(" Pending bit array offset: 0x%08x\n", 2361 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2362 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2363 } 2364 2365 static void 2366 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2367 { 2368 pcireg_t reg; 2369 2370 printf("\n Serial ATA Capability Register\n"); 2371 2372 reg = regs[o2i(capoff + PCI_SATA_REV)]; 2373 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2374 printf(" Revision: %u.%u\n", 2375 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2376 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2377 2378 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2379 2380 printf(" BAR Register: 0x%08x\n", reg); 2381 printf(" Register location: "); 2382 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2383 printf("in config space\n"); 2384 else { 2385 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2386 printf(" BAR offset: 0x%08x\n", 2387 (pcireg_t)__SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2388 } 2389 } 2390 2391 static void 2392 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2393 { 2394 pcireg_t reg; 2395 2396 printf("\n Advanced Features Capability Register\n"); 2397 2398 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2399 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2400 printf(" AF Structure Length: 0x%02x\n", 2401 (pcireg_t)__SHIFTOUT(reg, PCI_AF_LENGTH)); 2402 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2403 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2404 reg = regs[o2i(capoff + PCI_AFCSR)]; 2405 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2406 /* 2407 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2408 * and it's always 0 on read 2409 */ 2410 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2411 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2412 } 2413 2414 /* XXX pci_conf_print_ea_cap */ 2415 /* XXX pci_conf_print_fpb_cap */ 2416 2417 static struct { 2418 pcireg_t cap; 2419 const char *name; 2420 void (*printfunc)(const pcireg_t *, int); 2421 } pci_captab[] = { 2422 { PCI_CAP_RESERVED0, "reserved", NULL }, 2423 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2424 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2425 { PCI_CAP_VPD, "VPD", NULL }, 2426 { PCI_CAP_SLOTID, "SlotID", NULL }, 2427 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2428 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2429 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2430 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2431 { PCI_CAP_VENDSPEC, "Vendor-specific", 2432 pci_conf_print_vendspec_cap }, 2433 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2434 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2435 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2436 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2437 pci_conf_print_subsystem_cap }, 2438 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2439 { PCI_CAP_SECURE, "Secure Device", pci_conf_print_secure_cap }, 2440 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2441 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2442 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2443 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2444 { PCI_CAP_EA, "Enhanced Allocation", NULL }, 2445 { PCI_CAP_FPB, "Flattening Portal Bridge", NULL } 2446 }; 2447 2448 static int 2449 pci_conf_find_cap(const pcireg_t *regs, int capoff, unsigned int capid, 2450 int *offsetp) 2451 { 2452 pcireg_t rval; 2453 int off; 2454 2455 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2456 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2457 rval = regs[o2i(off)]; 2458 if (capid == PCI_CAPLIST_CAP(rval)) { 2459 if (offsetp != NULL) 2460 *offsetp = off; 2461 return 1; 2462 } 2463 } 2464 return 0; 2465 } 2466 2467 static void 2468 pci_conf_print_caplist( 2469 #ifdef _KERNEL 2470 pci_chipset_tag_t pc, pcitag_t tag, 2471 #endif 2472 const pcireg_t *regs, int capoff) 2473 { 2474 int off; 2475 pcireg_t foundcap; 2476 pcireg_t rval; 2477 bool foundtable[__arraycount(pci_captab)]; 2478 unsigned int i; 2479 2480 /* Clear table */ 2481 for (i = 0; i < __arraycount(pci_captab); i++) 2482 foundtable[i] = false; 2483 2484 /* Print capability register's offset and the type first */ 2485 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2486 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2487 rval = regs[o2i(off)]; 2488 printf(" Capability register at 0x%02x\n", off); 2489 2490 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2491 foundcap = PCI_CAPLIST_CAP(rval); 2492 if (foundcap < __arraycount(pci_captab)) { 2493 printf("%s)\n", pci_captab[foundcap].name); 2494 /* Mark as found */ 2495 foundtable[foundcap] = true; 2496 } else 2497 printf("unknown)\n"); 2498 } 2499 2500 /* 2501 * And then, print the detail of each capability registers 2502 * in capability value's order. 2503 */ 2504 for (i = 0; i < __arraycount(pci_captab); i++) { 2505 if (foundtable[i] == false) 2506 continue; 2507 2508 /* 2509 * The type was found. Search capability list again and 2510 * print all capabilities that the capabiliy type is 2511 * the same. This is required because some capabilities 2512 * appear multiple times (e.g. HyperTransport capability). 2513 */ 2514 #if 0 2515 if (pci_conf_find_cap(regs, capoff, i, &off)) { 2516 rval = regs[o2i(off)]; 2517 if (pci_captab[i].printfunc != NULL) 2518 pci_captab[i].printfunc(regs, off); 2519 } 2520 #else 2521 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2522 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2523 rval = regs[o2i(off)]; 2524 if ((PCI_CAPLIST_CAP(rval) == i) 2525 && (pci_captab[i].printfunc != NULL)) 2526 pci_captab[i].printfunc(regs, off); 2527 } 2528 #endif 2529 } 2530 } 2531 2532 /* Extended Capability */ 2533 2534 static void 2535 pci_conf_print_aer_cap_uc(pcireg_t reg) 2536 { 2537 2538 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2539 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2540 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2541 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2542 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2543 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2544 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2545 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2546 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2547 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2548 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2549 onoff("Unsupported Request Error", reg, 2550 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2551 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2552 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2553 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2554 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2555 onoff("TLP Prefix Blocked Error", reg, 2556 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2557 onoff("Poisoned TLP Egress Blocked", reg, 2558 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2559 } 2560 2561 static void 2562 pci_conf_print_aer_cap_cor(pcireg_t reg) 2563 { 2564 2565 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2566 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2567 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2568 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2569 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2570 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2571 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2572 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2573 } 2574 2575 static void 2576 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2577 { 2578 2579 printf(" First Error Pointer: 0x%04x\n", 2580 (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2581 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2582 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2583 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2584 onoff("ECRC Check Enable", reg, PCI_AER_ECRC_CHECK_ENABLE); 2585 onoff("Multiple Header Recording Capable", reg, 2586 PCI_AER_MULT_HDR_CAPABLE); 2587 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2588 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2589 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2590 2591 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2592 if (!tlp_prefix_log) 2593 return; 2594 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2595 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2596 } 2597 2598 static void 2599 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2600 { 2601 2602 onoff("Correctable Error Reporting Enable", reg, 2603 PCI_AER_ROOTERR_COR_ENABLE); 2604 onoff("Non-Fatal Error Reporting Enable", reg, 2605 PCI_AER_ROOTERR_NF_ENABLE); 2606 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2607 } 2608 2609 static void 2610 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2611 { 2612 2613 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2614 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2615 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2616 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2617 PCI_AER_ROOTERR_MULTI_UC_ERR); 2618 onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL); 2619 onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR); 2620 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2621 printf(" Advanced Error Interrupt Message Number: 0x%02x\n", 2622 (unsigned int)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2623 } 2624 2625 static void 2626 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2627 { 2628 2629 printf(" Correctable Source ID: 0x%04x\n", 2630 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2631 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2632 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2633 } 2634 2635 static void 2636 pci_conf_print_aer_cap(const pcireg_t *regs, int capoff, int extcapoff) 2637 { 2638 pcireg_t reg; 2639 int pcie_capoff; 2640 int pcie_devtype = -1; 2641 bool tlp_prefix_log = false; 2642 2643 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2644 reg = regs[o2i(pcie_capoff)]; 2645 pcie_devtype = PCIE_XCAP_TYPE(reg); 2646 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2647 if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2648 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2649 /* End-End TLP Prefix Supported */ 2650 if (reg & PCIE_DCAP2_EETLP_PREF) { 2651 tlp_prefix_log = true; 2652 } 2653 } 2654 } 2655 2656 printf("\n Advanced Error Reporting Register\n"); 2657 2658 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2659 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2660 pci_conf_print_aer_cap_uc(reg); 2661 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2662 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2663 pci_conf_print_aer_cap_uc(reg); 2664 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2665 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2666 pci_conf_print_aer_cap_uc(reg); 2667 2668 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2669 printf(" Correctable Error Status register: 0x%08x\n", reg); 2670 pci_conf_print_aer_cap_cor(reg); 2671 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2672 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2673 pci_conf_print_aer_cap_cor(reg); 2674 2675 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2676 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2677 reg); 2678 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2679 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2680 printf(" Header Log register:\n"); 2681 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2682 extcapoff + PCI_AER_ROOTERR_CMD); 2683 2684 switch (pcie_devtype) { 2685 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2686 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2687 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2688 printf(" Root Error Command register: 0x%08x\n", reg); 2689 pci_conf_print_aer_cap_rooterr_cmd(reg); 2690 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2691 printf(" Root Error Status register: 0x%08x\n", reg); 2692 pci_conf_print_aer_cap_rooterr_status(reg); 2693 2694 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2695 printf(" Error Source Identification register: 0x%08x\n", 2696 reg); 2697 pci_conf_print_aer_cap_errsrc_id(reg); 2698 break; 2699 } 2700 2701 if (tlp_prefix_log) { 2702 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2703 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2704 } 2705 } 2706 2707 static void 2708 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2709 pcireg_t parbsel, int parbsize) 2710 { 2711 pcireg_t reg; 2712 int num = 16 << parbsel; 2713 int num_per_reg = sizeof(pcireg_t) / parbsize; 2714 int i, j; 2715 2716 /* First, dump the table */ 2717 for (i = 0; i < num; i += num_per_reg) { 2718 reg = regs[o2i(off + i / num_per_reg)]; 2719 printf(" %s Arbitration Table: 0x%08x\n", name, reg); 2720 } 2721 /* And then, decode each entry */ 2722 for (i = 0; i < num; i += num_per_reg) { 2723 reg = regs[o2i(off + i / num_per_reg)]; 2724 for (j = 0; j < num_per_reg; j++) 2725 printf(" Phase[%d]: %d\n", j, reg); 2726 } 2727 } 2728 2729 static void 2730 pci_conf_print_vc_cap(const pcireg_t *regs, int capoff, int extcapoff) 2731 { 2732 pcireg_t reg, n; 2733 int parbtab, parbsize; 2734 pcireg_t parbsel; 2735 int varbtab, varbsize; 2736 pcireg_t varbsel; 2737 int i, count; 2738 2739 printf("\n Virtual Channel Register\n"); 2740 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2741 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2742 count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2743 printf(" Extended VC Count: %d\n", count); 2744 n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2745 printf(" Low Priority Extended VC Count: %u\n", n); 2746 n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2747 printf(" Reference Clock: %s\n", 2748 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 2749 parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2750 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2751 2752 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2753 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2754 onoff("Hardware fixed arbitration scheme", 2755 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2756 onoff("WRR arbitration with 32 phases", 2757 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2758 onoff("WRR arbitration with 64 phases", 2759 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2760 onoff("WRR arbitration with 128 phases", 2761 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2762 varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2763 printf(" VC Arbitration Table Offset: 0x%x\n", varbtab); 2764 2765 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2766 printf(" Port VC Control register: 0x%04x\n", reg); 2767 varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2768 printf(" VC Arbitration Select: 0x%x\n", varbsel); 2769 2770 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2771 printf(" Port VC Status register: 0x%04x\n", reg); 2772 onoff("VC Arbitration Table Status", 2773 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 2774 2775 for (i = 0; i < count + 1; i++) { 2776 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 2777 printf(" VC number %d\n", i); 2778 printf(" VC Resource Capability Register: 0x%08x\n", reg); 2779 onoff(" Non-configurable Hardware fixed arbitration scheme", 2780 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 2781 onoff(" WRR arbitration with 32 phases", 2782 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 2783 onoff(" WRR arbitration with 64 phases", 2784 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 2785 onoff(" WRR arbitration with 128 phases", 2786 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 2787 onoff(" Time-based WRR arbitration with 128 phases", 2788 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 2789 onoff(" WRR arbitration with 256 phases", 2790 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 2791 onoff(" Advanced Packet Switching", 2792 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 2793 onoff(" Reject Snoop Transaction", 2794 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 2795 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 2796 printf(" Maximum Time Slots: %d\n", n); 2797 parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S; 2798 printf(" Port Arbitration Table offset: 0x%02x\n", 2799 parbtab); 2800 2801 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 2802 printf(" VC Resource Control Register: 0x%08x\n", reg); 2803 printf(" TC/VC Map: 0x%02x\n", 2804 (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 2805 /* 2806 * The load Port Arbitration Table bit is used to update 2807 * the Port Arbitration logic and it's always 0 on read, so 2808 * we don't print it. 2809 */ 2810 parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 2811 printf(" Port Arbitration Select: 0x%x\n", parbsel); 2812 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 2813 printf(" VC ID: %d\n", n); 2814 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 2815 2816 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 2817 printf(" VC Resource Status Register: 0x%08x\n", reg); 2818 onoff(" Port Arbitration Table Status", 2819 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 2820 onoff(" VC Negotiation Pending", 2821 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 2822 2823 if ((parbtab != 0) && (parbsel != 0)) 2824 pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab, 2825 "Port", parbsel, parbsize); 2826 } 2827 2828 varbsize = 8; 2829 if ((varbtab != 0) && (varbsel != 0)) 2830 pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab, 2831 " VC", varbsel, varbsize); 2832 } 2833 2834 /* 2835 * Print Power limit. This encoding is the same among the following registers: 2836 * - The Captured Slot Power Limit in the PCIe Device Capability Register. 2837 * - The Slot Power Limit in the PCIe Slot Capability Register. 2838 * - The Base Power in the Data register of Power Budgeting capability. 2839 */ 2840 static void 2841 pci_conf_print_pcie_power(uint8_t base, unsigned int scale) 2842 { 2843 unsigned int sdiv = 1; 2844 2845 if ((scale == 0) && (base > 0xef)) { 2846 const char *s; 2847 2848 switch (base) { 2849 case 0xf0: 2850 s = "239W < x <= 250W"; 2851 break; 2852 case 0xf1: 2853 s = "250W < x <= 275W"; 2854 break; 2855 case 0xf2: 2856 s = "275W < x <= 300W"; 2857 break; 2858 default: 2859 s = "reserved for above 300W"; 2860 break; 2861 } 2862 printf("%s\n", s); 2863 return; 2864 } 2865 2866 for (unsigned int i = scale; i > 0; i--) 2867 sdiv *= 10; 2868 2869 printf("%u", base / sdiv); 2870 2871 if (scale != 0) { 2872 printf(".%u", base % sdiv); 2873 } 2874 printf ("W\n"); 2875 return; 2876 } 2877 2878 static const char * 2879 pci_conf_print_pwrbdgt_type(uint8_t reg) 2880 { 2881 2882 switch (reg) { 2883 case 0x00: 2884 return "PME Aux"; 2885 case 0x01: 2886 return "Auxilary"; 2887 case 0x02: 2888 return "Idle"; 2889 case 0x03: 2890 return "Sustained"; 2891 case 0x04: 2892 return "Sustained (Emergency Power Reduction)"; 2893 case 0x05: 2894 return "Maximum (Emergency Power Reduction)"; 2895 case 0x07: 2896 return "Maximum"; 2897 default: 2898 return "Unknown"; 2899 } 2900 } 2901 2902 static const char * 2903 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 2904 { 2905 2906 switch (reg) { 2907 case 0x00: 2908 return "Power(12V)"; 2909 case 0x01: 2910 return "Power(3.3V)"; 2911 case 0x02: 2912 return "Power(1.5V or 1.8V)"; 2913 case 0x07: 2914 return "Thermal"; 2915 default: 2916 return "Unknown"; 2917 } 2918 } 2919 2920 static void 2921 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int capoff, int extcapoff) 2922 { 2923 pcireg_t reg; 2924 2925 printf("\n Power Budgeting\n"); 2926 2927 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 2928 printf(" Data Select register: 0x%08x\n", reg); 2929 2930 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 2931 printf(" Data register: 0x%08x\n", reg); 2932 printf(" Base Power: "); 2933 pci_conf_print_pcie_power( 2934 __SHIFTOUT(reg, PCI_PWRBDGT_DATA_BASEPWR), 2935 __SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE)); 2936 printf(" PM Sub State: 0x%hhx\n", 2937 (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 2938 printf(" PM State: D%u\n", 2939 (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 2940 printf(" Type: %s\n", 2941 pci_conf_print_pwrbdgt_type( 2942 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 2943 printf(" Power Rail: %s\n", 2944 pci_conf_print_pwrbdgt_pwrrail( 2945 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 2946 2947 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 2948 printf(" Power Budget Capability register: 0x%08x\n", reg); 2949 onoff("System Allocated", 2950 reg, PCI_PWRBDGT_CAP_SYSALLOC); 2951 } 2952 2953 static const char * 2954 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 2955 { 2956 2957 switch (type) { 2958 case 0x00: 2959 return "Configuration Space Element"; 2960 case 0x01: 2961 return "System Egress Port or internal sink (memory)"; 2962 case 0x02: 2963 return "Internal Root Complex Link"; 2964 default: 2965 return "Unknown"; 2966 } 2967 } 2968 2969 static void 2970 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int capoff, int extcapoff) 2971 { 2972 pcireg_t reg; 2973 unsigned char nent, linktype; 2974 int i; 2975 2976 printf("\n Root Complex Link Declaration\n"); 2977 2978 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 2979 printf(" Element Self Description Register: 0x%08x\n", reg); 2980 printf(" Element Type: %s\n", 2981 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 2982 nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 2983 printf(" Number of Link Entries: %hhu\n", nent); 2984 printf(" Component ID: %hhu\n", 2985 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 2986 printf(" Port Number: %hhu\n", 2987 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 2988 for (i = 0; i < nent; i++) { 2989 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 2990 printf(" Link Entry %d:\n", i + 1); 2991 printf(" Link Description Register: 0x%08x\n", reg); 2992 onoff(" Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID); 2993 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 2994 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 2995 "Configuration Space", "Memory-Mapped Space"); 2996 onoff(" Associated RCRB Header", reg, 2997 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 2998 printf(" Target Component ID: %hhu\n", 2999 (unsigned char)__SHIFTOUT(reg, 3000 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 3001 printf(" Target Port Number: %hhu\n", 3002 (unsigned char)__SHIFTOUT(reg, 3003 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 3004 3005 if (linktype == 0) { 3006 /* Memory-Mapped Space */ 3007 reg = regs[o2i(extcapoff 3008 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 3009 printf(" Link Address Low Register: 0x%08x\n", 3010 reg); 3011 reg = regs[o2i(extcapoff 3012 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 3013 printf(" Link Address High Register: 0x%08x\n", 3014 reg); 3015 } else { 3016 unsigned int nb; 3017 pcireg_t lo, hi; 3018 3019 /* Configuration Space */ 3020 lo = regs[o2i(extcapoff 3021 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 3022 printf(" Configuration Space Low Register: " 3023 "0x%08x\n", lo); 3024 hi = regs[o2i(extcapoff 3025 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 3026 printf(" Configuration Space High Register: " 3027 "0x%08x\n", hi); 3028 nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 3029 printf(" N: %u\n", nb); 3030 printf(" Func: %hhu\n", 3031 (unsigned char)__SHIFTOUT(lo, 3032 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 3033 printf(" Dev: %hhu\n", 3034 (unsigned char)__SHIFTOUT(lo, 3035 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 3036 printf(" Bus: %hhu\n", 3037 (unsigned char)__SHIFTOUT(lo, 3038 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 3039 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 3040 printf(" Configuration Space Base Address: " 3041 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 3042 } 3043 } 3044 } 3045 3046 /* XXX pci_conf_print_rclink_ctl_cap */ 3047 3048 static void 3049 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int capoff, int extcapoff) 3050 { 3051 pcireg_t reg; 3052 3053 printf("\n Root Complex Event Collector Association\n"); 3054 3055 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 3056 printf(" Association Bitmap for Root Complex Integrated Devices:" 3057 " 0x%08x\n", reg); 3058 } 3059 3060 /* XXX pci_conf_print_mfvc_cap */ 3061 /* XXX pci_conf_print_vc2_cap */ 3062 /* XXX pci_conf_print_rcrb_cap */ 3063 /* XXX pci_conf_print_vendor_cap */ 3064 /* XXX pci_conf_print_cac_cap */ 3065 3066 static void 3067 pci_conf_print_acs_cap(const pcireg_t *regs, int capoff, int extcapoff) 3068 { 3069 pcireg_t reg, cap, ctl; 3070 unsigned int size, i; 3071 3072 printf("\n Access Control Services\n"); 3073 3074 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 3075 cap = reg & 0xffff; 3076 ctl = reg >> 16; 3077 printf(" ACS Capability register: 0x%08x\n", cap); 3078 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 3079 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 3080 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 3081 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 3082 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 3083 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 3084 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 3085 size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 3086 if (size == 0) 3087 size = 256; 3088 printf(" Egress Control Vector Size: %u\n", size); 3089 printf(" ACS Control register: 0x%08x\n", ctl); 3090 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 3091 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 3092 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 3093 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 3094 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 3095 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 3096 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 3097 3098 /* 3099 * If the P2P Egress Control Capability bit is 0, ignore the Egress 3100 * Control vector. 3101 */ 3102 if ((cap & PCI_ACS_CAP_E) == 0) 3103 return; 3104 for (i = 0; i < size; i += 32) 3105 printf(" Egress Control Vector [%u..%u]: 0x%08x\n", i + 31, 3106 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 3107 } 3108 3109 static void 3110 pci_conf_print_ari_cap(const pcireg_t *regs, int capoff, int extcapoff) 3111 { 3112 pcireg_t reg, cap, ctl; 3113 3114 printf("\n Alternative Routing-ID Interpretation Register\n"); 3115 3116 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3117 cap = reg & 0xffff; 3118 ctl = reg >> 16; 3119 printf(" Capability register: 0x%08x\n", cap); 3120 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 3121 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 3122 printf(" Next Function Number: %u\n", 3123 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 3124 printf(" Control register: 0x%08x\n", ctl); 3125 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 3126 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 3127 printf(" Function Group: %u\n", 3128 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 3129 } 3130 3131 static void 3132 pci_conf_print_ats_cap(const pcireg_t *regs, int capoff, int extcapoff) 3133 { 3134 pcireg_t reg, cap, ctl; 3135 unsigned int num; 3136 3137 printf("\n Address Translation Services\n"); 3138 3139 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3140 cap = reg & 0xffff; 3141 ctl = reg >> 16; 3142 printf(" Capability register: 0x%04x\n", cap); 3143 num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 3144 if (num == 0) 3145 num = 32; 3146 printf(" Invalidate Queue Depth: %u\n", num); 3147 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 3148 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 3149 3150 printf(" Control register: 0x%04x\n", ctl); 3151 printf(" Smallest Translation Unit: %u\n", 3152 (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU)); 3153 onoff("Enable", reg, PCI_ATS_CTL_EN); 3154 } 3155 3156 static void 3157 pci_conf_print_sernum_cap(const pcireg_t *regs, int capoff, int extcapoff) 3158 { 3159 pcireg_t lo, hi; 3160 3161 printf("\n Device Serial Number Register\n"); 3162 3163 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 3164 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 3165 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 3166 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 3167 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 3168 } 3169 3170 static void 3171 pci_conf_print_sriov_cap(const pcireg_t *regs, int capoff, int extcapoff) 3172 { 3173 char buf[sizeof("99999 MB")]; 3174 pcireg_t reg; 3175 pcireg_t total_vfs; 3176 int i; 3177 bool first; 3178 3179 printf("\n Single Root IO Virtualization Register\n"); 3180 3181 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 3182 printf(" Capabilities register: 0x%08x\n", reg); 3183 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 3184 onoff("ARI Capable Hierarchy Preserved", reg, 3185 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 3186 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 3187 printf(" VF Migration Interrupt Message Number: 0x%03x\n", 3188 (pcireg_t)__SHIFTOUT(reg, 3189 PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 3190 } 3191 3192 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 3193 printf(" Control register: 0x%04x\n", reg); 3194 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 3195 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 3196 onoff("VF Migration Interrupt Enable", reg, 3197 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 3198 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 3199 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 3200 3201 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 3202 printf(" Status register: 0x%04x\n", reg); 3203 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 3204 3205 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 3206 printf(" InitialVFs register: 0x%04x\n", reg); 3207 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 3208 printf(" TotalVFs register: 0x%04x\n", reg); 3209 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 3210 printf(" NumVFs register: 0x%04x\n", reg); 3211 3212 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 3213 printf(" Function Dependency Link register: 0x%04x\n", reg); 3214 3215 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 3216 printf(" First VF Offset register: 0x%04x\n", reg); 3217 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 3218 printf(" VF Stride register: 0x%04x\n", reg); 3219 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16; 3220 printf(" Device ID: 0x%04x\n", reg); 3221 3222 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 3223 printf(" Supported Page Sizes register: 0x%08x\n", reg); 3224 printf(" Supported Page Size:"); 3225 for (i = 0, first = true; i < 32; i++) { 3226 if (reg & __BIT(i)) { 3227 #ifdef _KERNEL 3228 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 3229 #else 3230 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 3231 HN_AUTOSCALE, 0); 3232 #endif 3233 printf("%s %s", first ? "" : ",", buf); 3234 first = false; 3235 } 3236 } 3237 printf("\n"); 3238 3239 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 3240 printf(" System Page Sizes register: 0x%08x\n", reg); 3241 printf(" Page Size: "); 3242 if (reg != 0) { 3243 int bitpos = ffs(reg) -1; 3244 3245 /* Assume only one bit is set. */ 3246 #ifdef _KERNEL 3247 format_bytes(buf, sizeof(buf), 1LL << (bitpos + 12)); 3248 #else 3249 humanize_number(buf, sizeof(buf), 1LL << (bitpos + 12), 3250 "B", HN_AUTOSCALE, 0); 3251 #endif 3252 printf("%s", buf); 3253 } else { 3254 printf("unknown"); 3255 } 3256 printf("\n"); 3257 3258 for (i = 0; i < 6; i++) { 3259 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 3260 printf(" VF BAR%d register: 0x%08x\n", i, reg); 3261 } 3262 3263 if (total_vfs > 0) { 3264 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 3265 printf(" VF Migration State Array Offset register: 0x%08x\n", 3266 reg); 3267 printf(" VF Migration State Offset: 0x%08x\n", 3268 (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 3269 i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 3270 printf(" VF Migration State BIR: "); 3271 if (i >= 0 && i <= 5) { 3272 printf("BAR%d", i); 3273 } else { 3274 printf("unknown BAR (%d)", i); 3275 } 3276 printf("\n"); 3277 } 3278 } 3279 3280 /* XXX pci_conf_print_mriov_cap */ 3281 3282 static void 3283 pci_conf_print_multicast_cap(const pcireg_t *regs, int capoff, int extcapoff) 3284 { 3285 pcireg_t reg, cap, ctl; 3286 pcireg_t regl, regh; 3287 uint64_t addr; 3288 int n; 3289 3290 printf("\n Multicast\n"); 3291 3292 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 3293 cap = reg & 0xffff; 3294 ctl = reg >> 16; 3295 printf(" Capability Register: 0x%04x\n", cap); 3296 printf(" Max Group: %u\n", 3297 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 3298 3299 /* Endpoint Only */ 3300 n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 3301 if (n > 0) 3302 printf(" Windw Size Requested: %d\n", 1 << (n - 1)); 3303 3304 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 3305 3306 printf(" Control Register: 0x%04x\n", ctl); 3307 printf(" Num Group: %u\n", 3308 (unsigned int)__SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 3309 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 3310 3311 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 3312 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 3313 printf(" Base Address Register 0: 0x%08x\n", regl); 3314 printf(" Base Address Register 1: 0x%08x\n", regh); 3315 printf(" Index Position: %u\n", 3316 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 3317 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 3318 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 3319 3320 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 3321 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 3322 printf(" Receive Register 0: 0x%08x\n", regl); 3323 printf(" Receive Register 1: 0x%08x\n", regh); 3324 3325 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 3326 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 3327 printf(" Block All Register 0: 0x%08x\n", regl); 3328 printf(" Block All Register 1: 0x%08x\n", regh); 3329 3330 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 3331 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 3332 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 3333 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 3334 3335 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 3336 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 3337 printf(" Overlay BAR 0: 0x%08x\n", regl); 3338 printf(" Overlay BAR 1: 0x%08x\n", regh); 3339 3340 n = regl & PCI_MCAST_OVERLAYL_SIZE; 3341 printf(" Overlay Size: "); 3342 if (n >= 6) 3343 printf("%d\n", n); 3344 else 3345 printf("off\n"); 3346 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 3347 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 3348 } 3349 3350 static void 3351 pci_conf_print_page_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3352 { 3353 pcireg_t reg, ctl, sta; 3354 3355 printf("\n Page Request\n"); 3356 3357 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 3358 ctl = reg & 0xffff; 3359 sta = reg >> 16; 3360 printf(" Control Register: 0x%04x\n", ctl); 3361 onoff("Enalbe", reg, PCI_PAGE_REQ_CTL_E); 3362 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 3363 3364 printf(" Status Register: 0x%04x\n", sta); 3365 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 3366 onoff("Unexpected Page Request Group Index", reg, 3367 PCI_PAGE_REQ_STA_UPRGI); 3368 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 3369 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 3370 3371 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 3372 printf(" Outstanding Page Request Capacity: %u\n", reg); 3373 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 3374 printf(" Outstanding Page Request Allocation: %u\n", reg); 3375 } 3376 3377 /* XXX pci_conf_print_amd_cap */ 3378 3379 #define MEM_PBUFSIZE sizeof("999GB") 3380 3381 static void 3382 pci_conf_print_resizbar_cap(const pcireg_t *regs, int capoff, int extcapoff) 3383 { 3384 pcireg_t cap, ctl; 3385 unsigned int bars, i, n; 3386 char pbuf[MEM_PBUFSIZE]; 3387 3388 printf("\n Resizable BAR\n"); 3389 3390 /* Get Number of Resizable BARs */ 3391 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))]; 3392 bars = __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR); 3393 printf(" Number of Resizable BARs: "); 3394 if (bars <= 6) 3395 printf("%u\n", bars); 3396 else { 3397 printf("incorrect (%u)\n", bars); 3398 return; 3399 } 3400 3401 for (n = 0; n < 6; n++) { 3402 cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))]; 3403 printf(" Capability register(%u): 0x%08x\n", n, cap); 3404 if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0) 3405 continue; /* Not Used */ 3406 printf(" Acceptable BAR sizes:"); 3407 for (i = 4; i <= 23; i++) { 3408 if ((cap & (1 << i)) != 0) { 3409 humanize_number(pbuf, MEM_PBUFSIZE, 3410 (int64_t)1024 * 1024 << (i - 4), "B", 3411 #ifdef _KERNEL 3412 1); 3413 #else 3414 HN_AUTOSCALE, HN_NOSPACE); 3415 #endif 3416 printf(" %s", pbuf); 3417 } 3418 } 3419 printf("\n"); 3420 3421 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))]; 3422 printf(" Control register(%u): 0x%08x\n", n, ctl); 3423 printf(" BAR Index: %u\n", 3424 (unsigned int)__SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX)); 3425 humanize_number(pbuf, MEM_PBUFSIZE, 3426 (int64_t)1024 * 1024 3427 << __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ), 3428 "B", 3429 #ifdef _KERNEL 3430 1); 3431 #else 3432 HN_AUTOSCALE, HN_NOSPACE); 3433 #endif 3434 printf(" BAR Size: %s\n", pbuf); 3435 } 3436 } 3437 3438 static void 3439 pci_conf_print_dpa_cap(const pcireg_t *regs, int capoff, int extcapoff) 3440 { 3441 pcireg_t reg; 3442 unsigned int substmax, i; 3443 3444 printf("\n Dynamic Power Allocation\n"); 3445 3446 reg = regs[o2i(extcapoff + PCI_DPA_CAP)]; 3447 printf(" Capability register: 0x%08x\n", reg); 3448 substmax = __SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX); 3449 printf(" Substate Max: %u\n", substmax); 3450 printf(" Transition Latency Unit: "); 3451 switch (__SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) { 3452 case 0: 3453 printf("1ms\n"); 3454 break; 3455 case 1: 3456 printf("10ms\n"); 3457 break; 3458 case 2: 3459 printf("100ms\n"); 3460 break; 3461 default: 3462 printf("reserved\n"); 3463 break; 3464 } 3465 printf(" Power Allocation Scale: "); 3466 switch (__SHIFTOUT(reg, PCI_DPA_CAP_PAS)) { 3467 case 0: 3468 printf("10.0x\n"); 3469 break; 3470 case 1: 3471 printf("1.0x\n"); 3472 break; 3473 case 2: 3474 printf("0.1x\n"); 3475 break; 3476 case 3: 3477 printf("0.01x\n"); 3478 break; 3479 } 3480 printf(" Transition Latency Value 0: %u\n", 3481 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY0)); 3482 printf(" Transition Latency Value 1: %u\n", 3483 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); 3484 3485 reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; 3486 printf(" Latency Indicatior register: 0x%08x\n", reg); 3487 3488 reg = regs[o2i(extcapoff + PCI_DPA_CS)]; 3489 printf(" Status register: 0x%04x\n", reg & 0xffff); 3490 printf(" Substate Status: 0x%02x\n", 3491 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT)); 3492 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN); 3493 printf(" Control register: 0x%04x\n", reg >> 16); 3494 printf(" Substate Control: 0x%02x\n", 3495 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL)); 3496 3497 for (i = 0; i <= substmax; i++) 3498 printf(" Substate Power Allocation register %d: 0x%02x\n", 3499 i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff)); 3500 } 3501 3502 static const char * 3503 pci_conf_print_tph_req_cap_sttabloc(uint8_t val) 3504 { 3505 3506 switch (val) { 3507 case PCI_TPH_REQ_STTBLLOC_NONE: 3508 return "Not Present"; 3509 case PCI_TPH_REQ_STTBLLOC_TPHREQ: 3510 return "in the TPH Requester Capability Structure"; 3511 case PCI_TPH_REQ_STTBLLOC_MSIX: 3512 return "in the MSI-X Table"; 3513 default: 3514 return "Unknown"; 3515 } 3516 } 3517 3518 static void 3519 pci_conf_print_tph_req_cap(const pcireg_t *regs, int capoff, int extcapoff) 3520 { 3521 pcireg_t reg; 3522 int size, i, j; 3523 uint8_t sttbloc; 3524 3525 printf("\n TPH Requester Extended Capability\n"); 3526 3527 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3528 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3529 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3530 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3531 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3532 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3533 sttbloc = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC); 3534 printf(" ST Table Location: %s\n", 3535 pci_conf_print_tph_req_cap_sttabloc(sttbloc)); 3536 size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3537 printf(" ST Table Size: %d\n", size); 3538 3539 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CTL)]; 3540 printf(" TPH Requester Control register: 0x%08x\n", reg); 3541 printf(" ST Mode Select: "); 3542 switch (__SHIFTOUT(reg, PCI_TPH_REQ_CTL_STSEL)) { 3543 case PCI_TPH_REQ_CTL_STSEL_NO: 3544 printf("No ST Mode\n"); 3545 break; 3546 case PCI_TPH_REQ_CTL_STSEL_IV: 3547 printf("Interrupt Vector Mode\n"); 3548 break; 3549 case PCI_TPH_REQ_CTL_STSEL_DS: 3550 printf("Device Specific Mode\n"); 3551 break; 3552 default: 3553 printf("(reserved vaule)\n"); 3554 break; 3555 } 3556 printf(" TPH Requester Enable: "); 3557 switch (__SHIFTOUT(reg, PCI_TPH_REQ_CTL_TPHREQEN)) { 3558 case PCI_TPH_REQ_CTL_TPHREQEN_NO: /* 0x0 */ 3559 printf("Not permitted\n"); 3560 break; 3561 case PCI_TPH_REQ_CTL_TPHREQEN_TPH: 3562 printf("TPH and not Extended TPH\n"); 3563 break; 3564 case PCI_TPH_REQ_CTL_TPHREQEN_ETPH: 3565 printf("TPH and Extended TPH"); 3566 break; 3567 default: 3568 printf("(reserved vaule)\n"); 3569 break; 3570 } 3571 3572 if (sttbloc != PCI_TPH_REQ_STTBLLOC_TPHREQ) 3573 return; 3574 3575 for (i = 0; i < size ; i += 2) { 3576 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3577 for (j = 0; j < 2 ; j++) { 3578 uint32_t entry = reg; 3579 3580 if (j != 0) 3581 entry >>= 16; 3582 entry &= 0xffff; 3583 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3584 i + j, entry); 3585 } 3586 } 3587 } 3588 3589 static void 3590 pci_conf_print_ltr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3591 { 3592 pcireg_t reg; 3593 3594 printf("\n Latency Tolerance Reporting\n"); 3595 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)]; 3596 printf(" Max Snoop Latency Register: 0x%04x\n", reg & 0xffff); 3597 printf(" Max Snoop Latency: %juns\n", 3598 (uintmax_t)(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL) 3599 * PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE)))); 3600 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg >> 16); 3601 printf(" Max No-Snoop Latency: %juns\n", 3602 (uintmax_t)(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL) 3603 * PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE)))); 3604 } 3605 3606 static void 3607 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int capoff, int extcapoff) 3608 { 3609 int pcie_capoff; 3610 pcireg_t reg; 3611 int i, maxlinkwidth; 3612 3613 printf("\n Secondary PCI Express Register\n"); 3614 3615 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3616 printf(" Link Control 3 register: 0x%08x\n", reg); 3617 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3618 onoff("Link Equalization Request Interrupt Enable", 3619 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3620 printf(" Enable Lower SKP OS Generation Vector:"); 3621 pci_print_pcie_linkspeedvector( 3622 __SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3623 printf("\n"); 3624 3625 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3626 printf(" Lane Error Status register: 0x%08x\n", reg); 3627 3628 /* Get Max Link Width */ 3629 if (pci_conf_find_cap(regs, capoff, PCI_CAP_PCIEXPRESS, &pcie_capoff)){ 3630 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3631 maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3632 } else { 3633 printf("error: falied to get PCIe capablity\n"); 3634 return; 3635 } 3636 for (i = 0; i < maxlinkwidth; i++) { 3637 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3638 if (i % 2 != 0) 3639 reg >>= 16; 3640 else 3641 reg &= 0xffff; 3642 printf(" Equalization Control Register (Link %d): 0x%04x\n", 3643 i, reg); 3644 printf(" Downstream Port Transmit Preset: 0x%x\n", 3645 (pcireg_t)__SHIFTOUT(reg, 3646 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3647 printf(" Downstream Port Receive Hint: 0x%x\n", 3648 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3649 printf(" Upstream Port Transmit Preset: 0x%x\n", 3650 (pcireg_t)__SHIFTOUT(reg, 3651 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3652 printf(" Upstream Port Receive Hint: 0x%x\n", 3653 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3654 } 3655 } 3656 3657 /* XXX pci_conf_print_pmux_cap */ 3658 3659 static void 3660 pci_conf_print_pasid_cap(const pcireg_t *regs, int capoff, int extcapoff) 3661 { 3662 pcireg_t reg, cap, ctl; 3663 unsigned int num; 3664 3665 printf("\n Process Address Space ID\n"); 3666 3667 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3668 cap = reg & 0xffff; 3669 ctl = reg >> 16; 3670 printf(" PASID Capability Register: 0x%04x\n", cap); 3671 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3672 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3673 num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3674 printf(" Max PASID Width: %u\n", num); 3675 3676 printf(" PASID Control Register: 0x%04x\n", ctl); 3677 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3678 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3679 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3680 } 3681 3682 static void 3683 pci_conf_print_lnr_cap(const pcireg_t *regs, int capoff, int extcapoff) 3684 { 3685 pcireg_t reg, cap, ctl; 3686 unsigned int num; 3687 3688 printf("\n LN Requester\n"); 3689 3690 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3691 cap = reg & 0xffff; 3692 ctl = reg >> 16; 3693 printf(" LNR Capability register: 0x%04x\n", cap); 3694 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 3695 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 3696 num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 3697 printf(" LNR Registration MAX: %u\n", num); 3698 3699 printf(" LNR Control register: 0x%04x\n", ctl); 3700 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 3701 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 3702 num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 3703 printf(" LNR Registration Limit: %u\n", num); 3704 } 3705 3706 static void 3707 pci_conf_print_dpc_pio(pcireg_t r) 3708 { 3709 onoff("Cfg Request received UR Completion", r,PCI_DPC_RPPIO_CFGUR_CPL); 3710 onoff("Cfg Request received CA Completion", r,PCI_DPC_RPPIO_CFGCA_CPL); 3711 onoff("Cfg Request Completion Timeout", r, PCI_DPC_RPPIO_CFG_CTO); 3712 onoff("I/O Request received UR Completion", r, PCI_DPC_RPPIO_IOUR_CPL); 3713 onoff("I/O Request received CA Completion", r, PCI_DPC_RPPIO_IOCA_CPL); 3714 onoff("I/O Request Completion Timeout", r, PCI_DPC_RPPIO_IO_CTO); 3715 onoff("Mem Request received UR Completion", r,PCI_DPC_RPPIO_MEMUR_CPL); 3716 onoff("Mem Request received CA Completion", r,PCI_DPC_RPPIO_MEMCA_CPL); 3717 onoff("Mem Request Completion Timeout", r, PCI_DPC_RPPIO_MEM_CTO); 3718 } 3719 3720 static void 3721 pci_conf_print_dpc_cap(const pcireg_t *regs, int capoff, int extcapoff) 3722 { 3723 pcireg_t reg, cap, ctl, stat, errsrc; 3724 const char *trigstr; 3725 bool rpext; 3726 3727 printf("\n Downstream Port Containment\n"); 3728 3729 reg = regs[o2i(extcapoff + PCI_DPC_CCR)]; 3730 cap = reg & 0xffff; 3731 ctl = reg >> 16; 3732 rpext = (reg & PCI_DPCCAP_RPEXT) ? true : false; 3733 printf(" DPC Capability register: 0x%04x\n", cap); 3734 printf(" DPC Interrupt Message Number: %02x\n", 3735 (unsigned int)(cap & PCI_DPCCAP_IMSGN)); 3736 onoff("RP Extensions for DPC", reg, PCI_DPCCAP_RPEXT); 3737 onoff("Poisoned TLP Egress Blocking Supported", reg, 3738 PCI_DPCCAP_POISONTLPEB); 3739 onoff("DPC Software Triggering Supported", reg, PCI_DPCCAP_SWTRIG); 3740 printf(" RP PIO Log Size: %u\n", 3741 (unsigned int)__SHIFTOUT(reg, PCI_DPCCAP_RPPIOLOGSZ)); 3742 onoff("DL_Active ERR_COR Signaling Supported", reg, 3743 PCI_DPCCAP_DLACTECORS); 3744 printf(" DPC Control register: 0x%04x\n", ctl); 3745 switch (__SHIFTOUT(reg, PCI_DPCCTL_TIRGEN)) { 3746 case 0: 3747 trigstr = "disabled"; 3748 break; 3749 case 1: 3750 trigstr = "enabled(ERR_FATAL)"; 3751 break; 3752 case 2: 3753 trigstr = "enabled(ERR_NONFATAL or ERR_FATAL)"; 3754 break; 3755 default: 3756 trigstr = "(reserverd)"; 3757 break; 3758 } 3759 printf(" DPC Trigger Enable: %s\n", trigstr); 3760 printf(" DPC Completion Control: %s Completion Status\n", 3761 (reg & PCI_DPCCTL_COMPCTL) 3762 ? "Unsupported Request(UR)" : "Completer Abort(CA)"); 3763 onoff("DPC Interrupt Enable", reg, PCI_DPCCTL_IE); 3764 onoff("DPC ERR_COR Enable", reg, PCI_DPCCTL_ERRCOREN); 3765 onoff("Poisoned TLP Egress Blocking Enable", reg, 3766 PCI_DPCCTL_POISONTLPEB); 3767 onoff("DPC Software Trigger", reg, PCI_DPCCTL_SWTRIG); 3768 onoff("DL_Active ERR_COR Enable", reg, PCI_DPCCTL_DLACTECOR); 3769 3770 reg = regs[o2i(extcapoff + PCI_DPC_STATESID)]; 3771 stat = reg & 0xffff; 3772 errsrc = reg >> 16; 3773 printf(" DPC Status register: 0x%04x\n", stat); 3774 onoff("DPC Trigger Status", reg, PCI_DPCSTAT_TSTAT); 3775 switch (__SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 3776 case 0: 3777 trigstr = "an unmasked uncorrectable error"; 3778 break; 3779 case 1: 3780 trigstr = "receiving an ERR_NONFATAL"; 3781 break; 3782 case 2: 3783 trigstr = "receiving an ERR_FATAL"; 3784 break; 3785 case 3: 3786 trigstr = "DPC Trigger Reason Extension field"; 3787 break; 3788 } 3789 printf(" DPC Trigger Reason: Due to %s\n", trigstr); 3790 onoff("DPC Interrupt Status", reg, PCI_DPCSTAT_ISTAT); 3791 if (rpext) 3792 onoff("DPC RP Busy", reg, PCI_DPCSTAT_RPBUSY); 3793 switch (__SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 3794 case 0: 3795 trigstr = "Due to RP PIO error"; 3796 break; 3797 case 1: 3798 trigstr = "Due to the DPC Software trigger bit"; 3799 break; 3800 default: 3801 trigstr = "(reserved)"; 3802 break; 3803 } 3804 printf(" DPC Trigger Reason Extension: %s\n", trigstr); 3805 if (rpext) 3806 printf(" RP PIO First Error Pointer: %02x\n", 3807 (unsigned int)__SHIFTOUT(reg, PCI_DPCSTAT_RPPIOFEP)); 3808 printf(" DPC Error Source ID register: 0x%04x\n", errsrc); 3809 3810 if (!rpext) 3811 return; 3812 /* 3813 * All of the following registers are implemented by a device which has 3814 * RP Extensions for DPC 3815 */ 3816 3817 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_STAT)]; 3818 printf(" RP PIO Status Register: 0x%04x\n", reg); 3819 pci_conf_print_dpc_pio(reg); 3820 3821 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_MASK)]; 3822 printf(" RP PIO Mask Register: 0x%04x\n", reg); 3823 pci_conf_print_dpc_pio(reg); 3824 3825 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SEVE)]; 3826 printf(" RP PIO Severity Register: 0x%04x\n", reg); 3827 pci_conf_print_dpc_pio(reg); 3828 3829 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SYSERR)]; 3830 printf(" RP PIO SysError Register: 0x%04x\n", reg); 3831 pci_conf_print_dpc_pio(reg); 3832 3833 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_EXCPT)]; 3834 printf(" RP PIO Exception Register: 0x%04x\n", reg); 3835 pci_conf_print_dpc_pio(reg); 3836 3837 printf(" RP PIO Header Log Register: start from 0x%03x\n", 3838 extcapoff + PCI_DPC_RPPIO_HLOG); 3839 printf(" RP PIO ImpSpec Log Register: start from 0x%03x\n", 3840 extcapoff + PCI_DPC_RPPIO_IMPSLOG); 3841 printf(" RP PIO TPL Prefix Log Register: start from 0x%03x\n", 3842 extcapoff + PCI_DPC_RPPIO_TLPPLOG); 3843 } 3844 3845 3846 static int 3847 pci_conf_l1pm_cap_tposcale(unsigned char scale) 3848 { 3849 3850 /* Return scale in us */ 3851 switch (scale) { 3852 case 0x0: 3853 return 2; 3854 case 0x1: 3855 return 10; 3856 case 0x2: 3857 return 100; 3858 default: 3859 return -1; 3860 } 3861 } 3862 3863 static void 3864 pci_conf_print_l1pm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3865 { 3866 pcireg_t reg; 3867 int scale, val; 3868 3869 printf("\n L1 PM Substates\n"); 3870 3871 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 3872 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 3873 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 3874 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 3875 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 3876 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 3877 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 3878 printf(" Port Common Mode Restore Time: %uus\n", 3879 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 3880 scale = pci_conf_l1pm_cap_tposcale( 3881 __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 3882 val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 3883 printf(" Port T_POWER_ON: "); 3884 if (scale == -1) 3885 printf("unknown\n"); 3886 else 3887 printf("%dus\n", val * scale); 3888 3889 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 3890 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 3891 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 3892 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 3893 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 3894 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 3895 printf(" Common Mode Restore Time: %uus\n", 3896 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 3897 scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 3898 val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 3899 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 3900 3901 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 3902 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 3903 scale = pci_conf_l1pm_cap_tposcale( 3904 __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 3905 val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 3906 printf(" T_POWER_ON: "); 3907 if (scale == -1) 3908 printf("unknown\n"); 3909 else 3910 printf("%dus\n", val * scale); 3911 } 3912 3913 static void 3914 pci_conf_print_ptm_cap(const pcireg_t *regs, int capoff, int extcapoff) 3915 { 3916 pcireg_t reg; 3917 uint32_t val; 3918 3919 printf("\n Precision Time Management\n"); 3920 3921 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 3922 printf(" PTM Capability register: 0x%08x\n", reg); 3923 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 3924 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 3925 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 3926 printf(" Local Clock Granularity: "); 3927 val = __SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 3928 switch (val) { 3929 case 0: 3930 printf("Not implemented\n"); 3931 break; 3932 case 0xffff: 3933 printf("> 254ns\n"); 3934 break; 3935 default: 3936 printf("%uns\n", val); 3937 break; 3938 } 3939 3940 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 3941 printf(" PTM Control register: 0x%08x\n", reg); 3942 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 3943 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 3944 printf(" Effective Granularity: "); 3945 val = __SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 3946 switch (val) { 3947 case 0: 3948 printf("Unknown\n"); 3949 break; 3950 case 0xffff: 3951 printf("> 254ns\n"); 3952 break; 3953 default: 3954 printf("%uns\n", val); 3955 break; 3956 } 3957 } 3958 3959 /* XXX pci_conf_print_mpcie_cap */ 3960 /* XXX pci_conf_print_frsq_cap */ 3961 /* XXX pci_conf_print_rtr_cap */ 3962 /* XXX pci_conf_print_desigvndsp_cap */ 3963 /* XXX pci_conf_print_vf_resizbar_cap */ 3964 /* XXX pci_conf_print_hierarchyid_cap */ 3965 /* XXX pci_conf_print_npem_cap */ 3966 3967 #undef MS 3968 #undef SM 3969 #undef RW 3970 3971 static struct { 3972 pcireg_t cap; 3973 const char *name; 3974 void (*printfunc)(const pcireg_t *, int, int); 3975 } pci_extcaptab[] = { 3976 { 0, "reserved", 3977 NULL }, 3978 { PCI_EXTCAP_AER, "Advanced Error Reporting", 3979 pci_conf_print_aer_cap }, 3980 { PCI_EXTCAP_VC, "Virtual Channel", 3981 pci_conf_print_vc_cap }, 3982 { PCI_EXTCAP_SERNUM, "Device Serial Number", 3983 pci_conf_print_sernum_cap }, 3984 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 3985 pci_conf_print_pwrbdgt_cap }, 3986 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 3987 pci_conf_print_rclink_dcl_cap }, 3988 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 3989 NULL }, 3990 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 3991 pci_conf_print_rcec_assoc_cap }, 3992 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 3993 NULL }, 3994 { PCI_EXTCAP_VC2, "Virtual Channel", 3995 NULL }, 3996 { PCI_EXTCAP_RCRB, "RCRB Header", 3997 NULL }, 3998 { PCI_EXTCAP_VENDOR, "Vendor Unique", 3999 NULL }, 4000 { PCI_EXTCAP_CAC, "Configuration Access Correction", 4001 NULL }, 4002 { PCI_EXTCAP_ACS, "Access Control Services", 4003 pci_conf_print_acs_cap }, 4004 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 4005 pci_conf_print_ari_cap }, 4006 { PCI_EXTCAP_ATS, "Address Translation Services", 4007 pci_conf_print_ats_cap }, 4008 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 4009 pci_conf_print_sriov_cap }, 4010 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 4011 NULL }, 4012 { PCI_EXTCAP_MCAST, "Multicast", 4013 pci_conf_print_multicast_cap }, 4014 { PCI_EXTCAP_PAGE_REQ, "Page Request", 4015 pci_conf_print_page_req_cap }, 4016 { PCI_EXTCAP_AMD, "Reserved for AMD", 4017 NULL }, 4018 { PCI_EXTCAP_RESIZBAR, "Resizable BAR", 4019 pci_conf_print_resizbar_cap }, 4020 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 4021 pci_conf_print_dpa_cap }, 4022 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 4023 pci_conf_print_tph_req_cap }, 4024 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 4025 pci_conf_print_ltr_cap }, 4026 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 4027 pci_conf_print_sec_pcie_cap }, 4028 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 4029 NULL }, 4030 { PCI_EXTCAP_PASID, "Process Address Space ID", 4031 pci_conf_print_pasid_cap }, 4032 { PCI_EXTCAP_LNR, "LN Requester", 4033 pci_conf_print_lnr_cap }, 4034 { PCI_EXTCAP_DPC, "Downstream Port Containment", 4035 pci_conf_print_dpc_cap }, 4036 { PCI_EXTCAP_L1PM, "L1 PM Substates", 4037 pci_conf_print_l1pm_cap }, 4038 { PCI_EXTCAP_PTM, "Precision Time Management", 4039 pci_conf_print_ptm_cap }, 4040 { PCI_EXTCAP_MPCIE, "M-PCIe", 4041 NULL }, 4042 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 4043 NULL }, 4044 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 4045 NULL }, 4046 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 4047 NULL }, 4048 { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", 4049 NULL }, 4050 { PCI_EXTCAP_HIERARCHYID, "Hierarchy ID", 4051 NULL }, 4052 { PCI_EXTCAP_NPEM, "Native PCIe Enclosure Management", 4053 NULL }, 4054 }; 4055 4056 static int 4057 pci_conf_find_extcap(const pcireg_t *regs, int capoff, unsigned int capid, 4058 int *offsetp) 4059 { 4060 int off; 4061 pcireg_t rval; 4062 4063 for (off = PCI_EXTCAPLIST_BASE; 4064 off != 0; 4065 off = PCI_EXTCAPLIST_NEXT(rval)) { 4066 rval = regs[o2i(off)]; 4067 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 4068 if (offsetp != NULL) 4069 *offsetp = off; 4070 return 1; 4071 } 4072 } 4073 return 0; 4074 } 4075 4076 static void 4077 pci_conf_print_extcaplist( 4078 #ifdef _KERNEL 4079 pci_chipset_tag_t pc, pcitag_t tag, 4080 #endif 4081 const pcireg_t *regs, int capoff) 4082 { 4083 int off; 4084 pcireg_t foundcap; 4085 pcireg_t rval; 4086 bool foundtable[__arraycount(pci_extcaptab)]; 4087 unsigned int i; 4088 4089 /* Check Extended capability structure */ 4090 off = PCI_EXTCAPLIST_BASE; 4091 rval = regs[o2i(off)]; 4092 if (rval == 0xffffffff || rval == 0) 4093 return; 4094 4095 /* Clear table */ 4096 for (i = 0; i < __arraycount(pci_extcaptab); i++) 4097 foundtable[i] = false; 4098 4099 /* Print extended capability register's offset and the type first */ 4100 for (;;) { 4101 printf(" Extended Capability Register at 0x%02x\n", off); 4102 4103 foundcap = PCI_EXTCAPLIST_CAP(rval); 4104 printf(" type: 0x%04x (", foundcap); 4105 if (foundcap < __arraycount(pci_extcaptab)) { 4106 printf("%s)\n", pci_extcaptab[foundcap].name); 4107 /* Mark as found */ 4108 foundtable[foundcap] = true; 4109 } else 4110 printf("unknown)\n"); 4111 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 4112 4113 off = PCI_EXTCAPLIST_NEXT(rval); 4114 if (off == 0) 4115 break; 4116 else if (off <= PCI_CONF_SIZE) { 4117 printf(" next pointer: 0x%03x (incorrect)\n", off); 4118 return; 4119 } 4120 rval = regs[o2i(off)]; 4121 } 4122 4123 /* 4124 * And then, print the detail of each capability registers 4125 * in capability value's order. 4126 */ 4127 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 4128 if (foundtable[i] == false) 4129 continue; 4130 4131 /* 4132 * The type was found. Search capability list again and 4133 * print all capabilities that the capabiliy type is 4134 * the same. 4135 */ 4136 if (pci_conf_find_extcap(regs, capoff, i, &off) == 0) 4137 continue; 4138 rval = regs[o2i(off)]; 4139 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 4140 || (pci_extcaptab[i].printfunc == NULL)) 4141 continue; 4142 4143 pci_extcaptab[i].printfunc(regs, capoff, off); 4144 4145 } 4146 } 4147 4148 /* Print the Secondary Status Register. */ 4149 static void 4150 pci_conf_print_ssr(pcireg_t rval) 4151 { 4152 pcireg_t devsel; 4153 4154 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 4155 onoff("66 MHz capable", rval, __BIT(5)); 4156 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 4157 onoff("Fast back-to-back capable", rval, __BIT(7)); 4158 onoff("Data parity error detected", rval, __BIT(8)); 4159 4160 printf(" DEVSEL timing: "); 4161 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 4162 switch (devsel) { 4163 case 0: 4164 printf("fast"); 4165 break; 4166 case 1: 4167 printf("medium"); 4168 break; 4169 case 2: 4170 printf("slow"); 4171 break; 4172 default: 4173 printf("unknown/reserved"); /* XXX */ 4174 break; 4175 } 4176 printf(" (0x%x)\n", devsel); 4177 4178 onoff("Signalled target abort", rval, __BIT(11)); 4179 onoff("Received target abort", rval, __BIT(12)); 4180 onoff("Received master abort", rval, __BIT(13)); 4181 onoff("Received system error", rval, __BIT(14)); 4182 onoff("Detected parity error", rval, __BIT(15)); 4183 } 4184 4185 static void 4186 pci_conf_print_type0( 4187 #ifdef _KERNEL 4188 pci_chipset_tag_t pc, pcitag_t tag, 4189 #endif 4190 const pcireg_t *regs) 4191 { 4192 int off, width; 4193 pcireg_t rval; 4194 const char *str; 4195 4196 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 4197 #ifdef _KERNEL 4198 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4199 #else 4200 width = pci_conf_print_bar(regs, off, NULL); 4201 #endif 4202 } 4203 4204 printf(" Cardbus CIS Pointer: 0x%08x\n", 4205 regs[o2i(PCI_CARDBUS_CIS_REG)]); 4206 4207 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 4208 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4209 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4210 4211 rval = regs[o2i(PCI_MAPREG_ROM)]; 4212 printf(" Expansion ROM Base Address Register: 0x%08x\n", rval); 4213 printf(" base: 0x%08x\n", (uint32_t)PCI_MAPREG_ROM_ADDR(rval)); 4214 onoff("Expansion ROM Enable", rval, PCI_MAPREG_ROM_ENABLE); 4215 printf(" Validation Status: "); 4216 switch (__SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_STAT)) { 4217 case PCI_MAPREG_ROM_VSTAT_NOTSUPP: 4218 str = "Validation not supported"; 4219 break; 4220 case PCI_MAPREG_ROM_VSTAT_INPROG: 4221 str = "Validation in Progress"; 4222 break; 4223 case PCI_MAPREG_ROM_VSTAT_VPASS: 4224 str = "Validation Pass. " 4225 "Valid contents, trust test was not performed"; 4226 break; 4227 case PCI_MAPREG_ROM_VSTAT_VPASSTRUST: 4228 str = "Validation Pass. Valid and trusted contents"; 4229 break; 4230 case PCI_MAPREG_ROM_VSTAT_VFAIL: 4231 str = "Validation Fail. Invalid contents"; 4232 break; 4233 case PCI_MAPREG_ROM_VSTAT_VFAILUNTRUST: 4234 str = "Validation Fail. Valid but untrusted contents"; 4235 break; 4236 case PCI_MAPREG_ROM_VSTAT_WPASS: 4237 str = "Warning Pass. Validation passed with warning. " 4238 "Valid contents, trust test was not performed"; 4239 break; 4240 case PCI_MAPREG_ROM_VSTAT_WPASSTRUST: 4241 str = "Warning Pass. Validation passed with warning. " 4242 "Valid and trusted contents"; 4243 break; 4244 } 4245 printf("%s\n", str); 4246 printf(" Validation Details: 0x%x\n", 4247 (uint32_t)__SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_DETAIL)); 4248 4249 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4250 printf(" Capability list pointer: 0x%02x\n", 4251 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4252 else 4253 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4254 4255 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 4256 4257 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4258 printf(" Maximum Latency: 0x%02x\n", PCI_MAX_LAT(rval)); 4259 printf(" Minimum Grant: 0x%02x\n", PCI_MIN_GNT(rval)); 4260 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 4261 switch (PCI_INTERRUPT_PIN(rval)) { 4262 case PCI_INTERRUPT_PIN_NONE: 4263 printf("(none)"); 4264 break; 4265 case PCI_INTERRUPT_PIN_A: 4266 printf("(pin A)"); 4267 break; 4268 case PCI_INTERRUPT_PIN_B: 4269 printf("(pin B)"); 4270 break; 4271 case PCI_INTERRUPT_PIN_C: 4272 printf("(pin C)"); 4273 break; 4274 case PCI_INTERRUPT_PIN_D: 4275 printf("(pin D)"); 4276 break; 4277 default: 4278 printf("(? ? ?)"); 4279 break; 4280 } 4281 printf("\n"); 4282 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 4283 } 4284 4285 static void 4286 pci_conf_print_type1( 4287 #ifdef _KERNEL 4288 pci_chipset_tag_t pc, pcitag_t tag, 4289 #endif 4290 const pcireg_t *regs) 4291 { 4292 int off, width; 4293 pcireg_t rval, csreg; 4294 uint32_t base, limit; 4295 uint32_t base_h, limit_h; 4296 uint64_t pbase, plimit; 4297 int use_upper; 4298 4299 /* 4300 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 4301 * Bridge chip documentation, and may not be correct with 4302 * respect to various standards. (XXX) 4303 */ 4304 4305 for (off = 0x10; off < 0x18; off += width) { 4306 #ifdef _KERNEL 4307 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4308 #else 4309 width = pci_conf_print_bar(regs, off, NULL); 4310 #endif 4311 } 4312 4313 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4314 printf(" Primary bus number: 0x%02x\n", 4315 PCI_BRIDGE_BUS_PRIMARY(rval)); 4316 printf(" Secondary bus number: 0x%02x\n", 4317 PCI_BRIDGE_BUS_SECONDARY(rval)); 4318 printf(" Subordinate bus number: 0x%02x\n", 4319 PCI_BRIDGE_BUS_SUBORDINATE(rval)); 4320 printf(" Secondary bus latency timer: 0x%02x\n", 4321 PCI_BRIDGE_BUS_SEC_LATTIMER(rval)); 4322 4323 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 4324 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 4325 4326 /* I/O region */ 4327 printf(" I/O region:\n"); 4328 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 4329 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 4330 if (PCI_BRIDGE_IO_32BITS(rval)) 4331 use_upper = 1; 4332 else 4333 use_upper = 0; 4334 onoff("32bit I/O", rval, use_upper); 4335 base = (rval & PCI_BRIDGE_STATIO_IOBASE_MASK) << 8; 4336 limit = ((rval >> PCI_BRIDGE_STATIO_IOLIMIT_SHIFT) 4337 & PCI_BRIDGE_STATIO_IOLIMIT_MASK) << 8; 4338 limit |= 0x00000fff; 4339 4340 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 4341 base_h = (rval >> 0) & 0xffff; 4342 limit_h = (rval >> 16) & 0xffff; 4343 printf(" base upper 16 bits register: 0x%04x\n", base_h); 4344 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 4345 4346 if (use_upper == 1) { 4347 base |= base_h << 16; 4348 limit |= limit_h << 16; 4349 } 4350 if (base < limit) { 4351 if (use_upper == 1) 4352 printf(" range: 0x%08x-0x%08x\n", base, limit); 4353 else 4354 printf(" range: 0x%04x-0x%04x\n", base, limit); 4355 } else 4356 printf(" range: not set\n"); 4357 4358 /* Non-prefetchable memory region */ 4359 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 4360 printf(" Memory region:\n"); 4361 printf(" base register: 0x%04x\n", 4362 (rval >> 0) & 0xffff); 4363 printf(" limit register: 0x%04x\n", 4364 (rval >> 16) & 0xffff); 4365 base = ((rval >> PCI_BRIDGE_MEMORY_BASE_SHIFT) 4366 & PCI_BRIDGE_MEMORY_BASE_MASK) << 20; 4367 limit = (((rval >> PCI_BRIDGE_MEMORY_LIMIT_SHIFT) 4368 & PCI_BRIDGE_MEMORY_LIMIT_MASK) << 20) | 0x000fffff; 4369 if (base < limit) 4370 printf(" range: 0x%08x-0x%08x\n", base, limit); 4371 else 4372 printf(" range: not set\n"); 4373 4374 /* Prefetchable memory region */ 4375 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 4376 printf(" Prefetchable memory region:\n"); 4377 printf(" base register: 0x%04x\n", 4378 (rval >> 0) & 0xffff); 4379 printf(" limit register: 0x%04x\n", 4380 (rval >> 16) & 0xffff); 4381 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]; 4382 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]; 4383 printf(" base upper 32 bits register: 0x%08x\n", 4384 base_h); 4385 printf(" limit upper 32 bits register: 0x%08x\n", 4386 limit_h); 4387 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 4388 use_upper = 1; 4389 else 4390 use_upper = 0; 4391 onoff("64bit memory address", rval, use_upper); 4392 pbase = ((rval >> PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT) 4393 & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) << 20; 4394 plimit = (((rval >> PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT) 4395 & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) << 20) | 0x000fffff; 4396 if (use_upper == 1) { 4397 pbase |= (uint64_t)base_h << 32; 4398 plimit |= (uint64_t)limit_h << 32; 4399 } 4400 if (pbase < plimit) { 4401 if (use_upper == 1) 4402 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 4403 "\n", pbase, plimit); 4404 else 4405 printf(" range: 0x%08x-0x%08x\n", 4406 (uint32_t)pbase, (uint32_t)plimit); 4407 } else 4408 printf(" range: not set\n"); 4409 4410 csreg = regs[o2i(PCI_COMMAND_STATUS_REG)]; 4411 if (csreg & PCI_STATUS_CAPLIST_SUPPORT) 4412 printf(" Capability list pointer: 0x%02x\n", 4413 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4414 else 4415 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4416 4417 /* XXX */ 4418 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 4419 4420 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4421 printf(" Interrupt line: 0x%02x\n", 4422 (rval >> 0) & 0xff); 4423 printf(" Interrupt pin: 0x%02x ", 4424 (rval >> 8) & 0xff); 4425 switch ((rval >> 8) & 0xff) { 4426 case PCI_INTERRUPT_PIN_NONE: 4427 printf("(none)"); 4428 break; 4429 case PCI_INTERRUPT_PIN_A: 4430 printf("(pin A)"); 4431 break; 4432 case PCI_INTERRUPT_PIN_B: 4433 printf("(pin B)"); 4434 break; 4435 case PCI_INTERRUPT_PIN_C: 4436 printf("(pin C)"); 4437 break; 4438 case PCI_INTERRUPT_PIN_D: 4439 printf("(pin D)"); 4440 break; 4441 default: 4442 printf("(? ? ?)"); 4443 break; 4444 } 4445 printf("\n"); 4446 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 4447 & PCI_BRIDGE_CONTROL_MASK; 4448 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 4449 onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE); 4450 onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR); 4451 onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA); 4452 onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA); 4453 /* 4454 * VGA 16bit decode bit has meaning if the VGA enable bit or the 4455 * VGA Palette Snoop Enable bit is set. 4456 */ 4457 if (((rval & PCI_BRIDGE_CONTROL_VGA) != 0) 4458 || ((csreg & PCI_COMMAND_PALETTE_ENABLE) != 0)) 4459 onoff("VGA 16bit enable", rval, PCI_BRIDGE_CONTROL_VGA16); 4460 onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT); 4461 onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR); 4462 onoff("Fast back-to-back capable", rval,PCI_BRIDGE_CONTROL_SECFASTB2B); 4463 } 4464 4465 static void 4466 pci_conf_print_type2( 4467 #ifdef _KERNEL 4468 pci_chipset_tag_t pc, pcitag_t tag, 4469 #endif 4470 const pcireg_t *regs) 4471 { 4472 pcireg_t rval; 4473 4474 /* 4475 * XXX these need to be printed in more detail, need to be 4476 * XXX checked against specs/docs, etc. 4477 * 4478 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 4479 * controller chip documentation, and may not be correct with 4480 * respect to various standards. (XXX) 4481 */ 4482 4483 #ifdef _KERNEL 4484 pci_conf_print_bar(pc, tag, regs, 0x10, 4485 "CardBus socket/ExCA registers"); 4486 #else 4487 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 4488 #endif 4489 4490 /* Capability list pointer and secondary status register */ 4491 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 4492 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4493 printf(" Capability list pointer: 0x%02x\n", 4494 PCI_CAPLIST_PTR(rval)); 4495 else 4496 printf(" Reserved @ 0x14: 0x%04x\n", 4497 (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0))); 4498 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 4499 4500 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4501 printf(" PCI bus number: 0x%02x\n", 4502 (rval >> 0) & 0xff); 4503 printf(" CardBus bus number: 0x%02x\n", 4504 (rval >> 8) & 0xff); 4505 printf(" Subordinate bus number: 0x%02x\n", 4506 (rval >> 16) & 0xff); 4507 printf(" CardBus latency timer: 0x%02x\n", 4508 (rval >> 24) & 0xff); 4509 4510 /* XXX Print more prettily */ 4511 printf(" CardBus memory region 0:\n"); 4512 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 4513 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 4514 printf(" CardBus memory region 1:\n"); 4515 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 4516 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 4517 printf(" CardBus I/O region 0:\n"); 4518 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 4519 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 4520 printf(" CardBus I/O region 1:\n"); 4521 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 4522 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 4523 4524 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4525 printf(" Interrupt line: 0x%02x\n", 4526 (rval >> 0) & 0xff); 4527 printf(" Interrupt pin: 0x%02x ", 4528 (rval >> 8) & 0xff); 4529 switch ((rval >> 8) & 0xff) { 4530 case PCI_INTERRUPT_PIN_NONE: 4531 printf("(none)"); 4532 break; 4533 case PCI_INTERRUPT_PIN_A: 4534 printf("(pin A)"); 4535 break; 4536 case PCI_INTERRUPT_PIN_B: 4537 printf("(pin B)"); 4538 break; 4539 case PCI_INTERRUPT_PIN_C: 4540 printf("(pin C)"); 4541 break; 4542 case PCI_INTERRUPT_PIN_D: 4543 printf("(pin D)"); 4544 break; 4545 default: 4546 printf("(? ? ?)"); 4547 break; 4548 } 4549 printf("\n"); 4550 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> 16) & 0xffff; 4551 printf(" Bridge control register: 0x%04x\n", rval); 4552 onoff("Parity error response", rval, __BIT(0)); 4553 onoff("SERR# enable", rval, __BIT(1)); 4554 onoff("ISA enable", rval, __BIT(2)); 4555 onoff("VGA enable", rval, __BIT(3)); 4556 onoff("Master abort mode", rval, __BIT(5)); 4557 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 4558 onoff("Functional interrupts routed by ExCA registers", rval, 4559 __BIT(7)); 4560 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 4561 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 4562 onoff("Write posting enable", rval, __BIT(10)); 4563 4564 rval = regs[o2i(0x40)]; 4565 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4566 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4567 4568 #ifdef _KERNEL 4569 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers"); 4570 #else 4571 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 4572 #endif 4573 } 4574 4575 void 4576 pci_conf_print( 4577 #ifdef _KERNEL 4578 pci_chipset_tag_t pc, pcitag_t tag, 4579 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 4580 #else 4581 int pcifd, u_int bus, u_int dev, u_int func 4582 #endif 4583 ) 4584 { 4585 pcireg_t regs[o2i(PCI_EXTCONF_SIZE)]; 4586 int off, capoff, endoff, hdrtype; 4587 const char *type_name; 4588 #ifdef _KERNEL 4589 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 4590 #else 4591 void (*type_printfn)(const pcireg_t *); 4592 #endif 4593 4594 printf("PCI configuration registers:\n"); 4595 4596 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 4597 #ifdef _KERNEL 4598 regs[o2i(off)] = pci_conf_read(pc, tag, off); 4599 #else 4600 if (pcibus_conf_read(pcifd, bus, dev, func, off, 4601 ®s[o2i(off)]) == -1) 4602 regs[o2i(off)] = 0; 4603 #endif 4604 } 4605 4606 /* common header */ 4607 printf(" Common header:\n"); 4608 pci_conf_print_regs(regs, 0, 16); 4609 4610 printf("\n"); 4611 #ifdef _KERNEL 4612 pci_conf_print_common(pc, tag, regs); 4613 #else 4614 pci_conf_print_common(regs); 4615 #endif 4616 printf("\n"); 4617 4618 /* type-dependent header */ 4619 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 4620 switch (hdrtype) { /* XXX make a table, eventually */ 4621 case 0: 4622 /* Standard device header */ 4623 type_name = "\"normal\" device"; 4624 type_printfn = &pci_conf_print_type0; 4625 capoff = PCI_CAPLISTPTR_REG; 4626 endoff = 64; 4627 break; 4628 case 1: 4629 /* PCI-PCI bridge header */ 4630 type_name = "PCI-PCI bridge"; 4631 type_printfn = &pci_conf_print_type1; 4632 capoff = PCI_CAPLISTPTR_REG; 4633 endoff = 64; 4634 break; 4635 case 2: 4636 /* PCI-CardBus bridge header */ 4637 type_name = "PCI-CardBus bridge"; 4638 type_printfn = &pci_conf_print_type2; 4639 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 4640 endoff = 72; 4641 break; 4642 default: 4643 type_name = NULL; 4644 type_printfn = 0; 4645 capoff = -1; 4646 endoff = 64; 4647 break; 4648 } 4649 printf(" Type %d ", hdrtype); 4650 if (type_name != NULL) 4651 printf("(%s) ", type_name); 4652 printf("header:\n"); 4653 pci_conf_print_regs(regs, 16, endoff); 4654 printf("\n"); 4655 if (type_printfn) { 4656 #ifdef _KERNEL 4657 (*type_printfn)(pc, tag, regs); 4658 #else 4659 (*type_printfn)(regs); 4660 #endif 4661 } else 4662 printf(" Don't know how to pretty-print type %d header.\n", 4663 hdrtype); 4664 printf("\n"); 4665 4666 /* capability list, if present */ 4667 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4668 && (capoff > 0)) { 4669 #ifdef _KERNEL 4670 pci_conf_print_caplist(pc, tag, regs, capoff); 4671 #else 4672 pci_conf_print_caplist(regs, capoff); 4673 #endif 4674 printf("\n"); 4675 } 4676 4677 /* device-dependent header */ 4678 printf(" Device-dependent header:\n"); 4679 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 4680 printf("\n"); 4681 #ifdef _KERNEL 4682 if (printfn) 4683 (*printfn)(pc, tag, regs); 4684 else 4685 printf(" Don't know how to pretty-print device-dependent header.\n"); 4686 printf("\n"); 4687 #endif /* _KERNEL */ 4688 4689 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 4690 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 4691 return; 4692 4693 #ifdef _KERNEL 4694 pci_conf_print_extcaplist(pc, tag, regs, capoff); 4695 #else 4696 pci_conf_print_extcaplist(regs, capoff); 4697 #endif 4698 printf("\n"); 4699 4700 /* Extended Configuration Space, if present */ 4701 printf(" Extended Configuration Space:\n"); 4702 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 4703 } 4704
Indexes created Wed Sep 24 05:09:52 GMT 2025