pci_subr.c revision 1.201.2.2
1 /* $NetBSD: pci_subr.c,v 1.201.2.2 2020/04/13 08:04:27 martin Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.201.2.2 2020/04/13 08:04:27 martin Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdarg.h> 58 #include <stdbool.h> 59 #include <stdio.h> 60 #include <stdlib.h> 61 #include <string.h> 62 #endif 63 64 #include <dev/pci/pcireg.h> 65 #ifdef _KERNEL 66 #include <dev/pci/pcivar.h> 67 #else 68 #include <dev/pci/pci_verbose.h> 69 #include <dev/pci/pcidevs.h> 70 #include <dev/pci/pcidevs_data.h> 71 #endif 72 73 static int pci_conf_find_cap(const pcireg_t *, unsigned int, int *); 74 static int pci_conf_find_extcap(const pcireg_t *, unsigned int, int *); 75 static void pci_conf_print_pcie_power(uint8_t, unsigned int); 76 #define PCIREG_SHIFTOUT(a, b) ((pcireg_t)__SHIFTOUT((a), (b))) 77 78 /* 79 * Descriptions of known PCI classes and subclasses. 80 * 81 * Subclasses are described in the same way as classes, but have a 82 * NULL subclass pointer. 83 */ 84 struct pci_class { 85 const char *name; 86 u_int val; /* as wide as pci_{,sub}class_t */ 87 const struct pci_class *subclasses; 88 }; 89 90 /* 91 * Class 0x00. 92 * Before rev. 2.0. 93 */ 94 static const struct pci_class pci_subclass_prehistoric[] = { 95 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 96 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 97 { NULL, 0, NULL, }, 98 }; 99 100 /* 101 * Class 0x01. 102 * Mass storage controller 103 */ 104 105 /* ATA programming interface */ 106 static const struct pci_class pci_interface_ata[] = { 107 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 108 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 109 { NULL, 0, NULL, }, 110 }; 111 112 /* SATA programming interface */ 113 static const struct pci_class pci_interface_sata[] = { 114 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 115 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 116 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 117 { NULL, 0, NULL, }, 118 }; 119 120 /* Flash programming interface */ 121 static const struct pci_class pci_interface_nvm[] = { 122 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 123 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 124 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 125 { NULL, 0, NULL, }, 126 }; 127 128 /* Subclasses */ 129 static const struct pci_class pci_subclass_mass_storage[] = { 130 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 131 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 132 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 133 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 134 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 135 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 136 pci_interface_ata, }, 137 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 138 pci_interface_sata, }, 139 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 140 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 141 pci_interface_nvm, }, 142 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 143 { NULL, 0, NULL, }, 144 }; 145 146 /* 147 * Class 0x02. 148 * Network controller. 149 */ 150 static const struct pci_class pci_subclass_network[] = { 151 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 152 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 153 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 154 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 155 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 156 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 157 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 158 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 159 { NULL, 0, NULL, }, 160 }; 161 162 /* 163 * Class 0x03. 164 * Display controller. 165 */ 166 167 /* VGA programming interface */ 168 static const struct pci_class pci_interface_vga[] = { 169 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 170 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 171 { NULL, 0, NULL, }, 172 }; 173 /* Subclasses */ 174 static const struct pci_class pci_subclass_display[] = { 175 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 176 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 177 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 178 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 179 { NULL, 0, NULL, }, 180 }; 181 182 /* 183 * Class 0x04. 184 * Multimedia device. 185 */ 186 static const struct pci_class pci_subclass_multimedia[] = { 187 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 188 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 189 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 190 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 191 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 192 { NULL, 0, NULL, }, 193 }; 194 195 /* 196 * Class 0x05. 197 * Memory controller. 198 */ 199 static const struct pci_class pci_subclass_memory[] = { 200 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 201 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 202 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 203 { NULL, 0, NULL, }, 204 }; 205 206 /* 207 * Class 0x06. 208 * Bridge device. 209 */ 210 211 /* PCI bridge programming interface */ 212 static const struct pci_class pci_interface_pcibridge[] = { 213 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 214 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 215 { NULL, 0, NULL, }, 216 }; 217 218 /* Semi-transparent PCI-to-PCI bridge programming interface */ 219 static const struct pci_class pci_interface_stpci[] = { 220 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 221 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 222 { NULL, 0, NULL, }, 223 }; 224 225 /* Advanced Switching programming interface */ 226 static const struct pci_class pci_interface_advsw[] = { 227 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 228 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 229 { NULL, 0, NULL, }, 230 }; 231 232 /* Subclasses */ 233 static const struct pci_class pci_subclass_bridge[] = { 234 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 235 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 236 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 237 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 238 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 239 pci_interface_pcibridge, }, 240 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 241 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 242 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 243 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 244 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 245 pci_interface_stpci, }, 246 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 247 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 248 pci_interface_advsw, }, 249 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 250 { NULL, 0, NULL, }, 251 }; 252 253 /* 254 * Class 0x07. 255 * Simple communications controller. 256 */ 257 258 /* Serial controller programming interface */ 259 static const struct pci_class pci_interface_serial[] = { 260 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 261 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 262 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 263 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 264 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 265 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 266 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 267 { NULL, 0, NULL, }, 268 }; 269 270 /* Parallel controller programming interface */ 271 static const struct pci_class pci_interface_parallel[] = { 272 { "", PCI_INTERFACE_PARALLEL, NULL,}, 273 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 274 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 275 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 276 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 277 { NULL, 0, NULL,}, 278 }; 279 280 /* Modem programming interface */ 281 static const struct pci_class pci_interface_modem[] = { 282 { "", PCI_INTERFACE_MODEM, NULL,}, 283 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 284 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 285 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 286 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 287 { NULL, 0, NULL,}, 288 }; 289 290 /* Subclasses */ 291 static const struct pci_class pci_subclass_communications[] = { 292 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 293 pci_interface_serial, }, 294 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 295 pci_interface_parallel, }, 296 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 297 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 298 pci_interface_modem, }, 299 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 300 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 301 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 302 { NULL, 0, NULL,}, 303 }; 304 305 /* 306 * Class 0x08. 307 * Base system peripheral. 308 */ 309 310 /* PIC programming interface */ 311 static const struct pci_class pci_interface_pic[] = { 312 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 313 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 314 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 315 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 316 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 317 { NULL, 0, NULL, }, 318 }; 319 320 /* DMA programming interface */ 321 static const struct pci_class pci_interface_dma[] = { 322 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 323 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 324 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 325 { NULL, 0, NULL, }, 326 }; 327 328 /* Timer programming interface */ 329 static const struct pci_class pci_interface_tmr[] = { 330 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 331 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 332 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 333 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 334 { NULL, 0, NULL, }, 335 }; 336 337 /* RTC programming interface */ 338 static const struct pci_class pci_interface_rtc[] = { 339 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 340 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 341 { NULL, 0, NULL, }, 342 }; 343 344 /* Subclasses */ 345 static const struct pci_class pci_subclass_system[] = { 346 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 347 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 348 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 349 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 350 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 351 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 352 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 353 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 354 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 355 { NULL, 0, NULL, }, 356 }; 357 358 /* 359 * Class 0x09. 360 * Input device. 361 */ 362 363 /* Gameport programming interface */ 364 static const struct pci_class pci_interface_game[] = { 365 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 366 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 367 { NULL, 0, NULL, }, 368 }; 369 370 /* Subclasses */ 371 static const struct pci_class pci_subclass_input[] = { 372 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 373 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 374 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 375 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 376 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 377 pci_interface_game, }, 378 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 379 { NULL, 0, NULL, }, 380 }; 381 382 /* 383 * Class 0x0a. 384 * Docking station. 385 */ 386 static const struct pci_class pci_subclass_dock[] = { 387 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 388 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 389 { NULL, 0, NULL, }, 390 }; 391 392 /* 393 * Class 0x0b. 394 * Processor. 395 */ 396 static const struct pci_class pci_subclass_processor[] = { 397 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 398 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 399 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 400 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 401 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 402 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 403 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 404 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 405 { NULL, 0, NULL, }, 406 }; 407 408 /* 409 * Class 0x0c. 410 * Serial bus controller. 411 */ 412 413 /* IEEE1394 programming interface */ 414 static const struct pci_class pci_interface_ieee1394[] = { 415 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 416 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 417 { NULL, 0, NULL,}, 418 }; 419 420 /* USB programming interface */ 421 static const struct pci_class pci_interface_usb[] = { 422 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 423 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 424 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 425 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 426 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 427 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 428 { NULL, 0, NULL, }, 429 }; 430 431 /* IPMI programming interface */ 432 static const struct pci_class pci_interface_ipmi[] = { 433 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL, }, 434 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL, }, 435 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL, }, 436 { NULL, 0, NULL, }, 437 }; 438 439 /* Subclasses */ 440 static const struct pci_class pci_subclass_serialbus[] = { 441 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 442 pci_interface_ieee1394, }, 443 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 444 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 445 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 446 pci_interface_usb, }, 447 /* XXX Fiber Channel/_FIBRECHANNEL */ 448 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 449 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 450 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 451 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 452 pci_interface_ipmi, }, 453 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 454 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 455 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 456 { NULL, 0, NULL, }, 457 }; 458 459 /* 460 * Class 0x0d. 461 * Wireless Controller. 462 */ 463 static const struct pci_class pci_subclass_wireless[] = { 464 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 465 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 466 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 467 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 468 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 469 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 470 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 471 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 472 { NULL, 0, NULL, }, 473 }; 474 475 /* 476 * Class 0x0e. 477 * Intelligent IO controller. 478 */ 479 480 /* Intelligent IO programming interface */ 481 static const struct pci_class pci_interface_i2o[] = { 482 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL, }, 483 { NULL, 0, NULL, }, 484 }; 485 486 /* Subclasses */ 487 static const struct pci_class pci_subclass_i2o[] = { 488 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 489 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 490 { NULL, 0, NULL, }, 491 }; 492 493 /* 494 * Class 0x0f. 495 * Satellite communication controller. 496 */ 497 static const struct pci_class pci_subclass_satcom[] = { 498 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 499 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 500 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 501 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 502 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 503 { NULL, 0, NULL, }, 504 }; 505 506 /* 507 * Class 0x10. 508 * Encryption/Decryption controller. 509 */ 510 static const struct pci_class pci_subclass_crypto[] = { 511 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 512 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 513 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 514 { NULL, 0, NULL, }, 515 }; 516 517 /* 518 * Class 0x11. 519 * Data aquuisition and signal processing controller. 520 */ 521 static const struct pci_class pci_subclass_dasp[] = { 522 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 523 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 524 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 525 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 526 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 527 { NULL, 0, NULL, }, 528 }; 529 530 /* List of classes */ 531 static const struct pci_class pci_classes[] = { 532 { "prehistoric", PCI_CLASS_PREHISTORIC, 533 pci_subclass_prehistoric, }, 534 { "mass storage", PCI_CLASS_MASS_STORAGE, 535 pci_subclass_mass_storage, }, 536 { "network", PCI_CLASS_NETWORK, 537 pci_subclass_network, }, 538 { "display", PCI_CLASS_DISPLAY, 539 pci_subclass_display, }, 540 { "multimedia", PCI_CLASS_MULTIMEDIA, 541 pci_subclass_multimedia, }, 542 { "memory", PCI_CLASS_MEMORY, 543 pci_subclass_memory, }, 544 { "bridge", PCI_CLASS_BRIDGE, 545 pci_subclass_bridge, }, 546 { "communications", PCI_CLASS_COMMUNICATIONS, 547 pci_subclass_communications, }, 548 { "system", PCI_CLASS_SYSTEM, 549 pci_subclass_system, }, 550 { "input", PCI_CLASS_INPUT, 551 pci_subclass_input, }, 552 { "dock", PCI_CLASS_DOCK, 553 pci_subclass_dock, }, 554 { "processor", PCI_CLASS_PROCESSOR, 555 pci_subclass_processor, }, 556 { "serial bus", PCI_CLASS_SERIALBUS, 557 pci_subclass_serialbus, }, 558 { "wireless", PCI_CLASS_WIRELESS, 559 pci_subclass_wireless, }, 560 { "I2O", PCI_CLASS_I2O, 561 pci_subclass_i2o, }, 562 { "satellite comm", PCI_CLASS_SATCOM, 563 pci_subclass_satcom, }, 564 { "crypto", PCI_CLASS_CRYPTO, 565 pci_subclass_crypto, }, 566 { "DASP", PCI_CLASS_DASP, 567 pci_subclass_dasp, }, 568 { "processing accelerators", PCI_CLASS_ACCEL, 569 NULL, }, 570 { "non-essential instrumentation", PCI_CLASS_INSTRUMENT, 571 NULL, }, 572 { "undefined", PCI_CLASS_UNDEFINED, 573 NULL, }, 574 { NULL, 0, 575 NULL, }, 576 }; 577 578 DEV_VERBOSE_DEFINE(pci); 579 580 /* 581 * Append a formatted string to dest without writing more than len 582 * characters (including the trailing NUL character). dest and len 583 * are updated for use in subsequent calls to snappendf(). 584 * 585 * Returns 0 on success, a negative value if vnsprintf() fails, or 586 * a positive value if the dest buffer would have overflowed. 587 */ 588 589 static int __printflike(3, 4) 590 snappendf(char **dest, size_t *len, const char * restrict fmt, ...) 591 { 592 va_list ap; 593 int count; 594 595 va_start(ap, fmt); 596 count = vsnprintf(*dest, *len, fmt, ap); 597 va_end(ap); 598 599 /* Let vsnprintf() errors bubble up to caller */ 600 if (count < 0 || *len == 0) 601 return count; 602 603 /* Handle overflow */ 604 if ((size_t)count >= *len) { 605 *dest += *len - 1; 606 *len = 1; 607 return 1; 608 } 609 610 /* Update dest & len to point at trailing NUL */ 611 *dest += count; 612 *len -= count; 613 614 return 0; 615 } 616 617 void 618 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 619 size_t l) 620 { 621 pci_class_t class; 622 pci_subclass_t subclass; 623 pci_interface_t interface; 624 pci_revision_t revision; 625 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 626 const struct pci_class *classp, *subclassp, *interfacep; 627 628 class = PCI_CLASS(class_reg); 629 subclass = PCI_SUBCLASS(class_reg); 630 interface = PCI_INTERFACE(class_reg); 631 revision = PCI_REVISION(class_reg); 632 633 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 634 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 635 PCI_PRODUCT(id_reg)); 636 637 classp = pci_classes; 638 while (classp->name != NULL) { 639 if (class == classp->val) 640 break; 641 classp++; 642 } 643 644 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 645 while (subclassp && subclassp->name != NULL) { 646 if (subclass == subclassp->val) 647 break; 648 subclassp++; 649 } 650 651 interfacep = (subclassp && subclassp->name != NULL) ? 652 subclassp->subclasses : NULL; 653 while (interfacep && interfacep->name != NULL) { 654 if (interface == interfacep->val) 655 break; 656 interfacep++; 657 } 658 659 (void)snappendf(&cp, &l, "%s %s", vendor, product); 660 if (showclass) { 661 (void)snappendf(&cp, &l, " ("); 662 if (classp->name == NULL) 663 (void)snappendf(&cp, &l, 664 "class 0x%02x, subclass 0x%02x", 665 class, subclass); 666 else { 667 if (subclassp == NULL || subclassp->name == NULL) 668 (void)snappendf(&cp, &l, 669 "%s, subclass 0x%02x", 670 classp->name, subclass); 671 else 672 (void)snappendf(&cp, &l, "%s %s", 673 subclassp->name, classp->name); 674 } 675 if ((interfacep == NULL) || (interfacep->name == NULL)) { 676 if (interface != 0) 677 (void)snappendf(&cp, &l, ", interface 0x%02x", 678 interface); 679 } else if (strncmp(interfacep->name, "", 1) != 0) 680 (void)snappendf(&cp, &l, ", %s", interfacep->name); 681 if (revision != 0) 682 (void)snappendf(&cp, &l, ", revision 0x%02x", revision); 683 (void)snappendf(&cp, &l, ")"); 684 } 685 } 686 687 #ifdef _KERNEL 688 void 689 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 690 const char *known, int addrev) 691 { 692 char devinfo[256]; 693 694 if (known) { 695 aprint_normal(": %s", known); 696 if (addrev) 697 aprint_normal(" (rev. 0x%02x)", 698 PCI_REVISION(pa->pa_class)); 699 aprint_normal("\n"); 700 } else { 701 pci_devinfo(pa->pa_id, pa->pa_class, 0, 702 devinfo, sizeof(devinfo)); 703 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 704 PCI_REVISION(pa->pa_class)); 705 } 706 if (naive) 707 aprint_naive(": %s\n", naive); 708 else 709 aprint_naive("\n"); 710 } 711 #endif 712 713 /* 714 * Print out most of the PCI configuration registers. Typically used 715 * in a device attach routine like this: 716 * 717 * #ifdef MYDEV_DEBUG 718 * printf("%s: ", device_xname(sc->sc_dev)); 719 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 720 * #endif 721 */ 722 723 #define i2o(i) ((i) * 4) 724 #define o2i(o) ((o) / 4) 725 #define onoff2(str, rval, bit, onstr, offstr) \ 726 /*CONSTCOND*/ \ 727 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 728 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 729 730 static void 731 pci_conf_print_common( 732 #ifdef _KERNEL 733 pci_chipset_tag_t pc, pcitag_t tag, 734 #endif 735 const pcireg_t *regs) 736 { 737 pci_class_t class; 738 pci_subclass_t subclass; 739 pci_interface_t interface; 740 pci_revision_t revision; 741 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 742 const struct pci_class *classp, *subclassp, *interfacep; 743 const char *name; 744 pcireg_t rval; 745 unsigned int num; 746 747 rval = regs[o2i(PCI_CLASS_REG)]; 748 class = PCI_CLASS(rval); 749 subclass = PCI_SUBCLASS(rval); 750 interface = PCI_INTERFACE(rval); 751 revision = PCI_REVISION(rval); 752 753 rval = regs[o2i(PCI_ID_REG)]; 754 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 755 if (name) 756 printf(" Vendor Name: %s (0x%04x)\n", name, 757 PCI_VENDOR(rval)); 758 else 759 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 760 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 761 PCI_PRODUCT(rval)); 762 if (name) 763 printf(" Device Name: %s (0x%04x)\n", name, 764 PCI_PRODUCT(rval)); 765 else 766 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 767 768 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 769 770 printf(" Command register: 0x%04x\n", rval & 0xffff); 771 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 772 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 773 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 774 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 775 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 776 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 777 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 778 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 779 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 780 onoff("Fast back-to-back transactions", rval, 781 PCI_COMMAND_BACKTOBACK_ENABLE); 782 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 783 784 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 785 onoff("Immediate Readiness", rval, PCI_STATUS_IMMD_READNESS); 786 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 787 "inactive"); 788 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 789 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 790 onoff("User Definable Features (UDF) support", rval, 791 PCI_STATUS_UDF_SUPPORT); 792 onoff("Fast back-to-back capable", rval, 793 PCI_STATUS_BACKTOBACK_SUPPORT); 794 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 795 796 printf(" DEVSEL timing: "); 797 switch (rval & PCI_STATUS_DEVSEL_MASK) { 798 case PCI_STATUS_DEVSEL_FAST: 799 printf("fast"); 800 break; 801 case PCI_STATUS_DEVSEL_MEDIUM: 802 printf("medium"); 803 break; 804 case PCI_STATUS_DEVSEL_SLOW: 805 printf("slow"); 806 break; 807 default: 808 printf("unknown/reserved"); /* XXX */ 809 break; 810 } 811 printf(" (0x%x)\n", PCIREG_SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK)); 812 813 onoff("Slave signaled Target Abort", rval, 814 PCI_STATUS_TARGET_TARGET_ABORT); 815 onoff("Master received Target Abort", rval, 816 PCI_STATUS_MASTER_TARGET_ABORT); 817 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 818 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 819 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 820 821 rval = regs[o2i(PCI_CLASS_REG)]; 822 for (classp = pci_classes; classp->name != NULL; classp++) { 823 if (class == classp->val) 824 break; 825 } 826 827 /* 828 * ECN: Change Root Complex Event Collector Class Code 829 * Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type 830 * in PCIe extend capability to know whether it's RCEC or IOMMU. 831 */ 832 if ((class == PCI_CLASS_SYSTEM) 833 && (subclass == PCI_SUBCLASS_SYSTEM_IOMMU)) { 834 int pcie_capoff; 835 pcireg_t reg; 836 837 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 838 reg = regs[o2i(pcie_capoff + PCIE_XCAP)]; 839 if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_ROOT_EVNTC) 840 subclass = PCI_SUBCLASS_SYSTEM_RCEC; 841 } 842 } 843 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 844 while (subclassp && subclassp->name != NULL) { 845 if (subclass == subclassp->val) 846 break; 847 subclassp++; 848 } 849 850 interfacep = (subclassp && subclassp->name != NULL) ? 851 subclassp->subclasses : NULL; 852 while (interfacep && interfacep->name != NULL) { 853 if (interface == interfacep->val) 854 break; 855 interfacep++; 856 } 857 858 if (classp->name != NULL) 859 printf(" Class Name: %s (0x%02x)\n", classp->name, class); 860 else 861 printf(" Class ID: 0x%02x\n", class); 862 if (subclassp != NULL && subclassp->name != NULL) 863 printf(" Subclass Name: %s (0x%02x)\n", 864 subclassp->name, PCI_SUBCLASS(rval)); 865 else 866 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 867 if ((interfacep != NULL) && (interfacep->name != NULL) 868 && (strncmp(interfacep->name, "", 1) != 0)) 869 printf(" Interface Name: %s (0x%02x)\n", 870 interfacep->name, interface); 871 else 872 printf(" Interface: 0x%02x\n", interface); 873 printf(" Revision ID: 0x%02x\n", revision); 874 875 rval = regs[o2i(PCI_BHLC_REG)]; 876 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 877 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 878 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 879 PCI_HDRTYPE(rval)); 880 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 881 num = PCI_CACHELINE(rval); 882 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 883 } 884 885 static int 886 pci_conf_print_bar( 887 #ifdef _KERNEL 888 pci_chipset_tag_t pc, pcitag_t tag, 889 #endif 890 const pcireg_t *regs, int reg, const char *name) 891 { 892 int width; 893 pcireg_t rval, rval64h; 894 bool ioen, memen; 895 #ifdef _KERNEL 896 pcireg_t mask, mask64h = 0; 897 #endif 898 899 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 900 ioen = rval & PCI_COMMAND_IO_ENABLE; 901 memen = rval & PCI_COMMAND_MEM_ENABLE; 902 903 width = 4; 904 /* 905 * Section 6.2.5.1, `Address Maps', tells us that: 906 * 907 * 1) The builtin software should have already mapped the 908 * device in a reasonable way. 909 * 910 * 2) A device which wants 2^n bytes of memory will hardwire 911 * the bottom n bits of the address to 0. As recommended, 912 * we write all 1s and see what we get back. 913 */ 914 915 rval = regs[o2i(reg)]; 916 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 917 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 918 rval64h = regs[o2i(reg + 4)]; 919 width = 8; 920 } else 921 rval64h = 0; 922 923 #ifdef _KERNEL 924 if (rval != 0 && memen) { 925 int s; 926 927 /* 928 * The following sequence seems to make some devices 929 * (e.g. host bus bridges, which don't normally 930 * have their space mapped) very unhappy, to 931 * the point of crashing the system. 932 * 933 * Therefore, if the mapping register is zero to 934 * start out with, don't bother trying. 935 */ 936 s = splhigh(); 937 pci_conf_write(pc, tag, reg, 0xffffffff); 938 mask = pci_conf_read(pc, tag, reg); 939 pci_conf_write(pc, tag, reg, rval); 940 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 941 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 942 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 943 mask64h = pci_conf_read(pc, tag, reg + 4); 944 pci_conf_write(pc, tag, reg + 4, rval64h); 945 } 946 splx(s); 947 } else 948 mask = mask64h = 0; 949 #endif /* _KERNEL */ 950 951 printf(" Base address register at 0x%02x", reg); 952 if (name) 953 printf(" (%s)", name); 954 printf("\n "); 955 if (rval == 0) { 956 printf("not implemented\n"); 957 return width; 958 } 959 printf("type: "); 960 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 961 const char *type, *prefetch; 962 963 switch (PCI_MAPREG_MEM_TYPE(rval)) { 964 case PCI_MAPREG_MEM_TYPE_32BIT: 965 type = "32-bit"; 966 break; 967 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 968 type = "32-bit-1M"; 969 break; 970 case PCI_MAPREG_MEM_TYPE_64BIT: 971 type = "64-bit"; 972 break; 973 default: 974 type = "unknown (XXX)"; 975 break; 976 } 977 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 978 prefetch = ""; 979 else 980 prefetch = "non"; 981 printf("%s %sprefetchable memory\n", type, prefetch); 982 switch (PCI_MAPREG_MEM_TYPE(rval)) { 983 case PCI_MAPREG_MEM_TYPE_64BIT: 984 printf(" base: 0x%016llx", 985 PCI_MAPREG_MEM64_ADDR( 986 ((((long long) rval64h) << 32) | rval))); 987 if (!memen) 988 printf(", disabled"); 989 printf("\n"); 990 #ifdef _KERNEL 991 printf(" size: 0x%016llx\n", 992 PCI_MAPREG_MEM64_SIZE( 993 ((((long long) mask64h) << 32) | mask))); 994 #endif 995 break; 996 case PCI_MAPREG_MEM_TYPE_32BIT: 997 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 998 default: 999 printf(" base: 0x%08x", 1000 PCI_MAPREG_MEM_ADDR(rval)); 1001 if (!memen) 1002 printf(", disabled"); 1003 printf("\n"); 1004 #ifdef _KERNEL 1005 printf(" size: 0x%08x\n", 1006 PCI_MAPREG_MEM_SIZE(mask)); 1007 #endif 1008 break; 1009 } 1010 } else { 1011 #ifdef _KERNEL 1012 if (ioen) 1013 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 1014 #endif 1015 printf("I/O\n"); 1016 printf(" base: 0x%08x", PCI_MAPREG_IO_ADDR(rval)); 1017 if (!ioen) 1018 printf(", disabled"); 1019 printf("\n"); 1020 #ifdef _KERNEL 1021 printf(" size: 0x%08x\n", PCI_MAPREG_IO_SIZE(mask)); 1022 #endif 1023 } 1024 1025 return width; 1026 } 1027 1028 static void 1029 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 1030 { 1031 int off, needaddr, neednl; 1032 1033 needaddr = 1; 1034 neednl = 0; 1035 for (off = first; off < pastlast; off += 4) { 1036 if ((off % 16) == 0 || needaddr) { 1037 printf(" 0x%02x:", off); 1038 needaddr = 0; 1039 } 1040 printf(" 0x%08x", regs[o2i(off)]); 1041 neednl = 1; 1042 if ((off % 16) == 12) { 1043 printf("\n"); 1044 neednl = 0; 1045 } 1046 } 1047 if (neednl) 1048 printf("\n"); 1049 } 1050 1051 static const char * 1052 pci_conf_print_agp_calcycle(uint8_t cal) 1053 { 1054 1055 switch (cal) { 1056 case 0x0: 1057 return "4ms"; 1058 case 0x1: 1059 return "16ms"; 1060 case 0x2: 1061 return "64ms"; 1062 case 0x3: 1063 return "256ms"; 1064 case 0x7: 1065 return "Calibration Cycle Not Needed"; 1066 default: 1067 return "(reserved)"; 1068 } 1069 } 1070 1071 static void 1072 pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3) 1073 { 1074 if (isagp3) { 1075 /* AGP 3.0 */ 1076 if (reg & AGP_MODE_V3_RATE_4x) 1077 printf("x4"); 1078 if (reg & AGP_MODE_V3_RATE_8x) 1079 printf("x8"); 1080 } else { 1081 /* AGP 2.0 */ 1082 if (reg & AGP_MODE_V2_RATE_1x) 1083 printf("x1"); 1084 if (reg & AGP_MODE_V2_RATE_2x) 1085 printf("x2"); 1086 if (reg & AGP_MODE_V2_RATE_4x) 1087 printf("x4"); 1088 } 1089 printf("\n"); 1090 } 1091 1092 static void 1093 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1094 { 1095 pcireg_t rval; 1096 bool isagp3; 1097 1098 printf("\n AGP Capabilities Register\n"); 1099 1100 rval = regs[o2i(capoff)]; 1101 printf(" Revision: %d.%d\n", 1102 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1103 1104 rval = regs[o2i(capoff + PCI_AGP_STATUS)]; 1105 printf(" Status register: 0x%04x\n", rval); 1106 printf(" RQ: %u\n", 1107 PCIREG_SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1108 printf(" ARQSZ: %u\n", 1109 PCIREG_SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1110 printf(" CAL cycle: %s\n", 1111 pci_conf_print_agp_calcycle(PCIREG_SHIFTOUT(rval, AGP_MODE_CAL))); 1112 onoff("SBA", rval, AGP_MODE_SBA); 1113 onoff("htrans#", rval, AGP_MODE_HTRANS); 1114 onoff("Over 4G", rval, AGP_MODE_4G); 1115 onoff("Fast Write", rval, AGP_MODE_FW); 1116 onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3); 1117 isagp3 = rval & AGP_MODE_MODE_3; 1118 printf(" Data Rate Support: "); 1119 pci_conf_print_agp_datarate(rval, isagp3); 1120 1121 rval = regs[o2i(capoff + PCI_AGP_COMMAND)]; 1122 printf(" Command register: 0x%08x\n", rval); 1123 printf(" PRQ: %u\n", 1124 PCIREG_SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1125 printf(" PARQSZ: %u\n", 1126 PCIREG_SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1127 printf(" PCAL cycle: %s\n", 1128 pci_conf_print_agp_calcycle(PCIREG_SHIFTOUT(rval, AGP_MODE_CAL))); 1129 onoff("SBA", rval, AGP_MODE_SBA); 1130 onoff("AGP", rval, AGP_MODE_AGP); 1131 onoff("Over 4G", rval, AGP_MODE_4G); 1132 onoff("Fast Write", rval, AGP_MODE_FW); 1133 if (isagp3) { 1134 printf(" Data Rate Enable: "); 1135 /* 1136 * The Data Rate Enable bits are used only on 3.0 and the 1137 * Command register has no AGP_MODE_MODE_3 bit, so pass the 1138 * flag to print correctly. 1139 */ 1140 pci_conf_print_agp_datarate(rval, isagp3); 1141 } 1142 } 1143 1144 static const char * 1145 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1146 { 1147 1148 switch ((caps >> 6) & 7) { 1149 case 0: return "self-powered"; 1150 case 1: return "55 mA"; 1151 case 2: return "100 mA"; 1152 case 3: return "160 mA"; 1153 case 4: return "220 mA"; 1154 case 5: return "270 mA"; 1155 case 6: return "320 mA"; 1156 case 7: 1157 default: return "375 mA"; 1158 } 1159 } 1160 1161 static const char * 1162 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1163 { 1164 static const char unk[] = "unknown"; 1165 static const char *pmrev[8] = { 1166 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1167 }; 1168 if (val > 7) 1169 return unk; 1170 return pmrev[val]; 1171 } 1172 1173 static void 1174 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1175 { 1176 uint16_t caps, pmcsr; 1177 1178 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1179 pmcsr = regs[o2i(capoff + PCI_PMCSR)]; 1180 1181 printf("\n PCI Power Management Capabilities Register\n"); 1182 1183 printf(" Capabilities register: 0x%04x\n", caps); 1184 printf(" Version: %s\n", 1185 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1186 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1187 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1188 printf(" 3.3V auxiliary current: %s\n", 1189 pci_conf_print_pcipm_cap_aux(caps)); 1190 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1191 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1192 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1193 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1194 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1195 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1196 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1197 1198 printf(" Control/status register: 0x%08x\n", pmcsr); 1199 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1200 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1201 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1202 printf(" PME# assertion: %sabled\n", 1203 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1204 printf(" Data Select: %d\n", 1205 PCIREG_SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK)); 1206 printf(" Data Scale: %d\n", 1207 PCIREG_SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK)); 1208 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1209 printf(" Bridge Support Extensions register: 0x%02x\n", 1210 (pmcsr >> 16) & 0xff); 1211 onoff("B2/B3 support", pmcsr, PCI_PMCSR_B2B3_SUPPORT); 1212 onoff("Bus Power/Clock Control Enable", pmcsr, PCI_PMCSR_BPCC_EN); 1213 printf(" Data register: 0x%02x\n", 1214 PCIREG_SHIFTOUT(pmcsr, PCI_PMCSR_DATA)); 1215 } 1216 1217 /* XXX pci_conf_print_vpd_cap */ 1218 /* XXX pci_conf_print_slotid_cap */ 1219 1220 static void 1221 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1222 { 1223 uint32_t ctl, mmc, mme; 1224 1225 regs += o2i(capoff); 1226 ctl = *regs++; 1227 mmc = PCIREG_SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1228 mme = PCIREG_SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1229 1230 printf("\n PCI Message Signaled Interrupt\n"); 1231 1232 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1233 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1234 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1235 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1236 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1237 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1238 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1239 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1240 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP); 1241 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN); 1242 printf(" Message Address %sregister: 0x%08x\n", 1243 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1244 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1245 printf(" Message Address %sregister: 0x%08x\n", 1246 "(upper) ", *regs++); 1247 } 1248 printf(" Message Data register: "); 1249 if (ctl & PCI_MSI_CTL_EXTMDATA_CAP) 1250 printf("0x%08x\n", *regs); 1251 else 1252 printf("0x%04x\n", *regs & 0xffff); 1253 regs++; 1254 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1255 printf(" Vector Mask register: 0x%08x\n", *regs++); 1256 printf(" Vector Pending register: 0x%08x\n", *regs++); 1257 } 1258 } 1259 1260 /* XXX pci_conf_print_cpci_hostwap_cap */ 1261 1262 /* 1263 * For both command register and status register. 1264 * The argument "idx" is index number (0 to 7). 1265 */ 1266 static int 1267 pcix_split_trans(unsigned int idx) 1268 { 1269 static int table[8] = { 1270 1, 2, 3, 4, 8, 12, 16, 32 1271 }; 1272 1273 if (idx >= __arraycount(table)) 1274 return -1; 1275 return table[idx]; 1276 } 1277 1278 static void 1279 pci_conf_print_pcix_cap_2ndbusmode(int num) 1280 { 1281 const char *maxfreq, *maxperiod; 1282 1283 printf(" Mode: "); 1284 if (num <= 0x07) 1285 printf("PCI-X Mode 1\n"); 1286 else if (num <= 0x0b) 1287 printf("PCI-X 266 (Mode 2)\n"); 1288 else 1289 printf("PCI-X 533 (Mode 2)\n"); 1290 1291 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1292 switch (num & 0x03) { 1293 default: 1294 case 0: 1295 maxfreq = "N/A"; 1296 maxperiod = "N/A"; 1297 break; 1298 case 1: 1299 maxfreq = "66MHz"; 1300 maxperiod = "15ns"; 1301 break; 1302 case 2: 1303 maxfreq = "100MHz"; 1304 maxperiod = "10ns"; 1305 break; 1306 case 3: 1307 maxfreq = "133MHz"; 1308 maxperiod = "7.5ns"; 1309 break; 1310 } 1311 printf(" Max Clock Freq: %s\n", maxfreq); 1312 printf(" Min Clock Period: %s\n", maxperiod); 1313 } 1314 1315 static void 1316 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1317 { 1318 pcireg_t reg; 1319 int isbridge; 1320 int i; 1321 1322 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1323 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1324 printf("\n PCI-X %s Capabilities Register\n", 1325 isbridge ? "Bridge" : "Non-bridge"); 1326 1327 reg = regs[o2i(capoff)]; 1328 if (isbridge != 0) { 1329 printf(" Secondary status register: 0x%04x\n", 1330 (reg & 0xffff0000) >> 16); 1331 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1332 onoff("133MHz capable", reg, PCIX_STATUS_133); 1333 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1334 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1335 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1336 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1337 pci_conf_print_pcix_cap_2ndbusmode( 1338 PCIREG_SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1339 printf(" Version: 0x%x\n", 1340 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1341 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1342 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1343 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1344 } else { 1345 printf(" Command register: 0x%04x\n", 1346 (reg & 0xffff0000) >> 16); 1347 onoff("Data Parity Error Recovery", reg, 1348 PCIX_CMD_PERR_RECOVER); 1349 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1350 printf(" Maximum Burst Read Count: %u\n", 1351 PCIX_CMD_BYTECNT(reg)); 1352 printf(" Maximum Split Transactions: %d\n", 1353 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1354 >> PCIX_CMD_SPLTRANS_SHIFT)); 1355 } 1356 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1357 printf(" %sStatus register: 0x%08x\n", 1358 isbridge ? "Bridge " : "", reg); 1359 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1360 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1361 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1362 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1363 onoff("133MHz capable", reg, PCIX_STATUS_133); 1364 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1365 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1366 if (isbridge != 0) { 1367 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1368 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1369 } else { 1370 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1371 "bridge device", "simple device"); 1372 printf(" Designed max memory read byte count: %d\n", 1373 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1374 >> PCIX_STATUS_MAXB_SHIFT)); 1375 printf(" Designed max outstanding split transaction: %d\n", 1376 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1377 >> PCIX_STATUS_MAXST_SHIFT)); 1378 printf(" MAX cumulative Read Size: %u\n", 1379 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1380 onoff("Received split completion error", reg, 1381 PCIX_STATUS_SCERR); 1382 } 1383 onoff("266MHz capable", reg, PCIX_STATUS_266); 1384 onoff("533MHz capable", reg, PCIX_STATUS_533); 1385 1386 if (isbridge == 0) 1387 return; 1388 1389 /* Only for bridge */ 1390 for (i = 0; i < 2; i++) { 1391 reg = regs[o2i(capoff + PCIX_BRIDGE_UP_STCR + (4 * i))]; 1392 printf(" %s split transaction control register: 0x%08x\n", 1393 (i == 0) ? "Upstream" : "Downstream", reg); 1394 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1395 printf(" Commitment Limit: %d\n", 1396 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1397 } 1398 } 1399 1400 /* pci_conf_print_ht_slave_cap */ 1401 /* pci_conf_print_ht_host_cap */ 1402 /* pci_conf_print_ht_switch_cap */ 1403 /* pci_conf_print_ht_intr_cap */ 1404 /* pci_conf_print_ht_revid_cap */ 1405 /* pci_conf_print_ht_unitid_cap */ 1406 /* pci_conf_print_ht_extcnf_cap */ 1407 /* pci_conf_print_ht_addrmap_cap */ 1408 /* pci_conf_print_ht_msimap_cap */ 1409 1410 static void 1411 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1412 { 1413 pcireg_t val; 1414 uint32_t lo, hi; 1415 1416 /* 1417 * Print the rest of the command register bits. Others are 1418 * printed in pci_conf_print_ht_cap(). 1419 */ 1420 val = regs[o2i(capoff + PCI_HT_CMD)]; 1421 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1422 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1423 1424 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1425 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1426 printf(" Address Low register: 0x%08x\n", lo); 1427 printf(" Address high register: 0x%08x\n", hi); 1428 printf(" Address: 0x%016" PRIx64 "\n", 1429 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1430 } 1431 1432 /* pci_conf_print_ht_droute_cap */ 1433 /* pci_conf_print_ht_vcset_cap */ 1434 /* pci_conf_print_ht_retry_cap */ 1435 /* pci_conf_print_ht_x86enc_cap */ 1436 /* pci_conf_print_ht_gen3_cap */ 1437 /* pci_conf_print_ht_fle_cap */ 1438 /* pci_conf_print_ht_pm_cap */ 1439 /* pci_conf_print_ht_hnc_cap */ 1440 1441 static const struct ht_types { 1442 pcireg_t cap; 1443 const char *name; 1444 void (*printfunc)(const pcireg_t *, int); 1445 } ht_captab[] = { 1446 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1447 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1448 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1449 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1450 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1451 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1452 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1453 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1454 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1455 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1456 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1457 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1458 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1459 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1460 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1461 {PCI_HT_CAP_PM, "Power Management", NULL }, 1462 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1463 }; 1464 1465 static void 1466 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1467 { 1468 pcireg_t val, foundcap; 1469 unsigned int off; 1470 1471 val = regs[o2i(capoff + PCI_HT_CMD)]; 1472 1473 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1474 1475 printf(" Command register: 0x%04x\n", val >> 16); 1476 foundcap = PCI_HT_CAP(val); 1477 for (off = 0; off < __arraycount(ht_captab); off++) { 1478 if (ht_captab[off].cap == foundcap) 1479 break; 1480 } 1481 printf(" Capability Type: 0x%02x ", foundcap); 1482 if (off >= __arraycount(ht_captab)) { 1483 printf("(unknown)\n"); 1484 return; 1485 } 1486 printf("(%s)\n", ht_captab[off].name); 1487 if (ht_captab[off].printfunc != NULL) 1488 ht_captab[off].printfunc(regs, capoff); 1489 } 1490 1491 static void 1492 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1493 { 1494 uint16_t caps; 1495 1496 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1497 1498 printf("\n PCI Vendor Specific Capabilities Register\n"); 1499 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1500 } 1501 1502 static void 1503 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1504 { 1505 pcireg_t val; 1506 1507 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1508 1509 printf("\n Debugport Capability Register\n"); 1510 printf(" Debug base Register: 0x%04x\n", 1511 val >> PCI_DEBUG_BASER_SHIFT); 1512 printf(" port offset: 0x%04x\n", 1513 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1514 printf(" BAR number: %u\n", 1515 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1516 } 1517 1518 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1519 /* XXX pci_conf_print_hotplug_cap */ 1520 1521 static void 1522 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1523 { 1524 pcireg_t reg; 1525 1526 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1527 1528 printf("\n Subsystem ID Capability Register\n"); 1529 printf(" Subsystem ID: 0x%08x\n", reg); 1530 } 1531 1532 /* XXX pci_conf_print_agp8_cap */ 1533 static void 1534 pci_conf_print_secure_cap(const pcireg_t *regs, int capoff) 1535 { 1536 pcireg_t reg, reg2, val; 1537 bool havemisc1; 1538 1539 printf("\n Secure Capability Register\n"); 1540 reg = regs[o2i(capoff + PCI_SECURE_CAP)]; 1541 printf(" Capability Register: 0x%04x\n", reg >> 16); 1542 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_CAP_TYPE); 1543 printf(" Capability block type: "); 1544 /* I know IOMMU Only */ 1545 if (val == PCI_SECURE_CAP_TYPE_IOMMU) 1546 printf("IOMMU\n"); 1547 else { 1548 printf("0x%x(unknown)\n", val); 1549 return; 1550 } 1551 1552 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_CAP_REV); 1553 printf(" Capability revision: 0x%02x ", val); 1554 if (val == PCI_SECURE_CAP_REV_IOMMU) 1555 printf("(IOMMU)\n"); 1556 else { 1557 printf("(unknown)\n"); 1558 return; 1559 } 1560 onoff("IOTLB support", reg, PCI_SECURE_CAP_IOTLBSUP); 1561 onoff("HyperTransport tunnel translation support", reg, 1562 PCI_SECURE_CAP_HTTUNNEL); 1563 onoff("Not present table entries cached", reg, PCI_SECURE_CAP_NPCACHE); 1564 onoff("IOMMU Extended Feature Register support", reg, 1565 PCI_SECURE_CAP_EFRSUP); 1566 onoff("IOMMU Miscellaneous Information Register 1", reg, 1567 PCI_SECURE_CAP_EXT); 1568 havemisc1 = reg & PCI_SECURE_CAP_EXT; 1569 1570 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_BAL)]; 1571 printf(" Base Address Low Register: 0x%08x\n", reg); 1572 onoff("Enable", reg, PCI_SECURE_IOMMU_BAL_EN); 1573 reg2 = regs[o2i(capoff + PCI_SECURE_IOMMU_BAH)]; 1574 printf(" Base Address High Register: 0x%08x\n", reg2); 1575 printf(" Base Address: 0x%016" PRIx64 "\n", 1576 ((uint64_t)reg2 << 32) 1577 | (reg & (PCI_SECURE_IOMMU_BAL_H | PCI_SECURE_IOMMU_BAL_L))); 1578 1579 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_RANGE)]; 1580 printf(" IOMMU Range Register: 0x%08x\n", reg); 1581 printf(" HyperTransport UnitID: 0x%02x\n", 1582 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_UNITID)); 1583 onoff("Range valid", reg, PCI_SECURE_IOMMU_RANGE_RNGVALID); 1584 printf(" Device range bus number: 0x%02x\n", 1585 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_BUSNUM)); 1586 printf(" First device: 0x%04x\n", 1587 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_FIRSTDEV)); 1588 printf(" Last device: 0x%04x\n", 1589 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_LASTDEV)); 1590 1591 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC0)]; 1592 printf(" Miscellaneous Information Register 0: 0x%08x\n", reg); 1593 printf(" MSI Message number: 0x%02x\n", 1594 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MSINUM)); 1595 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_GVASIZE); 1596 printf(" Guest Virtual Address size: "); 1597 if (val == PCI_SECURE_IOMMU_MISC0_GVASIZE_48B) 1598 printf("48bits\n"); 1599 else 1600 printf("0x%x(unknown)\n", val); 1601 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_PASIZE); 1602 printf(" Physical Address size: %dbits\n", val); 1603 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_VASIZE); 1604 printf(" Virtual Address size: %dbits\n", val); 1605 onoff("ATS response address range reserved", reg, 1606 PCI_SECURE_IOMMU_MISC0_ATSRESV); 1607 printf(" Peripheral Page Request MSI Message number: 0x%02x\n", 1608 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MISNPPR)); 1609 1610 if (!havemisc1) 1611 return; 1612 1613 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC1)]; 1614 printf(" Miscellaneous Information Register 1: 0x%08x\n", reg); 1615 printf(" MSI Message number (GA): 0x%02x\n", 1616 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC1_MSINUM)); 1617 } 1618 1619 static void 1620 pci_print_pcie_L0s_latency(uint32_t val) 1621 { 1622 1623 switch (val) { 1624 case 0x0: 1625 printf("Less than 64ns\n"); 1626 break; 1627 case 0x1: 1628 case 0x2: 1629 case 0x3: 1630 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1631 break; 1632 case 0x4: 1633 printf("512ns to less than 1us\n"); 1634 break; 1635 case 0x5: 1636 printf("1us to less than 2us\n"); 1637 break; 1638 case 0x6: 1639 printf("2us - 4us\n"); 1640 break; 1641 case 0x7: 1642 printf("More than 4us\n"); 1643 break; 1644 } 1645 } 1646 1647 static void 1648 pci_print_pcie_L1_latency(uint32_t val) 1649 { 1650 1651 switch (val) { 1652 case 0x0: 1653 printf("Less than 1us\n"); 1654 break; 1655 case 0x6: 1656 printf("32us - 64us\n"); 1657 break; 1658 case 0x7: 1659 printf("More than 64us\n"); 1660 break; 1661 default: 1662 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1663 break; 1664 } 1665 } 1666 1667 static void 1668 pci_print_pcie_compl_timeout(uint32_t val) 1669 { 1670 1671 switch (val) { 1672 case 0x0: 1673 printf("50us to 50ms\n"); 1674 break; 1675 case 0x5: 1676 printf("16ms to 55ms\n"); 1677 break; 1678 case 0x6: 1679 printf("65ms to 210ms\n"); 1680 break; 1681 case 0x9: 1682 printf("260ms to 900ms\n"); 1683 break; 1684 case 0xa: 1685 printf("1s to 3.5s\n"); 1686 break; 1687 default: 1688 printf("unknown %u value\n", val); 1689 break; 1690 } 1691 } 1692 1693 static const char * const pcie_linkspeeds[] = {"2.5", "5.0", "8.0", "16.0"}; 1694 1695 /* 1696 * Print link speed. This function is used for the following register bits: 1697 * Maximum Link Speed in LCAP 1698 * Current Link Speed in LCSR 1699 * Target Link Speed in LCSR2 1700 * All of above bitfield's values start from 1. 1701 * For LCSR2, 0 is allowed for a device which supports 2.5GT/s only (and 1702 * this check also works for devices which compliant to versions of the base 1703 * specification prior to 3.0. 1704 */ 1705 static void 1706 pci_print_pcie_linkspeed(int regnum, pcireg_t val) 1707 { 1708 1709 if ((regnum == PCIE_LCSR2) && (val == 0)) 1710 printf("2.5GT/s\n"); 1711 else if ((val < 1) || (val > __arraycount(pcie_linkspeeds))) 1712 printf("unknown value (%u)\n", val); 1713 else 1714 printf("%sGT/s\n", pcie_linkspeeds[val - 1]); 1715 } 1716 1717 /* 1718 * Print link speed "vector". 1719 * This function is used for the following register bits: 1720 * Supported Link Speeds Vector in LCAP2 1721 * Lower SKP OS Generation Supported Speed Vector in LCAP2 1722 * Lower SKP OS Reception Supported Speed Vector in LCAP2 1723 * Enable Lower SKP OS Generation Vector in LCTL3 1724 * All of above bitfield's values start from 0. 1725 */ 1726 static void 1727 pci_print_pcie_linkspeedvector(pcireg_t val) 1728 { 1729 unsigned int i; 1730 1731 /* Start from 0 */ 1732 for (i = 0; i < 16; i++) 1733 if (((val >> i) & 0x01) != 0) { 1734 if (i >= __arraycount(pcie_linkspeeds)) 1735 printf(" unknown vector (0x%x)", 1 << i); 1736 else 1737 printf(" %sGT/s", pcie_linkspeeds[i]); 1738 } 1739 } 1740 1741 static void 1742 pci_print_pcie_link_deemphasis(pcireg_t val) 1743 { 1744 switch (val) { 1745 case 0: 1746 printf("-6dB"); 1747 break; 1748 case 1: 1749 printf("-3.5dB"); 1750 break; 1751 default: 1752 printf("(reserved value)"); 1753 } 1754 } 1755 1756 static void 1757 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1758 { 1759 pcireg_t reg; /* for each register */ 1760 pcireg_t val; /* for each bitfield */ 1761 bool check_slot = false; 1762 unsigned int pcie_devtype; 1763 bool check_upstreamport = false; 1764 unsigned int pciever; 1765 unsigned int i; 1766 1767 printf("\n PCI Express Capabilities Register\n"); 1768 /* Capability Register */ 1769 reg = regs[o2i(capoff)]; 1770 printf(" Capability register: 0x%04x\n", reg >> 16); 1771 pciever = (unsigned int)(PCIE_XCAP_VER(reg)); 1772 printf(" Capability version: %u\n", pciever); 1773 printf(" Device type: "); 1774 pcie_devtype = PCIE_XCAP_TYPE(reg); 1775 switch (pcie_devtype) { 1776 case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */ 1777 printf("PCI Express Endpoint device\n"); 1778 check_upstreamport = true; 1779 break; 1780 case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */ 1781 printf("Legacy PCI Express Endpoint device\n"); 1782 check_upstreamport = true; 1783 break; 1784 case PCIE_XCAP_TYPE_ROOT: /* 0x4 */ 1785 printf("Root Port of PCI Express Root Complex\n"); 1786 check_slot = true; 1787 break; 1788 case PCIE_XCAP_TYPE_UP: /* 0x5 */ 1789 printf("Upstream Port of PCI Express Switch\n"); 1790 check_upstreamport = true; 1791 break; 1792 case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ 1793 printf("Downstream Port of PCI Express Switch\n"); 1794 check_slot = true; 1795 break; 1796 case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ 1797 printf("PCI Express to PCI/PCI-X Bridge\n"); 1798 check_upstreamport = true; 1799 break; 1800 case PCIE_XCAP_TYPE_PCI2PCIE: /* 0x8 */ 1801 printf("PCI/PCI-X to PCI Express Bridge\n"); 1802 /* Upstream port is not PCIe */ 1803 check_slot = true; 1804 break; 1805 case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */ 1806 printf("Root Complex Integrated Endpoint\n"); 1807 break; 1808 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */ 1809 printf("Root Complex Event Collector\n"); 1810 break; 1811 default: 1812 printf("unknown\n"); 1813 break; 1814 } 1815 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1816 printf(" Interrupt Message Number: 0x%02x\n", 1817 PCIREG_SHIFTOUT(reg, PCIE_XCAP_IRQ)); 1818 1819 /* Device Capability Register */ 1820 reg = regs[o2i(capoff + PCIE_DCAP)]; 1821 printf(" Device Capabilities Register: 0x%08x\n", reg); 1822 printf(" Max Payload Size Supported: %u bytes max\n", 1823 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1824 printf(" Phantom Functions Supported: "); 1825 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) { 1826 case 0x0: 1827 printf("not available\n"); 1828 break; 1829 case 0x1: 1830 printf("MSB\n"); 1831 break; 1832 case 0x2: 1833 printf("two MSB\n"); 1834 break; 1835 case 0x3: 1836 printf("All three bits\n"); 1837 break; 1838 } 1839 printf(" Extended Tag Field Supported: %dbit\n", 1840 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1841 printf(" Endpoint L0 Acceptable Latency: "); 1842 pci_print_pcie_L0s_latency(PCIREG_SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY)); 1843 printf(" Endpoint L1 Acceptable Latency: "); 1844 pci_print_pcie_L1_latency(PCIREG_SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY)); 1845 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1846 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1847 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1848 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1849 if (check_upstreamport) { 1850 printf(" Captured Slot Power Limit: "); 1851 pci_conf_print_pcie_power( 1852 PCIREG_SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL), 1853 PCIREG_SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE)); 1854 } 1855 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1856 1857 /* Device Control Register */ 1858 reg = regs[o2i(capoff + PCIE_DCSR)]; 1859 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1860 onoff("Correctable Error Reporting Enable", reg, 1861 PCIE_DCSR_ENA_COR_ERR); 1862 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1863 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1864 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1865 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1866 printf(" Max Payload Size: %d byte\n", 1867 128 << PCIREG_SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD)); 1868 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1869 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1870 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1871 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1872 printf(" Max Read Request Size: %d byte\n", 1873 128 << PCIREG_SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ)); 1874 if (pcie_devtype == PCIE_XCAP_TYPE_PCIE2PCI) 1875 onoff("Bridge Config Retry Enable", reg, 1876 PCIE_DCSR_BRDG_CFG_RETRY); 1877 1878 /* Device Status Register */ 1879 reg = regs[o2i(capoff + PCIE_DCSR)]; 1880 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1881 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1882 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1883 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1884 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1885 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1886 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1887 onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD); 1888 1889 if (PCIE_HAS_LINKREGS(pcie_devtype)) { 1890 /* Link Capability Register */ 1891 reg = regs[o2i(capoff + PCIE_LCAP)]; 1892 printf(" Link Capabilities Register: 0x%08x\n", reg); 1893 printf(" Maximum Link Speed: "); 1894 pci_print_pcie_linkspeed(PCIE_LCAP, reg & PCIE_LCAP_MAX_SPEED); 1895 printf(" Maximum Link Width: x%u lanes\n", 1896 PCIREG_SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH)); 1897 printf(" Active State PM Support: "); 1898 switch (PCIREG_SHIFTOUT(reg, PCIE_LCAP_ASPM)) { 1899 case 0x0: 1900 printf("No ASPM support\n"); 1901 break; 1902 case 0x1: 1903 printf("L0s supported\n"); 1904 break; 1905 case 0x2: 1906 printf("L1 supported\n"); 1907 break; 1908 case 0x3: 1909 printf("L0s and L1 supported\n"); 1910 break; 1911 } 1912 printf(" L0 Exit Latency: "); 1913 pci_print_pcie_L0s_latency(PCIREG_SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT)); 1914 printf(" L1 Exit Latency: "); 1915 pci_print_pcie_L1_latency(PCIREG_SHIFTOUT(reg, PCIE_LCAP_L1_EXIT)); 1916 printf(" Port Number: %u\n", 1917 PCIREG_SHIFTOUT(reg, PCIE_LCAP_PORT)); 1918 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1919 onoff("Surprise Down Error Report", reg, 1920 PCIE_LCAP_SURPRISE_DOWN); 1921 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1922 onoff("Link BW Notification Capable", reg, 1923 PCIE_LCAP_LINK_BW_NOTIFY); 1924 onoff("ASPM Optionally Compliance", reg, 1925 PCIE_LCAP_ASPM_COMPLIANCE); 1926 1927 /* Link Control Register */ 1928 reg = regs[o2i(capoff + PCIE_LCSR)]; 1929 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1930 printf(" Active State PM Control: "); 1931 switch (reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S)) { 1932 case 0: 1933 printf("disabled\n"); 1934 break; 1935 case 1: 1936 printf("L0s Entry Enabled\n"); 1937 break; 1938 case 2: 1939 printf("L1 Entry Enabled\n"); 1940 break; 1941 case 3: 1942 printf("L0s and L1 Entry Enabled\n"); 1943 break; 1944 } 1945 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1946 "128bytes", "64bytes"); 1947 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1948 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1949 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1950 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1951 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1952 onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD); 1953 onoff("Link Bandwidth Management Interrupt Enable", reg, 1954 PCIE_LCSR_LBMIE); 1955 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1956 PCIE_LCSR_LABIE); 1957 printf(" DRS Signaling Control: "); 1958 switch (PCIREG_SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) { 1959 case 0: 1960 printf("not reported\n"); 1961 break; 1962 case 1: 1963 printf("Interrupt Enabled\n"); 1964 break; 1965 case 2: 1966 printf("DRS to FRS Signaling Enabled\n"); 1967 break; 1968 default: 1969 printf("reserved\n"); 1970 break; 1971 } 1972 1973 /* Link Status Register */ 1974 reg = regs[o2i(capoff + PCIE_LCSR)]; 1975 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1976 printf(" Negotiated Link Speed: "); 1977 pci_print_pcie_linkspeed(PCIE_LCSR, 1978 PCIREG_SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 1979 printf(" Negotiated Link Width: x%u lanes\n", 1980 PCIREG_SHIFTOUT(reg, PCIE_LCSR_NLW)); 1981 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1982 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1983 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1984 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1985 onoff("Link Bandwidth Management Status", reg, 1986 PCIE_LCSR_LINK_BW_MGMT); 1987 onoff("Link Autonomous Bandwidth Status", reg, 1988 PCIE_LCSR_LINK_AUTO_BW); 1989 } 1990 1991 if (check_slot == true) { 1992 pcireg_t slcap; 1993 1994 /* Slot Capability Register */ 1995 slcap = reg = regs[o2i(capoff + PCIE_SLCAP)]; 1996 printf(" Slot Capability Register: 0x%08x\n", reg); 1997 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 1998 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 1999 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 2000 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 2001 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 2002 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 2003 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 2004 printf(" Slot Power Limit Value: "); 2005 pci_conf_print_pcie_power(PCIREG_SHIFTOUT(reg, PCIE_SLCAP_SPLV), 2006 PCIREG_SHIFTOUT(reg, PCIE_SLCAP_SPLS)); 2007 onoff("Electromechanical Interlock Present", reg, 2008 PCIE_SLCAP_EIP); 2009 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 2010 printf(" Physical Slot Number: %d\n", 2011 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 2012 2013 /* Slot Control Register */ 2014 reg = regs[o2i(capoff + PCIE_SLCSR)]; 2015 printf(" Slot Control Register: 0x%04x\n", reg & 0xffff); 2016 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 2017 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 2018 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 2019 onoff("Presence Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 2020 onoff("Command Completed Interrupt Enabled", reg, 2021 PCIE_SLCSR_CCE); 2022 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 2023 /* 2024 * For Attention Indicator Control and Power Indicator Control, 2025 * it's allowed to be a read only value 0 if corresponding 2026 * capability register bit is 0. 2027 */ 2028 if (slcap & PCIE_SLCAP_AIP) { 2029 printf(" Attention Indicator Control: "); 2030 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 2031 case 0x0: 2032 printf("reserved\n"); 2033 break; 2034 case PCIE_SLCSR_IND_ON: 2035 printf("on\n"); 2036 break; 2037 case PCIE_SLCSR_IND_BLINK: 2038 printf("blink\n"); 2039 break; 2040 case PCIE_SLCSR_IND_OFF: 2041 printf("off\n"); 2042 break; 2043 } 2044 } 2045 if (slcap & PCIE_SLCAP_PIP) { 2046 printf(" Power Indicator Control: "); 2047 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 2048 case 0x0: 2049 printf("reserved\n"); 2050 break; 2051 case PCIE_SLCSR_IND_ON: 2052 printf("on\n"); 2053 break; 2054 case PCIE_SLCSR_IND_BLINK: 2055 printf("blink\n"); 2056 break; 2057 case PCIE_SLCSR_IND_OFF: 2058 printf("off\n"); 2059 break; 2060 } 2061 } 2062 printf(" Power Controller Control: Power %s\n", 2063 reg & PCIE_SLCSR_PCC ? "off" : "on"); 2064 onoff("Electromechanical Interlock Control", 2065 reg, PCIE_SLCSR_EIC); 2066 onoff("Data Link Layer State Changed Enable", reg, 2067 PCIE_SLCSR_DLLSCE); 2068 onoff("Auto Slot Power Limit Disable", reg, 2069 PCIE_SLCSR_AUTOSPLDIS); 2070 2071 /* Slot Status Register */ 2072 printf(" Slot Status Register: 0x%04x\n", reg >> 16); 2073 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 2074 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 2075 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 2076 onoff("Presence Detect Changed", reg, PCIE_SLCSR_PDC); 2077 onoff("Command Completed", reg, PCIE_SLCSR_CC); 2078 onoff("MRL Open", reg, PCIE_SLCSR_MS); 2079 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 2080 onoff("Electromechanical Interlock engaged", reg, 2081 PCIE_SLCSR_EIS); 2082 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 2083 } 2084 2085 if (PCIE_HAS_ROOTREGS(pcie_devtype)) { 2086 /* Root Control Register */ 2087 reg = regs[o2i(capoff + PCIE_RCR)]; 2088 printf(" Root Control Register: 0x%04x\n", reg & 0xffff); 2089 onoff("SERR on Correctable Error Enable", reg, 2090 PCIE_RCR_SERR_CER); 2091 onoff("SERR on Non-Fatal Error Enable", reg, 2092 PCIE_RCR_SERR_NFER); 2093 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 2094 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 2095 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 2096 2097 /* Root Capability Register */ 2098 printf(" Root Capability Register: 0x%04x\n", 2099 reg >> 16); 2100 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 2101 2102 /* Root Status Register */ 2103 reg = regs[o2i(capoff + PCIE_RSR)]; 2104 printf(" Root Status Register: 0x%08x\n", reg); 2105 printf(" PME Requester ID: 0x%04x\n", 2106 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 2107 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 2108 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 2109 } 2110 2111 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2112 if (pciever < 2) 2113 return; 2114 2115 /* Device Capabilities 2 */ 2116 reg = regs[o2i(capoff + PCIE_DCAP2)]; 2117 printf(" Device Capabilities 2: 0x%08x\n", reg); 2118 printf(" Completion Timeout Ranges Supported: "); 2119 val = reg & PCIE_DCAP2_COMPT_RANGE; 2120 switch (val) { 2121 case 0: 2122 printf("not supported\n"); 2123 break; 2124 default: 2125 for (i = 0; i <= 3; i++) { 2126 if (((val >> i) & 0x01) != 0) 2127 printf("%c", 'A' + i); 2128 } 2129 printf("\n"); 2130 } 2131 onoff("Completion Timeout Disable Supported", reg, 2132 PCIE_DCAP2_COMPT_DIS); 2133 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 2134 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 2135 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 2136 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 2137 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 2138 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 2139 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 2140 printf(" TPH Completer Supported: "); 2141 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) { 2142 case 0: 2143 printf("Not supported\n"); 2144 break; 2145 case 1: 2146 printf("TPH\n"); 2147 break; 2148 case 3: 2149 printf("TPH and Extended TPH\n"); 2150 break; 2151 default: 2152 printf("(reserved value)\n"); 2153 break; 2154 } 2155 printf(" LN System CLS: "); 2156 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 2157 case 0x0: 2158 printf("Not supported or not in effect\n"); 2159 break; 2160 case 0x1: 2161 printf("64byte cachelines in effect\n"); 2162 break; 2163 case 0x2: 2164 printf("128byte cachelines in effect\n"); 2165 break; 2166 case 0x3: 2167 printf("Reserved\n"); 2168 break; 2169 } 2170 onoff("10-bit Tag Completer Supported", reg, PCIE_DCAP2_TBT_COMP); 2171 onoff("10-bit Tag Requester Supported", reg, PCIE_DCAP2_TBT_REQ); 2172 printf(" OBFF Supported: "); 2173 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_OBFF)) { 2174 case 0x0: 2175 printf("Not supported\n"); 2176 break; 2177 case 0x1: 2178 printf("Message only\n"); 2179 break; 2180 case 0x2: 2181 printf("WAKE# only\n"); 2182 break; 2183 case 0x3: 2184 printf("Both\n"); 2185 break; 2186 } 2187 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 2188 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 2189 val = PCIREG_SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP); 2190 printf(" Max End-End TLP Prefixes: %u\n", (val == 0) ? 4 : val); 2191 printf(" Emergency Power Reduction Supported: "); 2192 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) { 2193 case 0x0: 2194 printf("Not supported\n"); 2195 break; 2196 case 0x1: 2197 printf("Device Specific mechanism\n"); 2198 break; 2199 case 0x2: 2200 printf("Form Factor spec or Device Specific mechanism\n"); 2201 break; 2202 case 0x3: 2203 printf("Reserved\n"); 2204 break; 2205 } 2206 onoff("Emergency Power Reduction Initialization Required", reg, 2207 PCIE_DCAP2_EMGPWRRED_INI); 2208 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 2209 2210 /* Device Control 2 */ 2211 reg = regs[o2i(capoff + PCIE_DCSR2)]; 2212 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 2213 printf(" Completion Timeout Value: "); 2214 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 2215 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 2216 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 2217 onoff("AtomicOp Requester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 2218 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 2219 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 2220 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 2221 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 2222 onoff("Emergency Power Reduction Request", reg, 2223 PCIE_DCSR2_EMGPWRRED_REQ); 2224 onoff("10-bit Tag Requester Enabled", reg, PCIE_DCSR2_TBT_REQ); 2225 printf(" OBFF: "); 2226 switch (PCIREG_SHIFTOUT(reg, PCIE_DCSR2_OBFF_EN)) { 2227 case 0x0: 2228 printf("Disabled\n"); 2229 break; 2230 case 0x1: 2231 printf("Enabled with Message Signaling Variation A\n"); 2232 break; 2233 case 0x2: 2234 printf("Enabled with Message Signaling Variation B\n"); 2235 break; 2236 case 0x3: 2237 printf("Enabled using WAKE# signaling\n"); 2238 break; 2239 } 2240 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 2241 2242 if (PCIE_HAS_LINKREGS(pcie_devtype)) { 2243 bool drs_supported = false; 2244 2245 /* Link Capability 2 */ 2246 reg = regs[o2i(capoff + PCIE_LCAP2)]; 2247 /* If the vector is 0, LCAP2 is not implemented */ 2248 if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) { 2249 printf(" Link Capabilities 2: 0x%08x\n", reg); 2250 printf(" Supported Link Speeds Vector:"); 2251 pci_print_pcie_linkspeedvector( 2252 PCIREG_SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 2253 printf("\n"); 2254 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 2255 printf(" " 2256 "Lower SKP OS Generation Supported Speed Vector:"); 2257 pci_print_pcie_linkspeedvector( 2258 PCIREG_SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 2259 printf("\n"); 2260 printf(" " 2261 "Lower SKP OS Reception Supported Speed Vector:"); 2262 pci_print_pcie_linkspeedvector( 2263 PCIREG_SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 2264 printf("\n"); 2265 onoff("Retimer Presence Detect Supported", reg, 2266 PCIE_LCAP2_RETIMERPD); 2267 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 2268 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 2269 } 2270 2271 /* Link Control 2 */ 2272 reg = regs[o2i(capoff + PCIE_LCSR2)]; 2273 /* If the vector is 0, LCAP2 is not implemented */ 2274 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 2275 printf(" Target Link Speed: "); 2276 pci_print_pcie_linkspeed(PCIE_LCSR2, 2277 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_TGT_LSPEED)); 2278 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 2279 onoff("HW Autonomous Speed Disabled", reg, 2280 PCIE_LCSR2_HW_AS_DIS); 2281 printf(" Selectable De-emphasis: "); 2282 pci_print_pcie_link_deemphasis( 2283 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP)); 2284 printf("\n"); 2285 printf(" Transmit Margin: %u\n", 2286 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_TX_MARGIN)); 2287 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 2288 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 2289 printf(" Compliance Present/De-emphasis: "); 2290 pci_print_pcie_link_deemphasis( 2291 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP)); 2292 printf("\n"); 2293 2294 /* Link Status 2 */ 2295 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 2296 printf(" Current De-emphasis Level: "); 2297 pci_print_pcie_link_deemphasis( 2298 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL)); 2299 printf("\n"); 2300 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 2301 onoff("Equalization Phase 1 Successful", reg, 2302 PCIE_LCSR2_EQP1_SUC); 2303 onoff("Equalization Phase 2 Successful", reg, 2304 PCIE_LCSR2_EQP2_SUC); 2305 onoff("Equalization Phase 3 Successful", reg, 2306 PCIE_LCSR2_EQP3_SUC); 2307 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 2308 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 2309 if (drs_supported) { 2310 printf(" Downstream Component Presence: "); 2311 switch (PCIREG_SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 2312 case PCIE_DSCOMPN_DOWN_NOTDETERM: 2313 printf("Link Down - Presence Not" 2314 " Determined\n"); 2315 break; 2316 case PCIE_DSCOMPN_DOWN_NOTPRES: 2317 printf("Link Down - Component Not Present\n"); 2318 break; 2319 case PCIE_DSCOMPN_DOWN_PRES: 2320 printf("Link Down - Component Present\n"); 2321 break; 2322 case PCIE_DSCOMPN_UP_PRES: 2323 printf("Link Up - Component Present\n"); 2324 break; 2325 case PCIE_DSCOMPN_UP_PRES_DRS: 2326 printf("Link Up - Component Present and DRS" 2327 " received\n"); 2328 break; 2329 default: 2330 printf("reserved\n"); 2331 break; 2332 } 2333 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 2334 } 2335 } 2336 2337 /* Slot Capability 2 */ 2338 /* Slot Control 2 */ 2339 /* Slot Status 2 */ 2340 } 2341 2342 static void 2343 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 2344 { 2345 pcireg_t reg; 2346 2347 printf("\n MSI-X Capability Register\n"); 2348 2349 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2350 printf(" Message Control register: 0x%04x\n", 2351 (reg >> 16) & 0xff); 2352 printf(" Table Size: %d\n", PCI_MSIX_CTL_TBLSIZE(reg)); 2353 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 2354 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 2355 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 2356 printf(" Table offset register: 0x%08x\n", reg); 2357 printf(" Table offset: 0x%08x\n", 2358 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 2359 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 2360 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 2361 printf(" Pending bit array register: 0x%08x\n", reg); 2362 printf(" Pending bit array offset: 0x%08x\n", 2363 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2364 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2365 } 2366 2367 static void 2368 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2369 { 2370 pcireg_t reg; 2371 2372 printf("\n Serial ATA Capability Register\n"); 2373 2374 reg = regs[o2i(capoff + PCI_SATA_REV)]; 2375 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2376 printf(" Revision: %u.%u\n", 2377 PCIREG_SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2378 PCIREG_SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2379 2380 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2381 2382 printf(" BAR Register: 0x%08x\n", reg); 2383 printf(" Register location: "); 2384 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2385 printf("in config space\n"); 2386 else { 2387 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2388 printf(" BAR offset: 0x%08x\n", 2389 PCIREG_SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2390 } 2391 } 2392 2393 static void 2394 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2395 { 2396 pcireg_t reg; 2397 2398 printf("\n Advanced Features Capability Register\n"); 2399 2400 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2401 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2402 printf(" AF Structure Length: 0x%02x\n", 2403 PCIREG_SHIFTOUT(reg, PCI_AF_LENGTH)); 2404 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2405 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2406 reg = regs[o2i(capoff + PCI_AFCSR)]; 2407 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2408 /* 2409 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2410 * and it's always 0 on read 2411 */ 2412 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2413 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2414 } 2415 2416 static void 2417 pci_conf_print_ea_cap_prop(unsigned int prop) 2418 { 2419 2420 switch (prop) { 2421 case PCI_EA_PROP_MEM_NONPREF: 2422 printf("Memory Space, Non-Prefetchable\n"); 2423 break; 2424 case PCI_EA_PROP_MEM_PREF: 2425 printf("Memory Space, Prefetchable\n"); 2426 break; 2427 case PCI_EA_PROP_IO: 2428 printf("I/O Space\n"); 2429 break; 2430 case PCI_EA_PROP_VF_MEM_NONPREF: 2431 printf("Resorce for VF use, Memory Space, Non-Prefetchable\n"); 2432 break; 2433 case PCI_EA_PROP_VF_MEM_PREF: 2434 printf("Resorce for VF use, Memory Space, Prefetch\n"); 2435 break; 2436 case PCI_EA_PROP_BB_MEM_NONPREF: 2437 printf("Behind the Bridge, Memory Space, Non-Pref\n"); 2438 break; 2439 case PCI_EA_PROP_BB_MEM_PREF: 2440 printf("Behind the Bridge, Memory Space. Prefetchable\n"); 2441 break; 2442 case PCI_EA_PROP_BB_IO: 2443 printf("Behind Bridge, I/O Space\n"); 2444 break; 2445 case PCI_EA_PROP_MEM_UNAVAIL: 2446 printf("Memory Space Unavailable\n"); 2447 break; 2448 case PCI_EA_PROP_IO_UNAVAIL: 2449 printf("IO Space Unavailable\n"); 2450 break; 2451 case PCI_EA_PROP_UNAVAIL: 2452 printf("Entry Unavailable for use\n"); 2453 break; 2454 default: 2455 printf("Reserved\n"); 2456 break; 2457 } 2458 } 2459 2460 static void 2461 pci_conf_print_ea_cap(const pcireg_t *regs, int capoff) 2462 { 2463 pcireg_t reg, reg2; 2464 unsigned int entries, entoff, i; 2465 2466 printf("\n Enhanced Allocation Capability Register\n"); 2467 2468 reg = regs[o2i(capoff + PCI_EA_CAP1)]; 2469 printf(" EA Num Entries register: 0x%04x\n", reg >> 16); 2470 entries = PCIREG_SHIFTOUT(reg, PCI_EA_CAP1_NUMENTRIES); 2471 printf(" EA Num Entries: %u\n", entries); 2472 2473 /* Type 1 only */ 2474 if (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) == PCI_HDRTYPE_PPB) { 2475 reg = regs[o2i(capoff + PCI_EA_CAP2)]; 2476 printf(" EA Capability Second register: 0x%08x\n", reg); 2477 printf(" Fixed Secondary Bus Number: %hhu\n", 2478 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_EA_CAP2_SECONDARY)); 2479 printf(" Fixed Subordinate Bus Number: %hhu\n", 2480 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_EA_CAP2_SUBORDINATE)); 2481 entoff = capoff + 8; 2482 } else 2483 entoff = capoff + 4; 2484 2485 for (i = 0; i < entries; i++) { 2486 uint64_t base, offset; 2487 bool baseis64, offsetis64; 2488 unsigned int bei, entry_size; 2489 2490 printf(" Entry %u:\n", i); 2491 /* The first DW */ 2492 reg = regs[o2i(entoff)]; 2493 printf(" The first register: 0x%08x\n", reg); 2494 entry_size = PCIREG_SHIFTOUT(reg, PCI_EA_ES); 2495 printf(" Entry size: %u\n", entry_size); 2496 printf(" BAR Equivalent Indicator: "); 2497 bei = PCIREG_SHIFTOUT(reg, PCI_EA_BEI); 2498 switch (bei) { 2499 case PCI_EA_BEI_BAR0: 2500 case PCI_EA_BEI_BAR1: 2501 case PCI_EA_BEI_BAR2: 2502 case PCI_EA_BEI_BAR3: 2503 case PCI_EA_BEI_BAR4: 2504 case PCI_EA_BEI_BAR5: 2505 printf("BAR %u\n", bei - PCI_EA_BEI_BAR0); 2506 break; 2507 case PCI_EA_BEI_BEHIND: 2508 printf("Behind the function\n"); 2509 break; 2510 case PCI_EA_BEI_NOTIND: 2511 printf("Not Indicated\n"); 2512 break; 2513 case PCI_EA_BEI_EXPROM: 2514 printf("Expansion ROM\n"); 2515 break; 2516 case PCI_EA_BEI_VFBAR0: 2517 case PCI_EA_BEI_VFBAR1: 2518 case PCI_EA_BEI_VFBAR2: 2519 case PCI_EA_BEI_VFBAR3: 2520 case PCI_EA_BEI_VFBAR4: 2521 case PCI_EA_BEI_VFBAR5: 2522 printf("VF BAR %u\n", bei - PCI_EA_BEI_VFBAR0); 2523 break; 2524 case PCI_EA_BEI_RESERVED: 2525 default: 2526 printf("Reserved\n"); 2527 break; 2528 } 2529 2530 printf(" Primary Properties: "); 2531 pci_conf_print_ea_cap_prop(PCIREG_SHIFTOUT(reg, PCI_EA_PP)); 2532 printf(" Secondary Properties: "); 2533 pci_conf_print_ea_cap_prop(PCIREG_SHIFTOUT(reg, PCI_EA_SP)); 2534 onoff("Writable", reg, PCI_EA_W); 2535 onoff("Enable for this entry", reg, PCI_EA_E); 2536 2537 if (entry_size == 0) { 2538 entoff += 4; 2539 continue; 2540 } 2541 2542 /* Base addr */ 2543 reg = regs[o2i(entoff + 4)]; 2544 base = reg & PCI_EA_LOWMASK; 2545 baseis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT; 2546 printf(" Base Address Register Low: 0x%08x\n", reg); 2547 if (baseis64) { 2548 /* 64bit */ 2549 reg2 = regs[o2i(entoff + 12)]; 2550 printf(" Base Address Register high: 0x%08x\n", 2551 reg2); 2552 base |= (uint64_t)reg2 << 32; 2553 } 2554 2555 /* Offset addr */ 2556 reg = regs[o2i(entoff + 8)]; 2557 offset = reg & PCI_EA_LOWMASK; 2558 offsetis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT; 2559 printf(" Max Offset Register Low: 0x%08x\n", reg); 2560 if (offsetis64) { 2561 /* 64bit */ 2562 reg2 = regs[o2i(entoff + (baseis64 ? 16 : 12))]; 2563 printf(" Max Offset Register high: 0x%08x\n", 2564 reg2); 2565 offset |= (uint64_t)reg2 << 32; 2566 } 2567 2568 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 2569 "\n", base, base + offset); 2570 2571 entoff += 4 + (4 * entry_size); 2572 } 2573 } 2574 2575 /* XXX pci_conf_print_fpb_cap */ 2576 2577 static struct { 2578 pcireg_t cap; 2579 const char *name; 2580 void (*printfunc)(const pcireg_t *, int); 2581 } pci_captab[] = { 2582 { PCI_CAP_RESERVED0, "reserved", NULL }, 2583 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2584 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2585 { PCI_CAP_VPD, "VPD", NULL }, 2586 { PCI_CAP_SLOTID, "SlotID", NULL }, 2587 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2588 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2589 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2590 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2591 { PCI_CAP_VENDSPEC, "Vendor-specific", 2592 pci_conf_print_vendspec_cap }, 2593 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2594 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2595 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2596 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2597 pci_conf_print_subsystem_cap }, 2598 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2599 { PCI_CAP_SECURE, "Secure Device", pci_conf_print_secure_cap }, 2600 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2601 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2602 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2603 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2604 { PCI_CAP_EA, "Enhanced Allocation", pci_conf_print_ea_cap }, 2605 { PCI_CAP_FPB, "Flattening Portal Bridge", NULL } 2606 }; 2607 2608 static int 2609 pci_conf_find_cap(const pcireg_t *regs, unsigned int capid, int *offsetp) 2610 { 2611 pcireg_t rval; 2612 unsigned int capptr; 2613 int off; 2614 2615 if (!(regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)) 2616 return 0; 2617 2618 /* Determine the Capability List Pointer register to start with. */ 2619 switch (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)])) { 2620 case 0: /* standard device header */ 2621 case 1: /* PCI-PCI bridge header */ 2622 capptr = PCI_CAPLISTPTR_REG; 2623 break; 2624 case 2: /* PCI-CardBus Bridge header */ 2625 capptr = PCI_CARDBUS_CAPLISTPTR_REG; 2626 break; 2627 default: 2628 return 0; 2629 } 2630 2631 for (off = PCI_CAPLIST_PTR(regs[o2i(capptr)]); 2632 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2633 rval = regs[o2i(off)]; 2634 if (capid == PCI_CAPLIST_CAP(rval)) { 2635 if (offsetp != NULL) 2636 *offsetp = off; 2637 return 1; 2638 } 2639 } 2640 return 0; 2641 } 2642 2643 static void 2644 pci_conf_print_caplist( 2645 #ifdef _KERNEL 2646 pci_chipset_tag_t pc, pcitag_t tag, 2647 #endif 2648 const pcireg_t *regs, int capoff) 2649 { 2650 int off; 2651 pcireg_t foundcap; 2652 pcireg_t rval; 2653 bool foundtable[__arraycount(pci_captab)]; 2654 unsigned int i; 2655 2656 /* Clear table */ 2657 for (i = 0; i < __arraycount(pci_captab); i++) 2658 foundtable[i] = false; 2659 2660 /* Print capability register's offset and the type first */ 2661 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2662 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2663 rval = regs[o2i(off)]; 2664 printf(" Capability register at 0x%02x\n", off); 2665 2666 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2667 foundcap = PCI_CAPLIST_CAP(rval); 2668 if (foundcap < __arraycount(pci_captab)) { 2669 printf("%s)\n", pci_captab[foundcap].name); 2670 /* Mark as found */ 2671 foundtable[foundcap] = true; 2672 } else 2673 printf("unknown)\n"); 2674 } 2675 2676 /* 2677 * And then, print the detail of each capability registers 2678 * in capability value's order. 2679 */ 2680 for (i = 0; i < __arraycount(pci_captab); i++) { 2681 if (foundtable[i] == false) 2682 continue; 2683 2684 /* 2685 * The type was found. Search capability list again and 2686 * print all capabilities that the capabiliy type is 2687 * the same. This is required because some capabilities 2688 * appear multiple times (e.g. HyperTransport capability). 2689 */ 2690 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2691 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2692 rval = regs[o2i(off)]; 2693 if ((PCI_CAPLIST_CAP(rval) == i) 2694 && (pci_captab[i].printfunc != NULL)) 2695 pci_captab[i].printfunc(regs, off); 2696 } 2697 } 2698 } 2699 2700 /* Extended Capability */ 2701 2702 static void 2703 pci_conf_print_aer_cap_uc(pcireg_t reg) 2704 { 2705 2706 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2707 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2708 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2709 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2710 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2711 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2712 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2713 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2714 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2715 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2716 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2717 onoff("Unsupported Request Error", reg, 2718 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2719 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2720 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2721 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2722 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2723 onoff("TLP Prefix Blocked Error", reg, 2724 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2725 onoff("Poisoned TLP Egress Blocked", reg, 2726 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2727 } 2728 2729 static void 2730 pci_conf_print_aer_cap_cor(pcireg_t reg) 2731 { 2732 2733 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2734 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2735 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2736 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2737 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2738 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2739 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2740 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2741 } 2742 2743 static void 2744 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2745 { 2746 2747 printf(" First Error Pointer: 0x%04x\n", 2748 PCIREG_SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2749 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2750 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2751 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2752 onoff("ECRC Check Enable", reg, PCI_AER_ECRC_CHECK_ENABLE); 2753 onoff("Multiple Header Recording Capable", reg, 2754 PCI_AER_MULT_HDR_CAPABLE); 2755 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2756 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2757 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2758 2759 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2760 if (!tlp_prefix_log) 2761 return; 2762 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2763 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2764 } 2765 2766 static void 2767 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2768 { 2769 2770 onoff("Correctable Error Reporting Enable", reg, 2771 PCI_AER_ROOTERR_COR_ENABLE); 2772 onoff("Non-Fatal Error Reporting Enable", reg, 2773 PCI_AER_ROOTERR_NF_ENABLE); 2774 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2775 } 2776 2777 static void 2778 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2779 { 2780 2781 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2782 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2783 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2784 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2785 PCI_AER_ROOTERR_MULTI_UC_ERR); 2786 onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL); 2787 onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR); 2788 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2789 printf(" Advanced Error Interrupt Message Number: 0x%02x\n", 2790 PCIREG_SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2791 } 2792 2793 static void 2794 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2795 { 2796 2797 printf(" Correctable Source ID: 0x%04x\n", 2798 PCIREG_SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2799 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2800 PCIREG_SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2801 } 2802 2803 static void 2804 pci_conf_print_aer_cap(const pcireg_t *regs, int extcapoff) 2805 { 2806 pcireg_t reg; 2807 int pcie_capoff; 2808 int pcie_devtype = -1; 2809 bool tlp_prefix_log = false; 2810 2811 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2812 reg = regs[o2i(pcie_capoff)]; 2813 pcie_devtype = PCIE_XCAP_TYPE(reg); 2814 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2815 if (PCIREG_SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2816 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2817 /* End-End TLP Prefix Supported */ 2818 if (reg & PCIE_DCAP2_EETLP_PREF) { 2819 tlp_prefix_log = true; 2820 } 2821 } 2822 } 2823 2824 printf("\n Advanced Error Reporting Register\n"); 2825 2826 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2827 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2828 pci_conf_print_aer_cap_uc(reg); 2829 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2830 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2831 pci_conf_print_aer_cap_uc(reg); 2832 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2833 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2834 pci_conf_print_aer_cap_uc(reg); 2835 2836 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2837 printf(" Correctable Error Status register: 0x%08x\n", reg); 2838 pci_conf_print_aer_cap_cor(reg); 2839 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2840 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2841 pci_conf_print_aer_cap_cor(reg); 2842 2843 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2844 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2845 reg); 2846 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2847 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2848 printf(" Header Log register:\n"); 2849 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2850 extcapoff + PCI_AER_ROOTERR_CMD); 2851 2852 switch (pcie_devtype) { 2853 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2854 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2855 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2856 printf(" Root Error Command register: 0x%08x\n", reg); 2857 pci_conf_print_aer_cap_rooterr_cmd(reg); 2858 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2859 printf(" Root Error Status register: 0x%08x\n", reg); 2860 pci_conf_print_aer_cap_rooterr_status(reg); 2861 2862 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2863 printf(" Error Source Identification register: 0x%08x\n", 2864 reg); 2865 pci_conf_print_aer_cap_errsrc_id(reg); 2866 break; 2867 } 2868 2869 if (tlp_prefix_log) { 2870 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2871 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2872 } 2873 } 2874 2875 /* 2876 * Helper function to print the arbitration phase register. 2877 * 2878 * phases: Number of phases in the arbitration tables. 2879 * arbsize: Number of bits in each phase. 2880 * indent: Add more two spaces if it's true. 2881 */ 2882 static void 2883 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2884 const int phases, int arbsize, bool indent) 2885 { 2886 pcireg_t reg; 2887 int num_per_reg = 32 / arbsize; 2888 int i, j; 2889 2890 printf("%s %s Arbitration Table:\n", indent ? " " : "", name); 2891 for (i = 0; i < phases; i += num_per_reg) { 2892 reg = regs[o2i(off + (sizeof(uint32_t) * (i / num_per_reg)))]; 2893 for (j = 0; j < num_per_reg; j++) { 2894 printf("%s Phase[%d]: 0x%x\n", indent ? " " : "", 2895 i + j, 2896 (uint32_t)(reg & __BITS(arbsize - 1, 0))); 2897 reg >>= arbsize; 2898 } 2899 } 2900 } 2901 2902 /* For VC, bit 4-7 are reserved. For Port, bit 6-7 are reserved */ 2903 static const int arb_phases[8] = {0, 32, 64, 128, 128, 256, 0, 0 }; 2904 2905 static void 2906 pci_conf_print_vc_cap(const pcireg_t *regs, int extcapoff) 2907 { 2908 pcireg_t reg, n; 2909 int arbtab, parbsize; 2910 pcireg_t arbsel; 2911 int i, count; 2912 2913 printf("\n Virtual Channel Register\n"); 2914 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2915 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2916 count = PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2917 printf(" Extended VC Count: %d\n", count); 2918 n = PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2919 printf(" Low Priority Extended VC Count: %u\n", n); 2920 n = PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2921 printf(" Reference Clock: %s\n", 2922 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 2923 parbsize = 1 << PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2924 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2925 2926 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2927 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2928 onoff("Hardware fixed arbitration scheme", 2929 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2930 onoff("WRR arbitration with 32 phases", 2931 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2932 onoff("WRR arbitration with 64 phases", 2933 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2934 onoff("WRR arbitration with 128 phases", 2935 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2936 arbtab = PCIREG_SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2937 printf(" VC Arbitration Table Offset: 0x%x\n", arbtab); 2938 2939 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2940 printf(" Port VC Control register: 0x%04x\n", reg); 2941 arbsel = PCIREG_SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2942 printf(" VC Arbitration Select: 0x%x\n", arbsel); 2943 2944 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2945 printf(" Port VC Status register: 0x%04x\n", reg); 2946 onoff("VC Arbitration Table Status", 2947 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 2948 2949 if ((arbtab != 0) && (arbsel != 0)) 2950 pci_conf_print_vc_cap_arbtab(regs, extcapoff + (arbtab * 16), 2951 "VC", arb_phases[arbsel], 4, false); 2952 2953 for (i = 0; i < count + 1; i++) { 2954 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 2955 printf(" VC number %d\n", i); 2956 printf(" VC Resource Capability Register: 0x%08x\n", reg); 2957 onoff(" Non-configurable Hardware fixed arbitration scheme", 2958 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 2959 onoff(" WRR arbitration with 32 phases", 2960 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 2961 onoff(" WRR arbitration with 64 phases", 2962 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 2963 onoff(" WRR arbitration with 128 phases", 2964 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 2965 onoff(" Time-based WRR arbitration with 128 phases", 2966 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 2967 onoff(" WRR arbitration with 256 phases", 2968 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 2969 onoff(" Advanced Packet Switching", 2970 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 2971 onoff(" Reject Snoop Transaction", 2972 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 2973 n = PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 2974 printf(" Maximum Time Slots: %d\n", n); 2975 arbtab = PCIREG_SHIFTOUT(reg, 2976 PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET); 2977 printf(" Port Arbitration Table offset: 0x%02x\n", 2978 arbtab); 2979 2980 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 2981 printf(" VC Resource Control Register: 0x%08x\n", reg); 2982 printf(" TC/VC Map: 0x%02x\n", 2983 PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 2984 /* 2985 * The load Port Arbitration Table bit is used to update 2986 * the Port Arbitration logic and it's always 0 on read, so 2987 * we don't print it. 2988 */ 2989 arbsel = PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 2990 printf(" Port Arbitration Select: 0x%x\n", arbsel); 2991 n = PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 2992 printf(" VC ID: %d\n", n); 2993 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 2994 2995 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 2996 printf(" VC Resource Status Register: 0x%08x\n", reg); 2997 onoff(" Port Arbitration Table Status", 2998 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 2999 onoff(" VC Negotiation Pending", 3000 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 3001 3002 if ((arbtab != 0) && (arbsel != 0)) 3003 pci_conf_print_vc_cap_arbtab(regs, 3004 extcapoff + (arbtab * 16), 3005 "Port", arb_phases[arbsel], parbsize, true); 3006 } 3007 } 3008 3009 /* 3010 * Print Power limit. This encoding is the same among the following registers: 3011 * - The Captured Slot Power Limit in the PCIe Device Capability Register. 3012 * - The Slot Power Limit in the PCIe Slot Capability Register. 3013 * - The Base Power in the Data register of Power Budgeting capability. 3014 */ 3015 static void 3016 pci_conf_print_pcie_power(uint8_t base, unsigned int scale) 3017 { 3018 unsigned int sdiv = 1; 3019 3020 if ((scale == 0) && (base > 0xef)) { 3021 const char *s; 3022 3023 switch (base) { 3024 case 0xf0: 3025 s = "239W < x <= 250W"; 3026 break; 3027 case 0xf1: 3028 s = "250W < x <= 275W"; 3029 break; 3030 case 0xf2: 3031 s = "275W < x <= 300W"; 3032 break; 3033 default: 3034 s = "reserved for greater than 300W"; 3035 break; 3036 } 3037 printf("%s\n", s); 3038 return; 3039 } 3040 3041 for (unsigned int i = scale; i > 0; i--) 3042 sdiv *= 10; 3043 3044 printf("%u", base / sdiv); 3045 3046 if (scale != 0) { 3047 printf(".%u", base % sdiv); 3048 } 3049 printf ("W\n"); 3050 return; 3051 } 3052 3053 static const char * 3054 pci_conf_print_pwrbdgt_type(uint8_t reg) 3055 { 3056 3057 switch (reg) { 3058 case 0x00: 3059 return "PME Aux"; 3060 case 0x01: 3061 return "Auxilary"; 3062 case 0x02: 3063 return "Idle"; 3064 case 0x03: 3065 return "Sustained"; 3066 case 0x04: 3067 return "Sustained (Emergency Power Reduction)"; 3068 case 0x05: 3069 return "Maximum (Emergency Power Reduction)"; 3070 case 0x07: 3071 return "Maximum"; 3072 default: 3073 return "Unknown"; 3074 } 3075 } 3076 3077 static const char * 3078 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 3079 { 3080 3081 switch (reg) { 3082 case 0x00: 3083 return "Power(12V)"; 3084 case 0x01: 3085 return "Power(3.3V)"; 3086 case 0x02: 3087 return "Power(1.5V or 1.8V)"; 3088 case 0x07: 3089 return "Thermal"; 3090 default: 3091 return "Unknown"; 3092 } 3093 } 3094 3095 static void 3096 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int extcapoff) 3097 { 3098 pcireg_t reg; 3099 3100 printf("\n Power Budgeting\n"); 3101 3102 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 3103 printf(" Data Select register: 0x%08x\n", reg); 3104 3105 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 3106 printf(" Data register: 0x%08x\n", reg); 3107 printf(" Base Power: "); 3108 pci_conf_print_pcie_power( 3109 PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_DATA_BASEPWR), 3110 PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE)); 3111 printf(" PM Sub State: 0x%hhx\n", 3112 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 3113 printf(" PM State: D%u\n", 3114 PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 3115 printf(" Type: %s\n", 3116 pci_conf_print_pwrbdgt_type( 3117 (uint8_t)(PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 3118 printf(" Power Rail: %s\n", 3119 pci_conf_print_pwrbdgt_pwrrail( 3120 (uint8_t)(PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 3121 3122 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 3123 printf(" Power Budget Capability register: 0x%08x\n", reg); 3124 onoff("System Allocated", 3125 reg, PCI_PWRBDGT_CAP_SYSALLOC); 3126 } 3127 3128 static const char * 3129 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 3130 { 3131 3132 switch (type) { 3133 case 0x00: 3134 return "Configuration Space Element"; 3135 case 0x01: 3136 return "System Egress Port or internal sink (memory)"; 3137 case 0x02: 3138 return "Internal Root Complex Link"; 3139 default: 3140 return "Unknown"; 3141 } 3142 } 3143 3144 static void 3145 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int extcapoff) 3146 { 3147 pcireg_t reg; 3148 unsigned char nent, linktype; 3149 int i; 3150 3151 printf("\n Root Complex Link Declaration\n"); 3152 3153 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 3154 printf(" Element Self Description Register: 0x%08x\n", reg); 3155 printf(" Element Type: %s\n", 3156 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 3157 nent = PCIREG_SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 3158 printf(" Number of Link Entries: %hhu\n", nent); 3159 printf(" Component ID: %hhu\n", 3160 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 3161 printf(" Port Number: %hhu\n", 3162 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 3163 for (i = 0; i < nent; i++) { 3164 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 3165 printf(" Link Entry %d:\n", i + 1); 3166 printf(" Link Description Register: 0x%08x\n", reg); 3167 onoff(" Link Valid", reg, PCI_RCLINK_DCL_LINKDESC_LVALID); 3168 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 3169 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 3170 "Configuration Space", "Memory-Mapped Space"); 3171 onoff(" Associated RCRB Header", reg, 3172 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 3173 printf(" Target Component ID: %hhu\n", 3174 (uint8_t)PCIREG_SHIFTOUT(reg, 3175 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 3176 printf(" Target Port Number: %hhu\n", 3177 (uint8_t)PCIREG_SHIFTOUT(reg, 3178 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 3179 3180 if (linktype == 0) { 3181 /* Memory-Mapped Space */ 3182 reg = regs[o2i(extcapoff 3183 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 3184 printf(" Link Address Low Register: 0x%08x\n", 3185 reg); 3186 reg = regs[o2i(extcapoff 3187 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 3188 printf(" Link Address High Register: 0x%08x\n", 3189 reg); 3190 } else { 3191 unsigned int nb; 3192 pcireg_t lo, hi; 3193 3194 /* Configuration Space */ 3195 lo = regs[o2i(extcapoff 3196 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 3197 printf(" Configuration Space Low Register: " 3198 "0x%08x\n", lo); 3199 hi = regs[o2i(extcapoff 3200 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 3201 printf(" Configuration Space High Register: " 3202 "0x%08x\n", hi); 3203 nb = PCIREG_SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 3204 printf(" N: %u\n", nb); 3205 printf(" Func: %hhu\n", 3206 (uint8_t)PCIREG_SHIFTOUT(lo, 3207 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 3208 printf(" Dev: %hhu\n", 3209 (uint8_t)PCIREG_SHIFTOUT(lo, 3210 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 3211 printf(" Bus: %hhu\n", 3212 (uint8_t)PCIREG_SHIFTOUT(lo, 3213 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 3214 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 3215 printf(" Configuration Space Base Address: " 3216 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 3217 } 3218 } 3219 } 3220 3221 /* XXX pci_conf_print_rclink_ctl_cap */ 3222 3223 static void 3224 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int extcapoff) 3225 { 3226 pcireg_t reg; 3227 3228 printf("\n Root Complex Event Collector Association\n"); 3229 3230 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 3231 printf(" Association Bitmap for Root Complex Integrated Devices:" 3232 " 0x%08x\n", reg); 3233 3234 if (PCI_EXTCAPLIST_VERSION(regs[o2i(extcapoff)]) >= 2) { 3235 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBUSNUM)]; 3236 printf(" RCEC Associated Bus Numbers register: 0x%08x\n", 3237 reg); 3238 printf(" RCEC Next Bus: %u\n", 3239 PCIREG_SHIFTOUT(reg, 3240 PCI_RCEC_ASSOCBUSNUM_RCECNEXT)); 3241 printf(" RCEC Last Bus: %u\n", 3242 PCIREG_SHIFTOUT(reg, 3243 PCI_RCEC_ASSOCBUSNUM_RCECLAST)); 3244 } 3245 } 3246 3247 /* XXX pci_conf_print_mfvc_cap */ 3248 /* XXX pci_conf_print_vc2_cap */ 3249 /* XXX pci_conf_print_rcrb_cap */ 3250 /* XXX pci_conf_print_vendor_cap */ 3251 /* XXX pci_conf_print_cac_cap */ 3252 3253 static void 3254 pci_conf_print_acs_cap(const pcireg_t *regs, int extcapoff) 3255 { 3256 pcireg_t reg, cap, ctl; 3257 unsigned int size, i; 3258 3259 printf("\n Access Control Services\n"); 3260 3261 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 3262 cap = reg & 0xffff; 3263 ctl = reg >> 16; 3264 printf(" ACS Capability register: 0x%08x\n", cap); 3265 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 3266 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 3267 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 3268 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 3269 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 3270 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 3271 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 3272 size = PCIREG_SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 3273 if (size == 0) 3274 size = 256; 3275 printf(" Egress Control Vector Size: %u\n", size); 3276 printf(" ACS Control register: 0x%08x\n", ctl); 3277 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 3278 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 3279 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 3280 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 3281 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 3282 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 3283 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 3284 3285 /* 3286 * If the P2P Egress Control Capability bit is 0, ignore the Egress 3287 * Control vector. 3288 */ 3289 if ((cap & PCI_ACS_CAP_E) == 0) 3290 return; 3291 for (i = 0; i < size; i += 32) 3292 printf(" Egress Control Vector [%u..%u]: 0x%08x\n", i + 31, 3293 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 3294 } 3295 3296 static void 3297 pci_conf_print_ari_cap(const pcireg_t *regs, int extcapoff) 3298 { 3299 pcireg_t reg, cap, ctl; 3300 3301 printf("\n Alternative Routing-ID Interpretation Register\n"); 3302 3303 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3304 cap = reg & 0xffff; 3305 ctl = reg >> 16; 3306 printf(" Capability register: 0x%08x\n", cap); 3307 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 3308 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 3309 printf(" Next Function Number: %u\n", 3310 PCIREG_SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 3311 printf(" Control register: 0x%08x\n", ctl); 3312 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 3313 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 3314 printf(" Function Group: %u\n", 3315 PCIREG_SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 3316 } 3317 3318 static void 3319 pci_conf_print_ats_cap(const pcireg_t *regs, int extcapoff) 3320 { 3321 pcireg_t reg, cap, ctl; 3322 unsigned int num; 3323 3324 printf("\n Address Translation Services\n"); 3325 3326 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3327 cap = reg & 0xffff; 3328 ctl = reg >> 16; 3329 printf(" Capability register: 0x%04x\n", cap); 3330 num = PCIREG_SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 3331 if (num == 0) 3332 num = 32; 3333 printf(" Invalidate Queue Depth: %u\n", num); 3334 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 3335 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 3336 onoff("Relaxed Ordering", reg, PCI_ATS_CAP_RELAXORD); 3337 3338 printf(" Control register: 0x%04x\n", ctl); 3339 printf(" Smallest Translation Unit: %u\n", 3340 PCIREG_SHIFTOUT(reg, PCI_ATS_CTL_STU)); 3341 onoff("Enable", reg, PCI_ATS_CTL_EN); 3342 } 3343 3344 static void 3345 pci_conf_print_sernum_cap(const pcireg_t *regs, int extcapoff) 3346 { 3347 pcireg_t lo, hi; 3348 3349 printf("\n Device Serial Number Register\n"); 3350 3351 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 3352 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 3353 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 3354 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 3355 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 3356 } 3357 3358 static void 3359 pci_conf_print_sriov_cap(const pcireg_t *regs, int extcapoff) 3360 { 3361 char buf[sizeof("99999 MB")]; 3362 pcireg_t reg; 3363 pcireg_t total_vfs; 3364 int i; 3365 bool first; 3366 3367 printf("\n Single Root IO Virtualization Register\n"); 3368 3369 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 3370 printf(" Capabilities register: 0x%08x\n", reg); 3371 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 3372 onoff("ARI Capable Hierarchy Preserved", reg, 3373 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 3374 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 3375 printf(" VF Migration Interrupt Message Number: 0x%03x\n", 3376 PCIREG_SHIFTOUT(reg, PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 3377 } 3378 3379 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 3380 printf(" Control register: 0x%04x\n", reg); 3381 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 3382 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 3383 onoff("VF Migration Interrupt Enable", reg, 3384 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 3385 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 3386 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 3387 3388 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 3389 printf(" Status register: 0x%04x\n", reg); 3390 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 3391 3392 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 3393 printf(" InitialVFs register: 0x%04x\n", reg); 3394 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 3395 printf(" TotalVFs register: 0x%04x\n", reg); 3396 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 3397 printf(" NumVFs register: 0x%04x\n", reg); 3398 3399 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 3400 printf(" Function Dependency Link register: 0x%04x\n", reg); 3401 3402 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 3403 printf(" First VF Offset register: 0x%04x\n", reg); 3404 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 3405 printf(" VF Stride register: 0x%04x\n", reg); 3406 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16; 3407 printf(" Device ID: 0x%04x\n", reg); 3408 3409 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 3410 printf(" Supported Page Sizes register: 0x%08x\n", reg); 3411 printf(" Supported Page Size:"); 3412 for (i = 0, first = true; i < 32; i++) { 3413 if (reg & __BIT(i)) { 3414 #ifdef _KERNEL 3415 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 3416 #else 3417 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 3418 HN_AUTOSCALE, 0); 3419 #endif 3420 printf("%s %s", first ? "" : ",", buf); 3421 first = false; 3422 } 3423 } 3424 printf("\n"); 3425 3426 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 3427 printf(" System Page Sizes register: 0x%08x\n", reg); 3428 printf(" Page Size: "); 3429 if (reg != 0) { 3430 int bitpos = ffs(reg) -1; 3431 3432 /* Assume only one bit is set. */ 3433 #ifdef _KERNEL 3434 format_bytes(buf, sizeof(buf), 1LL << (bitpos + 12)); 3435 #else 3436 humanize_number(buf, sizeof(buf), 1LL << (bitpos + 12), 3437 "B", HN_AUTOSCALE, 0); 3438 #endif 3439 printf("%s", buf); 3440 } else { 3441 printf("unknown"); 3442 } 3443 printf("\n"); 3444 3445 for (i = 0; i < 6; i++) { 3446 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 3447 printf(" VF BAR%d register: 0x%08x\n", i, reg); 3448 } 3449 3450 if (total_vfs > 0) { 3451 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 3452 printf(" VF Migration State Array Offset register: 0x%08x\n", 3453 reg); 3454 printf(" VF Migration State Offset: 0x%08x\n", 3455 PCIREG_SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 3456 i = PCIREG_SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 3457 printf(" VF Migration State BIR: "); 3458 if (i >= 0 && i <= 5) { 3459 printf("BAR%d", i); 3460 } else { 3461 printf("unknown BAR (%d)", i); 3462 } 3463 printf("\n"); 3464 } 3465 } 3466 3467 /* XXX pci_conf_print_mriov_cap */ 3468 3469 static void 3470 pci_conf_print_multicast_cap(const pcireg_t *regs, int extcapoff) 3471 { 3472 pcireg_t reg, cap, ctl; 3473 pcireg_t regl, regh; 3474 uint64_t addr; 3475 int n; 3476 3477 printf("\n Multicast\n"); 3478 3479 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 3480 cap = reg & 0xffff; 3481 ctl = reg >> 16; 3482 printf(" Capability Register: 0x%04x\n", cap); 3483 printf(" Max Group: %u\n", 3484 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 3485 3486 /* Endpoint Only */ 3487 n = PCIREG_SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 3488 if (n > 0) 3489 printf(" Windw Size Requested: %d\n", 1 << (n - 1)); 3490 3491 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 3492 3493 printf(" Control Register: 0x%04x\n", ctl); 3494 printf(" Num Group: %u\n", 3495 PCIREG_SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 3496 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 3497 3498 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 3499 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 3500 printf(" Base Address Register 0: 0x%08x\n", regl); 3501 printf(" Base Address Register 1: 0x%08x\n", regh); 3502 printf(" Index Position: %u\n", 3503 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 3504 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 3505 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 3506 3507 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 3508 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 3509 printf(" Receive Register 0: 0x%08x\n", regl); 3510 printf(" Receive Register 1: 0x%08x\n", regh); 3511 3512 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 3513 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 3514 printf(" Block All Register 0: 0x%08x\n", regl); 3515 printf(" Block All Register 1: 0x%08x\n", regh); 3516 3517 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 3518 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 3519 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 3520 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 3521 3522 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 3523 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 3524 printf(" Overlay BAR 0: 0x%08x\n", regl); 3525 printf(" Overlay BAR 1: 0x%08x\n", regh); 3526 3527 n = regl & PCI_MCAST_OVERLAYL_SIZE; 3528 printf(" Overlay Size: "); 3529 if (n >= 6) 3530 printf("%d\n", n); 3531 else 3532 printf("off\n"); 3533 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 3534 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 3535 } 3536 3537 static void 3538 pci_conf_print_page_req_cap(const pcireg_t *regs, int extcapoff) 3539 { 3540 pcireg_t reg, ctl, sta; 3541 3542 printf("\n Page Request\n"); 3543 3544 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 3545 ctl = reg & 0xffff; 3546 sta = reg >> 16; 3547 printf(" Control Register: 0x%04x\n", ctl); 3548 onoff("Enable", reg, PCI_PAGE_REQ_CTL_E); 3549 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 3550 3551 printf(" Status Register: 0x%04x\n", sta); 3552 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 3553 onoff("Unexpected Page Request Group Index", reg, 3554 PCI_PAGE_REQ_STA_UPRGI); 3555 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 3556 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 3557 3558 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 3559 printf(" Outstanding Page Request Capacity: %u\n", reg); 3560 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 3561 printf(" Outstanding Page Request Allocation: %u\n", reg); 3562 } 3563 3564 /* XXX pci_conf_print_amd_cap */ 3565 3566 #define MEM_PBUFSIZE sizeof("999GB") 3567 3568 static void 3569 pci_conf_print_resizbar_cap(const pcireg_t *regs, int extcapoff) 3570 { 3571 pcireg_t cap, ctl; 3572 unsigned int bars, i, n; 3573 char pbuf[MEM_PBUFSIZE]; 3574 3575 printf("\n Resizable BAR\n"); 3576 3577 /* Get Number of Resizable BARs */ 3578 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))]; 3579 bars = PCIREG_SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR); 3580 printf(" Number of Resizable BARs: "); 3581 if (bars <= 6) 3582 printf("%u\n", bars); 3583 else { 3584 printf("incorrect (%u)\n", bars); 3585 return; 3586 } 3587 3588 for (n = 0; n < 6; n++) { 3589 cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))]; 3590 printf(" Capability register(%u): 0x%08x\n", n, cap); 3591 if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0) 3592 continue; /* Not Used */ 3593 printf(" Acceptable BAR sizes:"); 3594 for (i = 4; i <= 23; i++) { 3595 if ((cap & (1 << i)) != 0) { 3596 humanize_number(pbuf, MEM_PBUFSIZE, 3597 (int64_t)1024 * 1024 << (i - 4), "B", 3598 #ifdef _KERNEL 3599 1); 3600 #else 3601 HN_AUTOSCALE, HN_NOSPACE); 3602 #endif 3603 printf(" %s", pbuf); 3604 } 3605 } 3606 printf("\n"); 3607 3608 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))]; 3609 printf(" Control register(%u): 0x%08x\n", n, ctl); 3610 printf(" BAR Index: %u\n", 3611 PCIREG_SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX)); 3612 humanize_number(pbuf, MEM_PBUFSIZE, 3613 (int64_t)1024 * 1024 3614 << PCIREG_SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ), 3615 "B", 3616 #ifdef _KERNEL 3617 1); 3618 #else 3619 HN_AUTOSCALE, HN_NOSPACE); 3620 #endif 3621 printf(" BAR Size: %s\n", pbuf); 3622 } 3623 } 3624 3625 static void 3626 pci_conf_print_dpa_cap(const pcireg_t *regs, int extcapoff) 3627 { 3628 pcireg_t reg; 3629 unsigned int substmax, i; 3630 3631 printf("\n Dynamic Power Allocation\n"); 3632 3633 reg = regs[o2i(extcapoff + PCI_DPA_CAP)]; 3634 printf(" Capability register: 0x%08x\n", reg); 3635 substmax = PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX); 3636 printf(" Substate Max: %u\n", substmax); 3637 printf(" Transition Latency Unit: "); 3638 switch (PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) { 3639 case 0: 3640 printf("1ms\n"); 3641 break; 3642 case 1: 3643 printf("10ms\n"); 3644 break; 3645 case 2: 3646 printf("100ms\n"); 3647 break; 3648 default: 3649 printf("reserved\n"); 3650 break; 3651 } 3652 printf(" Power Allocation Scale: "); 3653 switch (PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_PAS)) { 3654 case 0: 3655 printf("10.0x\n"); 3656 break; 3657 case 1: 3658 printf("1.0x\n"); 3659 break; 3660 case 2: 3661 printf("0.1x\n"); 3662 break; 3663 case 3: 3664 printf("0.01x\n"); 3665 break; 3666 } 3667 printf(" Transition Latency Value 0: %u\n", 3668 PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_XLCY0)); 3669 printf(" Transition Latency Value 1: %u\n", 3670 PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); 3671 3672 reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; 3673 printf(" Latency Indicatior register: 0x%08x\n", reg); 3674 3675 reg = regs[o2i(extcapoff + PCI_DPA_CS)]; 3676 printf(" Status register: 0x%04x\n", reg & 0xffff); 3677 printf(" Substate Status: 0x%02x\n", 3678 PCIREG_SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT)); 3679 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN); 3680 printf(" Control register: 0x%04x\n", reg >> 16); 3681 printf(" Substate Control: 0x%02x\n", 3682 PCIREG_SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL)); 3683 3684 for (i = 0; i <= substmax; i++) 3685 printf(" Substate Power Allocation register %d: 0x%02x\n", 3686 i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff)); 3687 } 3688 3689 static const char * 3690 pci_conf_print_tph_req_cap_sttabloc(uint8_t val) 3691 { 3692 3693 switch (val) { 3694 case PCI_TPH_REQ_STTBLLOC_NONE: 3695 return "Not Present"; 3696 case PCI_TPH_REQ_STTBLLOC_TPHREQ: 3697 return "in the TPH Requester Capability Structure"; 3698 case PCI_TPH_REQ_STTBLLOC_MSIX: 3699 return "in the MSI-X Table"; 3700 default: 3701 return "Unknown"; 3702 } 3703 } 3704 3705 static void 3706 pci_conf_print_tph_req_cap(const pcireg_t *regs, int extcapoff) 3707 { 3708 pcireg_t reg; 3709 int size = 0, i, j; 3710 uint8_t sttbloc; 3711 3712 printf("\n TPH Requester Extended Capability\n"); 3713 3714 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3715 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3716 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3717 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3718 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3719 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3720 sttbloc = PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC); 3721 printf(" ST Table Location: %s\n", 3722 pci_conf_print_tph_req_cap_sttabloc(sttbloc)); 3723 if (sttbloc == PCI_TPH_REQ_STTBLLOC_TPHREQ) { 3724 size = PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3725 printf(" ST Table Size: %d\n", size); 3726 } 3727 3728 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CTL)]; 3729 printf(" TPH Requester Control register: 0x%08x\n", reg); 3730 printf(" ST Mode Select: "); 3731 switch (PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CTL_STSEL)) { 3732 case PCI_TPH_REQ_CTL_STSEL_NO: 3733 printf("No ST Mode\n"); 3734 break; 3735 case PCI_TPH_REQ_CTL_STSEL_IV: 3736 printf("Interrupt Vector Mode\n"); 3737 break; 3738 case PCI_TPH_REQ_CTL_STSEL_DS: 3739 printf("Device Specific Mode\n"); 3740 break; 3741 default: 3742 printf("(reserved value)\n"); 3743 break; 3744 } 3745 printf(" TPH Requester Enable: "); 3746 switch (PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CTL_TPHREQEN)) { 3747 case PCI_TPH_REQ_CTL_TPHREQEN_NO: /* 0x0 */ 3748 printf("Not permitted\n"); 3749 break; 3750 case PCI_TPH_REQ_CTL_TPHREQEN_TPH: 3751 printf("TPH and not Extended TPH\n"); 3752 break; 3753 case PCI_TPH_REQ_CTL_TPHREQEN_ETPH: 3754 printf("TPH and Extended TPH"); 3755 break; 3756 default: 3757 printf("(reserved value)\n"); 3758 break; 3759 } 3760 3761 if (sttbloc != PCI_TPH_REQ_STTBLLOC_TPHREQ) 3762 return; 3763 3764 for (i = 0; i < size ; i += 2) { 3765 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3766 for (j = 0; j < 2 ; j++) { 3767 uint32_t entry = reg; 3768 3769 if (j != 0) 3770 entry >>= 16; 3771 entry &= 0xffff; 3772 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3773 i + j, entry); 3774 } 3775 } 3776 } 3777 3778 static void 3779 pci_conf_print_ltr_cap(const pcireg_t *regs, int extcapoff) 3780 { 3781 pcireg_t reg; 3782 3783 printf("\n Latency Tolerance Reporting\n"); 3784 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)]; 3785 printf(" Max Snoop Latency Register: 0x%04x\n", reg & 0xffff); 3786 printf(" Max Snoop Latency: %juns\n", 3787 (uintmax_t)(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL) 3788 * PCI_LTR_SCALETONS(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE)))); 3789 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg >> 16); 3790 printf(" Max No-Snoop Latency: %juns\n", 3791 (uintmax_t)(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL) 3792 * PCI_LTR_SCALETONS(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE)))); 3793 } 3794 3795 static void 3796 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int extcapoff) 3797 { 3798 int pcie_capoff; 3799 pcireg_t reg; 3800 int i, maxlinkwidth; 3801 3802 printf("\n Secondary PCI Express Register\n"); 3803 3804 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3805 printf(" Link Control 3 register: 0x%08x\n", reg); 3806 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3807 onoff("Link Equalization Request Interrupt Enable", 3808 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3809 printf(" Enable Lower SKP OS Generation Vector:"); 3810 pci_print_pcie_linkspeedvector( 3811 PCIREG_SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3812 printf("\n"); 3813 3814 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3815 printf(" Lane Error Status register: 0x%08x\n", reg); 3816 3817 /* Get Max Link Width */ 3818 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 3819 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3820 maxlinkwidth = PCIREG_SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3821 } else { 3822 printf("error: falied to get PCIe capablity\n"); 3823 return; 3824 } 3825 for (i = 0; i < maxlinkwidth; i++) { 3826 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3827 if (i % 2 != 0) 3828 reg >>= 16; 3829 else 3830 reg &= 0xffff; 3831 printf(" Equalization Control Register (Link %d): 0x%04x\n", 3832 i, reg); 3833 printf(" Downstream Port Transmit Preset: 0x%x\n", 3834 PCIREG_SHIFTOUT(reg, 3835 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3836 printf(" Downstream Port Receive Hint: 0x%x\n", 3837 PCIREG_SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3838 printf(" Upstream Port Transmit Preset: 0x%x\n", 3839 PCIREG_SHIFTOUT(reg, 3840 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3841 printf(" Upstream Port Receive Hint: 0x%x\n", 3842 PCIREG_SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3843 } 3844 } 3845 3846 /* XXX pci_conf_print_pmux_cap */ 3847 3848 static void 3849 pci_conf_print_pasid_cap(const pcireg_t *regs, int extcapoff) 3850 { 3851 pcireg_t reg, cap, ctl; 3852 unsigned int num; 3853 3854 printf("\n Process Address Space ID\n"); 3855 3856 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3857 cap = reg & 0xffff; 3858 ctl = reg >> 16; 3859 printf(" PASID Capability Register: 0x%04x\n", cap); 3860 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3861 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3862 num = (1 << PCIREG_SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3863 printf(" Max PASID Width: %u\n", num); 3864 3865 printf(" PASID Control Register: 0x%04x\n", ctl); 3866 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3867 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3868 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3869 } 3870 3871 static void 3872 pci_conf_print_lnr_cap(const pcireg_t *regs, int extcapoff) 3873 { 3874 pcireg_t reg, cap, ctl; 3875 unsigned int num; 3876 3877 printf("\n LN Requester\n"); 3878 3879 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3880 cap = reg & 0xffff; 3881 ctl = reg >> 16; 3882 printf(" LNR Capability register: 0x%04x\n", cap); 3883 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 3884 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 3885 num = 1 << PCIREG_SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 3886 printf(" LNR Registration MAX: %u\n", num); 3887 3888 printf(" LNR Control register: 0x%04x\n", ctl); 3889 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 3890 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 3891 num = 1 << PCIREG_SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 3892 printf(" LNR Registration Limit: %u\n", num); 3893 } 3894 3895 static void 3896 pci_conf_print_dpc_pio(pcireg_t r) 3897 { 3898 onoff("Cfg Request received UR Completion", r,PCI_DPC_RPPIO_CFGUR_CPL); 3899 onoff("Cfg Request received CA Completion", r,PCI_DPC_RPPIO_CFGCA_CPL); 3900 onoff("Cfg Request Completion Timeout", r, PCI_DPC_RPPIO_CFG_CTO); 3901 onoff("I/O Request received UR Completion", r, PCI_DPC_RPPIO_IOUR_CPL); 3902 onoff("I/O Request received CA Completion", r, PCI_DPC_RPPIO_IOCA_CPL); 3903 onoff("I/O Request Completion Timeout", r, PCI_DPC_RPPIO_IO_CTO); 3904 onoff("Mem Request received UR Completion", r,PCI_DPC_RPPIO_MEMUR_CPL); 3905 onoff("Mem Request received CA Completion", r,PCI_DPC_RPPIO_MEMCA_CPL); 3906 onoff("Mem Request Completion Timeout", r, PCI_DPC_RPPIO_MEM_CTO); 3907 } 3908 3909 static void 3910 pci_conf_print_dpc_cap(const pcireg_t *regs, int extcapoff) 3911 { 3912 pcireg_t reg, cap, ctl, stat, errsrc; 3913 const char *trigstr; 3914 bool rpext; 3915 3916 printf("\n Downstream Port Containment\n"); 3917 3918 reg = regs[o2i(extcapoff + PCI_DPC_CCR)]; 3919 cap = reg & 0xffff; 3920 ctl = reg >> 16; 3921 rpext = (reg & PCI_DPCCAP_RPEXT) ? true : false; 3922 printf(" DPC Capability register: 0x%04x\n", cap); 3923 printf(" DPC Interrupt Message Number: %02x\n", 3924 (unsigned int)(cap & PCI_DPCCAP_IMSGN)); 3925 onoff("RP Extensions for DPC", reg, PCI_DPCCAP_RPEXT); 3926 onoff("Poisoned TLP Egress Blocking Supported", reg, 3927 PCI_DPCCAP_POISONTLPEB); 3928 onoff("DPC Software Triggering Supported", reg, PCI_DPCCAP_SWTRIG); 3929 printf(" RP PIO Log Size: %u\n", 3930 PCIREG_SHIFTOUT(reg, PCI_DPCCAP_RPPIOLOGSZ)); 3931 onoff("DL_Active ERR_COR Signaling Supported", reg, 3932 PCI_DPCCAP_DLACTECORS); 3933 printf(" DPC Control register: 0x%04x\n", ctl); 3934 switch (PCIREG_SHIFTOUT(reg, PCI_DPCCTL_TIRGEN)) { 3935 case 0: 3936 trigstr = "disabled"; 3937 break; 3938 case 1: 3939 trigstr = "enabled(ERR_FATAL)"; 3940 break; 3941 case 2: 3942 trigstr = "enabled(ERR_NONFATAL or ERR_FATAL)"; 3943 break; 3944 default: 3945 trigstr = "(reserverd)"; 3946 break; 3947 } 3948 printf(" DPC Trigger Enable: %s\n", trigstr); 3949 printf(" DPC Completion Control: %s Completion Status\n", 3950 (reg & PCI_DPCCTL_COMPCTL) 3951 ? "Unsupported Request(UR)" : "Completer Abort(CA)"); 3952 onoff("DPC Interrupt Enable", reg, PCI_DPCCTL_IE); 3953 onoff("DPC ERR_COR Enable", reg, PCI_DPCCTL_ERRCOREN); 3954 onoff("Poisoned TLP Egress Blocking Enable", reg, 3955 PCI_DPCCTL_POISONTLPEB); 3956 onoff("DPC Software Trigger", reg, PCI_DPCCTL_SWTRIG); 3957 onoff("DL_Active ERR_COR Enable", reg, PCI_DPCCTL_DLACTECOR); 3958 3959 reg = regs[o2i(extcapoff + PCI_DPC_STATESID)]; 3960 stat = reg & 0xffff; 3961 errsrc = reg >> 16; 3962 printf(" DPC Status register: 0x%04x\n", stat); 3963 onoff("DPC Trigger Status", reg, PCI_DPCSTAT_TSTAT); 3964 switch (PCIREG_SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 3965 case 0: 3966 trigstr = "an unmasked uncorrectable error"; 3967 break; 3968 case 1: 3969 trigstr = "receiving an ERR_NONFATAL"; 3970 break; 3971 case 2: 3972 trigstr = "receiving an ERR_FATAL"; 3973 break; 3974 case 3: 3975 trigstr = "DPC Trigger Reason Extension field"; 3976 break; 3977 } 3978 printf(" DPC Trigger Reason: Due to %s\n", trigstr); 3979 onoff("DPC Interrupt Status", reg, PCI_DPCSTAT_ISTAT); 3980 if (rpext) 3981 onoff("DPC RP Busy", reg, PCI_DPCSTAT_RPBUSY); 3982 switch (PCIREG_SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 3983 case 0: 3984 trigstr = "Due to RP PIO error"; 3985 break; 3986 case 1: 3987 trigstr = "Due to the DPC Software trigger bit"; 3988 break; 3989 default: 3990 trigstr = "(reserved)"; 3991 break; 3992 } 3993 printf(" DPC Trigger Reason Extension: %s\n", trigstr); 3994 if (rpext) 3995 printf(" RP PIO First Error Pointer: 0x%02x\n", 3996 PCIREG_SHIFTOUT(reg, PCI_DPCSTAT_RPPIOFEP)); 3997 printf(" DPC Error Source ID register: 0x%04x\n", errsrc); 3998 3999 if (!rpext) 4000 return; 4001 /* 4002 * All of the following registers are implemented by a device which has 4003 * RP Extensions for DPC 4004 */ 4005 4006 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_STAT)]; 4007 printf(" RP PIO Status Register: 0x%08x\n", reg); 4008 pci_conf_print_dpc_pio(reg); 4009 4010 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_MASK)]; 4011 printf(" RP PIO Mask Register: 0x%08x\n", reg); 4012 pci_conf_print_dpc_pio(reg); 4013 4014 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SEVE)]; 4015 printf(" RP PIO Severity Register: 0x%08x\n", reg); 4016 pci_conf_print_dpc_pio(reg); 4017 4018 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SYSERR)]; 4019 printf(" RP PIO SysError Register: 0x%08x\n", reg); 4020 pci_conf_print_dpc_pio(reg); 4021 4022 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_EXCPT)]; 4023 printf(" RP PIO Exception Register: 0x%08x\n", reg); 4024 pci_conf_print_dpc_pio(reg); 4025 4026 printf(" RP PIO Header Log Register: start from 0x%03x\n", 4027 extcapoff + PCI_DPC_RPPIO_HLOG); 4028 printf(" RP PIO ImpSpec Log Register: start from 0x%03x\n", 4029 extcapoff + PCI_DPC_RPPIO_IMPSLOG); 4030 printf(" RP PIO TLP Prefix Log Register: start from 0x%03x\n", 4031 extcapoff + PCI_DPC_RPPIO_TLPPLOG); 4032 } 4033 4034 4035 static int 4036 pci_conf_l1pm_cap_tposcale(unsigned char scale) 4037 { 4038 4039 /* Return scale in us */ 4040 switch (scale) { 4041 case 0x0: 4042 return 2; 4043 case 0x1: 4044 return 10; 4045 case 0x2: 4046 return 100; 4047 default: 4048 return -1; 4049 } 4050 } 4051 4052 static void 4053 pci_conf_print_l1pm_cap(const pcireg_t *regs, int extcapoff) 4054 { 4055 pcireg_t reg; 4056 int scale, val; 4057 int pcie_capoff; 4058 4059 printf("\n L1 PM Substates\n"); 4060 4061 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 4062 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 4063 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 4064 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 4065 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 4066 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 4067 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 4068 /* The Link Activation Supported bit is only for Downstream Port */ 4069 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 4070 uint32_t t = regs[o2i(pcie_capoff)]; 4071 4072 if ((t == PCIE_XCAP_TYPE_ROOT) || (t == PCIE_XCAP_TYPE_DOWN)) 4073 onoff("Link Activation Supported", reg, 4074 PCI_L1PM_CAP_LA); 4075 } 4076 printf(" Port Common Mode Restore Time: %uus\n", 4077 PCIREG_SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 4078 scale = pci_conf_l1pm_cap_tposcale( 4079 PCIREG_SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 4080 val = PCIREG_SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 4081 printf(" Port T_POWER_ON: "); 4082 if (scale == -1) 4083 printf("unknown\n"); 4084 else 4085 printf("%dus\n", val * scale); 4086 4087 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 4088 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 4089 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 4090 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 4091 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 4092 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 4093 onoff("Link Activation Interrupt Enable", reg, PCI_L1PM_CTL1_LAIE); 4094 onoff("Link Activation Control", reg, PCI_L1PM_CTL1_LA); 4095 printf(" Common Mode Restore Time: %uus\n", 4096 PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 4097 scale = PCI_LTR_SCALETONS(PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 4098 val = PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 4099 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 4100 4101 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 4102 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 4103 scale = pci_conf_l1pm_cap_tposcale( 4104 PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 4105 val = PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 4106 printf(" T_POWER_ON: "); 4107 if (scale == -1) 4108 printf("unknown\n"); 4109 else 4110 printf("%dus\n", val * scale); 4111 4112 if (PCI_EXTCAPLIST_VERSION(regs[o2i(extcapoff)]) >= 2) { 4113 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 4114 printf(" L1 PM Substates Status register: 0x%08x\n", reg); 4115 onoff("Link Activation Status", reg, PCI_L1PM_STAT_LA); 4116 } 4117 } 4118 4119 static void 4120 pci_conf_print_ptm_cap(const pcireg_t *regs, int extcapoff) 4121 { 4122 pcireg_t reg; 4123 uint32_t val; 4124 4125 printf("\n Precision Time Management\n"); 4126 4127 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 4128 printf(" PTM Capability register: 0x%08x\n", reg); 4129 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 4130 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 4131 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 4132 printf(" Local Clock Granularity: "); 4133 val = PCIREG_SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 4134 switch (val) { 4135 case 0: 4136 printf("Not implemented\n"); 4137 break; 4138 case 0xffff: 4139 printf("> 254ns\n"); 4140 break; 4141 default: 4142 printf("%uns\n", val); 4143 break; 4144 } 4145 4146 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 4147 printf(" PTM Control register: 0x%08x\n", reg); 4148 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 4149 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 4150 printf(" Effective Granularity: "); 4151 val = PCIREG_SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 4152 switch (val) { 4153 case 0: 4154 printf("Unknown\n"); 4155 break; 4156 case 0xffff: 4157 printf("> 254ns\n"); 4158 break; 4159 default: 4160 printf("%uns\n", val); 4161 break; 4162 } 4163 } 4164 4165 /* XXX pci_conf_print_mpcie_cap */ 4166 /* XXX pci_conf_print_frsq_cap */ 4167 /* XXX pci_conf_print_rtr_cap */ 4168 /* XXX pci_conf_print_desigvndsp_cap */ 4169 /* XXX pci_conf_print_vf_resizbar_cap */ 4170 4171 static void 4172 pci_conf_print_dlf_cap(const pcireg_t *regs, int extcapoff) 4173 { 4174 pcireg_t reg; 4175 4176 printf("\n Data link Feature Register\n"); 4177 reg = regs[o2i(extcapoff + PCI_DLF_CAP)]; 4178 printf(" Capability register: 0x%08x\n", reg); 4179 onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL); 4180 onoff("DLF Exchange enable", reg, PCI_DLF_CAP_XCHG); 4181 4182 reg = regs[o2i(extcapoff + PCI_DLF_STAT)]; 4183 printf(" Status register: 0x%08x\n", reg); 4184 onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL); 4185 onoff("Remote DLF supported Valid", reg, PCI_DLF_STAT_RMTVALID); 4186 } 4187 4188 /* XXX pci_conf_print_hierarchyid_cap */ 4189 /* XXX pci_conf_print_npem_cap */ 4190 4191 #undef MS 4192 #undef SM 4193 #undef RW 4194 4195 static struct { 4196 pcireg_t cap; 4197 const char *name; 4198 void (*printfunc)(const pcireg_t *, int); 4199 } pci_extcaptab[] = { 4200 { 0, "reserved", 4201 NULL }, 4202 { PCI_EXTCAP_AER, "Advanced Error Reporting", 4203 pci_conf_print_aer_cap }, 4204 { PCI_EXTCAP_VC, "Virtual Channel", 4205 pci_conf_print_vc_cap }, 4206 { PCI_EXTCAP_SERNUM, "Device Serial Number", 4207 pci_conf_print_sernum_cap }, 4208 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 4209 pci_conf_print_pwrbdgt_cap }, 4210 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 4211 pci_conf_print_rclink_dcl_cap }, 4212 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 4213 NULL }, 4214 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 4215 pci_conf_print_rcec_assoc_cap }, 4216 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 4217 NULL }, 4218 { PCI_EXTCAP_VC2, "Virtual Channel", 4219 NULL }, 4220 { PCI_EXTCAP_RCRB, "RCRB Header", 4221 NULL }, 4222 { PCI_EXTCAP_VENDOR, "Vendor Unique", 4223 NULL }, 4224 { PCI_EXTCAP_CAC, "Configuration Access Correction", 4225 NULL }, 4226 { PCI_EXTCAP_ACS, "Access Control Services", 4227 pci_conf_print_acs_cap }, 4228 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 4229 pci_conf_print_ari_cap }, 4230 { PCI_EXTCAP_ATS, "Address Translation Services", 4231 pci_conf_print_ats_cap }, 4232 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 4233 pci_conf_print_sriov_cap }, 4234 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 4235 NULL }, 4236 { PCI_EXTCAP_MCAST, "Multicast", 4237 pci_conf_print_multicast_cap }, 4238 { PCI_EXTCAP_PAGE_REQ, "Page Request", 4239 pci_conf_print_page_req_cap }, 4240 { PCI_EXTCAP_AMD, "Reserved for AMD", 4241 NULL }, 4242 { PCI_EXTCAP_RESIZBAR, "Resizable BAR", 4243 pci_conf_print_resizbar_cap }, 4244 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 4245 pci_conf_print_dpa_cap }, 4246 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 4247 pci_conf_print_tph_req_cap }, 4248 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 4249 pci_conf_print_ltr_cap }, 4250 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 4251 pci_conf_print_sec_pcie_cap }, 4252 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 4253 NULL }, 4254 { PCI_EXTCAP_PASID, "Process Address Space ID", 4255 pci_conf_print_pasid_cap }, 4256 { PCI_EXTCAP_LNR, "LN Requester", 4257 pci_conf_print_lnr_cap }, 4258 { PCI_EXTCAP_DPC, "Downstream Port Containment", 4259 pci_conf_print_dpc_cap }, 4260 { PCI_EXTCAP_L1PM, "L1 PM Substates", 4261 pci_conf_print_l1pm_cap }, 4262 { PCI_EXTCAP_PTM, "Precision Time Management", 4263 pci_conf_print_ptm_cap }, 4264 { PCI_EXTCAP_MPCIE, "M-PCIe", 4265 NULL }, 4266 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 4267 NULL }, 4268 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 4269 NULL }, 4270 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 4271 NULL }, 4272 { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", 4273 NULL }, 4274 { PCI_EXTCAP_DLF, "Data link Feature", pci_conf_print_dlf_cap }, 4275 { PCI_EXTCAP_PYSLAY_16GT, "Physical Layer 16.0 GT/s", NULL }, 4276 { 0x27, "unknown", NULL }, 4277 { PCI_EXTCAP_HIERARCHYID, "Hierarchy ID", 4278 NULL }, 4279 { PCI_EXTCAP_NPEM, "Native PCIe Enclosure Management", 4280 NULL }, 4281 }; 4282 4283 static int 4284 pci_conf_find_extcap(const pcireg_t *regs, unsigned int capid, int *offsetp) 4285 { 4286 int off; 4287 pcireg_t rval; 4288 4289 for (off = PCI_EXTCAPLIST_BASE; 4290 off != 0; 4291 off = PCI_EXTCAPLIST_NEXT(rval)) { 4292 rval = regs[o2i(off)]; 4293 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 4294 if (offsetp != NULL) 4295 *offsetp = off; 4296 return 1; 4297 } 4298 } 4299 return 0; 4300 } 4301 4302 static void 4303 pci_conf_print_extcaplist( 4304 #ifdef _KERNEL 4305 pci_chipset_tag_t pc, pcitag_t tag, 4306 #endif 4307 const pcireg_t *regs) 4308 { 4309 int off; 4310 pcireg_t foundcap; 4311 pcireg_t rval; 4312 bool foundtable[__arraycount(pci_extcaptab)]; 4313 unsigned int i; 4314 4315 /* Check Extended capability structure */ 4316 off = PCI_EXTCAPLIST_BASE; 4317 rval = regs[o2i(off)]; 4318 if (rval == 0xffffffff || rval == 0) 4319 return; 4320 4321 /* Clear table */ 4322 for (i = 0; i < __arraycount(pci_extcaptab); i++) 4323 foundtable[i] = false; 4324 4325 /* Print extended capability register's offset and the type first */ 4326 for (;;) { 4327 printf(" Extended Capability Register at 0x%02x\n", off); 4328 4329 foundcap = PCI_EXTCAPLIST_CAP(rval); 4330 printf(" type: 0x%04x (", foundcap); 4331 if (foundcap < __arraycount(pci_extcaptab)) { 4332 printf("%s)\n", pci_extcaptab[foundcap].name); 4333 /* Mark as found */ 4334 foundtable[foundcap] = true; 4335 } else 4336 printf("unknown)\n"); 4337 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 4338 4339 off = PCI_EXTCAPLIST_NEXT(rval); 4340 if (off == 0) 4341 break; 4342 else if (off <= PCI_CONF_SIZE) { 4343 printf(" next pointer: 0x%03x (incorrect)\n", off); 4344 return; 4345 } 4346 rval = regs[o2i(off)]; 4347 } 4348 4349 /* 4350 * And then, print the detail of each capability registers 4351 * in capability value's order. 4352 */ 4353 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 4354 if (foundtable[i] == false) 4355 continue; 4356 4357 /* 4358 * The type was found. Search capability list again and 4359 * print all capabilities that the capabiliy type is 4360 * the same. 4361 */ 4362 if (pci_conf_find_extcap(regs, i, &off) == 0) 4363 continue; 4364 rval = regs[o2i(off)]; 4365 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 4366 || (pci_extcaptab[i].printfunc == NULL)) 4367 continue; 4368 4369 pci_extcaptab[i].printfunc(regs, off); 4370 4371 } 4372 } 4373 4374 /* Print the Secondary Status Register. */ 4375 static void 4376 pci_conf_print_ssr(pcireg_t rval) 4377 { 4378 pcireg_t devsel; 4379 4380 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 4381 onoff("66 MHz capable", rval, __BIT(5)); 4382 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 4383 onoff("Fast back-to-back capable", rval, __BIT(7)); 4384 onoff("Data parity error detected", rval, __BIT(8)); 4385 4386 printf(" DEVSEL timing: "); 4387 devsel = PCIREG_SHIFTOUT(rval, __BITS(10, 9)); 4388 switch (devsel) { 4389 case 0: 4390 printf("fast"); 4391 break; 4392 case 1: 4393 printf("medium"); 4394 break; 4395 case 2: 4396 printf("slow"); 4397 break; 4398 default: 4399 printf("unknown/reserved"); /* XXX */ 4400 break; 4401 } 4402 printf(" (0x%x)\n", devsel); 4403 4404 onoff("Signalled target abort", rval, __BIT(11)); 4405 onoff("Received target abort", rval, __BIT(12)); 4406 onoff("Received master abort", rval, __BIT(13)); 4407 onoff("Received system error", rval, __BIT(14)); 4408 onoff("Detected parity error", rval, __BIT(15)); 4409 } 4410 4411 static void 4412 pci_conf_print_type0( 4413 #ifdef _KERNEL 4414 pci_chipset_tag_t pc, pcitag_t tag, 4415 #endif 4416 const pcireg_t *regs) 4417 { 4418 int off, width; 4419 pcireg_t rval; 4420 const char *str; 4421 4422 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 4423 #ifdef _KERNEL 4424 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4425 #else 4426 width = pci_conf_print_bar(regs, off, NULL); 4427 #endif 4428 } 4429 4430 printf(" Cardbus CIS Pointer: 0x%08x\n", 4431 regs[o2i(PCI_CARDBUS_CIS_REG)]); 4432 4433 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 4434 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4435 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4436 4437 rval = regs[o2i(PCI_MAPREG_ROM)]; 4438 printf(" Expansion ROM Base Address Register: 0x%08x\n", rval); 4439 printf(" base: 0x%08x\n", (uint32_t)PCI_MAPREG_ROM_ADDR(rval)); 4440 onoff("Expansion ROM Enable", rval, PCI_MAPREG_ROM_ENABLE); 4441 printf(" Validation Status: "); 4442 switch (PCIREG_SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_STAT)) { 4443 case PCI_MAPREG_ROM_VSTAT_NOTSUPP: 4444 str = "Validation not supported"; 4445 break; 4446 case PCI_MAPREG_ROM_VSTAT_INPROG: 4447 str = "Validation in Progress"; 4448 break; 4449 case PCI_MAPREG_ROM_VSTAT_VPASS: 4450 str = "Validation Pass. " 4451 "Valid contents, trust test was not performed"; 4452 break; 4453 case PCI_MAPREG_ROM_VSTAT_VPASSTRUST: 4454 str = "Validation Pass. Valid and trusted contents"; 4455 break; 4456 case PCI_MAPREG_ROM_VSTAT_VFAIL: 4457 str = "Validation Fail. Invalid contents"; 4458 break; 4459 case PCI_MAPREG_ROM_VSTAT_VFAILUNTRUST: 4460 str = "Validation Fail. Valid but untrusted contents"; 4461 break; 4462 case PCI_MAPREG_ROM_VSTAT_WPASS: 4463 str = "Warning Pass. Validation passed with warning. " 4464 "Valid contents, trust test was not performed"; 4465 break; 4466 case PCI_MAPREG_ROM_VSTAT_WPASSTRUST: 4467 str = "Warning Pass. Validation passed with warning. " 4468 "Valid and trusted contents"; 4469 break; 4470 } 4471 printf("%s\n", str); 4472 printf(" Validation Details: 0x%x\n", 4473 PCIREG_SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_DETAIL)); 4474 4475 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4476 printf(" Capability list pointer: 0x%02x\n", 4477 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4478 else 4479 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4480 4481 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 4482 4483 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4484 printf(" Maximum Latency: 0x%02x\n", PCI_MAX_LAT(rval)); 4485 printf(" Minimum Grant: 0x%02x\n", PCI_MIN_GNT(rval)); 4486 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 4487 switch (PCI_INTERRUPT_PIN(rval)) { 4488 case PCI_INTERRUPT_PIN_NONE: 4489 printf("(none)"); 4490 break; 4491 case PCI_INTERRUPT_PIN_A: 4492 printf("(pin A)"); 4493 break; 4494 case PCI_INTERRUPT_PIN_B: 4495 printf("(pin B)"); 4496 break; 4497 case PCI_INTERRUPT_PIN_C: 4498 printf("(pin C)"); 4499 break; 4500 case PCI_INTERRUPT_PIN_D: 4501 printf("(pin D)"); 4502 break; 4503 default: 4504 printf("(? ? ?)"); 4505 break; 4506 } 4507 printf("\n"); 4508 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 4509 } 4510 4511 static void 4512 pci_conf_print_type1( 4513 #ifdef _KERNEL 4514 pci_chipset_tag_t pc, pcitag_t tag, 4515 #endif 4516 const pcireg_t *regs) 4517 { 4518 int off, width; 4519 pcireg_t rval, csreg; 4520 uint32_t base, limit; 4521 uint32_t base_h, limit_h; 4522 uint64_t pbase, plimit; 4523 int use_upper; 4524 4525 /* 4526 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 4527 * Bridge chip documentation, and may not be correct with 4528 * respect to various standards. (XXX) 4529 */ 4530 4531 for (off = 0x10; off < 0x18; off += width) { 4532 #ifdef _KERNEL 4533 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4534 #else 4535 width = pci_conf_print_bar(regs, off, NULL); 4536 #endif 4537 } 4538 4539 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4540 printf(" Primary bus number: 0x%02x\n", 4541 PCI_BRIDGE_BUS_NUM_PRIMARY(rval)); 4542 printf(" Secondary bus number: 0x%02x\n", 4543 PCI_BRIDGE_BUS_NUM_SECONDARY(rval)); 4544 printf(" Subordinate bus number: 0x%02x\n", 4545 PCI_BRIDGE_BUS_NUM_SUBORDINATE(rval)); 4546 printf(" Secondary bus latency timer: 0x%02x\n", 4547 PCI_BRIDGE_BUS_SEC_LATTIMER_VAL(rval)); 4548 4549 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 4550 pci_conf_print_ssr(PCIREG_SHIFTOUT(rval, __BITS(31, 16))); 4551 4552 /* I/O region */ 4553 printf(" I/O region:\n"); 4554 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 4555 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 4556 if (PCI_BRIDGE_IO_32BITS(rval)) 4557 use_upper = 1; 4558 else 4559 use_upper = 0; 4560 onoff("32bit I/O", rval, use_upper); 4561 base = PCI_BRIDGE_STATIO_IOBASE_ADDR(rval); 4562 limit = PCI_BRIDGE_STATIO_IOLIMIT_ADDR(rval); 4563 4564 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 4565 base_h = PCIREG_SHIFTOUT(rval, PCI_BRIDGE_IOHIGH_BASE); 4566 limit_h = PCIREG_SHIFTOUT(rval, PCI_BRIDGE_IOHIGH_LIMIT); 4567 printf(" base upper 16 bits register: 0x%04x\n", base_h); 4568 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 4569 4570 if (use_upper == 1) { 4571 base |= base_h << 16; 4572 limit |= limit_h << 16; 4573 } 4574 if (base < limit) { 4575 if (use_upper == 1) 4576 printf(" range: 0x%08x-0x%08x\n", base, limit); 4577 else 4578 printf(" range: 0x%04x-0x%04x\n", base, limit); 4579 } else 4580 printf(" range: not set\n"); 4581 4582 /* Non-prefetchable memory region */ 4583 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 4584 printf(" Memory region:\n"); 4585 printf(" base register: 0x%04hx\n", 4586 (uint16_t)PCIREG_SHIFTOUT(rval, PCI_BRIDGE_MEMORY_BASE)); 4587 printf(" limit register: 0x%04hx\n", 4588 (uint16_t)PCIREG_SHIFTOUT(rval, PCI_BRIDGE_MEMORY_LIMIT)); 4589 base = PCI_BRIDGE_MEMORY_BASE_ADDR(rval); 4590 limit = PCI_BRIDGE_MEMORY_LIMIT_ADDR(rval); 4591 if (base < limit) 4592 printf(" range: 0x%08x-0x%08x\n", base, limit); 4593 else 4594 printf(" range: not set\n"); 4595 4596 /* Prefetchable memory region */ 4597 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 4598 printf(" Prefetchable memory region:\n"); 4599 printf(" base register: 0x%04x\n", 4600 (rval >> 0) & 0xffff); 4601 printf(" limit register: 0x%04x\n", 4602 (rval >> 16) & 0xffff); 4603 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASEUP32_REG)]; 4604 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMITUP32_REG)]; 4605 printf(" base upper 32 bits register: 0x%08x\n", 4606 base_h); 4607 printf(" limit upper 32 bits register: 0x%08x\n", 4608 limit_h); 4609 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 4610 use_upper = 1; 4611 else 4612 use_upper = 0; 4613 onoff("64bit memory address", rval, use_upper); 4614 pbase = PCI_BRIDGE_PREFETCHMEM_BASE_ADDR(rval); 4615 plimit = PCI_BRIDGE_PREFETCHMEM_LIMIT_ADDR(rval); 4616 if (use_upper == 1) { 4617 pbase |= (uint64_t)base_h << 32; 4618 plimit |= (uint64_t)limit_h << 32; 4619 } 4620 if (pbase < plimit) { 4621 if (use_upper == 1) 4622 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 4623 "\n", pbase, plimit); 4624 else 4625 printf(" range: 0x%08x-0x%08x\n", 4626 (uint32_t)pbase, (uint32_t)plimit); 4627 } else 4628 printf(" range: not set\n"); 4629 4630 csreg = regs[o2i(PCI_COMMAND_STATUS_REG)]; 4631 if (csreg & PCI_STATUS_CAPLIST_SUPPORT) 4632 printf(" Capability list pointer: 0x%02x\n", 4633 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4634 else 4635 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4636 4637 printf(" Expansion ROM Base Address: 0x%08x\n", 4638 regs[o2i(PCI_BRIDGE_EXPROMADDR_REG)]); 4639 4640 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4641 printf(" Interrupt line: 0x%02x\n", 4642 (rval >> 0) & 0xff); 4643 printf(" Interrupt pin: 0x%02x ", 4644 (rval >> 8) & 0xff); 4645 switch ((rval >> 8) & 0xff) { 4646 case PCI_INTERRUPT_PIN_NONE: 4647 printf("(none)"); 4648 break; 4649 case PCI_INTERRUPT_PIN_A: 4650 printf("(pin A)"); 4651 break; 4652 case PCI_INTERRUPT_PIN_B: 4653 printf("(pin B)"); 4654 break; 4655 case PCI_INTERRUPT_PIN_C: 4656 printf("(pin C)"); 4657 break; 4658 case PCI_INTERRUPT_PIN_D: 4659 printf("(pin D)"); 4660 break; 4661 default: 4662 printf("(? ? ?)"); 4663 break; 4664 } 4665 printf("\n"); 4666 rval = regs[o2i(PCI_BRIDGE_CONTROL_REG)]; 4667 printf(" Bridge control register: 0x%04hx\n", 4668 (uint16_t)PCIREG_SHIFTOUT(rval, PCI_BRIDGE_CONTROL)); 4669 onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE); 4670 onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR); 4671 onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA); 4672 onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA); 4673 /* 4674 * VGA 16bit decode bit has meaning if the VGA enable bit or the 4675 * VGA Palette Snoop Enable bit is set. 4676 */ 4677 if (((rval & PCI_BRIDGE_CONTROL_VGA) != 0) 4678 || ((csreg & PCI_COMMAND_PALETTE_ENABLE) != 0)) 4679 onoff("VGA 16bit enable", rval, PCI_BRIDGE_CONTROL_VGA16); 4680 onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT); 4681 onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR); 4682 onoff("Fast back-to-back enable", rval, PCI_BRIDGE_CONTROL_SECFASTB2B); 4683 onoff("Primary Discard Timer", rval, 4684 PCI_BRIDGE_CONTROL_PRI_DISC_TIMER); 4685 onoff("Secondary Discard Timer", 4686 rval, PCI_BRIDGE_CONTROL_SEC_DISC_TIMER); 4687 onoff("Discard Timer Status", rval, 4688 PCI_BRIDGE_CONTROL_DISC_TIMER_STAT); 4689 onoff("Discard Timer SERR# Enable", rval, 4690 PCI_BRIDGE_CONTROL_DISC_TIMER_SERR); 4691 } 4692 4693 static void 4694 pci_conf_print_type2( 4695 #ifdef _KERNEL 4696 pci_chipset_tag_t pc, pcitag_t tag, 4697 #endif 4698 const pcireg_t *regs) 4699 { 4700 pcireg_t rval; 4701 4702 /* 4703 * XXX these need to be printed in more detail, need to be 4704 * XXX checked against specs/docs, etc. 4705 * 4706 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 4707 * controller chip documentation, and may not be correct with 4708 * respect to various standards. (XXX) 4709 */ 4710 4711 #ifdef _KERNEL 4712 pci_conf_print_bar(pc, tag, regs, 0x10, 4713 "CardBus socket/ExCA registers"); 4714 #else 4715 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 4716 #endif 4717 4718 /* Capability list pointer and secondary status register */ 4719 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 4720 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4721 printf(" Capability list pointer: 0x%02x\n", 4722 PCI_CAPLIST_PTR(rval)); 4723 else 4724 printf(" Reserved @ 0x14: 0x%04x\n", 4725 PCIREG_SHIFTOUT(rval, __BITS(15, 0))); 4726 pci_conf_print_ssr(PCIREG_SHIFTOUT(rval, __BITS(31, 16))); 4727 4728 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4729 printf(" PCI bus number: 0x%02x\n", 4730 (rval >> 0) & 0xff); 4731 printf(" CardBus bus number: 0x%02x\n", 4732 (rval >> 8) & 0xff); 4733 printf(" Subordinate bus number: 0x%02x\n", 4734 (rval >> 16) & 0xff); 4735 printf(" CardBus latency timer: 0x%02x\n", 4736 (rval >> 24) & 0xff); 4737 4738 /* XXX Print more prettily */ 4739 printf(" CardBus memory region 0:\n"); 4740 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 4741 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 4742 printf(" CardBus memory region 1:\n"); 4743 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 4744 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 4745 printf(" CardBus I/O region 0:\n"); 4746 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 4747 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 4748 printf(" CardBus I/O region 1:\n"); 4749 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 4750 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 4751 4752 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4753 printf(" Interrupt line: 0x%02x\n", 4754 (rval >> 0) & 0xff); 4755 printf(" Interrupt pin: 0x%02x ", 4756 (rval >> 8) & 0xff); 4757 switch ((rval >> 8) & 0xff) { 4758 case PCI_INTERRUPT_PIN_NONE: 4759 printf("(none)"); 4760 break; 4761 case PCI_INTERRUPT_PIN_A: 4762 printf("(pin A)"); 4763 break; 4764 case PCI_INTERRUPT_PIN_B: 4765 printf("(pin B)"); 4766 break; 4767 case PCI_INTERRUPT_PIN_C: 4768 printf("(pin C)"); 4769 break; 4770 case PCI_INTERRUPT_PIN_D: 4771 printf("(pin D)"); 4772 break; 4773 default: 4774 printf("(? ? ?)"); 4775 break; 4776 } 4777 printf("\n"); 4778 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> 16) & 0xffff; 4779 printf(" Bridge control register: 0x%04x\n", rval); 4780 onoff("Parity error response", rval, __BIT(0)); 4781 onoff("SERR# enable", rval, __BIT(1)); 4782 onoff("ISA enable", rval, __BIT(2)); 4783 onoff("VGA enable", rval, __BIT(3)); 4784 onoff("Master abort mode", rval, __BIT(5)); 4785 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 4786 onoff("Functional interrupts routed by ExCA registers", rval, 4787 __BIT(7)); 4788 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 4789 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 4790 onoff("Write posting enable", rval, __BIT(10)); 4791 4792 rval = regs[o2i(0x40)]; 4793 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4794 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4795 4796 #ifdef _KERNEL 4797 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers"); 4798 #else 4799 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 4800 #endif 4801 } 4802 4803 void 4804 pci_conf_print( 4805 #ifdef _KERNEL 4806 pci_chipset_tag_t pc, pcitag_t tag, 4807 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 4808 #else 4809 int pcifd, u_int bus, u_int dev, u_int func 4810 #endif 4811 ) 4812 { 4813 pcireg_t regs[o2i(PCI_EXTCONF_SIZE)]; 4814 int off, capoff, endoff, hdrtype; 4815 const char *type_name; 4816 #ifdef _KERNEL 4817 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 4818 #else 4819 void (*type_printfn)(const pcireg_t *); 4820 #endif 4821 4822 printf("PCI configuration registers:\n"); 4823 4824 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 4825 #ifdef _KERNEL 4826 regs[o2i(off)] = pci_conf_read(pc, tag, off); 4827 #else 4828 if (pcibus_conf_read(pcifd, bus, dev, func, off, 4829 ®s[o2i(off)]) == -1) 4830 regs[o2i(off)] = 0; 4831 #endif 4832 } 4833 4834 /* common header */ 4835 printf(" Common header:\n"); 4836 pci_conf_print_regs(regs, 0, 16); 4837 4838 printf("\n"); 4839 #ifdef _KERNEL 4840 pci_conf_print_common(pc, tag, regs); 4841 #else 4842 pci_conf_print_common(regs); 4843 #endif 4844 printf("\n"); 4845 4846 /* type-dependent header */ 4847 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 4848 switch (hdrtype) { /* XXX make a table, eventually */ 4849 case 0: 4850 /* Standard device header */ 4851 type_name = "\"normal\" device"; 4852 type_printfn = &pci_conf_print_type0; 4853 capoff = PCI_CAPLISTPTR_REG; 4854 endoff = 64; 4855 break; 4856 case 1: 4857 /* PCI-PCI bridge header */ 4858 type_name = "PCI-PCI bridge"; 4859 type_printfn = &pci_conf_print_type1; 4860 capoff = PCI_CAPLISTPTR_REG; 4861 endoff = 64; 4862 break; 4863 case 2: 4864 /* PCI-CardBus bridge header */ 4865 type_name = "PCI-CardBus bridge"; 4866 type_printfn = &pci_conf_print_type2; 4867 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 4868 endoff = 72; 4869 break; 4870 default: 4871 type_name = NULL; 4872 type_printfn = 0; 4873 capoff = -1; 4874 endoff = 64; 4875 break; 4876 } 4877 printf(" Type %d ", hdrtype); 4878 if (type_name != NULL) 4879 printf("(%s) ", type_name); 4880 printf("header:\n"); 4881 pci_conf_print_regs(regs, 16, endoff); 4882 printf("\n"); 4883 if (type_printfn) { 4884 #ifdef _KERNEL 4885 (*type_printfn)(pc, tag, regs); 4886 #else 4887 (*type_printfn)(regs); 4888 #endif 4889 } else 4890 printf(" Don't know how to pretty-print type %d header.\n", 4891 hdrtype); 4892 printf("\n"); 4893 4894 /* capability list, if present */ 4895 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4896 && (capoff > 0)) { 4897 #ifdef _KERNEL 4898 pci_conf_print_caplist(pc, tag, regs, capoff); 4899 #else 4900 pci_conf_print_caplist(regs, capoff); 4901 #endif 4902 printf("\n"); 4903 } 4904 4905 /* device-dependent header */ 4906 printf(" Device-dependent header:\n"); 4907 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 4908 #ifdef _KERNEL 4909 printf("\n"); 4910 if (printfn) 4911 (*printfn)(pc, tag, regs); 4912 else 4913 printf(" Don't know how to pretty-print device-dependent header.\n"); 4914 #endif /* _KERNEL */ 4915 4916 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 4917 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 4918 return; 4919 4920 printf("\n"); 4921 #ifdef _KERNEL 4922 pci_conf_print_extcaplist(pc, tag, regs); 4923 #else 4924 pci_conf_print_extcaplist(regs); 4925 #endif 4926 printf("\n"); 4927 4928 /* Extended Configuration Space, if present */ 4929 printf(" Extended Configuration Space:\n"); 4930 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 4931 } 4932
Indexes created Tue Sep 30 11:09:46 GMT 2025