pci_subr.c revision 1.215.2.4
1 /* $NetBSD: pci_subr.c,v 1.215.2.4 2020/07/26 10:46:14 martin Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.215.2.4 2020/07/26 10:46:14 martin Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #include <sys/kmem.h> 56 57 #define MALLOC(sz) kmem_alloc(sz, KM_SLEEP) 58 #define FREE(p, sz) kmem_free(p, sz) 59 60 #else 61 #include <pci.h> 62 #include <stdarg.h> 63 #include <stdbool.h> 64 #include <stdio.h> 65 #include <stdlib.h> 66 #include <string.h> 67 68 #define MALLOC(sz) malloc(sz) 69 #define FREE(p, sz) free(p) 70 71 #endif 72 73 #include <dev/pci/pcireg.h> 74 #ifdef _KERNEL 75 #include <dev/pci/pcivar.h> 76 #else 77 #include <dev/pci/pci_verbose.h> 78 #include <dev/pci/pcidevs.h> 79 #include <dev/pci/pcidevs_data.h> 80 #endif 81 82 static int pci_conf_find_cap(const pcireg_t *, unsigned int, int *); 83 static int pci_conf_find_extcap(const pcireg_t *, unsigned int, int *); 84 static void pci_conf_print_pcie_power(uint8_t, unsigned int); 85 86 /* 87 * Descriptions of known PCI classes and subclasses. 88 * 89 * Subclasses are described in the same way as classes, but have a 90 * NULL subclass pointer. 91 */ 92 struct pci_class { 93 const char *name; 94 u_int val; /* as wide as pci_{,sub}class_t */ 95 const struct pci_class *subclasses; 96 }; 97 98 /* 99 * Class 0x00. 100 * Before rev. 2.0. 101 */ 102 static const struct pci_class pci_subclass_prehistoric[] = { 103 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 104 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 105 { NULL, 0, NULL, }, 106 }; 107 108 /* 109 * Class 0x01. 110 * Mass storage controller 111 */ 112 113 /* ATA programming interface */ 114 static const struct pci_class pci_interface_ata[] = { 115 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 116 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 117 { NULL, 0, NULL, }, 118 }; 119 120 /* SATA programming interface */ 121 static const struct pci_class pci_interface_sata[] = { 122 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 123 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 124 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 125 { NULL, 0, NULL, }, 126 }; 127 128 /* Flash programming interface */ 129 static const struct pci_class pci_interface_nvm[] = { 130 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 131 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 132 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 133 { NULL, 0, NULL, }, 134 }; 135 136 /* Subclasses */ 137 static const struct pci_class pci_subclass_mass_storage[] = { 138 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 139 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 140 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 141 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 142 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 143 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 144 pci_interface_ata, }, 145 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 146 pci_interface_sata, }, 147 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 148 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 149 pci_interface_nvm, }, 150 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 151 { NULL, 0, NULL, }, 152 }; 153 154 /* 155 * Class 0x02. 156 * Network controller. 157 */ 158 static const struct pci_class pci_subclass_network[] = { 159 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 160 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 161 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 162 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 163 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 164 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 165 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 166 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 167 { NULL, 0, NULL, }, 168 }; 169 170 /* 171 * Class 0x03. 172 * Display controller. 173 */ 174 175 /* VGA programming interface */ 176 static const struct pci_class pci_interface_vga[] = { 177 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 178 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 179 { NULL, 0, NULL, }, 180 }; 181 /* Subclasses */ 182 static const struct pci_class pci_subclass_display[] = { 183 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 184 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 185 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 186 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 187 { NULL, 0, NULL, }, 188 }; 189 190 /* 191 * Class 0x04. 192 * Multimedia device. 193 */ 194 static const struct pci_class pci_subclass_multimedia[] = { 195 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 196 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 197 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 198 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 199 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 200 { NULL, 0, NULL, }, 201 }; 202 203 /* 204 * Class 0x05. 205 * Memory controller. 206 */ 207 static const struct pci_class pci_subclass_memory[] = { 208 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 209 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 210 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 211 { NULL, 0, NULL, }, 212 }; 213 214 /* 215 * Class 0x06. 216 * Bridge device. 217 */ 218 219 /* PCI bridge programming interface */ 220 static const struct pci_class pci_interface_pcibridge[] = { 221 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 222 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 223 { NULL, 0, NULL, }, 224 }; 225 226 /* Semi-transparent PCI-to-PCI bridge programming interface */ 227 static const struct pci_class pci_interface_stpci[] = { 228 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 229 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 230 { NULL, 0, NULL, }, 231 }; 232 233 /* Advanced Switching programming interface */ 234 static const struct pci_class pci_interface_advsw[] = { 235 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 236 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 237 { NULL, 0, NULL, }, 238 }; 239 240 /* Subclasses */ 241 static const struct pci_class pci_subclass_bridge[] = { 242 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 243 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 244 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 245 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 246 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 247 pci_interface_pcibridge, }, 248 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 249 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 250 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 251 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 252 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 253 pci_interface_stpci, }, 254 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 255 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 256 pci_interface_advsw, }, 257 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 258 { NULL, 0, NULL, }, 259 }; 260 261 /* 262 * Class 0x07. 263 * Simple communications controller. 264 */ 265 266 /* Serial controller programming interface */ 267 static const struct pci_class pci_interface_serial[] = { 268 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 269 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 270 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 271 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 272 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 273 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 274 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 275 { NULL, 0, NULL, }, 276 }; 277 278 /* Parallel controller programming interface */ 279 static const struct pci_class pci_interface_parallel[] = { 280 { "", PCI_INTERFACE_PARALLEL, NULL,}, 281 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 282 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 283 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 284 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 285 { NULL, 0, NULL,}, 286 }; 287 288 /* Modem programming interface */ 289 static const struct pci_class pci_interface_modem[] = { 290 { "", PCI_INTERFACE_MODEM, NULL,}, 291 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 292 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 293 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 294 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 295 { NULL, 0, NULL,}, 296 }; 297 298 /* Subclasses */ 299 static const struct pci_class pci_subclass_communications[] = { 300 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 301 pci_interface_serial, }, 302 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 303 pci_interface_parallel, }, 304 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 305 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 306 pci_interface_modem, }, 307 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 308 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 309 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 310 { NULL, 0, NULL,}, 311 }; 312 313 /* 314 * Class 0x08. 315 * Base system peripheral. 316 */ 317 318 /* PIC programming interface */ 319 static const struct pci_class pci_interface_pic[] = { 320 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 321 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 322 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 323 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 324 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 325 { NULL, 0, NULL, }, 326 }; 327 328 /* DMA programming interface */ 329 static const struct pci_class pci_interface_dma[] = { 330 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 331 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 332 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 333 { NULL, 0, NULL, }, 334 }; 335 336 /* Timer programming interface */ 337 static const struct pci_class pci_interface_tmr[] = { 338 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 339 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 340 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 341 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 342 { NULL, 0, NULL, }, 343 }; 344 345 /* RTC programming interface */ 346 static const struct pci_class pci_interface_rtc[] = { 347 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 348 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 349 { NULL, 0, NULL, }, 350 }; 351 352 /* Subclasses */ 353 static const struct pci_class pci_subclass_system[] = { 354 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 355 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 356 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 357 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 358 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 359 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 360 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 361 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 362 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 363 { NULL, 0, NULL, }, 364 }; 365 366 /* 367 * Class 0x09. 368 * Input device. 369 */ 370 371 /* Gameport programming interface */ 372 static const struct pci_class pci_interface_game[] = { 373 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 374 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 375 { NULL, 0, NULL, }, 376 }; 377 378 /* Subclasses */ 379 static const struct pci_class pci_subclass_input[] = { 380 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 381 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 382 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 383 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 384 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 385 pci_interface_game, }, 386 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 387 { NULL, 0, NULL, }, 388 }; 389 390 /* 391 * Class 0x0a. 392 * Docking station. 393 */ 394 static const struct pci_class pci_subclass_dock[] = { 395 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 396 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 397 { NULL, 0, NULL, }, 398 }; 399 400 /* 401 * Class 0x0b. 402 * Processor. 403 */ 404 static const struct pci_class pci_subclass_processor[] = { 405 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 406 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 407 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 408 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 409 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 410 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 411 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 412 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 413 { NULL, 0, NULL, }, 414 }; 415 416 /* 417 * Class 0x0c. 418 * Serial bus controller. 419 */ 420 421 /* IEEE1394 programming interface */ 422 static const struct pci_class pci_interface_ieee1394[] = { 423 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 424 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 425 { NULL, 0, NULL,}, 426 }; 427 428 /* USB programming interface */ 429 static const struct pci_class pci_interface_usb[] = { 430 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 431 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 432 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 433 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 434 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 435 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 436 { NULL, 0, NULL, }, 437 }; 438 439 /* IPMI programming interface */ 440 static const struct pci_class pci_interface_ipmi[] = { 441 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL, }, 442 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL, }, 443 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL, }, 444 { NULL, 0, NULL, }, 445 }; 446 447 /* Subclasses */ 448 static const struct pci_class pci_subclass_serialbus[] = { 449 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 450 pci_interface_ieee1394, }, 451 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 452 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 453 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 454 pci_interface_usb, }, 455 /* XXX Fiber Channel/_FIBRECHANNEL */ 456 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 457 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 458 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 459 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 460 pci_interface_ipmi, }, 461 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 462 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 463 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 464 { NULL, 0, NULL, }, 465 }; 466 467 /* 468 * Class 0x0d. 469 * Wireless Controller. 470 */ 471 static const struct pci_class pci_subclass_wireless[] = { 472 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 473 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 474 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 475 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 476 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 477 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 478 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 479 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 480 { NULL, 0, NULL, }, 481 }; 482 483 /* 484 * Class 0x0e. 485 * Intelligent IO controller. 486 */ 487 488 /* Intelligent IO programming interface */ 489 static const struct pci_class pci_interface_i2o[] = { 490 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL, }, 491 { NULL, 0, NULL, }, 492 }; 493 494 /* Subclasses */ 495 static const struct pci_class pci_subclass_i2o[] = { 496 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 497 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 498 { NULL, 0, NULL, }, 499 }; 500 501 /* 502 * Class 0x0f. 503 * Satellite communication controller. 504 */ 505 static const struct pci_class pci_subclass_satcom[] = { 506 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 507 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 508 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 509 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 510 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 511 { NULL, 0, NULL, }, 512 }; 513 514 /* 515 * Class 0x10. 516 * Encryption/Decryption controller. 517 */ 518 static const struct pci_class pci_subclass_crypto[] = { 519 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 520 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 521 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 522 { NULL, 0, NULL, }, 523 }; 524 525 /* 526 * Class 0x11. 527 * Data aquuisition and signal processing controller. 528 */ 529 static const struct pci_class pci_subclass_dasp[] = { 530 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 531 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 532 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 533 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 534 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 535 { NULL, 0, NULL, }, 536 }; 537 538 /* List of classes */ 539 static const struct pci_class pci_classes[] = { 540 { "prehistoric", PCI_CLASS_PREHISTORIC, 541 pci_subclass_prehistoric, }, 542 { "mass storage", PCI_CLASS_MASS_STORAGE, 543 pci_subclass_mass_storage, }, 544 { "network", PCI_CLASS_NETWORK, 545 pci_subclass_network, }, 546 { "display", PCI_CLASS_DISPLAY, 547 pci_subclass_display, }, 548 { "multimedia", PCI_CLASS_MULTIMEDIA, 549 pci_subclass_multimedia, }, 550 { "memory", PCI_CLASS_MEMORY, 551 pci_subclass_memory, }, 552 { "bridge", PCI_CLASS_BRIDGE, 553 pci_subclass_bridge, }, 554 { "communications", PCI_CLASS_COMMUNICATIONS, 555 pci_subclass_communications, }, 556 { "system", PCI_CLASS_SYSTEM, 557 pci_subclass_system, }, 558 { "input", PCI_CLASS_INPUT, 559 pci_subclass_input, }, 560 { "dock", PCI_CLASS_DOCK, 561 pci_subclass_dock, }, 562 { "processor", PCI_CLASS_PROCESSOR, 563 pci_subclass_processor, }, 564 { "serial bus", PCI_CLASS_SERIALBUS, 565 pci_subclass_serialbus, }, 566 { "wireless", PCI_CLASS_WIRELESS, 567 pci_subclass_wireless, }, 568 { "I2O", PCI_CLASS_I2O, 569 pci_subclass_i2o, }, 570 { "satellite comm", PCI_CLASS_SATCOM, 571 pci_subclass_satcom, }, 572 { "crypto", PCI_CLASS_CRYPTO, 573 pci_subclass_crypto, }, 574 { "DASP", PCI_CLASS_DASP, 575 pci_subclass_dasp, }, 576 { "processing accelerators", PCI_CLASS_ACCEL, 577 NULL, }, 578 { "non-essential instrumentation", PCI_CLASS_INSTRUMENT, 579 NULL, }, 580 { "undefined", PCI_CLASS_UNDEFINED, 581 NULL, }, 582 { NULL, 0, 583 NULL, }, 584 }; 585 586 DEV_VERBOSE_DEFINE(pci); 587 588 /* 589 * Append a formatted string to dest without writing more than len 590 * characters (including the trailing NUL character). dest and len 591 * are updated for use in subsequent calls to snappendf(). 592 * 593 * Returns 0 on success, a negative value if vnsprintf() fails, or 594 * a positive value if the dest buffer would have overflowed. 595 */ 596 597 static int __printflike(3, 4) 598 snappendf(char **dest, size_t *len, const char * restrict fmt, ...) 599 { 600 va_list ap; 601 int count; 602 603 va_start(ap, fmt); 604 count = vsnprintf(*dest, *len, fmt, ap); 605 va_end(ap); 606 607 /* Let vsnprintf() errors bubble up to caller */ 608 if (count < 0 || *len == 0) 609 return count; 610 611 /* Handle overflow */ 612 if ((size_t)count >= *len) { 613 *dest += *len - 1; 614 *len = 1; 615 return 1; 616 } 617 618 /* Update dest & len to point at trailing NUL */ 619 *dest += count; 620 *len -= count; 621 622 return 0; 623 } 624 625 void 626 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 627 size_t l) 628 { 629 pci_class_t class; 630 pci_subclass_t subclass; 631 pci_interface_t interface; 632 pci_revision_t revision; 633 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 634 const struct pci_class *classp, *subclassp, *interfacep; 635 636 class = PCI_CLASS(class_reg); 637 subclass = PCI_SUBCLASS(class_reg); 638 interface = PCI_INTERFACE(class_reg); 639 revision = PCI_REVISION(class_reg); 640 641 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 642 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 643 PCI_PRODUCT(id_reg)); 644 645 classp = pci_classes; 646 while (classp->name != NULL) { 647 if (class == classp->val) 648 break; 649 classp++; 650 } 651 652 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 653 while (subclassp && subclassp->name != NULL) { 654 if (subclass == subclassp->val) 655 break; 656 subclassp++; 657 } 658 659 interfacep = (subclassp && subclassp->name != NULL) ? 660 subclassp->subclasses : NULL; 661 while (interfacep && interfacep->name != NULL) { 662 if (interface == interfacep->val) 663 break; 664 interfacep++; 665 } 666 667 (void)snappendf(&cp, &l, "%s %s", vendor, product); 668 if (showclass) { 669 (void)snappendf(&cp, &l, " ("); 670 if (classp->name == NULL) 671 (void)snappendf(&cp, &l, 672 "class 0x%02x, subclass 0x%02x", 673 class, subclass); 674 else { 675 if (subclassp == NULL || subclassp->name == NULL) 676 (void)snappendf(&cp, &l, 677 "%s, subclass 0x%02x", 678 classp->name, subclass); 679 else 680 (void)snappendf(&cp, &l, "%s %s", 681 subclassp->name, classp->name); 682 } 683 if ((interfacep == NULL) || (interfacep->name == NULL)) { 684 if (interface != 0) 685 (void)snappendf(&cp, &l, ", interface 0x%02x", 686 interface); 687 } else if (strncmp(interfacep->name, "", 1) != 0) 688 (void)snappendf(&cp, &l, ", %s", interfacep->name); 689 if (revision != 0) 690 (void)snappendf(&cp, &l, ", revision 0x%02x", revision); 691 (void)snappendf(&cp, &l, ")"); 692 } 693 } 694 695 #ifdef _KERNEL 696 void 697 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 698 const char *known, int addrev) 699 { 700 char devinfo[256]; 701 702 if (known) { 703 aprint_normal(": %s", known); 704 if (addrev) 705 aprint_normal(" (rev. 0x%02x)", 706 PCI_REVISION(pa->pa_class)); 707 aprint_normal("\n"); 708 } else { 709 pci_devinfo(pa->pa_id, pa->pa_class, 0, 710 devinfo, sizeof(devinfo)); 711 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 712 PCI_REVISION(pa->pa_class)); 713 } 714 if (naive) 715 aprint_naive(": %s\n", naive); 716 else 717 aprint_naive("\n"); 718 } 719 #endif 720 721 /* 722 * Print out most of the PCI configuration registers. Typically used 723 * in a device attach routine like this: 724 * 725 * #ifdef MYDEV_DEBUG 726 * printf("%s: ", device_xname(sc->sc_dev)); 727 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 728 * #endif 729 */ 730 731 #define i2o(i) ((i) * 4) 732 #define o2i(o) ((o) / 4) 733 #define onoff2(str, rval, bit, onstr, offstr) \ 734 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 735 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 736 737 static void 738 pci_conf_print_common( 739 #ifdef _KERNEL 740 pci_chipset_tag_t pc, pcitag_t tag, 741 #endif 742 const pcireg_t *regs) 743 { 744 pci_class_t class; 745 pci_subclass_t subclass; 746 pci_interface_t interface; 747 pci_revision_t revision; 748 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 749 const struct pci_class *classp, *subclassp, *interfacep; 750 const char *name; 751 pcireg_t rval; 752 unsigned int num; 753 754 rval = regs[o2i(PCI_CLASS_REG)]; 755 class = PCI_CLASS(rval); 756 subclass = PCI_SUBCLASS(rval); 757 interface = PCI_INTERFACE(rval); 758 revision = PCI_REVISION(rval); 759 760 rval = regs[o2i(PCI_ID_REG)]; 761 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 762 if (name) 763 printf(" Vendor Name: %s (0x%04x)\n", name, 764 PCI_VENDOR(rval)); 765 else 766 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 767 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 768 PCI_PRODUCT(rval)); 769 if (name) 770 printf(" Device Name: %s (0x%04x)\n", name, 771 PCI_PRODUCT(rval)); 772 else 773 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 774 775 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 776 777 printf(" Command register: 0x%04x\n", rval & 0xffff); 778 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 779 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 780 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 781 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 782 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 783 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 784 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 785 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 786 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 787 onoff("Fast back-to-back transactions", rval, 788 PCI_COMMAND_BACKTOBACK_ENABLE); 789 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 790 791 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 792 onoff("Immediate Readiness", rval, PCI_STATUS_IMMD_READNESS); 793 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 794 "inactive"); 795 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 796 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 797 onoff("User Definable Features (UDF) support", rval, 798 PCI_STATUS_UDF_SUPPORT); 799 onoff("Fast back-to-back capable", rval, 800 PCI_STATUS_BACKTOBACK_SUPPORT); 801 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 802 803 printf(" DEVSEL timing: "); 804 switch (rval & PCI_STATUS_DEVSEL_MASK) { 805 case PCI_STATUS_DEVSEL_FAST: 806 printf("fast"); 807 break; 808 case PCI_STATUS_DEVSEL_MEDIUM: 809 printf("medium"); 810 break; 811 case PCI_STATUS_DEVSEL_SLOW: 812 printf("slow"); 813 break; 814 default: 815 printf("unknown/reserved"); /* XXX */ 816 break; 817 } 818 printf(" (0x%x)\n", __SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK)); 819 820 onoff("Slave signaled Target Abort", rval, 821 PCI_STATUS_TARGET_TARGET_ABORT); 822 onoff("Master received Target Abort", rval, 823 PCI_STATUS_MASTER_TARGET_ABORT); 824 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 825 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 826 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 827 828 rval = regs[o2i(PCI_CLASS_REG)]; 829 for (classp = pci_classes; classp->name != NULL; classp++) { 830 if (class == classp->val) 831 break; 832 } 833 834 /* 835 * ECN: Change Root Complex Event Collector Class Code 836 * Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type 837 * in PCIe extend capability to know whether it's RCEC or IOMMU. 838 */ 839 if ((class == PCI_CLASS_SYSTEM) 840 && (subclass == PCI_SUBCLASS_SYSTEM_IOMMU)) { 841 int pcie_capoff; 842 pcireg_t reg; 843 844 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 845 reg = regs[o2i(pcie_capoff + PCIE_XCAP)]; 846 if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_ROOT_EVNTC) 847 subclass = PCI_SUBCLASS_SYSTEM_RCEC; 848 } 849 } 850 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 851 while (subclassp && subclassp->name != NULL) { 852 if (subclass == subclassp->val) 853 break; 854 subclassp++; 855 } 856 857 interfacep = (subclassp && subclassp->name != NULL) ? 858 subclassp->subclasses : NULL; 859 while (interfacep && interfacep->name != NULL) { 860 if (interface == interfacep->val) 861 break; 862 interfacep++; 863 } 864 865 if (classp->name != NULL) 866 printf(" Class Name: %s (0x%02x)\n", classp->name, class); 867 else 868 printf(" Class ID: 0x%02x\n", class); 869 if (subclassp != NULL && subclassp->name != NULL) 870 printf(" Subclass Name: %s (0x%02x)\n", 871 subclassp->name, PCI_SUBCLASS(rval)); 872 else 873 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 874 if ((interfacep != NULL) && (interfacep->name != NULL) 875 && (strncmp(interfacep->name, "", 1) != 0)) 876 printf(" Interface Name: %s (0x%02x)\n", 877 interfacep->name, interface); 878 else 879 printf(" Interface: 0x%02x\n", interface); 880 printf(" Revision ID: 0x%02x\n", revision); 881 882 rval = regs[o2i(PCI_BHLC_REG)]; 883 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 884 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 885 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 886 PCI_HDRTYPE(rval)); 887 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 888 num = PCI_CACHELINE(rval); 889 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 890 } 891 892 static int 893 pci_conf_print_bar( 894 #ifdef _KERNEL 895 pci_chipset_tag_t pc, pcitag_t tag, 896 #endif 897 const pcireg_t *regs, int reg, const char *name) 898 { 899 int width; 900 pcireg_t rval, rval64h; 901 bool ioen, memen; 902 #ifdef _KERNEL 903 pcireg_t mask, mask64h = 0; 904 #endif 905 906 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 907 ioen = rval & PCI_COMMAND_IO_ENABLE; 908 memen = rval & PCI_COMMAND_MEM_ENABLE; 909 910 width = 4; 911 /* 912 * Section 6.2.5.1, `Address Maps', tells us that: 913 * 914 * 1) The builtin software should have already mapped the 915 * device in a reasonable way. 916 * 917 * 2) A device which wants 2^n bytes of memory will hardwire 918 * the bottom n bits of the address to 0. As recommended, 919 * we write all 1s and see what we get back. 920 */ 921 922 rval = regs[o2i(reg)]; 923 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 924 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 925 rval64h = regs[o2i(reg + 4)]; 926 width = 8; 927 } else 928 rval64h = 0; 929 930 #ifdef _KERNEL 931 if (rval != 0 && memen) { 932 int s; 933 934 /* 935 * The following sequence seems to make some devices 936 * (e.g. host bus bridges, which don't normally 937 * have their space mapped) very unhappy, to 938 * the point of crashing the system. 939 * 940 * Therefore, if the mapping register is zero to 941 * start out with, don't bother trying. 942 */ 943 s = splhigh(); 944 pci_conf_write(pc, tag, reg, 0xffffffff); 945 mask = pci_conf_read(pc, tag, reg); 946 pci_conf_write(pc, tag, reg, rval); 947 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 948 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 949 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 950 mask64h = pci_conf_read(pc, tag, reg + 4); 951 pci_conf_write(pc, tag, reg + 4, rval64h); 952 } 953 splx(s); 954 } else 955 mask = mask64h = 0; 956 #endif /* _KERNEL */ 957 958 printf(" Base address register at 0x%02x", reg); 959 if (name) 960 printf(" (%s)", name); 961 printf("\n "); 962 if (rval == 0) { 963 printf("not implemented\n"); 964 return width; 965 } 966 printf("type: "); 967 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 968 const char *type, *prefetch; 969 970 switch (PCI_MAPREG_MEM_TYPE(rval)) { 971 case PCI_MAPREG_MEM_TYPE_32BIT: 972 type = "32-bit"; 973 break; 974 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 975 type = "32-bit-1M"; 976 break; 977 case PCI_MAPREG_MEM_TYPE_64BIT: 978 type = "64-bit"; 979 break; 980 default: 981 type = "unknown (XXX)"; 982 break; 983 } 984 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 985 prefetch = ""; 986 else 987 prefetch = "non"; 988 printf("%s %sprefetchable memory\n", type, prefetch); 989 switch (PCI_MAPREG_MEM_TYPE(rval)) { 990 case PCI_MAPREG_MEM_TYPE_64BIT: 991 printf(" base: 0x%016llx", 992 PCI_MAPREG_MEM64_ADDR( 993 ((((long long) rval64h) << 32) | rval))); 994 if (!memen) 995 printf(", disabled"); 996 printf("\n"); 997 #ifdef _KERNEL 998 printf(" size: 0x%016llx\n", 999 PCI_MAPREG_MEM64_SIZE( 1000 ((((long long) mask64h) << 32) | mask))); 1001 #endif 1002 break; 1003 case PCI_MAPREG_MEM_TYPE_32BIT: 1004 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 1005 default: 1006 printf(" base: 0x%08x", 1007 PCI_MAPREG_MEM_ADDR(rval)); 1008 if (!memen) 1009 printf(", disabled"); 1010 printf("\n"); 1011 #ifdef _KERNEL 1012 printf(" size: 0x%08x\n", 1013 PCI_MAPREG_MEM_SIZE(mask)); 1014 #endif 1015 break; 1016 } 1017 } else { 1018 #ifdef _KERNEL 1019 if (ioen) 1020 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 1021 #endif 1022 printf("I/O\n"); 1023 printf(" base: 0x%08x", PCI_MAPREG_IO_ADDR(rval)); 1024 if (!ioen) 1025 printf(", disabled"); 1026 printf("\n"); 1027 #ifdef _KERNEL 1028 printf(" size: 0x%08x\n", PCI_MAPREG_IO_SIZE(mask)); 1029 #endif 1030 } 1031 1032 return width; 1033 } 1034 1035 static void 1036 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 1037 { 1038 int off, needaddr, neednl; 1039 1040 needaddr = 1; 1041 neednl = 0; 1042 for (off = first; off < pastlast; off += 4) { 1043 if ((off % 16) == 0 || needaddr) { 1044 printf(" 0x%02x:", off); 1045 needaddr = 0; 1046 } 1047 printf(" 0x%08x", regs[o2i(off)]); 1048 neednl = 1; 1049 if ((off % 16) == 12) { 1050 printf("\n"); 1051 neednl = 0; 1052 } 1053 } 1054 if (neednl) 1055 printf("\n"); 1056 } 1057 1058 static const char * 1059 pci_conf_print_agp_calcycle(uint8_t cal) 1060 { 1061 1062 switch (cal) { 1063 case 0x0: 1064 return "4ms"; 1065 case 0x1: 1066 return "16ms"; 1067 case 0x2: 1068 return "64ms"; 1069 case 0x3: 1070 return "256ms"; 1071 case 0x7: 1072 return "Calibration Cycle Not Needed"; 1073 default: 1074 return "(reserved)"; 1075 } 1076 } 1077 1078 static void 1079 pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3) 1080 { 1081 if (isagp3) { 1082 /* AGP 3.0 */ 1083 if (reg & AGP_MODE_V3_RATE_4x) 1084 printf("x4"); 1085 if (reg & AGP_MODE_V3_RATE_8x) 1086 printf("x8"); 1087 } else { 1088 /* AGP 2.0 */ 1089 if (reg & AGP_MODE_V2_RATE_1x) 1090 printf("x1"); 1091 if (reg & AGP_MODE_V2_RATE_2x) 1092 printf("x2"); 1093 if (reg & AGP_MODE_V2_RATE_4x) 1094 printf("x4"); 1095 } 1096 printf("\n"); 1097 } 1098 1099 static void 1100 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1101 { 1102 pcireg_t rval; 1103 bool isagp3; 1104 1105 printf("\n AGP Capabilities Register\n"); 1106 1107 rval = regs[o2i(capoff)]; 1108 printf(" Revision: %d.%d\n", 1109 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1110 1111 rval = regs[o2i(capoff + PCI_AGP_STATUS)]; 1112 printf(" Status register: 0x%04x\n", rval); 1113 printf(" RQ: %d\n", 1114 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1115 printf(" ARQSZ: %d\n", 1116 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1117 printf(" CAL cycle: %s\n", 1118 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1119 onoff("SBA", rval, AGP_MODE_SBA); 1120 onoff("htrans#", rval, AGP_MODE_HTRANS); 1121 onoff("Over 4G", rval, AGP_MODE_4G); 1122 onoff("Fast Write", rval, AGP_MODE_FW); 1123 onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3); 1124 isagp3 = rval & AGP_MODE_MODE_3; 1125 printf(" Data Rate Support: "); 1126 pci_conf_print_agp_datarate(rval, isagp3); 1127 1128 rval = regs[o2i(capoff + PCI_AGP_COMMAND)]; 1129 printf(" Command register: 0x%08x\n", rval); 1130 printf(" PRQ: %d\n", 1131 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1132 printf(" PARQSZ: %d\n", 1133 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1134 printf(" PCAL cycle: %s\n", 1135 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1136 onoff("SBA", rval, AGP_MODE_SBA); 1137 onoff("AGP", rval, AGP_MODE_AGP); 1138 onoff("Over 4G", rval, AGP_MODE_4G); 1139 onoff("Fast Write", rval, AGP_MODE_FW); 1140 if (isagp3) { 1141 printf(" Data Rate Enable: "); 1142 /* 1143 * The Data Rate Enable bits are used only on 3.0 and the 1144 * Command register has no AGP_MODE_MODE_3 bit, so pass the 1145 * flag to print correctly. 1146 */ 1147 pci_conf_print_agp_datarate(rval, isagp3); 1148 } 1149 } 1150 1151 static const char * 1152 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1153 { 1154 1155 switch ((caps >> 6) & 7) { 1156 case 0: return "self-powered"; 1157 case 1: return "55 mA"; 1158 case 2: return "100 mA"; 1159 case 3: return "160 mA"; 1160 case 4: return "220 mA"; 1161 case 5: return "270 mA"; 1162 case 6: return "320 mA"; 1163 case 7: 1164 default: return "375 mA"; 1165 } 1166 } 1167 1168 static const char * 1169 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1170 { 1171 static const char unk[] = "unknown"; 1172 static const char *pmrev[8] = { 1173 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1174 }; 1175 if (val > 7) 1176 return unk; 1177 return pmrev[val]; 1178 } 1179 1180 static void 1181 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1182 { 1183 uint16_t caps, pmcsr; 1184 1185 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1186 pmcsr = regs[o2i(capoff + PCI_PMCSR)]; 1187 1188 printf("\n PCI Power Management Capabilities Register\n"); 1189 1190 printf(" Capabilities register: 0x%04x\n", caps); 1191 printf(" Version: %s\n", 1192 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1193 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1194 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1195 printf(" 3.3V auxiliary current: %s\n", 1196 pci_conf_print_pcipm_cap_aux(caps)); 1197 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1198 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1199 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1200 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1201 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1202 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1203 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1204 1205 printf(" Control/status register: 0x%08x\n", pmcsr); 1206 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1207 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1208 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1209 printf(" PME# assertion: %sabled\n", 1210 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1211 printf(" Data Select: %d\n", 1212 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK)); 1213 printf(" Data Scale: %d\n", 1214 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK)); 1215 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1216 printf(" Bridge Support Extensions register: 0x%02x\n", 1217 (pmcsr >> 16) & 0xff); 1218 onoff("B2/B3 support", pmcsr, PCI_PMCSR_B2B3_SUPPORT); 1219 onoff("Bus Power/Clock Control Enable", pmcsr, PCI_PMCSR_BPCC_EN); 1220 printf(" Data register: 0x%02x\n", 1221 __SHIFTOUT(pmcsr, PCI_PMCSR_DATA)); 1222 } 1223 1224 /* XXX pci_conf_print_vpd_cap */ 1225 /* XXX pci_conf_print_slotid_cap */ 1226 1227 static void 1228 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1229 { 1230 uint32_t ctl, mmc, mme; 1231 1232 regs += o2i(capoff); 1233 ctl = *regs++; 1234 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1235 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1236 1237 printf("\n PCI Message Signaled Interrupt\n"); 1238 1239 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1240 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1241 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1242 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1243 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1244 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1245 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1246 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1247 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP); 1248 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN); 1249 printf(" Message Address %sregister: 0x%08x\n", 1250 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1251 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1252 printf(" Message Address %sregister: 0x%08x\n", 1253 "(upper) ", *regs++); 1254 } 1255 printf(" Message Data register: "); 1256 if (ctl & PCI_MSI_CTL_EXTMDATA_CAP) 1257 printf("0x%08x\n", *regs); 1258 else 1259 printf("0x%04x\n", *regs & 0xffff); 1260 regs++; 1261 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1262 printf(" Vector Mask register: 0x%08x\n", *regs++); 1263 printf(" Vector Pending register: 0x%08x\n", *regs++); 1264 } 1265 } 1266 1267 /* XXX pci_conf_print_cpci_hostwap_cap */ 1268 1269 /* 1270 * For both command register and status register. 1271 * The argument "idx" is index number (0 to 7). 1272 */ 1273 static int 1274 pcix_split_trans(unsigned int idx) 1275 { 1276 static int table[8] = { 1277 1, 2, 3, 4, 8, 12, 16, 32 1278 }; 1279 1280 if (idx >= __arraycount(table)) 1281 return -1; 1282 return table[idx]; 1283 } 1284 1285 static void 1286 pci_conf_print_pcix_cap_2ndbusmode(int num) 1287 { 1288 const char *maxfreq, *maxperiod; 1289 1290 printf(" Mode: "); 1291 if (num <= 0x07) 1292 printf("PCI-X Mode 1\n"); 1293 else if (num <= 0x0b) 1294 printf("PCI-X 266 (Mode 2)\n"); 1295 else 1296 printf("PCI-X 533 (Mode 2)\n"); 1297 1298 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1299 switch (num & 0x03) { 1300 default: 1301 case 0: 1302 maxfreq = "N/A"; 1303 maxperiod = "N/A"; 1304 break; 1305 case 1: 1306 maxfreq = "66MHz"; 1307 maxperiod = "15ns"; 1308 break; 1309 case 2: 1310 maxfreq = "100MHz"; 1311 maxperiod = "10ns"; 1312 break; 1313 case 3: 1314 maxfreq = "133MHz"; 1315 maxperiod = "7.5ns"; 1316 break; 1317 } 1318 printf(" Max Clock Freq: %s\n", maxfreq); 1319 printf(" Min Clock Period: %s\n", maxperiod); 1320 } 1321 1322 static void 1323 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1324 { 1325 pcireg_t reg; 1326 int isbridge; 1327 int i; 1328 1329 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1330 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1331 printf("\n PCI-X %s Capabilities Register\n", 1332 isbridge ? "Bridge" : "Non-bridge"); 1333 1334 reg = regs[o2i(capoff)]; 1335 if (isbridge != 0) { 1336 printf(" Secondary status register: 0x%04x\n", 1337 (reg & 0xffff0000) >> 16); 1338 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1339 onoff("133MHz capable", reg, PCIX_STATUS_133); 1340 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1341 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1342 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1343 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1344 pci_conf_print_pcix_cap_2ndbusmode( 1345 __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1346 printf(" Version: 0x%x\n", 1347 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1348 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1349 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1350 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1351 } else { 1352 printf(" Command register: 0x%04x\n", 1353 (reg & 0xffff0000) >> 16); 1354 onoff("Data Parity Error Recovery", reg, 1355 PCIX_CMD_PERR_RECOVER); 1356 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1357 printf(" Maximum Burst Read Count: %u\n", 1358 PCIX_CMD_BYTECNT(reg)); 1359 printf(" Maximum Split Transactions: %d\n", 1360 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1361 >> PCIX_CMD_SPLTRANS_SHIFT)); 1362 } 1363 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1364 printf(" %sStatus register: 0x%08x\n", 1365 isbridge ? "Bridge " : "", reg); 1366 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1367 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1368 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1369 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1370 onoff("133MHz capable", reg, PCIX_STATUS_133); 1371 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1372 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1373 if (isbridge != 0) { 1374 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1375 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1376 } else { 1377 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1378 "bridge device", "simple device"); 1379 printf(" Designed max memory read byte count: %d\n", 1380 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1381 >> PCIX_STATUS_MAXB_SHIFT)); 1382 printf(" Designed max outstanding split transaction: %d\n", 1383 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1384 >> PCIX_STATUS_MAXST_SHIFT)); 1385 printf(" MAX cumulative Read Size: %u\n", 1386 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1387 onoff("Received split completion error", reg, 1388 PCIX_STATUS_SCERR); 1389 } 1390 onoff("266MHz capable", reg, PCIX_STATUS_266); 1391 onoff("533MHz capable", reg, PCIX_STATUS_533); 1392 1393 if (isbridge == 0) 1394 return; 1395 1396 /* Only for bridge */ 1397 for (i = 0; i < 2; i++) { 1398 reg = regs[o2i(capoff + PCIX_BRIDGE_UP_STCR + (4 * i))]; 1399 printf(" %s split transaction control register: 0x%08x\n", 1400 (i == 0) ? "Upstream" : "Downstream", reg); 1401 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1402 printf(" Commitment Limit: %d\n", 1403 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1404 } 1405 } 1406 1407 /* pci_conf_print_ht_slave_cap */ 1408 /* pci_conf_print_ht_host_cap */ 1409 /* pci_conf_print_ht_switch_cap */ 1410 /* pci_conf_print_ht_intr_cap */ 1411 /* pci_conf_print_ht_revid_cap */ 1412 /* pci_conf_print_ht_unitid_cap */ 1413 /* pci_conf_print_ht_extcnf_cap */ 1414 /* pci_conf_print_ht_addrmap_cap */ 1415 /* pci_conf_print_ht_msimap_cap */ 1416 1417 static void 1418 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1419 { 1420 pcireg_t val; 1421 uint32_t lo, hi; 1422 1423 /* 1424 * Print the rest of the command register bits. Others are 1425 * printed in pci_conf_print_ht_cap(). 1426 */ 1427 val = regs[o2i(capoff + PCI_HT_CMD)]; 1428 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1429 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1430 1431 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1432 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1433 printf(" Address Low register: 0x%08x\n", lo); 1434 printf(" Address high register: 0x%08x\n", hi); 1435 printf(" Address: 0x%016" PRIx64 "\n", 1436 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1437 } 1438 1439 /* pci_conf_print_ht_droute_cap */ 1440 /* pci_conf_print_ht_vcset_cap */ 1441 /* pci_conf_print_ht_retry_cap */ 1442 /* pci_conf_print_ht_x86enc_cap */ 1443 /* pci_conf_print_ht_gen3_cap */ 1444 /* pci_conf_print_ht_fle_cap */ 1445 /* pci_conf_print_ht_pm_cap */ 1446 /* pci_conf_print_ht_hnc_cap */ 1447 1448 static const struct ht_types { 1449 pcireg_t cap; 1450 const char *name; 1451 void (*printfunc)(const pcireg_t *, int); 1452 } ht_captab[] = { 1453 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1454 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1455 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1456 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1457 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1458 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1459 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1460 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1461 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1462 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1463 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1464 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1465 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1466 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1467 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1468 {PCI_HT_CAP_PM, "Power Management", NULL }, 1469 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1470 }; 1471 1472 static void 1473 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1474 { 1475 pcireg_t val, foundcap; 1476 unsigned int off; 1477 1478 val = regs[o2i(capoff + PCI_HT_CMD)]; 1479 1480 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1481 1482 printf(" Command register: 0x%04x\n", val >> 16); 1483 foundcap = PCI_HT_CAP(val); 1484 for (off = 0; off < __arraycount(ht_captab); off++) { 1485 if (ht_captab[off].cap == foundcap) 1486 break; 1487 } 1488 printf(" Capability Type: 0x%02x ", foundcap); 1489 if (off >= __arraycount(ht_captab)) { 1490 printf("(unknown)\n"); 1491 return; 1492 } 1493 printf("(%s)\n", ht_captab[off].name); 1494 if (ht_captab[off].printfunc != NULL) 1495 ht_captab[off].printfunc(regs, capoff); 1496 } 1497 1498 static void 1499 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1500 { 1501 uint16_t caps; 1502 1503 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1504 1505 printf("\n PCI Vendor Specific Capabilities Register\n"); 1506 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1507 } 1508 1509 static void 1510 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1511 { 1512 pcireg_t val; 1513 1514 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1515 1516 printf("\n Debugport Capability Register\n"); 1517 printf(" Debug base Register: 0x%04x\n", 1518 val >> PCI_DEBUG_BASER_SHIFT); 1519 printf(" port offset: 0x%04x\n", 1520 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1521 printf(" BAR number: %u\n", 1522 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1523 } 1524 1525 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1526 /* XXX pci_conf_print_hotplug_cap */ 1527 1528 static void 1529 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1530 { 1531 pcireg_t reg; 1532 1533 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1534 1535 printf("\n Subsystem ID Capability Register\n"); 1536 printf(" Subsystem ID: 0x%08x\n", reg); 1537 } 1538 1539 /* XXX pci_conf_print_agp8_cap */ 1540 static void 1541 pci_conf_print_secure_cap(const pcireg_t *regs, int capoff) 1542 { 1543 pcireg_t reg, reg2, val; 1544 bool havemisc1; 1545 1546 printf("\n Secure Capability Register\n"); 1547 reg = regs[o2i(capoff + PCI_SECURE_CAP)]; 1548 printf(" Capability Register: 0x%04x\n", reg >> 16); 1549 val = __SHIFTOUT(reg, PCI_SECURE_CAP_TYPE); 1550 printf(" Capability block type: "); 1551 /* I know IOMMU Only */ 1552 if (val == PCI_SECURE_CAP_TYPE_IOMMU) 1553 printf("IOMMU\n"); 1554 else { 1555 printf("0x%x(unknown)\n", val); 1556 return; 1557 } 1558 1559 val = __SHIFTOUT(reg, PCI_SECURE_CAP_REV); 1560 printf(" Capability revision: 0x%02x ", val); 1561 if (val == PCI_SECURE_CAP_REV_IOMMU) 1562 printf("(IOMMU)\n"); 1563 else { 1564 printf("(unknown)\n"); 1565 return; 1566 } 1567 onoff("IOTLB support", reg, PCI_SECURE_CAP_IOTLBSUP); 1568 onoff("HyperTransport tunnel translation support", reg, 1569 PCI_SECURE_CAP_HTTUNNEL); 1570 onoff("Not present table entries cached", reg, PCI_SECURE_CAP_NPCACHE); 1571 onoff("IOMMU Extended Feature Register support", reg, 1572 PCI_SECURE_CAP_EFRSUP); 1573 onoff("IOMMU Miscellaneous Information Register 1", reg, 1574 PCI_SECURE_CAP_EXT); 1575 havemisc1 = reg & PCI_SECURE_CAP_EXT; 1576 1577 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_BAL)]; 1578 printf(" Base Address Low Register: 0x%08x\n", reg); 1579 onoff("Enable", reg, PCI_SECURE_IOMMU_BAL_EN); 1580 reg2 = regs[o2i(capoff + PCI_SECURE_IOMMU_BAH)]; 1581 printf(" Base Address High Register: 0x%08x\n", reg2); 1582 printf(" Base Address: 0x%016" PRIx64 "\n", 1583 ((uint64_t)reg2 << 32) 1584 | (reg & (PCI_SECURE_IOMMU_BAL_H | PCI_SECURE_IOMMU_BAL_L))); 1585 1586 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_RANGE)]; 1587 printf(" IOMMU Range Register: 0x%08x\n", reg); 1588 printf(" HyperTransport UnitID: 0x%02x\n", 1589 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_UNITID)); 1590 onoff("Range valid", reg, PCI_SECURE_IOMMU_RANGE_RNGVALID); 1591 printf(" Device range bus number: 0x%02x\n", 1592 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_BUSNUM)); 1593 printf(" First device: 0x%04x\n", 1594 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_FIRSTDEV)); 1595 printf(" Last device: 0x%04x\n", 1596 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_LASTDEV)); 1597 1598 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC0)]; 1599 printf(" Miscellaneous Information Register 0: 0x%08x\n", reg); 1600 printf(" MSI Message number: 0x%02x\n", 1601 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MSINUM)); 1602 val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_GVASIZE); 1603 printf(" Guest Virtual Address size: "); 1604 if (val == PCI_SECURE_IOMMU_MISC0_GVASIZE_48B) 1605 printf("48bits\n"); 1606 else 1607 printf("0x%x(unknown)\n", val); 1608 val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_PASIZE); 1609 printf(" Physical Address size: %dbits\n", val); 1610 val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_VASIZE); 1611 printf(" Virtual Address size: %dbits\n", val); 1612 onoff("ATS response address range reserved", reg, 1613 PCI_SECURE_IOMMU_MISC0_ATSRESV); 1614 printf(" Peripheral Page Request MSI Message number: 0x%02x\n", 1615 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MISNPPR)); 1616 1617 if (!havemisc1) 1618 return; 1619 1620 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC1)]; 1621 printf(" Miscellaneous Information Register 1: 0x%08x\n", reg); 1622 printf(" MSI Message number (GA): 0x%02x\n", 1623 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC1_MSINUM)); 1624 } 1625 1626 static void 1627 pci_print_pcie_L0s_latency(uint32_t val) 1628 { 1629 1630 switch (val) { 1631 case 0x0: 1632 printf("Less than 64ns\n"); 1633 break; 1634 case 0x1: 1635 case 0x2: 1636 case 0x3: 1637 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1638 break; 1639 case 0x4: 1640 printf("512ns to less than 1us\n"); 1641 break; 1642 case 0x5: 1643 printf("1us to less than 2us\n"); 1644 break; 1645 case 0x6: 1646 printf("2us - 4us\n"); 1647 break; 1648 case 0x7: 1649 printf("More than 4us\n"); 1650 break; 1651 } 1652 } 1653 1654 static void 1655 pci_print_pcie_L1_latency(uint32_t val) 1656 { 1657 1658 switch (val) { 1659 case 0x0: 1660 printf("Less than 1us\n"); 1661 break; 1662 case 0x6: 1663 printf("32us - 64us\n"); 1664 break; 1665 case 0x7: 1666 printf("More than 64us\n"); 1667 break; 1668 default: 1669 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1670 break; 1671 } 1672 } 1673 1674 static void 1675 pci_print_pcie_compl_timeout(uint32_t val) 1676 { 1677 1678 switch (val) { 1679 case 0x0: 1680 printf("50us to 50ms\n"); 1681 break; 1682 case 0x5: 1683 printf("16ms to 55ms\n"); 1684 break; 1685 case 0x6: 1686 printf("65ms to 210ms\n"); 1687 break; 1688 case 0x9: 1689 printf("260ms to 900ms\n"); 1690 break; 1691 case 0xa: 1692 printf("1s to 3.5s\n"); 1693 break; 1694 default: 1695 printf("unknown %u value\n", val); 1696 break; 1697 } 1698 } 1699 1700 static const char * const pcie_linkspeeds[] = {"2.5", "5.0", "8.0", "16.0"}; 1701 1702 /* 1703 * Print link speed. This function is used for the following register bits: 1704 * Maximum Link Speed in LCAP 1705 * Current Link Speed in LCSR 1706 * Target Link Speed in LCSR2 1707 * All of above bitfield's values start from 1. 1708 * For LCSR2, 0 is allowed for a device which supports 2.5GT/s only (and 1709 * this check also works for devices which compliant to versions of the base 1710 * specification prior to 3.0. 1711 */ 1712 static void 1713 pci_print_pcie_linkspeed(int regnum, pcireg_t val) 1714 { 1715 1716 if ((regnum == PCIE_LCSR2) && (val == 0)) 1717 printf("2.5GT/s\n"); 1718 else if ((val < 1) || (val > __arraycount(pcie_linkspeeds))) 1719 printf("unknown value (%u)\n", val); 1720 else 1721 printf("%sGT/s\n", pcie_linkspeeds[val - 1]); 1722 } 1723 1724 /* 1725 * Print link speed "vector". 1726 * This function is used for the following register bits: 1727 * Supported Link Speeds Vector in LCAP2 1728 * Lower SKP OS Generation Supported Speed Vector in LCAP2 1729 * Lower SKP OS Reception Supported Speed Vector in LCAP2 1730 * Enable Lower SKP OS Generation Vector in LCTL3 1731 * All of above bitfield's values start from 0. 1732 */ 1733 static void 1734 pci_print_pcie_linkspeedvector(pcireg_t val) 1735 { 1736 unsigned int i; 1737 1738 /* Start from 0 */ 1739 for (i = 0; i < 16; i++) 1740 if (((val >> i) & 0x01) != 0) { 1741 if (i >= __arraycount(pcie_linkspeeds)) 1742 printf(" unknown vector (0x%x)", 1 << i); 1743 else 1744 printf(" %sGT/s", pcie_linkspeeds[i]); 1745 } 1746 } 1747 1748 static void 1749 pci_print_pcie_link_deemphasis(pcireg_t val) 1750 { 1751 switch (val) { 1752 case 0: 1753 printf("-6dB"); 1754 break; 1755 case 1: 1756 printf("-3.5dB"); 1757 break; 1758 default: 1759 printf("(reserved value)"); 1760 } 1761 } 1762 1763 static void 1764 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1765 { 1766 pcireg_t reg; /* for each register */ 1767 pcireg_t val; /* for each bitfield */ 1768 bool check_slot = false; 1769 unsigned int pcie_devtype; 1770 bool check_upstreamport = false; 1771 unsigned int pciever; 1772 unsigned int i; 1773 1774 printf("\n PCI Express Capabilities Register\n"); 1775 /* Capability Register */ 1776 reg = regs[o2i(capoff)]; 1777 printf(" Capability register: 0x%04x\n", reg >> 16); 1778 pciever = (unsigned int)(PCIE_XCAP_VER(reg)); 1779 printf(" Capability version: %u\n", pciever); 1780 printf(" Device type: "); 1781 pcie_devtype = PCIE_XCAP_TYPE(reg); 1782 switch (pcie_devtype) { 1783 case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */ 1784 printf("PCI Express Endpoint device\n"); 1785 check_upstreamport = true; 1786 break; 1787 case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */ 1788 printf("Legacy PCI Express Endpoint device\n"); 1789 check_upstreamport = true; 1790 break; 1791 case PCIE_XCAP_TYPE_ROOT: /* 0x4 */ 1792 printf("Root Port of PCI Express Root Complex\n"); 1793 check_slot = true; 1794 break; 1795 case PCIE_XCAP_TYPE_UP: /* 0x5 */ 1796 printf("Upstream Port of PCI Express Switch\n"); 1797 check_upstreamport = true; 1798 break; 1799 case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ 1800 printf("Downstream Port of PCI Express Switch\n"); 1801 check_slot = true; 1802 break; 1803 case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ 1804 printf("PCI Express to PCI/PCI-X Bridge\n"); 1805 check_upstreamport = true; 1806 break; 1807 case PCIE_XCAP_TYPE_PCI2PCIE: /* 0x8 */ 1808 printf("PCI/PCI-X to PCI Express Bridge\n"); 1809 /* Upstream port is not PCIe */ 1810 check_slot = true; 1811 break; 1812 case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */ 1813 printf("Root Complex Integrated Endpoint\n"); 1814 break; 1815 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */ 1816 printf("Root Complex Event Collector\n"); 1817 break; 1818 default: 1819 printf("unknown\n"); 1820 break; 1821 } 1822 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1823 printf(" Interrupt Message Number: 0x%02x\n", 1824 (unsigned int)__SHIFTOUT(reg, PCIE_XCAP_IRQ)); 1825 1826 /* Device Capability Register */ 1827 reg = regs[o2i(capoff + PCIE_DCAP)]; 1828 printf(" Device Capabilities Register: 0x%08x\n", reg); 1829 printf(" Max Payload Size Supported: %u bytes max\n", 1830 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1831 printf(" Phantom Functions Supported: "); 1832 switch (__SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) { 1833 case 0x0: 1834 printf("not available\n"); 1835 break; 1836 case 0x1: 1837 printf("MSB\n"); 1838 break; 1839 case 0x2: 1840 printf("two MSB\n"); 1841 break; 1842 case 0x3: 1843 printf("All three bits\n"); 1844 break; 1845 } 1846 printf(" Extended Tag Field Supported: %dbit\n", 1847 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1848 printf(" Endpoint L0 Acceptable Latency: "); 1849 pci_print_pcie_L0s_latency(__SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY)); 1850 printf(" Endpoint L1 Acceptable Latency: "); 1851 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY)); 1852 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1853 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1854 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1855 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1856 if (check_upstreamport) { 1857 printf(" Captured Slot Power Limit: "); 1858 pci_conf_print_pcie_power( 1859 __SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL), 1860 __SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE)); 1861 } 1862 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1863 1864 /* Device Control Register */ 1865 reg = regs[o2i(capoff + PCIE_DCSR)]; 1866 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1867 onoff("Correctable Error Reporting Enable", reg, 1868 PCIE_DCSR_ENA_COR_ERR); 1869 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1870 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1871 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1872 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1873 printf(" Max Payload Size: %d byte\n", 1874 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD)); 1875 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1876 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1877 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1878 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1879 printf(" Max Read Request Size: %d byte\n", 1880 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ)); 1881 if (pcie_devtype == PCIE_XCAP_TYPE_PCIE2PCI) 1882 onoff("Bridge Config Retry Enable", reg, 1883 PCIE_DCSR_BRDG_CFG_RETRY); 1884 1885 /* Device Status Register */ 1886 reg = regs[o2i(capoff + PCIE_DCSR)]; 1887 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1888 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1889 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1890 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1891 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1892 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1893 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1894 onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD); 1895 1896 if (PCIE_HAS_LINKREGS(pcie_devtype)) { 1897 /* Link Capability Register */ 1898 reg = regs[o2i(capoff + PCIE_LCAP)]; 1899 printf(" Link Capabilities Register: 0x%08x\n", reg); 1900 printf(" Maximum Link Speed: "); 1901 pci_print_pcie_linkspeed(PCIE_LCAP, reg & PCIE_LCAP_MAX_SPEED); 1902 printf(" Maximum Link Width: x%u lanes\n", 1903 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH)); 1904 printf(" Active State PM Support: "); 1905 switch (__SHIFTOUT(reg, PCIE_LCAP_ASPM)) { 1906 case 0x0: 1907 printf("No ASPM support\n"); 1908 break; 1909 case 0x1: 1910 printf("L0s supported\n"); 1911 break; 1912 case 0x2: 1913 printf("L1 supported\n"); 1914 break; 1915 case 0x3: 1916 printf("L0s and L1 supported\n"); 1917 break; 1918 } 1919 printf(" L0 Exit Latency: "); 1920 pci_print_pcie_L0s_latency(__SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT)); 1921 printf(" L1 Exit Latency: "); 1922 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_LCAP_L1_EXIT)); 1923 printf(" Port Number: %u\n", 1924 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_PORT)); 1925 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1926 onoff("Surprise Down Error Report", reg, 1927 PCIE_LCAP_SURPRISE_DOWN); 1928 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1929 onoff("Link BW Notification Capable", reg, 1930 PCIE_LCAP_LINK_BW_NOTIFY); 1931 onoff("ASPM Optionally Compliance", reg, 1932 PCIE_LCAP_ASPM_COMPLIANCE); 1933 1934 /* Link Control Register */ 1935 reg = regs[o2i(capoff + PCIE_LCSR)]; 1936 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1937 printf(" Active State PM Control: "); 1938 switch (reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S)) { 1939 case 0: 1940 printf("disabled\n"); 1941 break; 1942 case 1: 1943 printf("L0s Entry Enabled\n"); 1944 break; 1945 case 2: 1946 printf("L1 Entry Enabled\n"); 1947 break; 1948 case 3: 1949 printf("L0s and L1 Entry Enabled\n"); 1950 break; 1951 } 1952 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1953 "128bytes", "64bytes"); 1954 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 1955 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 1956 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 1957 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 1958 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 1959 onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD); 1960 onoff("Link Bandwidth Management Interrupt Enable", reg, 1961 PCIE_LCSR_LBMIE); 1962 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 1963 PCIE_LCSR_LABIE); 1964 printf(" DRS Signaling Control: "); 1965 switch (__SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) { 1966 case 0: 1967 printf("not reported\n"); 1968 break; 1969 case 1: 1970 printf("Interrupt Enabled\n"); 1971 break; 1972 case 2: 1973 printf("DRS to FRS Signaling Enabled\n"); 1974 break; 1975 default: 1976 printf("reserved\n"); 1977 break; 1978 } 1979 1980 /* Link Status Register */ 1981 reg = regs[o2i(capoff + PCIE_LCSR)]; 1982 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1983 printf(" Negotiated Link Speed: "); 1984 pci_print_pcie_linkspeed(PCIE_LCSR, 1985 __SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 1986 printf(" Negotiated Link Width: x%u lanes\n", 1987 (unsigned int)__SHIFTOUT(reg, PCIE_LCSR_NLW)); 1988 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 1989 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 1990 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 1991 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 1992 onoff("Link Bandwidth Management Status", reg, 1993 PCIE_LCSR_LINK_BW_MGMT); 1994 onoff("Link Autonomous Bandwidth Status", reg, 1995 PCIE_LCSR_LINK_AUTO_BW); 1996 } 1997 1998 if (check_slot == true) { 1999 pcireg_t slcap; 2000 2001 /* Slot Capability Register */ 2002 slcap = reg = regs[o2i(capoff + PCIE_SLCAP)]; 2003 printf(" Slot Capability Register: 0x%08x\n", reg); 2004 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 2005 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 2006 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 2007 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 2008 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 2009 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 2010 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 2011 printf(" Slot Power Limit Value: "); 2012 pci_conf_print_pcie_power(__SHIFTOUT(reg, PCIE_SLCAP_SPLV), 2013 __SHIFTOUT(reg, PCIE_SLCAP_SPLS)); 2014 onoff("Electromechanical Interlock Present", reg, 2015 PCIE_SLCAP_EIP); 2016 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 2017 printf(" Physical Slot Number: %d\n", 2018 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 2019 2020 /* Slot Control Register */ 2021 reg = regs[o2i(capoff + PCIE_SLCSR)]; 2022 printf(" Slot Control Register: 0x%04x\n", reg & 0xffff); 2023 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 2024 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 2025 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 2026 onoff("Presence Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 2027 onoff("Command Completed Interrupt Enabled", reg, 2028 PCIE_SLCSR_CCE); 2029 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 2030 /* 2031 * For Attention Indicator Control and Power Indicator Control, 2032 * it's allowed to be a read only value 0 if corresponding 2033 * capability register bit is 0. 2034 */ 2035 if (slcap & PCIE_SLCAP_AIP) { 2036 printf(" Attention Indicator Control: "); 2037 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 2038 case 0x0: 2039 printf("reserved\n"); 2040 break; 2041 case PCIE_SLCSR_IND_ON: 2042 printf("on\n"); 2043 break; 2044 case PCIE_SLCSR_IND_BLINK: 2045 printf("blink\n"); 2046 break; 2047 case PCIE_SLCSR_IND_OFF: 2048 printf("off\n"); 2049 break; 2050 } 2051 } 2052 if (slcap & PCIE_SLCAP_PIP) { 2053 printf(" Power Indicator Control: "); 2054 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 2055 case 0x0: 2056 printf("reserved\n"); 2057 break; 2058 case PCIE_SLCSR_IND_ON: 2059 printf("on\n"); 2060 break; 2061 case PCIE_SLCSR_IND_BLINK: 2062 printf("blink\n"); 2063 break; 2064 case PCIE_SLCSR_IND_OFF: 2065 printf("off\n"); 2066 break; 2067 } 2068 } 2069 printf(" Power Controller Control: Power %s\n", 2070 reg & PCIE_SLCSR_PCC ? "off" : "on"); 2071 onoff("Electromechanical Interlock Control", 2072 reg, PCIE_SLCSR_EIC); 2073 onoff("Data Link Layer State Changed Enable", reg, 2074 PCIE_SLCSR_DLLSCE); 2075 onoff("Auto Slot Power Limit Disable", reg, 2076 PCIE_SLCSR_AUTOSPLDIS); 2077 2078 /* Slot Status Register */ 2079 printf(" Slot Status Register: 0x%04x\n", reg >> 16); 2080 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 2081 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 2082 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 2083 onoff("Presence Detect Changed", reg, PCIE_SLCSR_PDC); 2084 onoff("Command Completed", reg, PCIE_SLCSR_CC); 2085 onoff("MRL Open", reg, PCIE_SLCSR_MS); 2086 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 2087 onoff("Electromechanical Interlock engaged", reg, 2088 PCIE_SLCSR_EIS); 2089 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 2090 } 2091 2092 if (PCIE_HAS_ROOTREGS(pcie_devtype)) { 2093 /* Root Control Register */ 2094 reg = regs[o2i(capoff + PCIE_RCR)]; 2095 printf(" Root Control Register: 0x%04x\n", reg & 0xffff); 2096 onoff("SERR on Correctable Error Enable", reg, 2097 PCIE_RCR_SERR_CER); 2098 onoff("SERR on Non-Fatal Error Enable", reg, 2099 PCIE_RCR_SERR_NFER); 2100 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 2101 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 2102 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 2103 2104 /* Root Capability Register */ 2105 printf(" Root Capability Register: 0x%04x\n", 2106 reg >> 16); 2107 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 2108 2109 /* Root Status Register */ 2110 reg = regs[o2i(capoff + PCIE_RSR)]; 2111 printf(" Root Status Register: 0x%08x\n", reg); 2112 printf(" PME Requester ID: 0x%04x\n", 2113 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 2114 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 2115 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 2116 } 2117 2118 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2119 if (pciever < 2) 2120 return; 2121 2122 /* Device Capabilities 2 */ 2123 reg = regs[o2i(capoff + PCIE_DCAP2)]; 2124 printf(" Device Capabilities 2: 0x%08x\n", reg); 2125 printf(" Completion Timeout Ranges Supported: "); 2126 val = reg & PCIE_DCAP2_COMPT_RANGE; 2127 switch (val) { 2128 case 0: 2129 printf("not supported\n"); 2130 break; 2131 default: 2132 for (i = 0; i <= 3; i++) { 2133 if (((val >> i) & 0x01) != 0) 2134 printf("%c", 'A' + i); 2135 } 2136 printf("\n"); 2137 } 2138 onoff("Completion Timeout Disable Supported", reg, 2139 PCIE_DCAP2_COMPT_DIS); 2140 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 2141 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 2142 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 2143 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 2144 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 2145 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 2146 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 2147 printf(" TPH Completer Supported: "); 2148 switch (__SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) { 2149 case 0: 2150 printf("Not supported\n"); 2151 break; 2152 case 1: 2153 printf("TPH\n"); 2154 break; 2155 case 3: 2156 printf("TPH and Extended TPH\n"); 2157 break; 2158 default: 2159 printf("(reserved value)\n"); 2160 break; 2161 } 2162 printf(" LN System CLS: "); 2163 switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 2164 case 0x0: 2165 printf("Not supported or not in effect\n"); 2166 break; 2167 case 0x1: 2168 printf("64byte cachelines in effect\n"); 2169 break; 2170 case 0x2: 2171 printf("128byte cachelines in effect\n"); 2172 break; 2173 case 0x3: 2174 printf("Reserved\n"); 2175 break; 2176 } 2177 onoff("10-bit Tag Completer Supported", reg, PCIE_DCAP2_TBT_COMP); 2178 onoff("10-bit Tag Requester Supported", reg, PCIE_DCAP2_TBT_REQ); 2179 printf(" OBFF Supported: "); 2180 switch (__SHIFTOUT(reg, PCIE_DCAP2_OBFF)) { 2181 case 0x0: 2182 printf("Not supported\n"); 2183 break; 2184 case 0x1: 2185 printf("Message only\n"); 2186 break; 2187 case 0x2: 2188 printf("WAKE# only\n"); 2189 break; 2190 case 0x3: 2191 printf("Both\n"); 2192 break; 2193 } 2194 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 2195 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 2196 val = __SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP); 2197 printf(" Max End-End TLP Prefixes: %u\n", (val == 0) ? 4 : val); 2198 printf(" Emergency Power Reduction Supported: "); 2199 switch (__SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) { 2200 case 0x0: 2201 printf("Not supported\n"); 2202 break; 2203 case 0x1: 2204 printf("Device Specific mechanism\n"); 2205 break; 2206 case 0x2: 2207 printf("Form Factor spec or Device Specific mechanism\n"); 2208 break; 2209 case 0x3: 2210 printf("Reserved\n"); 2211 break; 2212 } 2213 onoff("Emergency Power Reduction Initialization Required", reg, 2214 PCIE_DCAP2_EMGPWRRED_INI); 2215 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 2216 2217 /* Device Control 2 */ 2218 reg = regs[o2i(capoff + PCIE_DCSR2)]; 2219 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 2220 printf(" Completion Timeout Value: "); 2221 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 2222 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 2223 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 2224 onoff("AtomicOp Requester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 2225 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 2226 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 2227 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 2228 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 2229 onoff("Emergency Power Reduction Request", reg, 2230 PCIE_DCSR2_EMGPWRRED_REQ); 2231 onoff("10-bit Tag Requester Enabled", reg, PCIE_DCSR2_TBT_REQ); 2232 printf(" OBFF: "); 2233 switch (__SHIFTOUT(reg, PCIE_DCSR2_OBFF_EN)) { 2234 case 0x0: 2235 printf("Disabled\n"); 2236 break; 2237 case 0x1: 2238 printf("Enabled with Message Signaling Variation A\n"); 2239 break; 2240 case 0x2: 2241 printf("Enabled with Message Signaling Variation B\n"); 2242 break; 2243 case 0x3: 2244 printf("Enabled using WAKE# signaling\n"); 2245 break; 2246 } 2247 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 2248 2249 if (PCIE_HAS_LINKREGS(pcie_devtype)) { 2250 bool drs_supported = false; 2251 2252 /* Link Capability 2 */ 2253 reg = regs[o2i(capoff + PCIE_LCAP2)]; 2254 /* If the vector is 0, LCAP2 is not implemented */ 2255 if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) { 2256 printf(" Link Capabilities 2: 0x%08x\n", reg); 2257 printf(" Supported Link Speeds Vector:"); 2258 pci_print_pcie_linkspeedvector( 2259 __SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 2260 printf("\n"); 2261 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 2262 printf(" " 2263 "Lower SKP OS Generation Supported Speed Vector:"); 2264 pci_print_pcie_linkspeedvector( 2265 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 2266 printf("\n"); 2267 printf(" " 2268 "Lower SKP OS Reception Supported Speed Vector:"); 2269 pci_print_pcie_linkspeedvector( 2270 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 2271 printf("\n"); 2272 onoff("Retimer Presence Detect Supported", reg, 2273 PCIE_LCAP2_RETIMERPD); 2274 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 2275 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 2276 } 2277 2278 /* Link Control 2 */ 2279 reg = regs[o2i(capoff + PCIE_LCSR2)]; 2280 /* If the vector is 0, LCAP2 is not implemented */ 2281 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 2282 printf(" Target Link Speed: "); 2283 pci_print_pcie_linkspeed(PCIE_LCSR2, 2284 __SHIFTOUT(reg, PCIE_LCSR2_TGT_LSPEED)); 2285 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 2286 onoff("HW Autonomous Speed Disabled", reg, 2287 PCIE_LCSR2_HW_AS_DIS); 2288 printf(" Selectable De-emphasis: "); 2289 pci_print_pcie_link_deemphasis( 2290 __SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP)); 2291 printf("\n"); 2292 printf(" Transmit Margin: %u\n", 2293 (unsigned int)__SHIFTOUT(reg, PCIE_LCSR2_TX_MARGIN)); 2294 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 2295 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 2296 printf(" Compliance Present/De-emphasis: "); 2297 pci_print_pcie_link_deemphasis( 2298 __SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP)); 2299 printf("\n"); 2300 2301 /* Link Status 2 */ 2302 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 2303 printf(" Current De-emphasis Level: "); 2304 pci_print_pcie_link_deemphasis( 2305 __SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL)); 2306 printf("\n"); 2307 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 2308 onoff("Equalization Phase 1 Successful", reg, 2309 PCIE_LCSR2_EQP1_SUC); 2310 onoff("Equalization Phase 2 Successful", reg, 2311 PCIE_LCSR2_EQP2_SUC); 2312 onoff("Equalization Phase 3 Successful", reg, 2313 PCIE_LCSR2_EQP3_SUC); 2314 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 2315 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 2316 if (drs_supported) { 2317 printf(" Downstream Component Presence: "); 2318 switch (__SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 2319 case PCIE_DSCOMPN_DOWN_NOTDETERM: 2320 printf("Link Down - Presence Not" 2321 " Determined\n"); 2322 break; 2323 case PCIE_DSCOMPN_DOWN_NOTPRES: 2324 printf("Link Down - Component Not Present\n"); 2325 break; 2326 case PCIE_DSCOMPN_DOWN_PRES: 2327 printf("Link Down - Component Present\n"); 2328 break; 2329 case PCIE_DSCOMPN_UP_PRES: 2330 printf("Link Up - Component Present\n"); 2331 break; 2332 case PCIE_DSCOMPN_UP_PRES_DRS: 2333 printf("Link Up - Component Present and DRS" 2334 " received\n"); 2335 break; 2336 default: 2337 printf("reserved\n"); 2338 break; 2339 } 2340 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 2341 } 2342 } 2343 2344 /* Slot Capability 2 */ 2345 /* Slot Control 2 */ 2346 /* Slot Status 2 */ 2347 } 2348 2349 static void 2350 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 2351 { 2352 pcireg_t reg; 2353 2354 printf("\n MSI-X Capability Register\n"); 2355 2356 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2357 printf(" Message Control register: 0x%04x\n", 2358 (reg >> 16) & 0xff); 2359 printf(" Table Size: %d\n", PCI_MSIX_CTL_TBLSIZE(reg)); 2360 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 2361 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 2362 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 2363 printf(" Table offset register: 0x%08x\n", reg); 2364 printf(" Table offset: 0x%08x\n", 2365 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 2366 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 2367 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 2368 printf(" Pending bit array register: 0x%08x\n", reg); 2369 printf(" Pending bit array offset: 0x%08x\n", 2370 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2371 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2372 } 2373 2374 static void 2375 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2376 { 2377 pcireg_t reg; 2378 2379 printf("\n Serial ATA Capability Register\n"); 2380 2381 reg = regs[o2i(capoff + PCI_SATA_REV)]; 2382 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2383 printf(" Revision: %u.%u\n", 2384 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2385 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2386 2387 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2388 2389 printf(" BAR Register: 0x%08x\n", reg); 2390 printf(" Register location: "); 2391 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2392 printf("in config space\n"); 2393 else { 2394 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2395 printf(" BAR offset: 0x%08x\n", 2396 (pcireg_t)__SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2397 } 2398 } 2399 2400 static void 2401 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2402 { 2403 pcireg_t reg; 2404 2405 printf("\n Advanced Features Capability Register\n"); 2406 2407 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2408 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2409 printf(" AF Structure Length: 0x%02x\n", 2410 (pcireg_t)__SHIFTOUT(reg, PCI_AF_LENGTH)); 2411 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2412 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2413 reg = regs[o2i(capoff + PCI_AFCSR)]; 2414 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2415 /* 2416 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2417 * and it's always 0 on read 2418 */ 2419 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2420 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2421 } 2422 2423 static void 2424 pci_conf_print_ea_cap_prop(unsigned int prop) 2425 { 2426 2427 switch (prop) { 2428 case PCI_EA_PROP_MEM_NONPREF: 2429 printf("Memory Space, Non-Prefetchable\n"); 2430 break; 2431 case PCI_EA_PROP_MEM_PREF: 2432 printf("Memory Space, Prefetchable\n"); 2433 break; 2434 case PCI_EA_PROP_IO: 2435 printf("I/O Space\n"); 2436 break; 2437 case PCI_EA_PROP_VF_MEM_NONPREF: 2438 printf("Resorce for VF use, Memory Space, Non-Prefetchable\n"); 2439 break; 2440 case PCI_EA_PROP_VF_MEM_PREF: 2441 printf("Resorce for VF use, Memory Space, Prefetch\n"); 2442 break; 2443 case PCI_EA_PROP_BB_MEM_NONPREF: 2444 printf("Behind the Bridge, Memory Space, Non-Pref\n"); 2445 break; 2446 case PCI_EA_PROP_BB_MEM_PREF: 2447 printf("Behind the Bridge, Memory Space. Prefetchable\n"); 2448 break; 2449 case PCI_EA_PROP_BB_IO: 2450 printf("Behind Bridge, I/O Space\n"); 2451 break; 2452 case PCI_EA_PROP_MEM_UNAVAIL: 2453 printf("Memory Space Unavailable\n"); 2454 break; 2455 case PCI_EA_PROP_IO_UNAVAIL: 2456 printf("IO Space Unavailable\n"); 2457 break; 2458 case PCI_EA_PROP_UNAVAIL: 2459 printf("Entry Unavailable for use\n"); 2460 break; 2461 default: 2462 printf("Reserved\n"); 2463 break; 2464 } 2465 } 2466 2467 static void 2468 pci_conf_print_ea_cap(const pcireg_t *regs, int capoff) 2469 { 2470 pcireg_t reg, reg2; 2471 unsigned int entries, entoff, i; 2472 2473 printf("\n Enhanced Allocation Capability Register\n"); 2474 2475 reg = regs[o2i(capoff + PCI_EA_CAP1)]; 2476 printf(" EA Num Entries register: 0x%04x\n", reg >> 16); 2477 entries = __SHIFTOUT(reg, PCI_EA_CAP1_NUMENTRIES); 2478 printf(" EA Num Entries: %u\n", entries); 2479 2480 /* Type 1 only */ 2481 if (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) == PCI_HDRTYPE_PPB) { 2482 reg = regs[o2i(capoff + PCI_EA_CAP2)]; 2483 printf(" EA Capability Second register: 0x%08x\n", reg); 2484 printf(" Fixed Secondary Bus Number: %hhu\n", 2485 (unsigned char)__SHIFTOUT(reg, PCI_EA_CAP2_SECONDARY)); 2486 printf(" Fixed Subordinate Bus Number: %hhu\n", 2487 (unsigned char)__SHIFTOUT(reg, PCI_EA_CAP2_SUBORDINATE)); 2488 entoff = capoff + 8; 2489 } else 2490 entoff = capoff + 4; 2491 2492 for (i = 0; i < entries; i++) { 2493 uint64_t base, offset; 2494 bool baseis64, offsetis64; 2495 unsigned int bei, entry_size; 2496 2497 printf(" Entry %u:\n", i); 2498 /* The first DW */ 2499 reg = regs[o2i(entoff)]; 2500 printf(" The first register: 0x%08x\n", reg); 2501 entry_size = __SHIFTOUT(reg, PCI_EA_ES); 2502 printf(" Entry size: %u\n", entry_size); 2503 printf(" BAR Equivalent Indicator: "); 2504 bei = __SHIFTOUT(reg, PCI_EA_BEI); 2505 switch (bei) { 2506 case PCI_EA_BEI_BAR0: 2507 case PCI_EA_BEI_BAR1: 2508 case PCI_EA_BEI_BAR2: 2509 case PCI_EA_BEI_BAR3: 2510 case PCI_EA_BEI_BAR4: 2511 case PCI_EA_BEI_BAR5: 2512 printf("BAR %u\n", bei - PCI_EA_BEI_BAR0); 2513 break; 2514 case PCI_EA_BEI_BEHIND: 2515 printf("Behind the function\n"); 2516 break; 2517 case PCI_EA_BEI_NOTIND: 2518 printf("Not Indicated\n"); 2519 break; 2520 case PCI_EA_BEI_EXPROM: 2521 printf("Expansion ROM\n"); 2522 break; 2523 case PCI_EA_BEI_VFBAR0: 2524 case PCI_EA_BEI_VFBAR1: 2525 case PCI_EA_BEI_VFBAR2: 2526 case PCI_EA_BEI_VFBAR3: 2527 case PCI_EA_BEI_VFBAR4: 2528 case PCI_EA_BEI_VFBAR5: 2529 printf("VF BAR %u\n", bei - PCI_EA_BEI_VFBAR0); 2530 break; 2531 case PCI_EA_BEI_RESERVED: 2532 default: 2533 printf("Reserved\n"); 2534 break; 2535 } 2536 2537 printf(" Primary Properties: "); 2538 pci_conf_print_ea_cap_prop(__SHIFTOUT(reg, PCI_EA_PP)); 2539 printf(" Secondary Properties: "); 2540 pci_conf_print_ea_cap_prop(__SHIFTOUT(reg, PCI_EA_SP)); 2541 onoff("Writable", reg, PCI_EA_W); 2542 onoff("Enable for this entry", reg, PCI_EA_E); 2543 2544 if (entry_size == 0) { 2545 entoff += 4; 2546 continue; 2547 } 2548 2549 /* Base addr */ 2550 reg = regs[o2i(entoff + 4)]; 2551 base = reg & PCI_EA_LOWMASK; 2552 baseis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT; 2553 printf(" Base Address Register Low: 0x%08x\n", reg); 2554 if (baseis64) { 2555 /* 64bit */ 2556 reg2 = regs[o2i(entoff + 12)]; 2557 printf(" Base Address Register high: 0x%08x\n", 2558 reg2); 2559 base |= (uint64_t)reg2 << 32; 2560 } 2561 2562 /* Offset addr */ 2563 reg = regs[o2i(entoff + 8)]; 2564 offset = reg & PCI_EA_LOWMASK; 2565 offsetis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT; 2566 printf(" Max Offset Register Low: 0x%08x\n", reg); 2567 if (offsetis64) { 2568 /* 64bit */ 2569 reg2 = regs[o2i(entoff + (baseis64 ? 16 : 12))]; 2570 printf(" Max Offset Register high: 0x%08x\n", 2571 reg2); 2572 offset |= (uint64_t)reg2 << 32; 2573 } 2574 2575 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 2576 "\n", base, base + offset); 2577 2578 entoff += 4; 2579 entoff += baseis64 ? 8 : 4; 2580 entoff += offsetis64 ? 8 : 4; 2581 } 2582 } 2583 2584 /* XXX pci_conf_print_fpb_cap */ 2585 2586 static struct { 2587 pcireg_t cap; 2588 const char *name; 2589 void (*printfunc)(const pcireg_t *, int); 2590 } pci_captab[] = { 2591 { PCI_CAP_RESERVED0, "reserved", NULL }, 2592 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2593 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2594 { PCI_CAP_VPD, "VPD", NULL }, 2595 { PCI_CAP_SLOTID, "SlotID", NULL }, 2596 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2597 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2598 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2599 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2600 { PCI_CAP_VENDSPEC, "Vendor-specific", 2601 pci_conf_print_vendspec_cap }, 2602 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2603 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2604 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2605 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2606 pci_conf_print_subsystem_cap }, 2607 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2608 { PCI_CAP_SECURE, "Secure Device", pci_conf_print_secure_cap }, 2609 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2610 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2611 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2612 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2613 { PCI_CAP_EA, "Enhanced Allocation", pci_conf_print_ea_cap }, 2614 { PCI_CAP_FPB, "Flattening Portal Bridge", NULL } 2615 }; 2616 2617 static int 2618 pci_conf_find_cap(const pcireg_t *regs, unsigned int capid, int *offsetp) 2619 { 2620 pcireg_t rval; 2621 unsigned int capptr; 2622 int off; 2623 2624 if (!(regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)) 2625 return 0; 2626 2627 /* Determine the Capability List Pointer register to start with. */ 2628 switch (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)])) { 2629 case 0: /* standard device header */ 2630 case 1: /* PCI-PCI bridge header */ 2631 capptr = PCI_CAPLISTPTR_REG; 2632 break; 2633 case 2: /* PCI-CardBus Bridge header */ 2634 capptr = PCI_CARDBUS_CAPLISTPTR_REG; 2635 break; 2636 default: 2637 return 0; 2638 } 2639 2640 for (off = PCI_CAPLIST_PTR(regs[o2i(capptr)]); 2641 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2642 rval = regs[o2i(off)]; 2643 if (capid == PCI_CAPLIST_CAP(rval)) { 2644 if (offsetp != NULL) 2645 *offsetp = off; 2646 return 1; 2647 } 2648 } 2649 return 0; 2650 } 2651 2652 static void 2653 pci_conf_print_caplist( 2654 #ifdef _KERNEL 2655 pci_chipset_tag_t pc, pcitag_t tag, 2656 #endif 2657 const pcireg_t *regs, int capoff) 2658 { 2659 int off; 2660 pcireg_t foundcap; 2661 pcireg_t rval; 2662 bool foundtable[__arraycount(pci_captab)]; 2663 unsigned int i; 2664 2665 /* Clear table */ 2666 for (i = 0; i < __arraycount(pci_captab); i++) 2667 foundtable[i] = false; 2668 2669 /* Print capability register's offset and the type first */ 2670 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2671 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2672 rval = regs[o2i(off)]; 2673 printf(" Capability register at 0x%02x\n", off); 2674 2675 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2676 foundcap = PCI_CAPLIST_CAP(rval); 2677 if (foundcap < __arraycount(pci_captab)) { 2678 printf("%s)\n", pci_captab[foundcap].name); 2679 /* Mark as found */ 2680 foundtable[foundcap] = true; 2681 } else 2682 printf("unknown)\n"); 2683 } 2684 2685 /* 2686 * And then, print the detail of each capability registers 2687 * in capability value's order. 2688 */ 2689 for (i = 0; i < __arraycount(pci_captab); i++) { 2690 if (foundtable[i] == false) 2691 continue; 2692 2693 /* 2694 * The type was found. Search capability list again and 2695 * print all capabilities that the capabiliy type is 2696 * the same. This is required because some capabilities 2697 * appear multiple times (e.g. HyperTransport capability). 2698 */ 2699 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2700 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2701 rval = regs[o2i(off)]; 2702 if ((PCI_CAPLIST_CAP(rval) == i) 2703 && (pci_captab[i].printfunc != NULL)) 2704 pci_captab[i].printfunc(regs, off); 2705 } 2706 } 2707 } 2708 2709 /* Extended Capability */ 2710 2711 static void 2712 pci_conf_print_aer_cap_uc(pcireg_t reg) 2713 { 2714 2715 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2716 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2717 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2718 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2719 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2720 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2721 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2722 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2723 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2724 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2725 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2726 onoff("Unsupported Request Error", reg, 2727 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2728 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2729 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2730 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2731 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2732 onoff("TLP Prefix Blocked Error", reg, 2733 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2734 onoff("Poisoned TLP Egress Blocked", reg, 2735 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2736 } 2737 2738 static void 2739 pci_conf_print_aer_cap_cor(pcireg_t reg) 2740 { 2741 2742 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2743 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2744 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2745 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2746 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2747 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2748 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2749 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2750 } 2751 2752 static void 2753 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2754 { 2755 2756 printf(" First Error Pointer: 0x%04x\n", 2757 (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2758 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2759 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2760 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2761 onoff("ECRC Check Enable", reg, PCI_AER_ECRC_CHECK_ENABLE); 2762 onoff("Multiple Header Recording Capable", reg, 2763 PCI_AER_MULT_HDR_CAPABLE); 2764 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2765 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2766 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2767 2768 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2769 if (!tlp_prefix_log) 2770 return; 2771 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2772 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2773 } 2774 2775 static void 2776 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2777 { 2778 2779 onoff("Correctable Error Reporting Enable", reg, 2780 PCI_AER_ROOTERR_COR_ENABLE); 2781 onoff("Non-Fatal Error Reporting Enable", reg, 2782 PCI_AER_ROOTERR_NF_ENABLE); 2783 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2784 } 2785 2786 static void 2787 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2788 { 2789 2790 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2791 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2792 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2793 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2794 PCI_AER_ROOTERR_MULTI_UC_ERR); 2795 onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL); 2796 onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR); 2797 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2798 printf(" Advanced Error Interrupt Message Number: 0x%02x\n", 2799 (unsigned int)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2800 } 2801 2802 static void 2803 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2804 { 2805 2806 printf(" Correctable Source ID: 0x%04x\n", 2807 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2808 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2809 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2810 } 2811 2812 static void 2813 pci_conf_print_aer_cap(const pcireg_t *regs, int extcapoff) 2814 { 2815 pcireg_t reg; 2816 int pcie_capoff; 2817 int pcie_devtype = -1; 2818 bool tlp_prefix_log = false; 2819 2820 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2821 reg = regs[o2i(pcie_capoff)]; 2822 pcie_devtype = PCIE_XCAP_TYPE(reg); 2823 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2824 if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2825 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2826 /* End-End TLP Prefix Supported */ 2827 if (reg & PCIE_DCAP2_EETLP_PREF) { 2828 tlp_prefix_log = true; 2829 } 2830 } 2831 } 2832 2833 printf("\n Advanced Error Reporting Register\n"); 2834 2835 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2836 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2837 pci_conf_print_aer_cap_uc(reg); 2838 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2839 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2840 pci_conf_print_aer_cap_uc(reg); 2841 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2842 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2843 pci_conf_print_aer_cap_uc(reg); 2844 2845 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2846 printf(" Correctable Error Status register: 0x%08x\n", reg); 2847 pci_conf_print_aer_cap_cor(reg); 2848 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2849 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2850 pci_conf_print_aer_cap_cor(reg); 2851 2852 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2853 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2854 reg); 2855 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2856 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2857 printf(" Header Log register:\n"); 2858 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2859 extcapoff + PCI_AER_ROOTERR_CMD); 2860 2861 switch (pcie_devtype) { 2862 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2863 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2864 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2865 printf(" Root Error Command register: 0x%08x\n", reg); 2866 pci_conf_print_aer_cap_rooterr_cmd(reg); 2867 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2868 printf(" Root Error Status register: 0x%08x\n", reg); 2869 pci_conf_print_aer_cap_rooterr_status(reg); 2870 2871 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2872 printf(" Error Source Identification register: 0x%08x\n", 2873 reg); 2874 pci_conf_print_aer_cap_errsrc_id(reg); 2875 break; 2876 } 2877 2878 if (tlp_prefix_log) { 2879 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2880 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2881 } 2882 } 2883 2884 /* 2885 * Helper function to print the arbitration phase register. 2886 * 2887 * phases: Number of phases in the arbitration tables. 2888 * arbsize: Number of bits in each phase. 2889 * indent: Add more two spaces if it's true. 2890 */ 2891 static void 2892 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2893 const int phases, int arbsize, bool indent) 2894 { 2895 pcireg_t reg; 2896 int num_per_reg = 32 / arbsize; 2897 int i, j; 2898 2899 printf("%s %s Arbitration Table:\n", indent ? " " : "", name); 2900 for (i = 0; i < phases; i += num_per_reg) { 2901 reg = regs[o2i(off + (sizeof(uint32_t) * (i / num_per_reg)))]; 2902 for (j = 0; j < num_per_reg; j++) { 2903 printf("%s Phase[%d]: 0x%x\n", indent ? " " : "", 2904 i + j, 2905 (uint32_t)(reg & __BITS(arbsize - 1, 0))); 2906 reg >>= arbsize; 2907 } 2908 } 2909 } 2910 2911 /* For VC, bit 4-7 are reserved. For Port, bit 6-7 are reserved */ 2912 static const int arb_phases[8] = {0, 32, 64, 128, 128, 256, 0, 0 }; 2913 2914 static void 2915 pci_conf_print_vc_cap(const pcireg_t *regs, int extcapoff) 2916 { 2917 pcireg_t reg, n; 2918 int arbtab, parbsize; 2919 pcireg_t arbsel; 2920 int i, count; 2921 2922 printf("\n Virtual Channel Register\n"); 2923 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2924 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2925 count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2926 printf(" Extended VC Count: %d\n", count); 2927 n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2928 printf(" Low Priority Extended VC Count: %u\n", n); 2929 n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2930 printf(" Reference Clock: %s\n", 2931 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 2932 parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2933 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2934 2935 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2936 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2937 onoff("Hardware fixed arbitration scheme", 2938 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2939 onoff("WRR arbitration with 32 phases", 2940 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2941 onoff("WRR arbitration with 64 phases", 2942 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2943 onoff("WRR arbitration with 128 phases", 2944 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2945 arbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2946 printf(" VC Arbitration Table Offset: 0x%x\n", arbtab); 2947 2948 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2949 printf(" Port VC Control register: 0x%04x\n", reg); 2950 arbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2951 printf(" VC Arbitration Select: 0x%x\n", arbsel); 2952 2953 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2954 printf(" Port VC Status register: 0x%04x\n", reg); 2955 onoff("VC Arbitration Table Status", 2956 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 2957 2958 if ((arbtab != 0) && (arbsel != 0)) 2959 pci_conf_print_vc_cap_arbtab(regs, extcapoff + (arbtab * 16), 2960 "VC", arb_phases[arbsel], 4, false); 2961 2962 for (i = 0; i < count + 1; i++) { 2963 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 2964 printf(" VC number %d\n", i); 2965 printf(" VC Resource Capability Register: 0x%08x\n", reg); 2966 onoff(" Non-configurable Hardware fixed arbitration scheme", 2967 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 2968 onoff(" WRR arbitration with 32 phases", 2969 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 2970 onoff(" WRR arbitration with 64 phases", 2971 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 2972 onoff(" WRR arbitration with 128 phases", 2973 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 2974 onoff(" Time-based WRR arbitration with 128 phases", 2975 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 2976 onoff(" WRR arbitration with 256 phases", 2977 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 2978 onoff(" Advanced Packet Switching", 2979 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 2980 onoff(" Reject Snoop Transaction", 2981 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 2982 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 2983 printf(" Maximum Time Slots: %d\n", n); 2984 arbtab = __SHIFTOUT(reg, 2985 PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET); 2986 printf(" Port Arbitration Table offset: 0x%02x\n", 2987 arbtab); 2988 2989 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 2990 printf(" VC Resource Control Register: 0x%08x\n", reg); 2991 printf(" TC/VC Map: 0x%02x\n", 2992 (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 2993 /* 2994 * The load Port Arbitration Table bit is used to update 2995 * the Port Arbitration logic and it's always 0 on read, so 2996 * we don't print it. 2997 */ 2998 arbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 2999 printf(" Port Arbitration Select: 0x%x\n", arbsel); 3000 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 3001 printf(" VC ID: %d\n", n); 3002 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 3003 3004 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 3005 printf(" VC Resource Status Register: 0x%08x\n", reg); 3006 onoff(" Port Arbitration Table Status", 3007 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 3008 onoff(" VC Negotiation Pending", 3009 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 3010 3011 if ((arbtab != 0) && (arbsel != 0)) 3012 pci_conf_print_vc_cap_arbtab(regs, 3013 extcapoff + (arbtab * 16), 3014 "Port", arb_phases[arbsel], parbsize, true); 3015 } 3016 } 3017 3018 /* 3019 * Print Power limit. This encoding is the same among the following registers: 3020 * - The Captured Slot Power Limit in the PCIe Device Capability Register. 3021 * - The Slot Power Limit in the PCIe Slot Capability Register. 3022 * - The Base Power in the Data register of Power Budgeting capability. 3023 */ 3024 static void 3025 pci_conf_print_pcie_power(uint8_t base, unsigned int scale) 3026 { 3027 unsigned int sdiv = 1; 3028 3029 if ((scale == 0) && (base > 0xef)) { 3030 const char *s; 3031 3032 switch (base) { 3033 case 0xf0: 3034 s = "239W < x <= 250W"; 3035 break; 3036 case 0xf1: 3037 s = "250W < x <= 275W"; 3038 break; 3039 case 0xf2: 3040 s = "275W < x <= 300W"; 3041 break; 3042 default: 3043 s = "reserved for greater than 300W"; 3044 break; 3045 } 3046 printf("%s\n", s); 3047 return; 3048 } 3049 3050 for (unsigned int i = scale; i > 0; i--) 3051 sdiv *= 10; 3052 3053 printf("%u", base / sdiv); 3054 3055 if (scale != 0) { 3056 printf(".%u", base % sdiv); 3057 } 3058 printf ("W\n"); 3059 return; 3060 } 3061 3062 static const char * 3063 pci_conf_print_pwrbdgt_type(uint8_t reg) 3064 { 3065 3066 switch (reg) { 3067 case 0x00: 3068 return "PME Aux"; 3069 case 0x01: 3070 return "Auxilary"; 3071 case 0x02: 3072 return "Idle"; 3073 case 0x03: 3074 return "Sustained"; 3075 case 0x04: 3076 return "Sustained (Emergency Power Reduction)"; 3077 case 0x05: 3078 return "Maximum (Emergency Power Reduction)"; 3079 case 0x07: 3080 return "Maximum"; 3081 default: 3082 return "Unknown"; 3083 } 3084 } 3085 3086 static const char * 3087 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 3088 { 3089 3090 switch (reg) { 3091 case 0x00: 3092 return "Power(12V)"; 3093 case 0x01: 3094 return "Power(3.3V)"; 3095 case 0x02: 3096 return "Power(1.5V or 1.8V)"; 3097 case 0x07: 3098 return "Thermal"; 3099 default: 3100 return "Unknown"; 3101 } 3102 } 3103 3104 static void 3105 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int extcapoff) 3106 { 3107 pcireg_t reg; 3108 3109 printf("\n Power Budgeting\n"); 3110 3111 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 3112 printf(" Data Select register: 0x%08x\n", reg); 3113 3114 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 3115 printf(" Data register: 0x%08x\n", reg); 3116 printf(" Base Power: "); 3117 pci_conf_print_pcie_power( 3118 __SHIFTOUT(reg, PCI_PWRBDGT_DATA_BASEPWR), 3119 __SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE)); 3120 printf(" PM Sub State: 0x%hhx\n", 3121 (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 3122 printf(" PM State: D%u\n", 3123 (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 3124 printf(" Type: %s\n", 3125 pci_conf_print_pwrbdgt_type( 3126 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 3127 printf(" Power Rail: %s\n", 3128 pci_conf_print_pwrbdgt_pwrrail( 3129 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 3130 3131 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 3132 printf(" Power Budget Capability register: 0x%08x\n", reg); 3133 onoff("System Allocated", 3134 reg, PCI_PWRBDGT_CAP_SYSALLOC); 3135 } 3136 3137 static const char * 3138 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 3139 { 3140 3141 switch (type) { 3142 case 0x00: 3143 return "Configuration Space Element"; 3144 case 0x01: 3145 return "System Egress Port or internal sink (memory)"; 3146 case 0x02: 3147 return "Internal Root Complex Link"; 3148 default: 3149 return "Unknown"; 3150 } 3151 } 3152 3153 static void 3154 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int extcapoff) 3155 { 3156 pcireg_t reg; 3157 unsigned char nent, linktype; 3158 int i; 3159 3160 printf("\n Root Complex Link Declaration\n"); 3161 3162 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 3163 printf(" Element Self Description Register: 0x%08x\n", reg); 3164 printf(" Element Type: %s\n", 3165 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 3166 nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 3167 printf(" Number of Link Entries: %hhu\n", nent); 3168 printf(" Component ID: %hhu\n", 3169 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 3170 printf(" Port Number: %hhu\n", 3171 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 3172 for (i = 0; i < nent; i++) { 3173 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 3174 printf(" Link Entry %d:\n", i + 1); 3175 printf(" Link Description Register: 0x%08x\n", reg); 3176 onoff(" Link Valid", reg, PCI_RCLINK_DCL_LINKDESC_LVALID); 3177 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 3178 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 3179 "Configuration Space", "Memory-Mapped Space"); 3180 onoff(" Associated RCRB Header", reg, 3181 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 3182 printf(" Target Component ID: %hhu\n", 3183 (unsigned char)__SHIFTOUT(reg, 3184 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 3185 printf(" Target Port Number: %hhu\n", 3186 (unsigned char)__SHIFTOUT(reg, 3187 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 3188 3189 if (linktype == 0) { 3190 /* Memory-Mapped Space */ 3191 reg = regs[o2i(extcapoff 3192 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 3193 printf(" Link Address Low Register: 0x%08x\n", 3194 reg); 3195 reg = regs[o2i(extcapoff 3196 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 3197 printf(" Link Address High Register: 0x%08x\n", 3198 reg); 3199 } else { 3200 unsigned int nb; 3201 pcireg_t lo, hi; 3202 3203 /* Configuration Space */ 3204 lo = regs[o2i(extcapoff 3205 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 3206 printf(" Configuration Space Low Register: " 3207 "0x%08x\n", lo); 3208 hi = regs[o2i(extcapoff 3209 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 3210 printf(" Configuration Space High Register: " 3211 "0x%08x\n", hi); 3212 nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 3213 printf(" N: %u\n", nb); 3214 printf(" Func: %hhu\n", 3215 (unsigned char)__SHIFTOUT(lo, 3216 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 3217 printf(" Dev: %hhu\n", 3218 (unsigned char)__SHIFTOUT(lo, 3219 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 3220 printf(" Bus: %hhu\n", 3221 (unsigned char)__SHIFTOUT(lo, 3222 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 3223 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 3224 printf(" Configuration Space Base Address: " 3225 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 3226 } 3227 } 3228 } 3229 3230 /* XXX pci_conf_print_rclink_ctl_cap */ 3231 3232 static void 3233 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int extcapoff) 3234 { 3235 pcireg_t reg; 3236 3237 printf("\n Root Complex Event Collector Association\n"); 3238 3239 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 3240 printf(" Association Bitmap for Root Complex Integrated Devices:" 3241 " 0x%08x\n", reg); 3242 3243 if (PCI_EXTCAPLIST_VERSION(regs[o2i(extcapoff)]) >= 2) { 3244 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBUSNUM)]; 3245 printf(" RCEC Associated Bus Numbers register: 0x%08x\n", 3246 reg); 3247 printf(" RCEC Next Bus: %u\n", 3248 (unsigned int)__SHIFTOUT(reg, 3249 PCI_RCEC_ASSOCBUSNUM_RCECNEXT)); 3250 printf(" RCEC Last Bus: %u\n", 3251 (unsigned int)__SHIFTOUT(reg, 3252 PCI_RCEC_ASSOCBUSNUM_RCECLAST)); 3253 } 3254 } 3255 3256 /* XXX pci_conf_print_mfvc_cap */ 3257 /* XXX pci_conf_print_vc2_cap */ 3258 /* XXX pci_conf_print_rcrb_cap */ 3259 /* XXX pci_conf_print_vendor_cap */ 3260 /* XXX pci_conf_print_cac_cap */ 3261 3262 static void 3263 pci_conf_print_acs_cap(const pcireg_t *regs, int extcapoff) 3264 { 3265 pcireg_t reg, cap, ctl; 3266 unsigned int size, i; 3267 3268 printf("\n Access Control Services\n"); 3269 3270 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 3271 cap = reg & 0xffff; 3272 ctl = reg >> 16; 3273 printf(" ACS Capability register: 0x%08x\n", cap); 3274 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 3275 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 3276 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 3277 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 3278 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 3279 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 3280 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 3281 size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 3282 if (size == 0) 3283 size = 256; 3284 printf(" Egress Control Vector Size: %u\n", size); 3285 printf(" ACS Control register: 0x%08x\n", ctl); 3286 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 3287 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 3288 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 3289 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 3290 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 3291 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 3292 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 3293 3294 /* 3295 * If the P2P Egress Control Capability bit is 0, ignore the Egress 3296 * Control vector. 3297 */ 3298 if ((cap & PCI_ACS_CAP_E) == 0) 3299 return; 3300 for (i = 0; i < size; i += 32) 3301 printf(" Egress Control Vector [%u..%u]: 0x%08x\n", i + 31, 3302 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 3303 } 3304 3305 static void 3306 pci_conf_print_ari_cap(const pcireg_t *regs, int extcapoff) 3307 { 3308 pcireg_t reg, cap, ctl; 3309 3310 printf("\n Alternative Routing-ID Interpretation Register\n"); 3311 3312 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3313 cap = reg & 0xffff; 3314 ctl = reg >> 16; 3315 printf(" Capability register: 0x%08x\n", cap); 3316 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 3317 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 3318 printf(" Next Function Number: %u\n", 3319 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 3320 printf(" Control register: 0x%08x\n", ctl); 3321 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 3322 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 3323 printf(" Function Group: %u\n", 3324 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 3325 } 3326 3327 static void 3328 pci_conf_print_ats_cap(const pcireg_t *regs, int extcapoff) 3329 { 3330 pcireg_t reg, cap, ctl; 3331 unsigned int num; 3332 3333 printf("\n Address Translation Services\n"); 3334 3335 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3336 cap = reg & 0xffff; 3337 ctl = reg >> 16; 3338 printf(" Capability register: 0x%04x\n", cap); 3339 num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 3340 if (num == 0) 3341 num = 32; 3342 printf(" Invalidate Queue Depth: %u\n", num); 3343 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 3344 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 3345 onoff("Relaxed Ordering", reg, PCI_ATS_CAP_RELAXORD); 3346 3347 printf(" Control register: 0x%04x\n", ctl); 3348 printf(" Smallest Translation Unit: %u\n", 3349 (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU)); 3350 onoff("Enable", reg, PCI_ATS_CTL_EN); 3351 } 3352 3353 static void 3354 pci_conf_print_sernum_cap(const pcireg_t *regs, int extcapoff) 3355 { 3356 pcireg_t lo, hi; 3357 3358 printf("\n Device Serial Number Register\n"); 3359 3360 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 3361 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 3362 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 3363 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 3364 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 3365 } 3366 3367 static void 3368 pci_conf_print_sriov_cap(const pcireg_t *regs, int extcapoff) 3369 { 3370 char buf[sizeof("99999 MB")]; 3371 pcireg_t reg; 3372 pcireg_t total_vfs; 3373 int i; 3374 bool first; 3375 3376 printf("\n Single Root IO Virtualization Register\n"); 3377 3378 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 3379 printf(" Capabilities register: 0x%08x\n", reg); 3380 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 3381 onoff("ARI Capable Hierarchy Preserved", reg, 3382 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 3383 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 3384 printf(" VF Migration Interrupt Message Number: 0x%03x\n", 3385 (pcireg_t)__SHIFTOUT(reg, 3386 PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 3387 } 3388 3389 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 3390 printf(" Control register: 0x%04x\n", reg); 3391 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 3392 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 3393 onoff("VF Migration Interrupt Enable", reg, 3394 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 3395 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 3396 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 3397 3398 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 3399 printf(" Status register: 0x%04x\n", reg); 3400 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 3401 3402 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 3403 printf(" InitialVFs register: 0x%04x\n", reg); 3404 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 3405 printf(" TotalVFs register: 0x%04x\n", reg); 3406 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 3407 printf(" NumVFs register: 0x%04x\n", reg); 3408 3409 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 3410 printf(" Function Dependency Link register: 0x%04x\n", reg); 3411 3412 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 3413 printf(" First VF Offset register: 0x%04x\n", reg); 3414 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 3415 printf(" VF Stride register: 0x%04x\n", reg); 3416 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16; 3417 printf(" Device ID: 0x%04x\n", reg); 3418 3419 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 3420 printf(" Supported Page Sizes register: 0x%08x\n", reg); 3421 printf(" Supported Page Size:"); 3422 for (i = 0, first = true; i < 32; i++) { 3423 if (reg & __BIT(i)) { 3424 #ifdef _KERNEL 3425 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 3426 #else 3427 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 3428 HN_AUTOSCALE, 0); 3429 #endif 3430 printf("%s %s", first ? "" : ",", buf); 3431 first = false; 3432 } 3433 } 3434 printf("\n"); 3435 3436 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 3437 printf(" System Page Sizes register: 0x%08x\n", reg); 3438 printf(" Page Size: "); 3439 if (reg != 0) { 3440 int bitpos = ffs(reg) -1; 3441 3442 /* Assume only one bit is set. */ 3443 #ifdef _KERNEL 3444 format_bytes(buf, sizeof(buf), 1LL << (bitpos + 12)); 3445 #else 3446 humanize_number(buf, sizeof(buf), 1LL << (bitpos + 12), 3447 "B", HN_AUTOSCALE, 0); 3448 #endif 3449 printf("%s", buf); 3450 } else { 3451 printf("unknown"); 3452 } 3453 printf("\n"); 3454 3455 for (i = 0; i < 6; i++) { 3456 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 3457 printf(" VF BAR%d register: 0x%08x\n", i, reg); 3458 } 3459 3460 if (total_vfs > 0) { 3461 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 3462 printf(" VF Migration State Array Offset register: 0x%08x\n", 3463 reg); 3464 printf(" VF Migration State Offset: 0x%08x\n", 3465 (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 3466 i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 3467 printf(" VF Migration State BIR: "); 3468 if (i >= 0 && i <= 5) { 3469 printf("BAR%d", i); 3470 } else { 3471 printf("unknown BAR (%d)", i); 3472 } 3473 printf("\n"); 3474 } 3475 } 3476 3477 /* XXX pci_conf_print_mriov_cap */ 3478 3479 static void 3480 pci_conf_print_multicast_cap(const pcireg_t *regs, int extcapoff) 3481 { 3482 pcireg_t reg, cap, ctl; 3483 pcireg_t regl, regh; 3484 uint64_t addr; 3485 int n; 3486 3487 printf("\n Multicast\n"); 3488 3489 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 3490 cap = reg & 0xffff; 3491 ctl = reg >> 16; 3492 printf(" Capability Register: 0x%04x\n", cap); 3493 printf(" Max Group: %u\n", 3494 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 3495 3496 /* Endpoint Only */ 3497 n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 3498 if (n > 0) 3499 printf(" Windw Size Requested: %d\n", 1 << (n - 1)); 3500 3501 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 3502 3503 printf(" Control Register: 0x%04x\n", ctl); 3504 printf(" Num Group: %u\n", 3505 (unsigned int)__SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 3506 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 3507 3508 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 3509 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 3510 printf(" Base Address Register 0: 0x%08x\n", regl); 3511 printf(" Base Address Register 1: 0x%08x\n", regh); 3512 printf(" Index Position: %u\n", 3513 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 3514 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 3515 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 3516 3517 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 3518 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 3519 printf(" Receive Register 0: 0x%08x\n", regl); 3520 printf(" Receive Register 1: 0x%08x\n", regh); 3521 3522 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 3523 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 3524 printf(" Block All Register 0: 0x%08x\n", regl); 3525 printf(" Block All Register 1: 0x%08x\n", regh); 3526 3527 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 3528 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 3529 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 3530 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 3531 3532 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 3533 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 3534 printf(" Overlay BAR 0: 0x%08x\n", regl); 3535 printf(" Overlay BAR 1: 0x%08x\n", regh); 3536 3537 n = regl & PCI_MCAST_OVERLAYL_SIZE; 3538 printf(" Overlay Size: "); 3539 if (n >= 6) 3540 printf("%d\n", n); 3541 else 3542 printf("off\n"); 3543 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 3544 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 3545 } 3546 3547 static void 3548 pci_conf_print_page_req_cap(const pcireg_t *regs, int extcapoff) 3549 { 3550 pcireg_t reg, ctl, sta; 3551 3552 printf("\n Page Request\n"); 3553 3554 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 3555 ctl = reg & 0xffff; 3556 sta = reg >> 16; 3557 printf(" Control Register: 0x%04x\n", ctl); 3558 onoff("Enable", reg, PCI_PAGE_REQ_CTL_E); 3559 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 3560 3561 printf(" Status Register: 0x%04x\n", sta); 3562 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 3563 onoff("Unexpected Page Request Group Index", reg, 3564 PCI_PAGE_REQ_STA_UPRGI); 3565 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 3566 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 3567 3568 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 3569 printf(" Outstanding Page Request Capacity: %u\n", reg); 3570 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 3571 printf(" Outstanding Page Request Allocation: %u\n", reg); 3572 } 3573 3574 /* XXX pci_conf_print_amd_cap */ 3575 3576 #define MEM_PBUFSIZE sizeof("999GB") 3577 3578 static void 3579 pci_conf_print_resizbar_cap(const pcireg_t *regs, int extcapoff) 3580 { 3581 pcireg_t cap, ctl; 3582 unsigned int bars, i, n; 3583 char pbuf[MEM_PBUFSIZE]; 3584 3585 printf("\n Resizable BAR\n"); 3586 3587 /* Get Number of Resizable BARs */ 3588 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))]; 3589 bars = __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR); 3590 printf(" Number of Resizable BARs: "); 3591 if (bars <= 6) 3592 printf("%u\n", bars); 3593 else { 3594 printf("incorrect (%u)\n", bars); 3595 return; 3596 } 3597 3598 for (n = 0; n < 6; n++) { 3599 cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))]; 3600 printf(" Capability register(%u): 0x%08x\n", n, cap); 3601 if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0) 3602 continue; /* Not Used */ 3603 printf(" Acceptable BAR sizes:"); 3604 for (i = 4; i <= 23; i++) { 3605 if ((cap & (1 << i)) != 0) { 3606 humanize_number(pbuf, MEM_PBUFSIZE, 3607 (int64_t)1024 * 1024 << (i - 4), "B", 3608 #ifdef _KERNEL 3609 1); 3610 #else 3611 HN_AUTOSCALE, HN_NOSPACE); 3612 #endif 3613 printf(" %s", pbuf); 3614 } 3615 } 3616 printf("\n"); 3617 3618 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))]; 3619 printf(" Control register(%u): 0x%08x\n", n, ctl); 3620 printf(" BAR Index: %u\n", 3621 (unsigned int)__SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX)); 3622 humanize_number(pbuf, MEM_PBUFSIZE, 3623 (int64_t)1024 * 1024 3624 << __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ), 3625 "B", 3626 #ifdef _KERNEL 3627 1); 3628 #else 3629 HN_AUTOSCALE, HN_NOSPACE); 3630 #endif 3631 printf(" BAR Size: %s\n", pbuf); 3632 } 3633 } 3634 3635 static void 3636 pci_conf_print_dpa_cap(const pcireg_t *regs, int extcapoff) 3637 { 3638 pcireg_t reg; 3639 unsigned int substmax, i; 3640 3641 printf("\n Dynamic Power Allocation\n"); 3642 3643 reg = regs[o2i(extcapoff + PCI_DPA_CAP)]; 3644 printf(" Capability register: 0x%08x\n", reg); 3645 substmax = __SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX); 3646 printf(" Substate Max: %u\n", substmax); 3647 printf(" Transition Latency Unit: "); 3648 switch (__SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) { 3649 case 0: 3650 printf("1ms\n"); 3651 break; 3652 case 1: 3653 printf("10ms\n"); 3654 break; 3655 case 2: 3656 printf("100ms\n"); 3657 break; 3658 default: 3659 printf("reserved\n"); 3660 break; 3661 } 3662 printf(" Power Allocation Scale: "); 3663 switch (__SHIFTOUT(reg, PCI_DPA_CAP_PAS)) { 3664 case 0: 3665 printf("10.0x\n"); 3666 break; 3667 case 1: 3668 printf("1.0x\n"); 3669 break; 3670 case 2: 3671 printf("0.1x\n"); 3672 break; 3673 case 3: 3674 printf("0.01x\n"); 3675 break; 3676 } 3677 printf(" Transition Latency Value 0: %u\n", 3678 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY0)); 3679 printf(" Transition Latency Value 1: %u\n", 3680 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); 3681 3682 reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; 3683 printf(" Latency Indicatior register: 0x%08x\n", reg); 3684 3685 reg = regs[o2i(extcapoff + PCI_DPA_CS)]; 3686 printf(" Status register: 0x%04x\n", reg & 0xffff); 3687 printf(" Substate Status: 0x%02x\n", 3688 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT)); 3689 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN); 3690 printf(" Control register: 0x%04x\n", reg >> 16); 3691 printf(" Substate Control: 0x%02x\n", 3692 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL)); 3693 3694 for (i = 0; i <= substmax; i++) 3695 printf(" Substate Power Allocation register %d: 0x%02x\n", 3696 i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff)); 3697 } 3698 3699 static const char * 3700 pci_conf_print_tph_req_cap_sttabloc(uint8_t val) 3701 { 3702 3703 switch (val) { 3704 case PCI_TPH_REQ_STTBLLOC_NONE: 3705 return "Not Present"; 3706 case PCI_TPH_REQ_STTBLLOC_TPHREQ: 3707 return "in the TPH Requester Capability Structure"; 3708 case PCI_TPH_REQ_STTBLLOC_MSIX: 3709 return "in the MSI-X Table"; 3710 default: 3711 return "Unknown"; 3712 } 3713 } 3714 3715 static void 3716 pci_conf_print_tph_req_cap(const pcireg_t *regs, int extcapoff) 3717 { 3718 pcireg_t reg; 3719 int size = 0, i, j; 3720 uint8_t sttbloc; 3721 3722 printf("\n TPH Requester Extended Capability\n"); 3723 3724 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3725 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3726 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3727 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3728 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3729 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3730 sttbloc = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC); 3731 printf(" ST Table Location: %s\n", 3732 pci_conf_print_tph_req_cap_sttabloc(sttbloc)); 3733 if (sttbloc == PCI_TPH_REQ_STTBLLOC_TPHREQ) { 3734 size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3735 printf(" ST Table Size: %d\n", size); 3736 } 3737 3738 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CTL)]; 3739 printf(" TPH Requester Control register: 0x%08x\n", reg); 3740 printf(" ST Mode Select: "); 3741 switch (__SHIFTOUT(reg, PCI_TPH_REQ_CTL_STSEL)) { 3742 case PCI_TPH_REQ_CTL_STSEL_NO: 3743 printf("No ST Mode\n"); 3744 break; 3745 case PCI_TPH_REQ_CTL_STSEL_IV: 3746 printf("Interrupt Vector Mode\n"); 3747 break; 3748 case PCI_TPH_REQ_CTL_STSEL_DS: 3749 printf("Device Specific Mode\n"); 3750 break; 3751 default: 3752 printf("(reserved value)\n"); 3753 break; 3754 } 3755 printf(" TPH Requester Enable: "); 3756 switch (__SHIFTOUT(reg, PCI_TPH_REQ_CTL_TPHREQEN)) { 3757 case PCI_TPH_REQ_CTL_TPHREQEN_NO: /* 0x0 */ 3758 printf("Not permitted\n"); 3759 break; 3760 case PCI_TPH_REQ_CTL_TPHREQEN_TPH: 3761 printf("TPH and not Extended TPH\n"); 3762 break; 3763 case PCI_TPH_REQ_CTL_TPHREQEN_ETPH: 3764 printf("TPH and Extended TPH"); 3765 break; 3766 default: 3767 printf("(reserved value)\n"); 3768 break; 3769 } 3770 3771 if (sttbloc != PCI_TPH_REQ_STTBLLOC_TPHREQ) 3772 return; 3773 3774 for (i = 0; i < size ; i += 2) { 3775 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3776 for (j = 0; j < 2 ; j++) { 3777 uint32_t entry = reg; 3778 3779 if (j != 0) 3780 entry >>= 16; 3781 entry &= 0xffff; 3782 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3783 i + j, entry); 3784 } 3785 } 3786 } 3787 3788 static void 3789 pci_conf_print_ltr_cap(const pcireg_t *regs, int extcapoff) 3790 { 3791 pcireg_t reg; 3792 3793 printf("\n Latency Tolerance Reporting\n"); 3794 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)]; 3795 printf(" Max Snoop Latency Register: 0x%04x\n", reg & 0xffff); 3796 printf(" Max Snoop Latency: %juns\n", 3797 (uintmax_t)(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL) 3798 * PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE)))); 3799 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg >> 16); 3800 printf(" Max No-Snoop Latency: %juns\n", 3801 (uintmax_t)(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL) 3802 * PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE)))); 3803 } 3804 3805 static void 3806 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int extcapoff) 3807 { 3808 int pcie_capoff; 3809 pcireg_t reg; 3810 int i, maxlinkwidth; 3811 3812 printf("\n Secondary PCI Express Register\n"); 3813 3814 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3815 printf(" Link Control 3 register: 0x%08x\n", reg); 3816 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3817 onoff("Link Equalization Request Interrupt Enable", 3818 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3819 printf(" Enable Lower SKP OS Generation Vector:"); 3820 pci_print_pcie_linkspeedvector( 3821 __SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3822 printf("\n"); 3823 3824 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3825 printf(" Lane Error Status register: 0x%08x\n", reg); 3826 3827 /* Get Max Link Width */ 3828 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 3829 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3830 maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3831 } else { 3832 printf("error: falied to get PCIe capablity\n"); 3833 return; 3834 } 3835 for (i = 0; i < maxlinkwidth; i++) { 3836 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3837 if (i % 2 != 0) 3838 reg >>= 16; 3839 else 3840 reg &= 0xffff; 3841 printf(" Equalization Control Register (Link %d): 0x%04x\n", 3842 i, reg); 3843 printf(" Downstream Port Transmit Preset: 0x%x\n", 3844 (pcireg_t)__SHIFTOUT(reg, 3845 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3846 printf(" Downstream Port Receive Hint: 0x%x\n", 3847 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3848 printf(" Upstream Port Transmit Preset: 0x%x\n", 3849 (pcireg_t)__SHIFTOUT(reg, 3850 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3851 printf(" Upstream Port Receive Hint: 0x%x\n", 3852 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3853 } 3854 } 3855 3856 /* XXX pci_conf_print_pmux_cap */ 3857 3858 static void 3859 pci_conf_print_pasid_cap(const pcireg_t *regs, int extcapoff) 3860 { 3861 pcireg_t reg, cap, ctl; 3862 unsigned int num; 3863 3864 printf("\n Process Address Space ID\n"); 3865 3866 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3867 cap = reg & 0xffff; 3868 ctl = reg >> 16; 3869 printf(" PASID Capability Register: 0x%04x\n", cap); 3870 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3871 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3872 num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3873 printf(" Max PASID Width: %u\n", num); 3874 3875 printf(" PASID Control Register: 0x%04x\n", ctl); 3876 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3877 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3878 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3879 } 3880 3881 static void 3882 pci_conf_print_lnr_cap(const pcireg_t *regs, int extcapoff) 3883 { 3884 pcireg_t reg, cap, ctl; 3885 unsigned int num; 3886 3887 printf("\n LN Requester\n"); 3888 3889 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3890 cap = reg & 0xffff; 3891 ctl = reg >> 16; 3892 printf(" LNR Capability register: 0x%04x\n", cap); 3893 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 3894 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 3895 num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 3896 printf(" LNR Registration MAX: %u\n", num); 3897 3898 printf(" LNR Control register: 0x%04x\n", ctl); 3899 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 3900 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 3901 num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 3902 printf(" LNR Registration Limit: %u\n", num); 3903 } 3904 3905 static void 3906 pci_conf_print_dpc_pio(pcireg_t r) 3907 { 3908 onoff("Cfg Request received UR Completion", r,PCI_DPC_RPPIO_CFGUR_CPL); 3909 onoff("Cfg Request received CA Completion", r,PCI_DPC_RPPIO_CFGCA_CPL); 3910 onoff("Cfg Request Completion Timeout", r, PCI_DPC_RPPIO_CFG_CTO); 3911 onoff("I/O Request received UR Completion", r, PCI_DPC_RPPIO_IOUR_CPL); 3912 onoff("I/O Request received CA Completion", r, PCI_DPC_RPPIO_IOCA_CPL); 3913 onoff("I/O Request Completion Timeout", r, PCI_DPC_RPPIO_IO_CTO); 3914 onoff("Mem Request received UR Completion", r,PCI_DPC_RPPIO_MEMUR_CPL); 3915 onoff("Mem Request received CA Completion", r,PCI_DPC_RPPIO_MEMCA_CPL); 3916 onoff("Mem Request Completion Timeout", r, PCI_DPC_RPPIO_MEM_CTO); 3917 } 3918 3919 static void 3920 pci_conf_print_dpc_cap(const pcireg_t *regs, int extcapoff) 3921 { 3922 pcireg_t reg, cap, ctl, stat, errsrc; 3923 const char *trigstr; 3924 bool rpext; 3925 3926 printf("\n Downstream Port Containment\n"); 3927 3928 reg = regs[o2i(extcapoff + PCI_DPC_CCR)]; 3929 cap = reg & 0xffff; 3930 ctl = reg >> 16; 3931 rpext = (reg & PCI_DPCCAP_RPEXT) ? true : false; 3932 printf(" DPC Capability register: 0x%04x\n", cap); 3933 printf(" DPC Interrupt Message Number: %02x\n", 3934 (unsigned int)(cap & PCI_DPCCAP_IMSGN)); 3935 onoff("RP Extensions for DPC", reg, PCI_DPCCAP_RPEXT); 3936 onoff("Poisoned TLP Egress Blocking Supported", reg, 3937 PCI_DPCCAP_POISONTLPEB); 3938 onoff("DPC Software Triggering Supported", reg, PCI_DPCCAP_SWTRIG); 3939 printf(" RP PIO Log Size: %u\n", 3940 (unsigned int)__SHIFTOUT(reg, PCI_DPCCAP_RPPIOLOGSZ)); 3941 onoff("DL_Active ERR_COR Signaling Supported", reg, 3942 PCI_DPCCAP_DLACTECORS); 3943 printf(" DPC Control register: 0x%04x\n", ctl); 3944 switch (__SHIFTOUT(reg, PCI_DPCCTL_TIRGEN)) { 3945 case 0: 3946 trigstr = "disabled"; 3947 break; 3948 case 1: 3949 trigstr = "enabled(ERR_FATAL)"; 3950 break; 3951 case 2: 3952 trigstr = "enabled(ERR_NONFATAL or ERR_FATAL)"; 3953 break; 3954 default: 3955 trigstr = "(reserverd)"; 3956 break; 3957 } 3958 printf(" DPC Trigger Enable: %s\n", trigstr); 3959 printf(" DPC Completion Control: %s Completion Status\n", 3960 (reg & PCI_DPCCTL_COMPCTL) 3961 ? "Unsupported Request(UR)" : "Completer Abort(CA)"); 3962 onoff("DPC Interrupt Enable", reg, PCI_DPCCTL_IE); 3963 onoff("DPC ERR_COR Enable", reg, PCI_DPCCTL_ERRCOREN); 3964 onoff("Poisoned TLP Egress Blocking Enable", reg, 3965 PCI_DPCCTL_POISONTLPEB); 3966 onoff("DPC Software Trigger", reg, PCI_DPCCTL_SWTRIG); 3967 onoff("DL_Active ERR_COR Enable", reg, PCI_DPCCTL_DLACTECOR); 3968 3969 reg = regs[o2i(extcapoff + PCI_DPC_STATESID)]; 3970 stat = reg & 0xffff; 3971 errsrc = reg >> 16; 3972 printf(" DPC Status register: 0x%04x\n", stat); 3973 onoff("DPC Trigger Status", reg, PCI_DPCSTAT_TSTAT); 3974 switch (__SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 3975 case 0: 3976 trigstr = "an unmasked uncorrectable error"; 3977 break; 3978 case 1: 3979 trigstr = "receiving an ERR_NONFATAL"; 3980 break; 3981 case 2: 3982 trigstr = "receiving an ERR_FATAL"; 3983 break; 3984 case 3: 3985 trigstr = "DPC Trigger Reason Extension field"; 3986 break; 3987 } 3988 printf(" DPC Trigger Reason: Due to %s\n", trigstr); 3989 onoff("DPC Interrupt Status", reg, PCI_DPCSTAT_ISTAT); 3990 if (rpext) 3991 onoff("DPC RP Busy", reg, PCI_DPCSTAT_RPBUSY); 3992 switch (__SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 3993 case 0: 3994 trigstr = "Due to RP PIO error"; 3995 break; 3996 case 1: 3997 trigstr = "Due to the DPC Software trigger bit"; 3998 break; 3999 default: 4000 trigstr = "(reserved)"; 4001 break; 4002 } 4003 printf(" DPC Trigger Reason Extension: %s\n", trigstr); 4004 if (rpext) 4005 printf(" RP PIO First Error Pointer: %02x\n", 4006 (unsigned int)__SHIFTOUT(reg, PCI_DPCSTAT_RPPIOFEP)); 4007 printf(" DPC Error Source ID register: 0x%04x\n", errsrc); 4008 4009 if (!rpext) 4010 return; 4011 /* 4012 * All of the following registers are implemented by a device which has 4013 * RP Extensions for DPC 4014 */ 4015 4016 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_STAT)]; 4017 printf(" RP PIO Status Register: 0x%08x\n", reg); 4018 pci_conf_print_dpc_pio(reg); 4019 4020 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_MASK)]; 4021 printf(" RP PIO Mask Register: 0x%08x\n", reg); 4022 pci_conf_print_dpc_pio(reg); 4023 4024 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SEVE)]; 4025 printf(" RP PIO Severity Register: 0x%08x\n", reg); 4026 pci_conf_print_dpc_pio(reg); 4027 4028 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SYSERR)]; 4029 printf(" RP PIO SysError Register: 0x%08x\n", reg); 4030 pci_conf_print_dpc_pio(reg); 4031 4032 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_EXCPT)]; 4033 printf(" RP PIO Exception Register: 0x%08x\n", reg); 4034 pci_conf_print_dpc_pio(reg); 4035 4036 printf(" RP PIO Header Log Register: start from 0x%03x\n", 4037 extcapoff + PCI_DPC_RPPIO_HLOG); 4038 printf(" RP PIO ImpSpec Log Register: start from 0x%03x\n", 4039 extcapoff + PCI_DPC_RPPIO_IMPSLOG); 4040 printf(" RP PIO TLP Prefix Log Register: start from 0x%03x\n", 4041 extcapoff + PCI_DPC_RPPIO_TLPPLOG); 4042 } 4043 4044 4045 static int 4046 pci_conf_l1pm_cap_tposcale(unsigned char scale) 4047 { 4048 4049 /* Return scale in us */ 4050 switch (scale) { 4051 case 0x0: 4052 return 2; 4053 case 0x1: 4054 return 10; 4055 case 0x2: 4056 return 100; 4057 default: 4058 return -1; 4059 } 4060 } 4061 4062 static void 4063 pci_conf_print_l1pm_cap(const pcireg_t *regs, int extcapoff) 4064 { 4065 pcireg_t reg; 4066 int scale, val; 4067 int pcie_capoff; 4068 4069 printf("\n L1 PM Substates\n"); 4070 4071 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 4072 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 4073 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 4074 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 4075 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 4076 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 4077 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 4078 /* The Link Activation Supported bit is only for Downstream Port */ 4079 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 4080 uint32_t t = regs[o2i(pcie_capoff)]; 4081 4082 if ((t == PCIE_XCAP_TYPE_ROOT) || (t == PCIE_XCAP_TYPE_DOWN)) 4083 onoff("Link Activation Supported", reg, 4084 PCI_L1PM_CAP_LA); 4085 } 4086 printf(" Port Common Mode Restore Time: %uus\n", 4087 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 4088 scale = pci_conf_l1pm_cap_tposcale( 4089 __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 4090 val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 4091 printf(" Port T_POWER_ON: "); 4092 if (scale == -1) 4093 printf("unknown\n"); 4094 else 4095 printf("%dus\n", val * scale); 4096 4097 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 4098 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 4099 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 4100 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 4101 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 4102 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 4103 onoff("Link Activation Interrupt Enable", reg, PCI_L1PM_CTL1_LAIE); 4104 onoff("Link Activation Control", reg, PCI_L1PM_CTL1_LA); 4105 printf(" Common Mode Restore Time: %uus\n", 4106 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 4107 scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 4108 val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 4109 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 4110 4111 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 4112 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 4113 scale = pci_conf_l1pm_cap_tposcale( 4114 __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 4115 val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 4116 printf(" T_POWER_ON: "); 4117 if (scale == -1) 4118 printf("unknown\n"); 4119 else 4120 printf("%dus\n", val * scale); 4121 4122 if (PCI_EXTCAPLIST_VERSION(regs[o2i(extcapoff)]) >= 2) { 4123 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 4124 printf(" L1 PM Substates Status register: 0x%08x\n", reg); 4125 onoff("Link Activation Status", reg, PCI_L1PM_STAT_LA); 4126 } 4127 } 4128 4129 static void 4130 pci_conf_print_ptm_cap(const pcireg_t *regs, int extcapoff) 4131 { 4132 pcireg_t reg; 4133 uint32_t val; 4134 4135 printf("\n Precision Time Management\n"); 4136 4137 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 4138 printf(" PTM Capability register: 0x%08x\n", reg); 4139 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 4140 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 4141 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 4142 printf(" Local Clock Granularity: "); 4143 val = __SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 4144 switch (val) { 4145 case 0: 4146 printf("Not implemented\n"); 4147 break; 4148 case 0xffff: 4149 printf("> 254ns\n"); 4150 break; 4151 default: 4152 printf("%uns\n", val); 4153 break; 4154 } 4155 4156 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 4157 printf(" PTM Control register: 0x%08x\n", reg); 4158 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 4159 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 4160 printf(" Effective Granularity: "); 4161 val = __SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 4162 switch (val) { 4163 case 0: 4164 printf("Unknown\n"); 4165 break; 4166 case 0xffff: 4167 printf("> 254ns\n"); 4168 break; 4169 default: 4170 printf("%uns\n", val); 4171 break; 4172 } 4173 } 4174 4175 /* XXX pci_conf_print_mpcie_cap */ 4176 /* XXX pci_conf_print_frsq_cap */ 4177 /* XXX pci_conf_print_rtr_cap */ 4178 /* XXX pci_conf_print_desigvndsp_cap */ 4179 /* XXX pci_conf_print_vf_resizbar_cap */ 4180 4181 static void 4182 pci_conf_print_dlf_cap(const pcireg_t *regs, int extcapoff) 4183 { 4184 pcireg_t reg; 4185 4186 printf("\n Data link Feature Register\n"); 4187 reg = regs[o2i(extcapoff + PCI_DLF_CAP)]; 4188 printf(" Capability register: 0x%08x\n", reg); 4189 onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL); 4190 onoff("DLF Exchange enable", reg, PCI_DLF_CAP_XCHG); 4191 4192 reg = regs[o2i(extcapoff + PCI_DLF_STAT)]; 4193 printf(" Status register: 0x%08x\n", reg); 4194 onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL); 4195 onoff("Remote DLF supported Valid", reg, PCI_DLF_STAT_RMTVALID); 4196 } 4197 4198 /* XXX pci_conf_print_hierarchyid_cap */ 4199 /* XXX pci_conf_print_npem_cap */ 4200 4201 #undef MS 4202 #undef SM 4203 #undef RW 4204 4205 static struct { 4206 pcireg_t cap; 4207 const char *name; 4208 void (*printfunc)(const pcireg_t *, int); 4209 } pci_extcaptab[] = { 4210 { 0, "reserved", 4211 NULL }, 4212 { PCI_EXTCAP_AER, "Advanced Error Reporting", 4213 pci_conf_print_aer_cap }, 4214 { PCI_EXTCAP_VC, "Virtual Channel", 4215 pci_conf_print_vc_cap }, 4216 { PCI_EXTCAP_SERNUM, "Device Serial Number", 4217 pci_conf_print_sernum_cap }, 4218 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 4219 pci_conf_print_pwrbdgt_cap }, 4220 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 4221 pci_conf_print_rclink_dcl_cap }, 4222 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 4223 NULL }, 4224 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 4225 pci_conf_print_rcec_assoc_cap }, 4226 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 4227 NULL }, 4228 { PCI_EXTCAP_VC2, "Virtual Channel", 4229 NULL }, 4230 { PCI_EXTCAP_RCRB, "RCRB Header", 4231 NULL }, 4232 { PCI_EXTCAP_VENDOR, "Vendor Unique", 4233 NULL }, 4234 { PCI_EXTCAP_CAC, "Configuration Access Correction", 4235 NULL }, 4236 { PCI_EXTCAP_ACS, "Access Control Services", 4237 pci_conf_print_acs_cap }, 4238 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 4239 pci_conf_print_ari_cap }, 4240 { PCI_EXTCAP_ATS, "Address Translation Services", 4241 pci_conf_print_ats_cap }, 4242 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 4243 pci_conf_print_sriov_cap }, 4244 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 4245 NULL }, 4246 { PCI_EXTCAP_MCAST, "Multicast", 4247 pci_conf_print_multicast_cap }, 4248 { PCI_EXTCAP_PAGE_REQ, "Page Request", 4249 pci_conf_print_page_req_cap }, 4250 { PCI_EXTCAP_AMD, "Reserved for AMD", 4251 NULL }, 4252 { PCI_EXTCAP_RESIZBAR, "Resizable BAR", 4253 pci_conf_print_resizbar_cap }, 4254 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 4255 pci_conf_print_dpa_cap }, 4256 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 4257 pci_conf_print_tph_req_cap }, 4258 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 4259 pci_conf_print_ltr_cap }, 4260 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 4261 pci_conf_print_sec_pcie_cap }, 4262 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 4263 NULL }, 4264 { PCI_EXTCAP_PASID, "Process Address Space ID", 4265 pci_conf_print_pasid_cap }, 4266 { PCI_EXTCAP_LNR, "LN Requester", 4267 pci_conf_print_lnr_cap }, 4268 { PCI_EXTCAP_DPC, "Downstream Port Containment", 4269 pci_conf_print_dpc_cap }, 4270 { PCI_EXTCAP_L1PM, "L1 PM Substates", 4271 pci_conf_print_l1pm_cap }, 4272 { PCI_EXTCAP_PTM, "Precision Time Management", 4273 pci_conf_print_ptm_cap }, 4274 { PCI_EXTCAP_MPCIE, "M-PCIe", 4275 NULL }, 4276 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 4277 NULL }, 4278 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 4279 NULL }, 4280 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 4281 NULL }, 4282 { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", 4283 NULL }, 4284 { PCI_EXTCAP_DLF, "Data link Feature", pci_conf_print_dlf_cap }, 4285 { PCI_EXTCAP_PYSLAY_16GT, "Physical Layer 16.0 GT/s", NULL }, 4286 { 0x27, "unknown", NULL }, 4287 { PCI_EXTCAP_HIERARCHYID, "Hierarchy ID", 4288 NULL }, 4289 { PCI_EXTCAP_NPEM, "Native PCIe Enclosure Management", 4290 NULL }, 4291 }; 4292 4293 static int 4294 pci_conf_find_extcap(const pcireg_t *regs, unsigned int capid, int *offsetp) 4295 { 4296 int off; 4297 pcireg_t rval; 4298 4299 for (off = PCI_EXTCAPLIST_BASE; 4300 off != 0; 4301 off = PCI_EXTCAPLIST_NEXT(rval)) { 4302 rval = regs[o2i(off)]; 4303 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 4304 if (offsetp != NULL) 4305 *offsetp = off; 4306 return 1; 4307 } 4308 } 4309 return 0; 4310 } 4311 4312 static void 4313 pci_conf_print_extcaplist( 4314 #ifdef _KERNEL 4315 pci_chipset_tag_t pc, pcitag_t tag, 4316 #endif 4317 const pcireg_t *regs) 4318 { 4319 int off; 4320 pcireg_t foundcap; 4321 pcireg_t rval; 4322 bool foundtable[__arraycount(pci_extcaptab)]; 4323 unsigned int i; 4324 4325 /* Check Extended capability structure */ 4326 off = PCI_EXTCAPLIST_BASE; 4327 rval = regs[o2i(off)]; 4328 if (rval == 0xffffffff || rval == 0) 4329 return; 4330 4331 /* Clear table */ 4332 for (i = 0; i < __arraycount(pci_extcaptab); i++) 4333 foundtable[i] = false; 4334 4335 /* Print extended capability register's offset and the type first */ 4336 for (;;) { 4337 printf(" Extended Capability Register at 0x%02x\n", off); 4338 4339 foundcap = PCI_EXTCAPLIST_CAP(rval); 4340 printf(" type: 0x%04x (", foundcap); 4341 if (foundcap < __arraycount(pci_extcaptab)) { 4342 printf("%s)\n", pci_extcaptab[foundcap].name); 4343 /* Mark as found */ 4344 foundtable[foundcap] = true; 4345 } else 4346 printf("unknown)\n"); 4347 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 4348 4349 off = PCI_EXTCAPLIST_NEXT(rval); 4350 if (off == 0) 4351 break; 4352 else if (off <= PCI_CONF_SIZE) { 4353 printf(" next pointer: 0x%03x (incorrect)\n", off); 4354 return; 4355 } 4356 rval = regs[o2i(off)]; 4357 } 4358 4359 /* 4360 * And then, print the detail of each capability registers 4361 * in capability value's order. 4362 */ 4363 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 4364 if (foundtable[i] == false) 4365 continue; 4366 4367 /* 4368 * The type was found. Search capability list again and 4369 * print all capabilities that the capabiliy type is 4370 * the same. 4371 */ 4372 if (pci_conf_find_extcap(regs, i, &off) == 0) 4373 continue; 4374 rval = regs[o2i(off)]; 4375 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 4376 || (pci_extcaptab[i].printfunc == NULL)) 4377 continue; 4378 4379 pci_extcaptab[i].printfunc(regs, off); 4380 4381 } 4382 } 4383 4384 /* Print the Secondary Status Register. */ 4385 static void 4386 pci_conf_print_ssr(pcireg_t rval) 4387 { 4388 pcireg_t devsel; 4389 4390 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 4391 onoff("66 MHz capable", rval, __BIT(5)); 4392 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 4393 onoff("Fast back-to-back capable", rval, __BIT(7)); 4394 onoff("Data parity error detected", rval, __BIT(8)); 4395 4396 printf(" DEVSEL timing: "); 4397 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 4398 switch (devsel) { 4399 case 0: 4400 printf("fast"); 4401 break; 4402 case 1: 4403 printf("medium"); 4404 break; 4405 case 2: 4406 printf("slow"); 4407 break; 4408 default: 4409 printf("unknown/reserved"); /* XXX */ 4410 break; 4411 } 4412 printf(" (0x%x)\n", devsel); 4413 4414 onoff("Signalled target abort", rval, __BIT(11)); 4415 onoff("Received target abort", rval, __BIT(12)); 4416 onoff("Received master abort", rval, __BIT(13)); 4417 onoff("Received system error", rval, __BIT(14)); 4418 onoff("Detected parity error", rval, __BIT(15)); 4419 } 4420 4421 static void 4422 pci_conf_print_type0( 4423 #ifdef _KERNEL 4424 pci_chipset_tag_t pc, pcitag_t tag, 4425 #endif 4426 const pcireg_t *regs) 4427 { 4428 int off, width; 4429 pcireg_t rval; 4430 const char *str; 4431 4432 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 4433 #ifdef _KERNEL 4434 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4435 #else 4436 width = pci_conf_print_bar(regs, off, NULL); 4437 #endif 4438 } 4439 4440 printf(" Cardbus CIS Pointer: 0x%08x\n", 4441 regs[o2i(PCI_CARDBUS_CIS_REG)]); 4442 4443 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 4444 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4445 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4446 4447 rval = regs[o2i(PCI_MAPREG_ROM)]; 4448 printf(" Expansion ROM Base Address Register: 0x%08x\n", rval); 4449 printf(" base: 0x%08x\n", (uint32_t)PCI_MAPREG_ROM_ADDR(rval)); 4450 onoff("Expansion ROM Enable", rval, PCI_MAPREG_ROM_ENABLE); 4451 printf(" Validation Status: "); 4452 switch (__SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_STAT)) { 4453 case PCI_MAPREG_ROM_VSTAT_NOTSUPP: 4454 str = "Validation not supported"; 4455 break; 4456 case PCI_MAPREG_ROM_VSTAT_INPROG: 4457 str = "Validation in Progress"; 4458 break; 4459 case PCI_MAPREG_ROM_VSTAT_VPASS: 4460 str = "Validation Pass. " 4461 "Valid contents, trust test was not performed"; 4462 break; 4463 case PCI_MAPREG_ROM_VSTAT_VPASSTRUST: 4464 str = "Validation Pass. Valid and trusted contents"; 4465 break; 4466 case PCI_MAPREG_ROM_VSTAT_VFAIL: 4467 str = "Validation Fail. Invalid contents"; 4468 break; 4469 case PCI_MAPREG_ROM_VSTAT_VFAILUNTRUST: 4470 str = "Validation Fail. Valid but untrusted contents"; 4471 break; 4472 case PCI_MAPREG_ROM_VSTAT_WPASS: 4473 str = "Warning Pass. Validation passed with warning. " 4474 "Valid contents, trust test was not performed"; 4475 break; 4476 case PCI_MAPREG_ROM_VSTAT_WPASSTRUST: 4477 str = "Warning Pass. Validation passed with warning. " 4478 "Valid and trusted contents"; 4479 break; 4480 } 4481 printf("%s\n", str); 4482 printf(" Validation Details: 0x%x\n", 4483 (uint32_t)__SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_DETAIL)); 4484 4485 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4486 printf(" Capability list pointer: 0x%02x\n", 4487 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4488 else 4489 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4490 4491 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 4492 4493 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4494 printf(" Maximum Latency: 0x%02x\n", PCI_MAX_LAT(rval)); 4495 printf(" Minimum Grant: 0x%02x\n", PCI_MIN_GNT(rval)); 4496 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 4497 switch (PCI_INTERRUPT_PIN(rval)) { 4498 case PCI_INTERRUPT_PIN_NONE: 4499 printf("(none)"); 4500 break; 4501 case PCI_INTERRUPT_PIN_A: 4502 printf("(pin A)"); 4503 break; 4504 case PCI_INTERRUPT_PIN_B: 4505 printf("(pin B)"); 4506 break; 4507 case PCI_INTERRUPT_PIN_C: 4508 printf("(pin C)"); 4509 break; 4510 case PCI_INTERRUPT_PIN_D: 4511 printf("(pin D)"); 4512 break; 4513 default: 4514 printf("(? ? ?)"); 4515 break; 4516 } 4517 printf("\n"); 4518 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 4519 } 4520 4521 static void 4522 pci_conf_print_type1( 4523 #ifdef _KERNEL 4524 pci_chipset_tag_t pc, pcitag_t tag, 4525 #endif 4526 const pcireg_t *regs) 4527 { 4528 int off, width; 4529 pcireg_t rval, csreg; 4530 uint32_t base, limit; 4531 uint32_t base_h, limit_h; 4532 uint64_t pbase, plimit; 4533 int use_upper; 4534 4535 /* 4536 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 4537 * Bridge chip documentation, and may not be correct with 4538 * respect to various standards. (XXX) 4539 */ 4540 4541 for (off = 0x10; off < 0x18; off += width) { 4542 #ifdef _KERNEL 4543 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4544 #else 4545 width = pci_conf_print_bar(regs, off, NULL); 4546 #endif 4547 } 4548 4549 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4550 printf(" Primary bus number: 0x%02x\n", 4551 PCI_BRIDGE_BUS_NUM_PRIMARY(rval)); 4552 printf(" Secondary bus number: 0x%02x\n", 4553 PCI_BRIDGE_BUS_NUM_SECONDARY(rval)); 4554 printf(" Subordinate bus number: 0x%02x\n", 4555 PCI_BRIDGE_BUS_NUM_SUBORDINATE(rval)); 4556 printf(" Secondary bus latency timer: 0x%02x\n", 4557 PCI_BRIDGE_BUS_SEC_LATTIMER_VAL(rval)); 4558 4559 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 4560 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 4561 4562 /* I/O region */ 4563 printf(" I/O region:\n"); 4564 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 4565 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 4566 if (PCI_BRIDGE_IO_32BITS(rval)) 4567 use_upper = 1; 4568 else 4569 use_upper = 0; 4570 onoff("32bit I/O", rval, use_upper); 4571 base = PCI_BRIDGE_STATIO_IOBASE_ADDR(rval); 4572 limit = PCI_BRIDGE_STATIO_IOLIMIT_ADDR(rval); 4573 4574 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 4575 base_h = __SHIFTOUT(rval, PCI_BRIDGE_IOHIGH_BASE); 4576 limit_h = __SHIFTOUT(rval, PCI_BRIDGE_IOHIGH_LIMIT); 4577 printf(" base upper 16 bits register: 0x%04x\n", base_h); 4578 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 4579 4580 if (use_upper == 1) { 4581 base |= base_h << 16; 4582 limit |= limit_h << 16; 4583 } 4584 if (base < limit) { 4585 if (use_upper == 1) 4586 printf(" range: 0x%08x-0x%08x\n", base, limit); 4587 else 4588 printf(" range: 0x%04x-0x%04x\n", base, limit); 4589 } else 4590 printf(" range: not set\n"); 4591 4592 /* Non-prefetchable memory region */ 4593 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 4594 printf(" Memory region:\n"); 4595 printf(" base register: 0x%04hx\n", 4596 (uint16_t)__SHIFTOUT(rval, PCI_BRIDGE_MEMORY_BASE)); 4597 printf(" limit register: 0x%04hx\n", 4598 (uint16_t)__SHIFTOUT(rval, PCI_BRIDGE_MEMORY_LIMIT)); 4599 base = PCI_BRIDGE_MEMORY_BASE_ADDR(rval); 4600 limit = PCI_BRIDGE_MEMORY_LIMIT_ADDR(rval); 4601 if (base < limit) 4602 printf(" range: 0x%08x-0x%08x\n", base, limit); 4603 else 4604 printf(" range: not set\n"); 4605 4606 /* Prefetchable memory region */ 4607 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 4608 printf(" Prefetchable memory region:\n"); 4609 printf(" base register: 0x%04x\n", 4610 (rval >> 0) & 0xffff); 4611 printf(" limit register: 0x%04x\n", 4612 (rval >> 16) & 0xffff); 4613 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASEUP32_REG)]; 4614 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMITUP32_REG)]; 4615 printf(" base upper 32 bits register: 0x%08x\n", 4616 base_h); 4617 printf(" limit upper 32 bits register: 0x%08x\n", 4618 limit_h); 4619 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 4620 use_upper = 1; 4621 else 4622 use_upper = 0; 4623 onoff("64bit memory address", rval, use_upper); 4624 pbase = PCI_BRIDGE_PREFETCHMEM_BASE_ADDR(rval); 4625 plimit = PCI_BRIDGE_PREFETCHMEM_LIMIT_ADDR(rval); 4626 if (use_upper == 1) { 4627 pbase |= (uint64_t)base_h << 32; 4628 plimit |= (uint64_t)limit_h << 32; 4629 } 4630 if (pbase < plimit) { 4631 if (use_upper == 1) 4632 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 4633 "\n", pbase, plimit); 4634 else 4635 printf(" range: 0x%08x-0x%08x\n", 4636 (uint32_t)pbase, (uint32_t)plimit); 4637 } else 4638 printf(" range: not set\n"); 4639 4640 csreg = regs[o2i(PCI_COMMAND_STATUS_REG)]; 4641 if (csreg & PCI_STATUS_CAPLIST_SUPPORT) 4642 printf(" Capability list pointer: 0x%02x\n", 4643 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4644 else 4645 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4646 4647 printf(" Expansion ROM Base Address: 0x%08x\n", 4648 regs[o2i(PCI_BRIDGE_EXPROMADDR_REG)]); 4649 4650 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4651 printf(" Interrupt line: 0x%02x\n", 4652 (rval >> 0) & 0xff); 4653 printf(" Interrupt pin: 0x%02x ", 4654 (rval >> 8) & 0xff); 4655 switch ((rval >> 8) & 0xff) { 4656 case PCI_INTERRUPT_PIN_NONE: 4657 printf("(none)"); 4658 break; 4659 case PCI_INTERRUPT_PIN_A: 4660 printf("(pin A)"); 4661 break; 4662 case PCI_INTERRUPT_PIN_B: 4663 printf("(pin B)"); 4664 break; 4665 case PCI_INTERRUPT_PIN_C: 4666 printf("(pin C)"); 4667 break; 4668 case PCI_INTERRUPT_PIN_D: 4669 printf("(pin D)"); 4670 break; 4671 default: 4672 printf("(? ? ?)"); 4673 break; 4674 } 4675 printf("\n"); 4676 rval = regs[o2i(PCI_BRIDGE_CONTROL_REG)]; 4677 printf(" Bridge control register: 0x%04hx\n", 4678 (uint16_t)__SHIFTOUT(rval, PCI_BRIDGE_CONTROL)); 4679 onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE); 4680 onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR); 4681 onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA); 4682 onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA); 4683 /* 4684 * VGA 16bit decode bit has meaning if the VGA enable bit or the 4685 * VGA Palette Snoop Enable bit is set. 4686 */ 4687 if (((rval & PCI_BRIDGE_CONTROL_VGA) != 0) 4688 || ((csreg & PCI_COMMAND_PALETTE_ENABLE) != 0)) 4689 onoff("VGA 16bit enable", rval, PCI_BRIDGE_CONTROL_VGA16); 4690 onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT); 4691 onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR); 4692 onoff("Fast back-to-back enable", rval, PCI_BRIDGE_CONTROL_SECFASTB2B); 4693 onoff("Primary Discard Timer", rval, 4694 PCI_BRIDGE_CONTROL_PRI_DISC_TIMER); 4695 onoff("Secondary Discard Timer", 4696 rval, PCI_BRIDGE_CONTROL_SEC_DISC_TIMER); 4697 onoff("Discard Timer Status", rval, 4698 PCI_BRIDGE_CONTROL_DISC_TIMER_STAT); 4699 onoff("Discard Timer SERR# Enable", rval, 4700 PCI_BRIDGE_CONTROL_DISC_TIMER_SERR); 4701 } 4702 4703 static void 4704 pci_conf_print_type2( 4705 #ifdef _KERNEL 4706 pci_chipset_tag_t pc, pcitag_t tag, 4707 #endif 4708 const pcireg_t *regs) 4709 { 4710 pcireg_t rval; 4711 4712 /* 4713 * XXX these need to be printed in more detail, need to be 4714 * XXX checked against specs/docs, etc. 4715 * 4716 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 4717 * controller chip documentation, and may not be correct with 4718 * respect to various standards. (XXX) 4719 */ 4720 4721 #ifdef _KERNEL 4722 pci_conf_print_bar(pc, tag, regs, 0x10, 4723 "CardBus socket/ExCA registers"); 4724 #else 4725 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 4726 #endif 4727 4728 /* Capability list pointer and secondary status register */ 4729 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 4730 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4731 printf(" Capability list pointer: 0x%02x\n", 4732 PCI_CAPLIST_PTR(rval)); 4733 else 4734 printf(" Reserved @ 0x14: 0x%04x\n", 4735 (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0))); 4736 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 4737 4738 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4739 printf(" PCI bus number: 0x%02x\n", 4740 (rval >> 0) & 0xff); 4741 printf(" CardBus bus number: 0x%02x\n", 4742 (rval >> 8) & 0xff); 4743 printf(" Subordinate bus number: 0x%02x\n", 4744 (rval >> 16) & 0xff); 4745 printf(" CardBus latency timer: 0x%02x\n", 4746 (rval >> 24) & 0xff); 4747 4748 /* XXX Print more prettily */ 4749 printf(" CardBus memory region 0:\n"); 4750 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 4751 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 4752 printf(" CardBus memory region 1:\n"); 4753 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 4754 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 4755 printf(" CardBus I/O region 0:\n"); 4756 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 4757 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 4758 printf(" CardBus I/O region 1:\n"); 4759 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 4760 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 4761 4762 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4763 printf(" Interrupt line: 0x%02x\n", 4764 (rval >> 0) & 0xff); 4765 printf(" Interrupt pin: 0x%02x ", 4766 (rval >> 8) & 0xff); 4767 switch ((rval >> 8) & 0xff) { 4768 case PCI_INTERRUPT_PIN_NONE: 4769 printf("(none)"); 4770 break; 4771 case PCI_INTERRUPT_PIN_A: 4772 printf("(pin A)"); 4773 break; 4774 case PCI_INTERRUPT_PIN_B: 4775 printf("(pin B)"); 4776 break; 4777 case PCI_INTERRUPT_PIN_C: 4778 printf("(pin C)"); 4779 break; 4780 case PCI_INTERRUPT_PIN_D: 4781 printf("(pin D)"); 4782 break; 4783 default: 4784 printf("(? ? ?)"); 4785 break; 4786 } 4787 printf("\n"); 4788 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> 16) & 0xffff; 4789 printf(" Bridge control register: 0x%04x\n", rval); 4790 onoff("Parity error response", rval, __BIT(0)); 4791 onoff("SERR# enable", rval, __BIT(1)); 4792 onoff("ISA enable", rval, __BIT(2)); 4793 onoff("VGA enable", rval, __BIT(3)); 4794 onoff("Master abort mode", rval, __BIT(5)); 4795 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 4796 onoff("Functional interrupts routed by ExCA registers", rval, 4797 __BIT(7)); 4798 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 4799 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 4800 onoff("Write posting enable", rval, __BIT(10)); 4801 4802 rval = regs[o2i(0x40)]; 4803 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4804 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4805 4806 #ifdef _KERNEL 4807 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers"); 4808 #else 4809 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 4810 #endif 4811 } 4812 4813 void 4814 pci_conf_print( 4815 #ifdef _KERNEL 4816 pci_chipset_tag_t pc, pcitag_t tag, 4817 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 4818 #else 4819 int pcifd, u_int bus, u_int dev, u_int func 4820 #endif 4821 ) 4822 { 4823 pcireg_t *regs; 4824 int off, capoff, endoff, hdrtype; 4825 const char *type_name; 4826 #ifdef _KERNEL 4827 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 4828 #else 4829 void (*type_printfn)(const pcireg_t *); 4830 #endif 4831 4832 regs = MALLOC(PCI_EXTCONF_SIZE); 4833 4834 printf("PCI configuration registers:\n"); 4835 4836 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 4837 #ifdef _KERNEL 4838 regs[o2i(off)] = pci_conf_read(pc, tag, off); 4839 #else 4840 if (pcibus_conf_read(pcifd, bus, dev, func, off, 4841 ®s[o2i(off)]) == -1) 4842 regs[o2i(off)] = 0; 4843 #endif 4844 } 4845 4846 /* common header */ 4847 printf(" Common header:\n"); 4848 pci_conf_print_regs(regs, 0, 16); 4849 4850 printf("\n"); 4851 #ifdef _KERNEL 4852 pci_conf_print_common(pc, tag, regs); 4853 #else 4854 pci_conf_print_common(regs); 4855 #endif 4856 printf("\n"); 4857 4858 /* type-dependent header */ 4859 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 4860 switch (hdrtype) { /* XXX make a table, eventually */ 4861 case 0: 4862 /* Standard device header */ 4863 type_name = "\"normal\" device"; 4864 type_printfn = &pci_conf_print_type0; 4865 capoff = PCI_CAPLISTPTR_REG; 4866 endoff = 64; 4867 break; 4868 case 1: 4869 /* PCI-PCI bridge header */ 4870 type_name = "PCI-PCI bridge"; 4871 type_printfn = &pci_conf_print_type1; 4872 capoff = PCI_CAPLISTPTR_REG; 4873 endoff = 64; 4874 break; 4875 case 2: 4876 /* PCI-CardBus bridge header */ 4877 type_name = "PCI-CardBus bridge"; 4878 type_printfn = &pci_conf_print_type2; 4879 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 4880 endoff = 72; 4881 break; 4882 default: 4883 type_name = NULL; 4884 type_printfn = 0; 4885 capoff = -1; 4886 endoff = 64; 4887 break; 4888 } 4889 printf(" Type %d ", hdrtype); 4890 if (type_name != NULL) 4891 printf("(%s) ", type_name); 4892 printf("header:\n"); 4893 pci_conf_print_regs(regs, 16, endoff); 4894 printf("\n"); 4895 if (type_printfn) { 4896 #ifdef _KERNEL 4897 (*type_printfn)(pc, tag, regs); 4898 #else 4899 (*type_printfn)(regs); 4900 #endif 4901 } else 4902 printf(" Don't know how to pretty-print type %d header.\n", 4903 hdrtype); 4904 printf("\n"); 4905 4906 /* capability list, if present */ 4907 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4908 && (capoff > 0)) { 4909 #ifdef _KERNEL 4910 pci_conf_print_caplist(pc, tag, regs, capoff); 4911 #else 4912 pci_conf_print_caplist(regs, capoff); 4913 #endif 4914 printf("\n"); 4915 } 4916 4917 /* device-dependent header */ 4918 printf(" Device-dependent header:\n"); 4919 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 4920 #ifdef _KERNEL 4921 printf("\n"); 4922 if (printfn) 4923 (*printfn)(pc, tag, regs); 4924 else 4925 printf(" Don't know how to pretty-print device-dependent header.\n"); 4926 #endif /* _KERNEL */ 4927 4928 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 4929 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 4930 goto out; 4931 4932 printf("\n"); 4933 #ifdef _KERNEL 4934 pci_conf_print_extcaplist(pc, tag, regs); 4935 #else 4936 pci_conf_print_extcaplist(regs); 4937 #endif 4938 printf("\n"); 4939 4940 /* Extended Configuration Space, if present */ 4941 printf(" Extended Configuration Space:\n"); 4942 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 4943 4944 out: 4945 FREE(regs, PCI_EXTCONF_SIZE); 4946 } 4947
Indexes created Tue Sep 30 11:09:46 GMT 2025