pci_subr.c revision 1.215.2.6
1 /* $NetBSD: pci_subr.c,v 1.215.2.6 2022/01/29 17:08:33 martin Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.215.2.6 2022/01/29 17:08:33 martin Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #include <sys/kmem.h> 56 57 #define MALLOC(sz) kmem_alloc(sz, KM_SLEEP) 58 #define FREE(p, sz) kmem_free(p, sz) 59 60 #else 61 #include <pci.h> 62 #include <stdarg.h> 63 #include <stdbool.h> 64 #include <stdio.h> 65 #include <stdlib.h> 66 #include <string.h> 67 68 #define MALLOC(sz) malloc(sz) 69 #define FREE(p, sz) free(p) 70 71 #endif 72 73 #include <dev/pci/pcireg.h> 74 #ifdef _KERNEL 75 #include <dev/pci/pcivar.h> 76 #else 77 #include <dev/pci/pci_verbose.h> 78 #include <dev/pci/pcidevs.h> 79 #include <dev/pci/pcidevs_data.h> 80 #endif 81 82 static int pci_conf_find_cap(const pcireg_t *, unsigned int, int *); 83 static int pci_conf_find_extcap(const pcireg_t *, unsigned int, int *); 84 static void pci_conf_print_pcie_power(uint8_t, unsigned int); 85 86 /* 87 * Descriptions of known PCI classes and subclasses. 88 * 89 * Subclasses are described in the same way as classes, but have a 90 * NULL subclass pointer. 91 */ 92 struct pci_class { 93 const char *name; 94 u_int val; /* as wide as pci_{,sub}class_t */ 95 const struct pci_class *subclasses; 96 }; 97 98 /* 99 * Class 0x00. 100 * Before rev. 2.0. 101 */ 102 static const struct pci_class pci_subclass_prehistoric[] = { 103 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 104 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 105 { NULL, 0, NULL, }, 106 }; 107 108 /* 109 * Class 0x01. 110 * Mass storage controller 111 */ 112 113 /* ATA programming interface */ 114 static const struct pci_class pci_interface_ata[] = { 115 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 116 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 117 { NULL, 0, NULL, }, 118 }; 119 120 /* SATA programming interface */ 121 static const struct pci_class pci_interface_sata[] = { 122 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 123 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 124 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 125 { NULL, 0, NULL, }, 126 }; 127 128 /* Flash programming interface */ 129 static const struct pci_class pci_interface_nvm[] = { 130 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 131 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 132 { "NVMe I/O", PCI_INTERFACE_NVM_NVME_IO, NULL, }, 133 { "NVMe admin", PCI_INTERFACE_NVM_NVME_ADMIN, NULL, }, 134 { NULL, 0, NULL, }, 135 }; 136 137 /* UFS programming interface */ 138 static const struct pci_class pci_interface_ufs[] = { 139 { "vendor specific", PCI_INTERFACE_UFS_VND, NULL, }, 140 { "UFSHCI", PCI_INTERFACE_UFS_UFSHCI, NULL, }, 141 { NULL, 0, NULL, }, 142 }; 143 144 /* Subclasses */ 145 static const struct pci_class pci_subclass_mass_storage[] = { 146 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 147 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 148 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 149 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 150 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 151 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 152 pci_interface_ata, }, 153 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 154 pci_interface_sata, }, 155 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 156 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 157 pci_interface_nvm, }, 158 { "UFS", PCI_SUBCLASS_MASS_STORAGE_UFS, 159 pci_interface_ufs, }, 160 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 161 { NULL, 0, NULL, }, 162 }; 163 164 /* 165 * Class 0x02. 166 * Network controller. 167 */ 168 static const struct pci_class pci_subclass_network[] = { 169 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 170 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 171 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 172 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 173 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 174 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 175 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 176 { "InfiniBand", PCI_SUBCLASS_NETWORK_INFINIBAND, NULL, }, 177 { "Host fabric", PCI_SUBCLASS_NETWORK_HFC, NULL, }, 178 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 179 { NULL, 0, NULL, }, 180 }; 181 182 /* 183 * Class 0x03. 184 * Display controller. 185 */ 186 187 /* VGA programming interface */ 188 static const struct pci_class pci_interface_vga[] = { 189 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 190 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 191 { NULL, 0, NULL, }, 192 }; 193 /* Subclasses */ 194 static const struct pci_class pci_subclass_display[] = { 195 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 196 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 197 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 198 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 199 { NULL, 0, NULL, }, 200 }; 201 202 /* 203 * Class 0x04. 204 * Multimedia device. 205 */ 206 207 /* HD Audio programming interface */ 208 static const struct pci_class pci_interface_hda[] = { 209 { "HD Audio 1.0", PCI_INTERFACE_HDAUDIO, NULL, }, 210 { "HD Audio 1.0 + vendor ext", PCI_INTERFACE_HDAUDIO_VND, NULL, }, 211 { NULL, 0, NULL, }, 212 }; 213 214 static const struct pci_class pci_subclass_multimedia[] = { 215 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 216 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 217 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 218 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, 219 pci_interface_hda, }, 220 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 221 { NULL, 0, NULL, }, 222 }; 223 224 /* 225 * Class 0x05. 226 * Memory controller. 227 */ 228 static const struct pci_class pci_subclass_memory[] = { 229 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 230 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 231 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 232 { NULL, 0, NULL, }, 233 }; 234 235 /* 236 * Class 0x06. 237 * Bridge device. 238 */ 239 240 /* PCI bridge programming interface */ 241 static const struct pci_class pci_interface_pcibridge[] = { 242 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 243 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 244 { NULL, 0, NULL, }, 245 }; 246 247 /* Semi-transparent PCI-to-PCI bridge programming interface */ 248 static const struct pci_class pci_interface_stpci[] = { 249 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 250 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 251 { NULL, 0, NULL, }, 252 }; 253 254 /* Advanced Switching programming interface */ 255 static const struct pci_class pci_interface_advsw[] = { 256 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 257 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 258 { NULL, 0, NULL, }, 259 }; 260 261 /* Subclasses */ 262 static const struct pci_class pci_subclass_bridge[] = { 263 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 264 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 265 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 266 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 267 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 268 pci_interface_pcibridge, }, 269 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 270 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 271 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 272 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 273 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 274 pci_interface_stpci, }, 275 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 276 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 277 pci_interface_advsw, }, 278 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 279 { NULL, 0, NULL, }, 280 }; 281 282 /* 283 * Class 0x07. 284 * Simple communications controller. 285 */ 286 287 /* Serial controller programming interface */ 288 static const struct pci_class pci_interface_serial[] = { 289 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 290 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 291 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 292 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 293 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 294 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 295 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 296 { NULL, 0, NULL, }, 297 }; 298 299 /* Parallel controller programming interface */ 300 static const struct pci_class pci_interface_parallel[] = { 301 { "", PCI_INTERFACE_PARALLEL, NULL,}, 302 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 303 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 304 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 305 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 306 { NULL, 0, NULL,}, 307 }; 308 309 /* Modem programming interface */ 310 static const struct pci_class pci_interface_modem[] = { 311 { "", PCI_INTERFACE_MODEM, NULL,}, 312 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 313 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 314 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 315 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 316 { NULL, 0, NULL,}, 317 }; 318 319 /* Subclasses */ 320 static const struct pci_class pci_subclass_communications[] = { 321 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 322 pci_interface_serial, }, 323 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 324 pci_interface_parallel, }, 325 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 326 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 327 pci_interface_modem, }, 328 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 329 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 330 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 331 { NULL, 0, NULL,}, 332 }; 333 334 /* 335 * Class 0x08. 336 * Base system peripheral. 337 */ 338 339 /* PIC programming interface */ 340 static const struct pci_class pci_interface_pic[] = { 341 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 342 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 343 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 344 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 345 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 346 { NULL, 0, NULL, }, 347 }; 348 349 /* DMA programming interface */ 350 static const struct pci_class pci_interface_dma[] = { 351 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 352 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 353 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 354 { NULL, 0, NULL, }, 355 }; 356 357 /* Timer programming interface */ 358 static const struct pci_class pci_interface_tmr[] = { 359 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 360 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 361 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 362 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 363 { NULL, 0, NULL, }, 364 }; 365 366 /* RTC programming interface */ 367 static const struct pci_class pci_interface_rtc[] = { 368 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 369 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 370 { NULL, 0, NULL, }, 371 }; 372 373 /* Subclasses */ 374 static const struct pci_class pci_subclass_system[] = { 375 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 376 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 377 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 378 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 379 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 380 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 381 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 382 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 383 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 384 { NULL, 0, NULL, }, 385 }; 386 387 /* 388 * Class 0x09. 389 * Input device. 390 */ 391 392 /* Gameport programming interface */ 393 static const struct pci_class pci_interface_game[] = { 394 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 395 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 396 { NULL, 0, NULL, }, 397 }; 398 399 /* Subclasses */ 400 static const struct pci_class pci_subclass_input[] = { 401 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 402 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 403 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 404 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 405 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 406 pci_interface_game, }, 407 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 408 { NULL, 0, NULL, }, 409 }; 410 411 /* 412 * Class 0x0a. 413 * Docking station. 414 */ 415 static const struct pci_class pci_subclass_dock[] = { 416 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 417 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 418 { NULL, 0, NULL, }, 419 }; 420 421 /* 422 * Class 0x0b. 423 * Processor. 424 */ 425 static const struct pci_class pci_subclass_processor[] = { 426 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 427 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 428 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 429 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 430 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 431 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 432 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 433 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 434 { NULL, 0, NULL, }, 435 }; 436 437 /* 438 * Class 0x0c. 439 * Serial bus controller. 440 */ 441 442 /* IEEE1394 programming interface */ 443 static const struct pci_class pci_interface_ieee1394[] = { 444 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 445 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 446 { NULL, 0, NULL,}, 447 }; 448 449 /* USB programming interface */ 450 static const struct pci_class pci_interface_usb[] = { 451 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 452 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 453 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 454 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 455 { "USB4 HCI", PCI_INTERFACE_USB_USB4HCI, NULL, }, 456 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 457 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 458 { NULL, 0, NULL, }, 459 }; 460 461 /* IPMI programming interface */ 462 static const struct pci_class pci_interface_ipmi[] = { 463 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL, }, 464 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL, }, 465 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL, }, 466 { NULL, 0, NULL, }, 467 }; 468 469 /* Subclasses */ 470 static const struct pci_class pci_subclass_serialbus[] = { 471 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 472 pci_interface_ieee1394, }, 473 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 474 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 475 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 476 pci_interface_usb, }, 477 /* XXX Fiber Channel/_FIBRECHANNEL */ 478 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 479 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 480 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 481 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 482 pci_interface_ipmi, }, 483 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 484 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 485 { "MIPI I3C", PCI_SUBCLASS_SERIALBUS_MIPI_I3C, NULL, }, 486 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 487 { NULL, 0, NULL, }, 488 }; 489 490 /* 491 * Class 0x0d. 492 * Wireless Controller. 493 */ 494 static const struct pci_class pci_subclass_wireless[] = { 495 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 496 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 497 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 498 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 499 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 500 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 501 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 502 { "Cellular", PCI_SUBCLASS_WIRELESS_CELL, NULL, }, 503 { "Cellular + Ethernet", PCI_SUBCLASS_WIRELESS_CELL_E, NULL, }, 504 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 505 { NULL, 0, NULL, }, 506 }; 507 508 /* 509 * Class 0x0e. 510 * Intelligent IO controller. 511 */ 512 513 /* Intelligent IO programming interface */ 514 static const struct pci_class pci_interface_i2o[] = { 515 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL, }, 516 { NULL, 0, NULL, }, 517 }; 518 519 /* Subclasses */ 520 static const struct pci_class pci_subclass_i2o[] = { 521 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 522 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 523 { NULL, 0, NULL, }, 524 }; 525 526 /* 527 * Class 0x0f. 528 * Satellite communication controller. 529 */ 530 static const struct pci_class pci_subclass_satcom[] = { 531 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 532 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 533 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 534 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 535 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 536 { NULL, 0, NULL, }, 537 }; 538 539 /* 540 * Class 0x10. 541 * Encryption/Decryption controller. 542 */ 543 static const struct pci_class pci_subclass_crypto[] = { 544 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 545 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 546 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 547 { NULL, 0, NULL, }, 548 }; 549 550 /* 551 * Class 0x11. 552 * Data aquuisition and signal processing controller. 553 */ 554 static const struct pci_class pci_subclass_dasp[] = { 555 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 556 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 557 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 558 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 559 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 560 { NULL, 0, NULL, }, 561 }; 562 563 /* List of classes */ 564 static const struct pci_class pci_classes[] = { 565 { "prehistoric", PCI_CLASS_PREHISTORIC, 566 pci_subclass_prehistoric, }, 567 { "mass storage", PCI_CLASS_MASS_STORAGE, 568 pci_subclass_mass_storage, }, 569 { "network", PCI_CLASS_NETWORK, 570 pci_subclass_network, }, 571 { "display", PCI_CLASS_DISPLAY, 572 pci_subclass_display, }, 573 { "multimedia", PCI_CLASS_MULTIMEDIA, 574 pci_subclass_multimedia, }, 575 { "memory", PCI_CLASS_MEMORY, 576 pci_subclass_memory, }, 577 { "bridge", PCI_CLASS_BRIDGE, 578 pci_subclass_bridge, }, 579 { "communications", PCI_CLASS_COMMUNICATIONS, 580 pci_subclass_communications, }, 581 { "system", PCI_CLASS_SYSTEM, 582 pci_subclass_system, }, 583 { "input", PCI_CLASS_INPUT, 584 pci_subclass_input, }, 585 { "dock", PCI_CLASS_DOCK, 586 pci_subclass_dock, }, 587 { "processor", PCI_CLASS_PROCESSOR, 588 pci_subclass_processor, }, 589 { "serial bus", PCI_CLASS_SERIALBUS, 590 pci_subclass_serialbus, }, 591 { "wireless", PCI_CLASS_WIRELESS, 592 pci_subclass_wireless, }, 593 { "I2O", PCI_CLASS_I2O, 594 pci_subclass_i2o, }, 595 { "satellite comm", PCI_CLASS_SATCOM, 596 pci_subclass_satcom, }, 597 { "crypto", PCI_CLASS_CRYPTO, 598 pci_subclass_crypto, }, 599 { "DASP", PCI_CLASS_DASP, 600 pci_subclass_dasp, }, 601 { "processing accelerators", PCI_CLASS_ACCEL, 602 NULL, }, 603 { "non-essential instrumentation", PCI_CLASS_INSTRUMENT, 604 NULL, }, 605 { "undefined", PCI_CLASS_UNDEFINED, 606 NULL, }, 607 { NULL, 0, 608 NULL, }, 609 }; 610 611 DEV_VERBOSE_DEFINE(pci); 612 613 /* 614 * Append a formatted string to dest without writing more than len 615 * characters (including the trailing NUL character). dest and len 616 * are updated for use in subsequent calls to snappendf(). 617 * 618 * Returns 0 on success, a negative value if vnsprintf() fails, or 619 * a positive value if the dest buffer would have overflowed. 620 */ 621 622 static int __printflike(3, 4) 623 snappendf(char **dest, size_t *len, const char * restrict fmt, ...) 624 { 625 va_list ap; 626 int count; 627 628 va_start(ap, fmt); 629 count = vsnprintf(*dest, *len, fmt, ap); 630 va_end(ap); 631 632 /* Let vsnprintf() errors bubble up to caller */ 633 if (count < 0 || *len == 0) 634 return count; 635 636 /* Handle overflow */ 637 if ((size_t)count >= *len) { 638 *dest += *len - 1; 639 *len = 1; 640 return 1; 641 } 642 643 /* Update dest & len to point at trailing NUL */ 644 *dest += count; 645 *len -= count; 646 647 return 0; 648 } 649 650 void 651 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 652 size_t l) 653 { 654 pci_class_t class; 655 pci_subclass_t subclass; 656 pci_interface_t interface; 657 pci_revision_t revision; 658 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 659 const struct pci_class *classp, *subclassp, *interfacep; 660 661 class = PCI_CLASS(class_reg); 662 subclass = PCI_SUBCLASS(class_reg); 663 interface = PCI_INTERFACE(class_reg); 664 revision = PCI_REVISION(class_reg); 665 666 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 667 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 668 PCI_PRODUCT(id_reg)); 669 670 classp = pci_classes; 671 while (classp->name != NULL) { 672 if (class == classp->val) 673 break; 674 classp++; 675 } 676 677 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 678 while (subclassp && subclassp->name != NULL) { 679 if (subclass == subclassp->val) 680 break; 681 subclassp++; 682 } 683 684 interfacep = (subclassp && subclassp->name != NULL) ? 685 subclassp->subclasses : NULL; 686 while (interfacep && interfacep->name != NULL) { 687 if (interface == interfacep->val) 688 break; 689 interfacep++; 690 } 691 692 (void)snappendf(&cp, &l, "%s %s", vendor, product); 693 if (showclass) { 694 (void)snappendf(&cp, &l, " ("); 695 if (classp->name == NULL) 696 (void)snappendf(&cp, &l, 697 "class 0x%02x, subclass 0x%02x", 698 class, subclass); 699 else { 700 if (subclassp == NULL || subclassp->name == NULL) 701 (void)snappendf(&cp, &l, 702 "%s, subclass 0x%02x", 703 classp->name, subclass); 704 else 705 (void)snappendf(&cp, &l, "%s %s", 706 subclassp->name, classp->name); 707 } 708 if ((interfacep == NULL) || (interfacep->name == NULL)) { 709 if (interface != 0) 710 (void)snappendf(&cp, &l, ", interface 0x%02x", 711 interface); 712 } else if (strncmp(interfacep->name, "", 1) != 0) 713 (void)snappendf(&cp, &l, ", %s", interfacep->name); 714 if (revision != 0) 715 (void)snappendf(&cp, &l, ", revision 0x%02x", revision); 716 (void)snappendf(&cp, &l, ")"); 717 } 718 } 719 720 #ifdef _KERNEL 721 void 722 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 723 const char *known, int addrev) 724 { 725 char devinfo[256]; 726 727 if (known) { 728 aprint_normal(": %s", known); 729 if (addrev) 730 aprint_normal(" (rev. 0x%02x)", 731 PCI_REVISION(pa->pa_class)); 732 aprint_normal("\n"); 733 } else { 734 pci_devinfo(pa->pa_id, pa->pa_class, 0, 735 devinfo, sizeof(devinfo)); 736 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 737 PCI_REVISION(pa->pa_class)); 738 } 739 if (naive) 740 aprint_naive(": %s\n", naive); 741 else 742 aprint_naive("\n"); 743 } 744 #endif 745 746 /* 747 * Print out most of the PCI configuration registers. Typically used 748 * in a device attach routine like this: 749 * 750 * #ifdef MYDEV_DEBUG 751 * printf("%s: ", device_xname(sc->sc_dev)); 752 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 753 * #endif 754 */ 755 756 #define i2o(i) ((i) * 4) 757 #define o2i(o) ((o) / 4) 758 #define onoff2(str, rval, bit, onstr, offstr) \ 759 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 760 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 761 762 static void 763 pci_conf_print_common( 764 #ifdef _KERNEL 765 pci_chipset_tag_t pc, pcitag_t tag, 766 #endif 767 const pcireg_t *regs) 768 { 769 pci_class_t class; 770 pci_subclass_t subclass; 771 pci_interface_t interface; 772 pci_revision_t revision; 773 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 774 const struct pci_class *classp, *subclassp, *interfacep; 775 const char *name; 776 pcireg_t rval; 777 unsigned int num; 778 779 rval = regs[o2i(PCI_CLASS_REG)]; 780 class = PCI_CLASS(rval); 781 subclass = PCI_SUBCLASS(rval); 782 interface = PCI_INTERFACE(rval); 783 revision = PCI_REVISION(rval); 784 785 rval = regs[o2i(PCI_ID_REG)]; 786 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 787 if (name) 788 printf(" Vendor Name: %s (0x%04x)\n", name, 789 PCI_VENDOR(rval)); 790 else 791 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 792 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 793 PCI_PRODUCT(rval)); 794 if (name) 795 printf(" Device Name: %s (0x%04x)\n", name, 796 PCI_PRODUCT(rval)); 797 else 798 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 799 800 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 801 802 printf(" Command register: 0x%04x\n", rval & 0xffff); 803 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 804 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 805 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 806 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 807 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 808 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 809 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 810 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 811 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 812 onoff("Fast back-to-back transactions", rval, 813 PCI_COMMAND_BACKTOBACK_ENABLE); 814 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 815 816 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 817 onoff("Immediate Readiness", rval, PCI_STATUS_IMMD_READNESS); 818 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 819 "inactive"); 820 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 821 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 822 onoff("User Definable Features (UDF) support", rval, 823 PCI_STATUS_UDF_SUPPORT); 824 onoff("Fast back-to-back capable", rval, 825 PCI_STATUS_BACKTOBACK_SUPPORT); 826 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 827 828 printf(" DEVSEL timing: "); 829 switch (rval & PCI_STATUS_DEVSEL_MASK) { 830 case PCI_STATUS_DEVSEL_FAST: 831 printf("fast"); 832 break; 833 case PCI_STATUS_DEVSEL_MEDIUM: 834 printf("medium"); 835 break; 836 case PCI_STATUS_DEVSEL_SLOW: 837 printf("slow"); 838 break; 839 default: 840 printf("unknown/reserved"); /* XXX */ 841 break; 842 } 843 printf(" (0x%x)\n", __SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK)); 844 845 onoff("Slave signaled Target Abort", rval, 846 PCI_STATUS_TARGET_TARGET_ABORT); 847 onoff("Master received Target Abort", rval, 848 PCI_STATUS_MASTER_TARGET_ABORT); 849 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 850 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 851 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 852 853 rval = regs[o2i(PCI_CLASS_REG)]; 854 for (classp = pci_classes; classp->name != NULL; classp++) { 855 if (class == classp->val) 856 break; 857 } 858 859 /* 860 * ECN: Change Root Complex Event Collector Class Code 861 * Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type 862 * in PCIe extend capability to know whether it's RCEC or IOMMU. 863 */ 864 if ((class == PCI_CLASS_SYSTEM) 865 && (subclass == PCI_SUBCLASS_SYSTEM_IOMMU)) { 866 int pcie_capoff; 867 pcireg_t reg; 868 869 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 870 reg = regs[o2i(pcie_capoff + PCIE_XCAP)]; 871 if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_RC_EVNTC) 872 subclass = PCI_SUBCLASS_SYSTEM_RCEC; 873 } 874 } 875 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 876 while (subclassp && subclassp->name != NULL) { 877 if (subclass == subclassp->val) 878 break; 879 subclassp++; 880 } 881 882 interfacep = (subclassp && subclassp->name != NULL) ? 883 subclassp->subclasses : NULL; 884 while (interfacep && interfacep->name != NULL) { 885 if (interface == interfacep->val) 886 break; 887 interfacep++; 888 } 889 890 if (classp->name != NULL) 891 printf(" Class Name: %s (0x%02x)\n", classp->name, class); 892 else 893 printf(" Class ID: 0x%02x\n", class); 894 if (subclassp != NULL && subclassp->name != NULL) 895 printf(" Subclass Name: %s (0x%02x)\n", 896 subclassp->name, PCI_SUBCLASS(rval)); 897 else 898 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 899 if ((interfacep != NULL) && (interfacep->name != NULL) 900 && (strncmp(interfacep->name, "", 1) != 0)) 901 printf(" Interface Name: %s (0x%02x)\n", 902 interfacep->name, interface); 903 else 904 printf(" Interface: 0x%02x\n", interface); 905 printf(" Revision ID: 0x%02x\n", revision); 906 907 rval = regs[o2i(PCI_BHLC_REG)]; 908 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 909 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 910 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 911 PCI_HDRTYPE(rval)); 912 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 913 num = PCI_CACHELINE(rval); 914 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 915 } 916 917 static int 918 pci_conf_print_bar( 919 #ifdef _KERNEL 920 pci_chipset_tag_t pc, pcitag_t tag, 921 #endif 922 const pcireg_t *regs, int reg, const char *name) 923 { 924 int width; 925 pcireg_t rval, rval64h; 926 bool ioen, memen; 927 #ifdef _KERNEL 928 pcireg_t mask, mask64h = 0; 929 #endif 930 931 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 932 ioen = rval & PCI_COMMAND_IO_ENABLE; 933 memen = rval & PCI_COMMAND_MEM_ENABLE; 934 935 width = 4; 936 /* 937 * Section 6.2.5.1, `Address Maps', tells us that: 938 * 939 * 1) The builtin software should have already mapped the 940 * device in a reasonable way. 941 * 942 * 2) A device which wants 2^n bytes of memory will hardwire 943 * the bottom n bits of the address to 0. As recommended, 944 * we write all 1s and see what we get back. 945 */ 946 947 rval = regs[o2i(reg)]; 948 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 949 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 950 rval64h = regs[o2i(reg + 4)]; 951 width = 8; 952 } else 953 rval64h = 0; 954 955 #ifdef _KERNEL 956 if (rval != 0 && memen) { 957 int s; 958 959 /* 960 * The following sequence seems to make some devices 961 * (e.g. host bus bridges, which don't normally 962 * have their space mapped) very unhappy, to 963 * the point of crashing the system. 964 * 965 * Therefore, if the mapping register is zero to 966 * start out with, don't bother trying. 967 */ 968 s = splhigh(); 969 pci_conf_write(pc, tag, reg, 0xffffffff); 970 mask = pci_conf_read(pc, tag, reg); 971 pci_conf_write(pc, tag, reg, rval); 972 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 973 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 974 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 975 mask64h = pci_conf_read(pc, tag, reg + 4); 976 pci_conf_write(pc, tag, reg + 4, rval64h); 977 } 978 splx(s); 979 } else 980 mask = mask64h = 0; 981 #endif /* _KERNEL */ 982 983 printf(" Base address register at 0x%02x", reg); 984 if (name) 985 printf(" (%s)", name); 986 printf("\n "); 987 if (rval == 0) { 988 printf("not implemented\n"); 989 return width; 990 } 991 printf("type: "); 992 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 993 const char *type, *prefetch; 994 995 switch (PCI_MAPREG_MEM_TYPE(rval)) { 996 case PCI_MAPREG_MEM_TYPE_32BIT: 997 type = "32-bit"; 998 break; 999 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 1000 type = "32-bit-1M"; 1001 break; 1002 case PCI_MAPREG_MEM_TYPE_64BIT: 1003 type = "64-bit"; 1004 break; 1005 default: 1006 type = "unknown (XXX)"; 1007 break; 1008 } 1009 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 1010 prefetch = ""; 1011 else 1012 prefetch = "non"; 1013 printf("%s %sprefetchable memory\n", type, prefetch); 1014 switch (PCI_MAPREG_MEM_TYPE(rval)) { 1015 case PCI_MAPREG_MEM_TYPE_64BIT: 1016 printf(" base: 0x%016llx", 1017 PCI_MAPREG_MEM64_ADDR( 1018 ((((long long) rval64h) << 32) | rval))); 1019 if (!memen) 1020 printf(", disabled"); 1021 printf("\n"); 1022 #ifdef _KERNEL 1023 printf(" size: 0x%016llx\n", 1024 PCI_MAPREG_MEM64_SIZE( 1025 ((((long long) mask64h) << 32) | mask))); 1026 #endif 1027 break; 1028 case PCI_MAPREG_MEM_TYPE_32BIT: 1029 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 1030 default: 1031 printf(" base: 0x%08x", 1032 PCI_MAPREG_MEM_ADDR(rval)); 1033 if (!memen) 1034 printf(", disabled"); 1035 printf("\n"); 1036 #ifdef _KERNEL 1037 printf(" size: 0x%08x\n", 1038 PCI_MAPREG_MEM_SIZE(mask)); 1039 #endif 1040 break; 1041 } 1042 } else { 1043 #ifdef _KERNEL 1044 if (ioen) 1045 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 1046 #endif 1047 printf("I/O\n"); 1048 printf(" base: 0x%08x", PCI_MAPREG_IO_ADDR(rval)); 1049 if (!ioen) 1050 printf(", disabled"); 1051 printf("\n"); 1052 #ifdef _KERNEL 1053 printf(" size: 0x%08x\n", PCI_MAPREG_IO_SIZE(mask)); 1054 #endif 1055 } 1056 1057 return width; 1058 } 1059 1060 static void 1061 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 1062 { 1063 int off, needaddr, neednl; 1064 1065 needaddr = 1; 1066 neednl = 0; 1067 for (off = first; off < pastlast; off += 4) { 1068 if ((off % 16) == 0 || needaddr) { 1069 printf(" 0x%02x:", off); 1070 needaddr = 0; 1071 } 1072 printf(" 0x%08x", regs[o2i(off)]); 1073 neednl = 1; 1074 if ((off % 16) == 12) { 1075 printf("\n"); 1076 neednl = 0; 1077 } 1078 } 1079 if (neednl) 1080 printf("\n"); 1081 } 1082 1083 static const char * 1084 pci_conf_print_agp_calcycle(uint8_t cal) 1085 { 1086 1087 switch (cal) { 1088 case 0x0: 1089 return "4ms"; 1090 case 0x1: 1091 return "16ms"; 1092 case 0x2: 1093 return "64ms"; 1094 case 0x3: 1095 return "256ms"; 1096 case 0x7: 1097 return "Calibration Cycle Not Needed"; 1098 default: 1099 return "(reserved)"; 1100 } 1101 } 1102 1103 static void 1104 pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3) 1105 { 1106 if (isagp3) { 1107 /* AGP 3.0 */ 1108 if (reg & AGP_MODE_V3_RATE_4x) 1109 printf("x4"); 1110 if (reg & AGP_MODE_V3_RATE_8x) 1111 printf("x8"); 1112 } else { 1113 /* AGP 2.0 */ 1114 if (reg & AGP_MODE_V2_RATE_1x) 1115 printf("x1"); 1116 if (reg & AGP_MODE_V2_RATE_2x) 1117 printf("x2"); 1118 if (reg & AGP_MODE_V2_RATE_4x) 1119 printf("x4"); 1120 } 1121 printf("\n"); 1122 } 1123 1124 static void 1125 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1126 { 1127 pcireg_t rval; 1128 bool isagp3; 1129 1130 printf("\n AGP Capabilities Register\n"); 1131 1132 rval = regs[o2i(capoff)]; 1133 printf(" Revision: %d.%d\n", 1134 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1135 1136 rval = regs[o2i(capoff + PCI_AGP_STATUS)]; 1137 printf(" Status register: 0x%04x\n", rval); 1138 printf(" RQ: %d\n", 1139 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1140 printf(" ARQSZ: %d\n", 1141 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1142 printf(" CAL cycle: %s\n", 1143 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1144 onoff("SBA", rval, AGP_MODE_SBA); 1145 onoff("htrans#", rval, AGP_MODE_HTRANS); 1146 onoff("Over 4G", rval, AGP_MODE_4G); 1147 onoff("Fast Write", rval, AGP_MODE_FW); 1148 onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3); 1149 isagp3 = rval & AGP_MODE_MODE_3; 1150 printf(" Data Rate Support: "); 1151 pci_conf_print_agp_datarate(rval, isagp3); 1152 1153 rval = regs[o2i(capoff + PCI_AGP_COMMAND)]; 1154 printf(" Command register: 0x%08x\n", rval); 1155 printf(" PRQ: %d\n", 1156 (unsigned int)__SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1157 printf(" PARQSZ: %d\n", 1158 (unsigned int)__SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1159 printf(" PCAL cycle: %s\n", 1160 pci_conf_print_agp_calcycle(__SHIFTOUT(rval, AGP_MODE_CAL))); 1161 onoff("SBA", rval, AGP_MODE_SBA); 1162 onoff("AGP", rval, AGP_MODE_AGP); 1163 onoff("Over 4G", rval, AGP_MODE_4G); 1164 onoff("Fast Write", rval, AGP_MODE_FW); 1165 if (isagp3) { 1166 printf(" Data Rate Enable: "); 1167 /* 1168 * The Data Rate Enable bits are used only on 3.0 and the 1169 * Command register has no AGP_MODE_MODE_3 bit, so pass the 1170 * flag to print correctly. 1171 */ 1172 pci_conf_print_agp_datarate(rval, isagp3); 1173 } 1174 } 1175 1176 static const char * 1177 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1178 { 1179 1180 switch ((caps >> 6) & 7) { 1181 case 0: return "self-powered"; 1182 case 1: return "55 mA"; 1183 case 2: return "100 mA"; 1184 case 3: return "160 mA"; 1185 case 4: return "220 mA"; 1186 case 5: return "270 mA"; 1187 case 6: return "320 mA"; 1188 case 7: 1189 default: return "375 mA"; 1190 } 1191 } 1192 1193 static const char * 1194 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1195 { 1196 static const char unk[] = "unknown"; 1197 static const char *pmrev[8] = { 1198 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1199 }; 1200 if (val > 7) 1201 return unk; 1202 return pmrev[val]; 1203 } 1204 1205 static void 1206 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1207 { 1208 uint16_t caps, pmcsr; 1209 1210 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1211 pmcsr = regs[o2i(capoff + PCI_PMCSR)]; 1212 1213 printf("\n PCI Power Management Capabilities Register\n"); 1214 1215 printf(" Capabilities register: 0x%04x\n", caps); 1216 printf(" Version: %s\n", 1217 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1218 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1219 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1220 printf(" 3.3V auxiliary current: %s\n", 1221 pci_conf_print_pcipm_cap_aux(caps)); 1222 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1223 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1224 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1225 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1226 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1227 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1228 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1229 1230 printf(" Control/status register: 0x%08x\n", pmcsr); 1231 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1232 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1233 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1234 printf(" PME# assertion: %sabled\n", 1235 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1236 printf(" Data Select: %d\n", 1237 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK)); 1238 printf(" Data Scale: %d\n", 1239 __SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK)); 1240 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1241 printf(" Bridge Support Extensions register: 0x%02x\n", 1242 (pmcsr >> 16) & 0xff); 1243 onoff("B2/B3 support", pmcsr, PCI_PMCSR_B2B3_SUPPORT); 1244 onoff("Bus Power/Clock Control Enable", pmcsr, PCI_PMCSR_BPCC_EN); 1245 printf(" Data register: 0x%02x\n", 1246 __SHIFTOUT(pmcsr, PCI_PMCSR_DATA)); 1247 } 1248 1249 /* XXX pci_conf_print_vpd_cap */ 1250 /* XXX pci_conf_print_slotid_cap */ 1251 1252 static void 1253 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1254 { 1255 uint32_t ctl, mmc, mme; 1256 1257 regs += o2i(capoff); 1258 ctl = *regs++; 1259 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1260 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1261 1262 printf("\n PCI Message Signaled Interrupt\n"); 1263 1264 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1265 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1266 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1267 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1268 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1269 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1270 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1271 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1272 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP); 1273 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN); 1274 printf(" Message Address %sregister: 0x%08x\n", 1275 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1276 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1277 printf(" Message Address %sregister: 0x%08x\n", 1278 "(upper) ", *regs++); 1279 } 1280 printf(" Message Data register: "); 1281 if (ctl & PCI_MSI_CTL_EXTMDATA_CAP) 1282 printf("0x%08x\n", *regs); 1283 else 1284 printf("0x%04x\n", *regs & 0xffff); 1285 regs++; 1286 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1287 printf(" Vector Mask register: 0x%08x\n", *regs++); 1288 printf(" Vector Pending register: 0x%08x\n", *regs++); 1289 } 1290 } 1291 1292 /* XXX pci_conf_print_cpci_hostwap_cap */ 1293 1294 /* 1295 * For both command register and status register. 1296 * The argument "idx" is index number (0 to 7). 1297 */ 1298 static int 1299 pcix_split_trans(unsigned int idx) 1300 { 1301 static int table[8] = { 1302 1, 2, 3, 4, 8, 12, 16, 32 1303 }; 1304 1305 if (idx >= __arraycount(table)) 1306 return -1; 1307 return table[idx]; 1308 } 1309 1310 static void 1311 pci_conf_print_pcix_cap_2ndbusmode(int num) 1312 { 1313 const char *maxfreq, *maxperiod; 1314 1315 printf(" Mode: "); 1316 if (num <= 0x07) 1317 printf("PCI-X Mode 1\n"); 1318 else if (num <= 0x0b) 1319 printf("PCI-X 266 (Mode 2)\n"); 1320 else 1321 printf("PCI-X 533 (Mode 2)\n"); 1322 1323 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1324 switch (num & 0x03) { 1325 default: 1326 case 0: 1327 maxfreq = "N/A"; 1328 maxperiod = "N/A"; 1329 break; 1330 case 1: 1331 maxfreq = "66MHz"; 1332 maxperiod = "15ns"; 1333 break; 1334 case 2: 1335 maxfreq = "100MHz"; 1336 maxperiod = "10ns"; 1337 break; 1338 case 3: 1339 maxfreq = "133MHz"; 1340 maxperiod = "7.5ns"; 1341 break; 1342 } 1343 printf(" Max Clock Freq: %s\n", maxfreq); 1344 printf(" Min Clock Period: %s\n", maxperiod); 1345 } 1346 1347 static void 1348 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1349 { 1350 pcireg_t reg; 1351 int isbridge; 1352 int i; 1353 1354 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1355 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1356 printf("\n PCI-X %s Capabilities Register\n", 1357 isbridge ? "Bridge" : "Non-bridge"); 1358 1359 reg = regs[o2i(capoff)]; 1360 if (isbridge != 0) { 1361 printf(" Secondary status register: 0x%04x\n", 1362 (reg & 0xffff0000) >> 16); 1363 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1364 onoff("133MHz capable", reg, PCIX_STATUS_133); 1365 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1366 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1367 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1368 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1369 pci_conf_print_pcix_cap_2ndbusmode( 1370 __SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1371 printf(" Version: 0x%x\n", 1372 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1373 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1374 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1375 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1376 } else { 1377 printf(" Command register: 0x%04x\n", 1378 (reg & 0xffff0000) >> 16); 1379 onoff("Data Parity Error Recovery", reg, 1380 PCIX_CMD_PERR_RECOVER); 1381 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1382 printf(" Maximum Burst Read Count: %u\n", 1383 PCIX_CMD_BYTECNT(reg)); 1384 printf(" Maximum Split Transactions: %d\n", 1385 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1386 >> PCIX_CMD_SPLTRANS_SHIFT)); 1387 } 1388 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1389 printf(" %sStatus register: 0x%08x\n", 1390 isbridge ? "Bridge " : "", reg); 1391 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1392 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1393 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1394 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1395 onoff("133MHz capable", reg, PCIX_STATUS_133); 1396 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1397 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1398 if (isbridge != 0) { 1399 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1400 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1401 } else { 1402 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1403 "bridge device", "simple device"); 1404 printf(" Designed max memory read byte count: %d\n", 1405 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1406 >> PCIX_STATUS_MAXB_SHIFT)); 1407 printf(" Designed max outstanding split transaction: %d\n", 1408 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1409 >> PCIX_STATUS_MAXST_SHIFT)); 1410 printf(" MAX cumulative Read Size: %u\n", 1411 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1412 onoff("Received split completion error", reg, 1413 PCIX_STATUS_SCERR); 1414 } 1415 onoff("266MHz capable", reg, PCIX_STATUS_266); 1416 onoff("533MHz capable", reg, PCIX_STATUS_533); 1417 1418 if (isbridge == 0) 1419 return; 1420 1421 /* Only for bridge */ 1422 for (i = 0; i < 2; i++) { 1423 reg = regs[o2i(capoff + PCIX_BRIDGE_UP_STCR + (4 * i))]; 1424 printf(" %s split transaction control register: 0x%08x\n", 1425 (i == 0) ? "Upstream" : "Downstream", reg); 1426 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1427 printf(" Commitment Limit: %d\n", 1428 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1429 } 1430 } 1431 1432 /* pci_conf_print_ht_slave_cap */ 1433 /* pci_conf_print_ht_host_cap */ 1434 /* pci_conf_print_ht_switch_cap */ 1435 /* pci_conf_print_ht_intr_cap */ 1436 /* pci_conf_print_ht_revid_cap */ 1437 /* pci_conf_print_ht_unitid_cap */ 1438 /* pci_conf_print_ht_extcnf_cap */ 1439 /* pci_conf_print_ht_addrmap_cap */ 1440 /* pci_conf_print_ht_msimap_cap */ 1441 1442 static void 1443 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1444 { 1445 pcireg_t val; 1446 uint32_t lo, hi; 1447 1448 /* 1449 * Print the rest of the command register bits. Others are 1450 * printed in pci_conf_print_ht_cap(). 1451 */ 1452 val = regs[o2i(capoff + PCI_HT_CMD)]; 1453 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1454 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1455 1456 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1457 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1458 printf(" Address Low register: 0x%08x\n", lo); 1459 printf(" Address high register: 0x%08x\n", hi); 1460 printf(" Address: 0x%016" PRIx64 "\n", 1461 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1462 } 1463 1464 /* pci_conf_print_ht_droute_cap */ 1465 /* pci_conf_print_ht_vcset_cap */ 1466 /* pci_conf_print_ht_retry_cap */ 1467 /* pci_conf_print_ht_x86enc_cap */ 1468 /* pci_conf_print_ht_gen3_cap */ 1469 /* pci_conf_print_ht_fle_cap */ 1470 /* pci_conf_print_ht_pm_cap */ 1471 /* pci_conf_print_ht_hnc_cap */ 1472 1473 static const struct ht_types { 1474 pcireg_t cap; 1475 const char *name; 1476 void (*printfunc)(const pcireg_t *, int); 1477 } ht_captab[] = { 1478 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1479 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1480 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1481 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1482 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1483 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1484 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1485 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1486 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1487 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1488 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1489 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1490 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1491 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1492 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1493 {PCI_HT_CAP_PM, "Power Management", NULL }, 1494 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1495 }; 1496 1497 static void 1498 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1499 { 1500 pcireg_t val, foundcap; 1501 unsigned int off; 1502 1503 val = regs[o2i(capoff + PCI_HT_CMD)]; 1504 1505 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1506 1507 printf(" Command register: 0x%04x\n", val >> 16); 1508 foundcap = PCI_HT_CAP(val); 1509 for (off = 0; off < __arraycount(ht_captab); off++) { 1510 if (ht_captab[off].cap == foundcap) 1511 break; 1512 } 1513 printf(" Capability Type: 0x%02x ", foundcap); 1514 if (off >= __arraycount(ht_captab)) { 1515 printf("(unknown)\n"); 1516 return; 1517 } 1518 printf("(%s)\n", ht_captab[off].name); 1519 if (ht_captab[off].printfunc != NULL) 1520 ht_captab[off].printfunc(regs, capoff); 1521 } 1522 1523 static void 1524 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1525 { 1526 uint16_t caps; 1527 1528 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1529 1530 printf("\n PCI Vendor Specific Capabilities Register\n"); 1531 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1532 } 1533 1534 static void 1535 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1536 { 1537 pcireg_t val; 1538 1539 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1540 1541 printf("\n Debugport Capability Register\n"); 1542 printf(" Debug base Register: 0x%04x\n", 1543 val >> PCI_DEBUG_BASER_SHIFT); 1544 printf(" port offset: 0x%04x\n", 1545 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1546 printf(" BAR number: %u\n", 1547 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1548 } 1549 1550 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1551 /* XXX pci_conf_print_hotplug_cap */ 1552 1553 static void 1554 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1555 { 1556 pcireg_t reg; 1557 1558 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1559 1560 printf("\n Subsystem ID Capability Register\n"); 1561 printf(" Subsystem ID: 0x%08x\n", reg); 1562 } 1563 1564 /* XXX pci_conf_print_agp8_cap */ 1565 static void 1566 pci_conf_print_secure_cap(const pcireg_t *regs, int capoff) 1567 { 1568 pcireg_t reg, reg2, val; 1569 bool havemisc1; 1570 1571 printf("\n Secure Capability Register\n"); 1572 reg = regs[o2i(capoff + PCI_SECURE_CAP)]; 1573 printf(" Capability Register: 0x%04x\n", reg >> 16); 1574 val = __SHIFTOUT(reg, PCI_SECURE_CAP_TYPE); 1575 printf(" Capability block type: "); 1576 /* I know IOMMU Only */ 1577 if (val == PCI_SECURE_CAP_TYPE_IOMMU) 1578 printf("IOMMU\n"); 1579 else { 1580 printf("0x%x(unknown)\n", val); 1581 return; 1582 } 1583 1584 val = __SHIFTOUT(reg, PCI_SECURE_CAP_REV); 1585 printf(" Capability revision: 0x%02x ", val); 1586 if (val == PCI_SECURE_CAP_REV_IOMMU) 1587 printf("(IOMMU)\n"); 1588 else { 1589 printf("(unknown)\n"); 1590 return; 1591 } 1592 onoff("IOTLB support", reg, PCI_SECURE_CAP_IOTLBSUP); 1593 onoff("HyperTransport tunnel translation support", reg, 1594 PCI_SECURE_CAP_HTTUNNEL); 1595 onoff("Not present table entries cached", reg, PCI_SECURE_CAP_NPCACHE); 1596 onoff("IOMMU Extended Feature Register support", reg, 1597 PCI_SECURE_CAP_EFRSUP); 1598 onoff("IOMMU Miscellaneous Information Register 1", reg, 1599 PCI_SECURE_CAP_EXT); 1600 havemisc1 = reg & PCI_SECURE_CAP_EXT; 1601 1602 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_BAL)]; 1603 printf(" Base Address Low Register: 0x%08x\n", reg); 1604 onoff("Enable", reg, PCI_SECURE_IOMMU_BAL_EN); 1605 reg2 = regs[o2i(capoff + PCI_SECURE_IOMMU_BAH)]; 1606 printf(" Base Address High Register: 0x%08x\n", reg2); 1607 printf(" Base Address: 0x%016" PRIx64 "\n", 1608 ((uint64_t)reg2 << 32) 1609 | (reg & (PCI_SECURE_IOMMU_BAL_H | PCI_SECURE_IOMMU_BAL_L))); 1610 1611 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_RANGE)]; 1612 printf(" IOMMU Range Register: 0x%08x\n", reg); 1613 printf(" HyperTransport UnitID: 0x%02x\n", 1614 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_UNITID)); 1615 onoff("Range valid", reg, PCI_SECURE_IOMMU_RANGE_RNGVALID); 1616 printf(" Device range bus number: 0x%02x\n", 1617 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_BUSNUM)); 1618 printf(" First device: 0x%04x\n", 1619 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_FIRSTDEV)); 1620 printf(" Last device: 0x%04x\n", 1621 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_LASTDEV)); 1622 1623 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC0)]; 1624 printf(" Miscellaneous Information Register 0: 0x%08x\n", reg); 1625 printf(" MSI Message number: 0x%02x\n", 1626 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MSINUM)); 1627 val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_GVASIZE); 1628 printf(" Guest Virtual Address size: "); 1629 if (val == PCI_SECURE_IOMMU_MISC0_GVASIZE_48B) 1630 printf("48bits\n"); 1631 else 1632 printf("0x%x(unknown)\n", val); 1633 val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_PASIZE); 1634 printf(" Physical Address size: %dbits\n", val); 1635 val = __SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_VASIZE); 1636 printf(" Virtual Address size: %dbits\n", val); 1637 onoff("ATS response address range reserved", reg, 1638 PCI_SECURE_IOMMU_MISC0_ATSRESV); 1639 printf(" Peripheral Page Request MSI Message number: 0x%02x\n", 1640 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MISNPPR)); 1641 1642 if (!havemisc1) 1643 return; 1644 1645 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC1)]; 1646 printf(" Miscellaneous Information Register 1: 0x%08x\n", reg); 1647 printf(" MSI Message number (GA): 0x%02x\n", 1648 (uint32_t)__SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC1_MSINUM)); 1649 } 1650 1651 static void 1652 pci_print_pcie_L0s_latency(uint32_t val) 1653 { 1654 1655 switch (val) { 1656 case 0x0: 1657 printf("Less than 64ns\n"); 1658 break; 1659 case 0x1: 1660 case 0x2: 1661 case 0x3: 1662 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1663 break; 1664 case 0x4: 1665 printf("512ns to less than 1us\n"); 1666 break; 1667 case 0x5: 1668 printf("1us to less than 2us\n"); 1669 break; 1670 case 0x6: 1671 printf("2us - 4us\n"); 1672 break; 1673 case 0x7: 1674 printf("More than 4us\n"); 1675 break; 1676 } 1677 } 1678 1679 static void 1680 pci_print_pcie_L1_latency(uint32_t val) 1681 { 1682 1683 switch (val) { 1684 case 0x0: 1685 printf("Less than 1us\n"); 1686 break; 1687 case 0x6: 1688 printf("32us - 64us\n"); 1689 break; 1690 case 0x7: 1691 printf("More than 64us\n"); 1692 break; 1693 default: 1694 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1695 break; 1696 } 1697 } 1698 1699 static void 1700 pci_print_pcie_compl_timeout(uint32_t val) 1701 { 1702 1703 switch (val) { 1704 case 0x0: 1705 printf("50us to 50ms\n"); 1706 break; 1707 case 0x5: 1708 printf("16ms to 55ms\n"); 1709 break; 1710 case 0x6: 1711 printf("65ms to 210ms\n"); 1712 break; 1713 case 0x9: 1714 printf("260ms to 900ms\n"); 1715 break; 1716 case 0xa: 1717 printf("1s to 3.5s\n"); 1718 break; 1719 default: 1720 printf("unknown %u value\n", val); 1721 break; 1722 } 1723 } 1724 1725 static const char * const pcie_linkspeeds[] = { 1726 "2.5", "5.0", "8.0", "16.0", "32.0" 1727 }; 1728 1729 /* 1730 * Print link speed. This function is used for the following register bits: 1731 * Maximum Link Speed in LCAP 1732 * Current Link Speed in LCSR 1733 * Target Link Speed in LCSR2 1734 * All of above bitfield's values start from 1. 1735 * For LCSR2, 0 is allowed for a device which supports 2.5GT/s only (and 1736 * this check also works for devices which compliant to versions of the base 1737 * specification prior to 3.0. 1738 */ 1739 static void 1740 pci_print_pcie_linkspeed(int regnum, pcireg_t val) 1741 { 1742 1743 if ((regnum == PCIE_LCSR2) && (val == 0)) 1744 printf("2.5GT/s\n"); 1745 else if ((val < 1) || (val > __arraycount(pcie_linkspeeds))) 1746 printf("unknown value (%u)\n", val); 1747 else 1748 printf("%sGT/s\n", pcie_linkspeeds[val - 1]); 1749 } 1750 1751 /* 1752 * Print link speed "vector". 1753 * This function is used for the following register bits: 1754 * Supported Link Speeds Vector in LCAP2 1755 * Lower SKP OS Generation Supported Speed Vector in LCAP2 1756 * Lower SKP OS Reception Supported Speed Vector in LCAP2 1757 * Enable Lower SKP OS Generation Vector in LCTL3 1758 * All of above bitfield's values start from 0. 1759 */ 1760 static void 1761 pci_print_pcie_linkspeedvector(pcireg_t val) 1762 { 1763 unsigned int i; 1764 1765 /* Start from 0 */ 1766 for (i = 0; i < 16; i++) 1767 if (((val >> i) & 0x01) != 0) { 1768 if (i >= __arraycount(pcie_linkspeeds)) 1769 printf(" unknown vector (0x%x)", 1 << i); 1770 else 1771 printf(" %sGT/s", pcie_linkspeeds[i]); 1772 } 1773 } 1774 1775 static void 1776 pci_print_pcie_link_deemphasis(pcireg_t val) 1777 { 1778 switch (val) { 1779 case 0: 1780 printf("-6dB"); 1781 break; 1782 case 1: 1783 printf("-3.5dB"); 1784 break; 1785 default: 1786 printf("(reserved value)"); 1787 } 1788 } 1789 1790 static const struct _pcie_link_preset_preshoot_deemphasis { 1791 const char *preshoot; 1792 const char *deemphasis; 1793 } pcie_link_preset_preshoot_deemphasis[] = { 1794 { "0.0", "-6.0+-1.5" }, /* P0 */ 1795 { "0.0", "-3.5+-1" }, /* P1 */ 1796 { "0.0", "-4.4+-1.5" }, /* P2 */ 1797 { "0.0", "-2.5+-1" }, /* P3 */ 1798 { "0.0", "0.0" }, /* P4 */ 1799 { "1.9+-1", "0.0" }, /* P5 */ 1800 { "2.5+-1", "0.0" }, /* P6 */ 1801 { "3.5+-1", "-6.0+-1.5" }, /* P7 */ 1802 { "3.5+-1", "-3.5+-1" }, /* P8 */ 1803 { "3.5+-1", "0.0" }, /* P9 */ 1804 { "0.0", NULL } /* P10 */ 1805 }; 1806 1807 static void 1808 pci_print_pcie_link_preset_preshoot_deemphasis(pcireg_t val) 1809 { 1810 const char *deemphasis; 1811 1812 if (val >= __arraycount(pcie_link_preset_preshoot_deemphasis)) { 1813 /* 1814 * This may be printed because the default value of some 1815 * register fields is 0b1111. 1816 */ 1817 printf("reserved value (0x%x)", val); 1818 return; 1819 } 1820 1821 printf("Preshoot %sdB", 1822 pcie_link_preset_preshoot_deemphasis[val].preshoot); 1823 deemphasis = pcie_link_preset_preshoot_deemphasis[val].deemphasis; 1824 1825 if (deemphasis != NULL) 1826 printf(", De-emphasis %sdB", deemphasis); 1827 } 1828 1829 static void 1830 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1831 { 1832 pcireg_t reg; /* for each register */ 1833 pcireg_t val; /* for each bitfield */ 1834 bool check_slot = false; 1835 unsigned int pcie_devtype; 1836 bool check_upstreamport = false; 1837 unsigned int pciever; 1838 unsigned int i; 1839 1840 printf("\n PCI Express Capabilities Register\n"); 1841 /* Capability Register */ 1842 reg = regs[o2i(capoff)]; 1843 printf(" Capability register: 0x%04x\n", reg >> 16); 1844 pciever = (unsigned int)(PCIE_XCAP_VER(reg)); 1845 printf(" Capability version: %u\n", pciever); 1846 printf(" Device type: "); 1847 pcie_devtype = PCIE_XCAP_TYPE(reg); 1848 switch (pcie_devtype) { 1849 case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */ 1850 printf("PCI Express Endpoint device\n"); 1851 check_upstreamport = true; 1852 break; 1853 case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */ 1854 printf("Legacy PCI Express Endpoint device\n"); 1855 check_upstreamport = true; 1856 break; 1857 case PCIE_XCAP_TYPE_RP: /* 0x4 */ 1858 printf("Root Port of PCI Express Root Complex\n"); 1859 check_slot = true; 1860 break; 1861 case PCIE_XCAP_TYPE_UP: /* 0x5 */ 1862 printf("Upstream Port of PCI Express Switch\n"); 1863 check_upstreamport = true; 1864 break; 1865 case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ 1866 printf("Downstream Port of PCI Express Switch\n"); 1867 check_slot = true; 1868 break; 1869 case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ 1870 printf("PCI Express to PCI/PCI-X Bridge\n"); 1871 check_upstreamport = true; 1872 break; 1873 case PCIE_XCAP_TYPE_PCI2PCIE: /* 0x8 */ 1874 printf("PCI/PCI-X to PCI Express Bridge\n"); 1875 /* Upstream port is not PCIe */ 1876 check_slot = true; 1877 break; 1878 case PCIE_XCAP_TYPE_RCIEP: /* 0x9 */ 1879 printf("Root Complex Integrated Endpoint\n"); 1880 break; 1881 case PCIE_XCAP_TYPE_RC_EVNTC: /* 0xa */ 1882 printf("Root Complex Event Collector\n"); 1883 break; 1884 default: 1885 printf("unknown\n"); 1886 break; 1887 } 1888 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1889 printf(" Interrupt Message Number: 0x%02x\n", 1890 (unsigned int)__SHIFTOUT(reg, PCIE_XCAP_IRQ)); 1891 1892 /* Device Capability Register */ 1893 reg = regs[o2i(capoff + PCIE_DCAP)]; 1894 printf(" Device Capabilities Register: 0x%08x\n", reg); 1895 printf(" Max Payload Size Supported: %u bytes max\n", 1896 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1897 printf(" Phantom Functions Supported: "); 1898 switch (__SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) { 1899 case 0x0: 1900 printf("not available\n"); 1901 break; 1902 case 0x1: 1903 printf("MSB\n"); 1904 break; 1905 case 0x2: 1906 printf("two MSB\n"); 1907 break; 1908 case 0x3: 1909 printf("All three bits\n"); 1910 break; 1911 } 1912 printf(" Extended Tag Field Supported: %dbit\n", 1913 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1914 printf(" Endpoint L0 Acceptable Latency: "); 1915 pci_print_pcie_L0s_latency(__SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY)); 1916 printf(" Endpoint L1 Acceptable Latency: "); 1917 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY)); 1918 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1919 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1920 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1921 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1922 if (check_upstreamport) { 1923 printf(" Captured Slot Power Limit: "); 1924 pci_conf_print_pcie_power( 1925 __SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL), 1926 __SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE)); 1927 } 1928 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1929 1930 /* Device Control Register */ 1931 reg = regs[o2i(capoff + PCIE_DCSR)]; 1932 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1933 onoff("Correctable Error Reporting Enable", reg, 1934 PCIE_DCSR_ENA_COR_ERR); 1935 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1936 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1937 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1938 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1939 printf(" Max Payload Size: %d byte\n", 1940 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD)); 1941 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1942 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1943 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1944 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1945 printf(" Max Read Request Size: %d byte\n", 1946 128 << __SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ)); 1947 if (pcie_devtype == PCIE_XCAP_TYPE_PCIE2PCI) 1948 onoff("Bridge Config Retry Enable", reg, 1949 PCIE_DCSR_BRDG_CFG_RETRY); 1950 1951 /* Device Status Register */ 1952 reg = regs[o2i(capoff + PCIE_DCSR)]; 1953 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1954 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1955 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1956 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1957 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1958 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1959 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1960 onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD); 1961 1962 if (PCIE_HAS_LINKREGS(pcie_devtype)) { 1963 /* Link Capability Register */ 1964 reg = regs[o2i(capoff + PCIE_LCAP)]; 1965 printf(" Link Capabilities Register: 0x%08x\n", reg); 1966 printf(" Maximum Link Speed: "); 1967 pci_print_pcie_linkspeed(PCIE_LCAP, reg & PCIE_LCAP_MAX_SPEED); 1968 printf(" Maximum Link Width: x%u lanes\n", 1969 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH)); 1970 printf(" Active State PM Support: "); 1971 switch (__SHIFTOUT(reg, PCIE_LCAP_ASPM)) { 1972 case 0x0: 1973 printf("No ASPM support\n"); 1974 break; 1975 case 0x1: 1976 printf("L0s supported\n"); 1977 break; 1978 case 0x2: 1979 printf("L1 supported\n"); 1980 break; 1981 case 0x3: 1982 printf("L0s and L1 supported\n"); 1983 break; 1984 } 1985 printf(" L0 Exit Latency: "); 1986 pci_print_pcie_L0s_latency(__SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT)); 1987 printf(" L1 Exit Latency: "); 1988 pci_print_pcie_L1_latency(__SHIFTOUT(reg, PCIE_LCAP_L1_EXIT)); 1989 printf(" Port Number: %u\n", 1990 (unsigned int)__SHIFTOUT(reg, PCIE_LCAP_PORT)); 1991 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1992 onoff("Surprise Down Error Report", reg, 1993 PCIE_LCAP_SURPRISE_DOWN); 1994 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1995 onoff("Link BW Notification Capable", reg, 1996 PCIE_LCAP_LINK_BW_NOTIFY); 1997 onoff("ASPM Optionally Compliance", reg, 1998 PCIE_LCAP_ASPM_COMPLIANCE); 1999 2000 /* Link Control Register */ 2001 reg = regs[o2i(capoff + PCIE_LCSR)]; 2002 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 2003 printf(" Active State PM Control: "); 2004 switch (reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S)) { 2005 case 0: 2006 printf("disabled\n"); 2007 break; 2008 case 1: 2009 printf("L0s Entry Enabled\n"); 2010 break; 2011 case 2: 2012 printf("L1 Entry Enabled\n"); 2013 break; 2014 case 3: 2015 printf("L0s and L1 Entry Enabled\n"); 2016 break; 2017 } 2018 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 2019 "128bytes", "64bytes"); 2020 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 2021 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 2022 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 2023 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 2024 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 2025 onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD); 2026 onoff("Link Bandwidth Management Interrupt Enable", reg, 2027 PCIE_LCSR_LBMIE); 2028 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 2029 PCIE_LCSR_LABIE); 2030 printf(" DRS Signaling Control: "); 2031 switch (__SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) { 2032 case 0: 2033 printf("not reported\n"); 2034 break; 2035 case 1: 2036 printf("Interrupt Enabled\n"); 2037 break; 2038 case 2: 2039 printf("DRS to FRS Signaling Enabled\n"); 2040 break; 2041 default: 2042 printf("reserved\n"); 2043 break; 2044 } 2045 2046 /* Link Status Register */ 2047 reg = regs[o2i(capoff + PCIE_LCSR)]; 2048 printf(" Link Status Register: 0x%04x\n", reg >> 16); 2049 printf(" Negotiated Link Speed: "); 2050 pci_print_pcie_linkspeed(PCIE_LCSR, 2051 __SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 2052 printf(" Negotiated Link Width: x%u lanes\n", 2053 (unsigned int)__SHIFTOUT(reg, PCIE_LCSR_NLW)); 2054 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 2055 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 2056 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 2057 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 2058 onoff("Link Bandwidth Management Status", reg, 2059 PCIE_LCSR_LINK_BW_MGMT); 2060 onoff("Link Autonomous Bandwidth Status", reg, 2061 PCIE_LCSR_LINK_AUTO_BW); 2062 } 2063 2064 if (check_slot == true) { 2065 pcireg_t slcap; 2066 2067 /* Slot Capability Register */ 2068 slcap = reg = regs[o2i(capoff + PCIE_SLCAP)]; 2069 printf(" Slot Capability Register: 0x%08x\n", reg); 2070 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 2071 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 2072 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 2073 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 2074 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 2075 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 2076 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 2077 printf(" Slot Power Limit Value: "); 2078 pci_conf_print_pcie_power(__SHIFTOUT(reg, PCIE_SLCAP_SPLV), 2079 __SHIFTOUT(reg, PCIE_SLCAP_SPLS)); 2080 onoff("Electromechanical Interlock Present", reg, 2081 PCIE_SLCAP_EIP); 2082 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 2083 printf(" Physical Slot Number: %d\n", 2084 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 2085 2086 /* Slot Control Register */ 2087 reg = regs[o2i(capoff + PCIE_SLCSR)]; 2088 printf(" Slot Control Register: 0x%04x\n", reg & 0xffff); 2089 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 2090 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 2091 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 2092 onoff("Presence Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 2093 onoff("Command Completed Interrupt Enabled", reg, 2094 PCIE_SLCSR_CCE); 2095 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 2096 /* 2097 * For Attention Indicator Control and Power Indicator Control, 2098 * it's allowed to be a read only value 0 if corresponding 2099 * capability register bit is 0. 2100 */ 2101 if (slcap & PCIE_SLCAP_AIP) { 2102 printf(" Attention Indicator Control: "); 2103 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 2104 case 0x0: 2105 printf("reserved\n"); 2106 break; 2107 case PCIE_SLCSR_IND_ON: 2108 printf("on\n"); 2109 break; 2110 case PCIE_SLCSR_IND_BLINK: 2111 printf("blink\n"); 2112 break; 2113 case PCIE_SLCSR_IND_OFF: 2114 printf("off\n"); 2115 break; 2116 } 2117 } 2118 if (slcap & PCIE_SLCAP_PIP) { 2119 printf(" Power Indicator Control: "); 2120 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 2121 case 0x0: 2122 printf("reserved\n"); 2123 break; 2124 case PCIE_SLCSR_IND_ON: 2125 printf("on\n"); 2126 break; 2127 case PCIE_SLCSR_IND_BLINK: 2128 printf("blink\n"); 2129 break; 2130 case PCIE_SLCSR_IND_OFF: 2131 printf("off\n"); 2132 break; 2133 } 2134 } 2135 printf(" Power Controller Control: Power %s\n", 2136 reg & PCIE_SLCSR_PCC ? "off" : "on"); 2137 onoff("Electromechanical Interlock Control", 2138 reg, PCIE_SLCSR_EIC); 2139 onoff("Data Link Layer State Changed Enable", reg, 2140 PCIE_SLCSR_DLLSCE); 2141 onoff("Auto Slot Power Limit Disable", reg, 2142 PCIE_SLCSR_AUTOSPLDIS); 2143 2144 /* Slot Status Register */ 2145 printf(" Slot Status Register: 0x%04x\n", reg >> 16); 2146 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 2147 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 2148 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 2149 onoff("Presence Detect Changed", reg, PCIE_SLCSR_PDC); 2150 onoff("Command Completed", reg, PCIE_SLCSR_CC); 2151 onoff("MRL Open", reg, PCIE_SLCSR_MS); 2152 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 2153 onoff("Electromechanical Interlock engaged", reg, 2154 PCIE_SLCSR_EIS); 2155 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 2156 } 2157 2158 if (PCIE_HAS_ROOTREGS(pcie_devtype)) { 2159 /* Root Control Register */ 2160 reg = regs[o2i(capoff + PCIE_RCR)]; 2161 printf(" Root Control Register: 0x%04x\n", reg & 0xffff); 2162 onoff("SERR on Correctable Error Enable", reg, 2163 PCIE_RCR_SERR_CER); 2164 onoff("SERR on Non-Fatal Error Enable", reg, 2165 PCIE_RCR_SERR_NFER); 2166 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 2167 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 2168 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 2169 2170 /* Root Capability Register */ 2171 printf(" Root Capability Register: 0x%04x\n", 2172 reg >> 16); 2173 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 2174 2175 /* Root Status Register */ 2176 reg = regs[o2i(capoff + PCIE_RSR)]; 2177 printf(" Root Status Register: 0x%08x\n", reg); 2178 printf(" PME Requester ID: 0x%04x\n", 2179 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 2180 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 2181 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 2182 } 2183 2184 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2185 if (pciever < 2) 2186 return; 2187 2188 /* Device Capabilities 2 */ 2189 reg = regs[o2i(capoff + PCIE_DCAP2)]; 2190 printf(" Device Capabilities 2: 0x%08x\n", reg); 2191 printf(" Completion Timeout Ranges Supported: "); 2192 val = reg & PCIE_DCAP2_COMPT_RANGE; 2193 switch (val) { 2194 case 0: 2195 printf("not supported\n"); 2196 break; 2197 default: 2198 for (i = 0; i <= 3; i++) { 2199 if (((val >> i) & 0x01) != 0) 2200 printf("%c", 'A' + i); 2201 } 2202 printf("\n"); 2203 } 2204 onoff("Completion Timeout Disable Supported", reg, 2205 PCIE_DCAP2_COMPT_DIS); 2206 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 2207 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 2208 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 2209 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 2210 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 2211 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 2212 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 2213 printf(" TPH Completer Supported: "); 2214 switch (__SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) { 2215 case 0: 2216 printf("Not supported\n"); 2217 break; 2218 case 1: 2219 printf("TPH\n"); 2220 break; 2221 case 3: 2222 printf("TPH and Extended TPH\n"); 2223 break; 2224 default: 2225 printf("(reserved value)\n"); 2226 break; 2227 } 2228 printf(" LN System CLS: "); 2229 switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 2230 case 0x0: 2231 printf("Not supported or not in effect\n"); 2232 break; 2233 case 0x1: 2234 printf("64byte cachelines in effect\n"); 2235 break; 2236 case 0x2: 2237 printf("128byte cachelines in effect\n"); 2238 break; 2239 case 0x3: 2240 printf("Reserved\n"); 2241 break; 2242 } 2243 onoff("10-bit Tag Completer Supported", reg, PCIE_DCAP2_TBT_COMP); 2244 onoff("10-bit Tag Requester Supported", reg, PCIE_DCAP2_TBT_REQ); 2245 printf(" OBFF Supported: "); 2246 switch (__SHIFTOUT(reg, PCIE_DCAP2_OBFF)) { 2247 case 0x0: 2248 printf("Not supported\n"); 2249 break; 2250 case 0x1: 2251 printf("Message only\n"); 2252 break; 2253 case 0x2: 2254 printf("WAKE# only\n"); 2255 break; 2256 case 0x3: 2257 printf("Both\n"); 2258 break; 2259 } 2260 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 2261 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 2262 val = __SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP); 2263 printf(" Max End-End TLP Prefixes: %u\n", (val == 0) ? 4 : val); 2264 printf(" Emergency Power Reduction Supported: "); 2265 switch (__SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) { 2266 case 0x0: 2267 printf("Not supported\n"); 2268 break; 2269 case 0x1: 2270 printf("Device Specific mechanism\n"); 2271 break; 2272 case 0x2: 2273 printf("Form Factor spec or Device Specific mechanism\n"); 2274 break; 2275 case 0x3: 2276 printf("Reserved\n"); 2277 break; 2278 } 2279 onoff("Emergency Power Reduction Initialization Required", reg, 2280 PCIE_DCAP2_EMGPWRRED_INI); 2281 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 2282 2283 /* Device Control 2 */ 2284 reg = regs[o2i(capoff + PCIE_DCSR2)]; 2285 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 2286 printf(" Completion Timeout Value: "); 2287 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 2288 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 2289 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 2290 onoff("AtomicOp Requester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 2291 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 2292 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 2293 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 2294 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 2295 onoff("Emergency Power Reduction Request", reg, 2296 PCIE_DCSR2_EMGPWRRED_REQ); 2297 onoff("10-bit Tag Requester Enabled", reg, PCIE_DCSR2_TBT_REQ); 2298 printf(" OBFF: "); 2299 switch (__SHIFTOUT(reg, PCIE_DCSR2_OBFF_EN)) { 2300 case 0x0: 2301 printf("Disabled\n"); 2302 break; 2303 case 0x1: 2304 printf("Enabled with Message Signaling Variation A\n"); 2305 break; 2306 case 0x2: 2307 printf("Enabled with Message Signaling Variation B\n"); 2308 break; 2309 case 0x3: 2310 printf("Enabled using WAKE# signaling\n"); 2311 break; 2312 } 2313 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 2314 2315 if (PCIE_HAS_LINKREGS(pcie_devtype)) { 2316 bool drs_supported = false; 2317 2318 /* Link Capability 2 */ 2319 reg = regs[o2i(capoff + PCIE_LCAP2)]; 2320 /* If the vector is 0, LCAP2 is not implemented */ 2321 if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) { 2322 printf(" Link Capabilities 2: 0x%08x\n", reg); 2323 printf(" Supported Link Speeds Vector:"); 2324 pci_print_pcie_linkspeedvector( 2325 __SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 2326 printf("\n"); 2327 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 2328 printf(" " 2329 "Lower SKP OS Generation Supported Speed Vector:"); 2330 pci_print_pcie_linkspeedvector( 2331 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 2332 printf("\n"); 2333 printf(" " 2334 "Lower SKP OS Reception Supported Speed Vector:"); 2335 pci_print_pcie_linkspeedvector( 2336 __SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 2337 printf("\n"); 2338 onoff("Retimer Presence Detect Supported", reg, 2339 PCIE_LCAP2_RETIMERPD); 2340 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 2341 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 2342 } 2343 2344 /* Link Control 2 */ 2345 reg = regs[o2i(capoff + PCIE_LCSR2)]; 2346 /* If the vector is 0, LCAP2 is not implemented */ 2347 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 2348 printf(" Target Link Speed: "); 2349 pci_print_pcie_linkspeed(PCIE_LCSR2, 2350 __SHIFTOUT(reg, PCIE_LCSR2_TGT_LSPEED)); 2351 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 2352 onoff("HW Autonomous Speed Disabled", reg, 2353 PCIE_LCSR2_HW_AS_DIS); 2354 printf(" Selectable De-emphasis: "); 2355 pci_print_pcie_link_deemphasis( 2356 __SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP)); 2357 printf("\n"); 2358 printf(" Transmit Margin: %u\n", 2359 (unsigned int)__SHIFTOUT(reg, PCIE_LCSR2_TX_MARGIN)); 2360 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 2361 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 2362 printf(" Compliance Preset/De-emphasis: "); 2363 pci_print_pcie_link_preset_preshoot_deemphasis( 2364 __SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP)); 2365 printf("\n"); 2366 2367 /* Link Status 2 */ 2368 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 2369 printf(" Current De-emphasis Level: "); 2370 pci_print_pcie_link_deemphasis( 2371 __SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL)); 2372 printf("\n"); 2373 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 2374 onoff("Equalization Phase 1 Successful", reg, 2375 PCIE_LCSR2_EQP1_SUC); 2376 onoff("Equalization Phase 2 Successful", reg, 2377 PCIE_LCSR2_EQP2_SUC); 2378 onoff("Equalization Phase 3 Successful", reg, 2379 PCIE_LCSR2_EQP3_SUC); 2380 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 2381 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 2382 if (drs_supported) { 2383 printf(" Downstream Component Presence: "); 2384 switch (__SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 2385 case PCIE_DSCOMPN_DOWN_NOTDETERM: 2386 printf("Link Down - Presence Not" 2387 " Determined\n"); 2388 break; 2389 case PCIE_DSCOMPN_DOWN_NOTPRES: 2390 printf("Link Down - Component Not Present\n"); 2391 break; 2392 case PCIE_DSCOMPN_DOWN_PRES: 2393 printf("Link Down - Component Present\n"); 2394 break; 2395 case PCIE_DSCOMPN_UP_PRES: 2396 printf("Link Up - Component Present\n"); 2397 break; 2398 case PCIE_DSCOMPN_UP_PRES_DRS: 2399 printf("Link Up - Component Present and DRS" 2400 " received\n"); 2401 break; 2402 default: 2403 printf("reserved\n"); 2404 break; 2405 } 2406 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 2407 } 2408 } 2409 2410 /* Slot Capability 2 */ 2411 /* Slot Control 2 */ 2412 /* Slot Status 2 */ 2413 } 2414 2415 static void 2416 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 2417 { 2418 pcireg_t reg; 2419 2420 printf("\n MSI-X Capability Register\n"); 2421 2422 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2423 printf(" Message Control register: 0x%04x\n", 2424 (reg >> 16) & 0xff); 2425 printf(" Table Size: %d\n", PCI_MSIX_CTL_TBLSIZE(reg)); 2426 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 2427 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 2428 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 2429 printf(" Table offset register: 0x%08x\n", reg); 2430 printf(" Table offset: 0x%08x\n", 2431 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 2432 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 2433 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 2434 printf(" Pending bit array register: 0x%08x\n", reg); 2435 printf(" Pending bit array offset: 0x%08x\n", 2436 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2437 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2438 } 2439 2440 static void 2441 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2442 { 2443 pcireg_t reg; 2444 2445 printf("\n Serial ATA Capability Register\n"); 2446 2447 reg = regs[o2i(capoff + PCI_SATA_REV)]; 2448 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2449 printf(" Revision: %u.%u\n", 2450 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2451 (unsigned int)__SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2452 2453 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2454 2455 printf(" BAR Register: 0x%08x\n", reg); 2456 printf(" Register location: "); 2457 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2458 printf("in config space\n"); 2459 else { 2460 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2461 printf(" BAR offset: 0x%08x\n", 2462 (pcireg_t)__SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2463 } 2464 } 2465 2466 static void 2467 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2468 { 2469 pcireg_t reg; 2470 2471 printf("\n Advanced Features Capability Register\n"); 2472 2473 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2474 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2475 printf(" AF Structure Length: 0x%02x\n", 2476 (pcireg_t)__SHIFTOUT(reg, PCI_AF_LENGTH)); 2477 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2478 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2479 reg = regs[o2i(capoff + PCI_AFCSR)]; 2480 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2481 /* 2482 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2483 * and it's always 0 on read 2484 */ 2485 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2486 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2487 } 2488 2489 static void 2490 pci_conf_print_ea_cap_prop(unsigned int prop) 2491 { 2492 2493 switch (prop) { 2494 case PCI_EA_PROP_MEM_NONPREF: 2495 printf("Memory Space, Non-Prefetchable\n"); 2496 break; 2497 case PCI_EA_PROP_MEM_PREF: 2498 printf("Memory Space, Prefetchable\n"); 2499 break; 2500 case PCI_EA_PROP_IO: 2501 printf("I/O Space\n"); 2502 break; 2503 case PCI_EA_PROP_VF_MEM_NONPREF: 2504 printf("Resorce for VF use, Memory Space, Non-Prefetchable\n"); 2505 break; 2506 case PCI_EA_PROP_VF_MEM_PREF: 2507 printf("Resorce for VF use, Memory Space, Prefetch\n"); 2508 break; 2509 case PCI_EA_PROP_BB_MEM_NONPREF: 2510 printf("Behind the Bridge, Memory Space, Non-Pref\n"); 2511 break; 2512 case PCI_EA_PROP_BB_MEM_PREF: 2513 printf("Behind the Bridge, Memory Space. Prefetchable\n"); 2514 break; 2515 case PCI_EA_PROP_BB_IO: 2516 printf("Behind Bridge, I/O Space\n"); 2517 break; 2518 case PCI_EA_PROP_MEM_UNAVAIL: 2519 printf("Memory Space Unavailable\n"); 2520 break; 2521 case PCI_EA_PROP_IO_UNAVAIL: 2522 printf("IO Space Unavailable\n"); 2523 break; 2524 case PCI_EA_PROP_UNAVAIL: 2525 printf("Entry Unavailable for use\n"); 2526 break; 2527 default: 2528 printf("Reserved\n"); 2529 break; 2530 } 2531 } 2532 2533 static void 2534 pci_conf_print_ea_cap(const pcireg_t *regs, int capoff) 2535 { 2536 pcireg_t reg, reg2; 2537 unsigned int entries, entoff, i; 2538 2539 printf("\n Enhanced Allocation Capability Register\n"); 2540 2541 reg = regs[o2i(capoff + PCI_EA_CAP1)]; 2542 printf(" EA Num Entries register: 0x%04x\n", reg >> 16); 2543 entries = __SHIFTOUT(reg, PCI_EA_CAP1_NUMENTRIES); 2544 printf(" EA Num Entries: %u\n", entries); 2545 2546 /* Type 1 only */ 2547 if (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) == PCI_HDRTYPE_PPB) { 2548 reg = regs[o2i(capoff + PCI_EA_CAP2)]; 2549 printf(" EA Capability Second register: 0x%08x\n", reg); 2550 printf(" Fixed Secondary Bus Number: %hhu\n", 2551 (unsigned char)__SHIFTOUT(reg, PCI_EA_CAP2_SECONDARY)); 2552 printf(" Fixed Subordinate Bus Number: %hhu\n", 2553 (unsigned char)__SHIFTOUT(reg, PCI_EA_CAP2_SUBORDINATE)); 2554 entoff = capoff + 8; 2555 } else 2556 entoff = capoff + 4; 2557 2558 for (i = 0; i < entries; i++) { 2559 uint64_t base, offset; 2560 bool baseis64, offsetis64; 2561 unsigned int bei, entry_size; 2562 2563 printf(" Entry %u:\n", i); 2564 /* The first DW */ 2565 reg = regs[o2i(entoff)]; 2566 printf(" The first register: 0x%08x\n", reg); 2567 entry_size = __SHIFTOUT(reg, PCI_EA_ES); 2568 printf(" Entry size: %u\n", entry_size); 2569 printf(" BAR Equivalent Indicator: "); 2570 bei = __SHIFTOUT(reg, PCI_EA_BEI); 2571 switch (bei) { 2572 case PCI_EA_BEI_BAR0: 2573 case PCI_EA_BEI_BAR1: 2574 case PCI_EA_BEI_BAR2: 2575 case PCI_EA_BEI_BAR3: 2576 case PCI_EA_BEI_BAR4: 2577 case PCI_EA_BEI_BAR5: 2578 printf("BAR %u\n", bei - PCI_EA_BEI_BAR0); 2579 break; 2580 case PCI_EA_BEI_BEHIND: 2581 printf("Behind the function\n"); 2582 break; 2583 case PCI_EA_BEI_NOTIND: 2584 printf("Not Indicated\n"); 2585 break; 2586 case PCI_EA_BEI_EXPROM: 2587 printf("Expansion ROM\n"); 2588 break; 2589 case PCI_EA_BEI_VFBAR0: 2590 case PCI_EA_BEI_VFBAR1: 2591 case PCI_EA_BEI_VFBAR2: 2592 case PCI_EA_BEI_VFBAR3: 2593 case PCI_EA_BEI_VFBAR4: 2594 case PCI_EA_BEI_VFBAR5: 2595 printf("VF BAR %u\n", bei - PCI_EA_BEI_VFBAR0); 2596 break; 2597 case PCI_EA_BEI_RESERVED: 2598 default: 2599 printf("Reserved\n"); 2600 break; 2601 } 2602 2603 printf(" Primary Properties: "); 2604 pci_conf_print_ea_cap_prop(__SHIFTOUT(reg, PCI_EA_PP)); 2605 printf(" Secondary Properties: "); 2606 pci_conf_print_ea_cap_prop(__SHIFTOUT(reg, PCI_EA_SP)); 2607 onoff("Writable", reg, PCI_EA_W); 2608 onoff("Enable for this entry", reg, PCI_EA_E); 2609 2610 if (entry_size == 0) { 2611 entoff += 4; 2612 continue; 2613 } 2614 2615 /* Base addr */ 2616 reg = regs[o2i(entoff + 4)]; 2617 base = reg & PCI_EA_LOWMASK; 2618 baseis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT; 2619 printf(" Base Address Register Low: 0x%08x\n", reg); 2620 if (baseis64) { 2621 /* 64bit */ 2622 reg2 = regs[o2i(entoff + 12)]; 2623 printf(" Base Address Register high: 0x%08x\n", 2624 reg2); 2625 base |= (uint64_t)reg2 << 32; 2626 } 2627 2628 /* Offset addr */ 2629 reg = regs[o2i(entoff + 8)]; 2630 offset = reg & PCI_EA_LOWMASK; 2631 offsetis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT; 2632 printf(" Max Offset Register Low: 0x%08x\n", reg); 2633 if (offsetis64) { 2634 /* 64bit */ 2635 reg2 = regs[o2i(entoff + (baseis64 ? 16 : 12))]; 2636 printf(" Max Offset Register high: 0x%08x\n", 2637 reg2); 2638 offset |= (uint64_t)reg2 << 32; 2639 } 2640 2641 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 2642 "\n", base, base + offset); 2643 2644 entoff += 4 + (4 * entry_size); 2645 } 2646 } 2647 2648 /* XXX pci_conf_print_fpb_cap */ 2649 2650 static struct { 2651 pcireg_t cap; 2652 const char *name; 2653 void (*printfunc)(const pcireg_t *, int); 2654 } pci_captab[] = { 2655 { PCI_CAP_RESERVED0, "reserved", NULL }, 2656 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2657 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2658 { PCI_CAP_VPD, "VPD", NULL }, 2659 { PCI_CAP_SLOTID, "SlotID", NULL }, 2660 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2661 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2662 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2663 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2664 { PCI_CAP_VENDSPEC, "Vendor-specific", 2665 pci_conf_print_vendspec_cap }, 2666 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2667 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2668 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2669 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2670 pci_conf_print_subsystem_cap }, 2671 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2672 { PCI_CAP_SECURE, "Secure Device", pci_conf_print_secure_cap }, 2673 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2674 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2675 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2676 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2677 { PCI_CAP_EA, "Enhanced Allocation", pci_conf_print_ea_cap }, 2678 { PCI_CAP_FPB, "Flattening Portal Bridge", NULL } 2679 }; 2680 2681 static int 2682 pci_conf_find_cap(const pcireg_t *regs, unsigned int capid, int *offsetp) 2683 { 2684 pcireg_t rval; 2685 unsigned int capptr; 2686 int off; 2687 2688 if (!(regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)) 2689 return 0; 2690 2691 /* Determine the Capability List Pointer register to start with. */ 2692 switch (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)])) { 2693 case 0: /* standard device header */ 2694 case 1: /* PCI-PCI bridge header */ 2695 capptr = PCI_CAPLISTPTR_REG; 2696 break; 2697 case 2: /* PCI-CardBus Bridge header */ 2698 capptr = PCI_CARDBUS_CAPLISTPTR_REG; 2699 break; 2700 default: 2701 return 0; 2702 } 2703 2704 for (off = PCI_CAPLIST_PTR(regs[o2i(capptr)]); 2705 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2706 rval = regs[o2i(off)]; 2707 if (capid == PCI_CAPLIST_CAP(rval)) { 2708 if (offsetp != NULL) 2709 *offsetp = off; 2710 return 1; 2711 } 2712 } 2713 return 0; 2714 } 2715 2716 static void 2717 pci_conf_print_caplist( 2718 #ifdef _KERNEL 2719 pci_chipset_tag_t pc, pcitag_t tag, 2720 #endif 2721 const pcireg_t *regs, int capoff) 2722 { 2723 int off; 2724 pcireg_t foundcap; 2725 pcireg_t rval; 2726 bool foundtable[__arraycount(pci_captab)]; 2727 unsigned int i; 2728 2729 /* Clear table */ 2730 for (i = 0; i < __arraycount(pci_captab); i++) 2731 foundtable[i] = false; 2732 2733 /* Print capability register's offset and the type first */ 2734 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2735 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2736 rval = regs[o2i(off)]; 2737 printf(" Capability register at 0x%02x\n", off); 2738 2739 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2740 foundcap = PCI_CAPLIST_CAP(rval); 2741 if (foundcap < __arraycount(pci_captab)) { 2742 printf("%s)\n", pci_captab[foundcap].name); 2743 /* Mark as found */ 2744 foundtable[foundcap] = true; 2745 } else 2746 printf("unknown)\n"); 2747 } 2748 2749 /* 2750 * And then, print the detail of each capability registers 2751 * in capability value's order. 2752 */ 2753 for (i = 0; i < __arraycount(pci_captab); i++) { 2754 if (foundtable[i] == false) 2755 continue; 2756 2757 /* 2758 * The type was found. Search capability list again and 2759 * print all capabilities that the capability type is 2760 * the same. This is required because some capabilities 2761 * appear multiple times (e.g. HyperTransport capability). 2762 */ 2763 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2764 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2765 rval = regs[o2i(off)]; 2766 if ((PCI_CAPLIST_CAP(rval) == i) 2767 && (pci_captab[i].printfunc != NULL)) 2768 pci_captab[i].printfunc(regs, off); 2769 } 2770 } 2771 } 2772 2773 /* Extended Capability */ 2774 2775 static void 2776 pci_conf_print_aer_cap_uc(pcireg_t reg) 2777 { 2778 2779 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2780 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2781 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2782 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2783 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2784 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2785 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2786 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2787 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2788 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2789 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2790 onoff("Unsupported Request Error", reg, 2791 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2792 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2793 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2794 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2795 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2796 onoff("TLP Prefix Blocked Error", reg, 2797 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2798 onoff("Poisoned TLP Egress Blocked", reg, 2799 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2800 } 2801 2802 static void 2803 pci_conf_print_aer_cap_cor(pcireg_t reg) 2804 { 2805 2806 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2807 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2808 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2809 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2810 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2811 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2812 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2813 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2814 } 2815 2816 static void 2817 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2818 { 2819 2820 printf(" First Error Pointer: 0x%04x\n", 2821 (pcireg_t)__SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2822 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2823 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2824 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2825 onoff("ECRC Check Enable", reg, PCI_AER_ECRC_CHECK_ENABLE); 2826 onoff("Multiple Header Recording Capable", reg, 2827 PCI_AER_MULT_HDR_CAPABLE); 2828 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2829 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2830 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2831 2832 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2833 if (!tlp_prefix_log) 2834 return; 2835 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2836 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2837 } 2838 2839 static void 2840 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2841 { 2842 2843 onoff("Correctable Error Reporting Enable", reg, 2844 PCI_AER_ROOTERR_COR_ENABLE); 2845 onoff("Non-Fatal Error Reporting Enable", reg, 2846 PCI_AER_ROOTERR_NF_ENABLE); 2847 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2848 } 2849 2850 static void 2851 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2852 { 2853 2854 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2855 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2856 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2857 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2858 PCI_AER_ROOTERR_MULTI_UC_ERR); 2859 onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL); 2860 onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR); 2861 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2862 printf(" Advanced Error Interrupt Message Number: 0x%02x\n", 2863 (unsigned int)__SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2864 } 2865 2866 static void 2867 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2868 { 2869 2870 printf(" Correctable Source ID: 0x%04x\n", 2871 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2872 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2873 (pcireg_t)__SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2874 } 2875 2876 static void 2877 pci_conf_print_aer_cap(const pcireg_t *regs, int extcapoff) 2878 { 2879 pcireg_t reg; 2880 int pcie_capoff; 2881 int pcie_devtype = -1; 2882 bool tlp_prefix_log = false; 2883 2884 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2885 reg = regs[o2i(pcie_capoff)]; 2886 pcie_devtype = PCIE_XCAP_TYPE(reg); 2887 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2888 if (__SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2889 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2890 /* End-End TLP Prefix Supported */ 2891 if (reg & PCIE_DCAP2_EETLP_PREF) { 2892 tlp_prefix_log = true; 2893 } 2894 } 2895 } 2896 2897 printf("\n Advanced Error Reporting Register\n"); 2898 2899 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2900 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2901 pci_conf_print_aer_cap_uc(reg); 2902 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2903 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2904 pci_conf_print_aer_cap_uc(reg); 2905 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2906 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2907 pci_conf_print_aer_cap_uc(reg); 2908 2909 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2910 printf(" Correctable Error Status register: 0x%08x\n", reg); 2911 pci_conf_print_aer_cap_cor(reg); 2912 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2913 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2914 pci_conf_print_aer_cap_cor(reg); 2915 2916 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2917 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2918 reg); 2919 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2920 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2921 printf(" Header Log register:\n"); 2922 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2923 extcapoff + PCI_AER_ROOTERR_CMD); 2924 2925 switch (pcie_devtype) { 2926 case PCIE_XCAP_TYPE_RP: /* Root Port of PCI Express Root Complex */ 2927 case PCIE_XCAP_TYPE_RC_EVNTC: /* Root Complex Event Collector */ 2928 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2929 printf(" Root Error Command register: 0x%08x\n", reg); 2930 pci_conf_print_aer_cap_rooterr_cmd(reg); 2931 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2932 printf(" Root Error Status register: 0x%08x\n", reg); 2933 pci_conf_print_aer_cap_rooterr_status(reg); 2934 2935 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2936 printf(" Error Source Identification register: 0x%08x\n", 2937 reg); 2938 pci_conf_print_aer_cap_errsrc_id(reg); 2939 break; 2940 } 2941 2942 if (tlp_prefix_log) { 2943 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2944 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2945 } 2946 } 2947 2948 /* 2949 * Helper function to print the arbitration phase register. 2950 * 2951 * phases: Number of phases in the arbitration tables. 2952 * arbsize: Number of bits in each phase. 2953 * indent: Add more two spaces if it's true. 2954 */ 2955 static void 2956 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2957 const int phases, int arbsize, bool indent) 2958 { 2959 pcireg_t reg; 2960 int num_per_reg = 32 / arbsize; 2961 int i, j; 2962 2963 printf("%s %s Arbitration Table:\n", indent ? " " : "", name); 2964 for (i = 0; i < phases; i += num_per_reg) { 2965 reg = regs[o2i(off + (sizeof(uint32_t) * (i / num_per_reg)))]; 2966 for (j = 0; j < num_per_reg; j++) { 2967 printf("%s Phase[%d]: 0x%x\n", indent ? " " : "", 2968 i + j, 2969 (uint32_t)(reg & __BITS(arbsize - 1, 0))); 2970 reg >>= arbsize; 2971 } 2972 } 2973 } 2974 2975 /* For VC, bit 4-7 are reserved. For Port, bit 6-7 are reserved */ 2976 static const int arb_phases[8] = {0, 32, 64, 128, 128, 256, 0, 0 }; 2977 2978 static void 2979 pci_conf_print_vc_cap(const pcireg_t *regs, int extcapoff) 2980 { 2981 pcireg_t reg, n; 2982 int arbtab, parbsize; 2983 pcireg_t arbsel; 2984 int i, count; 2985 2986 printf("\n Virtual Channel Register\n"); 2987 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2988 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2989 count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2990 printf(" Extended VC Count: %d\n", count); 2991 n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2992 printf(" Low Priority Extended VC Count: %u\n", n); 2993 n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2994 printf(" Reference Clock: %s\n", 2995 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 2996 parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2997 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2998 2999 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 3000 printf(" Port VC Capability register 2: 0x%08x\n", reg); 3001 onoff("Hardware fixed arbitration scheme", 3002 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 3003 onoff("WRR arbitration with 32 phases", 3004 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 3005 onoff("WRR arbitration with 64 phases", 3006 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 3007 onoff("WRR arbitration with 128 phases", 3008 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 3009 arbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 3010 printf(" VC Arbitration Table Offset: 0x%x\n", arbtab); 3011 3012 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 3013 printf(" Port VC Control register: 0x%04x\n", reg); 3014 arbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 3015 printf(" VC Arbitration Select: 0x%x\n", arbsel); 3016 3017 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 3018 printf(" Port VC Status register: 0x%04x\n", reg); 3019 onoff("VC Arbitration Table Status", 3020 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 3021 3022 if ((arbtab != 0) && (arbsel != 0)) 3023 pci_conf_print_vc_cap_arbtab(regs, extcapoff + (arbtab * 16), 3024 "VC", arb_phases[arbsel], 4, false); 3025 3026 for (i = 0; i < count + 1; i++) { 3027 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 3028 printf(" VC number %d\n", i); 3029 printf(" VC Resource Capability Register: 0x%08x\n", reg); 3030 onoff(" Non-configurable Hardware fixed arbitration scheme", 3031 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 3032 onoff(" WRR arbitration with 32 phases", 3033 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 3034 onoff(" WRR arbitration with 64 phases", 3035 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 3036 onoff(" WRR arbitration with 128 phases", 3037 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 3038 onoff(" Time-based WRR arbitration with 128 phases", 3039 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 3040 onoff(" WRR arbitration with 256 phases", 3041 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 3042 onoff(" Advanced Packet Switching", 3043 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 3044 onoff(" Reject Snoop Transaction", 3045 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 3046 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 3047 printf(" Maximum Time Slots: %d\n", n); 3048 arbtab = __SHIFTOUT(reg, 3049 PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET); 3050 printf(" Port Arbitration Table offset: 0x%02x\n", 3051 arbtab); 3052 3053 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 3054 printf(" VC Resource Control Register: 0x%08x\n", reg); 3055 printf(" TC/VC Map: 0x%02x\n", 3056 (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 3057 /* 3058 * The load Port Arbitration Table bit is used to update 3059 * the Port Arbitration logic and it's always 0 on read, so 3060 * we don't print it. 3061 */ 3062 arbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 3063 printf(" Port Arbitration Select: 0x%x\n", arbsel); 3064 n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 3065 printf(" VC ID: %d\n", n); 3066 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 3067 3068 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 3069 printf(" VC Resource Status Register: 0x%08x\n", reg); 3070 onoff(" Port Arbitration Table Status", 3071 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 3072 onoff(" VC Negotiation Pending", 3073 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 3074 3075 if ((arbtab != 0) && (arbsel != 0)) 3076 pci_conf_print_vc_cap_arbtab(regs, 3077 extcapoff + (arbtab * 16), 3078 "Port", arb_phases[arbsel], parbsize, true); 3079 } 3080 } 3081 3082 /* 3083 * Print Power limit. This encoding is the same among the following registers: 3084 * - The Captured Slot Power Limit in the PCIe Device Capability Register. 3085 * - The Slot Power Limit in the PCIe Slot Capability Register. 3086 * - The Base Power in the Data register of Power Budgeting capability. 3087 */ 3088 static void 3089 pci_conf_print_pcie_power(uint8_t base, unsigned int scale) 3090 { 3091 unsigned int sdiv = 1; 3092 3093 if ((scale == 0) && (base > 0xef)) { 3094 const char *s; 3095 3096 switch (base) { 3097 case 0xf0: 3098 s = "239W < x <= 250W"; 3099 break; 3100 case 0xf1: 3101 s = "250W < x <= 275W"; 3102 break; 3103 case 0xf2: 3104 s = "275W < x <= 300W"; 3105 break; 3106 default: 3107 s = "reserved for greater than 300W"; 3108 break; 3109 } 3110 printf("%s\n", s); 3111 return; 3112 } 3113 3114 for (unsigned int i = scale; i > 0; i--) 3115 sdiv *= 10; 3116 3117 printf("%u", base / sdiv); 3118 3119 if (scale != 0) { 3120 printf(".%u", base % sdiv); 3121 } 3122 printf ("W\n"); 3123 return; 3124 } 3125 3126 static const char * 3127 pci_conf_print_pwrbdgt_type(uint8_t reg) 3128 { 3129 3130 switch (reg) { 3131 case 0x00: 3132 return "PME Aux"; 3133 case 0x01: 3134 return "Auxilary"; 3135 case 0x02: 3136 return "Idle"; 3137 case 0x03: 3138 return "Sustained"; 3139 case 0x04: 3140 return "Sustained (Emergency Power Reduction)"; 3141 case 0x05: 3142 return "Maximum (Emergency Power Reduction)"; 3143 case 0x07: 3144 return "Maximum"; 3145 default: 3146 return "Unknown"; 3147 } 3148 } 3149 3150 static const char * 3151 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 3152 { 3153 3154 switch (reg) { 3155 case 0x00: 3156 return "Power(12V)"; 3157 case 0x01: 3158 return "Power(3.3V)"; 3159 case 0x02: 3160 return "Power(1.5V or 1.8V)"; 3161 case 0x07: 3162 return "Thermal"; 3163 default: 3164 return "Unknown"; 3165 } 3166 } 3167 3168 static void 3169 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int extcapoff) 3170 { 3171 pcireg_t reg; 3172 3173 printf("\n Power Budgeting\n"); 3174 3175 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 3176 printf(" Data Select register: 0x%08x\n", reg); 3177 3178 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 3179 printf(" Data register: 0x%08x\n", reg); 3180 printf(" Base Power: "); 3181 pci_conf_print_pcie_power( 3182 __SHIFTOUT(reg, PCI_PWRBDGT_DATA_BASEPWR), 3183 __SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE)); 3184 printf(" PM Sub State: 0x%hhx\n", 3185 (uint8_t)__SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 3186 printf(" PM State: D%u\n", 3187 (unsigned int)__SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 3188 printf(" Type: %s\n", 3189 pci_conf_print_pwrbdgt_type( 3190 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 3191 printf(" Power Rail: %s\n", 3192 pci_conf_print_pwrbdgt_pwrrail( 3193 (uint8_t)(__SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 3194 3195 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 3196 printf(" Power Budget Capability register: 0x%08x\n", reg); 3197 onoff("System Allocated", 3198 reg, PCI_PWRBDGT_CAP_SYSALLOC); 3199 } 3200 3201 static const char * 3202 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 3203 { 3204 3205 switch (type) { 3206 case 0x00: 3207 return "Configuration Space Element"; 3208 case 0x01: 3209 return "System Egress Port or internal sink (memory)"; 3210 case 0x02: 3211 return "Internal Root Complex Link"; 3212 default: 3213 return "Unknown"; 3214 } 3215 } 3216 3217 static void 3218 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int extcapoff) 3219 { 3220 pcireg_t reg; 3221 unsigned char nent, linktype; 3222 int i; 3223 3224 printf("\n Root Complex Link Declaration\n"); 3225 3226 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 3227 printf(" Element Self Description Register: 0x%08x\n", reg); 3228 printf(" Element Type: %s\n", 3229 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 3230 nent = __SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 3231 printf(" Number of Link Entries: %hhu\n", nent); 3232 printf(" Component ID: %hhu\n", 3233 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 3234 printf(" Port Number: %hhu\n", 3235 (uint8_t)__SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 3236 for (i = 0; i < nent; i++) { 3237 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 3238 printf(" Link Entry %d:\n", i + 1); 3239 printf(" Link Description Register: 0x%08x\n", reg); 3240 onoff(" Link Valid", reg, PCI_RCLINK_DCL_LINKDESC_LVALID); 3241 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 3242 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 3243 "Configuration Space", "Memory-Mapped Space"); 3244 onoff(" Associated RCRB Header", reg, 3245 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 3246 printf(" Target Component ID: %hhu\n", 3247 (unsigned char)__SHIFTOUT(reg, 3248 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 3249 printf(" Target Port Number: %hhu\n", 3250 (unsigned char)__SHIFTOUT(reg, 3251 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 3252 3253 if (linktype == 0) { 3254 /* Memory-Mapped Space */ 3255 reg = regs[o2i(extcapoff 3256 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 3257 printf(" Link Address Low Register: 0x%08x\n", 3258 reg); 3259 reg = regs[o2i(extcapoff 3260 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 3261 printf(" Link Address High Register: 0x%08x\n", 3262 reg); 3263 } else { 3264 unsigned int nb; 3265 pcireg_t lo, hi; 3266 3267 /* Configuration Space */ 3268 lo = regs[o2i(extcapoff 3269 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 3270 printf(" Configuration Space Low Register: " 3271 "0x%08x\n", lo); 3272 hi = regs[o2i(extcapoff 3273 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 3274 printf(" Configuration Space High Register: " 3275 "0x%08x\n", hi); 3276 nb = __SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 3277 printf(" N: %u\n", nb); 3278 printf(" Func: %hhu\n", 3279 (unsigned char)__SHIFTOUT(lo, 3280 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 3281 printf(" Dev: %hhu\n", 3282 (unsigned char)__SHIFTOUT(lo, 3283 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 3284 printf(" Bus: %hhu\n", 3285 (unsigned char)__SHIFTOUT(lo, 3286 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 3287 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 3288 printf(" Configuration Space Base Address: " 3289 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 3290 } 3291 } 3292 } 3293 3294 /* XXX pci_conf_print_rclink_ctl_cap */ 3295 3296 static void 3297 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int extcapoff) 3298 { 3299 pcireg_t reg; 3300 3301 printf("\n Root Complex Event Collector Association\n"); 3302 3303 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 3304 printf(" Association Bitmap for Root Complex Integrated Devices:" 3305 " 0x%08x\n", reg); 3306 3307 if (PCI_EXTCAPLIST_VERSION(regs[o2i(extcapoff)]) >= 2) { 3308 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBUSNUM)]; 3309 printf(" RCEC Associated Bus Numbers register: 0x%08x\n", 3310 reg); 3311 printf(" RCEC Next Bus: %u\n", 3312 (unsigned int)__SHIFTOUT(reg, 3313 PCI_RCEC_ASSOCBUSNUM_RCECNEXT)); 3314 printf(" RCEC Last Bus: %u\n", 3315 (unsigned int)__SHIFTOUT(reg, 3316 PCI_RCEC_ASSOCBUSNUM_RCECLAST)); 3317 } 3318 } 3319 3320 /* XXX pci_conf_print_mfvc_cap */ 3321 /* XXX pci_conf_print_vc2_cap */ 3322 /* XXX pci_conf_print_rcrb_cap */ 3323 /* XXX pci_conf_print_vendor_cap */ 3324 /* XXX pci_conf_print_cac_cap */ 3325 3326 static void 3327 pci_conf_print_acs_cap(const pcireg_t *regs, int extcapoff) 3328 { 3329 pcireg_t reg, cap, ctl; 3330 unsigned int size, i; 3331 3332 printf("\n Access Control Services\n"); 3333 3334 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 3335 cap = reg & 0xffff; 3336 ctl = reg >> 16; 3337 printf(" ACS Capability register: 0x%08x\n", cap); 3338 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 3339 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 3340 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 3341 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 3342 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 3343 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 3344 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 3345 size = __SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 3346 if (size == 0) 3347 size = 256; 3348 printf(" Egress Control Vector Size: %u\n", size); 3349 printf(" ACS Control register: 0x%08x\n", ctl); 3350 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 3351 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 3352 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 3353 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 3354 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 3355 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 3356 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 3357 3358 /* 3359 * If the P2P Egress Control Capability bit is 0, ignore the Egress 3360 * Control vector. 3361 */ 3362 if ((cap & PCI_ACS_CAP_E) == 0) 3363 return; 3364 for (i = 0; i < size; i += 32) 3365 printf(" Egress Control Vector [%u..%u]: 0x%08x\n", i + 31, 3366 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 3367 } 3368 3369 static void 3370 pci_conf_print_ari_cap(const pcireg_t *regs, int extcapoff) 3371 { 3372 pcireg_t reg, cap, ctl; 3373 3374 printf("\n Alternative Routing-ID Interpretation Register\n"); 3375 3376 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3377 cap = reg & 0xffff; 3378 ctl = reg >> 16; 3379 printf(" Capability register: 0x%08x\n", cap); 3380 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 3381 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 3382 printf(" Next Function Number: %u\n", 3383 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 3384 printf(" Control register: 0x%08x\n", ctl); 3385 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 3386 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 3387 printf(" Function Group: %u\n", 3388 (unsigned int)__SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 3389 } 3390 3391 static void 3392 pci_conf_print_ats_cap(const pcireg_t *regs, int extcapoff) 3393 { 3394 pcireg_t reg, cap, ctl; 3395 unsigned int num; 3396 3397 printf("\n Address Translation Services\n"); 3398 3399 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3400 cap = reg & 0xffff; 3401 ctl = reg >> 16; 3402 printf(" Capability register: 0x%04x\n", cap); 3403 num = __SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 3404 if (num == 0) 3405 num = 32; 3406 printf(" Invalidate Queue Depth: %u\n", num); 3407 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 3408 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 3409 onoff("Relaxed Ordering", reg, PCI_ATS_CAP_RELAXORD); 3410 3411 printf(" Control register: 0x%04x\n", ctl); 3412 printf(" Smallest Translation Unit: %u\n", 3413 (unsigned int)__SHIFTOUT(reg, PCI_ATS_CTL_STU)); 3414 onoff("Enable", reg, PCI_ATS_CTL_EN); 3415 } 3416 3417 static void 3418 pci_conf_print_sernum_cap(const pcireg_t *regs, int extcapoff) 3419 { 3420 pcireg_t lo, hi; 3421 3422 printf("\n Device Serial Number Register\n"); 3423 3424 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 3425 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 3426 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 3427 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 3428 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 3429 } 3430 3431 static void 3432 pci_conf_print_sriov_cap(const pcireg_t *regs, int extcapoff) 3433 { 3434 char buf[sizeof("99999 MB")]; 3435 pcireg_t reg; 3436 pcireg_t total_vfs; 3437 int i; 3438 bool first; 3439 3440 printf("\n Single Root IO Virtualization Register\n"); 3441 3442 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 3443 printf(" Capabilities register: 0x%08x\n", reg); 3444 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 3445 onoff("ARI Capable Hierarchy Preserved", reg, 3446 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 3447 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 3448 printf(" VF Migration Interrupt Message Number: 0x%03x\n", 3449 (pcireg_t)__SHIFTOUT(reg, 3450 PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 3451 } 3452 3453 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 3454 printf(" Control register: 0x%04x\n", reg); 3455 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 3456 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 3457 onoff("VF Migration Interrupt Enable", reg, 3458 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 3459 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 3460 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 3461 3462 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 3463 printf(" Status register: 0x%04x\n", reg); 3464 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 3465 3466 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 3467 printf(" InitialVFs register: 0x%04x\n", reg); 3468 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 3469 printf(" TotalVFs register: 0x%04x\n", reg); 3470 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 3471 printf(" NumVFs register: 0x%04x\n", reg); 3472 3473 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 3474 printf(" Function Dependency Link register: 0x%04x\n", reg); 3475 3476 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 3477 printf(" First VF Offset register: 0x%04x\n", reg); 3478 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 3479 printf(" VF Stride register: 0x%04x\n", reg); 3480 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16; 3481 printf(" Device ID: 0x%04x\n", reg); 3482 3483 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 3484 printf(" Supported Page Sizes register: 0x%08x\n", reg); 3485 printf(" Supported Page Size:"); 3486 for (i = 0, first = true; i < 32; i++) { 3487 if (reg & __BIT(i)) { 3488 #ifdef _KERNEL 3489 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 3490 #else 3491 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 3492 HN_AUTOSCALE, 0); 3493 #endif 3494 printf("%s %s", first ? "" : ",", buf); 3495 first = false; 3496 } 3497 } 3498 printf("\n"); 3499 3500 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 3501 printf(" System Page Sizes register: 0x%08x\n", reg); 3502 printf(" Page Size: "); 3503 if (reg != 0) { 3504 int bitpos = ffs(reg) -1; 3505 3506 /* Assume only one bit is set. */ 3507 #ifdef _KERNEL 3508 format_bytes(buf, sizeof(buf), 1LL << (bitpos + 12)); 3509 #else 3510 humanize_number(buf, sizeof(buf), 1LL << (bitpos + 12), 3511 "B", HN_AUTOSCALE, 0); 3512 #endif 3513 printf("%s", buf); 3514 } else { 3515 printf("unknown"); 3516 } 3517 printf("\n"); 3518 3519 for (i = 0; i < 6; i++) { 3520 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 3521 printf(" VF BAR%d register: 0x%08x\n", i, reg); 3522 } 3523 3524 if (total_vfs > 0) { 3525 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 3526 printf(" VF Migration State Array Offset register: 0x%08x\n", 3527 reg); 3528 printf(" VF Migration State Offset: 0x%08x\n", 3529 (pcireg_t)__SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 3530 i = __SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 3531 printf(" VF Migration State BIR: "); 3532 if (i >= 0 && i <= 5) { 3533 printf("BAR%d", i); 3534 } else { 3535 printf("unknown BAR (%d)", i); 3536 } 3537 printf("\n"); 3538 } 3539 } 3540 3541 /* XXX pci_conf_print_mriov_cap */ 3542 3543 static void 3544 pci_conf_print_multicast_cap(const pcireg_t *regs, int extcapoff) 3545 { 3546 pcireg_t reg, cap, ctl; 3547 pcireg_t regl, regh; 3548 uint64_t addr; 3549 int n; 3550 3551 printf("\n Multicast\n"); 3552 3553 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 3554 cap = reg & 0xffff; 3555 ctl = reg >> 16; 3556 printf(" Capability Register: 0x%04x\n", cap); 3557 printf(" Max Group: %u\n", 3558 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 3559 3560 /* Endpoint Only */ 3561 n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 3562 if (n > 0) 3563 printf(" Window Size Requested: %d\n", 1 << (n - 1)); 3564 3565 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 3566 3567 printf(" Control Register: 0x%04x\n", ctl); 3568 printf(" Num Group: %u\n", 3569 (unsigned int)__SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 3570 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 3571 3572 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 3573 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 3574 printf(" Base Address Register 0: 0x%08x\n", regl); 3575 printf(" Base Address Register 1: 0x%08x\n", regh); 3576 printf(" Index Position: %u\n", 3577 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 3578 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 3579 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 3580 3581 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 3582 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 3583 printf(" Receive Register 0: 0x%08x\n", regl); 3584 printf(" Receive Register 1: 0x%08x\n", regh); 3585 3586 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 3587 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 3588 printf(" Block All Register 0: 0x%08x\n", regl); 3589 printf(" Block All Register 1: 0x%08x\n", regh); 3590 3591 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 3592 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 3593 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 3594 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 3595 3596 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 3597 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 3598 printf(" Overlay BAR 0: 0x%08x\n", regl); 3599 printf(" Overlay BAR 1: 0x%08x\n", regh); 3600 3601 n = regl & PCI_MCAST_OVERLAYL_SIZE; 3602 printf(" Overlay Size: "); 3603 if (n >= 6) 3604 printf("%d\n", n); 3605 else 3606 printf("off\n"); 3607 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 3608 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 3609 } 3610 3611 static void 3612 pci_conf_print_page_req_cap(const pcireg_t *regs, int extcapoff) 3613 { 3614 pcireg_t reg, ctl, sta; 3615 3616 printf("\n Page Request\n"); 3617 3618 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 3619 ctl = reg & 0xffff; 3620 sta = reg >> 16; 3621 printf(" Control Register: 0x%04x\n", ctl); 3622 onoff("Enable", reg, PCI_PAGE_REQ_CTL_E); 3623 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 3624 3625 printf(" Status Register: 0x%04x\n", sta); 3626 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 3627 onoff("Unexpected Page Request Group Index", reg, 3628 PCI_PAGE_REQ_STA_UPRGI); 3629 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 3630 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 3631 3632 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 3633 printf(" Outstanding Page Request Capacity: %u\n", reg); 3634 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 3635 printf(" Outstanding Page Request Allocation: %u\n", reg); 3636 } 3637 3638 /* XXX pci_conf_print_amd_cap */ 3639 3640 #define MEM_PBUFSIZE sizeof("999GB") 3641 3642 static void 3643 pci_conf_print_resizbar_cap(const pcireg_t *regs, int extcapoff) 3644 { 3645 pcireg_t cap, ctl; 3646 unsigned int bars, i, n; 3647 char pbuf[MEM_PBUFSIZE]; 3648 3649 printf("\n Resizable BAR\n"); 3650 3651 /* Get Number of Resizable BARs */ 3652 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))]; 3653 bars = __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR); 3654 printf(" Number of Resizable BARs: "); 3655 if (bars <= 6) 3656 printf("%u\n", bars); 3657 else { 3658 printf("incorrect (%u)\n", bars); 3659 return; 3660 } 3661 3662 for (n = 0; n < 6; n++) { 3663 cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))]; 3664 printf(" Capability register(%u): 0x%08x\n", n, cap); 3665 if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0) 3666 continue; /* Not Used */ 3667 printf(" Acceptable BAR sizes:"); 3668 for (i = 4; i <= 23; i++) { 3669 if ((cap & (1 << i)) != 0) { 3670 humanize_number(pbuf, MEM_PBUFSIZE, 3671 (int64_t)1024 * 1024 << (i - 4), "B", 3672 #ifdef _KERNEL 3673 1); 3674 #else 3675 HN_AUTOSCALE, HN_NOSPACE); 3676 #endif 3677 printf(" %s", pbuf); 3678 } 3679 } 3680 printf("\n"); 3681 3682 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))]; 3683 printf(" Control register(%u): 0x%08x\n", n, ctl); 3684 printf(" BAR Index: %u\n", 3685 (unsigned int)__SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX)); 3686 humanize_number(pbuf, MEM_PBUFSIZE, 3687 (int64_t)1024 * 1024 3688 << __SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ), 3689 "B", 3690 #ifdef _KERNEL 3691 1); 3692 #else 3693 HN_AUTOSCALE, HN_NOSPACE); 3694 #endif 3695 printf(" BAR Size: %s\n", pbuf); 3696 } 3697 } 3698 3699 static void 3700 pci_conf_print_dpa_cap(const pcireg_t *regs, int extcapoff) 3701 { 3702 pcireg_t reg; 3703 unsigned int substmax, i; 3704 3705 printf("\n Dynamic Power Allocation\n"); 3706 3707 reg = regs[o2i(extcapoff + PCI_DPA_CAP)]; 3708 printf(" Capability register: 0x%08x\n", reg); 3709 substmax = __SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX); 3710 printf(" Substate Max: %u\n", substmax); 3711 printf(" Transition Latency Unit: "); 3712 switch (__SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) { 3713 case 0: 3714 printf("1ms\n"); 3715 break; 3716 case 1: 3717 printf("10ms\n"); 3718 break; 3719 case 2: 3720 printf("100ms\n"); 3721 break; 3722 default: 3723 printf("reserved\n"); 3724 break; 3725 } 3726 printf(" Power Allocation Scale: "); 3727 switch (__SHIFTOUT(reg, PCI_DPA_CAP_PAS)) { 3728 case 0: 3729 printf("10.0x\n"); 3730 break; 3731 case 1: 3732 printf("1.0x\n"); 3733 break; 3734 case 2: 3735 printf("0.1x\n"); 3736 break; 3737 case 3: 3738 printf("0.01x\n"); 3739 break; 3740 } 3741 printf(" Transition Latency Value 0: %u\n", 3742 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY0)); 3743 printf(" Transition Latency Value 1: %u\n", 3744 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); 3745 3746 reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; 3747 printf(" Latency Indicator register: 0x%08x\n", reg); 3748 3749 reg = regs[o2i(extcapoff + PCI_DPA_CS)]; 3750 printf(" Status register: 0x%04x\n", reg & 0xffff); 3751 printf(" Substate Status: 0x%02x\n", 3752 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT)); 3753 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN); 3754 printf(" Control register: 0x%04x\n", reg >> 16); 3755 printf(" Substate Control: 0x%02x\n", 3756 (unsigned int)__SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL)); 3757 3758 for (i = 0; i <= substmax; i++) 3759 printf(" Substate Power Allocation register %d: 0x%02x\n", 3760 i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff)); 3761 } 3762 3763 static const char * 3764 pci_conf_print_tph_req_cap_sttabloc(uint8_t val) 3765 { 3766 3767 switch (val) { 3768 case PCI_TPH_REQ_STTBLLOC_NONE: 3769 return "Not Present"; 3770 case PCI_TPH_REQ_STTBLLOC_TPHREQ: 3771 return "in the TPH Requester Capability Structure"; 3772 case PCI_TPH_REQ_STTBLLOC_MSIX: 3773 return "in the MSI-X Table"; 3774 default: 3775 return "Unknown"; 3776 } 3777 } 3778 3779 static void 3780 pci_conf_print_tph_req_cap(const pcireg_t *regs, int extcapoff) 3781 { 3782 pcireg_t reg; 3783 int size = 0, i, j; 3784 uint8_t sttbloc; 3785 3786 printf("\n TPH Requester Extended Capability\n"); 3787 3788 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3789 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3790 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3791 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3792 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3793 onoff("Extend TPH Requester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3794 sttbloc = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC); 3795 printf(" ST Table Location: %s\n", 3796 pci_conf_print_tph_req_cap_sttabloc(sttbloc)); 3797 if (sttbloc == PCI_TPH_REQ_STTBLLOC_TPHREQ) { 3798 size = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3799 printf(" ST Table Size: %d\n", size); 3800 } 3801 3802 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CTL)]; 3803 printf(" TPH Requester Control register: 0x%08x\n", reg); 3804 printf(" ST Mode Select: "); 3805 switch (__SHIFTOUT(reg, PCI_TPH_REQ_CTL_STSEL)) { 3806 case PCI_TPH_REQ_CTL_STSEL_NO: 3807 printf("No ST Mode\n"); 3808 break; 3809 case PCI_TPH_REQ_CTL_STSEL_IV: 3810 printf("Interrupt Vector Mode\n"); 3811 break; 3812 case PCI_TPH_REQ_CTL_STSEL_DS: 3813 printf("Device Specific Mode\n"); 3814 break; 3815 default: 3816 printf("(reserved value)\n"); 3817 break; 3818 } 3819 printf(" TPH Requester Enable: "); 3820 switch (__SHIFTOUT(reg, PCI_TPH_REQ_CTL_TPHREQEN)) { 3821 case PCI_TPH_REQ_CTL_TPHREQEN_NO: /* 0x0 */ 3822 printf("Not permitted\n"); 3823 break; 3824 case PCI_TPH_REQ_CTL_TPHREQEN_TPH: 3825 printf("TPH and not Extended TPH\n"); 3826 break; 3827 case PCI_TPH_REQ_CTL_TPHREQEN_ETPH: 3828 printf("TPH and Extended TPH"); 3829 break; 3830 default: 3831 printf("(reserved value)\n"); 3832 break; 3833 } 3834 3835 if (sttbloc != PCI_TPH_REQ_STTBLLOC_TPHREQ) 3836 return; 3837 3838 for (i = 0; i < size ; i += 2) { 3839 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3840 for (j = 0; j < 2 ; j++) { 3841 uint32_t entry = reg; 3842 3843 if (j != 0) 3844 entry >>= 16; 3845 entry &= 0xffff; 3846 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3847 i + j, entry); 3848 } 3849 } 3850 } 3851 3852 static void 3853 pci_conf_print_ltr_cap(const pcireg_t *regs, int extcapoff) 3854 { 3855 pcireg_t reg; 3856 3857 printf("\n Latency Tolerance Reporting\n"); 3858 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)]; 3859 printf(" Max Snoop Latency Register: 0x%04x\n", reg & 0xffff); 3860 printf(" Max Snoop Latency: %juns\n", 3861 (uintmax_t)(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL) 3862 * PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE)))); 3863 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg >> 16); 3864 printf(" Max No-Snoop Latency: %juns\n", 3865 (uintmax_t)(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL) 3866 * PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE)))); 3867 } 3868 3869 static void 3870 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int extcapoff) 3871 { 3872 int pcie_capoff; 3873 pcireg_t reg; 3874 int i, maxlinkwidth; 3875 3876 printf("\n Secondary PCI Express Register\n"); 3877 3878 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3879 printf(" Link Control 3 register: 0x%08x\n", reg); 3880 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3881 onoff("Link Equalization Request Interrupt Enable", 3882 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3883 printf(" Enable Lower SKP OS Generation Vector:"); 3884 pci_print_pcie_linkspeedvector( 3885 __SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3886 printf("\n"); 3887 3888 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3889 printf(" Lane Error Status register: 0x%08x\n", reg); 3890 3891 /* Get Max Link Width */ 3892 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 3893 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3894 maxlinkwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3895 } else { 3896 printf("error: failed to get PCIe capability\n"); 3897 return; 3898 } 3899 for (i = 0; i < maxlinkwidth; i++) { 3900 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3901 if (i % 2 != 0) 3902 reg >>= 16; 3903 else 3904 reg &= 0xffff; 3905 printf(" Equalization Control Register (Link %d): 0x%04x\n", 3906 i, reg); 3907 printf(" Downstream Port Transmit Preset: 0x%x\n", 3908 (pcireg_t)__SHIFTOUT(reg, 3909 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3910 printf(" Downstream Port Receive Hint: 0x%x\n", 3911 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3912 printf(" Upstream Port Transmit Preset: 0x%x\n", 3913 (pcireg_t)__SHIFTOUT(reg, 3914 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3915 printf(" Upstream Port Receive Hint: 0x%x\n", 3916 (pcireg_t)__SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3917 } 3918 } 3919 3920 /* XXX pci_conf_print_pmux_cap */ 3921 3922 static void 3923 pci_conf_print_pasid_cap(const pcireg_t *regs, int extcapoff) 3924 { 3925 pcireg_t reg, cap, ctl; 3926 unsigned int num; 3927 3928 printf("\n Process Address Space ID\n"); 3929 3930 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3931 cap = reg & 0xffff; 3932 ctl = reg >> 16; 3933 printf(" PASID Capability Register: 0x%04x\n", cap); 3934 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3935 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3936 num = (1 << __SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3937 printf(" Max PASID Width: %u\n", num); 3938 3939 printf(" PASID Control Register: 0x%04x\n", ctl); 3940 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3941 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3942 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3943 } 3944 3945 static void 3946 pci_conf_print_lnr_cap(const pcireg_t *regs, int extcapoff) 3947 { 3948 pcireg_t reg, cap, ctl; 3949 unsigned int num; 3950 3951 printf("\n LN Requester\n"); 3952 3953 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3954 cap = reg & 0xffff; 3955 ctl = reg >> 16; 3956 printf(" LNR Capability register: 0x%04x\n", cap); 3957 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 3958 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 3959 num = 1 << __SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 3960 printf(" LNR Registration MAX: %u\n", num); 3961 3962 printf(" LNR Control register: 0x%04x\n", ctl); 3963 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 3964 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 3965 num = 1 << __SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 3966 printf(" LNR Registration Limit: %u\n", num); 3967 } 3968 3969 static void 3970 pci_conf_print_dpc_pio(pcireg_t r) 3971 { 3972 onoff("Cfg Request received UR Completion", r,PCI_DPC_RPPIO_CFGUR_CPL); 3973 onoff("Cfg Request received CA Completion", r,PCI_DPC_RPPIO_CFGCA_CPL); 3974 onoff("Cfg Request Completion Timeout", r, PCI_DPC_RPPIO_CFG_CTO); 3975 onoff("I/O Request received UR Completion", r, PCI_DPC_RPPIO_IOUR_CPL); 3976 onoff("I/O Request received CA Completion", r, PCI_DPC_RPPIO_IOCA_CPL); 3977 onoff("I/O Request Completion Timeout", r, PCI_DPC_RPPIO_IO_CTO); 3978 onoff("Mem Request received UR Completion", r,PCI_DPC_RPPIO_MEMUR_CPL); 3979 onoff("Mem Request received CA Completion", r,PCI_DPC_RPPIO_MEMCA_CPL); 3980 onoff("Mem Request Completion Timeout", r, PCI_DPC_RPPIO_MEM_CTO); 3981 } 3982 3983 static void 3984 pci_conf_print_dpc_cap(const pcireg_t *regs, int extcapoff) 3985 { 3986 pcireg_t reg, cap, ctl, stat, errsrc; 3987 const char *trigstr; 3988 bool rpext; 3989 3990 printf("\n Downstream Port Containment\n"); 3991 3992 reg = regs[o2i(extcapoff + PCI_DPC_CCR)]; 3993 cap = reg & 0xffff; 3994 ctl = reg >> 16; 3995 rpext = (reg & PCI_DPCCAP_RPEXT) ? true : false; 3996 printf(" DPC Capability register: 0x%04x\n", cap); 3997 printf(" DPC Interrupt Message Number: %02x\n", 3998 (unsigned int)(cap & PCI_DPCCAP_IMSGN)); 3999 onoff("RP Extensions for DPC", reg, PCI_DPCCAP_RPEXT); 4000 onoff("Poisoned TLP Egress Blocking Supported", reg, 4001 PCI_DPCCAP_POISONTLPEB); 4002 onoff("DPC Software Triggering Supported", reg, PCI_DPCCAP_SWTRIG); 4003 printf(" RP PIO Log Size: %u\n", 4004 (unsigned int)__SHIFTOUT(reg, PCI_DPCCAP_RPPIOLOGSZ)); 4005 onoff("DL_Active ERR_COR Signaling Supported", reg, 4006 PCI_DPCCAP_DLACTECORS); 4007 printf(" DPC Control register: 0x%04x\n", ctl); 4008 switch (__SHIFTOUT(reg, PCI_DPCCTL_TIRGEN)) { 4009 case 0: 4010 trigstr = "disabled"; 4011 break; 4012 case 1: 4013 trigstr = "enabled(ERR_FATAL)"; 4014 break; 4015 case 2: 4016 trigstr = "enabled(ERR_NONFATAL or ERR_FATAL)"; 4017 break; 4018 default: 4019 trigstr = "(reserverd)"; 4020 break; 4021 } 4022 printf(" DPC Trigger Enable: %s\n", trigstr); 4023 printf(" DPC Completion Control: %s Completion Status\n", 4024 (reg & PCI_DPCCTL_COMPCTL) 4025 ? "Unsupported Request(UR)" : "Completer Abort(CA)"); 4026 onoff("DPC Interrupt Enable", reg, PCI_DPCCTL_IE); 4027 onoff("DPC ERR_COR Enable", reg, PCI_DPCCTL_ERRCOREN); 4028 onoff("Poisoned TLP Egress Blocking Enable", reg, 4029 PCI_DPCCTL_POISONTLPEB); 4030 onoff("DPC Software Trigger", reg, PCI_DPCCTL_SWTRIG); 4031 onoff("DL_Active ERR_COR Enable", reg, PCI_DPCCTL_DLACTECOR); 4032 4033 reg = regs[o2i(extcapoff + PCI_DPC_STATESID)]; 4034 stat = reg & 0xffff; 4035 errsrc = reg >> 16; 4036 printf(" DPC Status register: 0x%04x\n", stat); 4037 onoff("DPC Trigger Status", reg, PCI_DPCSTAT_TSTAT); 4038 switch (__SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 4039 case 0: 4040 trigstr = "an unmasked uncorrectable error"; 4041 break; 4042 case 1: 4043 trigstr = "receiving an ERR_NONFATAL"; 4044 break; 4045 case 2: 4046 trigstr = "receiving an ERR_FATAL"; 4047 break; 4048 case 3: 4049 trigstr = "DPC Trigger Reason Extension field"; 4050 break; 4051 } 4052 printf(" DPC Trigger Reason: Due to %s\n", trigstr); 4053 onoff("DPC Interrupt Status", reg, PCI_DPCSTAT_ISTAT); 4054 if (rpext) 4055 onoff("DPC RP Busy", reg, PCI_DPCSTAT_RPBUSY); 4056 switch (__SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 4057 case 0: 4058 trigstr = "Due to RP PIO error"; 4059 break; 4060 case 1: 4061 trigstr = "Due to the DPC Software trigger bit"; 4062 break; 4063 default: 4064 trigstr = "(reserved)"; 4065 break; 4066 } 4067 printf(" DPC Trigger Reason Extension: %s\n", trigstr); 4068 if (rpext) 4069 printf(" RP PIO First Error Pointer: %02x\n", 4070 (unsigned int)__SHIFTOUT(reg, PCI_DPCSTAT_RPPIOFEP)); 4071 printf(" DPC Error Source ID register: 0x%04x\n", errsrc); 4072 4073 if (!rpext) 4074 return; 4075 /* 4076 * All of the following registers are implemented by a device which has 4077 * RP Extensions for DPC 4078 */ 4079 4080 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_STAT)]; 4081 printf(" RP PIO Status Register: 0x%08x\n", reg); 4082 pci_conf_print_dpc_pio(reg); 4083 4084 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_MASK)]; 4085 printf(" RP PIO Mask Register: 0x%08x\n", reg); 4086 pci_conf_print_dpc_pio(reg); 4087 4088 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SEVE)]; 4089 printf(" RP PIO Severity Register: 0x%08x\n", reg); 4090 pci_conf_print_dpc_pio(reg); 4091 4092 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SYSERR)]; 4093 printf(" RP PIO SysError Register: 0x%08x\n", reg); 4094 pci_conf_print_dpc_pio(reg); 4095 4096 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_EXCPT)]; 4097 printf(" RP PIO Exception Register: 0x%08x\n", reg); 4098 pci_conf_print_dpc_pio(reg); 4099 4100 printf(" RP PIO Header Log Register: start from 0x%03x\n", 4101 extcapoff + PCI_DPC_RPPIO_HLOG); 4102 printf(" RP PIO ImpSpec Log Register: start from 0x%03x\n", 4103 extcapoff + PCI_DPC_RPPIO_IMPSLOG); 4104 printf(" RP PIO TLP Prefix Log Register: start from 0x%03x\n", 4105 extcapoff + PCI_DPC_RPPIO_TLPPLOG); 4106 } 4107 4108 4109 static int 4110 pci_conf_l1pm_cap_tposcale(unsigned char scale) 4111 { 4112 4113 /* Return scale in us */ 4114 switch (scale) { 4115 case 0x0: 4116 return 2; 4117 case 0x1: 4118 return 10; 4119 case 0x2: 4120 return 100; 4121 default: 4122 return -1; 4123 } 4124 } 4125 4126 static void 4127 pci_conf_print_l1pm_cap(const pcireg_t *regs, int extcapoff) 4128 { 4129 pcireg_t reg; 4130 int scale, val; 4131 int pcie_capoff; 4132 4133 printf("\n L1 PM Substates\n"); 4134 4135 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 4136 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 4137 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 4138 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 4139 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 4140 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 4141 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 4142 /* The Link Activation Supported bit is only for Downstream Port */ 4143 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 4144 uint32_t t = regs[o2i(pcie_capoff)]; 4145 4146 if ((t == PCIE_XCAP_TYPE_RP) || (t == PCIE_XCAP_TYPE_DOWN)) 4147 onoff("Link Activation Supported", reg, 4148 PCI_L1PM_CAP_LA); 4149 } 4150 printf(" Port Common Mode Restore Time: %uus\n", 4151 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 4152 scale = pci_conf_l1pm_cap_tposcale( 4153 __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 4154 val = __SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 4155 printf(" Port T_POWER_ON: "); 4156 if (scale == -1) 4157 printf("unknown\n"); 4158 else 4159 printf("%dus\n", val * scale); 4160 4161 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 4162 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 4163 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 4164 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 4165 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 4166 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 4167 onoff("Link Activation Interrupt Enable", reg, PCI_L1PM_CTL1_LAIE); 4168 onoff("Link Activation Control", reg, PCI_L1PM_CTL1_LA); 4169 printf(" Common Mode Restore Time: %uus\n", 4170 (unsigned int)__SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 4171 scale = PCI_LTR_SCALETONS(__SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 4172 val = __SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 4173 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 4174 4175 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 4176 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 4177 scale = pci_conf_l1pm_cap_tposcale( 4178 __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 4179 val = __SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 4180 printf(" T_POWER_ON: "); 4181 if (scale == -1) 4182 printf("unknown\n"); 4183 else 4184 printf("%dus\n", val * scale); 4185 4186 if (PCI_EXTCAPLIST_VERSION(regs[o2i(extcapoff)]) >= 2) { 4187 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 4188 printf(" L1 PM Substates Status register: 0x%08x\n", reg); 4189 onoff("Link Activation Status", reg, PCI_L1PM_STAT_LA); 4190 } 4191 } 4192 4193 static void 4194 pci_conf_print_ptm_cap(const pcireg_t *regs, int extcapoff) 4195 { 4196 pcireg_t reg; 4197 uint32_t val; 4198 4199 printf("\n Precision Time Measurement\n"); 4200 4201 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 4202 printf(" PTM Capability register: 0x%08x\n", reg); 4203 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 4204 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 4205 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 4206 printf(" Local Clock Granularity: "); 4207 val = __SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 4208 switch (val) { 4209 case 0: 4210 printf("Not implemented\n"); 4211 break; 4212 case 0xffff: 4213 printf("> 254ns\n"); 4214 break; 4215 default: 4216 printf("%uns\n", val); 4217 break; 4218 } 4219 4220 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 4221 printf(" PTM Control register: 0x%08x\n", reg); 4222 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 4223 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 4224 printf(" Effective Granularity: "); 4225 val = __SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 4226 switch (val) { 4227 case 0: 4228 printf("Unknown\n"); 4229 break; 4230 case 0xffff: 4231 printf("> 254ns\n"); 4232 break; 4233 default: 4234 printf("%uns\n", val); 4235 break; 4236 } 4237 } 4238 4239 /* XXX pci_conf_print_mpcie_cap */ 4240 /* XXX pci_conf_print_frsq_cap */ 4241 /* XXX pci_conf_print_rtr_cap */ 4242 /* XXX pci_conf_print_desigvndsp_cap */ 4243 /* XXX pci_conf_print_vf_resizbar_cap */ 4244 4245 static void 4246 pci_conf_print_dlf_cap(const pcireg_t *regs, int extcapoff) 4247 { 4248 pcireg_t reg; 4249 4250 printf("\n Data link Feature Register\n"); 4251 reg = regs[o2i(extcapoff + PCI_DLF_CAP)]; 4252 printf(" Capability register: 0x%08x\n", reg); 4253 onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL); 4254 onoff("DLF Exchange enable", reg, PCI_DLF_CAP_XCHG); 4255 4256 reg = regs[o2i(extcapoff + PCI_DLF_STAT)]; 4257 printf(" Status register: 0x%08x\n", reg); 4258 onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL); 4259 onoff("Remote DLF supported Valid", reg, PCI_DLF_STAT_RMTVALID); 4260 } 4261 4262 static void 4263 pci_conf_print_pl16g_cap(const pcireg_t *regs, int extcapoff) 4264 { 4265 pcireg_t reg, lwidth; 4266 int pcie_capoff; 4267 unsigned int i, j; 4268 4269 printf("\n Physical Layer 16.0 GT/s\n"); 4270 reg = regs[o2i(extcapoff + PCI_PL16G_CAP)]; 4271 printf(" Capability register: 0x%08x\n", reg); 4272 4273 reg = regs[o2i(extcapoff + PCI_PL16G_CTL)]; 4274 printf(" Control register: 0x%08x\n", reg); 4275 4276 reg = regs[o2i(extcapoff + PCI_PL16G_STAT)]; 4277 printf(" Status register: 0x%08x\n", reg); 4278 onoff("Equalization 16.0 GT/s Complete", reg, PCI_PL16G_STAT_EQ_COMPL); 4279 onoff("Equalization 16.0 GT/s Phase 1 Successful", reg, 4280 PCI_PL16G_STAT_EQ_P1S); 4281 onoff("Equalization 16.0 GT/s Phase 2 Successful", reg, 4282 PCI_PL16G_STAT_EQ_P2S); 4283 onoff("Equalization 16.0 GT/s Phase 3 Successful", reg, 4284 PCI_PL16G_STAT_EQ_P3S); 4285 4286 reg = regs[o2i(extcapoff + PCI_PL16G_LDPMS)]; 4287 printf(" Local Data Parity Mismatch Status register: 0x%08x\n", 4288 reg); 4289 4290 reg = regs[o2i(extcapoff + PCI_PL16G_FRDPMS)]; 4291 printf(" First Retimer Data Parity Mismatch Status register:" 4292 " 0x%08x\n", reg); 4293 4294 reg = regs[o2i(extcapoff + PCI_PL16G_SRDPMS)]; 4295 printf(" Second Retimer Data Parity Mismatch Status register:" 4296 " 0x%08x\n", reg); 4297 4298 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff) == 0) 4299 return; /* error */ 4300 4301 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 4302 lwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 4303 4304 for (i = 0; i < lwidth;) { 4305 reg = regs[o2i(extcapoff + PCI_PL16G_LEC + i)]; 4306 4307 for (j = 0; j < 4; j++) { 4308 pcireg_t up, down; 4309 4310 down = reg & 0x0000000f; 4311 up = (reg >> 4) & 0x0000000f; 4312 printf(" Lane %d downstream: ", i); 4313 pci_print_pcie_link_preset_preshoot_deemphasis(down); 4314 printf("\n Lane %d upstream: ", i); 4315 pci_print_pcie_link_preset_preshoot_deemphasis(up); 4316 printf("\n"); 4317 4318 reg >>= 8; 4319 i++; 4320 if (i >= lwidth) 4321 break; 4322 } 4323 } 4324 } 4325 4326 static const char * const pcie_receive_number_dp[] = { 4327 [0] = ("Broadcast " 4328 "(Downstream Port Receiver and all Retimer Pseudo Port Receiver)"), 4329 [1] = "Rx(A) (Downstream Port Receiver)", 4330 [2] = "Rx(B) (Retimer X or Z Upstream Pseudo Port Receiver)", 4331 [3] = "Rx(C) (Retimer X or Z Downstream Pseudo Port Receiver)", 4332 [4] = "Rx(D) (Retimer Y Upstream Pseudo Port Receiver)", 4333 [5] = "Rx(E) (Retimer Y Downstream Pseudo Port Receiver)", 4334 [6] = "Reserved", 4335 [7] = "Reserved" 4336 }; 4337 4338 static const char * const pcie_receive_number_up[] = { 4339 "Broadcast (Upstream Port Receiver)", 4340 "Reserved", 4341 "Reserved", 4342 "Reserved", 4343 "Reserved", 4344 "Reserved", 4345 "Rx(F) (Upstream Port Receiver)", 4346 "Reserved" 4347 }; 4348 4349 /* 4350 * Print PCI_LMR_LANECSR. This function is used for both control and status 4351 * register. The reg argument in the lower 16bit has the control or status 4352 * register. The encoding is the same except the receive number, so use _LCTL_ 4353 * macro. 4354 */ 4355 static void 4356 pci_conf_print_lmr_lcsr(pcireg_t reg, bool up, bool dp) 4357 { 4358 int rnum; 4359 4360 printf(" Receive Number: "); 4361 rnum = __SHIFTOUT(reg, PCI_LMR_LCTL_RNUM); 4362 if (up) 4363 printf("%s\n", pcie_receive_number_up[rnum]); 4364 else if (dp) 4365 printf("%s\n", pcie_receive_number_dp[rnum]); 4366 else 4367 printf("%x\n", rnum); 4368 4369 printf(" Margin Type: %x\n", 4370 (uint32_t)__SHIFTOUT(reg, PCI_LMR_LCTL_MTYPE)); 4371 printf(" Usage Model: %s\n", 4372 (__SHIFTOUT(reg, PCI_LMR_LCTL_UMODEL) == 0) 4373 ? "Lane Margining at Receiver" : "Reserved Encoding"); 4374 printf(" Margin Payload: 0x%02x\n", 4375 (uint32_t)__SHIFTOUT(reg, PCI_LMR_LCTL_MPAYLOAD)); 4376 } 4377 4378 static void 4379 pci_conf_print_lmr_cap(const pcireg_t *regs, int extcapoff) 4380 { 4381 pcireg_t reg, lwidth; 4382 int pcie_capoff; 4383 int pcie_devtype; 4384 unsigned int i; 4385 bool up, dp; 4386 4387 printf("\n Lane Margining at the Receiver\n"); 4388 reg = regs[o2i(extcapoff + PCI_LMR_PCAPSTAT)]; 4389 printf(" Port Capability register: 0x%04x\n", reg & 0xffff); 4390 onoff("Margining uses Driver Software", reg, PCI_LMR_PCAP_MUDS); 4391 printf(" Port Status register: 0x%04x\n", (reg >> 16) & 0xffff); 4392 onoff("Margining Ready", reg, PCI_LMR_PSTAT_MR); 4393 onoff("Margining Software Ready", reg, PCI_LMR_PSTAT_MSR); 4394 4395 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff) == 0) 4396 return; /* error */ 4397 4398 up = dp = false; 4399 reg = regs[o2i(pcie_capoff)]; 4400 pcie_devtype = PCIE_XCAP_TYPE(reg); 4401 switch (pcie_devtype) { 4402 case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */ 4403 case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */ 4404 case PCIE_XCAP_TYPE_UP: /* 0x5 */ 4405 case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ 4406 up = true; 4407 break; 4408 case PCIE_XCAP_TYPE_RP: /* 0x4 */ 4409 case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ 4410 dp = true; 4411 break; 4412 default: 4413 printf("neither upstream nor downstream?(%x)\n", pcie_devtype); 4414 break; 4415 } 4416 4417 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 4418 lwidth = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 4419 4420 for (i = 0; i < lwidth; i++) { 4421 pcireg_t lctl, lstat; 4422 4423 reg = regs[o2i(extcapoff + PCI_LMR_LANECSR + (i * 4))]; 4424 4425 lctl = reg & 0xffff; 4426 printf(" Lane %d control: 0x%04x\n", i, lctl); 4427 pci_conf_print_lmr_lcsr(lctl, up, dp); 4428 4429 lstat = (reg >> 16) & 0xffff; 4430 printf(" Lane %d status: 0x%04x\n", i, lstat); 4431 pci_conf_print_lmr_lcsr(lstat, up, dp); 4432 } 4433 } 4434 4435 /* XXX pci_conf_print_hierarchyid_cap */ 4436 /* XXX pci_conf_print_npem_cap */ 4437 4438 #undef MS 4439 #undef SM 4440 #undef RW 4441 4442 static struct { 4443 pcireg_t cap; 4444 const char *name; 4445 void (*printfunc)(const pcireg_t *, int); 4446 } pci_extcaptab[] = { 4447 { 0, "reserved", 4448 NULL }, 4449 { PCI_EXTCAP_AER, "Advanced Error Reporting", 4450 pci_conf_print_aer_cap }, 4451 { PCI_EXTCAP_VC, "Virtual Channel", 4452 pci_conf_print_vc_cap }, 4453 { PCI_EXTCAP_SERNUM, "Device Serial Number", 4454 pci_conf_print_sernum_cap }, 4455 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 4456 pci_conf_print_pwrbdgt_cap }, 4457 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 4458 pci_conf_print_rclink_dcl_cap }, 4459 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 4460 NULL }, 4461 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 4462 pci_conf_print_rcec_assoc_cap }, 4463 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 4464 NULL }, 4465 { PCI_EXTCAP_VC2, "Virtual Channel", 4466 NULL }, 4467 { PCI_EXTCAP_RCRB, "RCRB Header", 4468 NULL }, 4469 { PCI_EXTCAP_VENDOR, "Vendor Unique", 4470 NULL }, 4471 { PCI_EXTCAP_CAC, "Configuration Access Correction", 4472 NULL }, 4473 { PCI_EXTCAP_ACS, "Access Control Services", 4474 pci_conf_print_acs_cap }, 4475 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 4476 pci_conf_print_ari_cap }, 4477 { PCI_EXTCAP_ATS, "Address Translation Services", 4478 pci_conf_print_ats_cap }, 4479 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 4480 pci_conf_print_sriov_cap }, 4481 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 4482 NULL }, 4483 { PCI_EXTCAP_MCAST, "Multicast", 4484 pci_conf_print_multicast_cap }, 4485 { PCI_EXTCAP_PAGE_REQ, "Page Request", 4486 pci_conf_print_page_req_cap }, 4487 { PCI_EXTCAP_AMD, "Reserved for AMD", 4488 NULL }, 4489 { PCI_EXTCAP_RESIZBAR, "Resizable BAR", 4490 pci_conf_print_resizbar_cap }, 4491 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 4492 pci_conf_print_dpa_cap }, 4493 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 4494 pci_conf_print_tph_req_cap }, 4495 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 4496 pci_conf_print_ltr_cap }, 4497 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 4498 pci_conf_print_sec_pcie_cap }, 4499 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 4500 NULL }, 4501 { PCI_EXTCAP_PASID, "Process Address Space ID", 4502 pci_conf_print_pasid_cap }, 4503 { PCI_EXTCAP_LNR, "LN Requester", 4504 pci_conf_print_lnr_cap }, 4505 { PCI_EXTCAP_DPC, "Downstream Port Containment", 4506 pci_conf_print_dpc_cap }, 4507 { PCI_EXTCAP_L1PM, "L1 PM Substates", 4508 pci_conf_print_l1pm_cap }, 4509 { PCI_EXTCAP_PTM, "Precision Time Measurement", 4510 pci_conf_print_ptm_cap }, 4511 { PCI_EXTCAP_MPCIE, "M-PCIe", 4512 NULL }, 4513 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 4514 NULL }, 4515 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 4516 NULL }, 4517 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 4518 NULL }, 4519 { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", 4520 NULL }, 4521 { PCI_EXTCAP_DLF, "Data link Feature", pci_conf_print_dlf_cap }, 4522 { PCI_EXTCAP_PL16G, "Physical Layer 16.0 GT/s", 4523 pci_conf_print_pl16g_cap }, 4524 { PCI_EXTCAP_LMR, "Lane Margining at the Receiver", 4525 pci_conf_print_lmr_cap }, 4526 { PCI_EXTCAP_HIERARCHYID, "Hierarchy ID", 4527 NULL }, 4528 { PCI_EXTCAP_NPEM, "Native PCIe Enclosure Management", 4529 NULL }, 4530 }; 4531 4532 static int 4533 pci_conf_find_extcap(const pcireg_t *regs, unsigned int capid, int *offsetp) 4534 { 4535 int off; 4536 pcireg_t rval; 4537 4538 for (off = PCI_EXTCAPLIST_BASE; 4539 off != 0; 4540 off = PCI_EXTCAPLIST_NEXT(rval)) { 4541 rval = regs[o2i(off)]; 4542 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 4543 if (offsetp != NULL) 4544 *offsetp = off; 4545 return 1; 4546 } 4547 } 4548 return 0; 4549 } 4550 4551 static void 4552 pci_conf_print_extcaplist( 4553 #ifdef _KERNEL 4554 pci_chipset_tag_t pc, pcitag_t tag, 4555 #endif 4556 const pcireg_t *regs) 4557 { 4558 int off; 4559 pcireg_t foundcap; 4560 pcireg_t rval; 4561 bool foundtable[__arraycount(pci_extcaptab)]; 4562 unsigned int i; 4563 4564 /* Check Extended capability structure */ 4565 off = PCI_EXTCAPLIST_BASE; 4566 rval = regs[o2i(off)]; 4567 if (rval == 0xffffffff || rval == 0) 4568 return; 4569 4570 /* Clear table */ 4571 for (i = 0; i < __arraycount(pci_extcaptab); i++) 4572 foundtable[i] = false; 4573 4574 /* Print extended capability register's offset and the type first */ 4575 for (;;) { 4576 printf(" Extended Capability Register at 0x%02x\n", off); 4577 4578 foundcap = PCI_EXTCAPLIST_CAP(rval); 4579 printf(" type: 0x%04x (", foundcap); 4580 if (foundcap < __arraycount(pci_extcaptab)) { 4581 printf("%s)\n", pci_extcaptab[foundcap].name); 4582 /* Mark as found */ 4583 foundtable[foundcap] = true; 4584 } else 4585 printf("unknown)\n"); 4586 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 4587 4588 off = PCI_EXTCAPLIST_NEXT(rval); 4589 if (off == 0) 4590 break; 4591 else if (off <= PCI_CONF_SIZE) { 4592 printf(" next pointer: 0x%03x (incorrect)\n", off); 4593 return; 4594 } 4595 rval = regs[o2i(off)]; 4596 } 4597 4598 /* 4599 * And then, print the detail of each capability registers 4600 * in capability value's order. 4601 */ 4602 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 4603 if (foundtable[i] == false) 4604 continue; 4605 4606 /* 4607 * The type was found. Search capability list again and 4608 * print all capabilities that the capability type is 4609 * the same. 4610 */ 4611 if (pci_conf_find_extcap(regs, i, &off) == 0) 4612 continue; 4613 rval = regs[o2i(off)]; 4614 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 4615 || (pci_extcaptab[i].printfunc == NULL)) 4616 continue; 4617 4618 pci_extcaptab[i].printfunc(regs, off); 4619 4620 } 4621 } 4622 4623 /* Print the Secondary Status Register. */ 4624 static void 4625 pci_conf_print_ssr(pcireg_t rval) 4626 { 4627 pcireg_t devsel; 4628 4629 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 4630 onoff("66 MHz capable", rval, __BIT(5)); 4631 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 4632 onoff("Fast back-to-back capable", rval, __BIT(7)); 4633 onoff("Data parity error detected", rval, __BIT(8)); 4634 4635 printf(" DEVSEL timing: "); 4636 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 4637 switch (devsel) { 4638 case 0: 4639 printf("fast"); 4640 break; 4641 case 1: 4642 printf("medium"); 4643 break; 4644 case 2: 4645 printf("slow"); 4646 break; 4647 default: 4648 printf("unknown/reserved"); /* XXX */ 4649 break; 4650 } 4651 printf(" (0x%x)\n", devsel); 4652 4653 onoff("Signalled target abort", rval, __BIT(11)); 4654 onoff("Received target abort", rval, __BIT(12)); 4655 onoff("Received master abort", rval, __BIT(13)); 4656 onoff("Received system error", rval, __BIT(14)); 4657 onoff("Detected parity error", rval, __BIT(15)); 4658 } 4659 4660 static void 4661 pci_conf_print_type0( 4662 #ifdef _KERNEL 4663 pci_chipset_tag_t pc, pcitag_t tag, 4664 #endif 4665 const pcireg_t *regs) 4666 { 4667 int off, width; 4668 pcireg_t rval; 4669 const char *str; 4670 4671 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 4672 #ifdef _KERNEL 4673 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4674 #else 4675 width = pci_conf_print_bar(regs, off, NULL); 4676 #endif 4677 } 4678 4679 printf(" Cardbus CIS Pointer: 0x%08x\n", 4680 regs[o2i(PCI_CARDBUS_CIS_REG)]); 4681 4682 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 4683 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4684 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4685 4686 rval = regs[o2i(PCI_MAPREG_ROM)]; 4687 printf(" Expansion ROM Base Address Register: 0x%08x\n", rval); 4688 printf(" base: 0x%08x\n", (uint32_t)PCI_MAPREG_ROM_ADDR(rval)); 4689 onoff("Expansion ROM Enable", rval, PCI_MAPREG_ROM_ENABLE); 4690 printf(" Validation Status: "); 4691 switch (__SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_STAT)) { 4692 case PCI_MAPREG_ROM_VSTAT_NOTSUPP: 4693 str = "Validation not supported"; 4694 break; 4695 case PCI_MAPREG_ROM_VSTAT_INPROG: 4696 str = "Validation in Progress"; 4697 break; 4698 case PCI_MAPREG_ROM_VSTAT_VPASS: 4699 str = "Validation Pass. " 4700 "Valid contents, trust test was not performed"; 4701 break; 4702 case PCI_MAPREG_ROM_VSTAT_VPASSTRUST: 4703 str = "Validation Pass. Valid and trusted contents"; 4704 break; 4705 case PCI_MAPREG_ROM_VSTAT_VFAIL: 4706 str = "Validation Fail. Invalid contents"; 4707 break; 4708 case PCI_MAPREG_ROM_VSTAT_VFAILUNTRUST: 4709 str = "Validation Fail. Valid but untrusted contents"; 4710 break; 4711 case PCI_MAPREG_ROM_VSTAT_WPASS: 4712 str = "Warning Pass. Validation passed with warning. " 4713 "Valid contents, trust test was not performed"; 4714 break; 4715 case PCI_MAPREG_ROM_VSTAT_WPASSTRUST: 4716 str = "Warning Pass. Validation passed with warning. " 4717 "Valid and trusted contents"; 4718 break; 4719 } 4720 printf("%s\n", str); 4721 printf(" Validation Details: 0x%x\n", 4722 (uint32_t)__SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_DETAIL)); 4723 4724 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4725 printf(" Capability list pointer: 0x%02x\n", 4726 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4727 else 4728 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4729 4730 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 4731 4732 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4733 printf(" Maximum Latency: 0x%02x\n", PCI_MAX_LAT(rval)); 4734 printf(" Minimum Grant: 0x%02x\n", PCI_MIN_GNT(rval)); 4735 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 4736 switch (PCI_INTERRUPT_PIN(rval)) { 4737 case PCI_INTERRUPT_PIN_NONE: 4738 printf("(none)"); 4739 break; 4740 case PCI_INTERRUPT_PIN_A: 4741 printf("(pin A)"); 4742 break; 4743 case PCI_INTERRUPT_PIN_B: 4744 printf("(pin B)"); 4745 break; 4746 case PCI_INTERRUPT_PIN_C: 4747 printf("(pin C)"); 4748 break; 4749 case PCI_INTERRUPT_PIN_D: 4750 printf("(pin D)"); 4751 break; 4752 default: 4753 printf("(? ? ?)"); 4754 break; 4755 } 4756 printf("\n"); 4757 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 4758 } 4759 4760 static void 4761 pci_conf_print_type1( 4762 #ifdef _KERNEL 4763 pci_chipset_tag_t pc, pcitag_t tag, 4764 #endif 4765 const pcireg_t *regs) 4766 { 4767 int off, width; 4768 pcireg_t rval, csreg; 4769 uint32_t base, limit; 4770 uint32_t base_h, limit_h; 4771 uint64_t pbase, plimit; 4772 int use_upper; 4773 4774 /* 4775 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 4776 * Bridge chip documentation, and may not be correct with 4777 * respect to various standards. (XXX) 4778 */ 4779 4780 for (off = 0x10; off < 0x18; off += width) { 4781 #ifdef _KERNEL 4782 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4783 #else 4784 width = pci_conf_print_bar(regs, off, NULL); 4785 #endif 4786 } 4787 4788 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4789 printf(" Primary bus number: 0x%02x\n", 4790 PCI_BRIDGE_BUS_NUM_PRIMARY(rval)); 4791 printf(" Secondary bus number: 0x%02x\n", 4792 PCI_BRIDGE_BUS_NUM_SECONDARY(rval)); 4793 printf(" Subordinate bus number: 0x%02x\n", 4794 PCI_BRIDGE_BUS_NUM_SUBORDINATE(rval)); 4795 printf(" Secondary bus latency timer: 0x%02x\n", 4796 PCI_BRIDGE_BUS_SEC_LATTIMER_VAL(rval)); 4797 4798 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 4799 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 4800 4801 /* I/O region */ 4802 printf(" I/O region:\n"); 4803 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 4804 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 4805 if (PCI_BRIDGE_IO_32BITS(rval)) 4806 use_upper = 1; 4807 else 4808 use_upper = 0; 4809 onoff("32bit I/O", rval, use_upper); 4810 base = PCI_BRIDGE_STATIO_IOBASE_ADDR(rval); 4811 limit = PCI_BRIDGE_STATIO_IOLIMIT_ADDR(rval); 4812 4813 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 4814 base_h = __SHIFTOUT(rval, PCI_BRIDGE_IOHIGH_BASE); 4815 limit_h = __SHIFTOUT(rval, PCI_BRIDGE_IOHIGH_LIMIT); 4816 printf(" base upper 16 bits register: 0x%04x\n", base_h); 4817 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 4818 4819 if (use_upper == 1) { 4820 base |= base_h << 16; 4821 limit |= limit_h << 16; 4822 } 4823 if (base < limit) { 4824 if (use_upper == 1) 4825 printf(" range: 0x%08x-0x%08x\n", base, limit); 4826 else 4827 printf(" range: 0x%04x-0x%04x\n", base, limit); 4828 } else 4829 printf(" range: not set\n"); 4830 4831 /* Non-prefetchable memory region */ 4832 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 4833 printf(" Memory region:\n"); 4834 printf(" base register: 0x%04hx\n", 4835 (uint16_t)__SHIFTOUT(rval, PCI_BRIDGE_MEMORY_BASE)); 4836 printf(" limit register: 0x%04hx\n", 4837 (uint16_t)__SHIFTOUT(rval, PCI_BRIDGE_MEMORY_LIMIT)); 4838 base = PCI_BRIDGE_MEMORY_BASE_ADDR(rval); 4839 limit = PCI_BRIDGE_MEMORY_LIMIT_ADDR(rval); 4840 if (base < limit) 4841 printf(" range: 0x%08x-0x%08x\n", base, limit); 4842 else 4843 printf(" range: not set\n"); 4844 4845 /* Prefetchable memory region */ 4846 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 4847 printf(" Prefetchable memory region:\n"); 4848 printf(" base register: 0x%04x\n", 4849 (rval >> 0) & 0xffff); 4850 printf(" limit register: 0x%04x\n", 4851 (rval >> 16) & 0xffff); 4852 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASEUP32_REG)]; 4853 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMITUP32_REG)]; 4854 printf(" base upper 32 bits register: 0x%08x\n", 4855 base_h); 4856 printf(" limit upper 32 bits register: 0x%08x\n", 4857 limit_h); 4858 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 4859 use_upper = 1; 4860 else 4861 use_upper = 0; 4862 onoff("64bit memory address", rval, use_upper); 4863 pbase = PCI_BRIDGE_PREFETCHMEM_BASE_ADDR(rval); 4864 plimit = PCI_BRIDGE_PREFETCHMEM_LIMIT_ADDR(rval); 4865 if (use_upper == 1) { 4866 pbase |= (uint64_t)base_h << 32; 4867 plimit |= (uint64_t)limit_h << 32; 4868 } 4869 if (pbase < plimit) { 4870 if (use_upper == 1) 4871 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 4872 "\n", pbase, plimit); 4873 else 4874 printf(" range: 0x%08x-0x%08x\n", 4875 (uint32_t)pbase, (uint32_t)plimit); 4876 } else 4877 printf(" range: not set\n"); 4878 4879 csreg = regs[o2i(PCI_COMMAND_STATUS_REG)]; 4880 if (csreg & PCI_STATUS_CAPLIST_SUPPORT) 4881 printf(" Capability list pointer: 0x%02x\n", 4882 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4883 else 4884 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4885 4886 printf(" Expansion ROM Base Address: 0x%08x\n", 4887 regs[o2i(PCI_BRIDGE_EXPROMADDR_REG)]); 4888 4889 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4890 printf(" Interrupt line: 0x%02x\n", 4891 (rval >> 0) & 0xff); 4892 printf(" Interrupt pin: 0x%02x ", 4893 (rval >> 8) & 0xff); 4894 switch ((rval >> 8) & 0xff) { 4895 case PCI_INTERRUPT_PIN_NONE: 4896 printf("(none)"); 4897 break; 4898 case PCI_INTERRUPT_PIN_A: 4899 printf("(pin A)"); 4900 break; 4901 case PCI_INTERRUPT_PIN_B: 4902 printf("(pin B)"); 4903 break; 4904 case PCI_INTERRUPT_PIN_C: 4905 printf("(pin C)"); 4906 break; 4907 case PCI_INTERRUPT_PIN_D: 4908 printf("(pin D)"); 4909 break; 4910 default: 4911 printf("(? ? ?)"); 4912 break; 4913 } 4914 printf("\n"); 4915 rval = regs[o2i(PCI_BRIDGE_CONTROL_REG)]; 4916 printf(" Bridge control register: 0x%04hx\n", 4917 (uint16_t)__SHIFTOUT(rval, PCI_BRIDGE_CONTROL)); 4918 onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE); 4919 onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR); 4920 onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA); 4921 onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA); 4922 /* 4923 * VGA 16bit decode bit has meaning if the VGA enable bit or the 4924 * VGA Palette Snoop Enable bit is set. 4925 */ 4926 if (((rval & PCI_BRIDGE_CONTROL_VGA) != 0) 4927 || ((csreg & PCI_COMMAND_PALETTE_ENABLE) != 0)) 4928 onoff("VGA 16bit enable", rval, PCI_BRIDGE_CONTROL_VGA16); 4929 onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT); 4930 onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR); 4931 onoff("Fast back-to-back enable", rval, PCI_BRIDGE_CONTROL_SECFASTB2B); 4932 onoff("Primary Discard Timer", rval, 4933 PCI_BRIDGE_CONTROL_PRI_DISC_TIMER); 4934 onoff("Secondary Discard Timer", 4935 rval, PCI_BRIDGE_CONTROL_SEC_DISC_TIMER); 4936 onoff("Discard Timer Status", rval, 4937 PCI_BRIDGE_CONTROL_DISC_TIMER_STAT); 4938 onoff("Discard Timer SERR# Enable", rval, 4939 PCI_BRIDGE_CONTROL_DISC_TIMER_SERR); 4940 } 4941 4942 static void 4943 pci_conf_print_type2( 4944 #ifdef _KERNEL 4945 pci_chipset_tag_t pc, pcitag_t tag, 4946 #endif 4947 const pcireg_t *regs) 4948 { 4949 pcireg_t rval; 4950 4951 /* 4952 * XXX these need to be printed in more detail, need to be 4953 * XXX checked against specs/docs, etc. 4954 * 4955 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 4956 * controller chip documentation, and may not be correct with 4957 * respect to various standards. (XXX) 4958 */ 4959 4960 #ifdef _KERNEL 4961 pci_conf_print_bar(pc, tag, regs, 0x10, 4962 "CardBus socket/ExCA registers"); 4963 #else 4964 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 4965 #endif 4966 4967 /* Capability list pointer and secondary status register */ 4968 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 4969 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4970 printf(" Capability list pointer: 0x%02x\n", 4971 PCI_CAPLIST_PTR(rval)); 4972 else 4973 printf(" Reserved @ 0x14: 0x%04x\n", 4974 (pcireg_t)__SHIFTOUT(rval, __BITS(15, 0))); 4975 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 4976 4977 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4978 printf(" PCI bus number: 0x%02x\n", 4979 (rval >> 0) & 0xff); 4980 printf(" CardBus bus number: 0x%02x\n", 4981 (rval >> 8) & 0xff); 4982 printf(" Subordinate bus number: 0x%02x\n", 4983 (rval >> 16) & 0xff); 4984 printf(" CardBus latency timer: 0x%02x\n", 4985 (rval >> 24) & 0xff); 4986 4987 /* XXX Print more prettily */ 4988 printf(" CardBus memory region 0:\n"); 4989 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 4990 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 4991 printf(" CardBus memory region 1:\n"); 4992 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 4993 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 4994 printf(" CardBus I/O region 0:\n"); 4995 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 4996 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 4997 printf(" CardBus I/O region 1:\n"); 4998 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 4999 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 5000 5001 rval = regs[o2i(PCI_INTERRUPT_REG)]; 5002 printf(" Interrupt line: 0x%02x\n", 5003 (rval >> 0) & 0xff); 5004 printf(" Interrupt pin: 0x%02x ", 5005 (rval >> 8) & 0xff); 5006 switch ((rval >> 8) & 0xff) { 5007 case PCI_INTERRUPT_PIN_NONE: 5008 printf("(none)"); 5009 break; 5010 case PCI_INTERRUPT_PIN_A: 5011 printf("(pin A)"); 5012 break; 5013 case PCI_INTERRUPT_PIN_B: 5014 printf("(pin B)"); 5015 break; 5016 case PCI_INTERRUPT_PIN_C: 5017 printf("(pin C)"); 5018 break; 5019 case PCI_INTERRUPT_PIN_D: 5020 printf("(pin D)"); 5021 break; 5022 default: 5023 printf("(? ? ?)"); 5024 break; 5025 } 5026 printf("\n"); 5027 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> 16) & 0xffff; 5028 printf(" Bridge control register: 0x%04x\n", rval); 5029 onoff("Parity error response", rval, __BIT(0)); 5030 onoff("SERR# enable", rval, __BIT(1)); 5031 onoff("ISA enable", rval, __BIT(2)); 5032 onoff("VGA enable", rval, __BIT(3)); 5033 onoff("Master abort mode", rval, __BIT(5)); 5034 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 5035 onoff("Functional interrupts routed by ExCA registers", rval, 5036 __BIT(7)); 5037 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 5038 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 5039 onoff("Write posting enable", rval, __BIT(10)); 5040 5041 rval = regs[o2i(0x40)]; 5042 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 5043 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 5044 5045 #ifdef _KERNEL 5046 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers"); 5047 #else 5048 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 5049 #endif 5050 } 5051 5052 void 5053 pci_conf_print( 5054 #ifdef _KERNEL 5055 pci_chipset_tag_t pc, pcitag_t tag, 5056 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 5057 #else 5058 int pcifd, u_int bus, u_int dev, u_int func 5059 #endif 5060 ) 5061 { 5062 pcireg_t *regs; 5063 int off, capoff, endoff, hdrtype; 5064 const char *type_name; 5065 #ifdef _KERNEL 5066 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 5067 #else 5068 void (*type_printfn)(const pcireg_t *); 5069 #endif 5070 5071 regs = MALLOC(PCI_EXTCONF_SIZE); 5072 5073 printf("PCI configuration registers:\n"); 5074 5075 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 5076 #ifdef _KERNEL 5077 regs[o2i(off)] = pci_conf_read(pc, tag, off); 5078 #else 5079 if (pcibus_conf_read(pcifd, bus, dev, func, off, 5080 ®s[o2i(off)]) == -1) 5081 regs[o2i(off)] = 0; 5082 #endif 5083 } 5084 5085 /* common header */ 5086 printf(" Common header:\n"); 5087 pci_conf_print_regs(regs, 0, 16); 5088 5089 printf("\n"); 5090 #ifdef _KERNEL 5091 pci_conf_print_common(pc, tag, regs); 5092 #else 5093 pci_conf_print_common(regs); 5094 #endif 5095 printf("\n"); 5096 5097 /* type-dependent header */ 5098 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 5099 switch (hdrtype) { /* XXX make a table, eventually */ 5100 case 0: 5101 /* Standard device header */ 5102 type_name = "\"normal\" device"; 5103 type_printfn = &pci_conf_print_type0; 5104 capoff = PCI_CAPLISTPTR_REG; 5105 endoff = 64; 5106 break; 5107 case 1: 5108 /* PCI-PCI bridge header */ 5109 type_name = "PCI-PCI bridge"; 5110 type_printfn = &pci_conf_print_type1; 5111 capoff = PCI_CAPLISTPTR_REG; 5112 endoff = 64; 5113 break; 5114 case 2: 5115 /* PCI-CardBus bridge header */ 5116 type_name = "PCI-CardBus bridge"; 5117 type_printfn = &pci_conf_print_type2; 5118 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 5119 endoff = 72; 5120 break; 5121 default: 5122 type_name = NULL; 5123 type_printfn = 0; 5124 capoff = -1; 5125 endoff = 64; 5126 break; 5127 } 5128 printf(" Type %d ", hdrtype); 5129 if (type_name != NULL) 5130 printf("(%s) ", type_name); 5131 printf("header:\n"); 5132 pci_conf_print_regs(regs, 16, endoff); 5133 printf("\n"); 5134 if (type_printfn) { 5135 #ifdef _KERNEL 5136 (*type_printfn)(pc, tag, regs); 5137 #else 5138 (*type_printfn)(regs); 5139 #endif 5140 } else 5141 printf(" Don't know how to pretty-print type %d header.\n", 5142 hdrtype); 5143 printf("\n"); 5144 5145 /* capability list, if present */ 5146 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 5147 && (capoff > 0)) { 5148 #ifdef _KERNEL 5149 pci_conf_print_caplist(pc, tag, regs, capoff); 5150 #else 5151 pci_conf_print_caplist(regs, capoff); 5152 #endif 5153 printf("\n"); 5154 } 5155 5156 /* device-dependent header */ 5157 printf(" Device-dependent header:\n"); 5158 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 5159 #ifdef _KERNEL 5160 printf("\n"); 5161 if (printfn) 5162 (*printfn)(pc, tag, regs); 5163 else 5164 printf(" Don't know how to pretty-print device-dependent header.\n"); 5165 #endif /* _KERNEL */ 5166 5167 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 5168 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 5169 goto out; 5170 5171 printf("\n"); 5172 #ifdef _KERNEL 5173 pci_conf_print_extcaplist(pc, tag, regs); 5174 #else 5175 pci_conf_print_extcaplist(regs); 5176 #endif 5177 printf("\n"); 5178 5179 /* Extended Configuration Space, if present */ 5180 printf(" Extended Configuration Space:\n"); 5181 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 5182 5183 out: 5184 FREE(regs, PCI_EXTCONF_SIZE); 5185 } 5186
Indexes created Tue Sep 30 11:09:46 GMT 2025