pci_subr.c revision 1.226
1 /* $NetBSD: pci_subr.c,v 1.226 2021/06/29 21:03:36 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.226 2021/06/29 21:03:36 pgoyette Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #include <sys/kmem.h> 56 57 #define MALLOC(sz) kmem_alloc(sz, KM_SLEEP) 58 #define FREE(p, sz) kmem_free(p, sz) 59 60 #else 61 #include <pci.h> 62 #include <stdarg.h> 63 #include <stdbool.h> 64 #include <stdio.h> 65 #include <stdlib.h> 66 #include <string.h> 67 68 #define MALLOC(sz) malloc(sz) 69 #define FREE(p, sz) free(p) 70 71 #endif 72 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcidevs.h> 75 #ifdef _KERNEL 76 #include <dev/pci/pcivar.h> 77 #else 78 #include <dev/pci/pci_verbose.h> 79 #include <dev/pci/pcidevs_data.h> 80 #endif 81 82 static int pci_conf_find_cap(const pcireg_t *, unsigned int, int *); 83 static int pci_conf_find_extcap(const pcireg_t *, unsigned int, int *); 84 static void pci_conf_print_pcie_power(uint8_t, unsigned int); 85 #define PCIREG_SHIFTOUT(a, b) ((pcireg_t)__SHIFTOUT((a), (b))) 86 87 #ifdef _KERNEL 88 /* 89 * Common routines used to match a compatible device by its PCI ID code. 90 */ 91 92 const struct device_compatible_entry * 93 pci_compatible_lookup_id(pcireg_t const id, 94 const struct device_compatible_entry *dce) 95 { 96 return device_compatible_lookup_id(id, PCI_COMPAT_EOL_VALUE, dce); 97 } 98 99 const struct device_compatible_entry * 100 pci_compatible_lookup(const struct pci_attach_args * const pa, 101 const struct device_compatible_entry * const dce) 102 { 103 return pci_compatible_lookup_id(pa->pa_id, dce); 104 } 105 106 const struct device_compatible_entry * 107 pci_compatible_lookup_subsys(const struct pci_attach_args * const pa, 108 const struct device_compatible_entry * const dce) 109 { 110 const pcireg_t subsysid = 111 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 112 113 return pci_compatible_lookup_id(subsysid, dce); 114 } 115 116 int 117 pci_compatible_match(const struct pci_attach_args * const pa, 118 const struct device_compatible_entry * const dce) 119 { 120 return pci_compatible_lookup(pa, dce) != NULL; 121 } 122 123 int 124 pci_compatible_match_subsys(const struct pci_attach_args * const pa, 125 const struct device_compatible_entry * const dce) 126 { 127 return pci_compatible_lookup_subsys(pa, dce) != NULL; 128 } 129 #endif /* _KERNEL */ 130 131 /* 132 * Descriptions of known PCI classes and subclasses. 133 * 134 * Subclasses are described in the same way as classes, but have a 135 * NULL subclass pointer. 136 */ 137 struct pci_class { 138 const char *name; 139 u_int val; /* as wide as pci_{,sub}class_t */ 140 const struct pci_class *subclasses; 141 }; 142 143 /* 144 * Class 0x00. 145 * Before rev. 2.0. 146 */ 147 static const struct pci_class pci_subclass_prehistoric[] = { 148 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 149 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 150 { NULL, 0, NULL, }, 151 }; 152 153 /* 154 * Class 0x01. 155 * Mass storage controller 156 */ 157 158 /* ATA programming interface */ 159 static const struct pci_class pci_interface_ata[] = { 160 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 161 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 162 { NULL, 0, NULL, }, 163 }; 164 165 /* SATA programming interface */ 166 static const struct pci_class pci_interface_sata[] = { 167 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 168 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 169 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 170 { NULL, 0, NULL, }, 171 }; 172 173 /* Flash programming interface */ 174 static const struct pci_class pci_interface_nvm[] = { 175 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 176 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 177 { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, }, 178 { NULL, 0, NULL, }, 179 }; 180 181 /* Subclasses */ 182 static const struct pci_class pci_subclass_mass_storage[] = { 183 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 184 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 185 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 186 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 187 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 188 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 189 pci_interface_ata, }, 190 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 191 pci_interface_sata, }, 192 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 193 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 194 pci_interface_nvm, }, 195 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 196 { NULL, 0, NULL, }, 197 }; 198 199 /* 200 * Class 0x02. 201 * Network controller. 202 */ 203 static const struct pci_class pci_subclass_network[] = { 204 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 205 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 206 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 207 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 208 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 209 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 210 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 211 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 212 { NULL, 0, NULL, }, 213 }; 214 215 /* 216 * Class 0x03. 217 * Display controller. 218 */ 219 220 /* VGA programming interface */ 221 static const struct pci_class pci_interface_vga[] = { 222 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 223 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 224 { NULL, 0, NULL, }, 225 }; 226 /* Subclasses */ 227 static const struct pci_class pci_subclass_display[] = { 228 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 229 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 230 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 231 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 232 { NULL, 0, NULL, }, 233 }; 234 235 /* 236 * Class 0x04. 237 * Multimedia device. 238 */ 239 static const struct pci_class pci_subclass_multimedia[] = { 240 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 241 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 242 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 243 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 244 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 245 { NULL, 0, NULL, }, 246 }; 247 248 /* 249 * Class 0x05. 250 * Memory controller. 251 */ 252 static const struct pci_class pci_subclass_memory[] = { 253 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 254 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 255 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 256 { NULL, 0, NULL, }, 257 }; 258 259 /* 260 * Class 0x06. 261 * Bridge device. 262 */ 263 264 /* PCI bridge programming interface */ 265 static const struct pci_class pci_interface_pcibridge[] = { 266 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 267 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 268 { NULL, 0, NULL, }, 269 }; 270 271 /* Semi-transparent PCI-to-PCI bridge programming interface */ 272 static const struct pci_class pci_interface_stpci[] = { 273 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 274 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 275 { NULL, 0, NULL, }, 276 }; 277 278 /* Advanced Switching programming interface */ 279 static const struct pci_class pci_interface_advsw[] = { 280 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 281 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 282 { NULL, 0, NULL, }, 283 }; 284 285 /* Subclasses */ 286 static const struct pci_class pci_subclass_bridge[] = { 287 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 288 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 289 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 290 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 291 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 292 pci_interface_pcibridge, }, 293 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 294 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 295 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 296 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 297 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 298 pci_interface_stpci, }, 299 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 300 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 301 pci_interface_advsw, }, 302 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 303 { NULL, 0, NULL, }, 304 }; 305 306 /* 307 * Class 0x07. 308 * Simple communications controller. 309 */ 310 311 /* Serial controller programming interface */ 312 static const struct pci_class pci_interface_serial[] = { 313 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 314 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 315 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 316 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 317 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 318 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 319 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 320 { NULL, 0, NULL, }, 321 }; 322 323 /* Parallel controller programming interface */ 324 static const struct pci_class pci_interface_parallel[] = { 325 { "", PCI_INTERFACE_PARALLEL, NULL,}, 326 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 327 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 328 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 329 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 330 { NULL, 0, NULL,}, 331 }; 332 333 /* Modem programming interface */ 334 static const struct pci_class pci_interface_modem[] = { 335 { "", PCI_INTERFACE_MODEM, NULL,}, 336 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 337 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 338 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 339 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 340 { NULL, 0, NULL,}, 341 }; 342 343 /* Subclasses */ 344 static const struct pci_class pci_subclass_communications[] = { 345 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 346 pci_interface_serial, }, 347 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 348 pci_interface_parallel, }, 349 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 350 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 351 pci_interface_modem, }, 352 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 353 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 354 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 355 { NULL, 0, NULL,}, 356 }; 357 358 /* 359 * Class 0x08. 360 * Base system peripheral. 361 */ 362 363 /* PIC programming interface */ 364 static const struct pci_class pci_interface_pic[] = { 365 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 366 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 367 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 368 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 369 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 370 { NULL, 0, NULL, }, 371 }; 372 373 /* DMA programming interface */ 374 static const struct pci_class pci_interface_dma[] = { 375 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 376 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 377 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 378 { NULL, 0, NULL, }, 379 }; 380 381 /* Timer programming interface */ 382 static const struct pci_class pci_interface_tmr[] = { 383 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 384 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 385 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 386 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 387 { NULL, 0, NULL, }, 388 }; 389 390 /* RTC programming interface */ 391 static const struct pci_class pci_interface_rtc[] = { 392 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 393 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 394 { NULL, 0, NULL, }, 395 }; 396 397 /* Subclasses */ 398 static const struct pci_class pci_subclass_system[] = { 399 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 400 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 401 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 402 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 403 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 404 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 405 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 406 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 407 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 408 { NULL, 0, NULL, }, 409 }; 410 411 /* 412 * Class 0x09. 413 * Input device. 414 */ 415 416 /* Gameport programming interface */ 417 static const struct pci_class pci_interface_game[] = { 418 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 419 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 420 { NULL, 0, NULL, }, 421 }; 422 423 /* Subclasses */ 424 static const struct pci_class pci_subclass_input[] = { 425 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 426 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 427 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 428 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 429 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 430 pci_interface_game, }, 431 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 432 { NULL, 0, NULL, }, 433 }; 434 435 /* 436 * Class 0x0a. 437 * Docking station. 438 */ 439 static const struct pci_class pci_subclass_dock[] = { 440 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 441 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 442 { NULL, 0, NULL, }, 443 }; 444 445 /* 446 * Class 0x0b. 447 * Processor. 448 */ 449 static const struct pci_class pci_subclass_processor[] = { 450 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 451 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 452 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 453 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 454 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 455 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 456 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 457 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 458 { NULL, 0, NULL, }, 459 }; 460 461 /* 462 * Class 0x0c. 463 * Serial bus controller. 464 */ 465 466 /* IEEE1394 programming interface */ 467 static const struct pci_class pci_interface_ieee1394[] = { 468 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 469 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 470 { NULL, 0, NULL,}, 471 }; 472 473 /* USB programming interface */ 474 static const struct pci_class pci_interface_usb[] = { 475 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 476 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 477 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 478 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 479 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 480 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 481 { NULL, 0, NULL, }, 482 }; 483 484 /* IPMI programming interface */ 485 static const struct pci_class pci_interface_ipmi[] = { 486 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL, }, 487 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL, }, 488 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL, }, 489 { NULL, 0, NULL, }, 490 }; 491 492 /* Subclasses */ 493 static const struct pci_class pci_subclass_serialbus[] = { 494 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 495 pci_interface_ieee1394, }, 496 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 497 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 498 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 499 pci_interface_usb, }, 500 /* XXX Fiber Channel/_FIBRECHANNEL */ 501 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 502 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 503 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 504 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 505 pci_interface_ipmi, }, 506 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 507 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 508 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 509 { NULL, 0, NULL, }, 510 }; 511 512 /* 513 * Class 0x0d. 514 * Wireless Controller. 515 */ 516 static const struct pci_class pci_subclass_wireless[] = { 517 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 518 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 519 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 520 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 521 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 522 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 523 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 524 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 525 { NULL, 0, NULL, }, 526 }; 527 528 /* 529 * Class 0x0e. 530 * Intelligent IO controller. 531 */ 532 533 /* Intelligent IO programming interface */ 534 static const struct pci_class pci_interface_i2o[] = { 535 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL, }, 536 { NULL, 0, NULL, }, 537 }; 538 539 /* Subclasses */ 540 static const struct pci_class pci_subclass_i2o[] = { 541 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 542 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 543 { NULL, 0, NULL, }, 544 }; 545 546 /* 547 * Class 0x0f. 548 * Satellite communication controller. 549 */ 550 static const struct pci_class pci_subclass_satcom[] = { 551 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 552 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 553 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 554 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 555 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 556 { NULL, 0, NULL, }, 557 }; 558 559 /* 560 * Class 0x10. 561 * Encryption/Decryption controller. 562 */ 563 static const struct pci_class pci_subclass_crypto[] = { 564 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 565 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 566 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 567 { NULL, 0, NULL, }, 568 }; 569 570 /* 571 * Class 0x11. 572 * Data aquuisition and signal processing controller. 573 */ 574 static const struct pci_class pci_subclass_dasp[] = { 575 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 576 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 577 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 578 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 579 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 580 { NULL, 0, NULL, }, 581 }; 582 583 /* List of classes */ 584 static const struct pci_class pci_classes[] = { 585 { "prehistoric", PCI_CLASS_PREHISTORIC, 586 pci_subclass_prehistoric, }, 587 { "mass storage", PCI_CLASS_MASS_STORAGE, 588 pci_subclass_mass_storage, }, 589 { "network", PCI_CLASS_NETWORK, 590 pci_subclass_network, }, 591 { "display", PCI_CLASS_DISPLAY, 592 pci_subclass_display, }, 593 { "multimedia", PCI_CLASS_MULTIMEDIA, 594 pci_subclass_multimedia, }, 595 { "memory", PCI_CLASS_MEMORY, 596 pci_subclass_memory, }, 597 { "bridge", PCI_CLASS_BRIDGE, 598 pci_subclass_bridge, }, 599 { "communications", PCI_CLASS_COMMUNICATIONS, 600 pci_subclass_communications, }, 601 { "system", PCI_CLASS_SYSTEM, 602 pci_subclass_system, }, 603 { "input", PCI_CLASS_INPUT, 604 pci_subclass_input, }, 605 { "dock", PCI_CLASS_DOCK, 606 pci_subclass_dock, }, 607 { "processor", PCI_CLASS_PROCESSOR, 608 pci_subclass_processor, }, 609 { "serial bus", PCI_CLASS_SERIALBUS, 610 pci_subclass_serialbus, }, 611 { "wireless", PCI_CLASS_WIRELESS, 612 pci_subclass_wireless, }, 613 { "I2O", PCI_CLASS_I2O, 614 pci_subclass_i2o, }, 615 { "satellite comm", PCI_CLASS_SATCOM, 616 pci_subclass_satcom, }, 617 { "crypto", PCI_CLASS_CRYPTO, 618 pci_subclass_crypto, }, 619 { "DASP", PCI_CLASS_DASP, 620 pci_subclass_dasp, }, 621 { "processing accelerators", PCI_CLASS_ACCEL, 622 NULL, }, 623 { "non-essential instrumentation", PCI_CLASS_INSTRUMENT, 624 NULL, }, 625 { "undefined", PCI_CLASS_UNDEFINED, 626 NULL, }, 627 { NULL, 0, 628 NULL, }, 629 }; 630 631 DEV_VERBOSE_DEFINE(pci); 632 633 /* 634 * Append a formatted string to dest without writing more than len 635 * characters (including the trailing NUL character). dest and len 636 * are updated for use in subsequent calls to snappendf(). 637 * 638 * Returns 0 on success, a negative value if vnsprintf() fails, or 639 * a positive value if the dest buffer would have overflowed. 640 */ 641 642 static int __printflike(3, 4) 643 snappendf(char **dest, size_t *len, const char * restrict fmt, ...) 644 { 645 va_list ap; 646 int count; 647 648 va_start(ap, fmt); 649 count = vsnprintf(*dest, *len, fmt, ap); 650 va_end(ap); 651 652 /* Let vsnprintf() errors bubble up to caller */ 653 if (count < 0 || *len == 0) 654 return count; 655 656 /* Handle overflow */ 657 if ((size_t)count >= *len) { 658 *dest += *len - 1; 659 *len = 1; 660 return 1; 661 } 662 663 /* Update dest & len to point at trailing NUL */ 664 *dest += count; 665 *len -= count; 666 667 return 0; 668 } 669 670 void 671 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 672 size_t l) 673 { 674 pci_class_t class; 675 pci_subclass_t subclass; 676 pci_interface_t interface; 677 pci_revision_t revision; 678 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 679 const struct pci_class *classp, *subclassp, *interfacep; 680 681 class = PCI_CLASS(class_reg); 682 subclass = PCI_SUBCLASS(class_reg); 683 interface = PCI_INTERFACE(class_reg); 684 revision = PCI_REVISION(class_reg); 685 686 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 687 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 688 PCI_PRODUCT(id_reg)); 689 690 classp = pci_classes; 691 while (classp->name != NULL) { 692 if (class == classp->val) 693 break; 694 classp++; 695 } 696 697 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 698 while (subclassp && subclassp->name != NULL) { 699 if (subclass == subclassp->val) 700 break; 701 subclassp++; 702 } 703 704 interfacep = (subclassp && subclassp->name != NULL) ? 705 subclassp->subclasses : NULL; 706 while (interfacep && interfacep->name != NULL) { 707 if (interface == interfacep->val) 708 break; 709 interfacep++; 710 } 711 712 (void)snappendf(&cp, &l, "%s %s", vendor, product); 713 if (showclass) { 714 (void)snappendf(&cp, &l, " ("); 715 if (classp->name == NULL) 716 (void)snappendf(&cp, &l, 717 "class 0x%02x, subclass 0x%02x", 718 class, subclass); 719 else { 720 if (subclassp == NULL || subclassp->name == NULL) 721 (void)snappendf(&cp, &l, 722 "%s, subclass 0x%02x", 723 classp->name, subclass); 724 else 725 (void)snappendf(&cp, &l, "%s %s", 726 subclassp->name, classp->name); 727 } 728 if ((interfacep == NULL) || (interfacep->name == NULL)) { 729 if (interface != 0) 730 (void)snappendf(&cp, &l, ", interface 0x%02x", 731 interface); 732 } else if (strncmp(interfacep->name, "", 1) != 0) 733 (void)snappendf(&cp, &l, ", %s", interfacep->name); 734 if (revision != 0) 735 (void)snappendf(&cp, &l, ", revision 0x%02x", revision); 736 (void)snappendf(&cp, &l, ")"); 737 } 738 } 739 740 #ifdef _KERNEL 741 void 742 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 743 const char *known, int addrev) 744 { 745 char devinfo[256]; 746 747 if (known) { 748 aprint_normal(": %s", known); 749 if (addrev) 750 aprint_normal(" (rev. 0x%02x)", 751 PCI_REVISION(pa->pa_class)); 752 aprint_normal("\n"); 753 } else { 754 pci_devinfo(pa->pa_id, pa->pa_class, 0, 755 devinfo, sizeof(devinfo)); 756 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 757 PCI_REVISION(pa->pa_class)); 758 } 759 if (naive) 760 aprint_naive(": %s\n", naive); 761 else 762 aprint_naive("\n"); 763 } 764 #endif 765 766 /* 767 * Print out most of the PCI configuration registers. Typically used 768 * in a device attach routine like this: 769 * 770 * #ifdef MYDEV_DEBUG 771 * printf("%s: ", device_xname(sc->sc_dev)); 772 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 773 * #endif 774 */ 775 776 #define i2o(i) ((i) * 4) 777 #define o2i(o) ((o) / 4) 778 #define onoff2(str, rval, bit, onstr, offstr) \ 779 /*CONSTCOND*/ \ 780 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 781 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 782 783 static void 784 pci_conf_print_common( 785 #ifdef _KERNEL 786 pci_chipset_tag_t pc, pcitag_t tag, 787 #endif 788 const pcireg_t *regs) 789 { 790 pci_class_t class; 791 pci_subclass_t subclass; 792 pci_interface_t interface; 793 pci_revision_t revision; 794 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 795 const struct pci_class *classp, *subclassp, *interfacep; 796 const char *name; 797 pcireg_t rval; 798 unsigned int num; 799 800 rval = regs[o2i(PCI_CLASS_REG)]; 801 class = PCI_CLASS(rval); 802 subclass = PCI_SUBCLASS(rval); 803 interface = PCI_INTERFACE(rval); 804 revision = PCI_REVISION(rval); 805 806 rval = regs[o2i(PCI_ID_REG)]; 807 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 808 if (name) 809 printf(" Vendor Name: %s (0x%04x)\n", name, 810 PCI_VENDOR(rval)); 811 else 812 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 813 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 814 PCI_PRODUCT(rval)); 815 if (name) 816 printf(" Device Name: %s (0x%04x)\n", name, 817 PCI_PRODUCT(rval)); 818 else 819 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 820 821 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 822 823 printf(" Command register: 0x%04x\n", rval & 0xffff); 824 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 825 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 826 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 827 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 828 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 829 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 830 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 831 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 832 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 833 onoff("Fast back-to-back transactions", rval, 834 PCI_COMMAND_BACKTOBACK_ENABLE); 835 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 836 837 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 838 onoff("Immediate Readiness", rval, PCI_STATUS_IMMD_READNESS); 839 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 840 "inactive"); 841 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 842 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 843 onoff("User Definable Features (UDF) support", rval, 844 PCI_STATUS_UDF_SUPPORT); 845 onoff("Fast back-to-back capable", rval, 846 PCI_STATUS_BACKTOBACK_SUPPORT); 847 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 848 849 printf(" DEVSEL timing: "); 850 switch (rval & PCI_STATUS_DEVSEL_MASK) { 851 case PCI_STATUS_DEVSEL_FAST: 852 printf("fast"); 853 break; 854 case PCI_STATUS_DEVSEL_MEDIUM: 855 printf("medium"); 856 break; 857 case PCI_STATUS_DEVSEL_SLOW: 858 printf("slow"); 859 break; 860 default: 861 printf("unknown/reserved"); /* XXX */ 862 break; 863 } 864 printf(" (0x%x)\n", PCIREG_SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK)); 865 866 onoff("Slave signaled Target Abort", rval, 867 PCI_STATUS_TARGET_TARGET_ABORT); 868 onoff("Master received Target Abort", rval, 869 PCI_STATUS_MASTER_TARGET_ABORT); 870 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 871 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 872 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 873 874 rval = regs[o2i(PCI_CLASS_REG)]; 875 for (classp = pci_classes; classp->name != NULL; classp++) { 876 if (class == classp->val) 877 break; 878 } 879 880 /* 881 * ECN: Change Root Complex Event Collector Class Code 882 * Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type 883 * in PCIe extend capability to know whether it's RCEC or IOMMU. 884 */ 885 if ((class == PCI_CLASS_SYSTEM) 886 && (subclass == PCI_SUBCLASS_SYSTEM_IOMMU)) { 887 int pcie_capoff; 888 pcireg_t reg; 889 890 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 891 reg = regs[o2i(pcie_capoff + PCIE_XCAP)]; 892 if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_ROOT_EVNTC) 893 subclass = PCI_SUBCLASS_SYSTEM_RCEC; 894 } 895 } 896 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 897 while (subclassp && subclassp->name != NULL) { 898 if (subclass == subclassp->val) 899 break; 900 subclassp++; 901 } 902 903 interfacep = (subclassp && subclassp->name != NULL) ? 904 subclassp->subclasses : NULL; 905 while (interfacep && interfacep->name != NULL) { 906 if (interface == interfacep->val) 907 break; 908 interfacep++; 909 } 910 911 if (classp->name != NULL) 912 printf(" Class Name: %s (0x%02x)\n", classp->name, class); 913 else 914 printf(" Class ID: 0x%02x\n", class); 915 if (subclassp != NULL && subclassp->name != NULL) 916 printf(" Subclass Name: %s (0x%02x)\n", 917 subclassp->name, PCI_SUBCLASS(rval)); 918 else 919 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 920 if ((interfacep != NULL) && (interfacep->name != NULL) 921 && (strncmp(interfacep->name, "", 1) != 0)) 922 printf(" Interface Name: %s (0x%02x)\n", 923 interfacep->name, interface); 924 else 925 printf(" Interface: 0x%02x\n", interface); 926 printf(" Revision ID: 0x%02x\n", revision); 927 928 rval = regs[o2i(PCI_BHLC_REG)]; 929 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 930 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 931 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 932 PCI_HDRTYPE(rval)); 933 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 934 num = PCI_CACHELINE(rval); 935 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 936 } 937 938 static int 939 pci_conf_print_bar( 940 #ifdef _KERNEL 941 pci_chipset_tag_t pc, pcitag_t tag, 942 #endif 943 const pcireg_t *regs, int reg, const char *name) 944 { 945 int width; 946 pcireg_t rval, rval64h; 947 bool ioen, memen; 948 #ifdef _KERNEL 949 pcireg_t mask, mask64h = 0; 950 #endif 951 952 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 953 ioen = rval & PCI_COMMAND_IO_ENABLE; 954 memen = rval & PCI_COMMAND_MEM_ENABLE; 955 956 width = 4; 957 /* 958 * Section 6.2.5.1, `Address Maps', tells us that: 959 * 960 * 1) The builtin software should have already mapped the 961 * device in a reasonable way. 962 * 963 * 2) A device which wants 2^n bytes of memory will hardwire 964 * the bottom n bits of the address to 0. As recommended, 965 * we write all 1s and see what we get back. 966 */ 967 968 rval = regs[o2i(reg)]; 969 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 970 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 971 rval64h = regs[o2i(reg + 4)]; 972 width = 8; 973 } else 974 rval64h = 0; 975 976 #ifdef _KERNEL 977 if (rval != 0 && memen) { 978 int s; 979 980 /* 981 * The following sequence seems to make some devices 982 * (e.g. host bus bridges, which don't normally 983 * have their space mapped) very unhappy, to 984 * the point of crashing the system. 985 * 986 * Therefore, if the mapping register is zero to 987 * start out with, don't bother trying. 988 */ 989 s = splhigh(); 990 pci_conf_write(pc, tag, reg, 0xffffffff); 991 mask = pci_conf_read(pc, tag, reg); 992 pci_conf_write(pc, tag, reg, rval); 993 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 994 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 995 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 996 mask64h = pci_conf_read(pc, tag, reg + 4); 997 pci_conf_write(pc, tag, reg + 4, rval64h); 998 } 999 splx(s); 1000 } else 1001 mask = mask64h = 0; 1002 #endif /* _KERNEL */ 1003 1004 printf(" Base address register at 0x%02x", reg); 1005 if (name) 1006 printf(" (%s)", name); 1007 printf("\n "); 1008 if (rval == 0) { 1009 printf("not implemented\n"); 1010 return width; 1011 } 1012 printf("type: "); 1013 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 1014 const char *type, *prefetch; 1015 1016 switch (PCI_MAPREG_MEM_TYPE(rval)) { 1017 case PCI_MAPREG_MEM_TYPE_32BIT: 1018 type = "32-bit"; 1019 break; 1020 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 1021 type = "32-bit-1M"; 1022 break; 1023 case PCI_MAPREG_MEM_TYPE_64BIT: 1024 type = "64-bit"; 1025 break; 1026 default: 1027 type = "unknown (XXX)"; 1028 break; 1029 } 1030 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 1031 prefetch = ""; 1032 else 1033 prefetch = "non"; 1034 printf("%s %sprefetchable memory\n", type, prefetch); 1035 switch (PCI_MAPREG_MEM_TYPE(rval)) { 1036 case PCI_MAPREG_MEM_TYPE_64BIT: 1037 printf(" base: 0x%016llx", 1038 PCI_MAPREG_MEM64_ADDR( 1039 ((((long long) rval64h) << 32) | rval))); 1040 if (!memen) 1041 printf(", disabled"); 1042 printf("\n"); 1043 #ifdef _KERNEL 1044 printf(" size: 0x%016llx\n", 1045 PCI_MAPREG_MEM64_SIZE( 1046 ((((long long) mask64h) << 32) | mask))); 1047 #endif 1048 break; 1049 case PCI_MAPREG_MEM_TYPE_32BIT: 1050 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 1051 default: 1052 printf(" base: 0x%08x", 1053 PCI_MAPREG_MEM_ADDR(rval)); 1054 if (!memen) 1055 printf(", disabled"); 1056 printf("\n"); 1057 #ifdef _KERNEL 1058 printf(" size: 0x%08x\n", 1059 PCI_MAPREG_MEM_SIZE(mask)); 1060 #endif 1061 break; 1062 } 1063 } else { 1064 #ifdef _KERNEL 1065 if (ioen) 1066 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 1067 #endif 1068 printf("I/O\n"); 1069 printf(" base: 0x%08x", PCI_MAPREG_IO_ADDR(rval)); 1070 if (!ioen) 1071 printf(", disabled"); 1072 printf("\n"); 1073 #ifdef _KERNEL 1074 printf(" size: 0x%08x\n", PCI_MAPREG_IO_SIZE(mask)); 1075 #endif 1076 } 1077 1078 return width; 1079 } 1080 1081 static void 1082 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 1083 { 1084 int off, needaddr, neednl; 1085 1086 needaddr = 1; 1087 neednl = 0; 1088 for (off = first; off < pastlast; off += 4) { 1089 if ((off % 16) == 0 || needaddr) { 1090 printf(" 0x%02x:", off); 1091 needaddr = 0; 1092 } 1093 printf(" 0x%08x", regs[o2i(off)]); 1094 neednl = 1; 1095 if ((off % 16) == 12) { 1096 printf("\n"); 1097 neednl = 0; 1098 } 1099 } 1100 if (neednl) 1101 printf("\n"); 1102 } 1103 1104 static const char * 1105 pci_conf_print_agp_calcycle(uint8_t cal) 1106 { 1107 1108 switch (cal) { 1109 case 0x0: 1110 return "4ms"; 1111 case 0x1: 1112 return "16ms"; 1113 case 0x2: 1114 return "64ms"; 1115 case 0x3: 1116 return "256ms"; 1117 case 0x7: 1118 return "Calibration Cycle Not Needed"; 1119 default: 1120 return "(reserved)"; 1121 } 1122 } 1123 1124 static void 1125 pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3) 1126 { 1127 if (isagp3) { 1128 /* AGP 3.0 */ 1129 if (reg & AGP_MODE_V3_RATE_4x) 1130 printf("x4"); 1131 if (reg & AGP_MODE_V3_RATE_8x) 1132 printf("x8"); 1133 } else { 1134 /* AGP 2.0 */ 1135 if (reg & AGP_MODE_V2_RATE_1x) 1136 printf("x1"); 1137 if (reg & AGP_MODE_V2_RATE_2x) 1138 printf("x2"); 1139 if (reg & AGP_MODE_V2_RATE_4x) 1140 printf("x4"); 1141 } 1142 printf("\n"); 1143 } 1144 1145 static void 1146 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1147 { 1148 pcireg_t rval; 1149 bool isagp3; 1150 1151 printf("\n AGP Capabilities Register\n"); 1152 1153 rval = regs[o2i(capoff)]; 1154 printf(" Revision: %d.%d\n", 1155 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1156 1157 rval = regs[o2i(capoff + PCI_AGP_STATUS)]; 1158 printf(" Status register: 0x%04x\n", rval); 1159 printf(" RQ: %u\n", 1160 PCIREG_SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1161 printf(" ARQSZ: %u\n", 1162 PCIREG_SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1163 printf(" CAL cycle: %s\n", 1164 pci_conf_print_agp_calcycle(PCIREG_SHIFTOUT(rval, AGP_MODE_CAL))); 1165 onoff("SBA", rval, AGP_MODE_SBA); 1166 onoff("htrans#", rval, AGP_MODE_HTRANS); 1167 onoff("Over 4G", rval, AGP_MODE_4G); 1168 onoff("Fast Write", rval, AGP_MODE_FW); 1169 onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3); 1170 isagp3 = rval & AGP_MODE_MODE_3; 1171 printf(" Data Rate Support: "); 1172 pci_conf_print_agp_datarate(rval, isagp3); 1173 1174 rval = regs[o2i(capoff + PCI_AGP_COMMAND)]; 1175 printf(" Command register: 0x%08x\n", rval); 1176 printf(" PRQ: %u\n", 1177 PCIREG_SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1178 printf(" PARQSZ: %u\n", 1179 PCIREG_SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1180 printf(" PCAL cycle: %s\n", 1181 pci_conf_print_agp_calcycle(PCIREG_SHIFTOUT(rval, AGP_MODE_CAL))); 1182 onoff("SBA", rval, AGP_MODE_SBA); 1183 onoff("AGP", rval, AGP_MODE_AGP); 1184 onoff("Over 4G", rval, AGP_MODE_4G); 1185 onoff("Fast Write", rval, AGP_MODE_FW); 1186 if (isagp3) { 1187 printf(" Data Rate Enable: "); 1188 /* 1189 * The Data Rate Enable bits are used only on 3.0 and the 1190 * Command register has no AGP_MODE_MODE_3 bit, so pass the 1191 * flag to print correctly. 1192 */ 1193 pci_conf_print_agp_datarate(rval, isagp3); 1194 } 1195 } 1196 1197 static const char * 1198 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1199 { 1200 1201 switch ((caps >> 6) & 7) { 1202 case 0: return "self-powered"; 1203 case 1: return "55 mA"; 1204 case 2: return "100 mA"; 1205 case 3: return "160 mA"; 1206 case 4: return "220 mA"; 1207 case 5: return "270 mA"; 1208 case 6: return "320 mA"; 1209 case 7: 1210 default: return "375 mA"; 1211 } 1212 } 1213 1214 static const char * 1215 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1216 { 1217 static const char unk[] = "unknown"; 1218 static const char *pmrev[8] = { 1219 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1220 }; 1221 if (val > 7) 1222 return unk; 1223 return pmrev[val]; 1224 } 1225 1226 static void 1227 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1228 { 1229 uint16_t caps, pmcsr; 1230 1231 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1232 pmcsr = regs[o2i(capoff + PCI_PMCSR)]; 1233 1234 printf("\n PCI Power Management Capabilities Register\n"); 1235 1236 printf(" Capabilities register: 0x%04x\n", caps); 1237 printf(" Version: %s\n", 1238 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1239 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1240 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1241 printf(" 3.3V auxiliary current: %s\n", 1242 pci_conf_print_pcipm_cap_aux(caps)); 1243 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1244 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1245 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1246 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1247 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1248 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1249 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1250 1251 printf(" Control/status register: 0x%08x\n", pmcsr); 1252 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1253 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1254 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1255 printf(" PME# assertion: %sabled\n", 1256 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1257 printf(" Data Select: %d\n", 1258 PCIREG_SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK)); 1259 printf(" Data Scale: %d\n", 1260 PCIREG_SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK)); 1261 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1262 printf(" Bridge Support Extensions register: 0x%02x\n", 1263 (pmcsr >> 16) & 0xff); 1264 onoff("B2/B3 support", pmcsr, PCI_PMCSR_B2B3_SUPPORT); 1265 onoff("Bus Power/Clock Control Enable", pmcsr, PCI_PMCSR_BPCC_EN); 1266 printf(" Data register: 0x%02x\n", 1267 PCIREG_SHIFTOUT(pmcsr, PCI_PMCSR_DATA)); 1268 } 1269 1270 /* XXX pci_conf_print_vpd_cap */ 1271 /* XXX pci_conf_print_slotid_cap */ 1272 1273 static void 1274 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1275 { 1276 uint32_t ctl, mmc, mme; 1277 1278 regs += o2i(capoff); 1279 ctl = *regs++; 1280 mmc = PCIREG_SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1281 mme = PCIREG_SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1282 1283 printf("\n PCI Message Signaled Interrupt\n"); 1284 1285 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1286 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1287 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1288 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1289 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1290 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1291 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1292 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1293 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP); 1294 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN); 1295 printf(" Message Address %sregister: 0x%08x\n", 1296 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1297 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1298 printf(" Message Address %sregister: 0x%08x\n", 1299 "(upper) ", *regs++); 1300 } 1301 printf(" Message Data register: "); 1302 if (ctl & PCI_MSI_CTL_EXTMDATA_CAP) 1303 printf("0x%08x\n", *regs); 1304 else 1305 printf("0x%04x\n", *regs & 0xffff); 1306 regs++; 1307 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1308 printf(" Vector Mask register: 0x%08x\n", *regs++); 1309 printf(" Vector Pending register: 0x%08x\n", *regs++); 1310 } 1311 } 1312 1313 /* XXX pci_conf_print_cpci_hostwap_cap */ 1314 1315 /* 1316 * For both command register and status register. 1317 * The argument "idx" is index number (0 to 7). 1318 */ 1319 static int 1320 pcix_split_trans(unsigned int idx) 1321 { 1322 static int table[8] = { 1323 1, 2, 3, 4, 8, 12, 16, 32 1324 }; 1325 1326 if (idx >= __arraycount(table)) 1327 return -1; 1328 return table[idx]; 1329 } 1330 1331 static void 1332 pci_conf_print_pcix_cap_2ndbusmode(int num) 1333 { 1334 const char *maxfreq, *maxperiod; 1335 1336 printf(" Mode: "); 1337 if (num <= 0x07) 1338 printf("PCI-X Mode 1\n"); 1339 else if (num <= 0x0b) 1340 printf("PCI-X 266 (Mode 2)\n"); 1341 else 1342 printf("PCI-X 533 (Mode 2)\n"); 1343 1344 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1345 switch (num & 0x03) { 1346 default: 1347 case 0: 1348 maxfreq = "N/A"; 1349 maxperiod = "N/A"; 1350 break; 1351 case 1: 1352 maxfreq = "66MHz"; 1353 maxperiod = "15ns"; 1354 break; 1355 case 2: 1356 maxfreq = "100MHz"; 1357 maxperiod = "10ns"; 1358 break; 1359 case 3: 1360 maxfreq = "133MHz"; 1361 maxperiod = "7.5ns"; 1362 break; 1363 } 1364 printf(" Max Clock Freq: %s\n", maxfreq); 1365 printf(" Min Clock Period: %s\n", maxperiod); 1366 } 1367 1368 static void 1369 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1370 { 1371 pcireg_t reg; 1372 int isbridge; 1373 int i; 1374 1375 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1376 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1377 printf("\n PCI-X %s Capabilities Register\n", 1378 isbridge ? "Bridge" : "Non-bridge"); 1379 1380 reg = regs[o2i(capoff)]; 1381 if (isbridge != 0) { 1382 printf(" Secondary status register: 0x%04x\n", 1383 (reg & 0xffff0000) >> 16); 1384 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1385 onoff("133MHz capable", reg, PCIX_STATUS_133); 1386 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1387 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1388 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1389 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1390 pci_conf_print_pcix_cap_2ndbusmode( 1391 PCIREG_SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1392 printf(" Version: 0x%x\n", 1393 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1394 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1395 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1396 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1397 } else { 1398 printf(" Command register: 0x%04x\n", 1399 (reg & 0xffff0000) >> 16); 1400 onoff("Data Parity Error Recovery", reg, 1401 PCIX_CMD_PERR_RECOVER); 1402 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1403 printf(" Maximum Burst Read Count: %u\n", 1404 PCIX_CMD_BYTECNT(reg)); 1405 printf(" Maximum Split Transactions: %d\n", 1406 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1407 >> PCIX_CMD_SPLTRANS_SHIFT)); 1408 } 1409 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1410 printf(" %sStatus register: 0x%08x\n", 1411 isbridge ? "Bridge " : "", reg); 1412 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1413 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1414 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1415 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1416 onoff("133MHz capable", reg, PCIX_STATUS_133); 1417 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1418 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1419 if (isbridge != 0) { 1420 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1421 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1422 } else { 1423 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1424 "bridge device", "simple device"); 1425 printf(" Designed max memory read byte count: %d\n", 1426 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1427 >> PCIX_STATUS_MAXB_SHIFT)); 1428 printf(" Designed max outstanding split transaction: %d\n", 1429 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1430 >> PCIX_STATUS_MAXST_SHIFT)); 1431 printf(" MAX cumulative Read Size: %u\n", 1432 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1433 onoff("Received split completion error", reg, 1434 PCIX_STATUS_SCERR); 1435 } 1436 onoff("266MHz capable", reg, PCIX_STATUS_266); 1437 onoff("533MHz capable", reg, PCIX_STATUS_533); 1438 1439 if (isbridge == 0) 1440 return; 1441 1442 /* Only for bridge */ 1443 for (i = 0; i < 2; i++) { 1444 reg = regs[o2i(capoff + PCIX_BRIDGE_UP_STCR + (4 * i))]; 1445 printf(" %s split transaction control register: 0x%08x\n", 1446 (i == 0) ? "Upstream" : "Downstream", reg); 1447 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1448 printf(" Commitment Limit: %d\n", 1449 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1450 } 1451 } 1452 1453 /* pci_conf_print_ht_slave_cap */ 1454 /* pci_conf_print_ht_host_cap */ 1455 /* pci_conf_print_ht_switch_cap */ 1456 /* pci_conf_print_ht_intr_cap */ 1457 /* pci_conf_print_ht_revid_cap */ 1458 /* pci_conf_print_ht_unitid_cap */ 1459 /* pci_conf_print_ht_extcnf_cap */ 1460 /* pci_conf_print_ht_addrmap_cap */ 1461 /* pci_conf_print_ht_msimap_cap */ 1462 1463 static void 1464 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1465 { 1466 pcireg_t val; 1467 uint32_t lo, hi; 1468 1469 /* 1470 * Print the rest of the command register bits. Others are 1471 * printed in pci_conf_print_ht_cap(). 1472 */ 1473 val = regs[o2i(capoff + PCI_HT_CMD)]; 1474 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1475 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1476 1477 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1478 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1479 printf(" Address Low register: 0x%08x\n", lo); 1480 printf(" Address high register: 0x%08x\n", hi); 1481 printf(" Address: 0x%016" PRIx64 "\n", 1482 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1483 } 1484 1485 /* pci_conf_print_ht_droute_cap */ 1486 /* pci_conf_print_ht_vcset_cap */ 1487 /* pci_conf_print_ht_retry_cap */ 1488 /* pci_conf_print_ht_x86enc_cap */ 1489 /* pci_conf_print_ht_gen3_cap */ 1490 /* pci_conf_print_ht_fle_cap */ 1491 /* pci_conf_print_ht_pm_cap */ 1492 /* pci_conf_print_ht_hnc_cap */ 1493 1494 static const struct ht_types { 1495 pcireg_t cap; 1496 const char *name; 1497 void (*printfunc)(const pcireg_t *, int); 1498 } ht_captab[] = { 1499 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1500 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1501 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1502 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1503 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1504 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1505 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1506 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1507 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1508 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1509 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1510 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1511 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1512 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1513 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1514 {PCI_HT_CAP_PM, "Power Management", NULL }, 1515 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1516 }; 1517 1518 static void 1519 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1520 { 1521 pcireg_t val, foundcap; 1522 unsigned int off; 1523 1524 val = regs[o2i(capoff + PCI_HT_CMD)]; 1525 1526 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1527 1528 printf(" Command register: 0x%04x\n", val >> 16); 1529 foundcap = PCI_HT_CAP(val); 1530 for (off = 0; off < __arraycount(ht_captab); off++) { 1531 if (ht_captab[off].cap == foundcap) 1532 break; 1533 } 1534 printf(" Capability Type: 0x%02x ", foundcap); 1535 if (off >= __arraycount(ht_captab)) { 1536 printf("(unknown)\n"); 1537 return; 1538 } 1539 printf("(%s)\n", ht_captab[off].name); 1540 if (ht_captab[off].printfunc != NULL) 1541 ht_captab[off].printfunc(regs, capoff); 1542 } 1543 1544 static void 1545 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1546 { 1547 uint16_t caps; 1548 1549 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1550 1551 printf("\n PCI Vendor Specific Capabilities Register\n"); 1552 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1553 } 1554 1555 static void 1556 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1557 { 1558 pcireg_t val; 1559 1560 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1561 1562 printf("\n Debugport Capability Register\n"); 1563 printf(" Debug base Register: 0x%04x\n", 1564 val >> PCI_DEBUG_BASER_SHIFT); 1565 printf(" port offset: 0x%04x\n", 1566 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1567 printf(" BAR number: %u\n", 1568 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1569 } 1570 1571 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1572 /* XXX pci_conf_print_hotplug_cap */ 1573 1574 static void 1575 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1576 { 1577 pcireg_t reg; 1578 1579 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1580 1581 printf("\n Subsystem ID Capability Register\n"); 1582 printf(" Subsystem ID: 0x%08x\n", reg); 1583 } 1584 1585 /* XXX pci_conf_print_agp8_cap */ 1586 static void 1587 pci_conf_print_secure_cap(const pcireg_t *regs, int capoff) 1588 { 1589 pcireg_t reg, reg2, val; 1590 bool havemisc1; 1591 1592 printf("\n Secure Capability Register\n"); 1593 reg = regs[o2i(capoff + PCI_SECURE_CAP)]; 1594 printf(" Capability Register: 0x%04x\n", reg >> 16); 1595 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_CAP_TYPE); 1596 printf(" Capability block type: "); 1597 /* I know IOMMU Only */ 1598 if (val == PCI_SECURE_CAP_TYPE_IOMMU) 1599 printf("IOMMU\n"); 1600 else { 1601 printf("0x%x(unknown)\n", val); 1602 return; 1603 } 1604 1605 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_CAP_REV); 1606 printf(" Capability revision: 0x%02x ", val); 1607 if (val == PCI_SECURE_CAP_REV_IOMMU) 1608 printf("(IOMMU)\n"); 1609 else { 1610 printf("(unknown)\n"); 1611 return; 1612 } 1613 onoff("IOTLB support", reg, PCI_SECURE_CAP_IOTLBSUP); 1614 onoff("HyperTransport tunnel translation support", reg, 1615 PCI_SECURE_CAP_HTTUNNEL); 1616 onoff("Not present table entries cached", reg, PCI_SECURE_CAP_NPCACHE); 1617 onoff("IOMMU Extended Feature Register support", reg, 1618 PCI_SECURE_CAP_EFRSUP); 1619 onoff("IOMMU Miscellaneous Information Register 1", reg, 1620 PCI_SECURE_CAP_EXT); 1621 havemisc1 = reg & PCI_SECURE_CAP_EXT; 1622 1623 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_BAL)]; 1624 printf(" Base Address Low Register: 0x%08x\n", reg); 1625 onoff("Enable", reg, PCI_SECURE_IOMMU_BAL_EN); 1626 reg2 = regs[o2i(capoff + PCI_SECURE_IOMMU_BAH)]; 1627 printf(" Base Address High Register: 0x%08x\n", reg2); 1628 printf(" Base Address: 0x%016" PRIx64 "\n", 1629 ((uint64_t)reg2 << 32) 1630 | (reg & (PCI_SECURE_IOMMU_BAL_H | PCI_SECURE_IOMMU_BAL_L))); 1631 1632 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_RANGE)]; 1633 printf(" IOMMU Range Register: 0x%08x\n", reg); 1634 printf(" HyperTransport UnitID: 0x%02x\n", 1635 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_UNITID)); 1636 onoff("Range valid", reg, PCI_SECURE_IOMMU_RANGE_RNGVALID); 1637 printf(" Device range bus number: 0x%02x\n", 1638 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_BUSNUM)); 1639 printf(" First device: 0x%04x\n", 1640 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_FIRSTDEV)); 1641 printf(" Last device: 0x%04x\n", 1642 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_LASTDEV)); 1643 1644 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC0)]; 1645 printf(" Miscellaneous Information Register 0: 0x%08x\n", reg); 1646 printf(" MSI Message number: 0x%02x\n", 1647 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MSINUM)); 1648 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_GVASIZE); 1649 printf(" Guest Virtual Address size: "); 1650 if (val == PCI_SECURE_IOMMU_MISC0_GVASIZE_48B) 1651 printf("48bits\n"); 1652 else 1653 printf("0x%x(unknown)\n", val); 1654 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_PASIZE); 1655 printf(" Physical Address size: %dbits\n", val); 1656 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_VASIZE); 1657 printf(" Virtual Address size: %dbits\n", val); 1658 onoff("ATS response address range reserved", reg, 1659 PCI_SECURE_IOMMU_MISC0_ATSRESV); 1660 printf(" Peripheral Page Request MSI Message number: 0x%02x\n", 1661 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MISNPPR)); 1662 1663 if (!havemisc1) 1664 return; 1665 1666 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC1)]; 1667 printf(" Miscellaneous Information Register 1: 0x%08x\n", reg); 1668 printf(" MSI Message number (GA): 0x%02x\n", 1669 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC1_MSINUM)); 1670 } 1671 1672 static void 1673 pci_print_pcie_L0s_latency(uint32_t val) 1674 { 1675 1676 switch (val) { 1677 case 0x0: 1678 printf("Less than 64ns\n"); 1679 break; 1680 case 0x1: 1681 case 0x2: 1682 case 0x3: 1683 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1684 break; 1685 case 0x4: 1686 printf("512ns to less than 1us\n"); 1687 break; 1688 case 0x5: 1689 printf("1us to less than 2us\n"); 1690 break; 1691 case 0x6: 1692 printf("2us - 4us\n"); 1693 break; 1694 case 0x7: 1695 printf("More than 4us\n"); 1696 break; 1697 } 1698 } 1699 1700 static void 1701 pci_print_pcie_L1_latency(uint32_t val) 1702 { 1703 1704 switch (val) { 1705 case 0x0: 1706 printf("Less than 1us\n"); 1707 break; 1708 case 0x6: 1709 printf("32us - 64us\n"); 1710 break; 1711 case 0x7: 1712 printf("More than 64us\n"); 1713 break; 1714 default: 1715 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1716 break; 1717 } 1718 } 1719 1720 static void 1721 pci_print_pcie_compl_timeout(uint32_t val) 1722 { 1723 1724 switch (val) { 1725 case 0x0: 1726 printf("50us to 50ms\n"); 1727 break; 1728 case 0x5: 1729 printf("16ms to 55ms\n"); 1730 break; 1731 case 0x6: 1732 printf("65ms to 210ms\n"); 1733 break; 1734 case 0x9: 1735 printf("260ms to 900ms\n"); 1736 break; 1737 case 0xa: 1738 printf("1s to 3.5s\n"); 1739 break; 1740 default: 1741 printf("unknown %u value\n", val); 1742 break; 1743 } 1744 } 1745 1746 static const char * const pcie_linkspeeds[] = {"2.5", "5.0", "8.0", "16.0"}; 1747 1748 /* 1749 * Print link speed. This function is used for the following register bits: 1750 * Maximum Link Speed in LCAP 1751 * Current Link Speed in LCSR 1752 * Target Link Speed in LCSR2 1753 * All of above bitfield's values start from 1. 1754 * For LCSR2, 0 is allowed for a device which supports 2.5GT/s only (and 1755 * this check also works for devices which compliant to versions of the base 1756 * specification prior to 3.0. 1757 */ 1758 static void 1759 pci_print_pcie_linkspeed(int regnum, pcireg_t val) 1760 { 1761 1762 if ((regnum == PCIE_LCSR2) && (val == 0)) 1763 printf("2.5GT/s\n"); 1764 else if ((val < 1) || (val > __arraycount(pcie_linkspeeds))) 1765 printf("unknown value (%u)\n", val); 1766 else 1767 printf("%sGT/s\n", pcie_linkspeeds[val - 1]); 1768 } 1769 1770 /* 1771 * Print link speed "vector". 1772 * This function is used for the following register bits: 1773 * Supported Link Speeds Vector in LCAP2 1774 * Lower SKP OS Generation Supported Speed Vector in LCAP2 1775 * Lower SKP OS Reception Supported Speed Vector in LCAP2 1776 * Enable Lower SKP OS Generation Vector in LCTL3 1777 * All of above bitfield's values start from 0. 1778 */ 1779 static void 1780 pci_print_pcie_linkspeedvector(pcireg_t val) 1781 { 1782 unsigned int i; 1783 1784 /* Start from 0 */ 1785 for (i = 0; i < 16; i++) 1786 if (((val >> i) & 0x01) != 0) { 1787 if (i >= __arraycount(pcie_linkspeeds)) 1788 printf(" unknown vector (0x%x)", 1 << i); 1789 else 1790 printf(" %sGT/s", pcie_linkspeeds[i]); 1791 } 1792 } 1793 1794 static void 1795 pci_print_pcie_link_deemphasis(pcireg_t val) 1796 { 1797 switch (val) { 1798 case 0: 1799 printf("-6dB"); 1800 break; 1801 case 1: 1802 printf("-3.5dB"); 1803 break; 1804 default: 1805 printf("(reserved value)"); 1806 } 1807 } 1808 1809 static void 1810 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1811 { 1812 pcireg_t reg; /* for each register */ 1813 pcireg_t val; /* for each bitfield */ 1814 bool check_slot = false; 1815 unsigned int pcie_devtype; 1816 bool check_upstreamport = false; 1817 unsigned int pciever; 1818 unsigned int i; 1819 1820 printf("\n PCI Express Capabilities Register\n"); 1821 /* Capability Register */ 1822 reg = regs[o2i(capoff)]; 1823 printf(" Capability register: 0x%04x\n", reg >> 16); 1824 pciever = (unsigned int)(PCIE_XCAP_VER(reg)); 1825 printf(" Capability version: %u\n", pciever); 1826 printf(" Device type: "); 1827 pcie_devtype = PCIE_XCAP_TYPE(reg); 1828 switch (pcie_devtype) { 1829 case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */ 1830 printf("PCI Express Endpoint device\n"); 1831 check_upstreamport = true; 1832 break; 1833 case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */ 1834 printf("Legacy PCI Express Endpoint device\n"); 1835 check_upstreamport = true; 1836 break; 1837 case PCIE_XCAP_TYPE_ROOT: /* 0x4 */ 1838 printf("Root Port of PCI Express Root Complex\n"); 1839 check_slot = true; 1840 break; 1841 case PCIE_XCAP_TYPE_UP: /* 0x5 */ 1842 printf("Upstream Port of PCI Express Switch\n"); 1843 check_upstreamport = true; 1844 break; 1845 case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ 1846 printf("Downstream Port of PCI Express Switch\n"); 1847 check_slot = true; 1848 break; 1849 case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ 1850 printf("PCI Express to PCI/PCI-X Bridge\n"); 1851 check_upstreamport = true; 1852 break; 1853 case PCIE_XCAP_TYPE_PCI2PCIE: /* 0x8 */ 1854 printf("PCI/PCI-X to PCI Express Bridge\n"); 1855 /* Upstream port is not PCIe */ 1856 check_slot = true; 1857 break; 1858 case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */ 1859 printf("Root Complex Integrated Endpoint\n"); 1860 break; 1861 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */ 1862 printf("Root Complex Event Collector\n"); 1863 break; 1864 default: 1865 printf("unknown\n"); 1866 break; 1867 } 1868 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1869 printf(" Interrupt Message Number: 0x%02x\n", 1870 PCIREG_SHIFTOUT(reg, PCIE_XCAP_IRQ)); 1871 1872 /* Device Capability Register */ 1873 reg = regs[o2i(capoff + PCIE_DCAP)]; 1874 printf(" Device Capabilities Register: 0x%08x\n", reg); 1875 printf(" Max Payload Size Supported: %u bytes max\n", 1876 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1877 printf(" Phantom Functions Supported: "); 1878 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) { 1879 case 0x0: 1880 printf("not available\n"); 1881 break; 1882 case 0x1: 1883 printf("MSB\n"); 1884 break; 1885 case 0x2: 1886 printf("two MSB\n"); 1887 break; 1888 case 0x3: 1889 printf("All three bits\n"); 1890 break; 1891 } 1892 printf(" Extended Tag Field Supported: %dbit\n", 1893 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1894 printf(" Endpoint L0 Acceptable Latency: "); 1895 pci_print_pcie_L0s_latency(PCIREG_SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY)); 1896 printf(" Endpoint L1 Acceptable Latency: "); 1897 pci_print_pcie_L1_latency(PCIREG_SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY)); 1898 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1899 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1900 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1901 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1902 if (check_upstreamport) { 1903 printf(" Captured Slot Power Limit: "); 1904 pci_conf_print_pcie_power( 1905 PCIREG_SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL), 1906 PCIREG_SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE)); 1907 } 1908 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1909 1910 /* Device Control Register */ 1911 reg = regs[o2i(capoff + PCIE_DCSR)]; 1912 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1913 onoff("Correctable Error Reporting Enable", reg, 1914 PCIE_DCSR_ENA_COR_ERR); 1915 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1916 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1917 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1918 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1919 printf(" Max Payload Size: %d byte\n", 1920 128 << PCIREG_SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD)); 1921 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1922 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1923 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1924 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1925 printf(" Max Read Request Size: %d byte\n", 1926 128 << PCIREG_SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ)); 1927 if (pcie_devtype == PCIE_XCAP_TYPE_PCIE2PCI) 1928 onoff("Bridge Config Retry Enable", reg, 1929 PCIE_DCSR_BRDG_CFG_RETRY); 1930 1931 /* Device Status Register */ 1932 reg = regs[o2i(capoff + PCIE_DCSR)]; 1933 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1934 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1935 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1936 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1937 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1938 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1939 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1940 onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD); 1941 1942 if (PCIE_HAS_LINKREGS(pcie_devtype)) { 1943 /* Link Capability Register */ 1944 reg = regs[o2i(capoff + PCIE_LCAP)]; 1945 printf(" Link Capabilities Register: 0x%08x\n", reg); 1946 printf(" Maximum Link Speed: "); 1947 pci_print_pcie_linkspeed(PCIE_LCAP, reg & PCIE_LCAP_MAX_SPEED); 1948 printf(" Maximum Link Width: x%u lanes\n", 1949 PCIREG_SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH)); 1950 printf(" Active State PM Support: "); 1951 switch (PCIREG_SHIFTOUT(reg, PCIE_LCAP_ASPM)) { 1952 case 0x0: 1953 printf("No ASPM support\n"); 1954 break; 1955 case 0x1: 1956 printf("L0s supported\n"); 1957 break; 1958 case 0x2: 1959 printf("L1 supported\n"); 1960 break; 1961 case 0x3: 1962 printf("L0s and L1 supported\n"); 1963 break; 1964 } 1965 printf(" L0 Exit Latency: "); 1966 pci_print_pcie_L0s_latency(PCIREG_SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT)); 1967 printf(" L1 Exit Latency: "); 1968 pci_print_pcie_L1_latency(PCIREG_SHIFTOUT(reg, PCIE_LCAP_L1_EXIT)); 1969 printf(" Port Number: %u\n", 1970 PCIREG_SHIFTOUT(reg, PCIE_LCAP_PORT)); 1971 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1972 onoff("Surprise Down Error Report", reg, 1973 PCIE_LCAP_SURPRISE_DOWN); 1974 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 1975 onoff("Link BW Notification Capable", reg, 1976 PCIE_LCAP_LINK_BW_NOTIFY); 1977 onoff("ASPM Optionally Compliance", reg, 1978 PCIE_LCAP_ASPM_COMPLIANCE); 1979 1980 /* Link Control Register */ 1981 reg = regs[o2i(capoff + PCIE_LCSR)]; 1982 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1983 printf(" Active State PM Control: "); 1984 switch (reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S)) { 1985 case 0: 1986 printf("disabled\n"); 1987 break; 1988 case 1: 1989 printf("L0s Entry Enabled\n"); 1990 break; 1991 case 2: 1992 printf("L1 Entry Enabled\n"); 1993 break; 1994 case 3: 1995 printf("L0s and L1 Entry Enabled\n"); 1996 break; 1997 } 1998 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 1999 "128bytes", "64bytes"); 2000 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 2001 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 2002 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 2003 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 2004 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 2005 onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD); 2006 onoff("Link Bandwidth Management Interrupt Enable", reg, 2007 PCIE_LCSR_LBMIE); 2008 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 2009 PCIE_LCSR_LABIE); 2010 printf(" DRS Signaling Control: "); 2011 switch (PCIREG_SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) { 2012 case 0: 2013 printf("not reported\n"); 2014 break; 2015 case 1: 2016 printf("Interrupt Enabled\n"); 2017 break; 2018 case 2: 2019 printf("DRS to FRS Signaling Enabled\n"); 2020 break; 2021 default: 2022 printf("reserved\n"); 2023 break; 2024 } 2025 2026 /* Link Status Register */ 2027 reg = regs[o2i(capoff + PCIE_LCSR)]; 2028 printf(" Link Status Register: 0x%04x\n", reg >> 16); 2029 printf(" Negotiated Link Speed: "); 2030 pci_print_pcie_linkspeed(PCIE_LCSR, 2031 PCIREG_SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 2032 printf(" Negotiated Link Width: x%u lanes\n", 2033 PCIREG_SHIFTOUT(reg, PCIE_LCSR_NLW)); 2034 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 2035 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 2036 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 2037 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 2038 onoff("Link Bandwidth Management Status", reg, 2039 PCIE_LCSR_LINK_BW_MGMT); 2040 onoff("Link Autonomous Bandwidth Status", reg, 2041 PCIE_LCSR_LINK_AUTO_BW); 2042 } 2043 2044 if (check_slot == true) { 2045 pcireg_t slcap; 2046 2047 /* Slot Capability Register */ 2048 slcap = reg = regs[o2i(capoff + PCIE_SLCAP)]; 2049 printf(" Slot Capability Register: 0x%08x\n", reg); 2050 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 2051 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 2052 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 2053 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 2054 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 2055 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 2056 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 2057 printf(" Slot Power Limit Value: "); 2058 pci_conf_print_pcie_power(PCIREG_SHIFTOUT(reg, PCIE_SLCAP_SPLV), 2059 PCIREG_SHIFTOUT(reg, PCIE_SLCAP_SPLS)); 2060 onoff("Electromechanical Interlock Present", reg, 2061 PCIE_SLCAP_EIP); 2062 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 2063 printf(" Physical Slot Number: %d\n", 2064 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 2065 2066 /* Slot Control Register */ 2067 reg = regs[o2i(capoff + PCIE_SLCSR)]; 2068 printf(" Slot Control Register: 0x%04x\n", reg & 0xffff); 2069 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 2070 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 2071 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 2072 onoff("Presence Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 2073 onoff("Command Completed Interrupt Enabled", reg, 2074 PCIE_SLCSR_CCE); 2075 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 2076 /* 2077 * For Attention Indicator Control and Power Indicator Control, 2078 * it's allowed to be a read only value 0 if corresponding 2079 * capability register bit is 0. 2080 */ 2081 if (slcap & PCIE_SLCAP_AIP) { 2082 printf(" Attention Indicator Control: "); 2083 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 2084 case 0x0: 2085 printf("reserved\n"); 2086 break; 2087 case PCIE_SLCSR_IND_ON: 2088 printf("on\n"); 2089 break; 2090 case PCIE_SLCSR_IND_BLINK: 2091 printf("blink\n"); 2092 break; 2093 case PCIE_SLCSR_IND_OFF: 2094 printf("off\n"); 2095 break; 2096 } 2097 } 2098 if (slcap & PCIE_SLCAP_PIP) { 2099 printf(" Power Indicator Control: "); 2100 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 2101 case 0x0: 2102 printf("reserved\n"); 2103 break; 2104 case PCIE_SLCSR_IND_ON: 2105 printf("on\n"); 2106 break; 2107 case PCIE_SLCSR_IND_BLINK: 2108 printf("blink\n"); 2109 break; 2110 case PCIE_SLCSR_IND_OFF: 2111 printf("off\n"); 2112 break; 2113 } 2114 } 2115 printf(" Power Controller Control: Power %s\n", 2116 reg & PCIE_SLCSR_PCC ? "off" : "on"); 2117 onoff("Electromechanical Interlock Control", 2118 reg, PCIE_SLCSR_EIC); 2119 onoff("Data Link Layer State Changed Enable", reg, 2120 PCIE_SLCSR_DLLSCE); 2121 onoff("Auto Slot Power Limit Disable", reg, 2122 PCIE_SLCSR_AUTOSPLDIS); 2123 2124 /* Slot Status Register */ 2125 printf(" Slot Status Register: 0x%04x\n", reg >> 16); 2126 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 2127 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 2128 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 2129 onoff("Presence Detect Changed", reg, PCIE_SLCSR_PDC); 2130 onoff("Command Completed", reg, PCIE_SLCSR_CC); 2131 onoff("MRL Open", reg, PCIE_SLCSR_MS); 2132 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 2133 onoff("Electromechanical Interlock engaged", reg, 2134 PCIE_SLCSR_EIS); 2135 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 2136 } 2137 2138 if (PCIE_HAS_ROOTREGS(pcie_devtype)) { 2139 /* Root Control Register */ 2140 reg = regs[o2i(capoff + PCIE_RCR)]; 2141 printf(" Root Control Register: 0x%04x\n", reg & 0xffff); 2142 onoff("SERR on Correctable Error Enable", reg, 2143 PCIE_RCR_SERR_CER); 2144 onoff("SERR on Non-Fatal Error Enable", reg, 2145 PCIE_RCR_SERR_NFER); 2146 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 2147 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 2148 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 2149 2150 /* Root Capability Register */ 2151 printf(" Root Capability Register: 0x%04x\n", 2152 reg >> 16); 2153 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 2154 2155 /* Root Status Register */ 2156 reg = regs[o2i(capoff + PCIE_RSR)]; 2157 printf(" Root Status Register: 0x%08x\n", reg); 2158 printf(" PME Requester ID: 0x%04x\n", 2159 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 2160 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 2161 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 2162 } 2163 2164 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2165 if (pciever < 2) 2166 return; 2167 2168 /* Device Capabilities 2 */ 2169 reg = regs[o2i(capoff + PCIE_DCAP2)]; 2170 printf(" Device Capabilities 2: 0x%08x\n", reg); 2171 printf(" Completion Timeout Ranges Supported: "); 2172 val = reg & PCIE_DCAP2_COMPT_RANGE; 2173 switch (val) { 2174 case 0: 2175 printf("not supported\n"); 2176 break; 2177 default: 2178 for (i = 0; i <= 3; i++) { 2179 if (((val >> i) & 0x01) != 0) 2180 printf("%c", 'A' + i); 2181 } 2182 printf("\n"); 2183 } 2184 onoff("Completion Timeout Disable Supported", reg, 2185 PCIE_DCAP2_COMPT_DIS); 2186 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 2187 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 2188 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 2189 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 2190 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 2191 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 2192 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 2193 printf(" TPH Completer Supported: "); 2194 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) { 2195 case 0: 2196 printf("Not supported\n"); 2197 break; 2198 case 1: 2199 printf("TPH\n"); 2200 break; 2201 case 3: 2202 printf("TPH and Extended TPH\n"); 2203 break; 2204 default: 2205 printf("(reserved value)\n"); 2206 break; 2207 } 2208 printf(" LN System CLS: "); 2209 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 2210 case 0x0: 2211 printf("Not supported or not in effect\n"); 2212 break; 2213 case 0x1: 2214 printf("64byte cachelines in effect\n"); 2215 break; 2216 case 0x2: 2217 printf("128byte cachelines in effect\n"); 2218 break; 2219 case 0x3: 2220 printf("Reserved\n"); 2221 break; 2222 } 2223 onoff("10-bit Tag Completer Supported", reg, PCIE_DCAP2_TBT_COMP); 2224 onoff("10-bit Tag Requester Supported", reg, PCIE_DCAP2_TBT_REQ); 2225 printf(" OBFF Supported: "); 2226 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_OBFF)) { 2227 case 0x0: 2228 printf("Not supported\n"); 2229 break; 2230 case 0x1: 2231 printf("Message only\n"); 2232 break; 2233 case 0x2: 2234 printf("WAKE# only\n"); 2235 break; 2236 case 0x3: 2237 printf("Both\n"); 2238 break; 2239 } 2240 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 2241 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 2242 val = PCIREG_SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP); 2243 printf(" Max End-End TLP Prefixes: %u\n", (val == 0) ? 4 : val); 2244 printf(" Emergency Power Reduction Supported: "); 2245 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) { 2246 case 0x0: 2247 printf("Not supported\n"); 2248 break; 2249 case 0x1: 2250 printf("Device Specific mechanism\n"); 2251 break; 2252 case 0x2: 2253 printf("Form Factor spec or Device Specific mechanism\n"); 2254 break; 2255 case 0x3: 2256 printf("Reserved\n"); 2257 break; 2258 } 2259 onoff("Emergency Power Reduction Initialization Required", reg, 2260 PCIE_DCAP2_EMGPWRRED_INI); 2261 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 2262 2263 /* Device Control 2 */ 2264 reg = regs[o2i(capoff + PCIE_DCSR2)]; 2265 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 2266 printf(" Completion Timeout Value: "); 2267 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 2268 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 2269 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 2270 onoff("AtomicOp Requester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 2271 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 2272 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 2273 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 2274 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 2275 onoff("Emergency Power Reduction Request", reg, 2276 PCIE_DCSR2_EMGPWRRED_REQ); 2277 onoff("10-bit Tag Requester Enabled", reg, PCIE_DCSR2_TBT_REQ); 2278 printf(" OBFF: "); 2279 switch (PCIREG_SHIFTOUT(reg, PCIE_DCSR2_OBFF_EN)) { 2280 case 0x0: 2281 printf("Disabled\n"); 2282 break; 2283 case 0x1: 2284 printf("Enabled with Message Signaling Variation A\n"); 2285 break; 2286 case 0x2: 2287 printf("Enabled with Message Signaling Variation B\n"); 2288 break; 2289 case 0x3: 2290 printf("Enabled using WAKE# signaling\n"); 2291 break; 2292 } 2293 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 2294 2295 if (PCIE_HAS_LINKREGS(pcie_devtype)) { 2296 bool drs_supported = false; 2297 2298 /* Link Capability 2 */ 2299 reg = regs[o2i(capoff + PCIE_LCAP2)]; 2300 /* If the vector is 0, LCAP2 is not implemented */ 2301 if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) { 2302 printf(" Link Capabilities 2: 0x%08x\n", reg); 2303 printf(" Supported Link Speeds Vector:"); 2304 pci_print_pcie_linkspeedvector( 2305 PCIREG_SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 2306 printf("\n"); 2307 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 2308 printf(" " 2309 "Lower SKP OS Generation Supported Speed Vector:"); 2310 pci_print_pcie_linkspeedvector( 2311 PCIREG_SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 2312 printf("\n"); 2313 printf(" " 2314 "Lower SKP OS Reception Supported Speed Vector:"); 2315 pci_print_pcie_linkspeedvector( 2316 PCIREG_SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 2317 printf("\n"); 2318 onoff("Retimer Presence Detect Supported", reg, 2319 PCIE_LCAP2_RETIMERPD); 2320 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 2321 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 2322 } 2323 2324 /* Link Control 2 */ 2325 reg = regs[o2i(capoff + PCIE_LCSR2)]; 2326 /* If the vector is 0, LCAP2 is not implemented */ 2327 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 2328 printf(" Target Link Speed: "); 2329 pci_print_pcie_linkspeed(PCIE_LCSR2, 2330 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_TGT_LSPEED)); 2331 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 2332 onoff("HW Autonomous Speed Disabled", reg, 2333 PCIE_LCSR2_HW_AS_DIS); 2334 printf(" Selectable De-emphasis: "); 2335 pci_print_pcie_link_deemphasis( 2336 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP)); 2337 printf("\n"); 2338 printf(" Transmit Margin: %u\n", 2339 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_TX_MARGIN)); 2340 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 2341 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 2342 printf(" Compliance Present/De-emphasis: "); 2343 pci_print_pcie_link_deemphasis( 2344 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP)); 2345 printf("\n"); 2346 2347 /* Link Status 2 */ 2348 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 2349 printf(" Current De-emphasis Level: "); 2350 pci_print_pcie_link_deemphasis( 2351 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL)); 2352 printf("\n"); 2353 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 2354 onoff("Equalization Phase 1 Successful", reg, 2355 PCIE_LCSR2_EQP1_SUC); 2356 onoff("Equalization Phase 2 Successful", reg, 2357 PCIE_LCSR2_EQP2_SUC); 2358 onoff("Equalization Phase 3 Successful", reg, 2359 PCIE_LCSR2_EQP3_SUC); 2360 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 2361 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 2362 if (drs_supported) { 2363 printf(" Downstream Component Presence: "); 2364 switch (PCIREG_SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 2365 case PCIE_DSCOMPN_DOWN_NOTDETERM: 2366 printf("Link Down - Presence Not" 2367 " Determined\n"); 2368 break; 2369 case PCIE_DSCOMPN_DOWN_NOTPRES: 2370 printf("Link Down - Component Not Present\n"); 2371 break; 2372 case PCIE_DSCOMPN_DOWN_PRES: 2373 printf("Link Down - Component Present\n"); 2374 break; 2375 case PCIE_DSCOMPN_UP_PRES: 2376 printf("Link Up - Component Present\n"); 2377 break; 2378 case PCIE_DSCOMPN_UP_PRES_DRS: 2379 printf("Link Up - Component Present and DRS" 2380 " received\n"); 2381 break; 2382 default: 2383 printf("reserved\n"); 2384 break; 2385 } 2386 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 2387 } 2388 } 2389 2390 /* Slot Capability 2 */ 2391 /* Slot Control 2 */ 2392 /* Slot Status 2 */ 2393 } 2394 2395 static void 2396 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 2397 { 2398 pcireg_t reg; 2399 2400 printf("\n MSI-X Capability Register\n"); 2401 2402 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2403 printf(" Message Control register: 0x%04x\n", 2404 (reg >> 16) & 0xff); 2405 printf(" Table Size: %d\n", PCI_MSIX_CTL_TBLSIZE(reg)); 2406 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 2407 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 2408 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 2409 printf(" Table offset register: 0x%08x\n", reg); 2410 printf(" Table offset: 0x%08x\n", 2411 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 2412 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 2413 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 2414 printf(" Pending bit array register: 0x%08x\n", reg); 2415 printf(" Pending bit array offset: 0x%08x\n", 2416 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2417 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2418 } 2419 2420 static void 2421 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2422 { 2423 pcireg_t reg; 2424 2425 printf("\n Serial ATA Capability Register\n"); 2426 2427 reg = regs[o2i(capoff + PCI_SATA_REV)]; 2428 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2429 printf(" Revision: %u.%u\n", 2430 PCIREG_SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2431 PCIREG_SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2432 2433 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2434 2435 printf(" BAR Register: 0x%08x\n", reg); 2436 printf(" Register location: "); 2437 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2438 printf("in config space\n"); 2439 else { 2440 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2441 printf(" BAR offset: 0x%08x\n", 2442 PCIREG_SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2443 } 2444 } 2445 2446 static void 2447 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2448 { 2449 pcireg_t reg; 2450 2451 printf("\n Advanced Features Capability Register\n"); 2452 2453 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2454 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2455 printf(" AF Structure Length: 0x%02x\n", 2456 PCIREG_SHIFTOUT(reg, PCI_AF_LENGTH)); 2457 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2458 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2459 reg = regs[o2i(capoff + PCI_AFCSR)]; 2460 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2461 /* 2462 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2463 * and it's always 0 on read 2464 */ 2465 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2466 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2467 } 2468 2469 static void 2470 pci_conf_print_ea_cap_prop(unsigned int prop) 2471 { 2472 2473 switch (prop) { 2474 case PCI_EA_PROP_MEM_NONPREF: 2475 printf("Memory Space, Non-Prefetchable\n"); 2476 break; 2477 case PCI_EA_PROP_MEM_PREF: 2478 printf("Memory Space, Prefetchable\n"); 2479 break; 2480 case PCI_EA_PROP_IO: 2481 printf("I/O Space\n"); 2482 break; 2483 case PCI_EA_PROP_VF_MEM_NONPREF: 2484 printf("Resorce for VF use, Memory Space, Non-Prefetchable\n"); 2485 break; 2486 case PCI_EA_PROP_VF_MEM_PREF: 2487 printf("Resorce for VF use, Memory Space, Prefetch\n"); 2488 break; 2489 case PCI_EA_PROP_BB_MEM_NONPREF: 2490 printf("Behind the Bridge, Memory Space, Non-Pref\n"); 2491 break; 2492 case PCI_EA_PROP_BB_MEM_PREF: 2493 printf("Behind the Bridge, Memory Space. Prefetchable\n"); 2494 break; 2495 case PCI_EA_PROP_BB_IO: 2496 printf("Behind Bridge, I/O Space\n"); 2497 break; 2498 case PCI_EA_PROP_MEM_UNAVAIL: 2499 printf("Memory Space Unavailable\n"); 2500 break; 2501 case PCI_EA_PROP_IO_UNAVAIL: 2502 printf("IO Space Unavailable\n"); 2503 break; 2504 case PCI_EA_PROP_UNAVAIL: 2505 printf("Entry Unavailable for use\n"); 2506 break; 2507 default: 2508 printf("Reserved\n"); 2509 break; 2510 } 2511 } 2512 2513 static void 2514 pci_conf_print_ea_cap(const pcireg_t *regs, int capoff) 2515 { 2516 pcireg_t reg, reg2; 2517 unsigned int entries, entoff, i; 2518 2519 printf("\n Enhanced Allocation Capability Register\n"); 2520 2521 reg = regs[o2i(capoff + PCI_EA_CAP1)]; 2522 printf(" EA Num Entries register: 0x%04x\n", reg >> 16); 2523 entries = PCIREG_SHIFTOUT(reg, PCI_EA_CAP1_NUMENTRIES); 2524 printf(" EA Num Entries: %u\n", entries); 2525 2526 /* Type 1 only */ 2527 if (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) == PCI_HDRTYPE_PPB) { 2528 reg = regs[o2i(capoff + PCI_EA_CAP2)]; 2529 printf(" EA Capability Second register: 0x%08x\n", reg); 2530 printf(" Fixed Secondary Bus Number: %hhu\n", 2531 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_EA_CAP2_SECONDARY)); 2532 printf(" Fixed Subordinate Bus Number: %hhu\n", 2533 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_EA_CAP2_SUBORDINATE)); 2534 entoff = capoff + 8; 2535 } else 2536 entoff = capoff + 4; 2537 2538 for (i = 0; i < entries; i++) { 2539 uint64_t base, offset; 2540 bool baseis64, offsetis64; 2541 unsigned int bei, entry_size; 2542 2543 printf(" Entry %u:\n", i); 2544 /* The first DW */ 2545 reg = regs[o2i(entoff)]; 2546 printf(" The first register: 0x%08x\n", reg); 2547 entry_size = PCIREG_SHIFTOUT(reg, PCI_EA_ES); 2548 printf(" Entry size: %u\n", entry_size); 2549 printf(" BAR Equivalent Indicator: "); 2550 bei = PCIREG_SHIFTOUT(reg, PCI_EA_BEI); 2551 switch (bei) { 2552 case PCI_EA_BEI_BAR0: 2553 case PCI_EA_BEI_BAR1: 2554 case PCI_EA_BEI_BAR2: 2555 case PCI_EA_BEI_BAR3: 2556 case PCI_EA_BEI_BAR4: 2557 case PCI_EA_BEI_BAR5: 2558 printf("BAR %u\n", bei - PCI_EA_BEI_BAR0); 2559 break; 2560 case PCI_EA_BEI_BEHIND: 2561 printf("Behind the function\n"); 2562 break; 2563 case PCI_EA_BEI_NOTIND: 2564 printf("Not Indicated\n"); 2565 break; 2566 case PCI_EA_BEI_EXPROM: 2567 printf("Expansion ROM\n"); 2568 break; 2569 case PCI_EA_BEI_VFBAR0: 2570 case PCI_EA_BEI_VFBAR1: 2571 case PCI_EA_BEI_VFBAR2: 2572 case PCI_EA_BEI_VFBAR3: 2573 case PCI_EA_BEI_VFBAR4: 2574 case PCI_EA_BEI_VFBAR5: 2575 printf("VF BAR %u\n", bei - PCI_EA_BEI_VFBAR0); 2576 break; 2577 case PCI_EA_BEI_RESERVED: 2578 default: 2579 printf("Reserved\n"); 2580 break; 2581 } 2582 2583 printf(" Primary Properties: "); 2584 pci_conf_print_ea_cap_prop(PCIREG_SHIFTOUT(reg, PCI_EA_PP)); 2585 printf(" Secondary Properties: "); 2586 pci_conf_print_ea_cap_prop(PCIREG_SHIFTOUT(reg, PCI_EA_SP)); 2587 onoff("Writable", reg, PCI_EA_W); 2588 onoff("Enable for this entry", reg, PCI_EA_E); 2589 2590 if (entry_size == 0) { 2591 entoff += 4; 2592 continue; 2593 } 2594 2595 /* Base addr */ 2596 reg = regs[o2i(entoff + 4)]; 2597 base = reg & PCI_EA_LOWMASK; 2598 baseis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT; 2599 printf(" Base Address Register Low: 0x%08x\n", reg); 2600 if (baseis64) { 2601 /* 64bit */ 2602 reg2 = regs[o2i(entoff + 12)]; 2603 printf(" Base Address Register high: 0x%08x\n", 2604 reg2); 2605 base |= (uint64_t)reg2 << 32; 2606 } 2607 2608 /* Offset addr */ 2609 reg = regs[o2i(entoff + 8)]; 2610 offset = reg & PCI_EA_LOWMASK; 2611 offsetis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT; 2612 printf(" Max Offset Register Low: 0x%08x\n", reg); 2613 if (offsetis64) { 2614 /* 64bit */ 2615 reg2 = regs[o2i(entoff + (baseis64 ? 16 : 12))]; 2616 printf(" Max Offset Register high: 0x%08x\n", 2617 reg2); 2618 offset |= (uint64_t)reg2 << 32; 2619 } 2620 2621 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 2622 "\n", base, base + offset); 2623 2624 entoff += 4 + (4 * entry_size); 2625 } 2626 } 2627 2628 /* XXX pci_conf_print_fpb_cap */ 2629 2630 static struct { 2631 pcireg_t cap; 2632 const char *name; 2633 void (*printfunc)(const pcireg_t *, int); 2634 } pci_captab[] = { 2635 { PCI_CAP_RESERVED0, "reserved", NULL }, 2636 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2637 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2638 { PCI_CAP_VPD, "VPD", NULL }, 2639 { PCI_CAP_SLOTID, "SlotID", NULL }, 2640 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2641 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2642 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2643 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2644 { PCI_CAP_VENDSPEC, "Vendor-specific", 2645 pci_conf_print_vendspec_cap }, 2646 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2647 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2648 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2649 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2650 pci_conf_print_subsystem_cap }, 2651 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2652 { PCI_CAP_SECURE, "Secure Device", pci_conf_print_secure_cap }, 2653 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2654 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2655 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2656 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2657 { PCI_CAP_EA, "Enhanced Allocation", pci_conf_print_ea_cap }, 2658 { PCI_CAP_FPB, "Flattening Portal Bridge", NULL } 2659 }; 2660 2661 static int 2662 pci_conf_find_cap(const pcireg_t *regs, unsigned int capid, int *offsetp) 2663 { 2664 pcireg_t rval; 2665 unsigned int capptr; 2666 int off; 2667 2668 if (!(regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)) 2669 return 0; 2670 2671 /* Determine the Capability List Pointer register to start with. */ 2672 switch (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)])) { 2673 case 0: /* standard device header */ 2674 case 1: /* PCI-PCI bridge header */ 2675 capptr = PCI_CAPLISTPTR_REG; 2676 break; 2677 case 2: /* PCI-CardBus Bridge header */ 2678 capptr = PCI_CARDBUS_CAPLISTPTR_REG; 2679 break; 2680 default: 2681 return 0; 2682 } 2683 2684 for (off = PCI_CAPLIST_PTR(regs[o2i(capptr)]); 2685 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2686 rval = regs[o2i(off)]; 2687 if (capid == PCI_CAPLIST_CAP(rval)) { 2688 if (offsetp != NULL) 2689 *offsetp = off; 2690 return 1; 2691 } 2692 } 2693 return 0; 2694 } 2695 2696 static void 2697 pci_conf_print_caplist( 2698 #ifdef _KERNEL 2699 pci_chipset_tag_t pc, pcitag_t tag, 2700 #endif 2701 const pcireg_t *regs, int capoff) 2702 { 2703 int off; 2704 pcireg_t foundcap; 2705 pcireg_t rval; 2706 bool foundtable[__arraycount(pci_captab)]; 2707 unsigned int i; 2708 2709 /* Clear table */ 2710 for (i = 0; i < __arraycount(pci_captab); i++) 2711 foundtable[i] = false; 2712 2713 /* Print capability register's offset and the type first */ 2714 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2715 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2716 rval = regs[o2i(off)]; 2717 printf(" Capability register at 0x%02x\n", off); 2718 2719 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2720 foundcap = PCI_CAPLIST_CAP(rval); 2721 if (foundcap < __arraycount(pci_captab)) { 2722 printf("%s)\n", pci_captab[foundcap].name); 2723 /* Mark as found */ 2724 foundtable[foundcap] = true; 2725 } else 2726 printf("unknown)\n"); 2727 } 2728 2729 /* 2730 * And then, print the detail of each capability registers 2731 * in capability value's order. 2732 */ 2733 for (i = 0; i < __arraycount(pci_captab); i++) { 2734 if (foundtable[i] == false) 2735 continue; 2736 2737 /* 2738 * The type was found. Search capability list again and 2739 * print all capabilities that the capabiliy type is 2740 * the same. This is required because some capabilities 2741 * appear multiple times (e.g. HyperTransport capability). 2742 */ 2743 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2744 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2745 rval = regs[o2i(off)]; 2746 if ((PCI_CAPLIST_CAP(rval) == i) 2747 && (pci_captab[i].printfunc != NULL)) 2748 pci_captab[i].printfunc(regs, off); 2749 } 2750 } 2751 } 2752 2753 /* Extended Capability */ 2754 2755 static void 2756 pci_conf_print_aer_cap_uc(pcireg_t reg) 2757 { 2758 2759 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2760 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2761 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2762 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2763 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2764 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2765 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2766 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2767 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2768 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2769 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2770 onoff("Unsupported Request Error", reg, 2771 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2772 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2773 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2774 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2775 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2776 onoff("TLP Prefix Blocked Error", reg, 2777 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2778 onoff("Poisoned TLP Egress Blocked", reg, 2779 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2780 } 2781 2782 static void 2783 pci_conf_print_aer_cap_cor(pcireg_t reg) 2784 { 2785 2786 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2787 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2788 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2789 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2790 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2791 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2792 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2793 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2794 } 2795 2796 static void 2797 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2798 { 2799 2800 printf(" First Error Pointer: 0x%04x\n", 2801 PCIREG_SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2802 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2803 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2804 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2805 onoff("ECRC Check Enable", reg, PCI_AER_ECRC_CHECK_ENABLE); 2806 onoff("Multiple Header Recording Capable", reg, 2807 PCI_AER_MULT_HDR_CAPABLE); 2808 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2809 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2810 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2811 2812 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2813 if (!tlp_prefix_log) 2814 return; 2815 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2816 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2817 } 2818 2819 static void 2820 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2821 { 2822 2823 onoff("Correctable Error Reporting Enable", reg, 2824 PCI_AER_ROOTERR_COR_ENABLE); 2825 onoff("Non-Fatal Error Reporting Enable", reg, 2826 PCI_AER_ROOTERR_NF_ENABLE); 2827 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2828 } 2829 2830 static void 2831 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2832 { 2833 2834 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2835 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2836 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2837 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2838 PCI_AER_ROOTERR_MULTI_UC_ERR); 2839 onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL); 2840 onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR); 2841 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2842 printf(" Advanced Error Interrupt Message Number: 0x%02x\n", 2843 PCIREG_SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2844 } 2845 2846 static void 2847 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2848 { 2849 2850 printf(" Correctable Source ID: 0x%04x\n", 2851 PCIREG_SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2852 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2853 PCIREG_SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2854 } 2855 2856 static void 2857 pci_conf_print_aer_cap(const pcireg_t *regs, int extcapoff) 2858 { 2859 pcireg_t reg; 2860 int pcie_capoff; 2861 int pcie_devtype = -1; 2862 bool tlp_prefix_log = false; 2863 2864 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2865 reg = regs[o2i(pcie_capoff)]; 2866 pcie_devtype = PCIE_XCAP_TYPE(reg); 2867 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2868 if (PCIREG_SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2869 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2870 /* End-End TLP Prefix Supported */ 2871 if (reg & PCIE_DCAP2_EETLP_PREF) { 2872 tlp_prefix_log = true; 2873 } 2874 } 2875 } 2876 2877 printf("\n Advanced Error Reporting Register\n"); 2878 2879 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2880 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2881 pci_conf_print_aer_cap_uc(reg); 2882 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2883 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2884 pci_conf_print_aer_cap_uc(reg); 2885 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2886 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2887 pci_conf_print_aer_cap_uc(reg); 2888 2889 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2890 printf(" Correctable Error Status register: 0x%08x\n", reg); 2891 pci_conf_print_aer_cap_cor(reg); 2892 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2893 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2894 pci_conf_print_aer_cap_cor(reg); 2895 2896 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2897 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2898 reg); 2899 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2900 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2901 printf(" Header Log register:\n"); 2902 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2903 extcapoff + PCI_AER_ROOTERR_CMD); 2904 2905 switch (pcie_devtype) { 2906 case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */ 2907 case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */ 2908 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2909 printf(" Root Error Command register: 0x%08x\n", reg); 2910 pci_conf_print_aer_cap_rooterr_cmd(reg); 2911 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2912 printf(" Root Error Status register: 0x%08x\n", reg); 2913 pci_conf_print_aer_cap_rooterr_status(reg); 2914 2915 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2916 printf(" Error Source Identification register: 0x%08x\n", 2917 reg); 2918 pci_conf_print_aer_cap_errsrc_id(reg); 2919 break; 2920 } 2921 2922 if (tlp_prefix_log) { 2923 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2924 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2925 } 2926 } 2927 2928 /* 2929 * Helper function to print the arbitration phase register. 2930 * 2931 * phases: Number of phases in the arbitration tables. 2932 * arbsize: Number of bits in each phase. 2933 * indent: Add more two spaces if it's true. 2934 */ 2935 static void 2936 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2937 const int phases, int arbsize, bool indent) 2938 { 2939 pcireg_t reg; 2940 int num_per_reg = 32 / arbsize; 2941 int i, j; 2942 2943 printf("%s %s Arbitration Table:\n", indent ? " " : "", name); 2944 for (i = 0; i < phases; i += num_per_reg) { 2945 reg = regs[o2i(off + (sizeof(uint32_t) * (i / num_per_reg)))]; 2946 for (j = 0; j < num_per_reg; j++) { 2947 printf("%s Phase[%d]: 0x%x\n", indent ? " " : "", 2948 i + j, 2949 (uint32_t)(reg & __BITS(arbsize - 1, 0))); 2950 reg >>= arbsize; 2951 } 2952 } 2953 } 2954 2955 /* For VC, bit 4-7 are reserved. For Port, bit 6-7 are reserved */ 2956 static const int arb_phases[8] = {0, 32, 64, 128, 128, 256, 0, 0 }; 2957 2958 static void 2959 pci_conf_print_vc_cap(const pcireg_t *regs, int extcapoff) 2960 { 2961 pcireg_t reg, n; 2962 int arbtab, parbsize; 2963 pcireg_t arbsel; 2964 int i, count; 2965 2966 printf("\n Virtual Channel Register\n"); 2967 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2968 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2969 count = PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2970 printf(" Extended VC Count: %d\n", count); 2971 n = PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2972 printf(" Low Priority Extended VC Count: %u\n", n); 2973 n = PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 2974 printf(" Reference Clock: %s\n", 2975 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 2976 parbsize = 1 << PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 2977 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 2978 2979 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 2980 printf(" Port VC Capability register 2: 0x%08x\n", reg); 2981 onoff("Hardware fixed arbitration scheme", 2982 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 2983 onoff("WRR arbitration with 32 phases", 2984 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 2985 onoff("WRR arbitration with 64 phases", 2986 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 2987 onoff("WRR arbitration with 128 phases", 2988 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 2989 arbtab = PCIREG_SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 2990 printf(" VC Arbitration Table Offset: 0x%x\n", arbtab); 2991 2992 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 2993 printf(" Port VC Control register: 0x%04x\n", reg); 2994 arbsel = PCIREG_SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 2995 printf(" VC Arbitration Select: 0x%x\n", arbsel); 2996 2997 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 2998 printf(" Port VC Status register: 0x%04x\n", reg); 2999 onoff("VC Arbitration Table Status", 3000 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 3001 3002 if ((arbtab != 0) && (arbsel != 0)) 3003 pci_conf_print_vc_cap_arbtab(regs, extcapoff + (arbtab * 16), 3004 "VC", arb_phases[arbsel], 4, false); 3005 3006 for (i = 0; i < count + 1; i++) { 3007 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 3008 printf(" VC number %d\n", i); 3009 printf(" VC Resource Capability Register: 0x%08x\n", reg); 3010 onoff(" Non-configurable Hardware fixed arbitration scheme", 3011 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 3012 onoff(" WRR arbitration with 32 phases", 3013 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 3014 onoff(" WRR arbitration with 64 phases", 3015 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 3016 onoff(" WRR arbitration with 128 phases", 3017 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 3018 onoff(" Time-based WRR arbitration with 128 phases", 3019 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 3020 onoff(" WRR arbitration with 256 phases", 3021 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 3022 onoff(" Advanced Packet Switching", 3023 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 3024 onoff(" Reject Snoop Transaction", 3025 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 3026 n = PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 3027 printf(" Maximum Time Slots: %d\n", n); 3028 arbtab = PCIREG_SHIFTOUT(reg, 3029 PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET); 3030 printf(" Port Arbitration Table offset: 0x%02x\n", 3031 arbtab); 3032 3033 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 3034 printf(" VC Resource Control Register: 0x%08x\n", reg); 3035 printf(" TC/VC Map: 0x%02x\n", 3036 PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 3037 /* 3038 * The load Port Arbitration Table bit is used to update 3039 * the Port Arbitration logic and it's always 0 on read, so 3040 * we don't print it. 3041 */ 3042 arbsel = PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 3043 printf(" Port Arbitration Select: 0x%x\n", arbsel); 3044 n = PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 3045 printf(" VC ID: %d\n", n); 3046 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 3047 3048 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 3049 printf(" VC Resource Status Register: 0x%08x\n", reg); 3050 onoff(" Port Arbitration Table Status", 3051 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 3052 onoff(" VC Negotiation Pending", 3053 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 3054 3055 if ((arbtab != 0) && (arbsel != 0)) 3056 pci_conf_print_vc_cap_arbtab(regs, 3057 extcapoff + (arbtab * 16), 3058 "Port", arb_phases[arbsel], parbsize, true); 3059 } 3060 } 3061 3062 /* 3063 * Print Power limit. This encoding is the same among the following registers: 3064 * - The Captured Slot Power Limit in the PCIe Device Capability Register. 3065 * - The Slot Power Limit in the PCIe Slot Capability Register. 3066 * - The Base Power in the Data register of Power Budgeting capability. 3067 */ 3068 static void 3069 pci_conf_print_pcie_power(uint8_t base, unsigned int scale) 3070 { 3071 unsigned int sdiv = 1; 3072 3073 if ((scale == 0) && (base > 0xef)) { 3074 const char *s; 3075 3076 switch (base) { 3077 case 0xf0: 3078 s = "239W < x <= 250W"; 3079 break; 3080 case 0xf1: 3081 s = "250W < x <= 275W"; 3082 break; 3083 case 0xf2: 3084 s = "275W < x <= 300W"; 3085 break; 3086 default: 3087 s = "reserved for greater than 300W"; 3088 break; 3089 } 3090 printf("%s\n", s); 3091 return; 3092 } 3093 3094 for (unsigned int i = scale; i > 0; i--) 3095 sdiv *= 10; 3096 3097 printf("%u", base / sdiv); 3098 3099 if (scale != 0) { 3100 printf(".%u", base % sdiv); 3101 } 3102 printf ("W\n"); 3103 return; 3104 } 3105 3106 static const char * 3107 pci_conf_print_pwrbdgt_type(uint8_t reg) 3108 { 3109 3110 switch (reg) { 3111 case 0x00: 3112 return "PME Aux"; 3113 case 0x01: 3114 return "Auxilary"; 3115 case 0x02: 3116 return "Idle"; 3117 case 0x03: 3118 return "Sustained"; 3119 case 0x04: 3120 return "Sustained (Emergency Power Reduction)"; 3121 case 0x05: 3122 return "Maximum (Emergency Power Reduction)"; 3123 case 0x07: 3124 return "Maximum"; 3125 default: 3126 return "Unknown"; 3127 } 3128 } 3129 3130 static const char * 3131 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 3132 { 3133 3134 switch (reg) { 3135 case 0x00: 3136 return "Power(12V)"; 3137 case 0x01: 3138 return "Power(3.3V)"; 3139 case 0x02: 3140 return "Power(1.5V or 1.8V)"; 3141 case 0x07: 3142 return "Thermal"; 3143 default: 3144 return "Unknown"; 3145 } 3146 } 3147 3148 static void 3149 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int extcapoff) 3150 { 3151 pcireg_t reg; 3152 3153 printf("\n Power Budgeting\n"); 3154 3155 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 3156 printf(" Data Select register: 0x%08x\n", reg); 3157 3158 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 3159 printf(" Data register: 0x%08x\n", reg); 3160 printf(" Base Power: "); 3161 pci_conf_print_pcie_power( 3162 PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_DATA_BASEPWR), 3163 PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE)); 3164 printf(" PM Sub State: 0x%hhx\n", 3165 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 3166 printf(" PM State: D%u\n", 3167 PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 3168 printf(" Type: %s\n", 3169 pci_conf_print_pwrbdgt_type( 3170 (uint8_t)(PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 3171 printf(" Power Rail: %s\n", 3172 pci_conf_print_pwrbdgt_pwrrail( 3173 (uint8_t)(PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 3174 3175 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 3176 printf(" Power Budget Capability register: 0x%08x\n", reg); 3177 onoff("System Allocated", 3178 reg, PCI_PWRBDGT_CAP_SYSALLOC); 3179 } 3180 3181 static const char * 3182 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 3183 { 3184 3185 switch (type) { 3186 case 0x00: 3187 return "Configuration Space Element"; 3188 case 0x01: 3189 return "System Egress Port or internal sink (memory)"; 3190 case 0x02: 3191 return "Internal Root Complex Link"; 3192 default: 3193 return "Unknown"; 3194 } 3195 } 3196 3197 static void 3198 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int extcapoff) 3199 { 3200 pcireg_t reg; 3201 unsigned char nent, linktype; 3202 int i; 3203 3204 printf("\n Root Complex Link Declaration\n"); 3205 3206 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 3207 printf(" Element Self Description Register: 0x%08x\n", reg); 3208 printf(" Element Type: %s\n", 3209 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 3210 nent = PCIREG_SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 3211 printf(" Number of Link Entries: %hhu\n", nent); 3212 printf(" Component ID: %hhu\n", 3213 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 3214 printf(" Port Number: %hhu\n", 3215 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 3216 for (i = 0; i < nent; i++) { 3217 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 3218 printf(" Link Entry %d:\n", i + 1); 3219 printf(" Link Description Register: 0x%08x\n", reg); 3220 onoff(" Link Valid", reg, PCI_RCLINK_DCL_LINKDESC_LVALID); 3221 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 3222 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 3223 "Configuration Space", "Memory-Mapped Space"); 3224 onoff(" Associated RCRB Header", reg, 3225 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 3226 printf(" Target Component ID: %hhu\n", 3227 (uint8_t)PCIREG_SHIFTOUT(reg, 3228 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 3229 printf(" Target Port Number: %hhu\n", 3230 (uint8_t)PCIREG_SHIFTOUT(reg, 3231 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 3232 3233 if (linktype == 0) { 3234 /* Memory-Mapped Space */ 3235 reg = regs[o2i(extcapoff 3236 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 3237 printf(" Link Address Low Register: 0x%08x\n", 3238 reg); 3239 reg = regs[o2i(extcapoff 3240 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 3241 printf(" Link Address High Register: 0x%08x\n", 3242 reg); 3243 } else { 3244 unsigned int nb; 3245 pcireg_t lo, hi; 3246 3247 /* Configuration Space */ 3248 lo = regs[o2i(extcapoff 3249 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 3250 printf(" Configuration Space Low Register: " 3251 "0x%08x\n", lo); 3252 hi = regs[o2i(extcapoff 3253 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 3254 printf(" Configuration Space High Register: " 3255 "0x%08x\n", hi); 3256 nb = PCIREG_SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 3257 printf(" N: %u\n", nb); 3258 printf(" Func: %hhu\n", 3259 (uint8_t)PCIREG_SHIFTOUT(lo, 3260 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 3261 printf(" Dev: %hhu\n", 3262 (uint8_t)PCIREG_SHIFTOUT(lo, 3263 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 3264 printf(" Bus: %hhu\n", 3265 (uint8_t)PCIREG_SHIFTOUT(lo, 3266 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 3267 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 3268 printf(" Configuration Space Base Address: " 3269 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 3270 } 3271 } 3272 } 3273 3274 /* XXX pci_conf_print_rclink_ctl_cap */ 3275 3276 static void 3277 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int extcapoff) 3278 { 3279 pcireg_t reg; 3280 3281 printf("\n Root Complex Event Collector Association\n"); 3282 3283 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 3284 printf(" Association Bitmap for Root Complex Integrated Devices:" 3285 " 0x%08x\n", reg); 3286 3287 if (PCI_EXTCAPLIST_VERSION(regs[o2i(extcapoff)]) >= 2) { 3288 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBUSNUM)]; 3289 printf(" RCEC Associated Bus Numbers register: 0x%08x\n", 3290 reg); 3291 printf(" RCEC Next Bus: %u\n", 3292 PCIREG_SHIFTOUT(reg, 3293 PCI_RCEC_ASSOCBUSNUM_RCECNEXT)); 3294 printf(" RCEC Last Bus: %u\n", 3295 PCIREG_SHIFTOUT(reg, 3296 PCI_RCEC_ASSOCBUSNUM_RCECLAST)); 3297 } 3298 } 3299 3300 /* XXX pci_conf_print_mfvc_cap */ 3301 /* XXX pci_conf_print_vc2_cap */ 3302 /* XXX pci_conf_print_rcrb_cap */ 3303 /* XXX pci_conf_print_vendor_cap */ 3304 /* XXX pci_conf_print_cac_cap */ 3305 3306 static void 3307 pci_conf_print_acs_cap(const pcireg_t *regs, int extcapoff) 3308 { 3309 pcireg_t reg, cap, ctl; 3310 unsigned int size, i; 3311 3312 printf("\n Access Control Services\n"); 3313 3314 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 3315 cap = reg & 0xffff; 3316 ctl = reg >> 16; 3317 printf(" ACS Capability register: 0x%08x\n", cap); 3318 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 3319 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 3320 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 3321 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 3322 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 3323 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 3324 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 3325 size = PCIREG_SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 3326 if (size == 0) 3327 size = 256; 3328 printf(" Egress Control Vector Size: %u\n", size); 3329 printf(" ACS Control register: 0x%08x\n", ctl); 3330 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 3331 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 3332 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 3333 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 3334 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 3335 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 3336 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 3337 3338 /* 3339 * If the P2P Egress Control Capability bit is 0, ignore the Egress 3340 * Control vector. 3341 */ 3342 if ((cap & PCI_ACS_CAP_E) == 0) 3343 return; 3344 for (i = 0; i < size; i += 32) 3345 printf(" Egress Control Vector [%u..%u]: 0x%08x\n", i + 31, 3346 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 3347 } 3348 3349 static void 3350 pci_conf_print_ari_cap(const pcireg_t *regs, int extcapoff) 3351 { 3352 pcireg_t reg, cap, ctl; 3353 3354 printf("\n Alternative Routing-ID Interpretation Register\n"); 3355 3356 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3357 cap = reg & 0xffff; 3358 ctl = reg >> 16; 3359 printf(" Capability register: 0x%08x\n", cap); 3360 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 3361 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 3362 printf(" Next Function Number: %u\n", 3363 PCIREG_SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 3364 printf(" Control register: 0x%08x\n", ctl); 3365 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 3366 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 3367 printf(" Function Group: %u\n", 3368 PCIREG_SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 3369 } 3370 3371 static void 3372 pci_conf_print_ats_cap(const pcireg_t *regs, int extcapoff) 3373 { 3374 pcireg_t reg, cap, ctl; 3375 unsigned int num; 3376 3377 printf("\n Address Translation Services\n"); 3378 3379 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3380 cap = reg & 0xffff; 3381 ctl = reg >> 16; 3382 printf(" Capability register: 0x%04x\n", cap); 3383 num = PCIREG_SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 3384 if (num == 0) 3385 num = 32; 3386 printf(" Invalidate Queue Depth: %u\n", num); 3387 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 3388 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 3389 onoff("Relaxed Ordering", reg, PCI_ATS_CAP_RELAXORD); 3390 3391 printf(" Control register: 0x%04x\n", ctl); 3392 printf(" Smallest Translation Unit: %u\n", 3393 PCIREG_SHIFTOUT(reg, PCI_ATS_CTL_STU)); 3394 onoff("Enable", reg, PCI_ATS_CTL_EN); 3395 } 3396 3397 static void 3398 pci_conf_print_sernum_cap(const pcireg_t *regs, int extcapoff) 3399 { 3400 pcireg_t lo, hi; 3401 3402 printf("\n Device Serial Number Register\n"); 3403 3404 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 3405 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 3406 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 3407 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 3408 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 3409 } 3410 3411 static void 3412 pci_conf_print_sriov_cap(const pcireg_t *regs, int extcapoff) 3413 { 3414 char buf[sizeof("99999 MB")]; 3415 pcireg_t reg; 3416 pcireg_t total_vfs; 3417 int i; 3418 bool first; 3419 3420 printf("\n Single Root IO Virtualization Register\n"); 3421 3422 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 3423 printf(" Capabilities register: 0x%08x\n", reg); 3424 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 3425 onoff("ARI Capable Hierarchy Preserved", reg, 3426 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 3427 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 3428 printf(" VF Migration Interrupt Message Number: 0x%03x\n", 3429 PCIREG_SHIFTOUT(reg, PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 3430 } 3431 3432 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 3433 printf(" Control register: 0x%04x\n", reg); 3434 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 3435 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 3436 onoff("VF Migration Interrupt Enable", reg, 3437 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 3438 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 3439 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 3440 3441 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 3442 printf(" Status register: 0x%04x\n", reg); 3443 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 3444 3445 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 3446 printf(" InitialVFs register: 0x%04x\n", reg); 3447 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 3448 printf(" TotalVFs register: 0x%04x\n", reg); 3449 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 3450 printf(" NumVFs register: 0x%04x\n", reg); 3451 3452 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 3453 printf(" Function Dependency Link register: 0x%04x\n", reg); 3454 3455 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 3456 printf(" First VF Offset register: 0x%04x\n", reg); 3457 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 3458 printf(" VF Stride register: 0x%04x\n", reg); 3459 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16; 3460 printf(" Device ID: 0x%04x\n", reg); 3461 3462 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 3463 printf(" Supported Page Sizes register: 0x%08x\n", reg); 3464 printf(" Supported Page Size:"); 3465 for (i = 0, first = true; i < 32; i++) { 3466 if (reg & __BIT(i)) { 3467 #ifdef _KERNEL 3468 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 3469 #else 3470 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 3471 HN_AUTOSCALE, 0); 3472 #endif 3473 printf("%s %s", first ? "" : ",", buf); 3474 first = false; 3475 } 3476 } 3477 printf("\n"); 3478 3479 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 3480 printf(" System Page Sizes register: 0x%08x\n", reg); 3481 printf(" Page Size: "); 3482 if (reg != 0) { 3483 int bitpos = ffs(reg) -1; 3484 3485 /* Assume only one bit is set. */ 3486 #ifdef _KERNEL 3487 format_bytes(buf, sizeof(buf), 1LL << (bitpos + 12)); 3488 #else 3489 humanize_number(buf, sizeof(buf), 1LL << (bitpos + 12), 3490 "B", HN_AUTOSCALE, 0); 3491 #endif 3492 printf("%s", buf); 3493 } else { 3494 printf("unknown"); 3495 } 3496 printf("\n"); 3497 3498 for (i = 0; i < 6; i++) { 3499 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 3500 printf(" VF BAR%d register: 0x%08x\n", i, reg); 3501 } 3502 3503 if (total_vfs > 0) { 3504 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 3505 printf(" VF Migration State Array Offset register: 0x%08x\n", 3506 reg); 3507 printf(" VF Migration State Offset: 0x%08x\n", 3508 PCIREG_SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 3509 i = PCIREG_SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 3510 printf(" VF Migration State BIR: "); 3511 if (i >= 0 && i <= 5) { 3512 printf("BAR%d", i); 3513 } else { 3514 printf("unknown BAR (%d)", i); 3515 } 3516 printf("\n"); 3517 } 3518 } 3519 3520 /* XXX pci_conf_print_mriov_cap */ 3521 3522 static void 3523 pci_conf_print_multicast_cap(const pcireg_t *regs, int extcapoff) 3524 { 3525 pcireg_t reg, cap, ctl; 3526 pcireg_t regl, regh; 3527 uint64_t addr; 3528 int n; 3529 3530 printf("\n Multicast\n"); 3531 3532 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 3533 cap = reg & 0xffff; 3534 ctl = reg >> 16; 3535 printf(" Capability Register: 0x%04x\n", cap); 3536 printf(" Max Group: %u\n", 3537 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 3538 3539 /* Endpoint Only */ 3540 n = PCIREG_SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 3541 if (n > 0) 3542 printf(" Windw Size Requested: %d\n", 1 << (n - 1)); 3543 3544 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 3545 3546 printf(" Control Register: 0x%04x\n", ctl); 3547 printf(" Num Group: %u\n", 3548 PCIREG_SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 3549 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 3550 3551 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 3552 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 3553 printf(" Base Address Register 0: 0x%08x\n", regl); 3554 printf(" Base Address Register 1: 0x%08x\n", regh); 3555 printf(" Index Position: %u\n", 3556 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 3557 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 3558 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 3559 3560 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 3561 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 3562 printf(" Receive Register 0: 0x%08x\n", regl); 3563 printf(" Receive Register 1: 0x%08x\n", regh); 3564 3565 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 3566 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 3567 printf(" Block All Register 0: 0x%08x\n", regl); 3568 printf(" Block All Register 1: 0x%08x\n", regh); 3569 3570 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 3571 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 3572 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 3573 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 3574 3575 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 3576 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 3577 printf(" Overlay BAR 0: 0x%08x\n", regl); 3578 printf(" Overlay BAR 1: 0x%08x\n", regh); 3579 3580 n = regl & PCI_MCAST_OVERLAYL_SIZE; 3581 printf(" Overlay Size: "); 3582 if (n >= 6) 3583 printf("%d\n", n); 3584 else 3585 printf("off\n"); 3586 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 3587 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 3588 } 3589 3590 static void 3591 pci_conf_print_page_req_cap(const pcireg_t *regs, int extcapoff) 3592 { 3593 pcireg_t reg, ctl, sta; 3594 3595 printf("\n Page Request\n"); 3596 3597 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 3598 ctl = reg & 0xffff; 3599 sta = reg >> 16; 3600 printf(" Control Register: 0x%04x\n", ctl); 3601 onoff("Enable", reg, PCI_PAGE_REQ_CTL_E); 3602 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 3603 3604 printf(" Status Register: 0x%04x\n", sta); 3605 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 3606 onoff("Unexpected Page Request Group Index", reg, 3607 PCI_PAGE_REQ_STA_UPRGI); 3608 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 3609 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 3610 3611 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 3612 printf(" Outstanding Page Request Capacity: %u\n", reg); 3613 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 3614 printf(" Outstanding Page Request Allocation: %u\n", reg); 3615 } 3616 3617 /* XXX pci_conf_print_amd_cap */ 3618 3619 #define MEM_PBUFSIZE sizeof("999GB") 3620 3621 static void 3622 pci_conf_print_resizbar_cap(const pcireg_t *regs, int extcapoff) 3623 { 3624 pcireg_t cap, ctl; 3625 unsigned int bars, i, n; 3626 char pbuf[MEM_PBUFSIZE]; 3627 3628 printf("\n Resizable BAR\n"); 3629 3630 /* Get Number of Resizable BARs */ 3631 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))]; 3632 bars = PCIREG_SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR); 3633 printf(" Number of Resizable BARs: "); 3634 if (bars <= 6) 3635 printf("%u\n", bars); 3636 else { 3637 printf("incorrect (%u)\n", bars); 3638 return; 3639 } 3640 3641 for (n = 0; n < 6; n++) { 3642 cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))]; 3643 printf(" Capability register(%u): 0x%08x\n", n, cap); 3644 if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0) 3645 continue; /* Not Used */ 3646 printf(" Acceptable BAR sizes:"); 3647 for (i = 4; i <= 23; i++) { 3648 if ((cap & (1 << i)) != 0) { 3649 humanize_number(pbuf, MEM_PBUFSIZE, 3650 (int64_t)1024 * 1024 << (i - 4), "B", 3651 #ifdef _KERNEL 3652 1); 3653 #else 3654 HN_AUTOSCALE, HN_NOSPACE); 3655 #endif 3656 printf(" %s", pbuf); 3657 } 3658 } 3659 printf("\n"); 3660 3661 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))]; 3662 printf(" Control register(%u): 0x%08x\n", n, ctl); 3663 printf(" BAR Index: %u\n", 3664 PCIREG_SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX)); 3665 humanize_number(pbuf, MEM_PBUFSIZE, 3666 (int64_t)1024 * 1024 3667 << PCIREG_SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ), 3668 "B", 3669 #ifdef _KERNEL 3670 1); 3671 #else 3672 HN_AUTOSCALE, HN_NOSPACE); 3673 #endif 3674 printf(" BAR Size: %s\n", pbuf); 3675 } 3676 } 3677 3678 static void 3679 pci_conf_print_dpa_cap(const pcireg_t *regs, int extcapoff) 3680 { 3681 pcireg_t reg; 3682 unsigned int substmax, i; 3683 3684 printf("\n Dynamic Power Allocation\n"); 3685 3686 reg = regs[o2i(extcapoff + PCI_DPA_CAP)]; 3687 printf(" Capability register: 0x%08x\n", reg); 3688 substmax = PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX); 3689 printf(" Substate Max: %u\n", substmax); 3690 printf(" Transition Latency Unit: "); 3691 switch (PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) { 3692 case 0: 3693 printf("1ms\n"); 3694 break; 3695 case 1: 3696 printf("10ms\n"); 3697 break; 3698 case 2: 3699 printf("100ms\n"); 3700 break; 3701 default: 3702 printf("reserved\n"); 3703 break; 3704 } 3705 printf(" Power Allocation Scale: "); 3706 switch (PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_PAS)) { 3707 case 0: 3708 printf("10.0x\n"); 3709 break; 3710 case 1: 3711 printf("1.0x\n"); 3712 break; 3713 case 2: 3714 printf("0.1x\n"); 3715 break; 3716 case 3: 3717 printf("0.01x\n"); 3718 break; 3719 } 3720 printf(" Transition Latency Value 0: %u\n", 3721 PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_XLCY0)); 3722 printf(" Transition Latency Value 1: %u\n", 3723 PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); 3724 3725 reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; 3726 printf(" Latency Indicatior register: 0x%08x\n", reg); 3727 3728 reg = regs[o2i(extcapoff + PCI_DPA_CS)]; 3729 printf(" Status register: 0x%04x\n", reg & 0xffff); 3730 printf(" Substate Status: 0x%02x\n", 3731 PCIREG_SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT)); 3732 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN); 3733 printf(" Control register: 0x%04x\n", reg >> 16); 3734 printf(" Substate Control: 0x%02x\n", 3735 PCIREG_SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL)); 3736 3737 for (i = 0; i <= substmax; i++) 3738 printf(" Substate Power Allocation register %d: 0x%02x\n", 3739 i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff)); 3740 } 3741 3742 static const char * 3743 pci_conf_print_tph_req_cap_sttabloc(uint8_t val) 3744 { 3745 3746 switch (val) { 3747 case PCI_TPH_REQ_STTBLLOC_NONE: 3748 return "Not Present"; 3749 case PCI_TPH_REQ_STTBLLOC_TPHREQ: 3750 return "in the TPH Requester Capability Structure"; 3751 case PCI_TPH_REQ_STTBLLOC_MSIX: 3752 return "in the MSI-X Table"; 3753 default: 3754 return "Unknown"; 3755 } 3756 } 3757 3758 static void 3759 pci_conf_print_tph_req_cap(const pcireg_t *regs, int extcapoff) 3760 { 3761 pcireg_t reg; 3762 int size = 0, i, j; 3763 uint8_t sttbloc; 3764 3765 printf("\n TPH Requester Extended Capability\n"); 3766 3767 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3768 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3769 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3770 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3771 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3772 onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3773 sttbloc = PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC); 3774 printf(" ST Table Location: %s\n", 3775 pci_conf_print_tph_req_cap_sttabloc(sttbloc)); 3776 if (sttbloc == PCI_TPH_REQ_STTBLLOC_TPHREQ) { 3777 size = PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3778 printf(" ST Table Size: %d\n", size); 3779 } 3780 3781 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CTL)]; 3782 printf(" TPH Requester Control register: 0x%08x\n", reg); 3783 printf(" ST Mode Select: "); 3784 switch (PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CTL_STSEL)) { 3785 case PCI_TPH_REQ_CTL_STSEL_NO: 3786 printf("No ST Mode\n"); 3787 break; 3788 case PCI_TPH_REQ_CTL_STSEL_IV: 3789 printf("Interrupt Vector Mode\n"); 3790 break; 3791 case PCI_TPH_REQ_CTL_STSEL_DS: 3792 printf("Device Specific Mode\n"); 3793 break; 3794 default: 3795 printf("(reserved value)\n"); 3796 break; 3797 } 3798 printf(" TPH Requester Enable: "); 3799 switch (PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CTL_TPHREQEN)) { 3800 case PCI_TPH_REQ_CTL_TPHREQEN_NO: /* 0x0 */ 3801 printf("Not permitted\n"); 3802 break; 3803 case PCI_TPH_REQ_CTL_TPHREQEN_TPH: 3804 printf("TPH and not Extended TPH\n"); 3805 break; 3806 case PCI_TPH_REQ_CTL_TPHREQEN_ETPH: 3807 printf("TPH and Extended TPH"); 3808 break; 3809 default: 3810 printf("(reserved value)\n"); 3811 break; 3812 } 3813 3814 if (sttbloc != PCI_TPH_REQ_STTBLLOC_TPHREQ) 3815 return; 3816 3817 for (i = 0; i < size ; i += 2) { 3818 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3819 for (j = 0; j < 2 ; j++) { 3820 uint32_t entry = reg; 3821 3822 if (j != 0) 3823 entry >>= 16; 3824 entry &= 0xffff; 3825 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3826 i + j, entry); 3827 } 3828 } 3829 } 3830 3831 static void 3832 pci_conf_print_ltr_cap(const pcireg_t *regs, int extcapoff) 3833 { 3834 pcireg_t reg; 3835 3836 printf("\n Latency Tolerance Reporting\n"); 3837 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)]; 3838 printf(" Max Snoop Latency Register: 0x%04x\n", reg & 0xffff); 3839 printf(" Max Snoop Latency: %juns\n", 3840 (uintmax_t)(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL) 3841 * PCI_LTR_SCALETONS(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE)))); 3842 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg >> 16); 3843 printf(" Max No-Snoop Latency: %juns\n", 3844 (uintmax_t)(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL) 3845 * PCI_LTR_SCALETONS(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE)))); 3846 } 3847 3848 static void 3849 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int extcapoff) 3850 { 3851 int pcie_capoff; 3852 pcireg_t reg; 3853 int i, maxlinkwidth; 3854 3855 printf("\n Secondary PCI Express Register\n"); 3856 3857 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3858 printf(" Link Control 3 register: 0x%08x\n", reg); 3859 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3860 onoff("Link Equalization Request Interrupt Enable", 3861 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3862 printf(" Enable Lower SKP OS Generation Vector:"); 3863 pci_print_pcie_linkspeedvector( 3864 PCIREG_SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3865 printf("\n"); 3866 3867 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3868 printf(" Lane Error Status register: 0x%08x\n", reg); 3869 3870 /* Get Max Link Width */ 3871 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 3872 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3873 maxlinkwidth = PCIREG_SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3874 } else { 3875 printf("error: falied to get PCIe capablity\n"); 3876 return; 3877 } 3878 for (i = 0; i < maxlinkwidth; i++) { 3879 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3880 if (i % 2 != 0) 3881 reg >>= 16; 3882 else 3883 reg &= 0xffff; 3884 printf(" Equalization Control Register (Link %d): 0x%04x\n", 3885 i, reg); 3886 printf(" Downstream Port Transmit Preset: 0x%x\n", 3887 PCIREG_SHIFTOUT(reg, 3888 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3889 printf(" Downstream Port Receive Hint: 0x%x\n", 3890 PCIREG_SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3891 printf(" Upstream Port Transmit Preset: 0x%x\n", 3892 PCIREG_SHIFTOUT(reg, 3893 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3894 printf(" Upstream Port Receive Hint: 0x%x\n", 3895 PCIREG_SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3896 } 3897 } 3898 3899 /* XXX pci_conf_print_pmux_cap */ 3900 3901 static void 3902 pci_conf_print_pasid_cap(const pcireg_t *regs, int extcapoff) 3903 { 3904 pcireg_t reg, cap, ctl; 3905 unsigned int num; 3906 3907 printf("\n Process Address Space ID\n"); 3908 3909 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3910 cap = reg & 0xffff; 3911 ctl = reg >> 16; 3912 printf(" PASID Capability Register: 0x%04x\n", cap); 3913 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3914 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3915 num = (1 << PCIREG_SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3916 printf(" Max PASID Width: %u\n", num); 3917 3918 printf(" PASID Control Register: 0x%04x\n", ctl); 3919 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3920 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3921 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3922 } 3923 3924 static void 3925 pci_conf_print_lnr_cap(const pcireg_t *regs, int extcapoff) 3926 { 3927 pcireg_t reg, cap, ctl; 3928 unsigned int num; 3929 3930 printf("\n LN Requester\n"); 3931 3932 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3933 cap = reg & 0xffff; 3934 ctl = reg >> 16; 3935 printf(" LNR Capability register: 0x%04x\n", cap); 3936 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 3937 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 3938 num = 1 << PCIREG_SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 3939 printf(" LNR Registration MAX: %u\n", num); 3940 3941 printf(" LNR Control register: 0x%04x\n", ctl); 3942 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 3943 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 3944 num = 1 << PCIREG_SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 3945 printf(" LNR Registration Limit: %u\n", num); 3946 } 3947 3948 static void 3949 pci_conf_print_dpc_pio(pcireg_t r) 3950 { 3951 onoff("Cfg Request received UR Completion", r,PCI_DPC_RPPIO_CFGUR_CPL); 3952 onoff("Cfg Request received CA Completion", r,PCI_DPC_RPPIO_CFGCA_CPL); 3953 onoff("Cfg Request Completion Timeout", r, PCI_DPC_RPPIO_CFG_CTO); 3954 onoff("I/O Request received UR Completion", r, PCI_DPC_RPPIO_IOUR_CPL); 3955 onoff("I/O Request received CA Completion", r, PCI_DPC_RPPIO_IOCA_CPL); 3956 onoff("I/O Request Completion Timeout", r, PCI_DPC_RPPIO_IO_CTO); 3957 onoff("Mem Request received UR Completion", r,PCI_DPC_RPPIO_MEMUR_CPL); 3958 onoff("Mem Request received CA Completion", r,PCI_DPC_RPPIO_MEMCA_CPL); 3959 onoff("Mem Request Completion Timeout", r, PCI_DPC_RPPIO_MEM_CTO); 3960 } 3961 3962 static void 3963 pci_conf_print_dpc_cap(const pcireg_t *regs, int extcapoff) 3964 { 3965 pcireg_t reg, cap, ctl, stat, errsrc; 3966 const char *trigstr; 3967 bool rpext; 3968 3969 printf("\n Downstream Port Containment\n"); 3970 3971 reg = regs[o2i(extcapoff + PCI_DPC_CCR)]; 3972 cap = reg & 0xffff; 3973 ctl = reg >> 16; 3974 rpext = (reg & PCI_DPCCAP_RPEXT) ? true : false; 3975 printf(" DPC Capability register: 0x%04x\n", cap); 3976 printf(" DPC Interrupt Message Number: %02x\n", 3977 (unsigned int)(cap & PCI_DPCCAP_IMSGN)); 3978 onoff("RP Extensions for DPC", reg, PCI_DPCCAP_RPEXT); 3979 onoff("Poisoned TLP Egress Blocking Supported", reg, 3980 PCI_DPCCAP_POISONTLPEB); 3981 onoff("DPC Software Triggering Supported", reg, PCI_DPCCAP_SWTRIG); 3982 printf(" RP PIO Log Size: %u\n", 3983 PCIREG_SHIFTOUT(reg, PCI_DPCCAP_RPPIOLOGSZ)); 3984 onoff("DL_Active ERR_COR Signaling Supported", reg, 3985 PCI_DPCCAP_DLACTECORS); 3986 printf(" DPC Control register: 0x%04x\n", ctl); 3987 switch (PCIREG_SHIFTOUT(reg, PCI_DPCCTL_TIRGEN)) { 3988 case 0: 3989 trigstr = "disabled"; 3990 break; 3991 case 1: 3992 trigstr = "enabled(ERR_FATAL)"; 3993 break; 3994 case 2: 3995 trigstr = "enabled(ERR_NONFATAL or ERR_FATAL)"; 3996 break; 3997 default: 3998 trigstr = "(reserverd)"; 3999 break; 4000 } 4001 printf(" DPC Trigger Enable: %s\n", trigstr); 4002 printf(" DPC Completion Control: %s Completion Status\n", 4003 (reg & PCI_DPCCTL_COMPCTL) 4004 ? "Unsupported Request(UR)" : "Completer Abort(CA)"); 4005 onoff("DPC Interrupt Enable", reg, PCI_DPCCTL_IE); 4006 onoff("DPC ERR_COR Enable", reg, PCI_DPCCTL_ERRCOREN); 4007 onoff("Poisoned TLP Egress Blocking Enable", reg, 4008 PCI_DPCCTL_POISONTLPEB); 4009 onoff("DPC Software Trigger", reg, PCI_DPCCTL_SWTRIG); 4010 onoff("DL_Active ERR_COR Enable", reg, PCI_DPCCTL_DLACTECOR); 4011 4012 reg = regs[o2i(extcapoff + PCI_DPC_STATESID)]; 4013 stat = reg & 0xffff; 4014 errsrc = reg >> 16; 4015 printf(" DPC Status register: 0x%04x\n", stat); 4016 onoff("DPC Trigger Status", reg, PCI_DPCSTAT_TSTAT); 4017 switch (PCIREG_SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 4018 case 0: 4019 trigstr = "an unmasked uncorrectable error"; 4020 break; 4021 case 1: 4022 trigstr = "receiving an ERR_NONFATAL"; 4023 break; 4024 case 2: 4025 trigstr = "receiving an ERR_FATAL"; 4026 break; 4027 case 3: 4028 trigstr = "DPC Trigger Reason Extension field"; 4029 break; 4030 } 4031 printf(" DPC Trigger Reason: Due to %s\n", trigstr); 4032 onoff("DPC Interrupt Status", reg, PCI_DPCSTAT_ISTAT); 4033 if (rpext) 4034 onoff("DPC RP Busy", reg, PCI_DPCSTAT_RPBUSY); 4035 switch (PCIREG_SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 4036 case 0: 4037 trigstr = "Due to RP PIO error"; 4038 break; 4039 case 1: 4040 trigstr = "Due to the DPC Software trigger bit"; 4041 break; 4042 default: 4043 trigstr = "(reserved)"; 4044 break; 4045 } 4046 printf(" DPC Trigger Reason Extension: %s\n", trigstr); 4047 if (rpext) 4048 printf(" RP PIO First Error Pointer: 0x%02x\n", 4049 PCIREG_SHIFTOUT(reg, PCI_DPCSTAT_RPPIOFEP)); 4050 printf(" DPC Error Source ID register: 0x%04x\n", errsrc); 4051 4052 if (!rpext) 4053 return; 4054 /* 4055 * All of the following registers are implemented by a device which has 4056 * RP Extensions for DPC 4057 */ 4058 4059 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_STAT)]; 4060 printf(" RP PIO Status Register: 0x%08x\n", reg); 4061 pci_conf_print_dpc_pio(reg); 4062 4063 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_MASK)]; 4064 printf(" RP PIO Mask Register: 0x%08x\n", reg); 4065 pci_conf_print_dpc_pio(reg); 4066 4067 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SEVE)]; 4068 printf(" RP PIO Severity Register: 0x%08x\n", reg); 4069 pci_conf_print_dpc_pio(reg); 4070 4071 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SYSERR)]; 4072 printf(" RP PIO SysError Register: 0x%08x\n", reg); 4073 pci_conf_print_dpc_pio(reg); 4074 4075 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_EXCPT)]; 4076 printf(" RP PIO Exception Register: 0x%08x\n", reg); 4077 pci_conf_print_dpc_pio(reg); 4078 4079 printf(" RP PIO Header Log Register: start from 0x%03x\n", 4080 extcapoff + PCI_DPC_RPPIO_HLOG); 4081 printf(" RP PIO ImpSpec Log Register: start from 0x%03x\n", 4082 extcapoff + PCI_DPC_RPPIO_IMPSLOG); 4083 printf(" RP PIO TLP Prefix Log Register: start from 0x%03x\n", 4084 extcapoff + PCI_DPC_RPPIO_TLPPLOG); 4085 } 4086 4087 4088 static int 4089 pci_conf_l1pm_cap_tposcale(unsigned char scale) 4090 { 4091 4092 /* Return scale in us */ 4093 switch (scale) { 4094 case 0x0: 4095 return 2; 4096 case 0x1: 4097 return 10; 4098 case 0x2: 4099 return 100; 4100 default: 4101 return -1; 4102 } 4103 } 4104 4105 static void 4106 pci_conf_print_l1pm_cap(const pcireg_t *regs, int extcapoff) 4107 { 4108 pcireg_t reg; 4109 int scale, val; 4110 int pcie_capoff; 4111 4112 printf("\n L1 PM Substates\n"); 4113 4114 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 4115 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 4116 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 4117 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 4118 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 4119 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 4120 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 4121 /* The Link Activation Supported bit is only for Downstream Port */ 4122 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 4123 uint32_t t = regs[o2i(pcie_capoff)]; 4124 4125 if ((t == PCIE_XCAP_TYPE_ROOT) || (t == PCIE_XCAP_TYPE_DOWN)) 4126 onoff("Link Activation Supported", reg, 4127 PCI_L1PM_CAP_LA); 4128 } 4129 printf(" Port Common Mode Restore Time: %uus\n", 4130 PCIREG_SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 4131 scale = pci_conf_l1pm_cap_tposcale( 4132 PCIREG_SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 4133 val = PCIREG_SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 4134 printf(" Port T_POWER_ON: "); 4135 if (scale == -1) 4136 printf("unknown\n"); 4137 else 4138 printf("%dus\n", val * scale); 4139 4140 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 4141 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 4142 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 4143 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 4144 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 4145 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 4146 onoff("Link Activation Interrupt Enable", reg, PCI_L1PM_CTL1_LAIE); 4147 onoff("Link Activation Control", reg, PCI_L1PM_CTL1_LA); 4148 printf(" Common Mode Restore Time: %uus\n", 4149 PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 4150 scale = PCI_LTR_SCALETONS(PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 4151 val = PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 4152 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 4153 4154 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 4155 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 4156 scale = pci_conf_l1pm_cap_tposcale( 4157 PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 4158 val = PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 4159 printf(" T_POWER_ON: "); 4160 if (scale == -1) 4161 printf("unknown\n"); 4162 else 4163 printf("%dus\n", val * scale); 4164 4165 if (PCI_EXTCAPLIST_VERSION(regs[o2i(extcapoff)]) >= 2) { 4166 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 4167 printf(" L1 PM Substates Status register: 0x%08x\n", reg); 4168 onoff("Link Activation Status", reg, PCI_L1PM_STAT_LA); 4169 } 4170 } 4171 4172 static void 4173 pci_conf_print_ptm_cap(const pcireg_t *regs, int extcapoff) 4174 { 4175 pcireg_t reg; 4176 uint32_t val; 4177 4178 printf("\n Precision Time Management\n"); 4179 4180 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 4181 printf(" PTM Capability register: 0x%08x\n", reg); 4182 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 4183 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 4184 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 4185 printf(" Local Clock Granularity: "); 4186 val = PCIREG_SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 4187 switch (val) { 4188 case 0: 4189 printf("Not implemented\n"); 4190 break; 4191 case 0xffff: 4192 printf("> 254ns\n"); 4193 break; 4194 default: 4195 printf("%uns\n", val); 4196 break; 4197 } 4198 4199 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 4200 printf(" PTM Control register: 0x%08x\n", reg); 4201 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 4202 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 4203 printf(" Effective Granularity: "); 4204 val = PCIREG_SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 4205 switch (val) { 4206 case 0: 4207 printf("Unknown\n"); 4208 break; 4209 case 0xffff: 4210 printf("> 254ns\n"); 4211 break; 4212 default: 4213 printf("%uns\n", val); 4214 break; 4215 } 4216 } 4217 4218 /* XXX pci_conf_print_mpcie_cap */ 4219 /* XXX pci_conf_print_frsq_cap */ 4220 /* XXX pci_conf_print_rtr_cap */ 4221 /* XXX pci_conf_print_desigvndsp_cap */ 4222 /* XXX pci_conf_print_vf_resizbar_cap */ 4223 4224 static void 4225 pci_conf_print_dlf_cap(const pcireg_t *regs, int extcapoff) 4226 { 4227 pcireg_t reg; 4228 4229 printf("\n Data link Feature Register\n"); 4230 reg = regs[o2i(extcapoff + PCI_DLF_CAP)]; 4231 printf(" Capability register: 0x%08x\n", reg); 4232 onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL); 4233 onoff("DLF Exchange enable", reg, PCI_DLF_CAP_XCHG); 4234 4235 reg = regs[o2i(extcapoff + PCI_DLF_STAT)]; 4236 printf(" Status register: 0x%08x\n", reg); 4237 onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL); 4238 onoff("Remote DLF supported Valid", reg, PCI_DLF_STAT_RMTVALID); 4239 } 4240 4241 /* XXX pci_conf_print_hierarchyid_cap */ 4242 /* XXX pci_conf_print_npem_cap */ 4243 4244 #undef MS 4245 #undef SM 4246 #undef RW 4247 4248 static struct { 4249 pcireg_t cap; 4250 const char *name; 4251 void (*printfunc)(const pcireg_t *, int); 4252 } pci_extcaptab[] = { 4253 { 0, "reserved", 4254 NULL }, 4255 { PCI_EXTCAP_AER, "Advanced Error Reporting", 4256 pci_conf_print_aer_cap }, 4257 { PCI_EXTCAP_VC, "Virtual Channel", 4258 pci_conf_print_vc_cap }, 4259 { PCI_EXTCAP_SERNUM, "Device Serial Number", 4260 pci_conf_print_sernum_cap }, 4261 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 4262 pci_conf_print_pwrbdgt_cap }, 4263 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 4264 pci_conf_print_rclink_dcl_cap }, 4265 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 4266 NULL }, 4267 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 4268 pci_conf_print_rcec_assoc_cap }, 4269 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 4270 NULL }, 4271 { PCI_EXTCAP_VC2, "Virtual Channel", 4272 NULL }, 4273 { PCI_EXTCAP_RCRB, "RCRB Header", 4274 NULL }, 4275 { PCI_EXTCAP_VENDOR, "Vendor Unique", 4276 NULL }, 4277 { PCI_EXTCAP_CAC, "Configuration Access Correction", 4278 NULL }, 4279 { PCI_EXTCAP_ACS, "Access Control Services", 4280 pci_conf_print_acs_cap }, 4281 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 4282 pci_conf_print_ari_cap }, 4283 { PCI_EXTCAP_ATS, "Address Translation Services", 4284 pci_conf_print_ats_cap }, 4285 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 4286 pci_conf_print_sriov_cap }, 4287 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 4288 NULL }, 4289 { PCI_EXTCAP_MCAST, "Multicast", 4290 pci_conf_print_multicast_cap }, 4291 { PCI_EXTCAP_PAGE_REQ, "Page Request", 4292 pci_conf_print_page_req_cap }, 4293 { PCI_EXTCAP_AMD, "Reserved for AMD", 4294 NULL }, 4295 { PCI_EXTCAP_RESIZBAR, "Resizable BAR", 4296 pci_conf_print_resizbar_cap }, 4297 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 4298 pci_conf_print_dpa_cap }, 4299 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 4300 pci_conf_print_tph_req_cap }, 4301 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 4302 pci_conf_print_ltr_cap }, 4303 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 4304 pci_conf_print_sec_pcie_cap }, 4305 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 4306 NULL }, 4307 { PCI_EXTCAP_PASID, "Process Address Space ID", 4308 pci_conf_print_pasid_cap }, 4309 { PCI_EXTCAP_LNR, "LN Requester", 4310 pci_conf_print_lnr_cap }, 4311 { PCI_EXTCAP_DPC, "Downstream Port Containment", 4312 pci_conf_print_dpc_cap }, 4313 { PCI_EXTCAP_L1PM, "L1 PM Substates", 4314 pci_conf_print_l1pm_cap }, 4315 { PCI_EXTCAP_PTM, "Precision Time Management", 4316 pci_conf_print_ptm_cap }, 4317 { PCI_EXTCAP_MPCIE, "M-PCIe", 4318 NULL }, 4319 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 4320 NULL }, 4321 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 4322 NULL }, 4323 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 4324 NULL }, 4325 { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", 4326 NULL }, 4327 { PCI_EXTCAP_DLF, "Data link Feature", pci_conf_print_dlf_cap }, 4328 { PCI_EXTCAP_PYSLAY_16GT, "Physical Layer 16.0 GT/s", NULL }, 4329 { 0x27, "unknown", NULL }, 4330 { PCI_EXTCAP_HIERARCHYID, "Hierarchy ID", 4331 NULL }, 4332 { PCI_EXTCAP_NPEM, "Native PCIe Enclosure Management", 4333 NULL }, 4334 }; 4335 4336 static int 4337 pci_conf_find_extcap(const pcireg_t *regs, unsigned int capid, int *offsetp) 4338 { 4339 int off; 4340 pcireg_t rval; 4341 4342 for (off = PCI_EXTCAPLIST_BASE; 4343 off != 0; 4344 off = PCI_EXTCAPLIST_NEXT(rval)) { 4345 rval = regs[o2i(off)]; 4346 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 4347 if (offsetp != NULL) 4348 *offsetp = off; 4349 return 1; 4350 } 4351 } 4352 return 0; 4353 } 4354 4355 static void 4356 pci_conf_print_extcaplist( 4357 #ifdef _KERNEL 4358 pci_chipset_tag_t pc, pcitag_t tag, 4359 #endif 4360 const pcireg_t *regs) 4361 { 4362 int off; 4363 pcireg_t foundcap; 4364 pcireg_t rval; 4365 bool foundtable[__arraycount(pci_extcaptab)]; 4366 unsigned int i; 4367 4368 /* Check Extended capability structure */ 4369 off = PCI_EXTCAPLIST_BASE; 4370 rval = regs[o2i(off)]; 4371 if (rval == 0xffffffff || rval == 0) 4372 return; 4373 4374 /* Clear table */ 4375 for (i = 0; i < __arraycount(pci_extcaptab); i++) 4376 foundtable[i] = false; 4377 4378 /* Print extended capability register's offset and the type first */ 4379 for (;;) { 4380 printf(" Extended Capability Register at 0x%02x\n", off); 4381 4382 foundcap = PCI_EXTCAPLIST_CAP(rval); 4383 printf(" type: 0x%04x (", foundcap); 4384 if (foundcap < __arraycount(pci_extcaptab)) { 4385 printf("%s)\n", pci_extcaptab[foundcap].name); 4386 /* Mark as found */ 4387 foundtable[foundcap] = true; 4388 } else 4389 printf("unknown)\n"); 4390 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 4391 4392 off = PCI_EXTCAPLIST_NEXT(rval); 4393 if (off == 0) 4394 break; 4395 else if (off <= PCI_CONF_SIZE) { 4396 printf(" next pointer: 0x%03x (incorrect)\n", off); 4397 return; 4398 } 4399 rval = regs[o2i(off)]; 4400 } 4401 4402 /* 4403 * And then, print the detail of each capability registers 4404 * in capability value's order. 4405 */ 4406 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 4407 if (foundtable[i] == false) 4408 continue; 4409 4410 /* 4411 * The type was found. Search capability list again and 4412 * print all capabilities that the capabiliy type is 4413 * the same. 4414 */ 4415 if (pci_conf_find_extcap(regs, i, &off) == 0) 4416 continue; 4417 rval = regs[o2i(off)]; 4418 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 4419 || (pci_extcaptab[i].printfunc == NULL)) 4420 continue; 4421 4422 pci_extcaptab[i].printfunc(regs, off); 4423 4424 } 4425 } 4426 4427 /* Print the Secondary Status Register. */ 4428 static void 4429 pci_conf_print_ssr(pcireg_t rval) 4430 { 4431 pcireg_t devsel; 4432 4433 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 4434 onoff("66 MHz capable", rval, __BIT(5)); 4435 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 4436 onoff("Fast back-to-back capable", rval, __BIT(7)); 4437 onoff("Data parity error detected", rval, __BIT(8)); 4438 4439 printf(" DEVSEL timing: "); 4440 devsel = PCIREG_SHIFTOUT(rval, __BITS(10, 9)); 4441 switch (devsel) { 4442 case 0: 4443 printf("fast"); 4444 break; 4445 case 1: 4446 printf("medium"); 4447 break; 4448 case 2: 4449 printf("slow"); 4450 break; 4451 default: 4452 printf("unknown/reserved"); /* XXX */ 4453 break; 4454 } 4455 printf(" (0x%x)\n", devsel); 4456 4457 onoff("Signalled target abort", rval, __BIT(11)); 4458 onoff("Received target abort", rval, __BIT(12)); 4459 onoff("Received master abort", rval, __BIT(13)); 4460 onoff("Received system error", rval, __BIT(14)); 4461 onoff("Detected parity error", rval, __BIT(15)); 4462 } 4463 4464 static void 4465 pci_conf_print_type0( 4466 #ifdef _KERNEL 4467 pci_chipset_tag_t pc, pcitag_t tag, 4468 #endif 4469 const pcireg_t *regs) 4470 { 4471 int off, width; 4472 pcireg_t rval; 4473 const char *str; 4474 4475 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 4476 #ifdef _KERNEL 4477 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4478 #else 4479 width = pci_conf_print_bar(regs, off, NULL); 4480 #endif 4481 } 4482 4483 printf(" Cardbus CIS Pointer: 0x%08x\n", 4484 regs[o2i(PCI_CARDBUS_CIS_REG)]); 4485 4486 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 4487 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4488 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4489 4490 rval = regs[o2i(PCI_MAPREG_ROM)]; 4491 printf(" Expansion ROM Base Address Register: 0x%08x\n", rval); 4492 printf(" base: 0x%08x\n", (uint32_t)PCI_MAPREG_ROM_ADDR(rval)); 4493 onoff("Expansion ROM Enable", rval, PCI_MAPREG_ROM_ENABLE); 4494 printf(" Validation Status: "); 4495 switch (PCIREG_SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_STAT)) { 4496 case PCI_MAPREG_ROM_VSTAT_NOTSUPP: 4497 str = "Validation not supported"; 4498 break; 4499 case PCI_MAPREG_ROM_VSTAT_INPROG: 4500 str = "Validation in Progress"; 4501 break; 4502 case PCI_MAPREG_ROM_VSTAT_VPASS: 4503 str = "Validation Pass. " 4504 "Valid contents, trust test was not performed"; 4505 break; 4506 case PCI_MAPREG_ROM_VSTAT_VPASSTRUST: 4507 str = "Validation Pass. Valid and trusted contents"; 4508 break; 4509 case PCI_MAPREG_ROM_VSTAT_VFAIL: 4510 str = "Validation Fail. Invalid contents"; 4511 break; 4512 case PCI_MAPREG_ROM_VSTAT_VFAILUNTRUST: 4513 str = "Validation Fail. Valid but untrusted contents"; 4514 break; 4515 case PCI_MAPREG_ROM_VSTAT_WPASS: 4516 str = "Warning Pass. Validation passed with warning. " 4517 "Valid contents, trust test was not performed"; 4518 break; 4519 case PCI_MAPREG_ROM_VSTAT_WPASSTRUST: 4520 str = "Warning Pass. Validation passed with warning. " 4521 "Valid and trusted contents"; 4522 break; 4523 } 4524 printf("%s\n", str); 4525 printf(" Validation Details: 0x%x\n", 4526 PCIREG_SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_DETAIL)); 4527 4528 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4529 printf(" Capability list pointer: 0x%02x\n", 4530 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4531 else 4532 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4533 4534 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 4535 4536 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4537 printf(" Maximum Latency: 0x%02x\n", PCI_MAX_LAT(rval)); 4538 printf(" Minimum Grant: 0x%02x\n", PCI_MIN_GNT(rval)); 4539 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 4540 switch (PCI_INTERRUPT_PIN(rval)) { 4541 case PCI_INTERRUPT_PIN_NONE: 4542 printf("(none)"); 4543 break; 4544 case PCI_INTERRUPT_PIN_A: 4545 printf("(pin A)"); 4546 break; 4547 case PCI_INTERRUPT_PIN_B: 4548 printf("(pin B)"); 4549 break; 4550 case PCI_INTERRUPT_PIN_C: 4551 printf("(pin C)"); 4552 break; 4553 case PCI_INTERRUPT_PIN_D: 4554 printf("(pin D)"); 4555 break; 4556 default: 4557 printf("(? ? ?)"); 4558 break; 4559 } 4560 printf("\n"); 4561 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 4562 } 4563 4564 static void 4565 pci_conf_print_type1( 4566 #ifdef _KERNEL 4567 pci_chipset_tag_t pc, pcitag_t tag, 4568 #endif 4569 const pcireg_t *regs) 4570 { 4571 int off, width; 4572 pcireg_t rval, csreg; 4573 uint32_t base, limit; 4574 uint32_t base_h, limit_h; 4575 uint64_t pbase, plimit; 4576 int use_upper; 4577 4578 /* 4579 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 4580 * Bridge chip documentation, and may not be correct with 4581 * respect to various standards. (XXX) 4582 */ 4583 4584 for (off = 0x10; off < 0x18; off += width) { 4585 #ifdef _KERNEL 4586 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4587 #else 4588 width = pci_conf_print_bar(regs, off, NULL); 4589 #endif 4590 } 4591 4592 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4593 printf(" Primary bus number: 0x%02x\n", 4594 PCI_BRIDGE_BUS_NUM_PRIMARY(rval)); 4595 printf(" Secondary bus number: 0x%02x\n", 4596 PCI_BRIDGE_BUS_NUM_SECONDARY(rval)); 4597 printf(" Subordinate bus number: 0x%02x\n", 4598 PCI_BRIDGE_BUS_NUM_SUBORDINATE(rval)); 4599 printf(" Secondary bus latency timer: 0x%02x\n", 4600 PCI_BRIDGE_BUS_SEC_LATTIMER_VAL(rval)); 4601 4602 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 4603 pci_conf_print_ssr(PCIREG_SHIFTOUT(rval, __BITS(31, 16))); 4604 4605 /* I/O region */ 4606 printf(" I/O region:\n"); 4607 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 4608 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 4609 if (PCI_BRIDGE_IO_32BITS(rval)) 4610 use_upper = 1; 4611 else 4612 use_upper = 0; 4613 onoff("32bit I/O", rval, use_upper); 4614 base = PCI_BRIDGE_STATIO_IOBASE_ADDR(rval); 4615 limit = PCI_BRIDGE_STATIO_IOLIMIT_ADDR(rval); 4616 4617 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 4618 base_h = PCIREG_SHIFTOUT(rval, PCI_BRIDGE_IOHIGH_BASE); 4619 limit_h = PCIREG_SHIFTOUT(rval, PCI_BRIDGE_IOHIGH_LIMIT); 4620 printf(" base upper 16 bits register: 0x%04x\n", base_h); 4621 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 4622 4623 if (use_upper == 1) { 4624 base |= base_h << 16; 4625 limit |= limit_h << 16; 4626 } 4627 if (base < limit) { 4628 if (use_upper == 1) 4629 printf(" range: 0x%08x-0x%08x\n", base, limit); 4630 else 4631 printf(" range: 0x%04x-0x%04x\n", base, limit); 4632 } else 4633 printf(" range: not set\n"); 4634 4635 /* Non-prefetchable memory region */ 4636 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 4637 printf(" Memory region:\n"); 4638 printf(" base register: 0x%04hx\n", 4639 (uint16_t)PCIREG_SHIFTOUT(rval, PCI_BRIDGE_MEMORY_BASE)); 4640 printf(" limit register: 0x%04hx\n", 4641 (uint16_t)PCIREG_SHIFTOUT(rval, PCI_BRIDGE_MEMORY_LIMIT)); 4642 base = PCI_BRIDGE_MEMORY_BASE_ADDR(rval); 4643 limit = PCI_BRIDGE_MEMORY_LIMIT_ADDR(rval); 4644 if (base < limit) 4645 printf(" range: 0x%08x-0x%08x\n", base, limit); 4646 else 4647 printf(" range: not set\n"); 4648 4649 /* Prefetchable memory region */ 4650 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 4651 printf(" Prefetchable memory region:\n"); 4652 printf(" base register: 0x%04x\n", 4653 (rval >> 0) & 0xffff); 4654 printf(" limit register: 0x%04x\n", 4655 (rval >> 16) & 0xffff); 4656 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASEUP32_REG)]; 4657 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMITUP32_REG)]; 4658 printf(" base upper 32 bits register: 0x%08x\n", 4659 base_h); 4660 printf(" limit upper 32 bits register: 0x%08x\n", 4661 limit_h); 4662 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 4663 use_upper = 1; 4664 else 4665 use_upper = 0; 4666 onoff("64bit memory address", rval, use_upper); 4667 pbase = PCI_BRIDGE_PREFETCHMEM_BASE_ADDR(rval); 4668 plimit = PCI_BRIDGE_PREFETCHMEM_LIMIT_ADDR(rval); 4669 if (use_upper == 1) { 4670 pbase |= (uint64_t)base_h << 32; 4671 plimit |= (uint64_t)limit_h << 32; 4672 } 4673 if (pbase < plimit) { 4674 if (use_upper == 1) 4675 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 4676 "\n", pbase, plimit); 4677 else 4678 printf(" range: 0x%08x-0x%08x\n", 4679 (uint32_t)pbase, (uint32_t)plimit); 4680 } else 4681 printf(" range: not set\n"); 4682 4683 csreg = regs[o2i(PCI_COMMAND_STATUS_REG)]; 4684 if (csreg & PCI_STATUS_CAPLIST_SUPPORT) 4685 printf(" Capability list pointer: 0x%02x\n", 4686 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4687 else 4688 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4689 4690 printf(" Expansion ROM Base Address: 0x%08x\n", 4691 regs[o2i(PCI_BRIDGE_EXPROMADDR_REG)]); 4692 4693 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4694 printf(" Interrupt line: 0x%02x\n", 4695 (rval >> 0) & 0xff); 4696 printf(" Interrupt pin: 0x%02x ", 4697 (rval >> 8) & 0xff); 4698 switch ((rval >> 8) & 0xff) { 4699 case PCI_INTERRUPT_PIN_NONE: 4700 printf("(none)"); 4701 break; 4702 case PCI_INTERRUPT_PIN_A: 4703 printf("(pin A)"); 4704 break; 4705 case PCI_INTERRUPT_PIN_B: 4706 printf("(pin B)"); 4707 break; 4708 case PCI_INTERRUPT_PIN_C: 4709 printf("(pin C)"); 4710 break; 4711 case PCI_INTERRUPT_PIN_D: 4712 printf("(pin D)"); 4713 break; 4714 default: 4715 printf("(? ? ?)"); 4716 break; 4717 } 4718 printf("\n"); 4719 rval = regs[o2i(PCI_BRIDGE_CONTROL_REG)]; 4720 printf(" Bridge control register: 0x%04hx\n", 4721 (uint16_t)PCIREG_SHIFTOUT(rval, PCI_BRIDGE_CONTROL)); 4722 onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE); 4723 onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR); 4724 onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA); 4725 onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA); 4726 /* 4727 * VGA 16bit decode bit has meaning if the VGA enable bit or the 4728 * VGA Palette Snoop Enable bit is set. 4729 */ 4730 if (((rval & PCI_BRIDGE_CONTROL_VGA) != 0) 4731 || ((csreg & PCI_COMMAND_PALETTE_ENABLE) != 0)) 4732 onoff("VGA 16bit enable", rval, PCI_BRIDGE_CONTROL_VGA16); 4733 onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT); 4734 onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR); 4735 onoff("Fast back-to-back enable", rval, PCI_BRIDGE_CONTROL_SECFASTB2B); 4736 onoff("Primary Discard Timer", rval, 4737 PCI_BRIDGE_CONTROL_PRI_DISC_TIMER); 4738 onoff("Secondary Discard Timer", 4739 rval, PCI_BRIDGE_CONTROL_SEC_DISC_TIMER); 4740 onoff("Discard Timer Status", rval, 4741 PCI_BRIDGE_CONTROL_DISC_TIMER_STAT); 4742 onoff("Discard Timer SERR# Enable", rval, 4743 PCI_BRIDGE_CONTROL_DISC_TIMER_SERR); 4744 } 4745 4746 static void 4747 pci_conf_print_type2( 4748 #ifdef _KERNEL 4749 pci_chipset_tag_t pc, pcitag_t tag, 4750 #endif 4751 const pcireg_t *regs) 4752 { 4753 pcireg_t rval; 4754 4755 /* 4756 * XXX these need to be printed in more detail, need to be 4757 * XXX checked against specs/docs, etc. 4758 * 4759 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 4760 * controller chip documentation, and may not be correct with 4761 * respect to various standards. (XXX) 4762 */ 4763 4764 #ifdef _KERNEL 4765 pci_conf_print_bar(pc, tag, regs, 0x10, 4766 "CardBus socket/ExCA registers"); 4767 #else 4768 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 4769 #endif 4770 4771 /* Capability list pointer and secondary status register */ 4772 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 4773 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4774 printf(" Capability list pointer: 0x%02x\n", 4775 PCI_CAPLIST_PTR(rval)); 4776 else 4777 printf(" Reserved @ 0x14: 0x%04x\n", 4778 PCIREG_SHIFTOUT(rval, __BITS(15, 0))); 4779 pci_conf_print_ssr(PCIREG_SHIFTOUT(rval, __BITS(31, 16))); 4780 4781 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4782 printf(" PCI bus number: 0x%02x\n", 4783 (rval >> 0) & 0xff); 4784 printf(" CardBus bus number: 0x%02x\n", 4785 (rval >> 8) & 0xff); 4786 printf(" Subordinate bus number: 0x%02x\n", 4787 (rval >> 16) & 0xff); 4788 printf(" CardBus latency timer: 0x%02x\n", 4789 (rval >> 24) & 0xff); 4790 4791 /* XXX Print more prettily */ 4792 printf(" CardBus memory region 0:\n"); 4793 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 4794 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 4795 printf(" CardBus memory region 1:\n"); 4796 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 4797 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 4798 printf(" CardBus I/O region 0:\n"); 4799 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 4800 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 4801 printf(" CardBus I/O region 1:\n"); 4802 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 4803 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 4804 4805 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4806 printf(" Interrupt line: 0x%02x\n", 4807 (rval >> 0) & 0xff); 4808 printf(" Interrupt pin: 0x%02x ", 4809 (rval >> 8) & 0xff); 4810 switch ((rval >> 8) & 0xff) { 4811 case PCI_INTERRUPT_PIN_NONE: 4812 printf("(none)"); 4813 break; 4814 case PCI_INTERRUPT_PIN_A: 4815 printf("(pin A)"); 4816 break; 4817 case PCI_INTERRUPT_PIN_B: 4818 printf("(pin B)"); 4819 break; 4820 case PCI_INTERRUPT_PIN_C: 4821 printf("(pin C)"); 4822 break; 4823 case PCI_INTERRUPT_PIN_D: 4824 printf("(pin D)"); 4825 break; 4826 default: 4827 printf("(? ? ?)"); 4828 break; 4829 } 4830 printf("\n"); 4831 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> 16) & 0xffff; 4832 printf(" Bridge control register: 0x%04x\n", rval); 4833 onoff("Parity error response", rval, __BIT(0)); 4834 onoff("SERR# enable", rval, __BIT(1)); 4835 onoff("ISA enable", rval, __BIT(2)); 4836 onoff("VGA enable", rval, __BIT(3)); 4837 onoff("Master abort mode", rval, __BIT(5)); 4838 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 4839 onoff("Functional interrupts routed by ExCA registers", rval, 4840 __BIT(7)); 4841 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 4842 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 4843 onoff("Write posting enable", rval, __BIT(10)); 4844 4845 rval = regs[o2i(0x40)]; 4846 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4847 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4848 4849 #ifdef _KERNEL 4850 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers"); 4851 #else 4852 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 4853 #endif 4854 } 4855 4856 void 4857 pci_conf_print( 4858 #ifdef _KERNEL 4859 pci_chipset_tag_t pc, pcitag_t tag, 4860 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 4861 #else 4862 int pcifd, u_int bus, u_int dev, u_int func 4863 #endif 4864 ) 4865 { 4866 pcireg_t *regs; 4867 int off, capoff, endoff, hdrtype; 4868 const char *type_name; 4869 #ifdef _KERNEL 4870 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 4871 #else 4872 void (*type_printfn)(const pcireg_t *); 4873 #endif 4874 4875 regs = MALLOC(PCI_EXTCONF_SIZE); 4876 4877 printf("PCI configuration registers:\n"); 4878 4879 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 4880 #ifdef _KERNEL 4881 regs[o2i(off)] = pci_conf_read(pc, tag, off); 4882 #else 4883 if (pcibus_conf_read(pcifd, bus, dev, func, off, 4884 ®s[o2i(off)]) == -1) 4885 regs[o2i(off)] = 0; 4886 #endif 4887 } 4888 4889 /* common header */ 4890 printf(" Common header:\n"); 4891 pci_conf_print_regs(regs, 0, 16); 4892 4893 printf("\n"); 4894 #ifdef _KERNEL 4895 pci_conf_print_common(pc, tag, regs); 4896 #else 4897 pci_conf_print_common(regs); 4898 #endif 4899 printf("\n"); 4900 4901 /* type-dependent header */ 4902 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 4903 switch (hdrtype) { /* XXX make a table, eventually */ 4904 case 0: 4905 /* Standard device header */ 4906 type_name = "\"normal\" device"; 4907 type_printfn = &pci_conf_print_type0; 4908 capoff = PCI_CAPLISTPTR_REG; 4909 endoff = 64; 4910 break; 4911 case 1: 4912 /* PCI-PCI bridge header */ 4913 type_name = "PCI-PCI bridge"; 4914 type_printfn = &pci_conf_print_type1; 4915 capoff = PCI_CAPLISTPTR_REG; 4916 endoff = 64; 4917 break; 4918 case 2: 4919 /* PCI-CardBus bridge header */ 4920 type_name = "PCI-CardBus bridge"; 4921 type_printfn = &pci_conf_print_type2; 4922 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 4923 endoff = 72; 4924 break; 4925 default: 4926 type_name = NULL; 4927 type_printfn = 0; 4928 capoff = -1; 4929 endoff = 64; 4930 break; 4931 } 4932 printf(" Type %d ", hdrtype); 4933 if (type_name != NULL) 4934 printf("(%s) ", type_name); 4935 printf("header:\n"); 4936 pci_conf_print_regs(regs, 16, endoff); 4937 printf("\n"); 4938 if (type_printfn) { 4939 #ifdef _KERNEL 4940 (*type_printfn)(pc, tag, regs); 4941 #else 4942 (*type_printfn)(regs); 4943 #endif 4944 } else 4945 printf(" Don't know how to pretty-print type %d header.\n", 4946 hdrtype); 4947 printf("\n"); 4948 4949 /* capability list, if present */ 4950 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4951 && (capoff > 0)) { 4952 #ifdef _KERNEL 4953 pci_conf_print_caplist(pc, tag, regs, capoff); 4954 #else 4955 pci_conf_print_caplist(regs, capoff); 4956 #endif 4957 printf("\n"); 4958 } 4959 4960 /* device-dependent header */ 4961 printf(" Device-dependent header:\n"); 4962 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 4963 #ifdef _KERNEL 4964 printf("\n"); 4965 if (printfn) 4966 (*printfn)(pc, tag, regs); 4967 else 4968 printf(" Don't know how to pretty-print device-dependent header.\n"); 4969 #endif /* _KERNEL */ 4970 4971 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 4972 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 4973 goto out; 4974 4975 printf("\n"); 4976 #ifdef _KERNEL 4977 pci_conf_print_extcaplist(pc, tag, regs); 4978 #else 4979 pci_conf_print_extcaplist(regs); 4980 #endif 4981 printf("\n"); 4982 4983 /* Extended Configuration Space, if present */ 4984 printf(" Extended Configuration Space:\n"); 4985 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 4986 4987 out: 4988 FREE(regs, PCI_EXTCONF_SIZE); 4989 } 4990
Indexes created Tue Sep 23 23:09:58 GMT 2025