pci_subr.c revision 1.232
1 /* $NetBSD: pci_subr.c,v 1.232 2021/10/10 23:28:36 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.232 2021/10/10 23:28:36 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #include <sys/kmem.h> 56 57 #define MALLOC(sz) kmem_alloc(sz, KM_SLEEP) 58 #define FREE(p, sz) kmem_free(p, sz) 59 60 #else 61 #include <pci.h> 62 #include <stdarg.h> 63 #include <stdbool.h> 64 #include <stdio.h> 65 #include <stdlib.h> 66 #include <string.h> 67 68 #define MALLOC(sz) malloc(sz) 69 #define FREE(p, sz) free(p) 70 71 #endif 72 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcidevs.h> 75 #ifdef _KERNEL 76 #include <dev/pci/pcivar.h> 77 #else 78 #include <dev/pci/pci_verbose.h> 79 #include <dev/pci/pcidevs_data.h> 80 #endif 81 82 static int pci_conf_find_cap(const pcireg_t *, unsigned int, int *); 83 static int pci_conf_find_extcap(const pcireg_t *, unsigned int, int *); 84 static void pci_conf_print_pcie_power(uint8_t, unsigned int); 85 #define PCIREG_SHIFTOUT(a, b) ((pcireg_t)__SHIFTOUT((a), (b))) 86 87 #ifdef _KERNEL 88 /* 89 * Common routines used to match a compatible device by its PCI ID code. 90 */ 91 92 const struct device_compatible_entry * 93 pci_compatible_lookup_id(pcireg_t const id, 94 const struct device_compatible_entry *dce) 95 { 96 return device_compatible_lookup_id(id, PCI_COMPAT_EOL_VALUE, dce); 97 } 98 99 const struct device_compatible_entry * 100 pci_compatible_lookup(const struct pci_attach_args * const pa, 101 const struct device_compatible_entry * const dce) 102 { 103 return pci_compatible_lookup_id(pa->pa_id, dce); 104 } 105 106 const struct device_compatible_entry * 107 pci_compatible_lookup_subsys(const struct pci_attach_args * const pa, 108 const struct device_compatible_entry * const dce) 109 { 110 const pcireg_t subsysid = 111 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 112 113 return pci_compatible_lookup_id(subsysid, dce); 114 } 115 116 int 117 pci_compatible_match(const struct pci_attach_args * const pa, 118 const struct device_compatible_entry * const dce) 119 { 120 return pci_compatible_lookup(pa, dce) != NULL; 121 } 122 123 int 124 pci_compatible_match_subsys(const struct pci_attach_args * const pa, 125 const struct device_compatible_entry * const dce) 126 { 127 return pci_compatible_lookup_subsys(pa, dce) != NULL; 128 } 129 #endif /* _KERNEL */ 130 131 /* 132 * Descriptions of known PCI classes and subclasses. 133 * 134 * Subclasses are described in the same way as classes, but have a 135 * NULL subclass pointer. 136 */ 137 struct pci_class { 138 const char *name; 139 u_int val; /* as wide as pci_{,sub}class_t */ 140 const struct pci_class *subclasses; 141 }; 142 143 /* 144 * Class 0x00. 145 * Before rev. 2.0. 146 */ 147 static const struct pci_class pci_subclass_prehistoric[] = { 148 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 149 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 150 { NULL, 0, NULL, }, 151 }; 152 153 /* 154 * Class 0x01. 155 * Mass storage controller 156 */ 157 158 /* ATA programming interface */ 159 static const struct pci_class pci_interface_ata[] = { 160 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 161 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 162 { NULL, 0, NULL, }, 163 }; 164 165 /* SATA programming interface */ 166 static const struct pci_class pci_interface_sata[] = { 167 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 168 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 169 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 170 { NULL, 0, NULL, }, 171 }; 172 173 /* Flash programming interface */ 174 static const struct pci_class pci_interface_nvm[] = { 175 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 176 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 177 { "NVMe I/O", PCI_INTERFACE_NVM_NVME_IO, NULL, }, 178 { "NVMe admin", PCI_INTERFACE_NVM_NVME_ADMIN, NULL, }, 179 { NULL, 0, NULL, }, 180 }; 181 182 /* UFS programming interface */ 183 static const struct pci_class pci_interface_ufs[] = { 184 { "vendor specific", PCI_INTERFACE_UFS_VND, NULL, }, 185 { "UFSHCI", PCI_INTERFACE_UFS_UFSHCI, NULL, }, 186 { NULL, 0, NULL, }, 187 }; 188 189 /* Subclasses */ 190 static const struct pci_class pci_subclass_mass_storage[] = { 191 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 192 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 193 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 194 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 195 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 196 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 197 pci_interface_ata, }, 198 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 199 pci_interface_sata, }, 200 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 201 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 202 pci_interface_nvm, }, 203 { "UFS", PCI_SUBCLASS_MASS_STORAGE_UFS, 204 pci_interface_ufs, }, 205 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 206 { NULL, 0, NULL, }, 207 }; 208 209 /* 210 * Class 0x02. 211 * Network controller. 212 */ 213 static const struct pci_class pci_subclass_network[] = { 214 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 215 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 216 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 217 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 218 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 219 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 220 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 221 { "InfiniBand", PCI_SUBCLASS_NETWORK_INFINIBAND, NULL, }, 222 { "Host fabric", PCI_SUBCLASS_NETWORK_HFC, NULL, }, 223 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 224 { NULL, 0, NULL, }, 225 }; 226 227 /* 228 * Class 0x03. 229 * Display controller. 230 */ 231 232 /* VGA programming interface */ 233 static const struct pci_class pci_interface_vga[] = { 234 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 235 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 236 { NULL, 0, NULL, }, 237 }; 238 /* Subclasses */ 239 static const struct pci_class pci_subclass_display[] = { 240 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 241 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 242 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 243 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 244 { NULL, 0, NULL, }, 245 }; 246 247 /* 248 * Class 0x04. 249 * Multimedia device. 250 */ 251 252 /* HD Audio programming interface */ 253 static const struct pci_class pci_interface_hda[] = { 254 { "HD Audio 1.0", PCI_INTERFACE_HDAUDIO, NULL, }, 255 { "HD Audio 1.0 + vendor ext", PCI_INTERFACE_HDAUDIO_VND, NULL, }, 256 { NULL, 0, NULL, }, 257 }; 258 259 static const struct pci_class pci_subclass_multimedia[] = { 260 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 261 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 262 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 263 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, 264 pci_interface_hda, }, 265 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 266 { NULL, 0, NULL, }, 267 }; 268 269 /* 270 * Class 0x05. 271 * Memory controller. 272 */ 273 static const struct pci_class pci_subclass_memory[] = { 274 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 275 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 276 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 277 { NULL, 0, NULL, }, 278 }; 279 280 /* 281 * Class 0x06. 282 * Bridge device. 283 */ 284 285 /* PCI bridge programming interface */ 286 static const struct pci_class pci_interface_pcibridge[] = { 287 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 288 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 289 { NULL, 0, NULL, }, 290 }; 291 292 /* Semi-transparent PCI-to-PCI bridge programming interface */ 293 static const struct pci_class pci_interface_stpci[] = { 294 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 295 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 296 { NULL, 0, NULL, }, 297 }; 298 299 /* Advanced Switching programming interface */ 300 static const struct pci_class pci_interface_advsw[] = { 301 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 302 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 303 { NULL, 0, NULL, }, 304 }; 305 306 /* Subclasses */ 307 static const struct pci_class pci_subclass_bridge[] = { 308 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 309 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 310 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 311 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 312 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 313 pci_interface_pcibridge, }, 314 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 315 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 316 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 317 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 318 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 319 pci_interface_stpci, }, 320 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 321 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 322 pci_interface_advsw, }, 323 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 324 { NULL, 0, NULL, }, 325 }; 326 327 /* 328 * Class 0x07. 329 * Simple communications controller. 330 */ 331 332 /* Serial controller programming interface */ 333 static const struct pci_class pci_interface_serial[] = { 334 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 335 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 336 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 337 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 338 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 339 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 340 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 341 { NULL, 0, NULL, }, 342 }; 343 344 /* Parallel controller programming interface */ 345 static const struct pci_class pci_interface_parallel[] = { 346 { "", PCI_INTERFACE_PARALLEL, NULL,}, 347 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 348 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 349 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 350 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 351 { NULL, 0, NULL,}, 352 }; 353 354 /* Modem programming interface */ 355 static const struct pci_class pci_interface_modem[] = { 356 { "", PCI_INTERFACE_MODEM, NULL,}, 357 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 358 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 359 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 360 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 361 { NULL, 0, NULL,}, 362 }; 363 364 /* Subclasses */ 365 static const struct pci_class pci_subclass_communications[] = { 366 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 367 pci_interface_serial, }, 368 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 369 pci_interface_parallel, }, 370 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 371 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 372 pci_interface_modem, }, 373 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 374 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 375 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 376 { NULL, 0, NULL,}, 377 }; 378 379 /* 380 * Class 0x08. 381 * Base system peripheral. 382 */ 383 384 /* PIC programming interface */ 385 static const struct pci_class pci_interface_pic[] = { 386 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 387 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 388 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 389 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 390 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 391 { NULL, 0, NULL, }, 392 }; 393 394 /* DMA programming interface */ 395 static const struct pci_class pci_interface_dma[] = { 396 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 397 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 398 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 399 { NULL, 0, NULL, }, 400 }; 401 402 /* Timer programming interface */ 403 static const struct pci_class pci_interface_tmr[] = { 404 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 405 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 406 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 407 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 408 { NULL, 0, NULL, }, 409 }; 410 411 /* RTC programming interface */ 412 static const struct pci_class pci_interface_rtc[] = { 413 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 414 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 415 { NULL, 0, NULL, }, 416 }; 417 418 /* Subclasses */ 419 static const struct pci_class pci_subclass_system[] = { 420 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 421 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 422 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 423 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 424 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 425 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 426 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 427 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 428 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 429 { NULL, 0, NULL, }, 430 }; 431 432 /* 433 * Class 0x09. 434 * Input device. 435 */ 436 437 /* Gameport programming interface */ 438 static const struct pci_class pci_interface_game[] = { 439 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 440 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 441 { NULL, 0, NULL, }, 442 }; 443 444 /* Subclasses */ 445 static const struct pci_class pci_subclass_input[] = { 446 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 447 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 448 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 449 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 450 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 451 pci_interface_game, }, 452 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 453 { NULL, 0, NULL, }, 454 }; 455 456 /* 457 * Class 0x0a. 458 * Docking station. 459 */ 460 static const struct pci_class pci_subclass_dock[] = { 461 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 462 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 463 { NULL, 0, NULL, }, 464 }; 465 466 /* 467 * Class 0x0b. 468 * Processor. 469 */ 470 static const struct pci_class pci_subclass_processor[] = { 471 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 472 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 473 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 474 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 475 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 476 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 477 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 478 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 479 { NULL, 0, NULL, }, 480 }; 481 482 /* 483 * Class 0x0c. 484 * Serial bus controller. 485 */ 486 487 /* IEEE1394 programming interface */ 488 static const struct pci_class pci_interface_ieee1394[] = { 489 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 490 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 491 { NULL, 0, NULL,}, 492 }; 493 494 /* USB programming interface */ 495 static const struct pci_class pci_interface_usb[] = { 496 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 497 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 498 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 499 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 500 { "USB4 HCI", PCI_INTERFACE_USB_USB4HCI, NULL, }, 501 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 502 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 503 { NULL, 0, NULL, }, 504 }; 505 506 /* IPMI programming interface */ 507 static const struct pci_class pci_interface_ipmi[] = { 508 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL, }, 509 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL, }, 510 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL, }, 511 { NULL, 0, NULL, }, 512 }; 513 514 /* Subclasses */ 515 static const struct pci_class pci_subclass_serialbus[] = { 516 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 517 pci_interface_ieee1394, }, 518 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 519 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 520 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 521 pci_interface_usb, }, 522 /* XXX Fiber Channel/_FIBRECHANNEL */ 523 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 524 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 525 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 526 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 527 pci_interface_ipmi, }, 528 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 529 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 530 { "MIPI I3C", PCI_SUBCLASS_SERIALBUS_MIPI_I3C, NULL, }, 531 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 532 { NULL, 0, NULL, }, 533 }; 534 535 /* 536 * Class 0x0d. 537 * Wireless Controller. 538 */ 539 static const struct pci_class pci_subclass_wireless[] = { 540 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 541 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 542 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 543 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 544 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 545 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 546 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 547 { "Cellular", PCI_SUBCLASS_WIRELESS_CELL, NULL, }, 548 { "Cellular + Ethernet", PCI_SUBCLASS_WIRELESS_CELL_E, NULL, }, 549 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 550 { NULL, 0, NULL, }, 551 }; 552 553 /* 554 * Class 0x0e. 555 * Intelligent IO controller. 556 */ 557 558 /* Intelligent IO programming interface */ 559 static const struct pci_class pci_interface_i2o[] = { 560 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL, }, 561 { NULL, 0, NULL, }, 562 }; 563 564 /* Subclasses */ 565 static const struct pci_class pci_subclass_i2o[] = { 566 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 567 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 568 { NULL, 0, NULL, }, 569 }; 570 571 /* 572 * Class 0x0f. 573 * Satellite communication controller. 574 */ 575 static const struct pci_class pci_subclass_satcom[] = { 576 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 577 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 578 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 579 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 580 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 581 { NULL, 0, NULL, }, 582 }; 583 584 /* 585 * Class 0x10. 586 * Encryption/Decryption controller. 587 */ 588 static const struct pci_class pci_subclass_crypto[] = { 589 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 590 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 591 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 592 { NULL, 0, NULL, }, 593 }; 594 595 /* 596 * Class 0x11. 597 * Data aquuisition and signal processing controller. 598 */ 599 static const struct pci_class pci_subclass_dasp[] = { 600 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 601 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 602 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 603 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 604 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 605 { NULL, 0, NULL, }, 606 }; 607 608 /* List of classes */ 609 static const struct pci_class pci_classes[] = { 610 { "prehistoric", PCI_CLASS_PREHISTORIC, 611 pci_subclass_prehistoric, }, 612 { "mass storage", PCI_CLASS_MASS_STORAGE, 613 pci_subclass_mass_storage, }, 614 { "network", PCI_CLASS_NETWORK, 615 pci_subclass_network, }, 616 { "display", PCI_CLASS_DISPLAY, 617 pci_subclass_display, }, 618 { "multimedia", PCI_CLASS_MULTIMEDIA, 619 pci_subclass_multimedia, }, 620 { "memory", PCI_CLASS_MEMORY, 621 pci_subclass_memory, }, 622 { "bridge", PCI_CLASS_BRIDGE, 623 pci_subclass_bridge, }, 624 { "communications", PCI_CLASS_COMMUNICATIONS, 625 pci_subclass_communications, }, 626 { "system", PCI_CLASS_SYSTEM, 627 pci_subclass_system, }, 628 { "input", PCI_CLASS_INPUT, 629 pci_subclass_input, }, 630 { "dock", PCI_CLASS_DOCK, 631 pci_subclass_dock, }, 632 { "processor", PCI_CLASS_PROCESSOR, 633 pci_subclass_processor, }, 634 { "serial bus", PCI_CLASS_SERIALBUS, 635 pci_subclass_serialbus, }, 636 { "wireless", PCI_CLASS_WIRELESS, 637 pci_subclass_wireless, }, 638 { "I2O", PCI_CLASS_I2O, 639 pci_subclass_i2o, }, 640 { "satellite comm", PCI_CLASS_SATCOM, 641 pci_subclass_satcom, }, 642 { "crypto", PCI_CLASS_CRYPTO, 643 pci_subclass_crypto, }, 644 { "DASP", PCI_CLASS_DASP, 645 pci_subclass_dasp, }, 646 { "processing accelerators", PCI_CLASS_ACCEL, 647 NULL, }, 648 { "non-essential instrumentation", PCI_CLASS_INSTRUMENT, 649 NULL, }, 650 { "undefined", PCI_CLASS_UNDEFINED, 651 NULL, }, 652 { NULL, 0, 653 NULL, }, 654 }; 655 656 DEV_VERBOSE_DEFINE(pci); 657 658 /* 659 * Append a formatted string to dest without writing more than len 660 * characters (including the trailing NUL character). dest and len 661 * are updated for use in subsequent calls to snappendf(). 662 * 663 * Returns 0 on success, a negative value if vnsprintf() fails, or 664 * a positive value if the dest buffer would have overflowed. 665 */ 666 667 static int __printflike(3, 4) 668 snappendf(char **dest, size_t *len, const char * restrict fmt, ...) 669 { 670 va_list ap; 671 int count; 672 673 va_start(ap, fmt); 674 count = vsnprintf(*dest, *len, fmt, ap); 675 va_end(ap); 676 677 /* Let vsnprintf() errors bubble up to caller */ 678 if (count < 0 || *len == 0) 679 return count; 680 681 /* Handle overflow */ 682 if ((size_t)count >= *len) { 683 *dest += *len - 1; 684 *len = 1; 685 return 1; 686 } 687 688 /* Update dest & len to point at trailing NUL */ 689 *dest += count; 690 *len -= count; 691 692 return 0; 693 } 694 695 void 696 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 697 size_t l) 698 { 699 pci_class_t class; 700 pci_subclass_t subclass; 701 pci_interface_t interface; 702 pci_revision_t revision; 703 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 704 const struct pci_class *classp, *subclassp, *interfacep; 705 706 class = PCI_CLASS(class_reg); 707 subclass = PCI_SUBCLASS(class_reg); 708 interface = PCI_INTERFACE(class_reg); 709 revision = PCI_REVISION(class_reg); 710 711 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 712 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 713 PCI_PRODUCT(id_reg)); 714 715 classp = pci_classes; 716 while (classp->name != NULL) { 717 if (class == classp->val) 718 break; 719 classp++; 720 } 721 722 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 723 while (subclassp && subclassp->name != NULL) { 724 if (subclass == subclassp->val) 725 break; 726 subclassp++; 727 } 728 729 interfacep = (subclassp && subclassp->name != NULL) ? 730 subclassp->subclasses : NULL; 731 while (interfacep && interfacep->name != NULL) { 732 if (interface == interfacep->val) 733 break; 734 interfacep++; 735 } 736 737 (void)snappendf(&cp, &l, "%s %s", vendor, product); 738 if (showclass) { 739 (void)snappendf(&cp, &l, " ("); 740 if (classp->name == NULL) 741 (void)snappendf(&cp, &l, 742 "class 0x%02x, subclass 0x%02x", 743 class, subclass); 744 else { 745 if (subclassp == NULL || subclassp->name == NULL) 746 (void)snappendf(&cp, &l, 747 "%s, subclass 0x%02x", 748 classp->name, subclass); 749 else 750 (void)snappendf(&cp, &l, "%s %s", 751 subclassp->name, classp->name); 752 } 753 if ((interfacep == NULL) || (interfacep->name == NULL)) { 754 if (interface != 0) 755 (void)snappendf(&cp, &l, ", interface 0x%02x", 756 interface); 757 } else if (strncmp(interfacep->name, "", 1) != 0) 758 (void)snappendf(&cp, &l, ", %s", interfacep->name); 759 if (revision != 0) 760 (void)snappendf(&cp, &l, ", revision 0x%02x", revision); 761 (void)snappendf(&cp, &l, ")"); 762 } 763 } 764 765 #ifdef _KERNEL 766 void 767 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 768 const char *known, int addrev) 769 { 770 char devinfo[256]; 771 772 if (known) { 773 aprint_normal(": %s", known); 774 if (addrev) 775 aprint_normal(" (rev. 0x%02x)", 776 PCI_REVISION(pa->pa_class)); 777 aprint_normal("\n"); 778 } else { 779 pci_devinfo(pa->pa_id, pa->pa_class, 0, 780 devinfo, sizeof(devinfo)); 781 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 782 PCI_REVISION(pa->pa_class)); 783 } 784 if (naive) 785 aprint_naive(": %s\n", naive); 786 else 787 aprint_naive("\n"); 788 } 789 #endif 790 791 /* 792 * Print out most of the PCI configuration registers. Typically used 793 * in a device attach routine like this: 794 * 795 * #ifdef MYDEV_DEBUG 796 * printf("%s: ", device_xname(sc->sc_dev)); 797 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 798 * #endif 799 */ 800 801 #define i2o(i) ((i) * 4) 802 #define o2i(o) ((o) / 4) 803 #define onoff2(str, rval, bit, onstr, offstr) \ 804 /*CONSTCOND*/ \ 805 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 806 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 807 808 static void 809 pci_conf_print_common( 810 #ifdef _KERNEL 811 pci_chipset_tag_t pc, pcitag_t tag, 812 #endif 813 const pcireg_t *regs) 814 { 815 pci_class_t class; 816 pci_subclass_t subclass; 817 pci_interface_t interface; 818 pci_revision_t revision; 819 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 820 const struct pci_class *classp, *subclassp, *interfacep; 821 const char *name; 822 pcireg_t rval; 823 unsigned int num; 824 825 rval = regs[o2i(PCI_CLASS_REG)]; 826 class = PCI_CLASS(rval); 827 subclass = PCI_SUBCLASS(rval); 828 interface = PCI_INTERFACE(rval); 829 revision = PCI_REVISION(rval); 830 831 rval = regs[o2i(PCI_ID_REG)]; 832 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 833 if (name) 834 printf(" Vendor Name: %s (0x%04x)\n", name, 835 PCI_VENDOR(rval)); 836 else 837 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 838 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 839 PCI_PRODUCT(rval)); 840 if (name) 841 printf(" Device Name: %s (0x%04x)\n", name, 842 PCI_PRODUCT(rval)); 843 else 844 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 845 846 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 847 848 printf(" Command register: 0x%04x\n", rval & 0xffff); 849 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 850 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 851 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 852 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 853 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 854 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 855 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 856 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 857 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 858 onoff("Fast back-to-back transactions", rval, 859 PCI_COMMAND_BACKTOBACK_ENABLE); 860 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 861 862 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 863 onoff("Immediate Readiness", rval, PCI_STATUS_IMMD_READNESS); 864 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 865 "inactive"); 866 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 867 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 868 onoff("User Definable Features (UDF) support", rval, 869 PCI_STATUS_UDF_SUPPORT); 870 onoff("Fast back-to-back capable", rval, 871 PCI_STATUS_BACKTOBACK_SUPPORT); 872 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 873 874 printf(" DEVSEL timing: "); 875 switch (rval & PCI_STATUS_DEVSEL_MASK) { 876 case PCI_STATUS_DEVSEL_FAST: 877 printf("fast"); 878 break; 879 case PCI_STATUS_DEVSEL_MEDIUM: 880 printf("medium"); 881 break; 882 case PCI_STATUS_DEVSEL_SLOW: 883 printf("slow"); 884 break; 885 default: 886 printf("unknown/reserved"); /* XXX */ 887 break; 888 } 889 printf(" (0x%x)\n", PCIREG_SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK)); 890 891 onoff("Slave signaled Target Abort", rval, 892 PCI_STATUS_TARGET_TARGET_ABORT); 893 onoff("Master received Target Abort", rval, 894 PCI_STATUS_MASTER_TARGET_ABORT); 895 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 896 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 897 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 898 899 rval = regs[o2i(PCI_CLASS_REG)]; 900 for (classp = pci_classes; classp->name != NULL; classp++) { 901 if (class == classp->val) 902 break; 903 } 904 905 /* 906 * ECN: Change Root Complex Event Collector Class Code 907 * Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type 908 * in PCIe extend capability to know whether it's RCEC or IOMMU. 909 */ 910 if ((class == PCI_CLASS_SYSTEM) 911 && (subclass == PCI_SUBCLASS_SYSTEM_IOMMU)) { 912 int pcie_capoff; 913 pcireg_t reg; 914 915 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 916 reg = regs[o2i(pcie_capoff + PCIE_XCAP)]; 917 if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_RC_EVNTC) 918 subclass = PCI_SUBCLASS_SYSTEM_RCEC; 919 } 920 } 921 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 922 while (subclassp && subclassp->name != NULL) { 923 if (subclass == subclassp->val) 924 break; 925 subclassp++; 926 } 927 928 interfacep = (subclassp && subclassp->name != NULL) ? 929 subclassp->subclasses : NULL; 930 while (interfacep && interfacep->name != NULL) { 931 if (interface == interfacep->val) 932 break; 933 interfacep++; 934 } 935 936 if (classp->name != NULL) 937 printf(" Class Name: %s (0x%02x)\n", classp->name, class); 938 else 939 printf(" Class ID: 0x%02x\n", class); 940 if (subclassp != NULL && subclassp->name != NULL) 941 printf(" Subclass Name: %s (0x%02x)\n", 942 subclassp->name, PCI_SUBCLASS(rval)); 943 else 944 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 945 if ((interfacep != NULL) && (interfacep->name != NULL) 946 && (strncmp(interfacep->name, "", 1) != 0)) 947 printf(" Interface Name: %s (0x%02x)\n", 948 interfacep->name, interface); 949 else 950 printf(" Interface: 0x%02x\n", interface); 951 printf(" Revision ID: 0x%02x\n", revision); 952 953 rval = regs[o2i(PCI_BHLC_REG)]; 954 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 955 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 956 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 957 PCI_HDRTYPE(rval)); 958 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 959 num = PCI_CACHELINE(rval); 960 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 961 } 962 963 static int 964 pci_conf_print_bar( 965 #ifdef _KERNEL 966 pci_chipset_tag_t pc, pcitag_t tag, 967 #endif 968 const pcireg_t *regs, int reg, const char *name) 969 { 970 int width; 971 pcireg_t rval, rval64h; 972 bool ioen, memen; 973 #ifdef _KERNEL 974 pcireg_t mask, mask64h = 0; 975 #endif 976 977 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 978 ioen = rval & PCI_COMMAND_IO_ENABLE; 979 memen = rval & PCI_COMMAND_MEM_ENABLE; 980 981 width = 4; 982 /* 983 * Section 6.2.5.1, `Address Maps', tells us that: 984 * 985 * 1) The builtin software should have already mapped the 986 * device in a reasonable way. 987 * 988 * 2) A device which wants 2^n bytes of memory will hardwire 989 * the bottom n bits of the address to 0. As recommended, 990 * we write all 1s and see what we get back. 991 */ 992 993 rval = regs[o2i(reg)]; 994 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 995 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 996 rval64h = regs[o2i(reg + 4)]; 997 width = 8; 998 } else 999 rval64h = 0; 1000 1001 #ifdef _KERNEL 1002 if (rval != 0 && memen) { 1003 int s; 1004 1005 /* 1006 * The following sequence seems to make some devices 1007 * (e.g. host bus bridges, which don't normally 1008 * have their space mapped) very unhappy, to 1009 * the point of crashing the system. 1010 * 1011 * Therefore, if the mapping register is zero to 1012 * start out with, don't bother trying. 1013 */ 1014 s = splhigh(); 1015 pci_conf_write(pc, tag, reg, 0xffffffff); 1016 mask = pci_conf_read(pc, tag, reg); 1017 pci_conf_write(pc, tag, reg, rval); 1018 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 1019 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 1020 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 1021 mask64h = pci_conf_read(pc, tag, reg + 4); 1022 pci_conf_write(pc, tag, reg + 4, rval64h); 1023 } 1024 splx(s); 1025 } else 1026 mask = mask64h = 0; 1027 #endif /* _KERNEL */ 1028 1029 printf(" Base address register at 0x%02x", reg); 1030 if (name) 1031 printf(" (%s)", name); 1032 printf("\n "); 1033 if (rval == 0) { 1034 printf("not implemented\n"); 1035 return width; 1036 } 1037 printf("type: "); 1038 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 1039 const char *type, *prefetch; 1040 1041 switch (PCI_MAPREG_MEM_TYPE(rval)) { 1042 case PCI_MAPREG_MEM_TYPE_32BIT: 1043 type = "32-bit"; 1044 break; 1045 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 1046 type = "32-bit-1M"; 1047 break; 1048 case PCI_MAPREG_MEM_TYPE_64BIT: 1049 type = "64-bit"; 1050 break; 1051 default: 1052 type = "unknown (XXX)"; 1053 break; 1054 } 1055 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 1056 prefetch = ""; 1057 else 1058 prefetch = "non"; 1059 printf("%s %sprefetchable memory\n", type, prefetch); 1060 switch (PCI_MAPREG_MEM_TYPE(rval)) { 1061 case PCI_MAPREG_MEM_TYPE_64BIT: 1062 printf(" base: 0x%016llx", 1063 PCI_MAPREG_MEM64_ADDR( 1064 ((((long long) rval64h) << 32) | rval))); 1065 if (!memen) 1066 printf(", disabled"); 1067 printf("\n"); 1068 #ifdef _KERNEL 1069 printf(" size: 0x%016llx\n", 1070 PCI_MAPREG_MEM64_SIZE( 1071 ((((long long) mask64h) << 32) | mask))); 1072 #endif 1073 break; 1074 case PCI_MAPREG_MEM_TYPE_32BIT: 1075 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 1076 default: 1077 printf(" base: 0x%08x", 1078 PCI_MAPREG_MEM_ADDR(rval)); 1079 if (!memen) 1080 printf(", disabled"); 1081 printf("\n"); 1082 #ifdef _KERNEL 1083 printf(" size: 0x%08x\n", 1084 PCI_MAPREG_MEM_SIZE(mask)); 1085 #endif 1086 break; 1087 } 1088 } else { 1089 #ifdef _KERNEL 1090 if (ioen) 1091 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 1092 #endif 1093 printf("I/O\n"); 1094 printf(" base: 0x%08x", PCI_MAPREG_IO_ADDR(rval)); 1095 if (!ioen) 1096 printf(", disabled"); 1097 printf("\n"); 1098 #ifdef _KERNEL 1099 printf(" size: 0x%08x\n", PCI_MAPREG_IO_SIZE(mask)); 1100 #endif 1101 } 1102 1103 return width; 1104 } 1105 1106 static void 1107 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 1108 { 1109 int off, needaddr, neednl; 1110 1111 needaddr = 1; 1112 neednl = 0; 1113 for (off = first; off < pastlast; off += 4) { 1114 if ((off % 16) == 0 || needaddr) { 1115 printf(" 0x%02x:", off); 1116 needaddr = 0; 1117 } 1118 printf(" 0x%08x", regs[o2i(off)]); 1119 neednl = 1; 1120 if ((off % 16) == 12) { 1121 printf("\n"); 1122 neednl = 0; 1123 } 1124 } 1125 if (neednl) 1126 printf("\n"); 1127 } 1128 1129 static const char * 1130 pci_conf_print_agp_calcycle(uint8_t cal) 1131 { 1132 1133 switch (cal) { 1134 case 0x0: 1135 return "4ms"; 1136 case 0x1: 1137 return "16ms"; 1138 case 0x2: 1139 return "64ms"; 1140 case 0x3: 1141 return "256ms"; 1142 case 0x7: 1143 return "Calibration Cycle Not Needed"; 1144 default: 1145 return "(reserved)"; 1146 } 1147 } 1148 1149 static void 1150 pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3) 1151 { 1152 if (isagp3) { 1153 /* AGP 3.0 */ 1154 if (reg & AGP_MODE_V3_RATE_4x) 1155 printf("x4"); 1156 if (reg & AGP_MODE_V3_RATE_8x) 1157 printf("x8"); 1158 } else { 1159 /* AGP 2.0 */ 1160 if (reg & AGP_MODE_V2_RATE_1x) 1161 printf("x1"); 1162 if (reg & AGP_MODE_V2_RATE_2x) 1163 printf("x2"); 1164 if (reg & AGP_MODE_V2_RATE_4x) 1165 printf("x4"); 1166 } 1167 printf("\n"); 1168 } 1169 1170 static void 1171 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1172 { 1173 pcireg_t rval; 1174 bool isagp3; 1175 1176 printf("\n AGP Capabilities Register\n"); 1177 1178 rval = regs[o2i(capoff)]; 1179 printf(" Revision: %d.%d\n", 1180 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1181 1182 rval = regs[o2i(capoff + PCI_AGP_STATUS)]; 1183 printf(" Status register: 0x%04x\n", rval); 1184 printf(" RQ: %u\n", 1185 PCIREG_SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1186 printf(" ARQSZ: %u\n", 1187 PCIREG_SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1188 printf(" CAL cycle: %s\n", 1189 pci_conf_print_agp_calcycle(PCIREG_SHIFTOUT(rval, AGP_MODE_CAL))); 1190 onoff("SBA", rval, AGP_MODE_SBA); 1191 onoff("htrans#", rval, AGP_MODE_HTRANS); 1192 onoff("Over 4G", rval, AGP_MODE_4G); 1193 onoff("Fast Write", rval, AGP_MODE_FW); 1194 onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3); 1195 isagp3 = rval & AGP_MODE_MODE_3; 1196 printf(" Data Rate Support: "); 1197 pci_conf_print_agp_datarate(rval, isagp3); 1198 1199 rval = regs[o2i(capoff + PCI_AGP_COMMAND)]; 1200 printf(" Command register: 0x%08x\n", rval); 1201 printf(" PRQ: %u\n", 1202 PCIREG_SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1203 printf(" PARQSZ: %u\n", 1204 PCIREG_SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1205 printf(" PCAL cycle: %s\n", 1206 pci_conf_print_agp_calcycle(PCIREG_SHIFTOUT(rval, AGP_MODE_CAL))); 1207 onoff("SBA", rval, AGP_MODE_SBA); 1208 onoff("AGP", rval, AGP_MODE_AGP); 1209 onoff("Over 4G", rval, AGP_MODE_4G); 1210 onoff("Fast Write", rval, AGP_MODE_FW); 1211 if (isagp3) { 1212 printf(" Data Rate Enable: "); 1213 /* 1214 * The Data Rate Enable bits are used only on 3.0 and the 1215 * Command register has no AGP_MODE_MODE_3 bit, so pass the 1216 * flag to print correctly. 1217 */ 1218 pci_conf_print_agp_datarate(rval, isagp3); 1219 } 1220 } 1221 1222 static const char * 1223 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1224 { 1225 1226 switch ((caps >> 6) & 7) { 1227 case 0: return "self-powered"; 1228 case 1: return "55 mA"; 1229 case 2: return "100 mA"; 1230 case 3: return "160 mA"; 1231 case 4: return "220 mA"; 1232 case 5: return "270 mA"; 1233 case 6: return "320 mA"; 1234 case 7: 1235 default: return "375 mA"; 1236 } 1237 } 1238 1239 static const char * 1240 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1241 { 1242 static const char unk[] = "unknown"; 1243 static const char *pmrev[8] = { 1244 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1245 }; 1246 if (val > 7) 1247 return unk; 1248 return pmrev[val]; 1249 } 1250 1251 static void 1252 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1253 { 1254 uint16_t caps, pmcsr; 1255 1256 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1257 pmcsr = regs[o2i(capoff + PCI_PMCSR)]; 1258 1259 printf("\n PCI Power Management Capabilities Register\n"); 1260 1261 printf(" Capabilities register: 0x%04x\n", caps); 1262 printf(" Version: %s\n", 1263 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1264 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1265 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1266 printf(" 3.3V auxiliary current: %s\n", 1267 pci_conf_print_pcipm_cap_aux(caps)); 1268 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1269 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1270 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1271 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1272 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1273 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1274 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1275 1276 printf(" Control/status register: 0x%08x\n", pmcsr); 1277 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1278 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1279 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1280 printf(" PME# assertion: %sabled\n", 1281 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1282 printf(" Data Select: %d\n", 1283 PCIREG_SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK)); 1284 printf(" Data Scale: %d\n", 1285 PCIREG_SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK)); 1286 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1287 printf(" Bridge Support Extensions register: 0x%02x\n", 1288 (pmcsr >> 16) & 0xff); 1289 onoff("B2/B3 support", pmcsr, PCI_PMCSR_B2B3_SUPPORT); 1290 onoff("Bus Power/Clock Control Enable", pmcsr, PCI_PMCSR_BPCC_EN); 1291 printf(" Data register: 0x%02x\n", 1292 PCIREG_SHIFTOUT(pmcsr, PCI_PMCSR_DATA)); 1293 } 1294 1295 /* XXX pci_conf_print_vpd_cap */ 1296 /* XXX pci_conf_print_slotid_cap */ 1297 1298 static void 1299 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1300 { 1301 uint32_t ctl, mmc, mme; 1302 1303 regs += o2i(capoff); 1304 ctl = *regs++; 1305 mmc = PCIREG_SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1306 mme = PCIREG_SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1307 1308 printf("\n PCI Message Signaled Interrupt\n"); 1309 1310 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1311 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1312 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1313 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1314 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1315 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1316 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1317 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1318 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP); 1319 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN); 1320 printf(" Message Address %sregister: 0x%08x\n", 1321 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1322 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1323 printf(" Message Address %sregister: 0x%08x\n", 1324 "(upper) ", *regs++); 1325 } 1326 printf(" Message Data register: "); 1327 if (ctl & PCI_MSI_CTL_EXTMDATA_CAP) 1328 printf("0x%08x\n", *regs); 1329 else 1330 printf("0x%04x\n", *regs & 0xffff); 1331 regs++; 1332 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1333 printf(" Vector Mask register: 0x%08x\n", *regs++); 1334 printf(" Vector Pending register: 0x%08x\n", *regs++); 1335 } 1336 } 1337 1338 /* XXX pci_conf_print_cpci_hostwap_cap */ 1339 1340 /* 1341 * For both command register and status register. 1342 * The argument "idx" is index number (0 to 7). 1343 */ 1344 static int 1345 pcix_split_trans(unsigned int idx) 1346 { 1347 static int table[8] = { 1348 1, 2, 3, 4, 8, 12, 16, 32 1349 }; 1350 1351 if (idx >= __arraycount(table)) 1352 return -1; 1353 return table[idx]; 1354 } 1355 1356 static void 1357 pci_conf_print_pcix_cap_2ndbusmode(int num) 1358 { 1359 const char *maxfreq, *maxperiod; 1360 1361 printf(" Mode: "); 1362 if (num <= 0x07) 1363 printf("PCI-X Mode 1\n"); 1364 else if (num <= 0x0b) 1365 printf("PCI-X 266 (Mode 2)\n"); 1366 else 1367 printf("PCI-X 533 (Mode 2)\n"); 1368 1369 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1370 switch (num & 0x03) { 1371 default: 1372 case 0: 1373 maxfreq = "N/A"; 1374 maxperiod = "N/A"; 1375 break; 1376 case 1: 1377 maxfreq = "66MHz"; 1378 maxperiod = "15ns"; 1379 break; 1380 case 2: 1381 maxfreq = "100MHz"; 1382 maxperiod = "10ns"; 1383 break; 1384 case 3: 1385 maxfreq = "133MHz"; 1386 maxperiod = "7.5ns"; 1387 break; 1388 } 1389 printf(" Max Clock Freq: %s\n", maxfreq); 1390 printf(" Min Clock Period: %s\n", maxperiod); 1391 } 1392 1393 static void 1394 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1395 { 1396 pcireg_t reg; 1397 int isbridge; 1398 int i; 1399 1400 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1401 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1402 printf("\n PCI-X %s Capabilities Register\n", 1403 isbridge ? "Bridge" : "Non-bridge"); 1404 1405 reg = regs[o2i(capoff)]; 1406 if (isbridge != 0) { 1407 printf(" Secondary status register: 0x%04x\n", 1408 (reg & 0xffff0000) >> 16); 1409 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1410 onoff("133MHz capable", reg, PCIX_STATUS_133); 1411 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1412 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1413 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1414 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1415 pci_conf_print_pcix_cap_2ndbusmode( 1416 PCIREG_SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1417 printf(" Version: 0x%x\n", 1418 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1419 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1420 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1421 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1422 } else { 1423 printf(" Command register: 0x%04x\n", 1424 (reg & 0xffff0000) >> 16); 1425 onoff("Data Parity Error Recovery", reg, 1426 PCIX_CMD_PERR_RECOVER); 1427 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1428 printf(" Maximum Burst Read Count: %u\n", 1429 PCIX_CMD_BYTECNT(reg)); 1430 printf(" Maximum Split Transactions: %d\n", 1431 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1432 >> PCIX_CMD_SPLTRANS_SHIFT)); 1433 } 1434 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1435 printf(" %sStatus register: 0x%08x\n", 1436 isbridge ? "Bridge " : "", reg); 1437 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1438 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1439 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1440 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1441 onoff("133MHz capable", reg, PCIX_STATUS_133); 1442 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1443 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1444 if (isbridge != 0) { 1445 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1446 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1447 } else { 1448 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1449 "bridge device", "simple device"); 1450 printf(" Designed max memory read byte count: %d\n", 1451 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1452 >> PCIX_STATUS_MAXB_SHIFT)); 1453 printf(" Designed max outstanding split transaction: %d\n", 1454 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1455 >> PCIX_STATUS_MAXST_SHIFT)); 1456 printf(" MAX cumulative Read Size: %u\n", 1457 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1458 onoff("Received split completion error", reg, 1459 PCIX_STATUS_SCERR); 1460 } 1461 onoff("266MHz capable", reg, PCIX_STATUS_266); 1462 onoff("533MHz capable", reg, PCIX_STATUS_533); 1463 1464 if (isbridge == 0) 1465 return; 1466 1467 /* Only for bridge */ 1468 for (i = 0; i < 2; i++) { 1469 reg = regs[o2i(capoff + PCIX_BRIDGE_UP_STCR + (4 * i))]; 1470 printf(" %s split transaction control register: 0x%08x\n", 1471 (i == 0) ? "Upstream" : "Downstream", reg); 1472 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1473 printf(" Commitment Limit: %d\n", 1474 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1475 } 1476 } 1477 1478 /* pci_conf_print_ht_slave_cap */ 1479 /* pci_conf_print_ht_host_cap */ 1480 /* pci_conf_print_ht_switch_cap */ 1481 /* pci_conf_print_ht_intr_cap */ 1482 /* pci_conf_print_ht_revid_cap */ 1483 /* pci_conf_print_ht_unitid_cap */ 1484 /* pci_conf_print_ht_extcnf_cap */ 1485 /* pci_conf_print_ht_addrmap_cap */ 1486 /* pci_conf_print_ht_msimap_cap */ 1487 1488 static void 1489 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1490 { 1491 pcireg_t val; 1492 uint32_t lo, hi; 1493 1494 /* 1495 * Print the rest of the command register bits. Others are 1496 * printed in pci_conf_print_ht_cap(). 1497 */ 1498 val = regs[o2i(capoff + PCI_HT_CMD)]; 1499 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1500 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1501 1502 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1503 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1504 printf(" Address Low register: 0x%08x\n", lo); 1505 printf(" Address high register: 0x%08x\n", hi); 1506 printf(" Address: 0x%016" PRIx64 "\n", 1507 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1508 } 1509 1510 /* pci_conf_print_ht_droute_cap */ 1511 /* pci_conf_print_ht_vcset_cap */ 1512 /* pci_conf_print_ht_retry_cap */ 1513 /* pci_conf_print_ht_x86enc_cap */ 1514 /* pci_conf_print_ht_gen3_cap */ 1515 /* pci_conf_print_ht_fle_cap */ 1516 /* pci_conf_print_ht_pm_cap */ 1517 /* pci_conf_print_ht_hnc_cap */ 1518 1519 static const struct ht_types { 1520 pcireg_t cap; 1521 const char *name; 1522 void (*printfunc)(const pcireg_t *, int); 1523 } ht_captab[] = { 1524 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1525 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1526 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1527 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1528 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1529 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1530 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1531 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1532 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1533 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1534 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1535 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1536 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1537 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1538 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1539 {PCI_HT_CAP_PM, "Power Management", NULL }, 1540 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1541 }; 1542 1543 static void 1544 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1545 { 1546 pcireg_t val, foundcap; 1547 unsigned int off; 1548 1549 val = regs[o2i(capoff + PCI_HT_CMD)]; 1550 1551 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1552 1553 printf(" Command register: 0x%04x\n", val >> 16); 1554 foundcap = PCI_HT_CAP(val); 1555 for (off = 0; off < __arraycount(ht_captab); off++) { 1556 if (ht_captab[off].cap == foundcap) 1557 break; 1558 } 1559 printf(" Capability Type: 0x%02x ", foundcap); 1560 if (off >= __arraycount(ht_captab)) { 1561 printf("(unknown)\n"); 1562 return; 1563 } 1564 printf("(%s)\n", ht_captab[off].name); 1565 if (ht_captab[off].printfunc != NULL) 1566 ht_captab[off].printfunc(regs, capoff); 1567 } 1568 1569 static void 1570 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1571 { 1572 uint16_t caps; 1573 1574 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1575 1576 printf("\n PCI Vendor Specific Capabilities Register\n"); 1577 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1578 } 1579 1580 static void 1581 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1582 { 1583 pcireg_t val; 1584 1585 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1586 1587 printf("\n Debugport Capability Register\n"); 1588 printf(" Debug base Register: 0x%04x\n", 1589 val >> PCI_DEBUG_BASER_SHIFT); 1590 printf(" port offset: 0x%04x\n", 1591 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1592 printf(" BAR number: %u\n", 1593 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1594 } 1595 1596 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1597 /* XXX pci_conf_print_hotplug_cap */ 1598 1599 static void 1600 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1601 { 1602 pcireg_t reg; 1603 1604 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1605 1606 printf("\n Subsystem ID Capability Register\n"); 1607 printf(" Subsystem ID: 0x%08x\n", reg); 1608 } 1609 1610 /* XXX pci_conf_print_agp8_cap */ 1611 static void 1612 pci_conf_print_secure_cap(const pcireg_t *regs, int capoff) 1613 { 1614 pcireg_t reg, reg2, val; 1615 bool havemisc1; 1616 1617 printf("\n Secure Capability Register\n"); 1618 reg = regs[o2i(capoff + PCI_SECURE_CAP)]; 1619 printf(" Capability Register: 0x%04x\n", reg >> 16); 1620 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_CAP_TYPE); 1621 printf(" Capability block type: "); 1622 /* I know IOMMU Only */ 1623 if (val == PCI_SECURE_CAP_TYPE_IOMMU) 1624 printf("IOMMU\n"); 1625 else { 1626 printf("0x%x(unknown)\n", val); 1627 return; 1628 } 1629 1630 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_CAP_REV); 1631 printf(" Capability revision: 0x%02x ", val); 1632 if (val == PCI_SECURE_CAP_REV_IOMMU) 1633 printf("(IOMMU)\n"); 1634 else { 1635 printf("(unknown)\n"); 1636 return; 1637 } 1638 onoff("IOTLB support", reg, PCI_SECURE_CAP_IOTLBSUP); 1639 onoff("HyperTransport tunnel translation support", reg, 1640 PCI_SECURE_CAP_HTTUNNEL); 1641 onoff("Not present table entries cached", reg, PCI_SECURE_CAP_NPCACHE); 1642 onoff("IOMMU Extended Feature Register support", reg, 1643 PCI_SECURE_CAP_EFRSUP); 1644 onoff("IOMMU Miscellaneous Information Register 1", reg, 1645 PCI_SECURE_CAP_EXT); 1646 havemisc1 = reg & PCI_SECURE_CAP_EXT; 1647 1648 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_BAL)]; 1649 printf(" Base Address Low Register: 0x%08x\n", reg); 1650 onoff("Enable", reg, PCI_SECURE_IOMMU_BAL_EN); 1651 reg2 = regs[o2i(capoff + PCI_SECURE_IOMMU_BAH)]; 1652 printf(" Base Address High Register: 0x%08x\n", reg2); 1653 printf(" Base Address: 0x%016" PRIx64 "\n", 1654 ((uint64_t)reg2 << 32) 1655 | (reg & (PCI_SECURE_IOMMU_BAL_H | PCI_SECURE_IOMMU_BAL_L))); 1656 1657 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_RANGE)]; 1658 printf(" IOMMU Range Register: 0x%08x\n", reg); 1659 printf(" HyperTransport UnitID: 0x%02x\n", 1660 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_UNITID)); 1661 onoff("Range valid", reg, PCI_SECURE_IOMMU_RANGE_RNGVALID); 1662 printf(" Device range bus number: 0x%02x\n", 1663 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_BUSNUM)); 1664 printf(" First device: 0x%04x\n", 1665 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_FIRSTDEV)); 1666 printf(" Last device: 0x%04x\n", 1667 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_LASTDEV)); 1668 1669 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC0)]; 1670 printf(" Miscellaneous Information Register 0: 0x%08x\n", reg); 1671 printf(" MSI Message number: 0x%02x\n", 1672 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MSINUM)); 1673 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_GVASIZE); 1674 printf(" Guest Virtual Address size: "); 1675 if (val == PCI_SECURE_IOMMU_MISC0_GVASIZE_48B) 1676 printf("48bits\n"); 1677 else 1678 printf("0x%x(unknown)\n", val); 1679 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_PASIZE); 1680 printf(" Physical Address size: %dbits\n", val); 1681 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_VASIZE); 1682 printf(" Virtual Address size: %dbits\n", val); 1683 onoff("ATS response address range reserved", reg, 1684 PCI_SECURE_IOMMU_MISC0_ATSRESV); 1685 printf(" Peripheral Page Request MSI Message number: 0x%02x\n", 1686 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MISNPPR)); 1687 1688 if (!havemisc1) 1689 return; 1690 1691 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC1)]; 1692 printf(" Miscellaneous Information Register 1: 0x%08x\n", reg); 1693 printf(" MSI Message number (GA): 0x%02x\n", 1694 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC1_MSINUM)); 1695 } 1696 1697 static void 1698 pci_print_pcie_L0s_latency(uint32_t val) 1699 { 1700 1701 switch (val) { 1702 case 0x0: 1703 printf("Less than 64ns\n"); 1704 break; 1705 case 0x1: 1706 case 0x2: 1707 case 0x3: 1708 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1709 break; 1710 case 0x4: 1711 printf("512ns to less than 1us\n"); 1712 break; 1713 case 0x5: 1714 printf("1us to less than 2us\n"); 1715 break; 1716 case 0x6: 1717 printf("2us - 4us\n"); 1718 break; 1719 case 0x7: 1720 printf("More than 4us\n"); 1721 break; 1722 } 1723 } 1724 1725 static void 1726 pci_print_pcie_L1_latency(uint32_t val) 1727 { 1728 1729 switch (val) { 1730 case 0x0: 1731 printf("Less than 1us\n"); 1732 break; 1733 case 0x6: 1734 printf("32us - 64us\n"); 1735 break; 1736 case 0x7: 1737 printf("More than 64us\n"); 1738 break; 1739 default: 1740 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1741 break; 1742 } 1743 } 1744 1745 static void 1746 pci_print_pcie_compl_timeout(uint32_t val) 1747 { 1748 1749 switch (val) { 1750 case 0x0: 1751 printf("50us to 50ms\n"); 1752 break; 1753 case 0x5: 1754 printf("16ms to 55ms\n"); 1755 break; 1756 case 0x6: 1757 printf("65ms to 210ms\n"); 1758 break; 1759 case 0x9: 1760 printf("260ms to 900ms\n"); 1761 break; 1762 case 0xa: 1763 printf("1s to 3.5s\n"); 1764 break; 1765 default: 1766 printf("unknown %u value\n", val); 1767 break; 1768 } 1769 } 1770 1771 static const char * const pcie_linkspeeds[] = { 1772 "2.5", "5.0", "8.0", "16.0", "32.0" 1773 }; 1774 1775 /* 1776 * Print link speed. This function is used for the following register bits: 1777 * Maximum Link Speed in LCAP 1778 * Current Link Speed in LCSR 1779 * Target Link Speed in LCSR2 1780 * All of above bitfield's values start from 1. 1781 * For LCSR2, 0 is allowed for a device which supports 2.5GT/s only (and 1782 * this check also works for devices which compliant to versions of the base 1783 * specification prior to 3.0. 1784 */ 1785 static void 1786 pci_print_pcie_linkspeed(int regnum, pcireg_t val) 1787 { 1788 1789 if ((regnum == PCIE_LCSR2) && (val == 0)) 1790 printf("2.5GT/s\n"); 1791 else if ((val < 1) || (val > __arraycount(pcie_linkspeeds))) 1792 printf("unknown value (%u)\n", val); 1793 else 1794 printf("%sGT/s\n", pcie_linkspeeds[val - 1]); 1795 } 1796 1797 /* 1798 * Print link speed "vector". 1799 * This function is used for the following register bits: 1800 * Supported Link Speeds Vector in LCAP2 1801 * Lower SKP OS Generation Supported Speed Vector in LCAP2 1802 * Lower SKP OS Reception Supported Speed Vector in LCAP2 1803 * Enable Lower SKP OS Generation Vector in LCTL3 1804 * All of above bitfield's values start from 0. 1805 */ 1806 static void 1807 pci_print_pcie_linkspeedvector(pcireg_t val) 1808 { 1809 unsigned int i; 1810 1811 /* Start from 0 */ 1812 for (i = 0; i < 16; i++) 1813 if (((val >> i) & 0x01) != 0) { 1814 if (i >= __arraycount(pcie_linkspeeds)) 1815 printf(" unknown vector (0x%x)", 1 << i); 1816 else 1817 printf(" %sGT/s", pcie_linkspeeds[i]); 1818 } 1819 } 1820 1821 static void 1822 pci_print_pcie_link_deemphasis(pcireg_t val) 1823 { 1824 switch (val) { 1825 case 0: 1826 printf("-6dB"); 1827 break; 1828 case 1: 1829 printf("-3.5dB"); 1830 break; 1831 default: 1832 printf("(reserved value)"); 1833 } 1834 } 1835 1836 static void 1837 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1838 { 1839 pcireg_t reg; /* for each register */ 1840 pcireg_t val; /* for each bitfield */ 1841 bool check_slot = false; 1842 unsigned int pcie_devtype; 1843 bool check_upstreamport = false; 1844 unsigned int pciever; 1845 unsigned int i; 1846 1847 printf("\n PCI Express Capabilities Register\n"); 1848 /* Capability Register */ 1849 reg = regs[o2i(capoff)]; 1850 printf(" Capability register: 0x%04x\n", reg >> 16); 1851 pciever = (unsigned int)(PCIE_XCAP_VER(reg)); 1852 printf(" Capability version: %u\n", pciever); 1853 printf(" Device type: "); 1854 pcie_devtype = PCIE_XCAP_TYPE(reg); 1855 switch (pcie_devtype) { 1856 case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */ 1857 printf("PCI Express Endpoint device\n"); 1858 check_upstreamport = true; 1859 break; 1860 case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */ 1861 printf("Legacy PCI Express Endpoint device\n"); 1862 check_upstreamport = true; 1863 break; 1864 case PCIE_XCAP_TYPE_RP: /* 0x4 */ 1865 printf("Root Port of PCI Express Root Complex\n"); 1866 check_slot = true; 1867 break; 1868 case PCIE_XCAP_TYPE_UP: /* 0x5 */ 1869 printf("Upstream Port of PCI Express Switch\n"); 1870 check_upstreamport = true; 1871 break; 1872 case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ 1873 printf("Downstream Port of PCI Express Switch\n"); 1874 check_slot = true; 1875 break; 1876 case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ 1877 printf("PCI Express to PCI/PCI-X Bridge\n"); 1878 check_upstreamport = true; 1879 break; 1880 case PCIE_XCAP_TYPE_PCI2PCIE: /* 0x8 */ 1881 printf("PCI/PCI-X to PCI Express Bridge\n"); 1882 /* Upstream port is not PCIe */ 1883 check_slot = true; 1884 break; 1885 case PCIE_XCAP_TYPE_RCIEP: /* 0x9 */ 1886 printf("Root Complex Integrated Endpoint\n"); 1887 break; 1888 case PCIE_XCAP_TYPE_RC_EVNTC: /* 0xa */ 1889 printf("Root Complex Event Collector\n"); 1890 break; 1891 default: 1892 printf("unknown\n"); 1893 break; 1894 } 1895 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1896 printf(" Interrupt Message Number: 0x%02x\n", 1897 PCIREG_SHIFTOUT(reg, PCIE_XCAP_IRQ)); 1898 1899 /* Device Capability Register */ 1900 reg = regs[o2i(capoff + PCIE_DCAP)]; 1901 printf(" Device Capabilities Register: 0x%08x\n", reg); 1902 printf(" Max Payload Size Supported: %u bytes max\n", 1903 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1904 printf(" Phantom Functions Supported: "); 1905 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) { 1906 case 0x0: 1907 printf("not available\n"); 1908 break; 1909 case 0x1: 1910 printf("MSB\n"); 1911 break; 1912 case 0x2: 1913 printf("two MSB\n"); 1914 break; 1915 case 0x3: 1916 printf("All three bits\n"); 1917 break; 1918 } 1919 printf(" Extended Tag Field Supported: %dbit\n", 1920 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1921 printf(" Endpoint L0 Acceptable Latency: "); 1922 pci_print_pcie_L0s_latency(PCIREG_SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY)); 1923 printf(" Endpoint L1 Acceptable Latency: "); 1924 pci_print_pcie_L1_latency(PCIREG_SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY)); 1925 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1926 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1927 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1928 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1929 if (check_upstreamport) { 1930 printf(" Captured Slot Power Limit: "); 1931 pci_conf_print_pcie_power( 1932 PCIREG_SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL), 1933 PCIREG_SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE)); 1934 } 1935 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1936 1937 /* Device Control Register */ 1938 reg = regs[o2i(capoff + PCIE_DCSR)]; 1939 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1940 onoff("Correctable Error Reporting Enable", reg, 1941 PCIE_DCSR_ENA_COR_ERR); 1942 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1943 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1944 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1945 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1946 printf(" Max Payload Size: %d byte\n", 1947 128 << PCIREG_SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD)); 1948 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1949 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1950 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1951 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1952 printf(" Max Read Request Size: %d byte\n", 1953 128 << PCIREG_SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ)); 1954 if (pcie_devtype == PCIE_XCAP_TYPE_PCIE2PCI) 1955 onoff("Bridge Config Retry Enable", reg, 1956 PCIE_DCSR_BRDG_CFG_RETRY); 1957 1958 /* Device Status Register */ 1959 reg = regs[o2i(capoff + PCIE_DCSR)]; 1960 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1961 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 1962 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 1963 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 1964 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 1965 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 1966 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 1967 onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD); 1968 1969 if (PCIE_HAS_LINKREGS(pcie_devtype)) { 1970 /* Link Capability Register */ 1971 reg = regs[o2i(capoff + PCIE_LCAP)]; 1972 printf(" Link Capabilities Register: 0x%08x\n", reg); 1973 printf(" Maximum Link Speed: "); 1974 pci_print_pcie_linkspeed(PCIE_LCAP, reg & PCIE_LCAP_MAX_SPEED); 1975 printf(" Maximum Link Width: x%u lanes\n", 1976 PCIREG_SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH)); 1977 printf(" Active State PM Support: "); 1978 switch (PCIREG_SHIFTOUT(reg, PCIE_LCAP_ASPM)) { 1979 case 0x0: 1980 printf("No ASPM support\n"); 1981 break; 1982 case 0x1: 1983 printf("L0s supported\n"); 1984 break; 1985 case 0x2: 1986 printf("L1 supported\n"); 1987 break; 1988 case 0x3: 1989 printf("L0s and L1 supported\n"); 1990 break; 1991 } 1992 printf(" L0 Exit Latency: "); 1993 pci_print_pcie_L0s_latency(PCIREG_SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT)); 1994 printf(" L1 Exit Latency: "); 1995 pci_print_pcie_L1_latency(PCIREG_SHIFTOUT(reg, PCIE_LCAP_L1_EXIT)); 1996 printf(" Port Number: %u\n", 1997 PCIREG_SHIFTOUT(reg, PCIE_LCAP_PORT)); 1998 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 1999 onoff("Surprise Down Error Report", reg, 2000 PCIE_LCAP_SURPRISE_DOWN); 2001 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 2002 onoff("Link BW Notification Capable", reg, 2003 PCIE_LCAP_LINK_BW_NOTIFY); 2004 onoff("ASPM Optionally Compliance", reg, 2005 PCIE_LCAP_ASPM_COMPLIANCE); 2006 2007 /* Link Control Register */ 2008 reg = regs[o2i(capoff + PCIE_LCSR)]; 2009 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 2010 printf(" Active State PM Control: "); 2011 switch (reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S)) { 2012 case 0: 2013 printf("disabled\n"); 2014 break; 2015 case 1: 2016 printf("L0s Entry Enabled\n"); 2017 break; 2018 case 2: 2019 printf("L1 Entry Enabled\n"); 2020 break; 2021 case 3: 2022 printf("L0s and L1 Entry Enabled\n"); 2023 break; 2024 } 2025 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 2026 "128bytes", "64bytes"); 2027 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 2028 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 2029 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 2030 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 2031 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 2032 onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD); 2033 onoff("Link Bandwidth Management Interrupt Enable", reg, 2034 PCIE_LCSR_LBMIE); 2035 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 2036 PCIE_LCSR_LABIE); 2037 printf(" DRS Signaling Control: "); 2038 switch (PCIREG_SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) { 2039 case 0: 2040 printf("not reported\n"); 2041 break; 2042 case 1: 2043 printf("Interrupt Enabled\n"); 2044 break; 2045 case 2: 2046 printf("DRS to FRS Signaling Enabled\n"); 2047 break; 2048 default: 2049 printf("reserved\n"); 2050 break; 2051 } 2052 2053 /* Link Status Register */ 2054 reg = regs[o2i(capoff + PCIE_LCSR)]; 2055 printf(" Link Status Register: 0x%04x\n", reg >> 16); 2056 printf(" Negotiated Link Speed: "); 2057 pci_print_pcie_linkspeed(PCIE_LCSR, 2058 PCIREG_SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 2059 printf(" Negotiated Link Width: x%u lanes\n", 2060 PCIREG_SHIFTOUT(reg, PCIE_LCSR_NLW)); 2061 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 2062 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 2063 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 2064 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 2065 onoff("Link Bandwidth Management Status", reg, 2066 PCIE_LCSR_LINK_BW_MGMT); 2067 onoff("Link Autonomous Bandwidth Status", reg, 2068 PCIE_LCSR_LINK_AUTO_BW); 2069 } 2070 2071 if (check_slot == true) { 2072 pcireg_t slcap; 2073 2074 /* Slot Capability Register */ 2075 slcap = reg = regs[o2i(capoff + PCIE_SLCAP)]; 2076 printf(" Slot Capability Register: 0x%08x\n", reg); 2077 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 2078 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 2079 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 2080 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 2081 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 2082 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 2083 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 2084 printf(" Slot Power Limit Value: "); 2085 pci_conf_print_pcie_power(PCIREG_SHIFTOUT(reg, PCIE_SLCAP_SPLV), 2086 PCIREG_SHIFTOUT(reg, PCIE_SLCAP_SPLS)); 2087 onoff("Electromechanical Interlock Present", reg, 2088 PCIE_SLCAP_EIP); 2089 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 2090 printf(" Physical Slot Number: %d\n", 2091 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 2092 2093 /* Slot Control Register */ 2094 reg = regs[o2i(capoff + PCIE_SLCSR)]; 2095 printf(" Slot Control Register: 0x%04x\n", reg & 0xffff); 2096 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 2097 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 2098 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 2099 onoff("Presence Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 2100 onoff("Command Completed Interrupt Enabled", reg, 2101 PCIE_SLCSR_CCE); 2102 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 2103 /* 2104 * For Attention Indicator Control and Power Indicator Control, 2105 * it's allowed to be a read only value 0 if corresponding 2106 * capability register bit is 0. 2107 */ 2108 if (slcap & PCIE_SLCAP_AIP) { 2109 printf(" Attention Indicator Control: "); 2110 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 2111 case 0x0: 2112 printf("reserved\n"); 2113 break; 2114 case PCIE_SLCSR_IND_ON: 2115 printf("on\n"); 2116 break; 2117 case PCIE_SLCSR_IND_BLINK: 2118 printf("blink\n"); 2119 break; 2120 case PCIE_SLCSR_IND_OFF: 2121 printf("off\n"); 2122 break; 2123 } 2124 } 2125 if (slcap & PCIE_SLCAP_PIP) { 2126 printf(" Power Indicator Control: "); 2127 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 2128 case 0x0: 2129 printf("reserved\n"); 2130 break; 2131 case PCIE_SLCSR_IND_ON: 2132 printf("on\n"); 2133 break; 2134 case PCIE_SLCSR_IND_BLINK: 2135 printf("blink\n"); 2136 break; 2137 case PCIE_SLCSR_IND_OFF: 2138 printf("off\n"); 2139 break; 2140 } 2141 } 2142 printf(" Power Controller Control: Power %s\n", 2143 reg & PCIE_SLCSR_PCC ? "off" : "on"); 2144 onoff("Electromechanical Interlock Control", 2145 reg, PCIE_SLCSR_EIC); 2146 onoff("Data Link Layer State Changed Enable", reg, 2147 PCIE_SLCSR_DLLSCE); 2148 onoff("Auto Slot Power Limit Disable", reg, 2149 PCIE_SLCSR_AUTOSPLDIS); 2150 2151 /* Slot Status Register */ 2152 printf(" Slot Status Register: 0x%04x\n", reg >> 16); 2153 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 2154 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 2155 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 2156 onoff("Presence Detect Changed", reg, PCIE_SLCSR_PDC); 2157 onoff("Command Completed", reg, PCIE_SLCSR_CC); 2158 onoff("MRL Open", reg, PCIE_SLCSR_MS); 2159 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 2160 onoff("Electromechanical Interlock engaged", reg, 2161 PCIE_SLCSR_EIS); 2162 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 2163 } 2164 2165 if (PCIE_HAS_ROOTREGS(pcie_devtype)) { 2166 /* Root Control Register */ 2167 reg = regs[o2i(capoff + PCIE_RCR)]; 2168 printf(" Root Control Register: 0x%04x\n", reg & 0xffff); 2169 onoff("SERR on Correctable Error Enable", reg, 2170 PCIE_RCR_SERR_CER); 2171 onoff("SERR on Non-Fatal Error Enable", reg, 2172 PCIE_RCR_SERR_NFER); 2173 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 2174 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 2175 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 2176 2177 /* Root Capability Register */ 2178 printf(" Root Capability Register: 0x%04x\n", 2179 reg >> 16); 2180 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 2181 2182 /* Root Status Register */ 2183 reg = regs[o2i(capoff + PCIE_RSR)]; 2184 printf(" Root Status Register: 0x%08x\n", reg); 2185 printf(" PME Requester ID: 0x%04x\n", 2186 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 2187 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 2188 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 2189 } 2190 2191 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2192 if (pciever < 2) 2193 return; 2194 2195 /* Device Capabilities 2 */ 2196 reg = regs[o2i(capoff + PCIE_DCAP2)]; 2197 printf(" Device Capabilities 2: 0x%08x\n", reg); 2198 printf(" Completion Timeout Ranges Supported: "); 2199 val = reg & PCIE_DCAP2_COMPT_RANGE; 2200 switch (val) { 2201 case 0: 2202 printf("not supported\n"); 2203 break; 2204 default: 2205 for (i = 0; i <= 3; i++) { 2206 if (((val >> i) & 0x01) != 0) 2207 printf("%c", 'A' + i); 2208 } 2209 printf("\n"); 2210 } 2211 onoff("Completion Timeout Disable Supported", reg, 2212 PCIE_DCAP2_COMPT_DIS); 2213 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 2214 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 2215 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 2216 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 2217 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 2218 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 2219 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 2220 printf(" TPH Completer Supported: "); 2221 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) { 2222 case 0: 2223 printf("Not supported\n"); 2224 break; 2225 case 1: 2226 printf("TPH\n"); 2227 break; 2228 case 3: 2229 printf("TPH and Extended TPH\n"); 2230 break; 2231 default: 2232 printf("(reserved value)\n"); 2233 break; 2234 } 2235 printf(" LN System CLS: "); 2236 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 2237 case 0x0: 2238 printf("Not supported or not in effect\n"); 2239 break; 2240 case 0x1: 2241 printf("64byte cachelines in effect\n"); 2242 break; 2243 case 0x2: 2244 printf("128byte cachelines in effect\n"); 2245 break; 2246 case 0x3: 2247 printf("Reserved\n"); 2248 break; 2249 } 2250 onoff("10-bit Tag Completer Supported", reg, PCIE_DCAP2_TBT_COMP); 2251 onoff("10-bit Tag Requester Supported", reg, PCIE_DCAP2_TBT_REQ); 2252 printf(" OBFF Supported: "); 2253 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_OBFF)) { 2254 case 0x0: 2255 printf("Not supported\n"); 2256 break; 2257 case 0x1: 2258 printf("Message only\n"); 2259 break; 2260 case 0x2: 2261 printf("WAKE# only\n"); 2262 break; 2263 case 0x3: 2264 printf("Both\n"); 2265 break; 2266 } 2267 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 2268 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 2269 val = PCIREG_SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP); 2270 printf(" Max End-End TLP Prefixes: %u\n", (val == 0) ? 4 : val); 2271 printf(" Emergency Power Reduction Supported: "); 2272 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) { 2273 case 0x0: 2274 printf("Not supported\n"); 2275 break; 2276 case 0x1: 2277 printf("Device Specific mechanism\n"); 2278 break; 2279 case 0x2: 2280 printf("Form Factor spec or Device Specific mechanism\n"); 2281 break; 2282 case 0x3: 2283 printf("Reserved\n"); 2284 break; 2285 } 2286 onoff("Emergency Power Reduction Initialization Required", reg, 2287 PCIE_DCAP2_EMGPWRRED_INI); 2288 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 2289 2290 /* Device Control 2 */ 2291 reg = regs[o2i(capoff + PCIE_DCSR2)]; 2292 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 2293 printf(" Completion Timeout Value: "); 2294 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 2295 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 2296 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 2297 onoff("AtomicOp Requester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 2298 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 2299 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 2300 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 2301 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 2302 onoff("Emergency Power Reduction Request", reg, 2303 PCIE_DCSR2_EMGPWRRED_REQ); 2304 onoff("10-bit Tag Requester Enabled", reg, PCIE_DCSR2_TBT_REQ); 2305 printf(" OBFF: "); 2306 switch (PCIREG_SHIFTOUT(reg, PCIE_DCSR2_OBFF_EN)) { 2307 case 0x0: 2308 printf("Disabled\n"); 2309 break; 2310 case 0x1: 2311 printf("Enabled with Message Signaling Variation A\n"); 2312 break; 2313 case 0x2: 2314 printf("Enabled with Message Signaling Variation B\n"); 2315 break; 2316 case 0x3: 2317 printf("Enabled using WAKE# signaling\n"); 2318 break; 2319 } 2320 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 2321 2322 if (PCIE_HAS_LINKREGS(pcie_devtype)) { 2323 bool drs_supported = false; 2324 2325 /* Link Capability 2 */ 2326 reg = regs[o2i(capoff + PCIE_LCAP2)]; 2327 /* If the vector is 0, LCAP2 is not implemented */ 2328 if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) { 2329 printf(" Link Capabilities 2: 0x%08x\n", reg); 2330 printf(" Supported Link Speeds Vector:"); 2331 pci_print_pcie_linkspeedvector( 2332 PCIREG_SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 2333 printf("\n"); 2334 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 2335 printf(" " 2336 "Lower SKP OS Generation Supported Speed Vector:"); 2337 pci_print_pcie_linkspeedvector( 2338 PCIREG_SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 2339 printf("\n"); 2340 printf(" " 2341 "Lower SKP OS Reception Supported Speed Vector:"); 2342 pci_print_pcie_linkspeedvector( 2343 PCIREG_SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 2344 printf("\n"); 2345 onoff("Retimer Presence Detect Supported", reg, 2346 PCIE_LCAP2_RETIMERPD); 2347 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 2348 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 2349 } 2350 2351 /* Link Control 2 */ 2352 reg = regs[o2i(capoff + PCIE_LCSR2)]; 2353 /* If the vector is 0, LCAP2 is not implemented */ 2354 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 2355 printf(" Target Link Speed: "); 2356 pci_print_pcie_linkspeed(PCIE_LCSR2, 2357 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_TGT_LSPEED)); 2358 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 2359 onoff("HW Autonomous Speed Disabled", reg, 2360 PCIE_LCSR2_HW_AS_DIS); 2361 printf(" Selectable De-emphasis: "); 2362 pci_print_pcie_link_deemphasis( 2363 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP)); 2364 printf("\n"); 2365 printf(" Transmit Margin: %u\n", 2366 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_TX_MARGIN)); 2367 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 2368 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 2369 printf(" Compliance Present/De-emphasis: "); 2370 pci_print_pcie_link_deemphasis( 2371 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP)); 2372 printf("\n"); 2373 2374 /* Link Status 2 */ 2375 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 2376 printf(" Current De-emphasis Level: "); 2377 pci_print_pcie_link_deemphasis( 2378 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL)); 2379 printf("\n"); 2380 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 2381 onoff("Equalization Phase 1 Successful", reg, 2382 PCIE_LCSR2_EQP1_SUC); 2383 onoff("Equalization Phase 2 Successful", reg, 2384 PCIE_LCSR2_EQP2_SUC); 2385 onoff("Equalization Phase 3 Successful", reg, 2386 PCIE_LCSR2_EQP3_SUC); 2387 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 2388 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 2389 if (drs_supported) { 2390 printf(" Downstream Component Presence: "); 2391 switch (PCIREG_SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 2392 case PCIE_DSCOMPN_DOWN_NOTDETERM: 2393 printf("Link Down - Presence Not" 2394 " Determined\n"); 2395 break; 2396 case PCIE_DSCOMPN_DOWN_NOTPRES: 2397 printf("Link Down - Component Not Present\n"); 2398 break; 2399 case PCIE_DSCOMPN_DOWN_PRES: 2400 printf("Link Down - Component Present\n"); 2401 break; 2402 case PCIE_DSCOMPN_UP_PRES: 2403 printf("Link Up - Component Present\n"); 2404 break; 2405 case PCIE_DSCOMPN_UP_PRES_DRS: 2406 printf("Link Up - Component Present and DRS" 2407 " received\n"); 2408 break; 2409 default: 2410 printf("reserved\n"); 2411 break; 2412 } 2413 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 2414 } 2415 } 2416 2417 /* Slot Capability 2 */ 2418 /* Slot Control 2 */ 2419 /* Slot Status 2 */ 2420 } 2421 2422 static void 2423 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 2424 { 2425 pcireg_t reg; 2426 2427 printf("\n MSI-X Capability Register\n"); 2428 2429 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2430 printf(" Message Control register: 0x%04x\n", 2431 (reg >> 16) & 0xff); 2432 printf(" Table Size: %d\n", PCI_MSIX_CTL_TBLSIZE(reg)); 2433 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 2434 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 2435 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 2436 printf(" Table offset register: 0x%08x\n", reg); 2437 printf(" Table offset: 0x%08x\n", 2438 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 2439 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 2440 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 2441 printf(" Pending bit array register: 0x%08x\n", reg); 2442 printf(" Pending bit array offset: 0x%08x\n", 2443 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2444 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2445 } 2446 2447 static void 2448 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2449 { 2450 pcireg_t reg; 2451 2452 printf("\n Serial ATA Capability Register\n"); 2453 2454 reg = regs[o2i(capoff + PCI_SATA_REV)]; 2455 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2456 printf(" Revision: %u.%u\n", 2457 PCIREG_SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2458 PCIREG_SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2459 2460 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2461 2462 printf(" BAR Register: 0x%08x\n", reg); 2463 printf(" Register location: "); 2464 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2465 printf("in config space\n"); 2466 else { 2467 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2468 printf(" BAR offset: 0x%08x\n", 2469 PCIREG_SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2470 } 2471 } 2472 2473 static void 2474 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2475 { 2476 pcireg_t reg; 2477 2478 printf("\n Advanced Features Capability Register\n"); 2479 2480 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2481 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2482 printf(" AF Structure Length: 0x%02x\n", 2483 PCIREG_SHIFTOUT(reg, PCI_AF_LENGTH)); 2484 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2485 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2486 reg = regs[o2i(capoff + PCI_AFCSR)]; 2487 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2488 /* 2489 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2490 * and it's always 0 on read 2491 */ 2492 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2493 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2494 } 2495 2496 static void 2497 pci_conf_print_ea_cap_prop(unsigned int prop) 2498 { 2499 2500 switch (prop) { 2501 case PCI_EA_PROP_MEM_NONPREF: 2502 printf("Memory Space, Non-Prefetchable\n"); 2503 break; 2504 case PCI_EA_PROP_MEM_PREF: 2505 printf("Memory Space, Prefetchable\n"); 2506 break; 2507 case PCI_EA_PROP_IO: 2508 printf("I/O Space\n"); 2509 break; 2510 case PCI_EA_PROP_VF_MEM_NONPREF: 2511 printf("Resorce for VF use, Memory Space, Non-Prefetchable\n"); 2512 break; 2513 case PCI_EA_PROP_VF_MEM_PREF: 2514 printf("Resorce for VF use, Memory Space, Prefetch\n"); 2515 break; 2516 case PCI_EA_PROP_BB_MEM_NONPREF: 2517 printf("Behind the Bridge, Memory Space, Non-Pref\n"); 2518 break; 2519 case PCI_EA_PROP_BB_MEM_PREF: 2520 printf("Behind the Bridge, Memory Space. Prefetchable\n"); 2521 break; 2522 case PCI_EA_PROP_BB_IO: 2523 printf("Behind Bridge, I/O Space\n"); 2524 break; 2525 case PCI_EA_PROP_MEM_UNAVAIL: 2526 printf("Memory Space Unavailable\n"); 2527 break; 2528 case PCI_EA_PROP_IO_UNAVAIL: 2529 printf("IO Space Unavailable\n"); 2530 break; 2531 case PCI_EA_PROP_UNAVAIL: 2532 printf("Entry Unavailable for use\n"); 2533 break; 2534 default: 2535 printf("Reserved\n"); 2536 break; 2537 } 2538 } 2539 2540 static void 2541 pci_conf_print_ea_cap(const pcireg_t *regs, int capoff) 2542 { 2543 pcireg_t reg, reg2; 2544 unsigned int entries, entoff, i; 2545 2546 printf("\n Enhanced Allocation Capability Register\n"); 2547 2548 reg = regs[o2i(capoff + PCI_EA_CAP1)]; 2549 printf(" EA Num Entries register: 0x%04x\n", reg >> 16); 2550 entries = PCIREG_SHIFTOUT(reg, PCI_EA_CAP1_NUMENTRIES); 2551 printf(" EA Num Entries: %u\n", entries); 2552 2553 /* Type 1 only */ 2554 if (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) == PCI_HDRTYPE_PPB) { 2555 reg = regs[o2i(capoff + PCI_EA_CAP2)]; 2556 printf(" EA Capability Second register: 0x%08x\n", reg); 2557 printf(" Fixed Secondary Bus Number: %hhu\n", 2558 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_EA_CAP2_SECONDARY)); 2559 printf(" Fixed Subordinate Bus Number: %hhu\n", 2560 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_EA_CAP2_SUBORDINATE)); 2561 entoff = capoff + 8; 2562 } else 2563 entoff = capoff + 4; 2564 2565 for (i = 0; i < entries; i++) { 2566 uint64_t base, offset; 2567 bool baseis64, offsetis64; 2568 unsigned int bei, entry_size; 2569 2570 printf(" Entry %u:\n", i); 2571 /* The first DW */ 2572 reg = regs[o2i(entoff)]; 2573 printf(" The first register: 0x%08x\n", reg); 2574 entry_size = PCIREG_SHIFTOUT(reg, PCI_EA_ES); 2575 printf(" Entry size: %u\n", entry_size); 2576 printf(" BAR Equivalent Indicator: "); 2577 bei = PCIREG_SHIFTOUT(reg, PCI_EA_BEI); 2578 switch (bei) { 2579 case PCI_EA_BEI_BAR0: 2580 case PCI_EA_BEI_BAR1: 2581 case PCI_EA_BEI_BAR2: 2582 case PCI_EA_BEI_BAR3: 2583 case PCI_EA_BEI_BAR4: 2584 case PCI_EA_BEI_BAR5: 2585 printf("BAR %u\n", bei - PCI_EA_BEI_BAR0); 2586 break; 2587 case PCI_EA_BEI_BEHIND: 2588 printf("Behind the function\n"); 2589 break; 2590 case PCI_EA_BEI_NOTIND: 2591 printf("Not Indicated\n"); 2592 break; 2593 case PCI_EA_BEI_EXPROM: 2594 printf("Expansion ROM\n"); 2595 break; 2596 case PCI_EA_BEI_VFBAR0: 2597 case PCI_EA_BEI_VFBAR1: 2598 case PCI_EA_BEI_VFBAR2: 2599 case PCI_EA_BEI_VFBAR3: 2600 case PCI_EA_BEI_VFBAR4: 2601 case PCI_EA_BEI_VFBAR5: 2602 printf("VF BAR %u\n", bei - PCI_EA_BEI_VFBAR0); 2603 break; 2604 case PCI_EA_BEI_RESERVED: 2605 default: 2606 printf("Reserved\n"); 2607 break; 2608 } 2609 2610 printf(" Primary Properties: "); 2611 pci_conf_print_ea_cap_prop(PCIREG_SHIFTOUT(reg, PCI_EA_PP)); 2612 printf(" Secondary Properties: "); 2613 pci_conf_print_ea_cap_prop(PCIREG_SHIFTOUT(reg, PCI_EA_SP)); 2614 onoff("Writable", reg, PCI_EA_W); 2615 onoff("Enable for this entry", reg, PCI_EA_E); 2616 2617 if (entry_size == 0) { 2618 entoff += 4; 2619 continue; 2620 } 2621 2622 /* Base addr */ 2623 reg = regs[o2i(entoff + 4)]; 2624 base = reg & PCI_EA_LOWMASK; 2625 baseis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT; 2626 printf(" Base Address Register Low: 0x%08x\n", reg); 2627 if (baseis64) { 2628 /* 64bit */ 2629 reg2 = regs[o2i(entoff + 12)]; 2630 printf(" Base Address Register high: 0x%08x\n", 2631 reg2); 2632 base |= (uint64_t)reg2 << 32; 2633 } 2634 2635 /* Offset addr */ 2636 reg = regs[o2i(entoff + 8)]; 2637 offset = reg & PCI_EA_LOWMASK; 2638 offsetis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT; 2639 printf(" Max Offset Register Low: 0x%08x\n", reg); 2640 if (offsetis64) { 2641 /* 64bit */ 2642 reg2 = regs[o2i(entoff + (baseis64 ? 16 : 12))]; 2643 printf(" Max Offset Register high: 0x%08x\n", 2644 reg2); 2645 offset |= (uint64_t)reg2 << 32; 2646 } 2647 2648 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 2649 "\n", base, base + offset); 2650 2651 entoff += 4 + (4 * entry_size); 2652 } 2653 } 2654 2655 /* XXX pci_conf_print_fpb_cap */ 2656 2657 static struct { 2658 pcireg_t cap; 2659 const char *name; 2660 void (*printfunc)(const pcireg_t *, int); 2661 } pci_captab[] = { 2662 { PCI_CAP_RESERVED0, "reserved", NULL }, 2663 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2664 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2665 { PCI_CAP_VPD, "VPD", NULL }, 2666 { PCI_CAP_SLOTID, "SlotID", NULL }, 2667 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2668 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2669 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2670 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2671 { PCI_CAP_VENDSPEC, "Vendor-specific", 2672 pci_conf_print_vendspec_cap }, 2673 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2674 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2675 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2676 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2677 pci_conf_print_subsystem_cap }, 2678 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2679 { PCI_CAP_SECURE, "Secure Device", pci_conf_print_secure_cap }, 2680 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2681 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2682 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2683 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2684 { PCI_CAP_EA, "Enhanced Allocation", pci_conf_print_ea_cap }, 2685 { PCI_CAP_FPB, "Flattening Portal Bridge", NULL } 2686 }; 2687 2688 static int 2689 pci_conf_find_cap(const pcireg_t *regs, unsigned int capid, int *offsetp) 2690 { 2691 pcireg_t rval; 2692 unsigned int capptr; 2693 int off; 2694 2695 if (!(regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)) 2696 return 0; 2697 2698 /* Determine the Capability List Pointer register to start with. */ 2699 switch (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)])) { 2700 case 0: /* standard device header */ 2701 case 1: /* PCI-PCI bridge header */ 2702 capptr = PCI_CAPLISTPTR_REG; 2703 break; 2704 case 2: /* PCI-CardBus Bridge header */ 2705 capptr = PCI_CARDBUS_CAPLISTPTR_REG; 2706 break; 2707 default: 2708 return 0; 2709 } 2710 2711 for (off = PCI_CAPLIST_PTR(regs[o2i(capptr)]); 2712 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2713 rval = regs[o2i(off)]; 2714 if (capid == PCI_CAPLIST_CAP(rval)) { 2715 if (offsetp != NULL) 2716 *offsetp = off; 2717 return 1; 2718 } 2719 } 2720 return 0; 2721 } 2722 2723 static void 2724 pci_conf_print_caplist( 2725 #ifdef _KERNEL 2726 pci_chipset_tag_t pc, pcitag_t tag, 2727 #endif 2728 const pcireg_t *regs, int capoff) 2729 { 2730 int off; 2731 pcireg_t foundcap; 2732 pcireg_t rval; 2733 bool foundtable[__arraycount(pci_captab)]; 2734 unsigned int i; 2735 2736 /* Clear table */ 2737 for (i = 0; i < __arraycount(pci_captab); i++) 2738 foundtable[i] = false; 2739 2740 /* Print capability register's offset and the type first */ 2741 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2742 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2743 rval = regs[o2i(off)]; 2744 printf(" Capability register at 0x%02x\n", off); 2745 2746 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2747 foundcap = PCI_CAPLIST_CAP(rval); 2748 if (foundcap < __arraycount(pci_captab)) { 2749 printf("%s)\n", pci_captab[foundcap].name); 2750 /* Mark as found */ 2751 foundtable[foundcap] = true; 2752 } else 2753 printf("unknown)\n"); 2754 } 2755 2756 /* 2757 * And then, print the detail of each capability registers 2758 * in capability value's order. 2759 */ 2760 for (i = 0; i < __arraycount(pci_captab); i++) { 2761 if (foundtable[i] == false) 2762 continue; 2763 2764 /* 2765 * The type was found. Search capability list again and 2766 * print all capabilities that the capability type is 2767 * the same. This is required because some capabilities 2768 * appear multiple times (e.g. HyperTransport capability). 2769 */ 2770 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2771 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2772 rval = regs[o2i(off)]; 2773 if ((PCI_CAPLIST_CAP(rval) == i) 2774 && (pci_captab[i].printfunc != NULL)) 2775 pci_captab[i].printfunc(regs, off); 2776 } 2777 } 2778 } 2779 2780 /* Extended Capability */ 2781 2782 static void 2783 pci_conf_print_aer_cap_uc(pcireg_t reg) 2784 { 2785 2786 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2787 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2788 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2789 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2790 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2791 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2792 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2793 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2794 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2795 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2796 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2797 onoff("Unsupported Request Error", reg, 2798 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2799 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2800 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2801 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2802 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2803 onoff("TLP Prefix Blocked Error", reg, 2804 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2805 onoff("Poisoned TLP Egress Blocked", reg, 2806 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2807 } 2808 2809 static void 2810 pci_conf_print_aer_cap_cor(pcireg_t reg) 2811 { 2812 2813 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2814 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2815 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2816 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2817 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2818 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2819 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2820 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2821 } 2822 2823 static void 2824 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2825 { 2826 2827 printf(" First Error Pointer: 0x%04x\n", 2828 PCIREG_SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2829 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2830 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2831 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2832 onoff("ECRC Check Enable", reg, PCI_AER_ECRC_CHECK_ENABLE); 2833 onoff("Multiple Header Recording Capable", reg, 2834 PCI_AER_MULT_HDR_CAPABLE); 2835 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2836 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2837 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2838 2839 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2840 if (!tlp_prefix_log) 2841 return; 2842 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2843 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2844 } 2845 2846 static void 2847 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2848 { 2849 2850 onoff("Correctable Error Reporting Enable", reg, 2851 PCI_AER_ROOTERR_COR_ENABLE); 2852 onoff("Non-Fatal Error Reporting Enable", reg, 2853 PCI_AER_ROOTERR_NF_ENABLE); 2854 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2855 } 2856 2857 static void 2858 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2859 { 2860 2861 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2862 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2863 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2864 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2865 PCI_AER_ROOTERR_MULTI_UC_ERR); 2866 onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL); 2867 onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR); 2868 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2869 printf(" Advanced Error Interrupt Message Number: 0x%02x\n", 2870 PCIREG_SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2871 } 2872 2873 static void 2874 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2875 { 2876 2877 printf(" Correctable Source ID: 0x%04x\n", 2878 PCIREG_SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2879 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2880 PCIREG_SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2881 } 2882 2883 static void 2884 pci_conf_print_aer_cap(const pcireg_t *regs, int extcapoff) 2885 { 2886 pcireg_t reg; 2887 int pcie_capoff; 2888 int pcie_devtype = -1; 2889 bool tlp_prefix_log = false; 2890 2891 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2892 reg = regs[o2i(pcie_capoff)]; 2893 pcie_devtype = PCIE_XCAP_TYPE(reg); 2894 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2895 if (PCIREG_SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2896 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2897 /* End-End TLP Prefix Supported */ 2898 if (reg & PCIE_DCAP2_EETLP_PREF) { 2899 tlp_prefix_log = true; 2900 } 2901 } 2902 } 2903 2904 printf("\n Advanced Error Reporting Register\n"); 2905 2906 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2907 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2908 pci_conf_print_aer_cap_uc(reg); 2909 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2910 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2911 pci_conf_print_aer_cap_uc(reg); 2912 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2913 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2914 pci_conf_print_aer_cap_uc(reg); 2915 2916 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2917 printf(" Correctable Error Status register: 0x%08x\n", reg); 2918 pci_conf_print_aer_cap_cor(reg); 2919 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2920 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2921 pci_conf_print_aer_cap_cor(reg); 2922 2923 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2924 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2925 reg); 2926 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2927 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2928 printf(" Header Log register:\n"); 2929 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2930 extcapoff + PCI_AER_ROOTERR_CMD); 2931 2932 switch (pcie_devtype) { 2933 case PCIE_XCAP_TYPE_RP: /* Root Port of PCI Express Root Complex */ 2934 case PCIE_XCAP_TYPE_RC_EVNTC: /* Root Complex Event Collector */ 2935 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2936 printf(" Root Error Command register: 0x%08x\n", reg); 2937 pci_conf_print_aer_cap_rooterr_cmd(reg); 2938 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2939 printf(" Root Error Status register: 0x%08x\n", reg); 2940 pci_conf_print_aer_cap_rooterr_status(reg); 2941 2942 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2943 printf(" Error Source Identification register: 0x%08x\n", 2944 reg); 2945 pci_conf_print_aer_cap_errsrc_id(reg); 2946 break; 2947 } 2948 2949 if (tlp_prefix_log) { 2950 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2951 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2952 } 2953 } 2954 2955 /* 2956 * Helper function to print the arbitration phase register. 2957 * 2958 * phases: Number of phases in the arbitration tables. 2959 * arbsize: Number of bits in each phase. 2960 * indent: Add more two spaces if it's true. 2961 */ 2962 static void 2963 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 2964 const int phases, int arbsize, bool indent) 2965 { 2966 pcireg_t reg; 2967 int num_per_reg = 32 / arbsize; 2968 int i, j; 2969 2970 printf("%s %s Arbitration Table:\n", indent ? " " : "", name); 2971 for (i = 0; i < phases; i += num_per_reg) { 2972 reg = regs[o2i(off + (sizeof(uint32_t) * (i / num_per_reg)))]; 2973 for (j = 0; j < num_per_reg; j++) { 2974 printf("%s Phase[%d]: 0x%x\n", indent ? " " : "", 2975 i + j, 2976 (uint32_t)(reg & __BITS(arbsize - 1, 0))); 2977 reg >>= arbsize; 2978 } 2979 } 2980 } 2981 2982 /* For VC, bit 4-7 are reserved. For Port, bit 6-7 are reserved */ 2983 static const int arb_phases[8] = {0, 32, 64, 128, 128, 256, 0, 0 }; 2984 2985 static void 2986 pci_conf_print_vc_cap(const pcireg_t *regs, int extcapoff) 2987 { 2988 pcireg_t reg, n; 2989 int arbtab, parbsize; 2990 pcireg_t arbsel; 2991 int i, count; 2992 2993 printf("\n Virtual Channel Register\n"); 2994 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 2995 printf(" Port VC Capability register 1: 0x%08x\n", reg); 2996 count = PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 2997 printf(" Extended VC Count: %d\n", count); 2998 n = PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 2999 printf(" Low Priority Extended VC Count: %u\n", n); 3000 n = PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 3001 printf(" Reference Clock: %s\n", 3002 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 3003 parbsize = 1 << PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 3004 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 3005 3006 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 3007 printf(" Port VC Capability register 2: 0x%08x\n", reg); 3008 onoff("Hardware fixed arbitration scheme", 3009 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 3010 onoff("WRR arbitration with 32 phases", 3011 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 3012 onoff("WRR arbitration with 64 phases", 3013 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 3014 onoff("WRR arbitration with 128 phases", 3015 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 3016 arbtab = PCIREG_SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 3017 printf(" VC Arbitration Table Offset: 0x%x\n", arbtab); 3018 3019 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 3020 printf(" Port VC Control register: 0x%04x\n", reg); 3021 arbsel = PCIREG_SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 3022 printf(" VC Arbitration Select: 0x%x\n", arbsel); 3023 3024 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 3025 printf(" Port VC Status register: 0x%04x\n", reg); 3026 onoff("VC Arbitration Table Status", 3027 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 3028 3029 if ((arbtab != 0) && (arbsel != 0)) 3030 pci_conf_print_vc_cap_arbtab(regs, extcapoff + (arbtab * 16), 3031 "VC", arb_phases[arbsel], 4, false); 3032 3033 for (i = 0; i < count + 1; i++) { 3034 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 3035 printf(" VC number %d\n", i); 3036 printf(" VC Resource Capability Register: 0x%08x\n", reg); 3037 onoff(" Non-configurable Hardware fixed arbitration scheme", 3038 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 3039 onoff(" WRR arbitration with 32 phases", 3040 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 3041 onoff(" WRR arbitration with 64 phases", 3042 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 3043 onoff(" WRR arbitration with 128 phases", 3044 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 3045 onoff(" Time-based WRR arbitration with 128 phases", 3046 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 3047 onoff(" WRR arbitration with 256 phases", 3048 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 3049 onoff(" Advanced Packet Switching", 3050 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 3051 onoff(" Reject Snoop Transaction", 3052 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 3053 n = PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 3054 printf(" Maximum Time Slots: %d\n", n); 3055 arbtab = PCIREG_SHIFTOUT(reg, 3056 PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET); 3057 printf(" Port Arbitration Table offset: 0x%02x\n", 3058 arbtab); 3059 3060 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 3061 printf(" VC Resource Control Register: 0x%08x\n", reg); 3062 printf(" TC/VC Map: 0x%02x\n", 3063 PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 3064 /* 3065 * The load Port Arbitration Table bit is used to update 3066 * the Port Arbitration logic and it's always 0 on read, so 3067 * we don't print it. 3068 */ 3069 arbsel = PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 3070 printf(" Port Arbitration Select: 0x%x\n", arbsel); 3071 n = PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 3072 printf(" VC ID: %d\n", n); 3073 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 3074 3075 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 3076 printf(" VC Resource Status Register: 0x%08x\n", reg); 3077 onoff(" Port Arbitration Table Status", 3078 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 3079 onoff(" VC Negotiation Pending", 3080 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 3081 3082 if ((arbtab != 0) && (arbsel != 0)) 3083 pci_conf_print_vc_cap_arbtab(regs, 3084 extcapoff + (arbtab * 16), 3085 "Port", arb_phases[arbsel], parbsize, true); 3086 } 3087 } 3088 3089 /* 3090 * Print Power limit. This encoding is the same among the following registers: 3091 * - The Captured Slot Power Limit in the PCIe Device Capability Register. 3092 * - The Slot Power Limit in the PCIe Slot Capability Register. 3093 * - The Base Power in the Data register of Power Budgeting capability. 3094 */ 3095 static void 3096 pci_conf_print_pcie_power(uint8_t base, unsigned int scale) 3097 { 3098 unsigned int sdiv = 1; 3099 3100 if ((scale == 0) && (base > 0xef)) { 3101 const char *s; 3102 3103 switch (base) { 3104 case 0xf0: 3105 s = "239W < x <= 250W"; 3106 break; 3107 case 0xf1: 3108 s = "250W < x <= 275W"; 3109 break; 3110 case 0xf2: 3111 s = "275W < x <= 300W"; 3112 break; 3113 default: 3114 s = "reserved for greater than 300W"; 3115 break; 3116 } 3117 printf("%s\n", s); 3118 return; 3119 } 3120 3121 for (unsigned int i = scale; i > 0; i--) 3122 sdiv *= 10; 3123 3124 printf("%u", base / sdiv); 3125 3126 if (scale != 0) { 3127 printf(".%u", base % sdiv); 3128 } 3129 printf ("W\n"); 3130 return; 3131 } 3132 3133 static const char * 3134 pci_conf_print_pwrbdgt_type(uint8_t reg) 3135 { 3136 3137 switch (reg) { 3138 case 0x00: 3139 return "PME Aux"; 3140 case 0x01: 3141 return "Auxilary"; 3142 case 0x02: 3143 return "Idle"; 3144 case 0x03: 3145 return "Sustained"; 3146 case 0x04: 3147 return "Sustained (Emergency Power Reduction)"; 3148 case 0x05: 3149 return "Maximum (Emergency Power Reduction)"; 3150 case 0x07: 3151 return "Maximum"; 3152 default: 3153 return "Unknown"; 3154 } 3155 } 3156 3157 static const char * 3158 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 3159 { 3160 3161 switch (reg) { 3162 case 0x00: 3163 return "Power(12V)"; 3164 case 0x01: 3165 return "Power(3.3V)"; 3166 case 0x02: 3167 return "Power(1.5V or 1.8V)"; 3168 case 0x07: 3169 return "Thermal"; 3170 default: 3171 return "Unknown"; 3172 } 3173 } 3174 3175 static void 3176 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int extcapoff) 3177 { 3178 pcireg_t reg; 3179 3180 printf("\n Power Budgeting\n"); 3181 3182 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 3183 printf(" Data Select register: 0x%08x\n", reg); 3184 3185 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 3186 printf(" Data register: 0x%08x\n", reg); 3187 printf(" Base Power: "); 3188 pci_conf_print_pcie_power( 3189 PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_DATA_BASEPWR), 3190 PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE)); 3191 printf(" PM Sub State: 0x%hhx\n", 3192 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 3193 printf(" PM State: D%u\n", 3194 PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 3195 printf(" Type: %s\n", 3196 pci_conf_print_pwrbdgt_type( 3197 (uint8_t)(PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 3198 printf(" Power Rail: %s\n", 3199 pci_conf_print_pwrbdgt_pwrrail( 3200 (uint8_t)(PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 3201 3202 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 3203 printf(" Power Budget Capability register: 0x%08x\n", reg); 3204 onoff("System Allocated", 3205 reg, PCI_PWRBDGT_CAP_SYSALLOC); 3206 } 3207 3208 static const char * 3209 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 3210 { 3211 3212 switch (type) { 3213 case 0x00: 3214 return "Configuration Space Element"; 3215 case 0x01: 3216 return "System Egress Port or internal sink (memory)"; 3217 case 0x02: 3218 return "Internal Root Complex Link"; 3219 default: 3220 return "Unknown"; 3221 } 3222 } 3223 3224 static void 3225 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int extcapoff) 3226 { 3227 pcireg_t reg; 3228 unsigned char nent, linktype; 3229 int i; 3230 3231 printf("\n Root Complex Link Declaration\n"); 3232 3233 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 3234 printf(" Element Self Description Register: 0x%08x\n", reg); 3235 printf(" Element Type: %s\n", 3236 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 3237 nent = PCIREG_SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 3238 printf(" Number of Link Entries: %hhu\n", nent); 3239 printf(" Component ID: %hhu\n", 3240 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 3241 printf(" Port Number: %hhu\n", 3242 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 3243 for (i = 0; i < nent; i++) { 3244 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 3245 printf(" Link Entry %d:\n", i + 1); 3246 printf(" Link Description Register: 0x%08x\n", reg); 3247 onoff(" Link Valid", reg, PCI_RCLINK_DCL_LINKDESC_LVALID); 3248 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 3249 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 3250 "Configuration Space", "Memory-Mapped Space"); 3251 onoff(" Associated RCRB Header", reg, 3252 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 3253 printf(" Target Component ID: %hhu\n", 3254 (uint8_t)PCIREG_SHIFTOUT(reg, 3255 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 3256 printf(" Target Port Number: %hhu\n", 3257 (uint8_t)PCIREG_SHIFTOUT(reg, 3258 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 3259 3260 if (linktype == 0) { 3261 /* Memory-Mapped Space */ 3262 reg = regs[o2i(extcapoff 3263 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 3264 printf(" Link Address Low Register: 0x%08x\n", 3265 reg); 3266 reg = regs[o2i(extcapoff 3267 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 3268 printf(" Link Address High Register: 0x%08x\n", 3269 reg); 3270 } else { 3271 unsigned int nb; 3272 pcireg_t lo, hi; 3273 3274 /* Configuration Space */ 3275 lo = regs[o2i(extcapoff 3276 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 3277 printf(" Configuration Space Low Register: " 3278 "0x%08x\n", lo); 3279 hi = regs[o2i(extcapoff 3280 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 3281 printf(" Configuration Space High Register: " 3282 "0x%08x\n", hi); 3283 nb = PCIREG_SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 3284 printf(" N: %u\n", nb); 3285 printf(" Func: %hhu\n", 3286 (uint8_t)PCIREG_SHIFTOUT(lo, 3287 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 3288 printf(" Dev: %hhu\n", 3289 (uint8_t)PCIREG_SHIFTOUT(lo, 3290 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 3291 printf(" Bus: %hhu\n", 3292 (uint8_t)PCIREG_SHIFTOUT(lo, 3293 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 3294 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 3295 printf(" Configuration Space Base Address: " 3296 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 3297 } 3298 } 3299 } 3300 3301 /* XXX pci_conf_print_rclink_ctl_cap */ 3302 3303 static void 3304 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int extcapoff) 3305 { 3306 pcireg_t reg; 3307 3308 printf("\n Root Complex Event Collector Association\n"); 3309 3310 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 3311 printf(" Association Bitmap for Root Complex Integrated Devices:" 3312 " 0x%08x\n", reg); 3313 3314 if (PCI_EXTCAPLIST_VERSION(regs[o2i(extcapoff)]) >= 2) { 3315 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBUSNUM)]; 3316 printf(" RCEC Associated Bus Numbers register: 0x%08x\n", 3317 reg); 3318 printf(" RCEC Next Bus: %u\n", 3319 PCIREG_SHIFTOUT(reg, 3320 PCI_RCEC_ASSOCBUSNUM_RCECNEXT)); 3321 printf(" RCEC Last Bus: %u\n", 3322 PCIREG_SHIFTOUT(reg, 3323 PCI_RCEC_ASSOCBUSNUM_RCECLAST)); 3324 } 3325 } 3326 3327 /* XXX pci_conf_print_mfvc_cap */ 3328 /* XXX pci_conf_print_vc2_cap */ 3329 /* XXX pci_conf_print_rcrb_cap */ 3330 /* XXX pci_conf_print_vendor_cap */ 3331 /* XXX pci_conf_print_cac_cap */ 3332 3333 static void 3334 pci_conf_print_acs_cap(const pcireg_t *regs, int extcapoff) 3335 { 3336 pcireg_t reg, cap, ctl; 3337 unsigned int size, i; 3338 3339 printf("\n Access Control Services\n"); 3340 3341 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 3342 cap = reg & 0xffff; 3343 ctl = reg >> 16; 3344 printf(" ACS Capability register: 0x%08x\n", cap); 3345 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 3346 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 3347 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 3348 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 3349 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 3350 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 3351 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 3352 size = PCIREG_SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 3353 if (size == 0) 3354 size = 256; 3355 printf(" Egress Control Vector Size: %u\n", size); 3356 printf(" ACS Control register: 0x%08x\n", ctl); 3357 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 3358 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 3359 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 3360 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 3361 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 3362 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 3363 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 3364 3365 /* 3366 * If the P2P Egress Control Capability bit is 0, ignore the Egress 3367 * Control vector. 3368 */ 3369 if ((cap & PCI_ACS_CAP_E) == 0) 3370 return; 3371 for (i = 0; i < size; i += 32) 3372 printf(" Egress Control Vector [%u..%u]: 0x%08x\n", i + 31, 3373 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 3374 } 3375 3376 static void 3377 pci_conf_print_ari_cap(const pcireg_t *regs, int extcapoff) 3378 { 3379 pcireg_t reg, cap, ctl; 3380 3381 printf("\n Alternative Routing-ID Interpretation Register\n"); 3382 3383 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3384 cap = reg & 0xffff; 3385 ctl = reg >> 16; 3386 printf(" Capability register: 0x%08x\n", cap); 3387 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 3388 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 3389 printf(" Next Function Number: %u\n", 3390 PCIREG_SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 3391 printf(" Control register: 0x%08x\n", ctl); 3392 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 3393 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 3394 printf(" Function Group: %u\n", 3395 PCIREG_SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 3396 } 3397 3398 static void 3399 pci_conf_print_ats_cap(const pcireg_t *regs, int extcapoff) 3400 { 3401 pcireg_t reg, cap, ctl; 3402 unsigned int num; 3403 3404 printf("\n Address Translation Services\n"); 3405 3406 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3407 cap = reg & 0xffff; 3408 ctl = reg >> 16; 3409 printf(" Capability register: 0x%04x\n", cap); 3410 num = PCIREG_SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 3411 if (num == 0) 3412 num = 32; 3413 printf(" Invalidate Queue Depth: %u\n", num); 3414 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 3415 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 3416 onoff("Relaxed Ordering", reg, PCI_ATS_CAP_RELAXORD); 3417 3418 printf(" Control register: 0x%04x\n", ctl); 3419 printf(" Smallest Translation Unit: %u\n", 3420 PCIREG_SHIFTOUT(reg, PCI_ATS_CTL_STU)); 3421 onoff("Enable", reg, PCI_ATS_CTL_EN); 3422 } 3423 3424 static void 3425 pci_conf_print_sernum_cap(const pcireg_t *regs, int extcapoff) 3426 { 3427 pcireg_t lo, hi; 3428 3429 printf("\n Device Serial Number Register\n"); 3430 3431 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 3432 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 3433 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 3434 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 3435 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 3436 } 3437 3438 static void 3439 pci_conf_print_sriov_cap(const pcireg_t *regs, int extcapoff) 3440 { 3441 char buf[sizeof("99999 MB")]; 3442 pcireg_t reg; 3443 pcireg_t total_vfs; 3444 int i; 3445 bool first; 3446 3447 printf("\n Single Root IO Virtualization Register\n"); 3448 3449 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 3450 printf(" Capabilities register: 0x%08x\n", reg); 3451 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 3452 onoff("ARI Capable Hierarchy Preserved", reg, 3453 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 3454 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 3455 printf(" VF Migration Interrupt Message Number: 0x%03x\n", 3456 PCIREG_SHIFTOUT(reg, PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 3457 } 3458 3459 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 3460 printf(" Control register: 0x%04x\n", reg); 3461 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 3462 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 3463 onoff("VF Migration Interrupt Enable", reg, 3464 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 3465 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 3466 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 3467 3468 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 3469 printf(" Status register: 0x%04x\n", reg); 3470 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 3471 3472 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 3473 printf(" InitialVFs register: 0x%04x\n", reg); 3474 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 3475 printf(" TotalVFs register: 0x%04x\n", reg); 3476 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 3477 printf(" NumVFs register: 0x%04x\n", reg); 3478 3479 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 3480 printf(" Function Dependency Link register: 0x%04x\n", reg); 3481 3482 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 3483 printf(" First VF Offset register: 0x%04x\n", reg); 3484 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 3485 printf(" VF Stride register: 0x%04x\n", reg); 3486 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16; 3487 printf(" Device ID: 0x%04x\n", reg); 3488 3489 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 3490 printf(" Supported Page Sizes register: 0x%08x\n", reg); 3491 printf(" Supported Page Size:"); 3492 for (i = 0, first = true; i < 32; i++) { 3493 if (reg & __BIT(i)) { 3494 #ifdef _KERNEL 3495 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 3496 #else 3497 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 3498 HN_AUTOSCALE, 0); 3499 #endif 3500 printf("%s %s", first ? "" : ",", buf); 3501 first = false; 3502 } 3503 } 3504 printf("\n"); 3505 3506 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 3507 printf(" System Page Sizes register: 0x%08x\n", reg); 3508 printf(" Page Size: "); 3509 if (reg != 0) { 3510 int bitpos = ffs(reg) -1; 3511 3512 /* Assume only one bit is set. */ 3513 #ifdef _KERNEL 3514 format_bytes(buf, sizeof(buf), 1LL << (bitpos + 12)); 3515 #else 3516 humanize_number(buf, sizeof(buf), 1LL << (bitpos + 12), 3517 "B", HN_AUTOSCALE, 0); 3518 #endif 3519 printf("%s", buf); 3520 } else { 3521 printf("unknown"); 3522 } 3523 printf("\n"); 3524 3525 for (i = 0; i < 6; i++) { 3526 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 3527 printf(" VF BAR%d register: 0x%08x\n", i, reg); 3528 } 3529 3530 if (total_vfs > 0) { 3531 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 3532 printf(" VF Migration State Array Offset register: 0x%08x\n", 3533 reg); 3534 printf(" VF Migration State Offset: 0x%08x\n", 3535 PCIREG_SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 3536 i = PCIREG_SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 3537 printf(" VF Migration State BIR: "); 3538 if (i >= 0 && i <= 5) { 3539 printf("BAR%d", i); 3540 } else { 3541 printf("unknown BAR (%d)", i); 3542 } 3543 printf("\n"); 3544 } 3545 } 3546 3547 /* XXX pci_conf_print_mriov_cap */ 3548 3549 static void 3550 pci_conf_print_multicast_cap(const pcireg_t *regs, int extcapoff) 3551 { 3552 pcireg_t reg, cap, ctl; 3553 pcireg_t regl, regh; 3554 uint64_t addr; 3555 int n; 3556 3557 printf("\n Multicast\n"); 3558 3559 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 3560 cap = reg & 0xffff; 3561 ctl = reg >> 16; 3562 printf(" Capability Register: 0x%04x\n", cap); 3563 printf(" Max Group: %u\n", 3564 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 3565 3566 /* Endpoint Only */ 3567 n = PCIREG_SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 3568 if (n > 0) 3569 printf(" Window Size Requested: %d\n", 1 << (n - 1)); 3570 3571 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 3572 3573 printf(" Control Register: 0x%04x\n", ctl); 3574 printf(" Num Group: %u\n", 3575 PCIREG_SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 3576 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 3577 3578 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 3579 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 3580 printf(" Base Address Register 0: 0x%08x\n", regl); 3581 printf(" Base Address Register 1: 0x%08x\n", regh); 3582 printf(" Index Position: %u\n", 3583 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 3584 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 3585 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 3586 3587 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 3588 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 3589 printf(" Receive Register 0: 0x%08x\n", regl); 3590 printf(" Receive Register 1: 0x%08x\n", regh); 3591 3592 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 3593 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 3594 printf(" Block All Register 0: 0x%08x\n", regl); 3595 printf(" Block All Register 1: 0x%08x\n", regh); 3596 3597 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 3598 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 3599 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 3600 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 3601 3602 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 3603 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 3604 printf(" Overlay BAR 0: 0x%08x\n", regl); 3605 printf(" Overlay BAR 1: 0x%08x\n", regh); 3606 3607 n = regl & PCI_MCAST_OVERLAYL_SIZE; 3608 printf(" Overlay Size: "); 3609 if (n >= 6) 3610 printf("%d\n", n); 3611 else 3612 printf("off\n"); 3613 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 3614 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 3615 } 3616 3617 static void 3618 pci_conf_print_page_req_cap(const pcireg_t *regs, int extcapoff) 3619 { 3620 pcireg_t reg, ctl, sta; 3621 3622 printf("\n Page Request\n"); 3623 3624 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 3625 ctl = reg & 0xffff; 3626 sta = reg >> 16; 3627 printf(" Control Register: 0x%04x\n", ctl); 3628 onoff("Enable", reg, PCI_PAGE_REQ_CTL_E); 3629 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 3630 3631 printf(" Status Register: 0x%04x\n", sta); 3632 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 3633 onoff("Unexpected Page Request Group Index", reg, 3634 PCI_PAGE_REQ_STA_UPRGI); 3635 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 3636 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 3637 3638 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 3639 printf(" Outstanding Page Request Capacity: %u\n", reg); 3640 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 3641 printf(" Outstanding Page Request Allocation: %u\n", reg); 3642 } 3643 3644 /* XXX pci_conf_print_amd_cap */ 3645 3646 #define MEM_PBUFSIZE sizeof("999GB") 3647 3648 static void 3649 pci_conf_print_resizbar_cap(const pcireg_t *regs, int extcapoff) 3650 { 3651 pcireg_t cap, ctl; 3652 unsigned int bars, i, n; 3653 char pbuf[MEM_PBUFSIZE]; 3654 3655 printf("\n Resizable BAR\n"); 3656 3657 /* Get Number of Resizable BARs */ 3658 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))]; 3659 bars = PCIREG_SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR); 3660 printf(" Number of Resizable BARs: "); 3661 if (bars <= 6) 3662 printf("%u\n", bars); 3663 else { 3664 printf("incorrect (%u)\n", bars); 3665 return; 3666 } 3667 3668 for (n = 0; n < 6; n++) { 3669 cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))]; 3670 printf(" Capability register(%u): 0x%08x\n", n, cap); 3671 if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0) 3672 continue; /* Not Used */ 3673 printf(" Acceptable BAR sizes:"); 3674 for (i = 4; i <= 23; i++) { 3675 if ((cap & (1 << i)) != 0) { 3676 humanize_number(pbuf, MEM_PBUFSIZE, 3677 (int64_t)1024 * 1024 << (i - 4), "B", 3678 #ifdef _KERNEL 3679 1); 3680 #else 3681 HN_AUTOSCALE, HN_NOSPACE); 3682 #endif 3683 printf(" %s", pbuf); 3684 } 3685 } 3686 printf("\n"); 3687 3688 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))]; 3689 printf(" Control register(%u): 0x%08x\n", n, ctl); 3690 printf(" BAR Index: %u\n", 3691 PCIREG_SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX)); 3692 humanize_number(pbuf, MEM_PBUFSIZE, 3693 (int64_t)1024 * 1024 3694 << PCIREG_SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ), 3695 "B", 3696 #ifdef _KERNEL 3697 1); 3698 #else 3699 HN_AUTOSCALE, HN_NOSPACE); 3700 #endif 3701 printf(" BAR Size: %s\n", pbuf); 3702 } 3703 } 3704 3705 static void 3706 pci_conf_print_dpa_cap(const pcireg_t *regs, int extcapoff) 3707 { 3708 pcireg_t reg; 3709 unsigned int substmax, i; 3710 3711 printf("\n Dynamic Power Allocation\n"); 3712 3713 reg = regs[o2i(extcapoff + PCI_DPA_CAP)]; 3714 printf(" Capability register: 0x%08x\n", reg); 3715 substmax = PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX); 3716 printf(" Substate Max: %u\n", substmax); 3717 printf(" Transition Latency Unit: "); 3718 switch (PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) { 3719 case 0: 3720 printf("1ms\n"); 3721 break; 3722 case 1: 3723 printf("10ms\n"); 3724 break; 3725 case 2: 3726 printf("100ms\n"); 3727 break; 3728 default: 3729 printf("reserved\n"); 3730 break; 3731 } 3732 printf(" Power Allocation Scale: "); 3733 switch (PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_PAS)) { 3734 case 0: 3735 printf("10.0x\n"); 3736 break; 3737 case 1: 3738 printf("1.0x\n"); 3739 break; 3740 case 2: 3741 printf("0.1x\n"); 3742 break; 3743 case 3: 3744 printf("0.01x\n"); 3745 break; 3746 } 3747 printf(" Transition Latency Value 0: %u\n", 3748 PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_XLCY0)); 3749 printf(" Transition Latency Value 1: %u\n", 3750 PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); 3751 3752 reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; 3753 printf(" Latency Indicator register: 0x%08x\n", reg); 3754 3755 reg = regs[o2i(extcapoff + PCI_DPA_CS)]; 3756 printf(" Status register: 0x%04x\n", reg & 0xffff); 3757 printf(" Substate Status: 0x%02x\n", 3758 PCIREG_SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT)); 3759 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN); 3760 printf(" Control register: 0x%04x\n", reg >> 16); 3761 printf(" Substate Control: 0x%02x\n", 3762 PCIREG_SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL)); 3763 3764 for (i = 0; i <= substmax; i++) 3765 printf(" Substate Power Allocation register %d: 0x%02x\n", 3766 i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff)); 3767 } 3768 3769 static const char * 3770 pci_conf_print_tph_req_cap_sttabloc(uint8_t val) 3771 { 3772 3773 switch (val) { 3774 case PCI_TPH_REQ_STTBLLOC_NONE: 3775 return "Not Present"; 3776 case PCI_TPH_REQ_STTBLLOC_TPHREQ: 3777 return "in the TPH Requester Capability Structure"; 3778 case PCI_TPH_REQ_STTBLLOC_MSIX: 3779 return "in the MSI-X Table"; 3780 default: 3781 return "Unknown"; 3782 } 3783 } 3784 3785 static void 3786 pci_conf_print_tph_req_cap(const pcireg_t *regs, int extcapoff) 3787 { 3788 pcireg_t reg; 3789 int size = 0, i, j; 3790 uint8_t sttbloc; 3791 3792 printf("\n TPH Requester Extended Capability\n"); 3793 3794 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3795 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3796 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3797 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3798 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3799 onoff("Extend TPH Requester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3800 sttbloc = PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC); 3801 printf(" ST Table Location: %s\n", 3802 pci_conf_print_tph_req_cap_sttabloc(sttbloc)); 3803 if (sttbloc == PCI_TPH_REQ_STTBLLOC_TPHREQ) { 3804 size = PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3805 printf(" ST Table Size: %d\n", size); 3806 } 3807 3808 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CTL)]; 3809 printf(" TPH Requester Control register: 0x%08x\n", reg); 3810 printf(" ST Mode Select: "); 3811 switch (PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CTL_STSEL)) { 3812 case PCI_TPH_REQ_CTL_STSEL_NO: 3813 printf("No ST Mode\n"); 3814 break; 3815 case PCI_TPH_REQ_CTL_STSEL_IV: 3816 printf("Interrupt Vector Mode\n"); 3817 break; 3818 case PCI_TPH_REQ_CTL_STSEL_DS: 3819 printf("Device Specific Mode\n"); 3820 break; 3821 default: 3822 printf("(reserved value)\n"); 3823 break; 3824 } 3825 printf(" TPH Requester Enable: "); 3826 switch (PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CTL_TPHREQEN)) { 3827 case PCI_TPH_REQ_CTL_TPHREQEN_NO: /* 0x0 */ 3828 printf("Not permitted\n"); 3829 break; 3830 case PCI_TPH_REQ_CTL_TPHREQEN_TPH: 3831 printf("TPH and not Extended TPH\n"); 3832 break; 3833 case PCI_TPH_REQ_CTL_TPHREQEN_ETPH: 3834 printf("TPH and Extended TPH"); 3835 break; 3836 default: 3837 printf("(reserved value)\n"); 3838 break; 3839 } 3840 3841 if (sttbloc != PCI_TPH_REQ_STTBLLOC_TPHREQ) 3842 return; 3843 3844 for (i = 0; i < size ; i += 2) { 3845 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3846 for (j = 0; j < 2 ; j++) { 3847 uint32_t entry = reg; 3848 3849 if (j != 0) 3850 entry >>= 16; 3851 entry &= 0xffff; 3852 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3853 i + j, entry); 3854 } 3855 } 3856 } 3857 3858 static void 3859 pci_conf_print_ltr_cap(const pcireg_t *regs, int extcapoff) 3860 { 3861 pcireg_t reg; 3862 3863 printf("\n Latency Tolerance Reporting\n"); 3864 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)]; 3865 printf(" Max Snoop Latency Register: 0x%04x\n", reg & 0xffff); 3866 printf(" Max Snoop Latency: %juns\n", 3867 (uintmax_t)(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL) 3868 * PCI_LTR_SCALETONS(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE)))); 3869 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg >> 16); 3870 printf(" Max No-Snoop Latency: %juns\n", 3871 (uintmax_t)(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL) 3872 * PCI_LTR_SCALETONS(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE)))); 3873 } 3874 3875 static void 3876 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int extcapoff) 3877 { 3878 int pcie_capoff; 3879 pcireg_t reg; 3880 int i, maxlinkwidth; 3881 3882 printf("\n Secondary PCI Express Register\n"); 3883 3884 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3885 printf(" Link Control 3 register: 0x%08x\n", reg); 3886 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3887 onoff("Link Equalization Request Interrupt Enable", 3888 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3889 printf(" Enable Lower SKP OS Generation Vector:"); 3890 pci_print_pcie_linkspeedvector( 3891 PCIREG_SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3892 printf("\n"); 3893 3894 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3895 printf(" Lane Error Status register: 0x%08x\n", reg); 3896 3897 /* Get Max Link Width */ 3898 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 3899 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3900 maxlinkwidth = PCIREG_SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3901 } else { 3902 printf("error: falied to get PCIe capablity\n"); 3903 return; 3904 } 3905 for (i = 0; i < maxlinkwidth; i++) { 3906 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3907 if (i % 2 != 0) 3908 reg >>= 16; 3909 else 3910 reg &= 0xffff; 3911 printf(" Equalization Control Register (Link %d): 0x%04x\n", 3912 i, reg); 3913 printf(" Downstream Port Transmit Preset: 0x%x\n", 3914 PCIREG_SHIFTOUT(reg, 3915 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3916 printf(" Downstream Port Receive Hint: 0x%x\n", 3917 PCIREG_SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3918 printf(" Upstream Port Transmit Preset: 0x%x\n", 3919 PCIREG_SHIFTOUT(reg, 3920 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3921 printf(" Upstream Port Receive Hint: 0x%x\n", 3922 PCIREG_SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3923 } 3924 } 3925 3926 /* XXX pci_conf_print_pmux_cap */ 3927 3928 static void 3929 pci_conf_print_pasid_cap(const pcireg_t *regs, int extcapoff) 3930 { 3931 pcireg_t reg, cap, ctl; 3932 unsigned int num; 3933 3934 printf("\n Process Address Space ID\n"); 3935 3936 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3937 cap = reg & 0xffff; 3938 ctl = reg >> 16; 3939 printf(" PASID Capability Register: 0x%04x\n", cap); 3940 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3941 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3942 num = (1 << PCIREG_SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3943 printf(" Max PASID Width: %u\n", num); 3944 3945 printf(" PASID Control Register: 0x%04x\n", ctl); 3946 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3947 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3948 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3949 } 3950 3951 static void 3952 pci_conf_print_lnr_cap(const pcireg_t *regs, int extcapoff) 3953 { 3954 pcireg_t reg, cap, ctl; 3955 unsigned int num; 3956 3957 printf("\n LN Requester\n"); 3958 3959 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3960 cap = reg & 0xffff; 3961 ctl = reg >> 16; 3962 printf(" LNR Capability register: 0x%04x\n", cap); 3963 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 3964 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 3965 num = 1 << PCIREG_SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 3966 printf(" LNR Registration MAX: %u\n", num); 3967 3968 printf(" LNR Control register: 0x%04x\n", ctl); 3969 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 3970 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 3971 num = 1 << PCIREG_SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 3972 printf(" LNR Registration Limit: %u\n", num); 3973 } 3974 3975 static void 3976 pci_conf_print_dpc_pio(pcireg_t r) 3977 { 3978 onoff("Cfg Request received UR Completion", r,PCI_DPC_RPPIO_CFGUR_CPL); 3979 onoff("Cfg Request received CA Completion", r,PCI_DPC_RPPIO_CFGCA_CPL); 3980 onoff("Cfg Request Completion Timeout", r, PCI_DPC_RPPIO_CFG_CTO); 3981 onoff("I/O Request received UR Completion", r, PCI_DPC_RPPIO_IOUR_CPL); 3982 onoff("I/O Request received CA Completion", r, PCI_DPC_RPPIO_IOCA_CPL); 3983 onoff("I/O Request Completion Timeout", r, PCI_DPC_RPPIO_IO_CTO); 3984 onoff("Mem Request received UR Completion", r,PCI_DPC_RPPIO_MEMUR_CPL); 3985 onoff("Mem Request received CA Completion", r,PCI_DPC_RPPIO_MEMCA_CPL); 3986 onoff("Mem Request Completion Timeout", r, PCI_DPC_RPPIO_MEM_CTO); 3987 } 3988 3989 static void 3990 pci_conf_print_dpc_cap(const pcireg_t *regs, int extcapoff) 3991 { 3992 pcireg_t reg, cap, ctl, stat, errsrc; 3993 const char *trigstr; 3994 bool rpext; 3995 3996 printf("\n Downstream Port Containment\n"); 3997 3998 reg = regs[o2i(extcapoff + PCI_DPC_CCR)]; 3999 cap = reg & 0xffff; 4000 ctl = reg >> 16; 4001 rpext = (reg & PCI_DPCCAP_RPEXT) ? true : false; 4002 printf(" DPC Capability register: 0x%04x\n", cap); 4003 printf(" DPC Interrupt Message Number: %02x\n", 4004 (unsigned int)(cap & PCI_DPCCAP_IMSGN)); 4005 onoff("RP Extensions for DPC", reg, PCI_DPCCAP_RPEXT); 4006 onoff("Poisoned TLP Egress Blocking Supported", reg, 4007 PCI_DPCCAP_POISONTLPEB); 4008 onoff("DPC Software Triggering Supported", reg, PCI_DPCCAP_SWTRIG); 4009 printf(" RP PIO Log Size: %u\n", 4010 PCIREG_SHIFTOUT(reg, PCI_DPCCAP_RPPIOLOGSZ)); 4011 onoff("DL_Active ERR_COR Signaling Supported", reg, 4012 PCI_DPCCAP_DLACTECORS); 4013 printf(" DPC Control register: 0x%04x\n", ctl); 4014 switch (PCIREG_SHIFTOUT(reg, PCI_DPCCTL_TIRGEN)) { 4015 case 0: 4016 trigstr = "disabled"; 4017 break; 4018 case 1: 4019 trigstr = "enabled(ERR_FATAL)"; 4020 break; 4021 case 2: 4022 trigstr = "enabled(ERR_NONFATAL or ERR_FATAL)"; 4023 break; 4024 default: 4025 trigstr = "(reserverd)"; 4026 break; 4027 } 4028 printf(" DPC Trigger Enable: %s\n", trigstr); 4029 printf(" DPC Completion Control: %s Completion Status\n", 4030 (reg & PCI_DPCCTL_COMPCTL) 4031 ? "Unsupported Request(UR)" : "Completer Abort(CA)"); 4032 onoff("DPC Interrupt Enable", reg, PCI_DPCCTL_IE); 4033 onoff("DPC ERR_COR Enable", reg, PCI_DPCCTL_ERRCOREN); 4034 onoff("Poisoned TLP Egress Blocking Enable", reg, 4035 PCI_DPCCTL_POISONTLPEB); 4036 onoff("DPC Software Trigger", reg, PCI_DPCCTL_SWTRIG); 4037 onoff("DL_Active ERR_COR Enable", reg, PCI_DPCCTL_DLACTECOR); 4038 4039 reg = regs[o2i(extcapoff + PCI_DPC_STATESID)]; 4040 stat = reg & 0xffff; 4041 errsrc = reg >> 16; 4042 printf(" DPC Status register: 0x%04x\n", stat); 4043 onoff("DPC Trigger Status", reg, PCI_DPCSTAT_TSTAT); 4044 switch (PCIREG_SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 4045 case 0: 4046 trigstr = "an unmasked uncorrectable error"; 4047 break; 4048 case 1: 4049 trigstr = "receiving an ERR_NONFATAL"; 4050 break; 4051 case 2: 4052 trigstr = "receiving an ERR_FATAL"; 4053 break; 4054 case 3: 4055 trigstr = "DPC Trigger Reason Extension field"; 4056 break; 4057 } 4058 printf(" DPC Trigger Reason: Due to %s\n", trigstr); 4059 onoff("DPC Interrupt Status", reg, PCI_DPCSTAT_ISTAT); 4060 if (rpext) 4061 onoff("DPC RP Busy", reg, PCI_DPCSTAT_RPBUSY); 4062 switch (PCIREG_SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 4063 case 0: 4064 trigstr = "Due to RP PIO error"; 4065 break; 4066 case 1: 4067 trigstr = "Due to the DPC Software trigger bit"; 4068 break; 4069 default: 4070 trigstr = "(reserved)"; 4071 break; 4072 } 4073 printf(" DPC Trigger Reason Extension: %s\n", trigstr); 4074 if (rpext) 4075 printf(" RP PIO First Error Pointer: 0x%02x\n", 4076 PCIREG_SHIFTOUT(reg, PCI_DPCSTAT_RPPIOFEP)); 4077 printf(" DPC Error Source ID register: 0x%04x\n", errsrc); 4078 4079 if (!rpext) 4080 return; 4081 /* 4082 * All of the following registers are implemented by a device which has 4083 * RP Extensions for DPC 4084 */ 4085 4086 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_STAT)]; 4087 printf(" RP PIO Status Register: 0x%08x\n", reg); 4088 pci_conf_print_dpc_pio(reg); 4089 4090 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_MASK)]; 4091 printf(" RP PIO Mask Register: 0x%08x\n", reg); 4092 pci_conf_print_dpc_pio(reg); 4093 4094 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SEVE)]; 4095 printf(" RP PIO Severity Register: 0x%08x\n", reg); 4096 pci_conf_print_dpc_pio(reg); 4097 4098 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SYSERR)]; 4099 printf(" RP PIO SysError Register: 0x%08x\n", reg); 4100 pci_conf_print_dpc_pio(reg); 4101 4102 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_EXCPT)]; 4103 printf(" RP PIO Exception Register: 0x%08x\n", reg); 4104 pci_conf_print_dpc_pio(reg); 4105 4106 printf(" RP PIO Header Log Register: start from 0x%03x\n", 4107 extcapoff + PCI_DPC_RPPIO_HLOG); 4108 printf(" RP PIO ImpSpec Log Register: start from 0x%03x\n", 4109 extcapoff + PCI_DPC_RPPIO_IMPSLOG); 4110 printf(" RP PIO TLP Prefix Log Register: start from 0x%03x\n", 4111 extcapoff + PCI_DPC_RPPIO_TLPPLOG); 4112 } 4113 4114 4115 static int 4116 pci_conf_l1pm_cap_tposcale(unsigned char scale) 4117 { 4118 4119 /* Return scale in us */ 4120 switch (scale) { 4121 case 0x0: 4122 return 2; 4123 case 0x1: 4124 return 10; 4125 case 0x2: 4126 return 100; 4127 default: 4128 return -1; 4129 } 4130 } 4131 4132 static void 4133 pci_conf_print_l1pm_cap(const pcireg_t *regs, int extcapoff) 4134 { 4135 pcireg_t reg; 4136 int scale, val; 4137 int pcie_capoff; 4138 4139 printf("\n L1 PM Substates\n"); 4140 4141 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 4142 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 4143 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 4144 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 4145 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 4146 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 4147 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 4148 /* The Link Activation Supported bit is only for Downstream Port */ 4149 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 4150 uint32_t t = regs[o2i(pcie_capoff)]; 4151 4152 if ((t == PCIE_XCAP_TYPE_RP) || (t == PCIE_XCAP_TYPE_DOWN)) 4153 onoff("Link Activation Supported", reg, 4154 PCI_L1PM_CAP_LA); 4155 } 4156 printf(" Port Common Mode Restore Time: %uus\n", 4157 PCIREG_SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 4158 scale = pci_conf_l1pm_cap_tposcale( 4159 PCIREG_SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 4160 val = PCIREG_SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 4161 printf(" Port T_POWER_ON: "); 4162 if (scale == -1) 4163 printf("unknown\n"); 4164 else 4165 printf("%dus\n", val * scale); 4166 4167 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 4168 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 4169 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 4170 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 4171 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 4172 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 4173 onoff("Link Activation Interrupt Enable", reg, PCI_L1PM_CTL1_LAIE); 4174 onoff("Link Activation Control", reg, PCI_L1PM_CTL1_LA); 4175 printf(" Common Mode Restore Time: %uus\n", 4176 PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 4177 scale = PCI_LTR_SCALETONS(PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 4178 val = PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 4179 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 4180 4181 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 4182 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 4183 scale = pci_conf_l1pm_cap_tposcale( 4184 PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 4185 val = PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 4186 printf(" T_POWER_ON: "); 4187 if (scale == -1) 4188 printf("unknown\n"); 4189 else 4190 printf("%dus\n", val * scale); 4191 4192 if (PCI_EXTCAPLIST_VERSION(regs[o2i(extcapoff)]) >= 2) { 4193 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 4194 printf(" L1 PM Substates Status register: 0x%08x\n", reg); 4195 onoff("Link Activation Status", reg, PCI_L1PM_STAT_LA); 4196 } 4197 } 4198 4199 static void 4200 pci_conf_print_ptm_cap(const pcireg_t *regs, int extcapoff) 4201 { 4202 pcireg_t reg; 4203 uint32_t val; 4204 4205 printf("\n Precision Time Measurement\n"); 4206 4207 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 4208 printf(" PTM Capability register: 0x%08x\n", reg); 4209 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 4210 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 4211 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 4212 printf(" Local Clock Granularity: "); 4213 val = PCIREG_SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 4214 switch (val) { 4215 case 0: 4216 printf("Not implemented\n"); 4217 break; 4218 case 0xffff: 4219 printf("> 254ns\n"); 4220 break; 4221 default: 4222 printf("%uns\n", val); 4223 break; 4224 } 4225 4226 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 4227 printf(" PTM Control register: 0x%08x\n", reg); 4228 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 4229 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 4230 printf(" Effective Granularity: "); 4231 val = PCIREG_SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 4232 switch (val) { 4233 case 0: 4234 printf("Unknown\n"); 4235 break; 4236 case 0xffff: 4237 printf("> 254ns\n"); 4238 break; 4239 default: 4240 printf("%uns\n", val); 4241 break; 4242 } 4243 } 4244 4245 /* XXX pci_conf_print_mpcie_cap */ 4246 /* XXX pci_conf_print_frsq_cap */ 4247 /* XXX pci_conf_print_rtr_cap */ 4248 /* XXX pci_conf_print_desigvndsp_cap */ 4249 /* XXX pci_conf_print_vf_resizbar_cap */ 4250 4251 static void 4252 pci_conf_print_dlf_cap(const pcireg_t *regs, int extcapoff) 4253 { 4254 pcireg_t reg; 4255 4256 printf("\n Data link Feature Register\n"); 4257 reg = regs[o2i(extcapoff + PCI_DLF_CAP)]; 4258 printf(" Capability register: 0x%08x\n", reg); 4259 onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL); 4260 onoff("DLF Exchange enable", reg, PCI_DLF_CAP_XCHG); 4261 4262 reg = regs[o2i(extcapoff + PCI_DLF_STAT)]; 4263 printf(" Status register: 0x%08x\n", reg); 4264 onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL); 4265 onoff("Remote DLF supported Valid", reg, PCI_DLF_STAT_RMTVALID); 4266 } 4267 4268 /* XXX pci_conf_print_hierarchyid_cap */ 4269 /* XXX pci_conf_print_npem_cap */ 4270 4271 #undef MS 4272 #undef SM 4273 #undef RW 4274 4275 static struct { 4276 pcireg_t cap; 4277 const char *name; 4278 void (*printfunc)(const pcireg_t *, int); 4279 } pci_extcaptab[] = { 4280 { 0, "reserved", 4281 NULL }, 4282 { PCI_EXTCAP_AER, "Advanced Error Reporting", 4283 pci_conf_print_aer_cap }, 4284 { PCI_EXTCAP_VC, "Virtual Channel", 4285 pci_conf_print_vc_cap }, 4286 { PCI_EXTCAP_SERNUM, "Device Serial Number", 4287 pci_conf_print_sernum_cap }, 4288 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 4289 pci_conf_print_pwrbdgt_cap }, 4290 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 4291 pci_conf_print_rclink_dcl_cap }, 4292 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 4293 NULL }, 4294 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 4295 pci_conf_print_rcec_assoc_cap }, 4296 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 4297 NULL }, 4298 { PCI_EXTCAP_VC2, "Virtual Channel", 4299 NULL }, 4300 { PCI_EXTCAP_RCRB, "RCRB Header", 4301 NULL }, 4302 { PCI_EXTCAP_VENDOR, "Vendor Unique", 4303 NULL }, 4304 { PCI_EXTCAP_CAC, "Configuration Access Correction", 4305 NULL }, 4306 { PCI_EXTCAP_ACS, "Access Control Services", 4307 pci_conf_print_acs_cap }, 4308 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 4309 pci_conf_print_ari_cap }, 4310 { PCI_EXTCAP_ATS, "Address Translation Services", 4311 pci_conf_print_ats_cap }, 4312 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 4313 pci_conf_print_sriov_cap }, 4314 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 4315 NULL }, 4316 { PCI_EXTCAP_MCAST, "Multicast", 4317 pci_conf_print_multicast_cap }, 4318 { PCI_EXTCAP_PAGE_REQ, "Page Request", 4319 pci_conf_print_page_req_cap }, 4320 { PCI_EXTCAP_AMD, "Reserved for AMD", 4321 NULL }, 4322 { PCI_EXTCAP_RESIZBAR, "Resizable BAR", 4323 pci_conf_print_resizbar_cap }, 4324 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 4325 pci_conf_print_dpa_cap }, 4326 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 4327 pci_conf_print_tph_req_cap }, 4328 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 4329 pci_conf_print_ltr_cap }, 4330 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 4331 pci_conf_print_sec_pcie_cap }, 4332 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 4333 NULL }, 4334 { PCI_EXTCAP_PASID, "Process Address Space ID", 4335 pci_conf_print_pasid_cap }, 4336 { PCI_EXTCAP_LNR, "LN Requester", 4337 pci_conf_print_lnr_cap }, 4338 { PCI_EXTCAP_DPC, "Downstream Port Containment", 4339 pci_conf_print_dpc_cap }, 4340 { PCI_EXTCAP_L1PM, "L1 PM Substates", 4341 pci_conf_print_l1pm_cap }, 4342 { PCI_EXTCAP_PTM, "Precision Time Measurement", 4343 pci_conf_print_ptm_cap }, 4344 { PCI_EXTCAP_MPCIE, "M-PCIe", 4345 NULL }, 4346 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 4347 NULL }, 4348 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 4349 NULL }, 4350 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 4351 NULL }, 4352 { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", 4353 NULL }, 4354 { PCI_EXTCAP_DLF, "Data link Feature", pci_conf_print_dlf_cap }, 4355 { PCI_EXTCAP_PYSLAY_16GT, "Physical Layer 16.0 GT/s", NULL }, 4356 { PCI_EXTCAP_LMR, "Lane Margining at the Receiver", NULL }, 4357 { PCI_EXTCAP_HIERARCHYID, "Hierarchy ID", 4358 NULL }, 4359 { PCI_EXTCAP_NPEM, "Native PCIe Enclosure Management", 4360 NULL }, 4361 }; 4362 4363 static int 4364 pci_conf_find_extcap(const pcireg_t *regs, unsigned int capid, int *offsetp) 4365 { 4366 int off; 4367 pcireg_t rval; 4368 4369 for (off = PCI_EXTCAPLIST_BASE; 4370 off != 0; 4371 off = PCI_EXTCAPLIST_NEXT(rval)) { 4372 rval = regs[o2i(off)]; 4373 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 4374 if (offsetp != NULL) 4375 *offsetp = off; 4376 return 1; 4377 } 4378 } 4379 return 0; 4380 } 4381 4382 static void 4383 pci_conf_print_extcaplist( 4384 #ifdef _KERNEL 4385 pci_chipset_tag_t pc, pcitag_t tag, 4386 #endif 4387 const pcireg_t *regs) 4388 { 4389 int off; 4390 pcireg_t foundcap; 4391 pcireg_t rval; 4392 bool foundtable[__arraycount(pci_extcaptab)]; 4393 unsigned int i; 4394 4395 /* Check Extended capability structure */ 4396 off = PCI_EXTCAPLIST_BASE; 4397 rval = regs[o2i(off)]; 4398 if (rval == 0xffffffff || rval == 0) 4399 return; 4400 4401 /* Clear table */ 4402 for (i = 0; i < __arraycount(pci_extcaptab); i++) 4403 foundtable[i] = false; 4404 4405 /* Print extended capability register's offset and the type first */ 4406 for (;;) { 4407 printf(" Extended Capability Register at 0x%02x\n", off); 4408 4409 foundcap = PCI_EXTCAPLIST_CAP(rval); 4410 printf(" type: 0x%04x (", foundcap); 4411 if (foundcap < __arraycount(pci_extcaptab)) { 4412 printf("%s)\n", pci_extcaptab[foundcap].name); 4413 /* Mark as found */ 4414 foundtable[foundcap] = true; 4415 } else 4416 printf("unknown)\n"); 4417 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 4418 4419 off = PCI_EXTCAPLIST_NEXT(rval); 4420 if (off == 0) 4421 break; 4422 else if (off <= PCI_CONF_SIZE) { 4423 printf(" next pointer: 0x%03x (incorrect)\n", off); 4424 return; 4425 } 4426 rval = regs[o2i(off)]; 4427 } 4428 4429 /* 4430 * And then, print the detail of each capability registers 4431 * in capability value's order. 4432 */ 4433 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 4434 if (foundtable[i] == false) 4435 continue; 4436 4437 /* 4438 * The type was found. Search capability list again and 4439 * print all capabilities that the capability type is 4440 * the same. 4441 */ 4442 if (pci_conf_find_extcap(regs, i, &off) == 0) 4443 continue; 4444 rval = regs[o2i(off)]; 4445 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 4446 || (pci_extcaptab[i].printfunc == NULL)) 4447 continue; 4448 4449 pci_extcaptab[i].printfunc(regs, off); 4450 4451 } 4452 } 4453 4454 /* Print the Secondary Status Register. */ 4455 static void 4456 pci_conf_print_ssr(pcireg_t rval) 4457 { 4458 pcireg_t devsel; 4459 4460 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 4461 onoff("66 MHz capable", rval, __BIT(5)); 4462 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 4463 onoff("Fast back-to-back capable", rval, __BIT(7)); 4464 onoff("Data parity error detected", rval, __BIT(8)); 4465 4466 printf(" DEVSEL timing: "); 4467 devsel = PCIREG_SHIFTOUT(rval, __BITS(10, 9)); 4468 switch (devsel) { 4469 case 0: 4470 printf("fast"); 4471 break; 4472 case 1: 4473 printf("medium"); 4474 break; 4475 case 2: 4476 printf("slow"); 4477 break; 4478 default: 4479 printf("unknown/reserved"); /* XXX */ 4480 break; 4481 } 4482 printf(" (0x%x)\n", devsel); 4483 4484 onoff("Signalled target abort", rval, __BIT(11)); 4485 onoff("Received target abort", rval, __BIT(12)); 4486 onoff("Received master abort", rval, __BIT(13)); 4487 onoff("Received system error", rval, __BIT(14)); 4488 onoff("Detected parity error", rval, __BIT(15)); 4489 } 4490 4491 static void 4492 pci_conf_print_type0( 4493 #ifdef _KERNEL 4494 pci_chipset_tag_t pc, pcitag_t tag, 4495 #endif 4496 const pcireg_t *regs) 4497 { 4498 int off, width; 4499 pcireg_t rval; 4500 const char *str; 4501 4502 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 4503 #ifdef _KERNEL 4504 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4505 #else 4506 width = pci_conf_print_bar(regs, off, NULL); 4507 #endif 4508 } 4509 4510 printf(" Cardbus CIS Pointer: 0x%08x\n", 4511 regs[o2i(PCI_CARDBUS_CIS_REG)]); 4512 4513 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 4514 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4515 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4516 4517 rval = regs[o2i(PCI_MAPREG_ROM)]; 4518 printf(" Expansion ROM Base Address Register: 0x%08x\n", rval); 4519 printf(" base: 0x%08x\n", (uint32_t)PCI_MAPREG_ROM_ADDR(rval)); 4520 onoff("Expansion ROM Enable", rval, PCI_MAPREG_ROM_ENABLE); 4521 printf(" Validation Status: "); 4522 switch (PCIREG_SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_STAT)) { 4523 case PCI_MAPREG_ROM_VSTAT_NOTSUPP: 4524 str = "Validation not supported"; 4525 break; 4526 case PCI_MAPREG_ROM_VSTAT_INPROG: 4527 str = "Validation in Progress"; 4528 break; 4529 case PCI_MAPREG_ROM_VSTAT_VPASS: 4530 str = "Validation Pass. " 4531 "Valid contents, trust test was not performed"; 4532 break; 4533 case PCI_MAPREG_ROM_VSTAT_VPASSTRUST: 4534 str = "Validation Pass. Valid and trusted contents"; 4535 break; 4536 case PCI_MAPREG_ROM_VSTAT_VFAIL: 4537 str = "Validation Fail. Invalid contents"; 4538 break; 4539 case PCI_MAPREG_ROM_VSTAT_VFAILUNTRUST: 4540 str = "Validation Fail. Valid but untrusted contents"; 4541 break; 4542 case PCI_MAPREG_ROM_VSTAT_WPASS: 4543 str = "Warning Pass. Validation passed with warning. " 4544 "Valid contents, trust test was not performed"; 4545 break; 4546 case PCI_MAPREG_ROM_VSTAT_WPASSTRUST: 4547 str = "Warning Pass. Validation passed with warning. " 4548 "Valid and trusted contents"; 4549 break; 4550 } 4551 printf("%s\n", str); 4552 printf(" Validation Details: 0x%x\n", 4553 PCIREG_SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_DETAIL)); 4554 4555 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4556 printf(" Capability list pointer: 0x%02x\n", 4557 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4558 else 4559 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4560 4561 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 4562 4563 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4564 printf(" Maximum Latency: 0x%02x\n", PCI_MAX_LAT(rval)); 4565 printf(" Minimum Grant: 0x%02x\n", PCI_MIN_GNT(rval)); 4566 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 4567 switch (PCI_INTERRUPT_PIN(rval)) { 4568 case PCI_INTERRUPT_PIN_NONE: 4569 printf("(none)"); 4570 break; 4571 case PCI_INTERRUPT_PIN_A: 4572 printf("(pin A)"); 4573 break; 4574 case PCI_INTERRUPT_PIN_B: 4575 printf("(pin B)"); 4576 break; 4577 case PCI_INTERRUPT_PIN_C: 4578 printf("(pin C)"); 4579 break; 4580 case PCI_INTERRUPT_PIN_D: 4581 printf("(pin D)"); 4582 break; 4583 default: 4584 printf("(? ? ?)"); 4585 break; 4586 } 4587 printf("\n"); 4588 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 4589 } 4590 4591 static void 4592 pci_conf_print_type1( 4593 #ifdef _KERNEL 4594 pci_chipset_tag_t pc, pcitag_t tag, 4595 #endif 4596 const pcireg_t *regs) 4597 { 4598 int off, width; 4599 pcireg_t rval, csreg; 4600 uint32_t base, limit; 4601 uint32_t base_h, limit_h; 4602 uint64_t pbase, plimit; 4603 int use_upper; 4604 4605 /* 4606 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 4607 * Bridge chip documentation, and may not be correct with 4608 * respect to various standards. (XXX) 4609 */ 4610 4611 for (off = 0x10; off < 0x18; off += width) { 4612 #ifdef _KERNEL 4613 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4614 #else 4615 width = pci_conf_print_bar(regs, off, NULL); 4616 #endif 4617 } 4618 4619 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4620 printf(" Primary bus number: 0x%02x\n", 4621 PCI_BRIDGE_BUS_NUM_PRIMARY(rval)); 4622 printf(" Secondary bus number: 0x%02x\n", 4623 PCI_BRIDGE_BUS_NUM_SECONDARY(rval)); 4624 printf(" Subordinate bus number: 0x%02x\n", 4625 PCI_BRIDGE_BUS_NUM_SUBORDINATE(rval)); 4626 printf(" Secondary bus latency timer: 0x%02x\n", 4627 PCI_BRIDGE_BUS_SEC_LATTIMER_VAL(rval)); 4628 4629 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 4630 pci_conf_print_ssr(PCIREG_SHIFTOUT(rval, __BITS(31, 16))); 4631 4632 /* I/O region */ 4633 printf(" I/O region:\n"); 4634 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 4635 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 4636 if (PCI_BRIDGE_IO_32BITS(rval)) 4637 use_upper = 1; 4638 else 4639 use_upper = 0; 4640 onoff("32bit I/O", rval, use_upper); 4641 base = PCI_BRIDGE_STATIO_IOBASE_ADDR(rval); 4642 limit = PCI_BRIDGE_STATIO_IOLIMIT_ADDR(rval); 4643 4644 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 4645 base_h = PCIREG_SHIFTOUT(rval, PCI_BRIDGE_IOHIGH_BASE); 4646 limit_h = PCIREG_SHIFTOUT(rval, PCI_BRIDGE_IOHIGH_LIMIT); 4647 printf(" base upper 16 bits register: 0x%04x\n", base_h); 4648 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 4649 4650 if (use_upper == 1) { 4651 base |= base_h << 16; 4652 limit |= limit_h << 16; 4653 } 4654 if (base < limit) { 4655 if (use_upper == 1) 4656 printf(" range: 0x%08x-0x%08x\n", base, limit); 4657 else 4658 printf(" range: 0x%04x-0x%04x\n", base, limit); 4659 } else 4660 printf(" range: not set\n"); 4661 4662 /* Non-prefetchable memory region */ 4663 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 4664 printf(" Memory region:\n"); 4665 printf(" base register: 0x%04hx\n", 4666 (uint16_t)PCIREG_SHIFTOUT(rval, PCI_BRIDGE_MEMORY_BASE)); 4667 printf(" limit register: 0x%04hx\n", 4668 (uint16_t)PCIREG_SHIFTOUT(rval, PCI_BRIDGE_MEMORY_LIMIT)); 4669 base = PCI_BRIDGE_MEMORY_BASE_ADDR(rval); 4670 limit = PCI_BRIDGE_MEMORY_LIMIT_ADDR(rval); 4671 if (base < limit) 4672 printf(" range: 0x%08x-0x%08x\n", base, limit); 4673 else 4674 printf(" range: not set\n"); 4675 4676 /* Prefetchable memory region */ 4677 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 4678 printf(" Prefetchable memory region:\n"); 4679 printf(" base register: 0x%04x\n", 4680 (rval >> 0) & 0xffff); 4681 printf(" limit register: 0x%04x\n", 4682 (rval >> 16) & 0xffff); 4683 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASEUP32_REG)]; 4684 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMITUP32_REG)]; 4685 printf(" base upper 32 bits register: 0x%08x\n", 4686 base_h); 4687 printf(" limit upper 32 bits register: 0x%08x\n", 4688 limit_h); 4689 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 4690 use_upper = 1; 4691 else 4692 use_upper = 0; 4693 onoff("64bit memory address", rval, use_upper); 4694 pbase = PCI_BRIDGE_PREFETCHMEM_BASE_ADDR(rval); 4695 plimit = PCI_BRIDGE_PREFETCHMEM_LIMIT_ADDR(rval); 4696 if (use_upper == 1) { 4697 pbase |= (uint64_t)base_h << 32; 4698 plimit |= (uint64_t)limit_h << 32; 4699 } 4700 if (pbase < plimit) { 4701 if (use_upper == 1) 4702 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 4703 "\n", pbase, plimit); 4704 else 4705 printf(" range: 0x%08x-0x%08x\n", 4706 (uint32_t)pbase, (uint32_t)plimit); 4707 } else 4708 printf(" range: not set\n"); 4709 4710 csreg = regs[o2i(PCI_COMMAND_STATUS_REG)]; 4711 if (csreg & PCI_STATUS_CAPLIST_SUPPORT) 4712 printf(" Capability list pointer: 0x%02x\n", 4713 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4714 else 4715 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4716 4717 printf(" Expansion ROM Base Address: 0x%08x\n", 4718 regs[o2i(PCI_BRIDGE_EXPROMADDR_REG)]); 4719 4720 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4721 printf(" Interrupt line: 0x%02x\n", 4722 (rval >> 0) & 0xff); 4723 printf(" Interrupt pin: 0x%02x ", 4724 (rval >> 8) & 0xff); 4725 switch ((rval >> 8) & 0xff) { 4726 case PCI_INTERRUPT_PIN_NONE: 4727 printf("(none)"); 4728 break; 4729 case PCI_INTERRUPT_PIN_A: 4730 printf("(pin A)"); 4731 break; 4732 case PCI_INTERRUPT_PIN_B: 4733 printf("(pin B)"); 4734 break; 4735 case PCI_INTERRUPT_PIN_C: 4736 printf("(pin C)"); 4737 break; 4738 case PCI_INTERRUPT_PIN_D: 4739 printf("(pin D)"); 4740 break; 4741 default: 4742 printf("(? ? ?)"); 4743 break; 4744 } 4745 printf("\n"); 4746 rval = regs[o2i(PCI_BRIDGE_CONTROL_REG)]; 4747 printf(" Bridge control register: 0x%04hx\n", 4748 (uint16_t)PCIREG_SHIFTOUT(rval, PCI_BRIDGE_CONTROL)); 4749 onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE); 4750 onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR); 4751 onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA); 4752 onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA); 4753 /* 4754 * VGA 16bit decode bit has meaning if the VGA enable bit or the 4755 * VGA Palette Snoop Enable bit is set. 4756 */ 4757 if (((rval & PCI_BRIDGE_CONTROL_VGA) != 0) 4758 || ((csreg & PCI_COMMAND_PALETTE_ENABLE) != 0)) 4759 onoff("VGA 16bit enable", rval, PCI_BRIDGE_CONTROL_VGA16); 4760 onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT); 4761 onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR); 4762 onoff("Fast back-to-back enable", rval, PCI_BRIDGE_CONTROL_SECFASTB2B); 4763 onoff("Primary Discard Timer", rval, 4764 PCI_BRIDGE_CONTROL_PRI_DISC_TIMER); 4765 onoff("Secondary Discard Timer", 4766 rval, PCI_BRIDGE_CONTROL_SEC_DISC_TIMER); 4767 onoff("Discard Timer Status", rval, 4768 PCI_BRIDGE_CONTROL_DISC_TIMER_STAT); 4769 onoff("Discard Timer SERR# Enable", rval, 4770 PCI_BRIDGE_CONTROL_DISC_TIMER_SERR); 4771 } 4772 4773 static void 4774 pci_conf_print_type2( 4775 #ifdef _KERNEL 4776 pci_chipset_tag_t pc, pcitag_t tag, 4777 #endif 4778 const pcireg_t *regs) 4779 { 4780 pcireg_t rval; 4781 4782 /* 4783 * XXX these need to be printed in more detail, need to be 4784 * XXX checked against specs/docs, etc. 4785 * 4786 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 4787 * controller chip documentation, and may not be correct with 4788 * respect to various standards. (XXX) 4789 */ 4790 4791 #ifdef _KERNEL 4792 pci_conf_print_bar(pc, tag, regs, 0x10, 4793 "CardBus socket/ExCA registers"); 4794 #else 4795 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 4796 #endif 4797 4798 /* Capability list pointer and secondary status register */ 4799 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 4800 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4801 printf(" Capability list pointer: 0x%02x\n", 4802 PCI_CAPLIST_PTR(rval)); 4803 else 4804 printf(" Reserved @ 0x14: 0x%04x\n", 4805 PCIREG_SHIFTOUT(rval, __BITS(15, 0))); 4806 pci_conf_print_ssr(PCIREG_SHIFTOUT(rval, __BITS(31, 16))); 4807 4808 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4809 printf(" PCI bus number: 0x%02x\n", 4810 (rval >> 0) & 0xff); 4811 printf(" CardBus bus number: 0x%02x\n", 4812 (rval >> 8) & 0xff); 4813 printf(" Subordinate bus number: 0x%02x\n", 4814 (rval >> 16) & 0xff); 4815 printf(" CardBus latency timer: 0x%02x\n", 4816 (rval >> 24) & 0xff); 4817 4818 /* XXX Print more prettily */ 4819 printf(" CardBus memory region 0:\n"); 4820 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 4821 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 4822 printf(" CardBus memory region 1:\n"); 4823 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 4824 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 4825 printf(" CardBus I/O region 0:\n"); 4826 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 4827 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 4828 printf(" CardBus I/O region 1:\n"); 4829 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 4830 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 4831 4832 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4833 printf(" Interrupt line: 0x%02x\n", 4834 (rval >> 0) & 0xff); 4835 printf(" Interrupt pin: 0x%02x ", 4836 (rval >> 8) & 0xff); 4837 switch ((rval >> 8) & 0xff) { 4838 case PCI_INTERRUPT_PIN_NONE: 4839 printf("(none)"); 4840 break; 4841 case PCI_INTERRUPT_PIN_A: 4842 printf("(pin A)"); 4843 break; 4844 case PCI_INTERRUPT_PIN_B: 4845 printf("(pin B)"); 4846 break; 4847 case PCI_INTERRUPT_PIN_C: 4848 printf("(pin C)"); 4849 break; 4850 case PCI_INTERRUPT_PIN_D: 4851 printf("(pin D)"); 4852 break; 4853 default: 4854 printf("(? ? ?)"); 4855 break; 4856 } 4857 printf("\n"); 4858 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> 16) & 0xffff; 4859 printf(" Bridge control register: 0x%04x\n", rval); 4860 onoff("Parity error response", rval, __BIT(0)); 4861 onoff("SERR# enable", rval, __BIT(1)); 4862 onoff("ISA enable", rval, __BIT(2)); 4863 onoff("VGA enable", rval, __BIT(3)); 4864 onoff("Master abort mode", rval, __BIT(5)); 4865 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 4866 onoff("Functional interrupts routed by ExCA registers", rval, 4867 __BIT(7)); 4868 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 4869 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 4870 onoff("Write posting enable", rval, __BIT(10)); 4871 4872 rval = regs[o2i(0x40)]; 4873 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4874 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4875 4876 #ifdef _KERNEL 4877 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers"); 4878 #else 4879 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 4880 #endif 4881 } 4882 4883 void 4884 pci_conf_print( 4885 #ifdef _KERNEL 4886 pci_chipset_tag_t pc, pcitag_t tag, 4887 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 4888 #else 4889 int pcifd, u_int bus, u_int dev, u_int func 4890 #endif 4891 ) 4892 { 4893 pcireg_t *regs; 4894 int off, capoff, endoff, hdrtype; 4895 const char *type_name; 4896 #ifdef _KERNEL 4897 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 4898 #else 4899 void (*type_printfn)(const pcireg_t *); 4900 #endif 4901 4902 regs = MALLOC(PCI_EXTCONF_SIZE); 4903 4904 printf("PCI configuration registers:\n"); 4905 4906 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 4907 #ifdef _KERNEL 4908 regs[o2i(off)] = pci_conf_read(pc, tag, off); 4909 #else 4910 if (pcibus_conf_read(pcifd, bus, dev, func, off, 4911 ®s[o2i(off)]) == -1) 4912 regs[o2i(off)] = 0; 4913 #endif 4914 } 4915 4916 /* common header */ 4917 printf(" Common header:\n"); 4918 pci_conf_print_regs(regs, 0, 16); 4919 4920 printf("\n"); 4921 #ifdef _KERNEL 4922 pci_conf_print_common(pc, tag, regs); 4923 #else 4924 pci_conf_print_common(regs); 4925 #endif 4926 printf("\n"); 4927 4928 /* type-dependent header */ 4929 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 4930 switch (hdrtype) { /* XXX make a table, eventually */ 4931 case 0: 4932 /* Standard device header */ 4933 type_name = "\"normal\" device"; 4934 type_printfn = &pci_conf_print_type0; 4935 capoff = PCI_CAPLISTPTR_REG; 4936 endoff = 64; 4937 break; 4938 case 1: 4939 /* PCI-PCI bridge header */ 4940 type_name = "PCI-PCI bridge"; 4941 type_printfn = &pci_conf_print_type1; 4942 capoff = PCI_CAPLISTPTR_REG; 4943 endoff = 64; 4944 break; 4945 case 2: 4946 /* PCI-CardBus bridge header */ 4947 type_name = "PCI-CardBus bridge"; 4948 type_printfn = &pci_conf_print_type2; 4949 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 4950 endoff = 72; 4951 break; 4952 default: 4953 type_name = NULL; 4954 type_printfn = 0; 4955 capoff = -1; 4956 endoff = 64; 4957 break; 4958 } 4959 printf(" Type %d ", hdrtype); 4960 if (type_name != NULL) 4961 printf("(%s) ", type_name); 4962 printf("header:\n"); 4963 pci_conf_print_regs(regs, 16, endoff); 4964 printf("\n"); 4965 if (type_printfn) { 4966 #ifdef _KERNEL 4967 (*type_printfn)(pc, tag, regs); 4968 #else 4969 (*type_printfn)(regs); 4970 #endif 4971 } else 4972 printf(" Don't know how to pretty-print type %d header.\n", 4973 hdrtype); 4974 printf("\n"); 4975 4976 /* capability list, if present */ 4977 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4978 && (capoff > 0)) { 4979 #ifdef _KERNEL 4980 pci_conf_print_caplist(pc, tag, regs, capoff); 4981 #else 4982 pci_conf_print_caplist(regs, capoff); 4983 #endif 4984 printf("\n"); 4985 } 4986 4987 /* device-dependent header */ 4988 printf(" Device-dependent header:\n"); 4989 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 4990 #ifdef _KERNEL 4991 printf("\n"); 4992 if (printfn) 4993 (*printfn)(pc, tag, regs); 4994 else 4995 printf(" Don't know how to pretty-print device-dependent header.\n"); 4996 #endif /* _KERNEL */ 4997 4998 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 4999 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 5000 goto out; 5001 5002 printf("\n"); 5003 #ifdef _KERNEL 5004 pci_conf_print_extcaplist(pc, tag, regs); 5005 #else 5006 pci_conf_print_extcaplist(regs); 5007 #endif 5008 printf("\n"); 5009 5010 /* Extended Configuration Space, if present */ 5011 printf(" Extended Configuration Space:\n"); 5012 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 5013 5014 out: 5015 FREE(regs, PCI_EXTCONF_SIZE); 5016 } 5017
Indexes created Thu Sep 25 02:09:54 GMT 2025