pci_subr.c revision 1.240
1 /* $NetBSD: pci_subr.c,v 1.240 2022/01/31 10:11:33 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.240 2022/01/31 10:11:33 msaitoh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #include <sys/kmem.h> 56 57 #define MALLOC(sz) kmem_alloc(sz, KM_SLEEP) 58 #define FREE(p, sz) kmem_free(p, sz) 59 60 #else 61 #include <pci.h> 62 #include <stdarg.h> 63 #include <stdbool.h> 64 #include <stdio.h> 65 #include <stdlib.h> 66 #include <string.h> 67 68 #define MALLOC(sz) malloc(sz) 69 #define FREE(p, sz) free(p) 70 71 #endif 72 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcidevs.h> 75 #ifdef _KERNEL 76 #include <dev/pci/pcivar.h> 77 #else 78 #include <dev/pci/pci_verbose.h> 79 #include <dev/pci/pcidevs_data.h> 80 #endif 81 82 static int pci_conf_find_cap(const pcireg_t *, unsigned int, int *); 83 static int pci_conf_find_extcap(const pcireg_t *, unsigned int, int *); 84 static void pci_conf_print_pcie_power(uint8_t, unsigned int); 85 #define PCIREG_SHIFTOUT(a, b) ((pcireg_t)__SHIFTOUT((a), (b))) 86 87 #ifdef _KERNEL 88 /* 89 * Common routines used to match a compatible device by its PCI ID code. 90 */ 91 92 const struct device_compatible_entry * 93 pci_compatible_lookup_id(pcireg_t const id, 94 const struct device_compatible_entry *dce) 95 { 96 return device_compatible_lookup_id(id, PCI_COMPAT_EOL_VALUE, dce); 97 } 98 99 const struct device_compatible_entry * 100 pci_compatible_lookup(const struct pci_attach_args * const pa, 101 const struct device_compatible_entry * const dce) 102 { 103 return pci_compatible_lookup_id(pa->pa_id, dce); 104 } 105 106 const struct device_compatible_entry * 107 pci_compatible_lookup_subsys(const struct pci_attach_args * const pa, 108 const struct device_compatible_entry * const dce) 109 { 110 const pcireg_t subsysid = 111 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 112 113 return pci_compatible_lookup_id(subsysid, dce); 114 } 115 116 int 117 pci_compatible_match(const struct pci_attach_args * const pa, 118 const struct device_compatible_entry * const dce) 119 { 120 return pci_compatible_lookup(pa, dce) != NULL; 121 } 122 123 int 124 pci_compatible_match_subsys(const struct pci_attach_args * const pa, 125 const struct device_compatible_entry * const dce) 126 { 127 return pci_compatible_lookup_subsys(pa, dce) != NULL; 128 } 129 #endif /* _KERNEL */ 130 131 /* 132 * Descriptions of known PCI classes and subclasses. 133 * 134 * Subclasses are described in the same way as classes, but have a 135 * NULL subclass pointer. 136 */ 137 struct pci_class { 138 const char *name; 139 u_int val; /* as wide as pci_{,sub}class_t */ 140 const struct pci_class *subclasses; 141 }; 142 143 /* 144 * Class 0x00. 145 * Before rev. 2.0. 146 */ 147 static const struct pci_class pci_subclass_prehistoric[] = { 148 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 149 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 150 { NULL, 0, NULL, }, 151 }; 152 153 /* 154 * Class 0x01. 155 * Mass storage controller 156 */ 157 158 /* ATA programming interface */ 159 static const struct pci_class pci_interface_ata[] = { 160 { "with single DMA", PCI_INTERFACE_ATA_SINGLEDMA, NULL, }, 161 { "with chained DMA", PCI_INTERFACE_ATA_CHAINEDDMA, NULL, }, 162 { NULL, 0, NULL, }, 163 }; 164 165 /* SATA programming interface */ 166 static const struct pci_class pci_interface_sata[] = { 167 { "vendor specific", PCI_INTERFACE_SATA_VND, NULL, }, 168 { "AHCI 1.0", PCI_INTERFACE_SATA_AHCI10, NULL, }, 169 { "Serial Storage Bus Interface", PCI_INTERFACE_SATA_SSBI, NULL, }, 170 { NULL, 0, NULL, }, 171 }; 172 173 /* Flash programming interface */ 174 static const struct pci_class pci_interface_nvm[] = { 175 { "vendor specific", PCI_INTERFACE_NVM_VND, NULL, }, 176 { "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, }, 177 { "NVMe I/O", PCI_INTERFACE_NVM_NVME_IO, NULL, }, 178 { "NVMe admin", PCI_INTERFACE_NVM_NVME_ADMIN, NULL, }, 179 { NULL, 0, NULL, }, 180 }; 181 182 /* UFS programming interface */ 183 static const struct pci_class pci_interface_ufs[] = { 184 { "vendor specific", PCI_INTERFACE_UFS_VND, NULL, }, 185 { "UFSHCI", PCI_INTERFACE_UFS_UFSHCI, NULL, }, 186 { NULL, 0, NULL, }, 187 }; 188 189 /* Subclasses */ 190 static const struct pci_class pci_subclass_mass_storage[] = { 191 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 192 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 193 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 194 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 195 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 196 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, 197 pci_interface_ata, }, 198 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, 199 pci_interface_sata, }, 200 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 201 { "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM, 202 pci_interface_nvm, }, 203 { "UFS", PCI_SUBCLASS_MASS_STORAGE_UFS, 204 pci_interface_ufs, }, 205 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 206 { NULL, 0, NULL, }, 207 }; 208 209 /* 210 * Class 0x02. 211 * Network controller. 212 */ 213 static const struct pci_class pci_subclass_network[] = { 214 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 215 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 216 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 217 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 218 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 219 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 220 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 221 { "InfiniBand", PCI_SUBCLASS_NETWORK_INFINIBAND, NULL, }, 222 { "Host fabric", PCI_SUBCLASS_NETWORK_HFC, NULL, }, 223 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 224 { NULL, 0, NULL, }, 225 }; 226 227 /* 228 * Class 0x03. 229 * Display controller. 230 */ 231 232 /* VGA programming interface */ 233 static const struct pci_class pci_interface_vga[] = { 234 { "", PCI_INTERFACE_VGA_VGA, NULL, }, 235 { "8514-compat", PCI_INTERFACE_VGA_8514, NULL, }, 236 { NULL, 0, NULL, }, 237 }; 238 /* Subclasses */ 239 static const struct pci_class pci_subclass_display[] = { 240 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, pci_interface_vga,}, 241 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 242 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 243 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 244 { NULL, 0, NULL, }, 245 }; 246 247 /* 248 * Class 0x04. 249 * Multimedia device. 250 */ 251 252 /* HD Audio programming interface */ 253 static const struct pci_class pci_interface_hda[] = { 254 { "HD Audio 1.0", PCI_INTERFACE_HDAUDIO, NULL, }, 255 { "HD Audio 1.0 + vendor ext", PCI_INTERFACE_HDAUDIO_VND, NULL, }, 256 { NULL, 0, NULL, }, 257 }; 258 259 static const struct pci_class pci_subclass_multimedia[] = { 260 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 261 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 262 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 263 { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, 264 pci_interface_hda, }, 265 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 266 { NULL, 0, NULL, }, 267 }; 268 269 /* 270 * Class 0x05. 271 * Memory controller. 272 */ 273 static const struct pci_class pci_subclass_memory[] = { 274 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 275 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 276 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 277 { NULL, 0, NULL, }, 278 }; 279 280 /* 281 * Class 0x06. 282 * Bridge device. 283 */ 284 285 /* PCI bridge programming interface */ 286 static const struct pci_class pci_interface_pcibridge[] = { 287 { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, }, 288 { "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, }, 289 { NULL, 0, NULL, }, 290 }; 291 292 /* Semi-transparent PCI-to-PCI bridge programming interface */ 293 static const struct pci_class pci_interface_stpci[] = { 294 { "primary side facing host", PCI_INTERFACE_STPCI_PRIMARY, NULL, }, 295 { "secondary side facing host", PCI_INTERFACE_STPCI_SECONDARY, NULL, }, 296 { NULL, 0, NULL, }, 297 }; 298 299 /* Advanced Switching programming interface */ 300 static const struct pci_class pci_interface_advsw[] = { 301 { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, }, 302 { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, }, 303 { NULL, 0, NULL, }, 304 }; 305 306 /* Subclasses */ 307 static const struct pci_class pci_subclass_bridge[] = { 308 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 309 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 310 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 311 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 312 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, 313 pci_interface_pcibridge, }, 314 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 315 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 316 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 317 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 318 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, 319 pci_interface_stpci, }, 320 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 321 { "advanced switching", PCI_SUBCLASS_BRIDGE_ADVSW, 322 pci_interface_advsw, }, 323 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 324 { NULL, 0, NULL, }, 325 }; 326 327 /* 328 * Class 0x07. 329 * Simple communications controller. 330 */ 331 332 /* Serial controller programming interface */ 333 static const struct pci_class pci_interface_serial[] = { 334 { "generic XT-compat", PCI_INTERFACE_SERIAL_XT, NULL, }, 335 { "16450-compat", PCI_INTERFACE_SERIAL_16450, NULL, }, 336 { "16550-compat", PCI_INTERFACE_SERIAL_16550, NULL, }, 337 { "16650-compat", PCI_INTERFACE_SERIAL_16650, NULL, }, 338 { "16750-compat", PCI_INTERFACE_SERIAL_16750, NULL, }, 339 { "16850-compat", PCI_INTERFACE_SERIAL_16850, NULL, }, 340 { "16950-compat", PCI_INTERFACE_SERIAL_16950, NULL, }, 341 { NULL, 0, NULL, }, 342 }; 343 344 /* Parallel controller programming interface */ 345 static const struct pci_class pci_interface_parallel[] = { 346 { "", PCI_INTERFACE_PARALLEL, NULL,}, 347 { "bi-directional", PCI_INTERFACE_PARALLEL_BIDIRECTIONAL, NULL,}, 348 { "ECP 1.X-compat", PCI_INTERFACE_PARALLEL_ECP1X, NULL,}, 349 { "IEEE1284 controller", PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL, NULL,}, 350 { "IEEE1284 target", PCI_INTERFACE_PARALLEL_IEEE1284_TGT, NULL,}, 351 { NULL, 0, NULL,}, 352 }; 353 354 /* Modem programming interface */ 355 static const struct pci_class pci_interface_modem[] = { 356 { "", PCI_INTERFACE_MODEM, NULL,}, 357 { "Hayes&16450-compat", PCI_INTERFACE_MODEM_HAYES16450, NULL,}, 358 { "Hayes&16550-compat", PCI_INTERFACE_MODEM_HAYES16550, NULL,}, 359 { "Hayes&16650-compat", PCI_INTERFACE_MODEM_HAYES16650, NULL,}, 360 { "Hayes&16750-compat", PCI_INTERFACE_MODEM_HAYES16750, NULL,}, 361 { NULL, 0, NULL,}, 362 }; 363 364 /* Subclasses */ 365 static const struct pci_class pci_subclass_communications[] = { 366 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, 367 pci_interface_serial, }, 368 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, 369 pci_interface_parallel, }, 370 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL,}, 371 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, 372 pci_interface_modem, }, 373 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL,}, 374 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL,}, 375 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL,}, 376 { NULL, 0, NULL,}, 377 }; 378 379 /* 380 * Class 0x08. 381 * Base system peripheral. 382 */ 383 384 /* PIC programming interface */ 385 static const struct pci_class pci_interface_pic[] = { 386 { "generic 8259", PCI_INTERFACE_PIC_8259, NULL, }, 387 { "ISA PIC", PCI_INTERFACE_PIC_ISA, NULL, }, 388 { "EISA PIC", PCI_INTERFACE_PIC_EISA, NULL, }, 389 { "IO APIC", PCI_INTERFACE_PIC_IOAPIC, NULL, }, 390 { "IO(x) APIC", PCI_INTERFACE_PIC_IOXAPIC, NULL, }, 391 { NULL, 0, NULL, }, 392 }; 393 394 /* DMA programming interface */ 395 static const struct pci_class pci_interface_dma[] = { 396 { "generic 8237", PCI_INTERFACE_DMA_8237, NULL, }, 397 { "ISA", PCI_INTERFACE_DMA_ISA, NULL, }, 398 { "EISA", PCI_INTERFACE_DMA_EISA, NULL, }, 399 { NULL, 0, NULL, }, 400 }; 401 402 /* Timer programming interface */ 403 static const struct pci_class pci_interface_tmr[] = { 404 { "generic 8254", PCI_INTERFACE_TIMER_8254, NULL, }, 405 { "ISA", PCI_INTERFACE_TIMER_ISA, NULL, }, 406 { "EISA", PCI_INTERFACE_TIMER_EISA, NULL, }, 407 { "HPET", PCI_INTERFACE_TIMER_HPET, NULL, }, 408 { NULL, 0, NULL, }, 409 }; 410 411 /* RTC programming interface */ 412 static const struct pci_class pci_interface_rtc[] = { 413 { "generic", PCI_INTERFACE_RTC_GENERIC, NULL, }, 414 { "ISA", PCI_INTERFACE_RTC_ISA, NULL, }, 415 { NULL, 0, NULL, }, 416 }; 417 418 /* Subclasses */ 419 static const struct pci_class pci_subclass_system[] = { 420 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, pci_interface_pic,}, 421 { "DMA", PCI_SUBCLASS_SYSTEM_DMA, pci_interface_dma,}, 422 { "timer", PCI_SUBCLASS_SYSTEM_TIMER, pci_interface_tmr,}, 423 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, pci_interface_rtc,}, 424 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 425 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 426 { "IOMMU", PCI_SUBCLASS_SYSTEM_IOMMU, NULL, }, 427 { "Root Complex Event Collector", PCI_SUBCLASS_SYSTEM_RCEC, NULL, }, 428 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 429 { NULL, 0, NULL, }, 430 }; 431 432 /* 433 * Class 0x09. 434 * Input device. 435 */ 436 437 /* Gameport programming interface */ 438 static const struct pci_class pci_interface_game[] = { 439 { "generic", PCI_INTERFACE_GAMEPORT_GENERIC, NULL, }, 440 { "legacy", PCI_INTERFACE_GAMEPORT_LEGACY, NULL, }, 441 { NULL, 0, NULL, }, 442 }; 443 444 /* Subclasses */ 445 static const struct pci_class pci_subclass_input[] = { 446 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 447 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 448 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 449 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 450 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, 451 pci_interface_game, }, 452 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 453 { NULL, 0, NULL, }, 454 }; 455 456 /* 457 * Class 0x0a. 458 * Docking station. 459 */ 460 static const struct pci_class pci_subclass_dock[] = { 461 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 462 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 463 { NULL, 0, NULL, }, 464 }; 465 466 /* 467 * Class 0x0b. 468 * Processor. 469 */ 470 static const struct pci_class pci_subclass_processor[] = { 471 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 472 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 473 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 474 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 475 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 476 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 477 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 478 { "miscellaneous", PCI_SUBCLASS_PROCESSOR_MISC, NULL, }, 479 { NULL, 0, NULL, }, 480 }; 481 482 /* 483 * Class 0x0c. 484 * Serial bus controller. 485 */ 486 487 /* IEEE1394 programming interface */ 488 static const struct pci_class pci_interface_ieee1394[] = { 489 { "Firewire", PCI_INTERFACE_IEEE1394_FIREWIRE, NULL,}, 490 { "OpenHCI", PCI_INTERFACE_IEEE1394_OPENHCI, NULL,}, 491 { NULL, 0, NULL,}, 492 }; 493 494 /* USB programming interface */ 495 static const struct pci_class pci_interface_usb[] = { 496 { "UHCI", PCI_INTERFACE_USB_UHCI, NULL, }, 497 { "OHCI", PCI_INTERFACE_USB_OHCI, NULL, }, 498 { "EHCI", PCI_INTERFACE_USB_EHCI, NULL, }, 499 { "xHCI", PCI_INTERFACE_USB_XHCI, NULL, }, 500 { "USB4 HCI", PCI_INTERFACE_USB_USB4HCI, NULL, }, 501 { "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, }, 502 { "device", PCI_INTERFACE_USB_DEVICE, NULL, }, 503 { NULL, 0, NULL, }, 504 }; 505 506 /* IPMI programming interface */ 507 static const struct pci_class pci_interface_ipmi[] = { 508 { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL, }, 509 { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL, }, 510 { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL, }, 511 { NULL, 0, NULL, }, 512 }; 513 514 /* Subclasses */ 515 static const struct pci_class pci_subclass_serialbus[] = { 516 { "IEEE1394", PCI_SUBCLASS_SERIALBUS_FIREWIRE, 517 pci_interface_ieee1394, }, 518 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 519 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 520 { "USB", PCI_SUBCLASS_SERIALBUS_USB, 521 pci_interface_usb, }, 522 /* XXX Fiber Channel/_FIBRECHANNEL */ 523 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 524 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 525 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 526 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, 527 pci_interface_ipmi, }, 528 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 529 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 530 { "MIPI I3C", PCI_SUBCLASS_SERIALBUS_MIPI_I3C, NULL, }, 531 { "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, }, 532 { NULL, 0, NULL, }, 533 }; 534 535 /* 536 * Class 0x0d. 537 * Wireless Controller. 538 */ 539 static const struct pci_class pci_subclass_wireless[] = { 540 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 541 { "Consumer IR",/*XXX*/ PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 542 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 543 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 544 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 545 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 546 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 547 { "Cellular", PCI_SUBCLASS_WIRELESS_CELL, NULL, }, 548 { "Cellular + Ethernet", PCI_SUBCLASS_WIRELESS_CELL_E, NULL, }, 549 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 550 { NULL, 0, NULL, }, 551 }; 552 553 /* 554 * Class 0x0e. 555 * Intelligent IO controller. 556 */ 557 558 /* Intelligent IO programming interface */ 559 static const struct pci_class pci_interface_i2o[] = { 560 { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL, }, 561 { NULL, 0, NULL, }, 562 }; 563 564 /* Subclasses */ 565 static const struct pci_class pci_subclass_i2o[] = { 566 { "standard", PCI_SUBCLASS_I2O_STANDARD, pci_interface_i2o,}, 567 { "miscellaneous", PCI_SUBCLASS_I2O_MISC, NULL, }, 568 { NULL, 0, NULL, }, 569 }; 570 571 /* 572 * Class 0x0f. 573 * Satellite communication controller. 574 */ 575 static const struct pci_class pci_subclass_satcom[] = { 576 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 577 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 578 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 579 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 580 { "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, }, 581 { NULL, 0, NULL, }, 582 }; 583 584 /* 585 * Class 0x10. 586 * Encryption/Decryption controller. 587 */ 588 static const struct pci_class pci_subclass_crypto[] = { 589 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 590 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 591 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 592 { NULL, 0, NULL, }, 593 }; 594 595 /* 596 * Class 0x11. 597 * Data aquuisition and signal processing controller. 598 */ 599 static const struct pci_class pci_subclass_dasp[] = { 600 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 601 { "performance counters", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 602 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 603 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 604 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 605 { NULL, 0, NULL, }, 606 }; 607 608 /* List of classes */ 609 static const struct pci_class pci_classes[] = { 610 { "prehistoric", PCI_CLASS_PREHISTORIC, 611 pci_subclass_prehistoric, }, 612 { "mass storage", PCI_CLASS_MASS_STORAGE, 613 pci_subclass_mass_storage, }, 614 { "network", PCI_CLASS_NETWORK, 615 pci_subclass_network, }, 616 { "display", PCI_CLASS_DISPLAY, 617 pci_subclass_display, }, 618 { "multimedia", PCI_CLASS_MULTIMEDIA, 619 pci_subclass_multimedia, }, 620 { "memory", PCI_CLASS_MEMORY, 621 pci_subclass_memory, }, 622 { "bridge", PCI_CLASS_BRIDGE, 623 pci_subclass_bridge, }, 624 { "communications", PCI_CLASS_COMMUNICATIONS, 625 pci_subclass_communications, }, 626 { "system", PCI_CLASS_SYSTEM, 627 pci_subclass_system, }, 628 { "input", PCI_CLASS_INPUT, 629 pci_subclass_input, }, 630 { "dock", PCI_CLASS_DOCK, 631 pci_subclass_dock, }, 632 { "processor", PCI_CLASS_PROCESSOR, 633 pci_subclass_processor, }, 634 { "serial bus", PCI_CLASS_SERIALBUS, 635 pci_subclass_serialbus, }, 636 { "wireless", PCI_CLASS_WIRELESS, 637 pci_subclass_wireless, }, 638 { "I2O", PCI_CLASS_I2O, 639 pci_subclass_i2o, }, 640 { "satellite comm", PCI_CLASS_SATCOM, 641 pci_subclass_satcom, }, 642 { "crypto", PCI_CLASS_CRYPTO, 643 pci_subclass_crypto, }, 644 { "DASP", PCI_CLASS_DASP, 645 pci_subclass_dasp, }, 646 { "processing accelerators", PCI_CLASS_ACCEL, 647 NULL, }, 648 { "non-essential instrumentation", PCI_CLASS_INSTRUMENT, 649 NULL, }, 650 { "undefined", PCI_CLASS_UNDEFINED, 651 NULL, }, 652 { NULL, 0, 653 NULL, }, 654 }; 655 656 DEV_VERBOSE_DEFINE(pci); 657 658 /* 659 * Append a formatted string to dest without writing more than len 660 * characters (including the trailing NUL character). dest and len 661 * are updated for use in subsequent calls to snappendf(). 662 * 663 * Returns 0 on success, a negative value if vnsprintf() fails, or 664 * a positive value if the dest buffer would have overflowed. 665 */ 666 667 static int __printflike(3, 4) 668 snappendf(char **dest, size_t *len, const char * restrict fmt, ...) 669 { 670 va_list ap; 671 int count; 672 673 va_start(ap, fmt); 674 count = vsnprintf(*dest, *len, fmt, ap); 675 va_end(ap); 676 677 /* Let vsnprintf() errors bubble up to caller */ 678 if (count < 0 || *len == 0) 679 return count; 680 681 /* Handle overflow */ 682 if ((size_t)count >= *len) { 683 *dest += *len - 1; 684 *len = 1; 685 return 1; 686 } 687 688 /* Update dest & len to point at trailing NUL */ 689 *dest += count; 690 *len -= count; 691 692 return 0; 693 } 694 695 void 696 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 697 size_t l) 698 { 699 pci_class_t class; 700 pci_subclass_t subclass; 701 pci_interface_t interface; 702 pci_revision_t revision; 703 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 704 const struct pci_class *classp, *subclassp, *interfacep; 705 706 class = PCI_CLASS(class_reg); 707 subclass = PCI_SUBCLASS(class_reg); 708 interface = PCI_INTERFACE(class_reg); 709 revision = PCI_REVISION(class_reg); 710 711 pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(id_reg)); 712 pci_findproduct(product, sizeof(product), PCI_VENDOR(id_reg), 713 PCI_PRODUCT(id_reg)); 714 715 classp = pci_classes; 716 while (classp->name != NULL) { 717 if (class == classp->val) 718 break; 719 classp++; 720 } 721 722 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 723 while (subclassp && subclassp->name != NULL) { 724 if (subclass == subclassp->val) 725 break; 726 subclassp++; 727 } 728 729 interfacep = (subclassp && subclassp->name != NULL) ? 730 subclassp->subclasses : NULL; 731 while (interfacep && interfacep->name != NULL) { 732 if (interface == interfacep->val) 733 break; 734 interfacep++; 735 } 736 737 (void)snappendf(&cp, &l, "%s %s", vendor, product); 738 if (showclass) { 739 (void)snappendf(&cp, &l, " ("); 740 if (classp->name == NULL) 741 (void)snappendf(&cp, &l, 742 "class 0x%02x, subclass 0x%02x", 743 class, subclass); 744 else { 745 if (subclassp == NULL || subclassp->name == NULL) 746 (void)snappendf(&cp, &l, 747 "%s, subclass 0x%02x", 748 classp->name, subclass); 749 else 750 (void)snappendf(&cp, &l, "%s %s", 751 subclassp->name, classp->name); 752 } 753 if ((interfacep == NULL) || (interfacep->name == NULL)) { 754 if (interface != 0) 755 (void)snappendf(&cp, &l, ", interface 0x%02x", 756 interface); 757 } else if (strncmp(interfacep->name, "", 1) != 0) 758 (void)snappendf(&cp, &l, ", %s", interfacep->name); 759 if (revision != 0) 760 (void)snappendf(&cp, &l, ", revision 0x%02x", revision); 761 (void)snappendf(&cp, &l, ")"); 762 } 763 } 764 765 #ifdef _KERNEL 766 void 767 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 768 const char *known, int addrev) 769 { 770 char devinfo[256]; 771 772 if (known) { 773 aprint_normal(": %s", known); 774 if (addrev) 775 aprint_normal(" (rev. 0x%02x)", 776 PCI_REVISION(pa->pa_class)); 777 aprint_normal("\n"); 778 } else { 779 pci_devinfo(pa->pa_id, pa->pa_class, 0, 780 devinfo, sizeof(devinfo)); 781 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 782 PCI_REVISION(pa->pa_class)); 783 } 784 if (naive) 785 aprint_naive(": %s\n", naive); 786 else 787 aprint_naive("\n"); 788 } 789 #endif 790 791 /* 792 * Print out most of the PCI configuration registers. Typically used 793 * in a device attach routine like this: 794 * 795 * #ifdef MYDEV_DEBUG 796 * printf("%s: ", device_xname(sc->sc_dev)); 797 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 798 * #endif 799 */ 800 801 #define i2o(i) ((i) * 4) 802 #define o2i(o) ((o) / 4) 803 #define onoff2(str, rval, bit, onstr, offstr) \ 804 /*CONSTCOND*/ \ 805 printf(" %s: %s\n", (str), ((rval) & (bit)) ? onstr : offstr); 806 #define onoff(str, rval, bit) onoff2(str, rval, bit, "on", "off") 807 808 static void 809 pci_conf_print_common( 810 #ifdef _KERNEL 811 pci_chipset_tag_t pc, pcitag_t tag, 812 #endif 813 const pcireg_t *regs) 814 { 815 pci_class_t class; 816 pci_subclass_t subclass; 817 pci_interface_t interface; 818 pci_revision_t revision; 819 char vendor[PCI_VENDORSTR_LEN], product[PCI_PRODUCTSTR_LEN]; 820 const struct pci_class *classp, *subclassp, *interfacep; 821 const char *name; 822 pcireg_t rval; 823 unsigned int num; 824 825 rval = regs[o2i(PCI_CLASS_REG)]; 826 class = PCI_CLASS(rval); 827 subclass = PCI_SUBCLASS(rval); 828 interface = PCI_INTERFACE(rval); 829 revision = PCI_REVISION(rval); 830 831 rval = regs[o2i(PCI_ID_REG)]; 832 name = pci_findvendor(vendor, sizeof(vendor), PCI_VENDOR(rval)); 833 if (name) 834 printf(" Vendor Name: %s (0x%04x)\n", name, 835 PCI_VENDOR(rval)); 836 else 837 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 838 name = pci_findproduct(product, sizeof(product), PCI_VENDOR(rval), 839 PCI_PRODUCT(rval)); 840 if (name) 841 printf(" Device Name: %s (0x%04x)\n", name, 842 PCI_PRODUCT(rval)); 843 else 844 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 845 846 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 847 848 printf(" Command register: 0x%04x\n", rval & 0xffff); 849 onoff("I/O space accesses", rval, PCI_COMMAND_IO_ENABLE); 850 onoff("Memory space accesses", rval, PCI_COMMAND_MEM_ENABLE); 851 onoff("Bus mastering", rval, PCI_COMMAND_MASTER_ENABLE); 852 onoff("Special cycles", rval, PCI_COMMAND_SPECIAL_ENABLE); 853 onoff("MWI transactions", rval, PCI_COMMAND_INVALIDATE_ENABLE); 854 onoff("Palette snooping", rval, PCI_COMMAND_PALETTE_ENABLE); 855 onoff("Parity error checking", rval, PCI_COMMAND_PARITY_ENABLE); 856 onoff("Address/data stepping", rval, PCI_COMMAND_STEPPING_ENABLE); 857 onoff("System error (SERR)", rval, PCI_COMMAND_SERR_ENABLE); 858 onoff("Fast back-to-back transactions", rval, 859 PCI_COMMAND_BACKTOBACK_ENABLE); 860 onoff("Interrupt disable", rval, PCI_COMMAND_INTERRUPT_DISABLE); 861 862 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 863 onoff("Immediate Readiness", rval, PCI_STATUS_IMMD_READNESS); 864 onoff2("Interrupt status", rval, PCI_STATUS_INT_STATUS, "active", 865 "inactive"); 866 onoff("Capability List support", rval, PCI_STATUS_CAPLIST_SUPPORT); 867 onoff("66 MHz capable", rval, PCI_STATUS_66MHZ_SUPPORT); 868 onoff("User Definable Features (UDF) support", rval, 869 PCI_STATUS_UDF_SUPPORT); 870 onoff("Fast back-to-back capable", rval, 871 PCI_STATUS_BACKTOBACK_SUPPORT); 872 onoff("Data parity error detected", rval, PCI_STATUS_PARITY_ERROR); 873 874 printf(" DEVSEL timing: "); 875 switch (rval & PCI_STATUS_DEVSEL_MASK) { 876 case PCI_STATUS_DEVSEL_FAST: 877 printf("fast"); 878 break; 879 case PCI_STATUS_DEVSEL_MEDIUM: 880 printf("medium"); 881 break; 882 case PCI_STATUS_DEVSEL_SLOW: 883 printf("slow"); 884 break; 885 default: 886 printf("unknown/reserved"); /* XXX */ 887 break; 888 } 889 printf(" (0x%x)\n", PCIREG_SHIFTOUT(rval, PCI_STATUS_DEVSEL_MASK)); 890 891 onoff("Slave signaled Target Abort", rval, 892 PCI_STATUS_TARGET_TARGET_ABORT); 893 onoff("Master received Target Abort", rval, 894 PCI_STATUS_MASTER_TARGET_ABORT); 895 onoff("Master received Master Abort", rval, PCI_STATUS_MASTER_ABORT); 896 onoff("Asserted System Error (SERR)", rval, PCI_STATUS_SPECIAL_ERROR); 897 onoff("Parity error detected", rval, PCI_STATUS_PARITY_DETECT); 898 899 rval = regs[o2i(PCI_CLASS_REG)]; 900 for (classp = pci_classes; classp->name != NULL; classp++) { 901 if (class == classp->val) 902 break; 903 } 904 905 /* 906 * ECN: Change Root Complex Event Collector Class Code 907 * Old RCEC has subclass 0x06. It's the same as IOMMU. Read the type 908 * in PCIe extend capability to know whether it's RCEC or IOMMU. 909 */ 910 if ((class == PCI_CLASS_SYSTEM) 911 && (subclass == PCI_SUBCLASS_SYSTEM_IOMMU)) { 912 int pcie_capoff; 913 pcireg_t reg; 914 915 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 916 reg = regs[o2i(pcie_capoff + PCIE_XCAP)]; 917 if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_RC_EVNTC) 918 subclass = PCI_SUBCLASS_SYSTEM_RCEC; 919 } 920 } 921 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 922 while (subclassp && subclassp->name != NULL) { 923 if (subclass == subclassp->val) 924 break; 925 subclassp++; 926 } 927 928 interfacep = (subclassp && subclassp->name != NULL) ? 929 subclassp->subclasses : NULL; 930 while (interfacep && interfacep->name != NULL) { 931 if (interface == interfacep->val) 932 break; 933 interfacep++; 934 } 935 936 if (classp->name != NULL) 937 printf(" Class Name: %s (0x%02x)\n", classp->name, class); 938 else 939 printf(" Class ID: 0x%02x\n", class); 940 if (subclassp != NULL && subclassp->name != NULL) 941 printf(" Subclass Name: %s (0x%02x)\n", 942 subclassp->name, PCI_SUBCLASS(rval)); 943 else 944 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 945 if ((interfacep != NULL) && (interfacep->name != NULL) 946 && (strncmp(interfacep->name, "", 1) != 0)) 947 printf(" Interface Name: %s (0x%02x)\n", 948 interfacep->name, interface); 949 else 950 printf(" Interface: 0x%02x\n", interface); 951 printf(" Revision ID: 0x%02x\n", revision); 952 953 rval = regs[o2i(PCI_BHLC_REG)]; 954 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 955 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 956 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 957 PCI_HDRTYPE(rval)); 958 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 959 num = PCI_CACHELINE(rval); 960 printf(" Cache Line Size: %ubytes (0x%02x)\n", num * 4, num); 961 } 962 963 static int 964 pci_conf_print_bar( 965 #ifdef _KERNEL 966 pci_chipset_tag_t pc, pcitag_t tag, 967 #endif 968 const pcireg_t *regs, int reg, const char *name) 969 { 970 int width; 971 pcireg_t rval, rval64h; 972 bool ioen, memen; 973 #ifdef _KERNEL 974 pcireg_t mask, mask64h = 0; 975 #endif 976 977 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 978 ioen = rval & PCI_COMMAND_IO_ENABLE; 979 memen = rval & PCI_COMMAND_MEM_ENABLE; 980 981 width = 4; 982 /* 983 * Section 6.2.5.1, `Address Maps', tells us that: 984 * 985 * 1) The builtin software should have already mapped the 986 * device in a reasonable way. 987 * 988 * 2) A device which wants 2^n bytes of memory will hardwire 989 * the bottom n bits of the address to 0. As recommended, 990 * we write all 1s and see what we get back. 991 */ 992 993 rval = regs[o2i(reg)]; 994 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 995 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 996 rval64h = regs[o2i(reg + 4)]; 997 width = 8; 998 } else 999 rval64h = 0; 1000 1001 #ifdef _KERNEL 1002 if (rval != 0 && memen) { 1003 int s; 1004 1005 /* 1006 * The following sequence seems to make some devices 1007 * (e.g. host bus bridges, which don't normally 1008 * have their space mapped) very unhappy, to 1009 * the point of crashing the system. 1010 * 1011 * Therefore, if the mapping register is zero to 1012 * start out with, don't bother trying. 1013 */ 1014 s = splhigh(); 1015 pci_conf_write(pc, tag, reg, 0xffffffff); 1016 mask = pci_conf_read(pc, tag, reg); 1017 pci_conf_write(pc, tag, reg, rval); 1018 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 1019 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 1020 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 1021 mask64h = pci_conf_read(pc, tag, reg + 4); 1022 pci_conf_write(pc, tag, reg + 4, rval64h); 1023 } 1024 splx(s); 1025 } else 1026 mask = mask64h = 0; 1027 #endif /* _KERNEL */ 1028 1029 printf(" Base address register at 0x%02x", reg); 1030 if (name) 1031 printf(" (%s)", name); 1032 printf("\n "); 1033 if (rval == 0) { 1034 printf("not implemented\n"); 1035 return width; 1036 } 1037 printf("type: "); 1038 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 1039 const char *type, *prefetch; 1040 1041 switch (PCI_MAPREG_MEM_TYPE(rval)) { 1042 case PCI_MAPREG_MEM_TYPE_32BIT: 1043 type = "32-bit"; 1044 break; 1045 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 1046 type = "32-bit-1M"; 1047 break; 1048 case PCI_MAPREG_MEM_TYPE_64BIT: 1049 type = "64-bit"; 1050 break; 1051 default: 1052 type = "unknown (XXX)"; 1053 break; 1054 } 1055 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 1056 prefetch = ""; 1057 else 1058 prefetch = "non"; 1059 printf("%s %sprefetchable memory\n", type, prefetch); 1060 switch (PCI_MAPREG_MEM_TYPE(rval)) { 1061 case PCI_MAPREG_MEM_TYPE_64BIT: 1062 printf(" base: 0x%016llx", 1063 PCI_MAPREG_MEM64_ADDR( 1064 ((((long long) rval64h) << 32) | rval))); 1065 if (!memen) 1066 printf(", disabled"); 1067 printf("\n"); 1068 #ifdef _KERNEL 1069 printf(" size: 0x%016llx\n", 1070 PCI_MAPREG_MEM64_SIZE( 1071 ((((long long) mask64h) << 32) | mask))); 1072 #endif 1073 break; 1074 case PCI_MAPREG_MEM_TYPE_32BIT: 1075 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 1076 default: 1077 printf(" base: 0x%08x", 1078 PCI_MAPREG_MEM_ADDR(rval)); 1079 if (!memen) 1080 printf(", disabled"); 1081 printf("\n"); 1082 #ifdef _KERNEL 1083 printf(" size: 0x%08x\n", 1084 PCI_MAPREG_MEM_SIZE(mask)); 1085 #endif 1086 break; 1087 } 1088 } else { 1089 #ifdef _KERNEL 1090 if (ioen) 1091 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 1092 #endif 1093 printf("I/O\n"); 1094 printf(" base: 0x%08x", PCI_MAPREG_IO_ADDR(rval)); 1095 if (!ioen) 1096 printf(", disabled"); 1097 printf("\n"); 1098 #ifdef _KERNEL 1099 printf(" size: 0x%08x\n", PCI_MAPREG_IO_SIZE(mask)); 1100 #endif 1101 } 1102 1103 return width; 1104 } 1105 1106 static void 1107 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 1108 { 1109 int off, needaddr, neednl; 1110 1111 needaddr = 1; 1112 neednl = 0; 1113 for (off = first; off < pastlast; off += 4) { 1114 if ((off % 16) == 0 || needaddr) { 1115 printf(" 0x%02x:", off); 1116 needaddr = 0; 1117 } 1118 printf(" 0x%08x", regs[o2i(off)]); 1119 neednl = 1; 1120 if ((off % 16) == 12) { 1121 printf("\n"); 1122 neednl = 0; 1123 } 1124 } 1125 if (neednl) 1126 printf("\n"); 1127 } 1128 1129 static const char * 1130 pci_conf_print_agp_calcycle(uint8_t cal) 1131 { 1132 1133 switch (cal) { 1134 case 0x0: 1135 return "4ms"; 1136 case 0x1: 1137 return "16ms"; 1138 case 0x2: 1139 return "64ms"; 1140 case 0x3: 1141 return "256ms"; 1142 case 0x7: 1143 return "Calibration Cycle Not Needed"; 1144 default: 1145 return "(reserved)"; 1146 } 1147 } 1148 1149 static void 1150 pci_conf_print_agp_datarate(pcireg_t reg, bool isagp3) 1151 { 1152 if (isagp3) { 1153 /* AGP 3.0 */ 1154 if (reg & AGP_MODE_V3_RATE_4x) 1155 printf("x4"); 1156 if (reg & AGP_MODE_V3_RATE_8x) 1157 printf("x8"); 1158 } else { 1159 /* AGP 2.0 */ 1160 if (reg & AGP_MODE_V2_RATE_1x) 1161 printf("x1"); 1162 if (reg & AGP_MODE_V2_RATE_2x) 1163 printf("x2"); 1164 if (reg & AGP_MODE_V2_RATE_4x) 1165 printf("x4"); 1166 } 1167 printf("\n"); 1168 } 1169 1170 static void 1171 pci_conf_print_agp_cap(const pcireg_t *regs, int capoff) 1172 { 1173 pcireg_t rval; 1174 bool isagp3; 1175 1176 printf("\n AGP Capabilities Register\n"); 1177 1178 rval = regs[o2i(capoff)]; 1179 printf(" Revision: %d.%d\n", 1180 PCI_CAP_AGP_MAJOR(rval), PCI_CAP_AGP_MINOR(rval)); 1181 1182 rval = regs[o2i(capoff + PCI_AGP_STATUS)]; 1183 printf(" Status register: 0x%04x\n", rval); 1184 printf(" RQ: %u\n", 1185 PCIREG_SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1186 printf(" ARQSZ: %u\n", 1187 PCIREG_SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1188 printf(" CAL cycle: %s\n", 1189 pci_conf_print_agp_calcycle(PCIREG_SHIFTOUT(rval, AGP_MODE_CAL))); 1190 onoff("SBA", rval, AGP_MODE_SBA); 1191 onoff("htrans#", rval, AGP_MODE_HTRANS); 1192 onoff("Over 4G", rval, AGP_MODE_4G); 1193 onoff("Fast Write", rval, AGP_MODE_FW); 1194 onoff("AGP 3.0 Mode", rval, AGP_MODE_MODE_3); 1195 isagp3 = rval & AGP_MODE_MODE_3; 1196 printf(" Data Rate Support: "); 1197 pci_conf_print_agp_datarate(rval, isagp3); 1198 1199 rval = regs[o2i(capoff + PCI_AGP_COMMAND)]; 1200 printf(" Command register: 0x%08x\n", rval); 1201 printf(" PRQ: %u\n", 1202 PCIREG_SHIFTOUT(rval, AGP_MODE_RQ) + 1); 1203 printf(" PARQSZ: %u\n", 1204 PCIREG_SHIFTOUT(rval, AGP_MODE_ARQSZ)); 1205 printf(" PCAL cycle: %s\n", 1206 pci_conf_print_agp_calcycle(PCIREG_SHIFTOUT(rval, AGP_MODE_CAL))); 1207 onoff("SBA", rval, AGP_MODE_SBA); 1208 onoff("AGP", rval, AGP_MODE_AGP); 1209 onoff("Over 4G", rval, AGP_MODE_4G); 1210 onoff("Fast Write", rval, AGP_MODE_FW); 1211 if (isagp3) { 1212 printf(" Data Rate Enable: "); 1213 /* 1214 * The Data Rate Enable bits are used only on 3.0 and the 1215 * Command register has no AGP_MODE_MODE_3 bit, so pass the 1216 * flag to print correctly. 1217 */ 1218 pci_conf_print_agp_datarate(rval, isagp3); 1219 } 1220 } 1221 1222 static const char * 1223 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1224 { 1225 1226 switch ((caps >> 6) & 7) { 1227 case 0: return "self-powered"; 1228 case 1: return "55 mA"; 1229 case 2: return "100 mA"; 1230 case 3: return "160 mA"; 1231 case 4: return "220 mA"; 1232 case 5: return "270 mA"; 1233 case 6: return "320 mA"; 1234 case 7: 1235 default: return "375 mA"; 1236 } 1237 } 1238 1239 static const char * 1240 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1241 { 1242 static const char unk[] = "unknown"; 1243 static const char *pmrev[8] = { 1244 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1245 }; 1246 if (val > 7) 1247 return unk; 1248 return pmrev[val]; 1249 } 1250 1251 static void 1252 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1253 { 1254 uint16_t caps, pmcsr; 1255 1256 caps = regs[o2i(capoff)] >> PCI_PMCR_SHIFT; 1257 pmcsr = regs[o2i(capoff + PCI_PMCSR)]; 1258 1259 printf("\n PCI Power Management Capabilities Register\n"); 1260 1261 printf(" Capabilities register: 0x%04x\n", caps); 1262 printf(" Version: %s\n", 1263 pci_conf_print_pcipm_cap_pmrev(caps & PCI_PMCR_VERSION_MASK)); 1264 onoff("PME# clock", caps, PCI_PMCR_PME_CLOCK); 1265 onoff("Device specific initialization", caps, PCI_PMCR_DSI); 1266 printf(" 3.3V auxiliary current: %s\n", 1267 pci_conf_print_pcipm_cap_aux(caps)); 1268 onoff("D1 power management state support", caps, PCI_PMCR_D1SUPP); 1269 onoff("D2 power management state support", caps, PCI_PMCR_D2SUPP); 1270 onoff("PME# support D0", caps, PCI_PMCR_PME_D0); 1271 onoff("PME# support D1", caps, PCI_PMCR_PME_D1); 1272 onoff("PME# support D2", caps, PCI_PMCR_PME_D2); 1273 onoff("PME# support D3 hot", caps, PCI_PMCR_PME_D3HOT); 1274 onoff("PME# support D3 cold", caps, PCI_PMCR_PME_D3COLD); 1275 1276 printf(" Control/status register: 0x%08x\n", pmcsr); 1277 printf(" Power state: D%d\n", pmcsr & PCI_PMCSR_STATE_MASK); 1278 onoff("PCI Express reserved", (pmcsr >> 2), 1); 1279 onoff("No soft reset", pmcsr, PCI_PMCSR_NO_SOFTRST); 1280 printf(" PME# assertion: %sabled\n", 1281 (pmcsr & PCI_PMCSR_PME_EN) ? "en" : "dis"); 1282 printf(" Data Select: %d\n", 1283 PCIREG_SHIFTOUT(pmcsr, PCI_PMCSR_DATASEL_MASK)); 1284 printf(" Data Scale: %d\n", 1285 PCIREG_SHIFTOUT(pmcsr, PCI_PMCSR_DATASCL_MASK)); 1286 onoff("PME# status", pmcsr, PCI_PMCSR_PME_STS); 1287 printf(" Bridge Support Extensions register: 0x%02x\n", 1288 (pmcsr >> 16) & 0xff); 1289 onoff("B2/B3 support", pmcsr, PCI_PMCSR_B2B3_SUPPORT); 1290 onoff("Bus Power/Clock Control Enable", pmcsr, PCI_PMCSR_BPCC_EN); 1291 printf(" Data register: 0x%02x\n", 1292 PCIREG_SHIFTOUT(pmcsr, PCI_PMCSR_DATA)); 1293 } 1294 1295 /* XXX pci_conf_print_vpd_cap */ 1296 /* XXX pci_conf_print_slotid_cap */ 1297 1298 static void 1299 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1300 { 1301 uint32_t ctl, mmc, mme; 1302 1303 regs += o2i(capoff); 1304 ctl = *regs++; 1305 mmc = PCIREG_SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1306 mme = PCIREG_SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1307 1308 printf("\n PCI Message Signaled Interrupt\n"); 1309 1310 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1311 onoff("MSI Enabled", ctl, PCI_MSI_CTL_MSI_ENABLE); 1312 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1313 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1314 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1315 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1316 onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR); 1317 onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK); 1318 onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP); 1319 onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN); 1320 printf(" Message Address %sregister: 0x%08x\n", 1321 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1322 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1323 printf(" Message Address %sregister: 0x%08x\n", 1324 "(upper) ", *regs++); 1325 } 1326 printf(" Message Data register: "); 1327 if (ctl & PCI_MSI_CTL_EXTMDATA_CAP) 1328 printf("0x%08x\n", *regs); 1329 else 1330 printf("0x%04x\n", *regs & 0xffff); 1331 regs++; 1332 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1333 printf(" Vector Mask register: 0x%08x\n", *regs++); 1334 printf(" Vector Pending register: 0x%08x\n", *regs++); 1335 } 1336 } 1337 1338 /* XXX pci_conf_print_cpci_hostwap_cap */ 1339 1340 /* 1341 * For both command register and status register. 1342 * The argument "idx" is index number (0 to 7). 1343 */ 1344 static int 1345 pcix_split_trans(unsigned int idx) 1346 { 1347 static int table[8] = { 1348 1, 2, 3, 4, 8, 12, 16, 32 1349 }; 1350 1351 if (idx >= __arraycount(table)) 1352 return -1; 1353 return table[idx]; 1354 } 1355 1356 static void 1357 pci_conf_print_pcix_cap_2ndbusmode(int num) 1358 { 1359 const char *maxfreq, *maxperiod; 1360 1361 printf(" Mode: "); 1362 if (num <= 0x07) 1363 printf("PCI-X Mode 1\n"); 1364 else if (num <= 0x0b) 1365 printf("PCI-X 266 (Mode 2)\n"); 1366 else 1367 printf("PCI-X 533 (Mode 2)\n"); 1368 1369 printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC"); 1370 switch (num & 0x03) { 1371 default: 1372 case 0: 1373 maxfreq = "N/A"; 1374 maxperiod = "N/A"; 1375 break; 1376 case 1: 1377 maxfreq = "66MHz"; 1378 maxperiod = "15ns"; 1379 break; 1380 case 2: 1381 maxfreq = "100MHz"; 1382 maxperiod = "10ns"; 1383 break; 1384 case 3: 1385 maxfreq = "133MHz"; 1386 maxperiod = "7.5ns"; 1387 break; 1388 } 1389 printf(" Max Clock Freq: %s\n", maxfreq); 1390 printf(" Min Clock Period: %s\n", maxperiod); 1391 } 1392 1393 static void 1394 pci_conf_print_pcix_cap(const pcireg_t *regs, int capoff) 1395 { 1396 pcireg_t reg; 1397 int isbridge; 1398 int i; 1399 1400 isbridge = (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) 1401 & PCI_HDRTYPE_PPB) != 0 ? 1 : 0; 1402 printf("\n PCI-X %s Capabilities Register\n", 1403 isbridge ? "Bridge" : "Non-bridge"); 1404 1405 reg = regs[o2i(capoff)]; 1406 if (isbridge != 0) { 1407 printf(" Secondary status register: 0x%04x\n", 1408 (reg & 0xffff0000) >> 16); 1409 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1410 onoff("133MHz capable", reg, PCIX_STATUS_133); 1411 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1412 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1413 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1414 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1415 pci_conf_print_pcix_cap_2ndbusmode( 1416 PCIREG_SHIFTOUT(reg, PCIX_BRIDGE_2NDST_CLKF)); 1417 printf(" Version: 0x%x\n", 1418 (reg & PCIX_BRIDGE_2NDST_VER_MASK) 1419 >> PCIX_BRIDGE_2NDST_VER_SHIFT); 1420 onoff("266MHz capable", reg, PCIX_BRIDGE_ST_266); 1421 onoff("533MHz capable", reg, PCIX_BRIDGE_ST_533); 1422 } else { 1423 printf(" Command register: 0x%04x\n", 1424 (reg & 0xffff0000) >> 16); 1425 onoff("Data Parity Error Recovery", reg, 1426 PCIX_CMD_PERR_RECOVER); 1427 onoff("Enable Relaxed Ordering", reg, PCIX_CMD_RELAXED_ORDER); 1428 printf(" Maximum Burst Read Count: %u\n", 1429 PCIX_CMD_BYTECNT(reg)); 1430 printf(" Maximum Split Transactions: %d\n", 1431 pcix_split_trans((reg & PCIX_CMD_SPLTRANS_MASK) 1432 >> PCIX_CMD_SPLTRANS_SHIFT)); 1433 } 1434 reg = regs[o2i(capoff+PCIX_STATUS)]; /* Or PCIX_BRIDGE_PRI_STATUS */ 1435 printf(" %sStatus register: 0x%08x\n", 1436 isbridge ? "Bridge " : "", reg); 1437 printf(" Function: %d\n", PCIX_STATUS_FN(reg)); 1438 printf(" Device: %d\n", PCIX_STATUS_DEV(reg)); 1439 printf(" Bus: %d\n", PCIX_STATUS_BUS(reg)); 1440 onoff("64bit device", reg, PCIX_STATUS_64BIT); 1441 onoff("133MHz capable", reg, PCIX_STATUS_133); 1442 onoff("Split completion discarded", reg, PCIX_STATUS_SPLDISC); 1443 onoff("Unexpected split completion", reg, PCIX_STATUS_SPLUNEX); 1444 if (isbridge != 0) { 1445 onoff("Split completion overrun", reg, PCIX_BRIDGE_ST_SPLOVRN); 1446 onoff("Split request delayed", reg, PCIX_BRIDGE_ST_SPLRQDL); 1447 } else { 1448 onoff2("Device Complexity", reg, PCIX_STATUS_DEVCPLX, 1449 "bridge device", "simple device"); 1450 printf(" Designed max memory read byte count: %d\n", 1451 512 << ((reg & PCIX_STATUS_MAXB_MASK) 1452 >> PCIX_STATUS_MAXB_SHIFT)); 1453 printf(" Designed max outstanding split transaction: %d\n", 1454 pcix_split_trans((reg & PCIX_STATUS_MAXST_MASK) 1455 >> PCIX_STATUS_MAXST_SHIFT)); 1456 printf(" MAX cumulative Read Size: %u\n", 1457 8 << ((reg & 0x1c000000) >> PCIX_STATUS_MAXRS_SHIFT)); 1458 onoff("Received split completion error", reg, 1459 PCIX_STATUS_SCERR); 1460 } 1461 onoff("266MHz capable", reg, PCIX_STATUS_266); 1462 onoff("533MHz capable", reg, PCIX_STATUS_533); 1463 1464 if (isbridge == 0) 1465 return; 1466 1467 /* Only for bridge */ 1468 for (i = 0; i < 2; i++) { 1469 reg = regs[o2i(capoff + PCIX_BRIDGE_UP_STCR + (4 * i))]; 1470 printf(" %s split transaction control register: 0x%08x\n", 1471 (i == 0) ? "Upstream" : "Downstream", reg); 1472 printf(" Capacity: %d\n", reg & PCIX_BRIDGE_STCAP); 1473 printf(" Commitment Limit: %d\n", 1474 (reg & PCIX_BRIDGE_STCLIM) >> PCIX_BRIDGE_STCLIM_SHIFT); 1475 } 1476 } 1477 1478 /* pci_conf_print_ht_slave_cap */ 1479 /* pci_conf_print_ht_host_cap */ 1480 /* pci_conf_print_ht_switch_cap */ 1481 /* pci_conf_print_ht_intr_cap */ 1482 /* pci_conf_print_ht_revid_cap */ 1483 /* pci_conf_print_ht_unitid_cap */ 1484 /* pci_conf_print_ht_extcnf_cap */ 1485 /* pci_conf_print_ht_addrmap_cap */ 1486 /* pci_conf_print_ht_msimap_cap */ 1487 1488 static void 1489 pci_conf_print_ht_msimap_cap(const pcireg_t *regs, int capoff) 1490 { 1491 pcireg_t val; 1492 uint32_t lo, hi; 1493 1494 /* 1495 * Print the rest of the command register bits. Others are 1496 * printed in pci_conf_print_ht_cap(). 1497 */ 1498 val = regs[o2i(capoff + PCI_HT_CMD)]; 1499 onoff("Enable", val, PCI_HT_MSI_ENABLED); 1500 onoff("Fixed", val, PCI_HT_MSI_FIXED); 1501 1502 lo = regs[o2i(capoff + PCI_HT_MSI_ADDR_LO)]; 1503 hi = regs[o2i(capoff + PCI_HT_MSI_ADDR_HI)]; 1504 printf(" Address Low register: 0x%08x\n", lo); 1505 printf(" Address high register: 0x%08x\n", hi); 1506 printf(" Address: 0x%016" PRIx64 "\n", 1507 (uint64_t)hi << 32 | (lo & PCI_HT_MSI_ADDR_LO_MASK)); 1508 } 1509 1510 /* pci_conf_print_ht_droute_cap */ 1511 /* pci_conf_print_ht_vcset_cap */ 1512 /* pci_conf_print_ht_retry_cap */ 1513 /* pci_conf_print_ht_x86enc_cap */ 1514 /* pci_conf_print_ht_gen3_cap */ 1515 /* pci_conf_print_ht_fle_cap */ 1516 /* pci_conf_print_ht_pm_cap */ 1517 /* pci_conf_print_ht_hnc_cap */ 1518 1519 static const struct ht_types { 1520 pcireg_t cap; 1521 const char *name; 1522 void (*printfunc)(const pcireg_t *, int); 1523 } ht_captab[] = { 1524 {PCI_HT_CAP_SLAVE, "Slave or Primary Interface", NULL }, 1525 {PCI_HT_CAP_HOST, "Host or Secondary Interface", NULL }, 1526 {PCI_HT_CAP_SWITCH, "Switch", NULL }, 1527 {PCI_HT_CAP_INTERRUPT, "Interrupt Discovery and Configuration", NULL}, 1528 {PCI_HT_CAP_REVID, "Revision ID", NULL }, 1529 {PCI_HT_CAP_UNITID_CLUMP, "UnitID Clumping", NULL }, 1530 {PCI_HT_CAP_EXTCNFSPACE, "Extended Configuration Space Access", NULL }, 1531 {PCI_HT_CAP_ADDRMAP, "Address Mapping", NULL }, 1532 {PCI_HT_CAP_MSIMAP, "MSI Mapping", pci_conf_print_ht_msimap_cap }, 1533 {PCI_HT_CAP_DIRECTROUTE, "Direct Route", NULL }, 1534 {PCI_HT_CAP_VCSET, "VCSet", NULL }, 1535 {PCI_HT_CAP_RETRYMODE, "Retry Mode", NULL }, 1536 {PCI_HT_CAP_X86ENCODE, "X86 Encoding", NULL }, 1537 {PCI_HT_CAP_GEN3, "Gen3", NULL }, 1538 {PCI_HT_CAP_FLE, "Function-Level Extension", NULL }, 1539 {PCI_HT_CAP_PM, "Power Management", NULL }, 1540 {PCI_HT_CAP_HIGHNODECNT, "High Node Count", NULL }, 1541 }; 1542 1543 static void 1544 pci_conf_print_ht_cap(const pcireg_t *regs, int capoff) 1545 { 1546 pcireg_t val, foundcap; 1547 unsigned int off; 1548 1549 val = regs[o2i(capoff + PCI_HT_CMD)]; 1550 1551 printf("\n HyperTransport Capability Register at 0x%02x\n", capoff); 1552 1553 printf(" Command register: 0x%04x\n", val >> 16); 1554 foundcap = PCI_HT_CAP(val); 1555 for (off = 0; off < __arraycount(ht_captab); off++) { 1556 if (ht_captab[off].cap == foundcap) 1557 break; 1558 } 1559 printf(" Capability Type: 0x%02x ", foundcap); 1560 if (off >= __arraycount(ht_captab)) { 1561 printf("(unknown)\n"); 1562 return; 1563 } 1564 printf("(%s)\n", ht_captab[off].name); 1565 if (ht_captab[off].printfunc != NULL) 1566 ht_captab[off].printfunc(regs, capoff); 1567 } 1568 1569 static void 1570 pci_conf_print_vendspec_cap(const pcireg_t *regs, int capoff) 1571 { 1572 uint16_t caps; 1573 1574 caps = regs[o2i(capoff)] >> PCI_VENDORSPECIFIC_SHIFT; 1575 1576 printf("\n PCI Vendor Specific Capabilities Register\n"); 1577 printf(" Capabilities length: 0x%02x\n", caps & 0xff); 1578 } 1579 1580 static void 1581 pci_conf_print_debugport_cap(const pcireg_t *regs, int capoff) 1582 { 1583 pcireg_t val; 1584 1585 val = regs[o2i(capoff + PCI_DEBUG_BASER)]; 1586 1587 printf("\n Debugport Capability Register\n"); 1588 printf(" Debug base Register: 0x%04x\n", 1589 val >> PCI_DEBUG_BASER_SHIFT); 1590 printf(" port offset: 0x%04x\n", 1591 (val & PCI_DEBUG_PORTOFF_MASK) >> PCI_DEBUG_PORTOFF_SHIFT); 1592 printf(" BAR number: %u\n", 1593 (val & PCI_DEBUG_BARNUM_MASK) >> PCI_DEBUG_BARNUM_SHIFT); 1594 } 1595 1596 /* XXX pci_conf_print_cpci_rsrcctl_cap */ 1597 /* XXX pci_conf_print_hotplug_cap */ 1598 1599 static void 1600 pci_conf_print_subsystem_cap(const pcireg_t *regs, int capoff) 1601 { 1602 pcireg_t reg; 1603 1604 reg = regs[o2i(capoff + PCI_CAP_SUBSYS_ID)]; 1605 1606 printf("\n Subsystem ID Capability Register\n"); 1607 printf(" Subsystem ID: 0x%08x\n", reg); 1608 } 1609 1610 /* XXX pci_conf_print_agp8_cap */ 1611 static void 1612 pci_conf_print_secure_cap(const pcireg_t *regs, int capoff) 1613 { 1614 pcireg_t reg, reg2, val; 1615 bool havemisc1; 1616 1617 printf("\n Secure Capability Register\n"); 1618 reg = regs[o2i(capoff + PCI_SECURE_CAP)]; 1619 printf(" Capability Register: 0x%04x\n", reg >> 16); 1620 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_CAP_TYPE); 1621 printf(" Capability block type: "); 1622 /* I know IOMMU Only */ 1623 if (val == PCI_SECURE_CAP_TYPE_IOMMU) 1624 printf("IOMMU\n"); 1625 else { 1626 printf("0x%x(unknown)\n", val); 1627 return; 1628 } 1629 1630 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_CAP_REV); 1631 printf(" Capability revision: 0x%02x ", val); 1632 if (val == PCI_SECURE_CAP_REV_IOMMU) 1633 printf("(IOMMU)\n"); 1634 else { 1635 printf("(unknown)\n"); 1636 return; 1637 } 1638 onoff("IOTLB support", reg, PCI_SECURE_CAP_IOTLBSUP); 1639 onoff("HyperTransport tunnel translation support", reg, 1640 PCI_SECURE_CAP_HTTUNNEL); 1641 onoff("Not present table entries cached", reg, PCI_SECURE_CAP_NPCACHE); 1642 onoff("IOMMU Extended Feature Register support", reg, 1643 PCI_SECURE_CAP_EFRSUP); 1644 onoff("IOMMU Miscellaneous Information Register 1", reg, 1645 PCI_SECURE_CAP_EXT); 1646 havemisc1 = reg & PCI_SECURE_CAP_EXT; 1647 1648 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_BAL)]; 1649 printf(" Base Address Low Register: 0x%08x\n", reg); 1650 onoff("Enable", reg, PCI_SECURE_IOMMU_BAL_EN); 1651 reg2 = regs[o2i(capoff + PCI_SECURE_IOMMU_BAH)]; 1652 printf(" Base Address High Register: 0x%08x\n", reg2); 1653 printf(" Base Address: 0x%016" PRIx64 "\n", 1654 ((uint64_t)reg2 << 32) 1655 | (reg & (PCI_SECURE_IOMMU_BAL_H | PCI_SECURE_IOMMU_BAL_L))); 1656 1657 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_RANGE)]; 1658 printf(" IOMMU Range Register: 0x%08x\n", reg); 1659 printf(" HyperTransport UnitID: 0x%02x\n", 1660 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_UNITID)); 1661 onoff("Range valid", reg, PCI_SECURE_IOMMU_RANGE_RNGVALID); 1662 printf(" Device range bus number: 0x%02x\n", 1663 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_BUSNUM)); 1664 printf(" First device: 0x%04x\n", 1665 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_FIRSTDEV)); 1666 printf(" Last device: 0x%04x\n", 1667 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_RANGE_LASTDEV)); 1668 1669 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC0)]; 1670 printf(" Miscellaneous Information Register 0: 0x%08x\n", reg); 1671 printf(" MSI Message number: 0x%02x\n", 1672 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MSINUM)); 1673 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_GVASIZE); 1674 printf(" Guest Virtual Address size: "); 1675 if (val == PCI_SECURE_IOMMU_MISC0_GVASIZE_48B) 1676 printf("48bits\n"); 1677 else 1678 printf("0x%x(unknown)\n", val); 1679 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_PASIZE); 1680 printf(" Physical Address size: %dbits\n", val); 1681 val = PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_VASIZE); 1682 printf(" Virtual Address size: %dbits\n", val); 1683 onoff("ATS response address range reserved", reg, 1684 PCI_SECURE_IOMMU_MISC0_ATSRESV); 1685 printf(" Peripheral Page Request MSI Message number: 0x%02x\n", 1686 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC0_MISNPPR)); 1687 1688 if (!havemisc1) 1689 return; 1690 1691 reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC1)]; 1692 printf(" Miscellaneous Information Register 1: 0x%08x\n", reg); 1693 printf(" MSI Message number (GA): 0x%02x\n", 1694 PCIREG_SHIFTOUT(reg, PCI_SECURE_IOMMU_MISC1_MSINUM)); 1695 } 1696 1697 static void 1698 pci_print_pcie_L0s_latency(uint32_t val) 1699 { 1700 1701 switch (val) { 1702 case 0x0: 1703 printf("Less than 64ns\n"); 1704 break; 1705 case 0x1: 1706 case 0x2: 1707 case 0x3: 1708 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 1709 break; 1710 case 0x4: 1711 printf("512ns to less than 1us\n"); 1712 break; 1713 case 0x5: 1714 printf("1us to less than 2us\n"); 1715 break; 1716 case 0x6: 1717 printf("2us - 4us\n"); 1718 break; 1719 case 0x7: 1720 printf("More than 4us\n"); 1721 break; 1722 } 1723 } 1724 1725 static void 1726 pci_print_pcie_L1_latency(uint32_t val) 1727 { 1728 1729 switch (val) { 1730 case 0x0: 1731 printf("Less than 1us\n"); 1732 break; 1733 case 0x6: 1734 printf("32us - 64us\n"); 1735 break; 1736 case 0x7: 1737 printf("More than 64us\n"); 1738 break; 1739 default: 1740 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 1741 break; 1742 } 1743 } 1744 1745 static void 1746 pci_print_pcie_compl_timeout(uint32_t val) 1747 { 1748 1749 switch (val) { 1750 case 0x0: 1751 printf("50us to 50ms\n"); 1752 break; 1753 case 0x5: 1754 printf("16ms to 55ms\n"); 1755 break; 1756 case 0x6: 1757 printf("65ms to 210ms\n"); 1758 break; 1759 case 0x9: 1760 printf("260ms to 900ms\n"); 1761 break; 1762 case 0xa: 1763 printf("1s to 3.5s\n"); 1764 break; 1765 default: 1766 printf("unknown %u value\n", val); 1767 break; 1768 } 1769 } 1770 1771 static const char * const pcie_linkspeeds[] = { 1772 "2.5", "5.0", "8.0", "16.0", "32.0" 1773 }; 1774 1775 /* 1776 * Print link speed. This function is used for the following register bits: 1777 * Maximum Link Speed in LCAP 1778 * Current Link Speed in LCSR 1779 * Target Link Speed in LCSR2 1780 * All of above bitfield's values start from 1. 1781 * For LCSR2, 0 is allowed for a device which supports 2.5GT/s only (and 1782 * this check also works for devices which compliant to versions of the base 1783 * specification prior to 3.0. 1784 */ 1785 static void 1786 pci_print_pcie_linkspeed(int regnum, pcireg_t val) 1787 { 1788 1789 if ((regnum == PCIE_LCSR2) && (val == 0)) 1790 printf("2.5GT/s\n"); 1791 else if ((val < 1) || (val > __arraycount(pcie_linkspeeds))) 1792 printf("unknown value (%u)\n", val); 1793 else 1794 printf("%sGT/s\n", pcie_linkspeeds[val - 1]); 1795 } 1796 1797 /* 1798 * Print link speed "vector". 1799 * This function is used for the following register bits: 1800 * Supported Link Speeds Vector in LCAP2 1801 * Lower SKP OS Generation Supported Speed Vector in LCAP2 1802 * Lower SKP OS Reception Supported Speed Vector in LCAP2 1803 * Enable Lower SKP OS Generation Vector in LCTL3 1804 * All of above bitfield's values start from 0. 1805 */ 1806 static void 1807 pci_print_pcie_linkspeedvector(pcireg_t val) 1808 { 1809 unsigned int i; 1810 1811 /* Start from 0 */ 1812 for (i = 0; i < 16; i++) 1813 if (((val >> i) & 0x01) != 0) { 1814 if (i >= __arraycount(pcie_linkspeeds)) 1815 printf(" unknown vector (0x%x)", 1 << i); 1816 else 1817 printf(" %sGT/s", pcie_linkspeeds[i]); 1818 } 1819 } 1820 1821 static void 1822 pci_print_pcie_link_deemphasis(pcireg_t val) 1823 { 1824 switch (val) { 1825 case 0: 1826 printf("-6dB"); 1827 break; 1828 case 1: 1829 printf("-3.5dB"); 1830 break; 1831 default: 1832 printf("(reserved value)"); 1833 } 1834 } 1835 1836 static const struct _pcie_link_preset_preshoot_deemphasis { 1837 const char *preshoot; 1838 const char *deemphasis; 1839 } pcie_link_preset_preshoot_deemphasis[] = { 1840 { "0.0", "-6.0+-1.5" }, /* P0 */ 1841 { "0.0", "-3.5+-1" }, /* P1 */ 1842 { "0.0", "-4.4+-1.5" }, /* P2 */ 1843 { "0.0", "-2.5+-1" }, /* P3 */ 1844 { "0.0", "0.0" }, /* P4 */ 1845 { "1.9+-1", "0.0" }, /* P5 */ 1846 { "2.5+-1", "0.0" }, /* P6 */ 1847 { "3.5+-1", "-6.0+-1.5" }, /* P7 */ 1848 { "3.5+-1", "-3.5+-1" }, /* P8 */ 1849 { "3.5+-1", "0.0" }, /* P9 */ 1850 { "0.0", NULL } /* P10 */ 1851 }; 1852 1853 static void 1854 pci_print_pcie_link_preset_preshoot_deemphasis(pcireg_t val) 1855 { 1856 const char *deemphasis; 1857 1858 if (val >= __arraycount(pcie_link_preset_preshoot_deemphasis)) { 1859 /* 1860 * This may be printed because the default value of some 1861 * register fields is 0b1111. 1862 */ 1863 printf("reserved value (0x%x)", val); 1864 return; 1865 } 1866 1867 printf("Preshoot %sdB", 1868 pcie_link_preset_preshoot_deemphasis[val].preshoot); 1869 deemphasis = pcie_link_preset_preshoot_deemphasis[val].deemphasis; 1870 1871 if (deemphasis != NULL) 1872 printf(", De-emphasis %sdB", deemphasis); 1873 } 1874 1875 static void 1876 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 1877 { 1878 pcireg_t reg; /* for each register */ 1879 pcireg_t val; /* for each bitfield */ 1880 bool check_slot = false; 1881 unsigned int pcie_devtype; 1882 bool check_upstreamport = false; 1883 unsigned int pciever; 1884 unsigned int i; 1885 1886 printf("\n PCI Express Capabilities Register\n"); 1887 /* Capability Register */ 1888 reg = regs[o2i(capoff)]; 1889 printf(" Capability register: 0x%04x\n", reg >> 16); 1890 pciever = (unsigned int)(PCIE_XCAP_VER(reg)); 1891 printf(" Capability version: %u\n", pciever); 1892 printf(" Device type: "); 1893 pcie_devtype = PCIE_XCAP_TYPE(reg); 1894 switch (pcie_devtype) { 1895 case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */ 1896 printf("PCI Express Endpoint device\n"); 1897 check_upstreamport = true; 1898 break; 1899 case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */ 1900 printf("Legacy PCI Express Endpoint device\n"); 1901 check_upstreamport = true; 1902 break; 1903 case PCIE_XCAP_TYPE_RP: /* 0x4 */ 1904 printf("Root Port of PCI Express Root Complex\n"); 1905 check_slot = true; 1906 break; 1907 case PCIE_XCAP_TYPE_UP: /* 0x5 */ 1908 printf("Upstream Port of PCI Express Switch\n"); 1909 check_upstreamport = true; 1910 break; 1911 case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ 1912 printf("Downstream Port of PCI Express Switch\n"); 1913 check_slot = true; 1914 break; 1915 case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ 1916 printf("PCI Express to PCI/PCI-X Bridge\n"); 1917 check_upstreamport = true; 1918 break; 1919 case PCIE_XCAP_TYPE_PCI2PCIE: /* 0x8 */ 1920 printf("PCI/PCI-X to PCI Express Bridge\n"); 1921 /* Upstream port is not PCIe */ 1922 check_slot = true; 1923 break; 1924 case PCIE_XCAP_TYPE_RCIEP: /* 0x9 */ 1925 printf("Root Complex Integrated Endpoint\n"); 1926 break; 1927 case PCIE_XCAP_TYPE_RC_EVNTC: /* 0xa */ 1928 printf("Root Complex Event Collector\n"); 1929 break; 1930 default: 1931 printf("unknown\n"); 1932 break; 1933 } 1934 onoff("Slot implemented", reg, PCIE_XCAP_SI); 1935 printf(" Interrupt Message Number: 0x%02x\n", 1936 PCIREG_SHIFTOUT(reg, PCIE_XCAP_IRQ)); 1937 1938 /* Device Capability Register */ 1939 reg = regs[o2i(capoff + PCIE_DCAP)]; 1940 printf(" Device Capabilities Register: 0x%08x\n", reg); 1941 printf(" Max Payload Size Supported: %u bytes max\n", 1942 128 << (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD)); 1943 printf(" Phantom Functions Supported: "); 1944 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP_PHANTOM_FUNCS)) { 1945 case 0x0: 1946 printf("not available\n"); 1947 break; 1948 case 0x1: 1949 printf("MSB\n"); 1950 break; 1951 case 0x2: 1952 printf("two MSB\n"); 1953 break; 1954 case 0x3: 1955 printf("All three bits\n"); 1956 break; 1957 } 1958 printf(" Extended Tag Field Supported: %dbit\n", 1959 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 1960 printf(" Endpoint L0 Acceptable Latency: "); 1961 pci_print_pcie_L0s_latency(PCIREG_SHIFTOUT(reg, PCIE_DCAP_L0S_LATENCY)); 1962 printf(" Endpoint L1 Acceptable Latency: "); 1963 pci_print_pcie_L1_latency(PCIREG_SHIFTOUT(reg, PCIE_DCAP_L1_LATENCY)); 1964 onoff("Attention Button Present", reg, PCIE_DCAP_ATTN_BUTTON); 1965 onoff("Attention Indicator Present", reg, PCIE_DCAP_ATTN_IND); 1966 onoff("Power Indicator Present", reg, PCIE_DCAP_PWR_IND); 1967 onoff("Role-Based Error Report", reg, PCIE_DCAP_ROLE_ERR_RPT); 1968 if (check_upstreamport) { 1969 printf(" Captured Slot Power Limit: "); 1970 pci_conf_print_pcie_power( 1971 PCIREG_SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_VAL), 1972 PCIREG_SHIFTOUT(reg, PCIE_DCAP_SLOT_PWR_LIM_SCALE)); 1973 } 1974 onoff("Function-Level Reset Capability", reg, PCIE_DCAP_FLR); 1975 1976 /* Device Control Register */ 1977 reg = regs[o2i(capoff + PCIE_DCSR)]; 1978 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 1979 onoff("Correctable Error Reporting Enable", reg, 1980 PCIE_DCSR_ENA_COR_ERR); 1981 onoff("Non Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_NFER); 1982 onoff("Fatal Error Reporting Enable", reg, PCIE_DCSR_ENA_FER); 1983 onoff("Unsupported Request Reporting Enable", reg, PCIE_DCSR_ENA_URR); 1984 onoff("Enable Relaxed Ordering", reg, PCIE_DCSR_ENA_RELAX_ORD); 1985 printf(" Max Payload Size: %d byte\n", 1986 128 << PCIREG_SHIFTOUT(reg, PCIE_DCSR_MAX_PAYLOAD)); 1987 onoff("Extended Tag Field Enable", reg, PCIE_DCSR_EXT_TAG_FIELD); 1988 onoff("Phantom Functions Enable", reg, PCIE_DCSR_PHANTOM_FUNCS); 1989 onoff("Aux Power PM Enable", reg, PCIE_DCSR_AUX_POWER_PM); 1990 onoff("Enable No Snoop", reg, PCIE_DCSR_ENA_NO_SNOOP); 1991 printf(" Max Read Request Size: %d byte\n", 1992 128 << PCIREG_SHIFTOUT(reg, PCIE_DCSR_MAX_READ_REQ)); 1993 if (pcie_devtype == PCIE_XCAP_TYPE_PCIE2PCI) 1994 onoff("Bridge Config Retry Enable", reg, 1995 PCIE_DCSR_BRDG_CFG_RETRY); 1996 1997 /* Device Status Register */ 1998 reg = regs[o2i(capoff + PCIE_DCSR)]; 1999 printf(" Device Status Register: 0x%04x\n", reg >> 16); 2000 onoff("Correctable Error Detected", reg, PCIE_DCSR_CED); 2001 onoff("Non Fatal Error Detected", reg, PCIE_DCSR_NFED); 2002 onoff("Fatal Error Detected", reg, PCIE_DCSR_FED); 2003 onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD); 2004 onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR); 2005 onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND); 2006 onoff("Emergency Power Reduction Detected", reg, PCIE_DCSR_EMGPWRREDD); 2007 2008 if (PCIE_HAS_LINKREGS(pcie_devtype)) { 2009 /* Link Capability Register */ 2010 reg = regs[o2i(capoff + PCIE_LCAP)]; 2011 printf(" Link Capabilities Register: 0x%08x\n", reg); 2012 printf(" Maximum Link Speed: "); 2013 pci_print_pcie_linkspeed(PCIE_LCAP, reg & PCIE_LCAP_MAX_SPEED); 2014 printf(" Maximum Link Width: x%u lanes\n", 2015 PCIREG_SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH)); 2016 printf(" Active State PM Support: "); 2017 switch (PCIREG_SHIFTOUT(reg, PCIE_LCAP_ASPM)) { 2018 case 0x0: 2019 printf("No ASPM support\n"); 2020 break; 2021 case 0x1: 2022 printf("L0s supported\n"); 2023 break; 2024 case 0x2: 2025 printf("L1 supported\n"); 2026 break; 2027 case 0x3: 2028 printf("L0s and L1 supported\n"); 2029 break; 2030 } 2031 printf(" L0 Exit Latency: "); 2032 pci_print_pcie_L0s_latency(PCIREG_SHIFTOUT(reg,PCIE_LCAP_L0S_EXIT)); 2033 printf(" L1 Exit Latency: "); 2034 pci_print_pcie_L1_latency(PCIREG_SHIFTOUT(reg, PCIE_LCAP_L1_EXIT)); 2035 printf(" Port Number: %u\n", 2036 PCIREG_SHIFTOUT(reg, PCIE_LCAP_PORT)); 2037 onoff("Clock Power Management", reg, PCIE_LCAP_CLOCK_PM); 2038 onoff("Surprise Down Error Report", reg, 2039 PCIE_LCAP_SURPRISE_DOWN); 2040 onoff("Data Link Layer Link Active", reg, PCIE_LCAP_DL_ACTIVE); 2041 onoff("Link BW Notification Capable", reg, 2042 PCIE_LCAP_LINK_BW_NOTIFY); 2043 onoff("ASPM Optionally Compliance", reg, 2044 PCIE_LCAP_ASPM_COMPLIANCE); 2045 2046 /* Link Control Register */ 2047 reg = regs[o2i(capoff + PCIE_LCSR)]; 2048 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 2049 printf(" Active State PM Control: "); 2050 switch (reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S)) { 2051 case 0: 2052 printf("disabled\n"); 2053 break; 2054 case 1: 2055 printf("L0s Entry Enabled\n"); 2056 break; 2057 case 2: 2058 printf("L1 Entry Enabled\n"); 2059 break; 2060 case 3: 2061 printf("L0s and L1 Entry Enabled\n"); 2062 break; 2063 } 2064 onoff2("Read Completion Boundary Control", reg, PCIE_LCSR_RCB, 2065 "128bytes", "64bytes"); 2066 onoff("Link Disable", reg, PCIE_LCSR_LINK_DIS); 2067 onoff("Retrain Link", reg, PCIE_LCSR_RETRAIN); 2068 onoff("Common Clock Configuration", reg, PCIE_LCSR_COMCLKCFG); 2069 onoff("Extended Synch", reg, PCIE_LCSR_EXTNDSYNC); 2070 onoff("Enable Clock Power Management", reg, PCIE_LCSR_ENCLKPM); 2071 onoff("Hardware Autonomous Width Disable", reg,PCIE_LCSR_HAWD); 2072 onoff("Link Bandwidth Management Interrupt Enable", reg, 2073 PCIE_LCSR_LBMIE); 2074 onoff("Link Autonomous Bandwidth Interrupt Enable", reg, 2075 PCIE_LCSR_LABIE); 2076 printf(" DRS Signaling Control: "); 2077 switch (PCIREG_SHIFTOUT(reg, PCIE_LCSR_DRSSGNL)) { 2078 case 0: 2079 printf("not reported\n"); 2080 break; 2081 case 1: 2082 printf("Interrupt Enabled\n"); 2083 break; 2084 case 2: 2085 printf("DRS to FRS Signaling Enabled\n"); 2086 break; 2087 default: 2088 printf("reserved\n"); 2089 break; 2090 } 2091 2092 /* Link Status Register */ 2093 reg = regs[o2i(capoff + PCIE_LCSR)]; 2094 printf(" Link Status Register: 0x%04x\n", reg >> 16); 2095 printf(" Negotiated Link Speed: "); 2096 pci_print_pcie_linkspeed(PCIE_LCSR, 2097 PCIREG_SHIFTOUT(reg, PCIE_LCSR_LINKSPEED)); 2098 printf(" Negotiated Link Width: x%u lanes\n", 2099 PCIREG_SHIFTOUT(reg, PCIE_LCSR_NLW)); 2100 onoff("Training Error", reg, PCIE_LCSR_LINKTRAIN_ERR); 2101 onoff("Link Training", reg, PCIE_LCSR_LINKTRAIN); 2102 onoff("Slot Clock Configuration", reg, PCIE_LCSR_SLOTCLKCFG); 2103 onoff("Data Link Layer Link Active", reg, PCIE_LCSR_DLACTIVE); 2104 onoff("Link Bandwidth Management Status", reg, 2105 PCIE_LCSR_LINK_BW_MGMT); 2106 onoff("Link Autonomous Bandwidth Status", reg, 2107 PCIE_LCSR_LINK_AUTO_BW); 2108 } 2109 2110 if (check_slot == true) { 2111 pcireg_t slcap; 2112 2113 /* Slot Capability Register */ 2114 slcap = reg = regs[o2i(capoff + PCIE_SLCAP)]; 2115 printf(" Slot Capability Register: 0x%08x\n", reg); 2116 onoff("Attention Button Present", reg, PCIE_SLCAP_ABP); 2117 onoff("Power Controller Present", reg, PCIE_SLCAP_PCP); 2118 onoff("MRL Sensor Present", reg, PCIE_SLCAP_MSP); 2119 onoff("Attention Indicator Present", reg, PCIE_SLCAP_AIP); 2120 onoff("Power Indicator Present", reg, PCIE_SLCAP_PIP); 2121 onoff("Hot-Plug Surprise", reg, PCIE_SLCAP_HPS); 2122 onoff("Hot-Plug Capable", reg, PCIE_SLCAP_HPC); 2123 printf(" Slot Power Limit Value: "); 2124 pci_conf_print_pcie_power(PCIREG_SHIFTOUT(reg, PCIE_SLCAP_SPLV), 2125 PCIREG_SHIFTOUT(reg, PCIE_SLCAP_SPLS)); 2126 onoff("Electromechanical Interlock Present", reg, 2127 PCIE_SLCAP_EIP); 2128 onoff("No Command Completed Support", reg, PCIE_SLCAP_NCCS); 2129 printf(" Physical Slot Number: %d\n", 2130 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 2131 2132 /* Slot Control Register */ 2133 reg = regs[o2i(capoff + PCIE_SLCSR)]; 2134 printf(" Slot Control Register: 0x%04x\n", reg & 0xffff); 2135 onoff("Attention Button Pressed Enabled", reg, PCIE_SLCSR_ABE); 2136 onoff("Power Fault Detected Enabled", reg, PCIE_SLCSR_PFE); 2137 onoff("MRL Sensor Changed Enabled", reg, PCIE_SLCSR_MSE); 2138 onoff("Presence Detect Changed Enabled", reg, PCIE_SLCSR_PDE); 2139 onoff("Command Completed Interrupt Enabled", reg, 2140 PCIE_SLCSR_CCE); 2141 onoff("Hot-Plug Interrupt Enabled", reg, PCIE_SLCSR_HPE); 2142 /* 2143 * For Attention Indicator Control and Power Indicator Control, 2144 * it's allowed to be a read only value 0 if corresponding 2145 * capability register bit is 0. 2146 */ 2147 if (slcap & PCIE_SLCAP_AIP) { 2148 printf(" Attention Indicator Control: "); 2149 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 2150 case 0x0: 2151 printf("reserved\n"); 2152 break; 2153 case PCIE_SLCSR_IND_ON: 2154 printf("on\n"); 2155 break; 2156 case PCIE_SLCSR_IND_BLINK: 2157 printf("blink\n"); 2158 break; 2159 case PCIE_SLCSR_IND_OFF: 2160 printf("off\n"); 2161 break; 2162 } 2163 } 2164 if (slcap & PCIE_SLCAP_PIP) { 2165 printf(" Power Indicator Control: "); 2166 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 2167 case 0x0: 2168 printf("reserved\n"); 2169 break; 2170 case PCIE_SLCSR_IND_ON: 2171 printf("on\n"); 2172 break; 2173 case PCIE_SLCSR_IND_BLINK: 2174 printf("blink\n"); 2175 break; 2176 case PCIE_SLCSR_IND_OFF: 2177 printf("off\n"); 2178 break; 2179 } 2180 } 2181 printf(" Power Controller Control: Power %s\n", 2182 reg & PCIE_SLCSR_PCC ? "off" : "on"); 2183 onoff("Electromechanical Interlock Control", 2184 reg, PCIE_SLCSR_EIC); 2185 onoff("Data Link Layer State Changed Enable", reg, 2186 PCIE_SLCSR_DLLSCE); 2187 onoff("Auto Slot Power Limit Disable", reg, 2188 PCIE_SLCSR_AUTOSPLDIS); 2189 2190 /* Slot Status Register */ 2191 printf(" Slot Status Register: 0x%04x\n", reg >> 16); 2192 onoff("Attention Button Pressed", reg, PCIE_SLCSR_ABP); 2193 onoff("Power Fault Detected", reg, PCIE_SLCSR_PFD); 2194 onoff("MRL Sensor Changed", reg, PCIE_SLCSR_MSC); 2195 onoff("Presence Detect Changed", reg, PCIE_SLCSR_PDC); 2196 onoff("Command Completed", reg, PCIE_SLCSR_CC); 2197 onoff("MRL Open", reg, PCIE_SLCSR_MS); 2198 onoff("Card Present in slot", reg, PCIE_SLCSR_PDS); 2199 onoff("Electromechanical Interlock engaged", reg, 2200 PCIE_SLCSR_EIS); 2201 onoff("Data Link Layer State Changed", reg, PCIE_SLCSR_LACS); 2202 } 2203 2204 if (PCIE_HAS_ROOTREGS(pcie_devtype)) { 2205 /* Root Control Register */ 2206 reg = regs[o2i(capoff + PCIE_RCR)]; 2207 printf(" Root Control Register: 0x%04x\n", reg & 0xffff); 2208 onoff("SERR on Correctable Error Enable", reg, 2209 PCIE_RCR_SERR_CER); 2210 onoff("SERR on Non-Fatal Error Enable", reg, 2211 PCIE_RCR_SERR_NFER); 2212 onoff("SERR on Fatal Error Enable", reg, PCIE_RCR_SERR_FER); 2213 onoff("PME Interrupt Enable", reg, PCIE_RCR_PME_IE); 2214 onoff("CRS Software Visibility Enable", reg, PCIE_RCR_CRS_SVE); 2215 2216 /* Root Capability Register */ 2217 printf(" Root Capability Register: 0x%04x\n", 2218 reg >> 16); 2219 onoff("CRS Software Visibility", reg, PCIE_RCR_CRS_SV); 2220 2221 /* Root Status Register */ 2222 reg = regs[o2i(capoff + PCIE_RSR)]; 2223 printf(" Root Status Register: 0x%08x\n", reg); 2224 printf(" PME Requester ID: 0x%04x\n", 2225 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 2226 onoff("PME was asserted", reg, PCIE_RSR_PME_STAT); 2227 onoff("another PME is pending", reg, PCIE_RSR_PME_PEND); 2228 } 2229 2230 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2231 if (pciever < 2) 2232 return; 2233 2234 /* Device Capabilities 2 */ 2235 reg = regs[o2i(capoff + PCIE_DCAP2)]; 2236 printf(" Device Capabilities 2: 0x%08x\n", reg); 2237 printf(" Completion Timeout Ranges Supported: "); 2238 val = reg & PCIE_DCAP2_COMPT_RANGE; 2239 switch (val) { 2240 case 0: 2241 printf("not supported\n"); 2242 break; 2243 default: 2244 for (i = 0; i <= 3; i++) { 2245 if (((val >> i) & 0x01) != 0) 2246 printf("%c", 'A' + i); 2247 } 2248 printf("\n"); 2249 } 2250 onoff("Completion Timeout Disable Supported", reg, 2251 PCIE_DCAP2_COMPT_DIS); 2252 onoff("ARI Forwarding Supported", reg, PCIE_DCAP2_ARI_FWD); 2253 onoff("AtomicOp Routing Supported", reg, PCIE_DCAP2_ATOM_ROUT); 2254 onoff("32bit AtomicOp Completer Supported", reg, PCIE_DCAP2_32ATOM); 2255 onoff("64bit AtomicOp Completer Supported", reg, PCIE_DCAP2_64ATOM); 2256 onoff("128-bit CAS Completer Supported", reg, PCIE_DCAP2_128CAS); 2257 onoff("No RO-enabled PR-PR passing", reg, PCIE_DCAP2_NO_ROPR_PASS); 2258 onoff("LTR Mechanism Supported", reg, PCIE_DCAP2_LTR_MEC); 2259 printf(" TPH Completer Supported: "); 2260 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_TPH_COMP)) { 2261 case 0: 2262 printf("Not supported\n"); 2263 break; 2264 case 1: 2265 printf("TPH\n"); 2266 break; 2267 case 3: 2268 printf("TPH and Extended TPH\n"); 2269 break; 2270 default: 2271 printf("(reserved value)\n"); 2272 break; 2273 } 2274 printf(" LN System CLS: "); 2275 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) { 2276 case 0x0: 2277 printf("Not supported or not in effect\n"); 2278 break; 2279 case 0x1: 2280 printf("64byte cachelines in effect\n"); 2281 break; 2282 case 0x2: 2283 printf("128byte cachelines in effect\n"); 2284 break; 2285 case 0x3: 2286 printf("Reserved\n"); 2287 break; 2288 } 2289 onoff("10-bit Tag Completer Supported", reg, PCIE_DCAP2_TBT_COMP); 2290 onoff("10-bit Tag Requester Supported", reg, PCIE_DCAP2_TBT_REQ); 2291 printf(" OBFF Supported: "); 2292 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_OBFF)) { 2293 case 0x0: 2294 printf("Not supported\n"); 2295 break; 2296 case 0x1: 2297 printf("Message only\n"); 2298 break; 2299 case 0x2: 2300 printf("WAKE# only\n"); 2301 break; 2302 case 0x3: 2303 printf("Both\n"); 2304 break; 2305 } 2306 onoff("Extended Fmt Field Supported", reg, PCIE_DCAP2_EXTFMT_FLD); 2307 onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF); 2308 val = PCIREG_SHIFTOUT(reg, PCIE_DCAP2_MAX_EETLP); 2309 printf(" Max End-End TLP Prefixes: %u\n", (val == 0) ? 4 : val); 2310 printf(" Emergency Power Reduction Supported: "); 2311 switch (PCIREG_SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) { 2312 case 0x0: 2313 printf("Not supported\n"); 2314 break; 2315 case 0x1: 2316 printf("Device Specific mechanism\n"); 2317 break; 2318 case 0x2: 2319 printf("Form Factor spec or Device Specific mechanism\n"); 2320 break; 2321 case 0x3: 2322 printf("Reserved\n"); 2323 break; 2324 } 2325 onoff("Emergency Power Reduction Initialization Required", reg, 2326 PCIE_DCAP2_EMGPWRRED_INI); 2327 onoff("FRS Supported", reg, PCIE_DCAP2_FRS); 2328 2329 /* Device Control 2 */ 2330 reg = regs[o2i(capoff + PCIE_DCSR2)]; 2331 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 2332 printf(" Completion Timeout Value: "); 2333 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 2334 onoff("Completion Timeout Disabled", reg, PCIE_DCSR2_COMPT_DIS); 2335 onoff("ARI Forwarding Enabled", reg, PCIE_DCSR2_ARI_FWD); 2336 onoff("AtomicOp Requester Enabled", reg, PCIE_DCSR2_ATOM_REQ); 2337 onoff("AtomicOp Egress Blocking", reg, PCIE_DCSR2_ATOM_EBLK); 2338 onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ); 2339 onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP); 2340 onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC); 2341 onoff("Emergency Power Reduction Request", reg, 2342 PCIE_DCSR2_EMGPWRRED_REQ); 2343 onoff("10-bit Tag Requester Enabled", reg, PCIE_DCSR2_TBT_REQ); 2344 printf(" OBFF: "); 2345 switch (PCIREG_SHIFTOUT(reg, PCIE_DCSR2_OBFF_EN)) { 2346 case 0x0: 2347 printf("Disabled\n"); 2348 break; 2349 case 0x1: 2350 printf("Enabled with Message Signaling Variation A\n"); 2351 break; 2352 case 0x2: 2353 printf("Enabled with Message Signaling Variation B\n"); 2354 break; 2355 case 0x3: 2356 printf("Enabled using WAKE# signaling\n"); 2357 break; 2358 } 2359 onoff("End-End TLP Prefix Blocking on", reg, PCIE_DCSR2_EETLP); 2360 2361 if (PCIE_HAS_LINKREGS(pcie_devtype)) { 2362 bool drs_supported = false; 2363 2364 /* Link Capability 2 */ 2365 reg = regs[o2i(capoff + PCIE_LCAP2)]; 2366 /* If the vector is 0, LCAP2 is not implemented */ 2367 if ((reg & PCIE_LCAP2_SUP_LNKSV) != 0) { 2368 printf(" Link Capabilities 2: 0x%08x\n", reg); 2369 printf(" Supported Link Speeds Vector:"); 2370 pci_print_pcie_linkspeedvector( 2371 PCIREG_SHIFTOUT(reg, PCIE_LCAP2_SUP_LNKSV)); 2372 printf("\n"); 2373 onoff("Crosslink Supported", reg, PCIE_LCAP2_CROSSLNK); 2374 printf(" " 2375 "Lower SKP OS Generation Supported Speed Vector:"); 2376 pci_print_pcie_linkspeedvector( 2377 PCIREG_SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_GENSUPPSV)); 2378 printf("\n"); 2379 printf(" " 2380 "Lower SKP OS Reception Supported Speed Vector:"); 2381 pci_print_pcie_linkspeedvector( 2382 PCIREG_SHIFTOUT(reg, PCIE_LCAP2_LOWSKPOS_RECSUPPSV)); 2383 printf("\n"); 2384 onoff("Retimer Presence Detect Supported", reg, 2385 PCIE_LCAP2_RETIMERPD); 2386 onoff("DRS Supported", reg, PCIE_LCAP2_DRS); 2387 drs_supported = (reg & PCIE_LCAP2_DRS) ? true : false; 2388 } 2389 2390 /* Link Control 2 */ 2391 reg = regs[o2i(capoff + PCIE_LCSR2)]; 2392 /* If the vector is 0, LCAP2 is not implemented */ 2393 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 2394 printf(" Target Link Speed: "); 2395 pci_print_pcie_linkspeed(PCIE_LCSR2, 2396 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_TGT_LSPEED)); 2397 onoff("Enter Compliance Enabled", reg, PCIE_LCSR2_ENT_COMPL); 2398 onoff("HW Autonomous Speed Disabled", reg, 2399 PCIE_LCSR2_HW_AS_DIS); 2400 printf(" Selectable De-emphasis: "); 2401 pci_print_pcie_link_deemphasis( 2402 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_SEL_DEEMP)); 2403 printf("\n"); 2404 printf(" Transmit Margin: %u\n", 2405 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_TX_MARGIN)); 2406 onoff("Enter Modified Compliance", reg, PCIE_LCSR2_EN_MCOMP); 2407 onoff("Compliance SOS", reg, PCIE_LCSR2_COMP_SOS); 2408 printf(" Compliance Preset/De-emphasis: "); 2409 pci_print_pcie_link_preset_preshoot_deemphasis( 2410 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_COMP_DEEMP)); 2411 printf("\n"); 2412 2413 /* Link Status 2 */ 2414 printf(" Link Status 2: 0x%04x\n", (reg >> 16) & 0xffff); 2415 printf(" Current De-emphasis Level: "); 2416 pci_print_pcie_link_deemphasis( 2417 PCIREG_SHIFTOUT(reg, PCIE_LCSR2_DEEMP_LVL)); 2418 printf("\n"); 2419 onoff("Equalization Complete", reg, PCIE_LCSR2_EQ_COMPL); 2420 onoff("Equalization Phase 1 Successful", reg, 2421 PCIE_LCSR2_EQP1_SUC); 2422 onoff("Equalization Phase 2 Successful", reg, 2423 PCIE_LCSR2_EQP2_SUC); 2424 onoff("Equalization Phase 3 Successful", reg, 2425 PCIE_LCSR2_EQP3_SUC); 2426 onoff("Link Equalization Request", reg, PCIE_LCSR2_LNKEQ_REQ); 2427 onoff("Retimer Presence Detected", reg, PCIE_LCSR2_RETIMERPD); 2428 if (drs_supported) { 2429 printf(" Downstream Component Presence: "); 2430 switch (PCIREG_SHIFTOUT(reg, PCIE_LCSR2_DSCOMPN)) { 2431 case PCIE_DSCOMPN_DOWN_NOTDETERM: 2432 printf("Link Down - Presence Not" 2433 " Determined\n"); 2434 break; 2435 case PCIE_DSCOMPN_DOWN_NOTPRES: 2436 printf("Link Down - Component Not Present\n"); 2437 break; 2438 case PCIE_DSCOMPN_DOWN_PRES: 2439 printf("Link Down - Component Present\n"); 2440 break; 2441 case PCIE_DSCOMPN_UP_PRES: 2442 printf("Link Up - Component Present\n"); 2443 break; 2444 case PCIE_DSCOMPN_UP_PRES_DRS: 2445 printf("Link Up - Component Present and DRS" 2446 " received\n"); 2447 break; 2448 default: 2449 printf("reserved\n"); 2450 break; 2451 } 2452 onoff("DRS Message Received", reg, PCIE_LCSR2_DRSRCV); 2453 } 2454 } 2455 2456 /* Slot Capability 2 */ 2457 /* Slot Control 2 */ 2458 /* Slot Status 2 */ 2459 } 2460 2461 static void 2462 pci_conf_print_msix_cap(const pcireg_t *regs, int capoff) 2463 { 2464 pcireg_t reg; 2465 2466 printf("\n MSI-X Capability Register\n"); 2467 2468 reg = regs[o2i(capoff + PCI_MSIX_CTL)]; 2469 printf(" Message Control register: 0x%04x\n", 2470 (reg >> 16) & 0xff); 2471 printf(" Table Size: %d\n", PCI_MSIX_CTL_TBLSIZE(reg)); 2472 onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK); 2473 onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE); 2474 reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)]; 2475 printf(" Table offset register: 0x%08x\n", reg); 2476 printf(" Table offset: 0x%08x\n", 2477 (pcireg_t)(reg & PCI_MSIX_TBLOFFSET_MASK)); 2478 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_TBLBIR_MASK)); 2479 reg = regs[o2i(capoff + PCI_MSIX_PBAOFFSET)]; 2480 printf(" Pending bit array register: 0x%08x\n", reg); 2481 printf(" Pending bit array offset: 0x%08x\n", 2482 (pcireg_t)(reg & PCI_MSIX_PBAOFFSET_MASK)); 2483 printf(" BIR: 0x%x\n", (pcireg_t)(reg & PCI_MSIX_PBABIR_MASK)); 2484 } 2485 2486 static void 2487 pci_conf_print_sata_cap(const pcireg_t *regs, int capoff) 2488 { 2489 pcireg_t reg; 2490 2491 printf("\n Serial ATA Capability Register\n"); 2492 2493 reg = regs[o2i(capoff + PCI_SATA_REV)]; 2494 printf(" Revision register: 0x%04x\n", (reg >> 16) & 0xff); 2495 printf(" Revision: %u.%u\n", 2496 PCIREG_SHIFTOUT(reg, PCI_SATA_REV_MAJOR), 2497 PCIREG_SHIFTOUT(reg, PCI_SATA_REV_MINOR)); 2498 2499 reg = regs[o2i(capoff + PCI_SATA_BAR)]; 2500 2501 printf(" BAR Register: 0x%08x\n", reg); 2502 printf(" Register location: "); 2503 if ((reg & PCI_SATA_BAR_SPEC) == PCI_SATA_BAR_INCONF) 2504 printf("in config space\n"); 2505 else { 2506 printf("BAR %d\n", (int)PCI_SATA_BAR_NUM(reg)); 2507 printf(" BAR offset: 0x%08x\n", 2508 PCIREG_SHIFTOUT(reg, PCI_SATA_BAR_OFFSET) * 4); 2509 } 2510 } 2511 2512 static void 2513 pci_conf_print_pciaf_cap(const pcireg_t *regs, int capoff) 2514 { 2515 pcireg_t reg; 2516 2517 printf("\n Advanced Features Capability Register\n"); 2518 2519 reg = regs[o2i(capoff + PCI_AFCAPR)]; 2520 printf(" AF Capabilities register: 0x%02x\n", (reg >> 24) & 0xff); 2521 printf(" AF Structure Length: 0x%02x\n", 2522 PCIREG_SHIFTOUT(reg, PCI_AF_LENGTH)); 2523 onoff("Transaction Pending", reg, PCI_AF_TP_CAP); 2524 onoff("Function Level Reset", reg, PCI_AF_FLR_CAP); 2525 reg = regs[o2i(capoff + PCI_AFCSR)]; 2526 printf(" AF Control register: 0x%02x\n", reg & 0xff); 2527 /* 2528 * Only PCI_AFCR_INITIATE_FLR is a member of the AF control register 2529 * and it's always 0 on read 2530 */ 2531 printf(" AF Status register: 0x%02x\n", (reg >> 8) & 0xff); 2532 onoff("Transaction Pending", reg, PCI_AFSR_TP); 2533 } 2534 2535 static void 2536 pci_conf_print_ea_cap_prop(unsigned int prop) 2537 { 2538 2539 switch (prop) { 2540 case PCI_EA_PROP_MEM_NONPREF: 2541 printf("Memory Space, Non-Prefetchable\n"); 2542 break; 2543 case PCI_EA_PROP_MEM_PREF: 2544 printf("Memory Space, Prefetchable\n"); 2545 break; 2546 case PCI_EA_PROP_IO: 2547 printf("I/O Space\n"); 2548 break; 2549 case PCI_EA_PROP_VF_MEM_NONPREF: 2550 printf("Resorce for VF use, Memory Space, Non-Prefetchable\n"); 2551 break; 2552 case PCI_EA_PROP_VF_MEM_PREF: 2553 printf("Resorce for VF use, Memory Space, Prefetch\n"); 2554 break; 2555 case PCI_EA_PROP_BB_MEM_NONPREF: 2556 printf("Behind the Bridge, Memory Space, Non-Pref\n"); 2557 break; 2558 case PCI_EA_PROP_BB_MEM_PREF: 2559 printf("Behind the Bridge, Memory Space. Prefetchable\n"); 2560 break; 2561 case PCI_EA_PROP_BB_IO: 2562 printf("Behind Bridge, I/O Space\n"); 2563 break; 2564 case PCI_EA_PROP_MEM_UNAVAIL: 2565 printf("Memory Space Unavailable\n"); 2566 break; 2567 case PCI_EA_PROP_IO_UNAVAIL: 2568 printf("IO Space Unavailable\n"); 2569 break; 2570 case PCI_EA_PROP_UNAVAIL: 2571 printf("Entry Unavailable for use\n"); 2572 break; 2573 default: 2574 printf("Reserved\n"); 2575 break; 2576 } 2577 } 2578 2579 static void 2580 pci_conf_print_ea_cap(const pcireg_t *regs, int capoff) 2581 { 2582 pcireg_t reg, reg2; 2583 unsigned int entries, entoff, i; 2584 2585 printf("\n Enhanced Allocation Capability Register\n"); 2586 2587 reg = regs[o2i(capoff + PCI_EA_CAP1)]; 2588 printf(" EA Num Entries register: 0x%04x\n", reg >> 16); 2589 entries = PCIREG_SHIFTOUT(reg, PCI_EA_CAP1_NUMENTRIES); 2590 printf(" EA Num Entries: %u\n", entries); 2591 2592 /* Type 1 only */ 2593 if (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) == PCI_HDRTYPE_PPB) { 2594 reg = regs[o2i(capoff + PCI_EA_CAP2)]; 2595 printf(" EA Capability Second register: 0x%08x\n", reg); 2596 printf(" Fixed Secondary Bus Number: %hhu\n", 2597 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_EA_CAP2_SECONDARY)); 2598 printf(" Fixed Subordinate Bus Number: %hhu\n", 2599 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_EA_CAP2_SUBORDINATE)); 2600 entoff = capoff + 8; 2601 } else 2602 entoff = capoff + 4; 2603 2604 for (i = 0; i < entries; i++) { 2605 uint64_t base, offset; 2606 bool baseis64, offsetis64; 2607 unsigned int bei, entry_size; 2608 2609 printf(" Entry %u:\n", i); 2610 /* The first DW */ 2611 reg = regs[o2i(entoff)]; 2612 printf(" The first register: 0x%08x\n", reg); 2613 entry_size = PCIREG_SHIFTOUT(reg, PCI_EA_ES); 2614 printf(" Entry size: %u\n", entry_size); 2615 printf(" BAR Equivalent Indicator: "); 2616 bei = PCIREG_SHIFTOUT(reg, PCI_EA_BEI); 2617 switch (bei) { 2618 case PCI_EA_BEI_BAR0: 2619 case PCI_EA_BEI_BAR1: 2620 case PCI_EA_BEI_BAR2: 2621 case PCI_EA_BEI_BAR3: 2622 case PCI_EA_BEI_BAR4: 2623 case PCI_EA_BEI_BAR5: 2624 printf("BAR %u\n", bei - PCI_EA_BEI_BAR0); 2625 break; 2626 case PCI_EA_BEI_BEHIND: 2627 printf("Behind the function\n"); 2628 break; 2629 case PCI_EA_BEI_NOTIND: 2630 printf("Not Indicated\n"); 2631 break; 2632 case PCI_EA_BEI_EXPROM: 2633 printf("Expansion ROM\n"); 2634 break; 2635 case PCI_EA_BEI_VFBAR0: 2636 case PCI_EA_BEI_VFBAR1: 2637 case PCI_EA_BEI_VFBAR2: 2638 case PCI_EA_BEI_VFBAR3: 2639 case PCI_EA_BEI_VFBAR4: 2640 case PCI_EA_BEI_VFBAR5: 2641 printf("VF BAR %u\n", bei - PCI_EA_BEI_VFBAR0); 2642 break; 2643 case PCI_EA_BEI_RESERVED: 2644 default: 2645 printf("Reserved\n"); 2646 break; 2647 } 2648 2649 printf(" Primary Properties: "); 2650 pci_conf_print_ea_cap_prop(PCIREG_SHIFTOUT(reg, PCI_EA_PP)); 2651 printf(" Secondary Properties: "); 2652 pci_conf_print_ea_cap_prop(PCIREG_SHIFTOUT(reg, PCI_EA_SP)); 2653 onoff("Writable", reg, PCI_EA_W); 2654 onoff("Enable for this entry", reg, PCI_EA_E); 2655 2656 if (entry_size == 0) { 2657 entoff += 4; 2658 continue; 2659 } 2660 2661 /* Base addr */ 2662 reg = regs[o2i(entoff + 4)]; 2663 base = reg & PCI_EA_LOWMASK; 2664 baseis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT; 2665 printf(" Base Address Register Low: 0x%08x\n", reg); 2666 if (baseis64) { 2667 /* 64bit */ 2668 reg2 = regs[o2i(entoff + 12)]; 2669 printf(" Base Address Register high: 0x%08x\n", 2670 reg2); 2671 base |= (uint64_t)reg2 << 32; 2672 } 2673 2674 /* Offset addr */ 2675 reg = regs[o2i(entoff + 8)]; 2676 offset = reg & PCI_EA_LOWMASK; 2677 offsetis64 = reg & PCI_EA_BASEMAXOFFSET_64BIT; 2678 printf(" Max Offset Register Low: 0x%08x\n", reg); 2679 if (offsetis64) { 2680 /* 64bit */ 2681 reg2 = regs[o2i(entoff + (baseis64 ? 16 : 12))]; 2682 printf(" Max Offset Register high: 0x%08x\n", 2683 reg2); 2684 offset |= (uint64_t)reg2 << 32; 2685 } 2686 2687 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 2688 "\n", base, base + offset); 2689 2690 entoff += 4 + (4 * entry_size); 2691 } 2692 } 2693 2694 /* XXX pci_conf_print_fpb_cap */ 2695 2696 static struct { 2697 pcireg_t cap; 2698 const char *name; 2699 void (*printfunc)(const pcireg_t *, int); 2700 } pci_captab[] = { 2701 { PCI_CAP_RESERVED0, "reserved", NULL }, 2702 { PCI_CAP_PWRMGMT, "Power Management", pci_conf_print_pcipm_cap }, 2703 { PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap }, 2704 { PCI_CAP_VPD, "VPD", NULL }, 2705 { PCI_CAP_SLOTID, "SlotID", NULL }, 2706 { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap }, 2707 { PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL }, 2708 { PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap }, 2709 { PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap }, 2710 { PCI_CAP_VENDSPEC, "Vendor-specific", 2711 pci_conf_print_vendspec_cap }, 2712 { PCI_CAP_DEBUGPORT, "Debug Port", pci_conf_print_debugport_cap }, 2713 { PCI_CAP_CPCI_RSRCCTL, "CompactPCI Resource Control", NULL }, 2714 { PCI_CAP_HOTPLUG, "Hot-Plug", NULL }, 2715 { PCI_CAP_SUBVENDOR, "Subsystem vendor ID", 2716 pci_conf_print_subsystem_cap }, 2717 { PCI_CAP_AGP8, "AGP 8x", NULL }, 2718 { PCI_CAP_SECURE, "Secure Device", pci_conf_print_secure_cap }, 2719 { PCI_CAP_PCIEXPRESS, "PCI Express", pci_conf_print_pcie_cap }, 2720 { PCI_CAP_MSIX, "MSI-X", pci_conf_print_msix_cap }, 2721 { PCI_CAP_SATA, "SATA", pci_conf_print_sata_cap }, 2722 { PCI_CAP_PCIAF, "Advanced Features", pci_conf_print_pciaf_cap}, 2723 { PCI_CAP_EA, "Enhanced Allocation", pci_conf_print_ea_cap }, 2724 { PCI_CAP_FPB, "Flattening Portal Bridge", NULL } 2725 }; 2726 2727 static int 2728 pci_conf_find_cap(const pcireg_t *regs, unsigned int capid, int *offsetp) 2729 { 2730 pcireg_t rval; 2731 unsigned int capptr; 2732 int off; 2733 2734 if (!(regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT)) 2735 return 0; 2736 2737 /* Determine the Capability List Pointer register to start with. */ 2738 switch (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)])) { 2739 case 0: /* standard device header */ 2740 case 1: /* PCI-PCI bridge header */ 2741 capptr = PCI_CAPLISTPTR_REG; 2742 break; 2743 case 2: /* PCI-CardBus Bridge header */ 2744 capptr = PCI_CARDBUS_CAPLISTPTR_REG; 2745 break; 2746 default: 2747 return 0; 2748 } 2749 2750 for (off = PCI_CAPLIST_PTR(regs[o2i(capptr)]); 2751 off != 0; off = PCI_CAPLIST_NEXT(rval)) { 2752 rval = regs[o2i(off)]; 2753 if (capid == PCI_CAPLIST_CAP(rval)) { 2754 if (offsetp != NULL) 2755 *offsetp = off; 2756 return 1; 2757 } 2758 } 2759 return 0; 2760 } 2761 2762 static void 2763 pci_conf_print_caplist( 2764 #ifdef _KERNEL 2765 pci_chipset_tag_t pc, pcitag_t tag, 2766 #endif 2767 const pcireg_t *regs, int capoff) 2768 { 2769 int off; 2770 pcireg_t foundcap; 2771 pcireg_t rval; 2772 bool foundtable[__arraycount(pci_captab)]; 2773 unsigned int i; 2774 2775 /* Clear table */ 2776 for (i = 0; i < __arraycount(pci_captab); i++) 2777 foundtable[i] = false; 2778 2779 /* Print capability register's offset and the type first */ 2780 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2781 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2782 rval = regs[o2i(off)]; 2783 printf(" Capability register at 0x%02x\n", off); 2784 2785 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 2786 foundcap = PCI_CAPLIST_CAP(rval); 2787 if (foundcap < __arraycount(pci_captab)) { 2788 printf("%s)\n", pci_captab[foundcap].name); 2789 /* Mark as found */ 2790 foundtable[foundcap] = true; 2791 } else 2792 printf("unknown)\n"); 2793 } 2794 2795 /* 2796 * And then, print the detail of each capability registers 2797 * in capability value's order. 2798 */ 2799 for (i = 0; i < __arraycount(pci_captab); i++) { 2800 if (foundtable[i] == false) 2801 continue; 2802 2803 /* 2804 * The type was found. Search capability list again and 2805 * print all capabilities that the capability type is 2806 * the same. This is required because some capabilities 2807 * appear multiple times (e.g. HyperTransport capability). 2808 */ 2809 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 2810 off != 0; off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 2811 rval = regs[o2i(off)]; 2812 if ((PCI_CAPLIST_CAP(rval) == i) 2813 && (pci_captab[i].printfunc != NULL)) 2814 pci_captab[i].printfunc(regs, off); 2815 } 2816 } 2817 } 2818 2819 /* Extended Capability */ 2820 2821 static void 2822 pci_conf_print_aer_cap_uc(pcireg_t reg) 2823 { 2824 2825 onoff("Undefined", reg, PCI_AER_UC_UNDEFINED); 2826 onoff("Data Link Protocol Error", reg, PCI_AER_UC_DL_PROTOCOL_ERROR); 2827 onoff("Surprise Down Error", reg, PCI_AER_UC_SURPRISE_DOWN_ERROR); 2828 onoff("Poisoned TLP Received", reg, PCI_AER_UC_POISONED_TLP); 2829 onoff("Flow Control Protocol Error", reg, PCI_AER_UC_FC_PROTOCOL_ERROR); 2830 onoff("Completion Timeout", reg, PCI_AER_UC_COMPLETION_TIMEOUT); 2831 onoff("Completer Abort", reg, PCI_AER_UC_COMPLETER_ABORT); 2832 onoff("Unexpected Completion", reg, PCI_AER_UC_UNEXPECTED_COMPLETION); 2833 onoff("Receiver Overflow", reg, PCI_AER_UC_RECEIVER_OVERFLOW); 2834 onoff("Malformed TLP", reg, PCI_AER_UC_MALFORMED_TLP); 2835 onoff("ECRC Error", reg, PCI_AER_UC_ECRC_ERROR); 2836 onoff("Unsupported Request Error", reg, 2837 PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR); 2838 onoff("ACS Violation", reg, PCI_AER_UC_ACS_VIOLATION); 2839 onoff("Uncorrectable Internal Error", reg, PCI_AER_UC_INTERNAL_ERROR); 2840 onoff("MC Blocked TLP", reg, PCI_AER_UC_MC_BLOCKED_TLP); 2841 onoff("AtomicOp Egress BLK", reg, PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED); 2842 onoff("TLP Prefix Blocked Error", reg, 2843 PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR); 2844 onoff("Poisoned TLP Egress Blocked", reg, 2845 PCI_AER_UC_POISONTLP_EGRESS_BLOCKED); 2846 } 2847 2848 static void 2849 pci_conf_print_aer_cap_cor(pcireg_t reg) 2850 { 2851 2852 onoff("Receiver Error", reg, PCI_AER_COR_RECEIVER_ERROR); 2853 onoff("Bad TLP", reg, PCI_AER_COR_BAD_TLP); 2854 onoff("Bad DLLP", reg, PCI_AER_COR_BAD_DLLP); 2855 onoff("REPLAY_NUM Rollover", reg, PCI_AER_COR_REPLAY_NUM_ROLLOVER); 2856 onoff("Replay Timer Timeout", reg, PCI_AER_COR_REPLAY_TIMER_TIMEOUT); 2857 onoff("Advisory Non-Fatal Error", reg, PCI_AER_COR_ADVISORY_NF_ERROR); 2858 onoff("Corrected Internal Error", reg, PCI_AER_COR_INTERNAL_ERROR); 2859 onoff("Header Log Overflow", reg, PCI_AER_COR_HEADER_LOG_OVERFLOW); 2860 } 2861 2862 static void 2863 pci_conf_print_aer_cap_control(pcireg_t reg, bool *tlp_prefix_log) 2864 { 2865 2866 printf(" First Error Pointer: 0x%04x\n", 2867 PCIREG_SHIFTOUT(reg, PCI_AER_FIRST_ERROR_PTR)); 2868 onoff("ECRC Generation Capable", reg, PCI_AER_ECRC_GEN_CAPABLE); 2869 onoff("ECRC Generation Enable", reg, PCI_AER_ECRC_GEN_ENABLE); 2870 onoff("ECRC Check Capable", reg, PCI_AER_ECRC_CHECK_CAPABLE); 2871 onoff("ECRC Check Enable", reg, PCI_AER_ECRC_CHECK_ENABLE); 2872 onoff("Multiple Header Recording Capable", reg, 2873 PCI_AER_MULT_HDR_CAPABLE); 2874 onoff("Multiple Header Recording Enable", reg,PCI_AER_MULT_HDR_ENABLE); 2875 onoff("Completion Timeout Prefix/Header Log Capable", reg, 2876 PCI_AER_COMPTOUTPRFXHDRLOG_CAP); 2877 2878 /* This bit is RsvdP if the End-End TLP Prefix Supported bit is Clear */ 2879 if (!tlp_prefix_log) 2880 return; 2881 onoff("TLP Prefix Log Present", reg, PCI_AER_TLP_PREFIX_LOG_PRESENT); 2882 *tlp_prefix_log = (reg & PCI_AER_TLP_PREFIX_LOG_PRESENT) ? true : false; 2883 } 2884 2885 static void 2886 pci_conf_print_aer_cap_rooterr_cmd(pcireg_t reg) 2887 { 2888 2889 onoff("Correctable Error Reporting Enable", reg, 2890 PCI_AER_ROOTERR_COR_ENABLE); 2891 onoff("Non-Fatal Error Reporting Enable", reg, 2892 PCI_AER_ROOTERR_NF_ENABLE); 2893 onoff("Fatal Error Reporting Enable", reg, PCI_AER_ROOTERR_F_ENABLE); 2894 } 2895 2896 static void 2897 pci_conf_print_aer_cap_rooterr_status(pcireg_t reg) 2898 { 2899 2900 onoff("ERR_COR Received", reg, PCI_AER_ROOTERR_COR_ERR); 2901 onoff("Multiple ERR_COR Received", reg, PCI_AER_ROOTERR_MULTI_COR_ERR); 2902 onoff("ERR_FATAL/NONFATAL_ERR Received", reg, PCI_AER_ROOTERR_UC_ERR); 2903 onoff("Multiple ERR_FATAL/NONFATAL_ERR Received", reg, 2904 PCI_AER_ROOTERR_MULTI_UC_ERR); 2905 onoff("First Uncorrectable Fatal", reg,PCI_AER_ROOTERR_FIRST_UC_FATAL); 2906 onoff("Non-Fatal Error Messages Received", reg,PCI_AER_ROOTERR_NF_ERR); 2907 onoff("Fatal Error Messages Received", reg, PCI_AER_ROOTERR_F_ERR); 2908 printf(" Advanced Error Interrupt Message Number: 0x%02x\n", 2909 PCIREG_SHIFTOUT(reg, PCI_AER_ROOTERR_INT_MESSAGE)); 2910 } 2911 2912 static void 2913 pci_conf_print_aer_cap_errsrc_id(pcireg_t reg) 2914 { 2915 2916 printf(" Correctable Source ID: 0x%04x\n", 2917 PCIREG_SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_COR)); 2918 printf(" ERR_FATAL/NONFATAL Source ID: 0x%04x\n", 2919 PCIREG_SHIFTOUT(reg, PCI_AER_ERRSRC_ID_ERR_UC)); 2920 } 2921 2922 static void 2923 pci_conf_print_aer_cap(const pcireg_t *regs, int extcapoff) 2924 { 2925 pcireg_t reg; 2926 int pcie_capoff; 2927 int pcie_devtype = -1; 2928 bool tlp_prefix_log = false; 2929 2930 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 2931 reg = regs[o2i(pcie_capoff)]; 2932 pcie_devtype = PCIE_XCAP_TYPE(reg); 2933 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 2934 if (PCIREG_SHIFTOUT(reg, PCIE_XCAP_VER_MASK) >= 2) { 2935 reg = regs[o2i(pcie_capoff + PCIE_DCAP2)]; 2936 /* End-End TLP Prefix Supported */ 2937 if (reg & PCIE_DCAP2_EETLP_PREF) { 2938 tlp_prefix_log = true; 2939 } 2940 } 2941 } 2942 2943 printf("\n Advanced Error Reporting Register\n"); 2944 2945 reg = regs[o2i(extcapoff + PCI_AER_UC_STATUS)]; 2946 printf(" Uncorrectable Error Status register: 0x%08x\n", reg); 2947 pci_conf_print_aer_cap_uc(reg); 2948 reg = regs[o2i(extcapoff + PCI_AER_UC_MASK)]; 2949 printf(" Uncorrectable Error Mask register: 0x%08x\n", reg); 2950 pci_conf_print_aer_cap_uc(reg); 2951 reg = regs[o2i(extcapoff + PCI_AER_UC_SEVERITY)]; 2952 printf(" Uncorrectable Error Severity register: 0x%08x\n", reg); 2953 pci_conf_print_aer_cap_uc(reg); 2954 2955 reg = regs[o2i(extcapoff + PCI_AER_COR_STATUS)]; 2956 printf(" Correctable Error Status register: 0x%08x\n", reg); 2957 pci_conf_print_aer_cap_cor(reg); 2958 reg = regs[o2i(extcapoff + PCI_AER_COR_MASK)]; 2959 printf(" Correctable Error Mask register: 0x%08x\n", reg); 2960 pci_conf_print_aer_cap_cor(reg); 2961 2962 reg = regs[o2i(extcapoff + PCI_AER_CAP_CONTROL)]; 2963 printf(" Advanced Error Capabilities and Control register: 0x%08x\n", 2964 reg); 2965 pci_conf_print_aer_cap_control(reg, &tlp_prefix_log); 2966 reg = regs[o2i(extcapoff + PCI_AER_HEADER_LOG)]; 2967 printf(" Header Log register:\n"); 2968 pci_conf_print_regs(regs, extcapoff + PCI_AER_HEADER_LOG, 2969 extcapoff + PCI_AER_ROOTERR_CMD); 2970 2971 switch (pcie_devtype) { 2972 case PCIE_XCAP_TYPE_RP: /* Root Port of PCI Express Root Complex */ 2973 case PCIE_XCAP_TYPE_RC_EVNTC: /* Root Complex Event Collector */ 2974 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)]; 2975 printf(" Root Error Command register: 0x%08x\n", reg); 2976 pci_conf_print_aer_cap_rooterr_cmd(reg); 2977 reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_STATUS)]; 2978 printf(" Root Error Status register: 0x%08x\n", reg); 2979 pci_conf_print_aer_cap_rooterr_status(reg); 2980 2981 reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)]; 2982 printf(" Error Source Identification register: 0x%08x\n", 2983 reg); 2984 pci_conf_print_aer_cap_errsrc_id(reg); 2985 break; 2986 } 2987 2988 if (tlp_prefix_log) { 2989 reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)]; 2990 printf(" TLP Prefix Log register: 0x%08x\n", reg); 2991 } 2992 } 2993 2994 /* 2995 * Helper function to print the arbitration phase register. 2996 * 2997 * phases: Number of phases in the arbitration tables. 2998 * arbsize: Number of bits in each phase. 2999 * indent: Add more two spaces if it's true. 3000 */ 3001 static void 3002 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name, 3003 const int phases, int arbsize, bool indent) 3004 { 3005 pcireg_t reg; 3006 int num_per_reg = 32 / arbsize; 3007 int i, j; 3008 3009 printf("%s %s Arbitration Table:\n", indent ? " " : "", name); 3010 for (i = 0; i < phases; i += num_per_reg) { 3011 reg = regs[o2i(off + (sizeof(uint32_t) * (i / num_per_reg)))]; 3012 for (j = 0; j < num_per_reg; j++) { 3013 printf("%s Phase[%d]: 0x%x\n", indent ? " " : "", 3014 i + j, 3015 (uint32_t)(reg & __BITS(arbsize - 1, 0))); 3016 reg >>= arbsize; 3017 } 3018 } 3019 } 3020 3021 /* For VC, bit 4-7 are reserved. For Port, bit 6-7 are reserved */ 3022 static const int arb_phases[8] = {0, 32, 64, 128, 128, 256, 0, 0 }; 3023 3024 static void 3025 pci_conf_print_vc_cap(const pcireg_t *regs, int extcapoff) 3026 { 3027 pcireg_t reg, n; 3028 int arbtab, parbsize; 3029 pcireg_t arbsel; 3030 int i, count; 3031 3032 printf("\n Virtual Channel Register\n"); 3033 reg = regs[o2i(extcapoff + PCI_VC_CAP1)]; 3034 printf(" Port VC Capability register 1: 0x%08x\n", reg); 3035 count = PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT); 3036 printf(" Extended VC Count: %d\n", count); 3037 n = PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT); 3038 printf(" Low Priority Extended VC Count: %u\n", n); 3039 n = PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_REFCLK); 3040 printf(" Reference Clock: %s\n", 3041 (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown"); 3042 parbsize = 1 << PCIREG_SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE); 3043 printf(" Port Arbitration Table Entry Size: %dbit\n", parbsize); 3044 3045 reg = regs[o2i(extcapoff + PCI_VC_CAP2)]; 3046 printf(" Port VC Capability register 2: 0x%08x\n", reg); 3047 onoff("Hardware fixed arbitration scheme", 3048 reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME); 3049 onoff("WRR arbitration with 32 phases", 3050 reg, PCI_VC_CAP2_ARB_CAP_WRR_32); 3051 onoff("WRR arbitration with 64 phases", 3052 reg, PCI_VC_CAP2_ARB_CAP_WRR_64); 3053 onoff("WRR arbitration with 128 phases", 3054 reg, PCI_VC_CAP2_ARB_CAP_WRR_128); 3055 arbtab = PCIREG_SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET); 3056 printf(" VC Arbitration Table Offset: 0x%x\n", arbtab); 3057 3058 reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff; 3059 printf(" Port VC Control register: 0x%04x\n", reg); 3060 arbsel = PCIREG_SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT); 3061 printf(" VC Arbitration Select: 0x%x\n", arbsel); 3062 3063 reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16; 3064 printf(" Port VC Status register: 0x%04x\n", reg); 3065 onoff("VC Arbitration Table Status", 3066 reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE); 3067 3068 if ((arbtab != 0) && (arbsel != 0)) 3069 pci_conf_print_vc_cap_arbtab(regs, extcapoff + (arbtab * 16), 3070 "VC", arb_phases[arbsel], 4, false); 3071 3072 for (i = 0; i < count + 1; i++) { 3073 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))]; 3074 printf(" VC number %d\n", i); 3075 printf(" VC Resource Capability Register: 0x%08x\n", reg); 3076 onoff(" Non-configurable Hardware fixed arbitration scheme", 3077 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME); 3078 onoff(" WRR arbitration with 32 phases", 3079 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32); 3080 onoff(" WRR arbitration with 64 phases", 3081 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64); 3082 onoff(" WRR arbitration with 128 phases", 3083 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128); 3084 onoff(" Time-based WRR arbitration with 128 phases", 3085 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128); 3086 onoff(" WRR arbitration with 256 phases", 3087 reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256); 3088 onoff(" Advanced Packet Switching", 3089 reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH); 3090 onoff(" Reject Snoop Transaction", 3091 reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS); 3092 n = PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1; 3093 printf(" Maximum Time Slots: %d\n", n); 3094 arbtab = PCIREG_SHIFTOUT(reg, 3095 PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET); 3096 printf(" Port Arbitration Table offset: 0x%02x\n", 3097 arbtab); 3098 3099 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))]; 3100 printf(" VC Resource Control Register: 0x%08x\n", reg); 3101 printf(" TC/VC Map: 0x%02x\n", 3102 PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP)); 3103 /* 3104 * The load Port Arbitration Table bit is used to update 3105 * the Port Arbitration logic and it's always 0 on read, so 3106 * we don't print it. 3107 */ 3108 arbsel = PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT); 3109 printf(" Port Arbitration Select: 0x%x\n", arbsel); 3110 n = PCIREG_SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID); 3111 printf(" VC ID: %d\n", n); 3112 onoff(" VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE); 3113 3114 reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16; 3115 printf(" VC Resource Status Register: 0x%08x\n", reg); 3116 onoff(" Port Arbitration Table Status", 3117 reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE); 3118 onoff(" VC Negotiation Pending", 3119 reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING); 3120 3121 if ((arbtab != 0) && (arbsel != 0)) 3122 pci_conf_print_vc_cap_arbtab(regs, 3123 extcapoff + (arbtab * 16), 3124 "Port", arb_phases[arbsel], parbsize, true); 3125 } 3126 } 3127 3128 /* 3129 * Print Power limit. This encoding is the same among the following registers: 3130 * - The Captured Slot Power Limit in the PCIe Device Capability Register. 3131 * - The Slot Power Limit in the PCIe Slot Capability Register. 3132 * - The Base Power in the Data register of Power Budgeting capability. 3133 */ 3134 static void 3135 pci_conf_print_pcie_power(uint8_t base, unsigned int scale) 3136 { 3137 unsigned int sdiv = 1; 3138 3139 if ((scale == 0) && (base > 0xef)) { 3140 const char *s; 3141 3142 switch (base) { 3143 case 0xf0: 3144 s = "239W < x <= 250W"; 3145 break; 3146 case 0xf1: 3147 s = "250W < x <= 275W"; 3148 break; 3149 case 0xf2: 3150 s = "275W < x <= 300W"; 3151 break; 3152 default: 3153 s = "reserved for greater than 300W"; 3154 break; 3155 } 3156 printf("%s\n", s); 3157 return; 3158 } 3159 3160 for (unsigned int i = scale; i > 0; i--) 3161 sdiv *= 10; 3162 3163 printf("%u", base / sdiv); 3164 3165 if (scale != 0) { 3166 printf(".%u", base % sdiv); 3167 } 3168 printf ("W\n"); 3169 return; 3170 } 3171 3172 static const char * 3173 pci_conf_print_pwrbdgt_type(uint8_t reg) 3174 { 3175 3176 switch (reg) { 3177 case 0x00: 3178 return "PME Aux"; 3179 case 0x01: 3180 return "Auxilary"; 3181 case 0x02: 3182 return "Idle"; 3183 case 0x03: 3184 return "Sustained"; 3185 case 0x04: 3186 return "Sustained (Emergency Power Reduction)"; 3187 case 0x05: 3188 return "Maximum (Emergency Power Reduction)"; 3189 case 0x07: 3190 return "Maximum"; 3191 default: 3192 return "Unknown"; 3193 } 3194 } 3195 3196 static const char * 3197 pci_conf_print_pwrbdgt_pwrrail(uint8_t reg) 3198 { 3199 3200 switch (reg) { 3201 case 0x00: 3202 return "Power(12V)"; 3203 case 0x01: 3204 return "Power(3.3V)"; 3205 case 0x02: 3206 return "Power(1.5V or 1.8V)"; 3207 case 0x07: 3208 return "Thermal"; 3209 default: 3210 return "Unknown"; 3211 } 3212 } 3213 3214 static void 3215 pci_conf_print_pwrbdgt_cap(const pcireg_t *regs, int extcapoff) 3216 { 3217 pcireg_t reg; 3218 3219 printf("\n Power Budgeting\n"); 3220 3221 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DSEL)]; 3222 printf(" Data Select register: 0x%08x\n", reg); 3223 3224 reg = regs[o2i(extcapoff + PCI_PWRBDGT_DATA)]; 3225 printf(" Data register: 0x%08x\n", reg); 3226 printf(" Base Power: "); 3227 pci_conf_print_pcie_power( 3228 PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_DATA_BASEPWR), 3229 PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_DATA_SCALE)); 3230 printf(" PM Sub State: 0x%hhx\n", 3231 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_PM_SUBSTAT)); 3232 printf(" PM State: D%u\n", 3233 PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_PM_STAT)); 3234 printf(" Type: %s\n", 3235 pci_conf_print_pwrbdgt_type( 3236 (uint8_t)(PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_TYPE)))); 3237 printf(" Power Rail: %s\n", 3238 pci_conf_print_pwrbdgt_pwrrail( 3239 (uint8_t)(PCIREG_SHIFTOUT(reg, PCI_PWRBDGT_PWRRAIL)))); 3240 3241 reg = regs[o2i(extcapoff + PCI_PWRBDGT_CAP)]; 3242 printf(" Power Budget Capability register: 0x%08x\n", reg); 3243 onoff("System Allocated", 3244 reg, PCI_PWRBDGT_CAP_SYSALLOC); 3245 } 3246 3247 static const char * 3248 pci_conf_print_rclink_dcl_cap_elmtype(unsigned char type) 3249 { 3250 3251 switch (type) { 3252 case 0x00: 3253 return "Configuration Space Element"; 3254 case 0x01: 3255 return "System Egress Port or internal sink (memory)"; 3256 case 0x02: 3257 return "Internal Root Complex Link"; 3258 default: 3259 return "Unknown"; 3260 } 3261 } 3262 3263 static void 3264 pci_conf_print_rclink_dcl_cap(const pcireg_t *regs, int extcapoff) 3265 { 3266 pcireg_t reg; 3267 unsigned char nent, linktype; 3268 int i; 3269 3270 printf("\n Root Complex Link Declaration\n"); 3271 3272 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_ESDESC)]; 3273 printf(" Element Self Description Register: 0x%08x\n", reg); 3274 printf(" Element Type: %s\n", 3275 pci_conf_print_rclink_dcl_cap_elmtype((unsigned char)reg)); 3276 nent = PCIREG_SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_NUMLINKENT); 3277 printf(" Number of Link Entries: %hhu\n", nent); 3278 printf(" Component ID: %hhu\n", 3279 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_COMPID)); 3280 printf(" Port Number: %hhu\n", 3281 (uint8_t)PCIREG_SHIFTOUT(reg, PCI_RCLINK_DCL_ESDESC_PORTNUM)); 3282 for (i = 0; i < nent; i++) { 3283 reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))]; 3284 printf(" Link Entry %d:\n", i + 1); 3285 printf(" Link Description Register: 0x%08x\n", reg); 3286 onoff(" Link Valid", reg, PCI_RCLINK_DCL_LINKDESC_LVALID); 3287 linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE; 3288 onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE, 3289 "Configuration Space", "Memory-Mapped Space"); 3290 onoff(" Associated RCRB Header", reg, 3291 PCI_RCLINK_DCL_LINKDESC_ARCRBH); 3292 printf(" Target Component ID: %hhu\n", 3293 (uint8_t)PCIREG_SHIFTOUT(reg, 3294 PCI_RCLINK_DCL_LINKDESC_TCOMPID)); 3295 printf(" Target Port Number: %hhu\n", 3296 (uint8_t)PCIREG_SHIFTOUT(reg, 3297 PCI_RCLINK_DCL_LINKDESC_TPNUM)); 3298 3299 if (linktype == 0) { 3300 /* Memory-Mapped Space */ 3301 reg = regs[o2i(extcapoff 3302 + PCI_RCLINK_DCL_LINKADDR_LT0_LO(i))]; 3303 printf(" Link Address Low Register: 0x%08x\n", 3304 reg); 3305 reg = regs[o2i(extcapoff 3306 + PCI_RCLINK_DCL_LINKADDR_LT0_HI(i))]; 3307 printf(" Link Address High Register: 0x%08x\n", 3308 reg); 3309 } else { 3310 unsigned int nb; 3311 pcireg_t lo, hi; 3312 3313 /* Configuration Space */ 3314 lo = regs[o2i(extcapoff 3315 + PCI_RCLINK_DCL_LINKADDR_LT1_LO(i))]; 3316 printf(" Configuration Space Low Register: " 3317 "0x%08x\n", lo); 3318 hi = regs[o2i(extcapoff 3319 + PCI_RCLINK_DCL_LINKADDR_LT1_HI(i))]; 3320 printf(" Configuration Space High Register: " 3321 "0x%08x\n", hi); 3322 nb = PCIREG_SHIFTOUT(lo, PCI_RCLINK_DCL_LINKADDR_LT1_N); 3323 printf(" N: %u\n", nb); 3324 printf(" Func: %hhu\n", 3325 (uint8_t)PCIREG_SHIFTOUT(lo, 3326 PCI_RCLINK_DCL_LINKADDR_LT1_FUNC)); 3327 printf(" Dev: %hhu\n", 3328 (uint8_t)PCIREG_SHIFTOUT(lo, 3329 PCI_RCLINK_DCL_LINKADDR_LT1_DEV)); 3330 printf(" Bus: %hhu\n", 3331 (uint8_t)PCIREG_SHIFTOUT(lo, 3332 PCI_RCLINK_DCL_LINKADDR_LT1_BUS(nb))); 3333 lo &= PCI_RCLINK_DCL_LINKADDR_LT1_BAL(i); 3334 printf(" Configuration Space Base Address: " 3335 "0x%016" PRIx64 "\n", ((uint64_t)hi << 32) + lo); 3336 } 3337 } 3338 } 3339 3340 /* XXX pci_conf_print_rclink_ctl_cap */ 3341 3342 static void 3343 pci_conf_print_rcec_assoc_cap(const pcireg_t *regs, int extcapoff) 3344 { 3345 pcireg_t reg; 3346 3347 printf("\n Root Complex Event Collector Association\n"); 3348 3349 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBITMAP)]; 3350 printf(" Association Bitmap for Root Complex Integrated Devices:" 3351 " 0x%08x\n", reg); 3352 3353 if (PCI_EXTCAPLIST_VERSION(regs[o2i(extcapoff)]) >= 2) { 3354 reg = regs[o2i(extcapoff + PCI_RCEC_ASSOC_ASSOCBUSNUM)]; 3355 printf(" RCEC Associated Bus Numbers register: 0x%08x\n", 3356 reg); 3357 printf(" RCEC Next Bus: %u\n", 3358 PCIREG_SHIFTOUT(reg, 3359 PCI_RCEC_ASSOCBUSNUM_RCECNEXT)); 3360 printf(" RCEC Last Bus: %u\n", 3361 PCIREG_SHIFTOUT(reg, 3362 PCI_RCEC_ASSOCBUSNUM_RCECLAST)); 3363 } 3364 } 3365 3366 /* XXX pci_conf_print_mfvc_cap */ 3367 /* XXX pci_conf_print_vc2_cap */ 3368 /* XXX pci_conf_print_rcrb_cap */ 3369 /* XXX pci_conf_print_vendor_cap */ 3370 /* XXX pci_conf_print_cac_cap */ 3371 3372 static void 3373 pci_conf_print_acs_cap(const pcireg_t *regs, int extcapoff) 3374 { 3375 pcireg_t reg, cap, ctl; 3376 unsigned int size, i; 3377 3378 printf("\n Access Control Services\n"); 3379 3380 reg = regs[o2i(extcapoff + PCI_ACS_CAP)]; 3381 cap = reg & 0xffff; 3382 ctl = reg >> 16; 3383 printf(" ACS Capability register: 0x%08x\n", cap); 3384 onoff("ACS Source Validation", cap, PCI_ACS_CAP_V); 3385 onoff("ACS Transaction Blocking", cap, PCI_ACS_CAP_B); 3386 onoff("ACS P2P Request Redirect", cap, PCI_ACS_CAP_R); 3387 onoff("ACS P2P Completion Redirect", cap, PCI_ACS_CAP_C); 3388 onoff("ACS Upstream Forwarding", cap, PCI_ACS_CAP_U); 3389 onoff("ACS Egress Control", cap, PCI_ACS_CAP_E); 3390 onoff("ACS Direct Translated P2P", cap, PCI_ACS_CAP_T); 3391 size = PCIREG_SHIFTOUT(cap, PCI_ACS_CAP_ECVSIZE); 3392 if (size == 0) 3393 size = 256; 3394 printf(" Egress Control Vector Size: %u\n", size); 3395 printf(" ACS Control register: 0x%08x\n", ctl); 3396 onoff("ACS Source Validation Enable", ctl, PCI_ACS_CTL_V); 3397 onoff("ACS Transaction Blocking Enable", ctl, PCI_ACS_CTL_B); 3398 onoff("ACS P2P Request Redirect Enable", ctl, PCI_ACS_CTL_R); 3399 onoff("ACS P2P Completion Redirect Enable", ctl, PCI_ACS_CTL_C); 3400 onoff("ACS Upstream Forwarding Enable", ctl, PCI_ACS_CTL_U); 3401 onoff("ACS Egress Control Enable", ctl, PCI_ACS_CTL_E); 3402 onoff("ACS Direct Translated P2P Enable", ctl, PCI_ACS_CTL_T); 3403 3404 /* 3405 * If the P2P Egress Control Capability bit is 0, ignore the Egress 3406 * Control vector. 3407 */ 3408 if ((cap & PCI_ACS_CAP_E) == 0) 3409 return; 3410 for (i = 0; i < size; i += 32) 3411 printf(" Egress Control Vector [%u..%u]: 0x%08x\n", i + 31, 3412 i, regs[o2i(extcapoff + PCI_ACS_ECV + (i / 32) * 4 )]); 3413 } 3414 3415 static void 3416 pci_conf_print_ari_cap(const pcireg_t *regs, int extcapoff) 3417 { 3418 pcireg_t reg, cap, ctl; 3419 3420 printf("\n Alternative Routing-ID Interpretation Register\n"); 3421 3422 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3423 cap = reg & 0xffff; 3424 ctl = reg >> 16; 3425 printf(" Capability register: 0x%08x\n", cap); 3426 onoff("MVFC Function Groups Capability", reg, PCI_ARI_CAP_M); 3427 onoff("ACS Function Groups Capability", reg, PCI_ARI_CAP_A); 3428 printf(" Next Function Number: %u\n", 3429 PCIREG_SHIFTOUT(reg, PCI_ARI_CAP_NXTFN)); 3430 printf(" Control register: 0x%08x\n", ctl); 3431 onoff("MVFC Function Groups Enable", reg, PCI_ARI_CTL_M); 3432 onoff("ACS Function Groups Enable", reg, PCI_ARI_CTL_A); 3433 printf(" Function Group: %u\n", 3434 PCIREG_SHIFTOUT(reg, PCI_ARI_CTL_FUNCGRP)); 3435 } 3436 3437 static void 3438 pci_conf_print_ats_cap(const pcireg_t *regs, int extcapoff) 3439 { 3440 pcireg_t reg, cap, ctl; 3441 unsigned int num; 3442 3443 printf("\n Address Translation Services\n"); 3444 3445 reg = regs[o2i(extcapoff + PCI_ARI_CAP)]; 3446 cap = reg & 0xffff; 3447 ctl = reg >> 16; 3448 printf(" Capability register: 0x%04x\n", cap); 3449 num = PCIREG_SHIFTOUT(reg, PCI_ATS_CAP_INVQDEPTH); 3450 if (num == 0) 3451 num = 32; 3452 printf(" Invalidate Queue Depth: %u\n", num); 3453 onoff("Page Aligned Request", reg, PCI_ATS_CAP_PALIGNREQ); 3454 onoff("Global Invalidate", reg, PCI_ATS_CAP_GLOBALINVL); 3455 onoff("Relaxed Ordering", reg, PCI_ATS_CAP_RELAXORD); 3456 3457 printf(" Control register: 0x%04x\n", ctl); 3458 printf(" Smallest Translation Unit: %u\n", 3459 PCIREG_SHIFTOUT(reg, PCI_ATS_CTL_STU)); 3460 onoff("Enable", reg, PCI_ATS_CTL_EN); 3461 } 3462 3463 static void 3464 pci_conf_print_sernum_cap(const pcireg_t *regs, int extcapoff) 3465 { 3466 pcireg_t lo, hi; 3467 3468 printf("\n Device Serial Number Register\n"); 3469 3470 lo = regs[o2i(extcapoff + PCI_SERIAL_LOW)]; 3471 hi = regs[o2i(extcapoff + PCI_SERIAL_HIGH)]; 3472 printf(" Serial Number: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 3473 hi >> 24, (hi >> 16) & 0xff, (hi >> 8) & 0xff, hi & 0xff, 3474 lo >> 24, (lo >> 16) & 0xff, (lo >> 8) & 0xff, lo & 0xff); 3475 } 3476 3477 static void 3478 pci_conf_print_sriov_cap(const pcireg_t *regs, int extcapoff) 3479 { 3480 char buf[sizeof("99999 MB")]; 3481 pcireg_t reg; 3482 pcireg_t total_vfs; 3483 int i; 3484 bool first; 3485 3486 printf("\n Single Root IO Virtualization Register\n"); 3487 3488 reg = regs[o2i(extcapoff + PCI_SRIOV_CAP)]; 3489 printf(" Capabilities register: 0x%08x\n", reg); 3490 onoff("VF Migration Capable", reg, PCI_SRIOV_CAP_VF_MIGRATION); 3491 onoff("ARI Capable Hierarchy Preserved", reg, 3492 PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED); 3493 if (reg & PCI_SRIOV_CAP_VF_MIGRATION) { 3494 printf(" VF Migration Interrupt Message Number: 0x%03x\n", 3495 PCIREG_SHIFTOUT(reg, PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N)); 3496 } 3497 3498 reg = regs[o2i(extcapoff + PCI_SRIOV_CTL)] & 0xffff; 3499 printf(" Control register: 0x%04x\n", reg); 3500 onoff("VF Enable", reg, PCI_SRIOV_CTL_VF_ENABLE); 3501 onoff("VF Migration Enable", reg, PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT); 3502 onoff("VF Migration Interrupt Enable", reg, 3503 PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE); 3504 onoff("VF Memory Space Enable", reg, PCI_SRIOV_CTL_VF_MSE); 3505 onoff("ARI Capable Hierarchy", reg, PCI_SRIOV_CTL_ARI_CAP_HIER); 3506 3507 reg = regs[o2i(extcapoff + PCI_SRIOV_STA)] >> 16; 3508 printf(" Status register: 0x%04x\n", reg); 3509 onoff("VF Migration Status", reg, PCI_SRIOV_STA_VF_MIGRATION); 3510 3511 reg = regs[o2i(extcapoff + PCI_SRIOV_INITIAL_VFS)] & 0xffff; 3512 printf(" InitialVFs register: 0x%04x\n", reg); 3513 total_vfs = reg = regs[o2i(extcapoff + PCI_SRIOV_TOTAL_VFS)] >> 16; 3514 printf(" TotalVFs register: 0x%04x\n", reg); 3515 reg = regs[o2i(extcapoff + PCI_SRIOV_NUM_VFS)] & 0xffff; 3516 printf(" NumVFs register: 0x%04x\n", reg); 3517 3518 reg = regs[o2i(extcapoff + PCI_SRIOV_FUNC_DEP_LINK)] >> 16; 3519 printf(" Function Dependency Link register: 0x%04x\n", reg); 3520 3521 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_OFF)] & 0xffff; 3522 printf(" First VF Offset register: 0x%04x\n", reg); 3523 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_STRIDE)] >> 16; 3524 printf(" VF Stride register: 0x%04x\n", reg); 3525 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_DID)] >> 16; 3526 printf(" Device ID: 0x%04x\n", reg); 3527 3528 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_CAP)]; 3529 printf(" Supported Page Sizes register: 0x%08x\n", reg); 3530 printf(" Supported Page Size:"); 3531 for (i = 0, first = true; i < 32; i++) { 3532 if (reg & __BIT(i)) { 3533 #ifdef _KERNEL 3534 format_bytes(buf, sizeof(buf), 1LL << (i + 12)); 3535 #else 3536 humanize_number(buf, sizeof(buf), 1LL << (i + 12), "B", 3537 HN_AUTOSCALE, 0); 3538 #endif 3539 printf("%s %s", first ? "" : ",", buf); 3540 first = false; 3541 } 3542 } 3543 printf("\n"); 3544 3545 reg = regs[o2i(extcapoff + PCI_SRIOV_PAGE_SIZE)]; 3546 printf(" System Page Sizes register: 0x%08x\n", reg); 3547 printf(" Page Size: "); 3548 if (reg != 0) { 3549 int bitpos = ffs(reg) -1; 3550 3551 /* Assume only one bit is set. */ 3552 #ifdef _KERNEL 3553 format_bytes(buf, sizeof(buf), 1LL << (bitpos + 12)); 3554 #else 3555 humanize_number(buf, sizeof(buf), 1LL << (bitpos + 12), 3556 "B", HN_AUTOSCALE, 0); 3557 #endif 3558 printf("%s", buf); 3559 } else { 3560 printf("unknown"); 3561 } 3562 printf("\n"); 3563 3564 for (i = 0; i < 6; i++) { 3565 reg = regs[o2i(extcapoff + PCI_SRIOV_BAR(i))]; 3566 printf(" VF BAR%d register: 0x%08x\n", i, reg); 3567 } 3568 3569 if (total_vfs > 0) { 3570 reg = regs[o2i(extcapoff + PCI_SRIOV_VF_MIG_STA_AR)]; 3571 printf(" VF Migration State Array Offset register: 0x%08x\n", 3572 reg); 3573 printf(" VF Migration State Offset: 0x%08x\n", 3574 PCIREG_SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_OFFSET)); 3575 i = PCIREG_SHIFTOUT(reg, PCI_SRIOV_VF_MIG_STA_BIR); 3576 printf(" VF Migration State BIR: "); 3577 if (i >= 0 && i <= 5) { 3578 printf("BAR%d", i); 3579 } else { 3580 printf("unknown BAR (%d)", i); 3581 } 3582 printf("\n"); 3583 } 3584 } 3585 3586 /* XXX pci_conf_print_mriov_cap */ 3587 3588 static void 3589 pci_conf_print_multicast_cap(const pcireg_t *regs, int extcapoff) 3590 { 3591 pcireg_t reg, cap, ctl; 3592 pcireg_t regl, regh; 3593 uint64_t addr; 3594 int n; 3595 3596 printf("\n Multicast\n"); 3597 3598 reg = regs[o2i(extcapoff + PCI_MCAST_CTL)]; 3599 cap = reg & 0xffff; 3600 ctl = reg >> 16; 3601 printf(" Capability Register: 0x%04x\n", cap); 3602 printf(" Max Group: %u\n", 3603 (pcireg_t)(reg & PCI_MCAST_CAP_MAXGRP) + 1); 3604 3605 /* Endpoint Only */ 3606 n = PCIREG_SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ); 3607 if (n > 0) 3608 printf(" Window Size Requested: %d\n", 1 << (n - 1)); 3609 3610 onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN); 3611 3612 printf(" Control Register: 0x%04x\n", ctl); 3613 printf(" Num Group: %u\n", 3614 PCIREG_SHIFTOUT(reg, PCI_MCAST_CTL_NUMGRP) + 1); 3615 onoff("Enable", reg, PCI_MCAST_CTL_ENA); 3616 3617 regl = regs[o2i(extcapoff + PCI_MCAST_BARL)]; 3618 regh = regs[o2i(extcapoff + PCI_MCAST_BARH)]; 3619 printf(" Base Address Register 0: 0x%08x\n", regl); 3620 printf(" Base Address Register 1: 0x%08x\n", regh); 3621 printf(" Index Position: %u\n", 3622 (unsigned int)(regl & PCI_MCAST_BARL_INDPOS)); 3623 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_BARL_ADDR); 3624 printf(" Base Address: 0x%016" PRIx64 "\n", addr); 3625 3626 regl = regs[o2i(extcapoff + PCI_MCAST_RECVL)]; 3627 regh = regs[o2i(extcapoff + PCI_MCAST_RECVH)]; 3628 printf(" Receive Register 0: 0x%08x\n", regl); 3629 printf(" Receive Register 1: 0x%08x\n", regh); 3630 3631 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLL)]; 3632 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKALLH)]; 3633 printf(" Block All Register 0: 0x%08x\n", regl); 3634 printf(" Block All Register 1: 0x%08x\n", regh); 3635 3636 regl = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSL)]; 3637 regh = regs[o2i(extcapoff + PCI_MCAST_BLOCKUNTRNSH)]; 3638 printf(" Block Untranslated Register 0: 0x%08x\n", regl); 3639 printf(" Block Untranslated Register 1: 0x%08x\n", regh); 3640 3641 regl = regs[o2i(extcapoff + PCI_MCAST_OVERLAYL)]; 3642 regh = regs[o2i(extcapoff + PCI_MCAST_OVERLAYH)]; 3643 printf(" Overlay BAR 0: 0x%08x\n", regl); 3644 printf(" Overlay BAR 1: 0x%08x\n", regh); 3645 3646 n = regl & PCI_MCAST_OVERLAYL_SIZE; 3647 printf(" Overlay Size: "); 3648 if (n >= 6) 3649 printf("%d\n", n); 3650 else 3651 printf("off\n"); 3652 addr = ((uint64_t)regh << 32) | (regl & PCI_MCAST_OVERLAYL_ADDR); 3653 printf(" Overlay BAR: 0x%016" PRIx64 "\n", addr); 3654 } 3655 3656 static void 3657 pci_conf_print_page_req_cap(const pcireg_t *regs, int extcapoff) 3658 { 3659 pcireg_t reg, ctl, sta; 3660 3661 printf("\n Page Request\n"); 3662 3663 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_CTL)]; 3664 ctl = reg & 0xffff; 3665 sta = reg >> 16; 3666 printf(" Control Register: 0x%04x\n", ctl); 3667 onoff("Enable", reg, PCI_PAGE_REQ_CTL_E); 3668 onoff("Reset", reg, PCI_PAGE_REQ_CTL_R); 3669 3670 printf(" Status Register: 0x%04x\n", sta); 3671 onoff("Response Failure", reg, PCI_PAGE_REQ_STA_RF); 3672 onoff("Unexpected Page Request Group Index", reg, 3673 PCI_PAGE_REQ_STA_UPRGI); 3674 onoff("Stopped", reg, PCI_PAGE_REQ_STA_S); 3675 onoff("PRG Response PASID Required", reg, PCI_PAGE_REQ_STA_PASIDR); 3676 3677 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTCAPA)]; 3678 printf(" Outstanding Page Request Capacity: %u\n", reg); 3679 reg = regs[o2i(extcapoff + PCI_PAGE_REQ_OUTSTALLOC)]; 3680 printf(" Outstanding Page Request Allocation: %u\n", reg); 3681 } 3682 3683 /* XXX pci_conf_print_amd_cap */ 3684 3685 #define MEM_PBUFSIZE sizeof("999GB") 3686 3687 static void 3688 pci_conf_print_resizbar_cap(const pcireg_t *regs, int extcapoff) 3689 { 3690 pcireg_t cap, ctl; 3691 unsigned int bars, i, n; 3692 char pbuf[MEM_PBUFSIZE]; 3693 3694 printf("\n Resizable BAR\n"); 3695 3696 /* Get Number of Resizable BARs */ 3697 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(0))]; 3698 bars = PCIREG_SHIFTOUT(ctl, PCI_RESIZBAR_CTL_NUMBAR); 3699 printf(" Number of Resizable BARs: "); 3700 if (bars <= 6) 3701 printf("%u\n", bars); 3702 else { 3703 printf("incorrect (%u)\n", bars); 3704 return; 3705 } 3706 3707 for (n = 0; n < 6; n++) { 3708 cap = regs[o2i(extcapoff + PCI_RESIZBAR_CAP(n))]; 3709 printf(" Capability register(%u): 0x%08x\n", n, cap); 3710 if ((cap & PCI_RESIZBAR_CAP_SIZEMASK) == 0) 3711 continue; /* Not Used */ 3712 printf(" Acceptable BAR sizes:"); 3713 for (i = 4; i <= 23; i++) { 3714 if ((cap & (1 << i)) != 0) { 3715 humanize_number(pbuf, MEM_PBUFSIZE, 3716 (int64_t)1024 * 1024 << (i - 4), "B", 3717 #ifdef _KERNEL 3718 1); 3719 #else 3720 HN_AUTOSCALE, HN_NOSPACE); 3721 #endif 3722 printf(" %s", pbuf); 3723 } 3724 } 3725 printf("\n"); 3726 3727 ctl = regs[o2i(extcapoff + PCI_RESIZBAR_CTL(n))]; 3728 printf(" Control register(%u): 0x%08x\n", n, ctl); 3729 printf(" BAR Index: %u\n", 3730 PCIREG_SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARIDX)); 3731 humanize_number(pbuf, MEM_PBUFSIZE, 3732 (int64_t)1024 * 1024 3733 << PCIREG_SHIFTOUT(ctl, PCI_RESIZBAR_CTL_BARSIZ), 3734 "B", 3735 #ifdef _KERNEL 3736 1); 3737 #else 3738 HN_AUTOSCALE, HN_NOSPACE); 3739 #endif 3740 printf(" BAR Size: %s\n", pbuf); 3741 } 3742 } 3743 3744 static void 3745 pci_conf_print_dpa_cap(const pcireg_t *regs, int extcapoff) 3746 { 3747 pcireg_t reg; 3748 unsigned int substmax, i; 3749 3750 printf("\n Dynamic Power Allocation\n"); 3751 3752 reg = regs[o2i(extcapoff + PCI_DPA_CAP)]; 3753 printf(" Capability register: 0x%08x\n", reg); 3754 substmax = PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_SUBSTMAX); 3755 printf(" Substate Max: %u\n", substmax); 3756 printf(" Transition Latency Unit: "); 3757 switch (PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_TLUINT)) { 3758 case 0: 3759 printf("1ms\n"); 3760 break; 3761 case 1: 3762 printf("10ms\n"); 3763 break; 3764 case 2: 3765 printf("100ms\n"); 3766 break; 3767 default: 3768 printf("reserved\n"); 3769 break; 3770 } 3771 printf(" Power Allocation Scale: "); 3772 switch (PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_PAS)) { 3773 case 0: 3774 printf("10.0x\n"); 3775 break; 3776 case 1: 3777 printf("1.0x\n"); 3778 break; 3779 case 2: 3780 printf("0.1x\n"); 3781 break; 3782 case 3: 3783 printf("0.01x\n"); 3784 break; 3785 } 3786 printf(" Transition Latency Value 0: %u\n", 3787 PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_XLCY0)); 3788 printf(" Transition Latency Value 1: %u\n", 3789 PCIREG_SHIFTOUT(reg, PCI_DPA_CAP_XLCY1)); 3790 3791 reg = regs[o2i(extcapoff + PCI_DPA_LATIND)]; 3792 printf(" Latency Indicator register: 0x%08x\n", reg); 3793 3794 reg = regs[o2i(extcapoff + PCI_DPA_CS)]; 3795 printf(" Status register: 0x%04x\n", reg & 0xffff); 3796 printf(" Substate Status: 0x%02x\n", 3797 PCIREG_SHIFTOUT(reg, PCI_DPA_CS_SUBSTSTAT)); 3798 onoff("Substate Control Enabled", reg, PCI_DPA_CS_SUBSTCTLEN); 3799 printf(" Control register: 0x%04x\n", reg >> 16); 3800 printf(" Substate Control: 0x%02x\n", 3801 PCIREG_SHIFTOUT(reg, PCI_DPA_CS_SUBSTCTL)); 3802 3803 for (i = 0; i <= substmax; i++) 3804 printf(" Substate Power Allocation register %d: 0x%02x\n", 3805 i, (regs[PCI_DPA_PWRALLOC + (i / 4)] >> (i % 4) & 0xff)); 3806 } 3807 3808 static const char * 3809 pci_conf_print_tph_req_cap_sttabloc(uint8_t val) 3810 { 3811 3812 switch (val) { 3813 case PCI_TPH_REQ_STTBLLOC_NONE: 3814 return "Not Present"; 3815 case PCI_TPH_REQ_STTBLLOC_TPHREQ: 3816 return "in the TPH Requester Capability Structure"; 3817 case PCI_TPH_REQ_STTBLLOC_MSIX: 3818 return "in the MSI-X Table"; 3819 default: 3820 return "Unknown"; 3821 } 3822 } 3823 3824 static void 3825 pci_conf_print_tph_req_cap(const pcireg_t *regs, int extcapoff) 3826 { 3827 pcireg_t reg; 3828 int size = 0, i, j; 3829 uint8_t sttbloc; 3830 3831 printf("\n TPH Requester Extended Capability\n"); 3832 3833 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CAP)]; 3834 printf(" TPH Requester Capabililty register: 0x%08x\n", reg); 3835 onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST); 3836 onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC); 3837 onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC); 3838 onoff("Extend TPH Requester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ); 3839 sttbloc = PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC); 3840 printf(" ST Table Location: %s\n", 3841 pci_conf_print_tph_req_cap_sttabloc(sttbloc)); 3842 if (sttbloc == PCI_TPH_REQ_STTBLLOC_TPHREQ) { 3843 size = PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLSIZ) + 1; 3844 printf(" ST Table Size: %d\n", size); 3845 } 3846 3847 reg = regs[o2i(extcapoff + PCI_TPH_REQ_CTL)]; 3848 printf(" TPH Requester Control register: 0x%08x\n", reg); 3849 printf(" ST Mode Select: "); 3850 switch (PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CTL_STSEL)) { 3851 case PCI_TPH_REQ_CTL_STSEL_NO: 3852 printf("No ST Mode\n"); 3853 break; 3854 case PCI_TPH_REQ_CTL_STSEL_IV: 3855 printf("Interrupt Vector Mode\n"); 3856 break; 3857 case PCI_TPH_REQ_CTL_STSEL_DS: 3858 printf("Device Specific Mode\n"); 3859 break; 3860 default: 3861 printf("(reserved value)\n"); 3862 break; 3863 } 3864 printf(" TPH Requester Enable: "); 3865 switch (PCIREG_SHIFTOUT(reg, PCI_TPH_REQ_CTL_TPHREQEN)) { 3866 case PCI_TPH_REQ_CTL_TPHREQEN_NO: /* 0x0 */ 3867 printf("Not permitted\n"); 3868 break; 3869 case PCI_TPH_REQ_CTL_TPHREQEN_TPH: 3870 printf("TPH and not Extended TPH\n"); 3871 break; 3872 case PCI_TPH_REQ_CTL_TPHREQEN_ETPH: 3873 printf("TPH and Extended TPH"); 3874 break; 3875 default: 3876 printf("(reserved value)\n"); 3877 break; 3878 } 3879 3880 if (sttbloc != PCI_TPH_REQ_STTBLLOC_TPHREQ) 3881 return; 3882 3883 for (i = 0; i < size ; i += 2) { 3884 reg = regs[o2i(extcapoff + PCI_TPH_REQ_STTBL + i / 2)]; 3885 for (j = 0; j < 2 ; j++) { 3886 uint32_t entry = reg; 3887 3888 if (j != 0) 3889 entry >>= 16; 3890 entry &= 0xffff; 3891 printf(" TPH ST Table Entry (%d): 0x%04"PRIx32"\n", 3892 i + j, entry); 3893 } 3894 } 3895 } 3896 3897 static void 3898 pci_conf_print_ltr_cap(const pcireg_t *regs, int extcapoff) 3899 { 3900 pcireg_t reg; 3901 3902 printf("\n Latency Tolerance Reporting\n"); 3903 reg = regs[o2i(extcapoff + PCI_LTR_MAXSNOOPLAT)]; 3904 printf(" Max Snoop Latency Register: 0x%04x\n", reg & 0xffff); 3905 printf(" Max Snoop Latency: %juns\n", 3906 (uintmax_t)(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_VAL) 3907 * PCI_LTR_SCALETONS(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXSNOOPLAT_SCALE)))); 3908 printf(" Max No-Snoop Latency Register: 0x%04x\n", reg >> 16); 3909 printf(" Max No-Snoop Latency: %juns\n", 3910 (uintmax_t)(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_VAL) 3911 * PCI_LTR_SCALETONS(PCIREG_SHIFTOUT(reg, PCI_LTR_MAXNOSNOOPLAT_SCALE)))); 3912 } 3913 3914 static void 3915 pci_conf_print_sec_pcie_cap(const pcireg_t *regs, int extcapoff) 3916 { 3917 int pcie_capoff; 3918 pcireg_t reg; 3919 int i, maxlinkwidth; 3920 3921 printf("\n Secondary PCI Express Register\n"); 3922 3923 reg = regs[o2i(extcapoff + PCI_SECPCIE_LCTL3)]; 3924 printf(" Link Control 3 register: 0x%08x\n", reg); 3925 onoff("Perform Equalization", reg, PCI_SECPCIE_LCTL3_PERFEQ); 3926 onoff("Link Equalization Request Interrupt Enable", 3927 reg, PCI_SECPCIE_LCTL3_LINKEQREQ_IE); 3928 printf(" Enable Lower SKP OS Generation Vector:"); 3929 pci_print_pcie_linkspeedvector( 3930 PCIREG_SHIFTOUT(reg, PCI_SECPCIE_LCTL3_ELSKPOSGENV)); 3931 printf("\n"); 3932 3933 reg = regs[o2i(extcapoff + PCI_SECPCIE_LANEERR_STA)]; 3934 printf(" Lane Error Status register: 0x%08x\n", reg); 3935 3936 /* Get Max Link Width */ 3937 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 3938 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 3939 maxlinkwidth = PCIREG_SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 3940 } else { 3941 printf("error: failed to get PCIe capability\n"); 3942 return; 3943 } 3944 for (i = 0; i < maxlinkwidth; i++) { 3945 reg = regs[o2i(extcapoff + PCI_SECPCIE_EQCTL(i))]; 3946 if (i % 2 != 0) 3947 reg >>= 16; 3948 else 3949 reg &= 0xffff; 3950 printf(" Equalization Control Register (Link %d): 0x%04x\n", 3951 i, reg); 3952 printf(" Downstream Port Transmit Preset: 0x%x\n", 3953 PCIREG_SHIFTOUT(reg, 3954 PCI_SECPCIE_EQCTL_DP_XMIT_PRESET)); 3955 printf(" Downstream Port Receive Hint: 0x%x\n", 3956 PCIREG_SHIFTOUT(reg, PCI_SECPCIE_EQCTL_DP_RCV_HINT)); 3957 printf(" Upstream Port Transmit Preset: 0x%x\n", 3958 PCIREG_SHIFTOUT(reg, 3959 PCI_SECPCIE_EQCTL_UP_XMIT_PRESET)); 3960 printf(" Upstream Port Receive Hint: 0x%x\n", 3961 PCIREG_SHIFTOUT(reg, PCI_SECPCIE_EQCTL_UP_RCV_HINT)); 3962 } 3963 } 3964 3965 /* XXX pci_conf_print_pmux_cap */ 3966 3967 static void 3968 pci_conf_print_pasid_cap(const pcireg_t *regs, int extcapoff) 3969 { 3970 pcireg_t reg, cap, ctl; 3971 unsigned int num; 3972 3973 printf("\n Process Address Space ID\n"); 3974 3975 reg = regs[o2i(extcapoff + PCI_PASID_CAP)]; 3976 cap = reg & 0xffff; 3977 ctl = reg >> 16; 3978 printf(" PASID Capability Register: 0x%04x\n", cap); 3979 onoff("Execute Permission Supported", reg, PCI_PASID_CAP_XPERM); 3980 onoff("Privileged Mode Supported", reg, PCI_PASID_CAP_PRIVMODE); 3981 num = (1 << PCIREG_SHIFTOUT(reg, PCI_PASID_CAP_MAXPASIDW)) - 1; 3982 printf(" Max PASID Width: %u\n", num); 3983 3984 printf(" PASID Control Register: 0x%04x\n", ctl); 3985 onoff("PASID Enable", reg, PCI_PASID_CTL_PASID_EN); 3986 onoff("Execute Permission Enable", reg, PCI_PASID_CTL_XPERM_EN); 3987 onoff("Privileged Mode Enable", reg, PCI_PASID_CTL_PRIVMODE_EN); 3988 } 3989 3990 static void 3991 pci_conf_print_lnr_cap(const pcireg_t *regs, int extcapoff) 3992 { 3993 pcireg_t reg, cap, ctl; 3994 unsigned int num; 3995 3996 printf("\n LN Requester\n"); 3997 3998 reg = regs[o2i(extcapoff + PCI_LNR_CAP)]; 3999 cap = reg & 0xffff; 4000 ctl = reg >> 16; 4001 printf(" LNR Capability register: 0x%04x\n", cap); 4002 onoff("LNR-64 Supported", reg, PCI_LNR_CAP_64); 4003 onoff("LNR-128 Supported", reg, PCI_LNR_CAP_128); 4004 num = 1 << PCIREG_SHIFTOUT(reg, PCI_LNR_CAP_REGISTMAX); 4005 printf(" LNR Registration MAX: %u\n", num); 4006 4007 printf(" LNR Control register: 0x%04x\n", ctl); 4008 onoff("LNR Enable", reg, PCI_LNR_CTL_EN); 4009 onoff("LNR CLS", reg, PCI_LNR_CTL_CLS); 4010 num = 1 << PCIREG_SHIFTOUT(reg, PCI_LNR_CTL_REGISTLIM); 4011 printf(" LNR Registration Limit: %u\n", num); 4012 } 4013 4014 static void 4015 pci_conf_print_dpc_pio(pcireg_t r) 4016 { 4017 onoff("Cfg Request received UR Completion", r,PCI_DPC_RPPIO_CFGUR_CPL); 4018 onoff("Cfg Request received CA Completion", r,PCI_DPC_RPPIO_CFGCA_CPL); 4019 onoff("Cfg Request Completion Timeout", r, PCI_DPC_RPPIO_CFG_CTO); 4020 onoff("I/O Request received UR Completion", r, PCI_DPC_RPPIO_IOUR_CPL); 4021 onoff("I/O Request received CA Completion", r, PCI_DPC_RPPIO_IOCA_CPL); 4022 onoff("I/O Request Completion Timeout", r, PCI_DPC_RPPIO_IO_CTO); 4023 onoff("Mem Request received UR Completion", r,PCI_DPC_RPPIO_MEMUR_CPL); 4024 onoff("Mem Request received CA Completion", r,PCI_DPC_RPPIO_MEMCA_CPL); 4025 onoff("Mem Request Completion Timeout", r, PCI_DPC_RPPIO_MEM_CTO); 4026 } 4027 4028 static void 4029 pci_conf_print_dpc_cap(const pcireg_t *regs, int extcapoff) 4030 { 4031 pcireg_t reg, cap, ctl, stat, errsrc; 4032 const char *trigstr; 4033 bool rpext; 4034 4035 printf("\n Downstream Port Containment\n"); 4036 4037 reg = regs[o2i(extcapoff + PCI_DPC_CCR)]; 4038 cap = reg & 0xffff; 4039 ctl = reg >> 16; 4040 rpext = (reg & PCI_DPCCAP_RPEXT) ? true : false; 4041 printf(" DPC Capability register: 0x%04x\n", cap); 4042 printf(" DPC Interrupt Message Number: %02x\n", 4043 (unsigned int)(cap & PCI_DPCCAP_IMSGN)); 4044 onoff("RP Extensions for DPC", reg, PCI_DPCCAP_RPEXT); 4045 onoff("Poisoned TLP Egress Blocking Supported", reg, 4046 PCI_DPCCAP_POISONTLPEB); 4047 onoff("DPC Software Triggering Supported", reg, PCI_DPCCAP_SWTRIG); 4048 printf(" RP PIO Log Size: %u\n", 4049 PCIREG_SHIFTOUT(reg, PCI_DPCCAP_RPPIOLOGSZ)); 4050 onoff("DL_Active ERR_COR Signaling Supported", reg, 4051 PCI_DPCCAP_DLACTECORS); 4052 printf(" DPC Control register: 0x%04x\n", ctl); 4053 switch (PCIREG_SHIFTOUT(reg, PCI_DPCCTL_TIRGEN)) { 4054 case 0: 4055 trigstr = "disabled"; 4056 break; 4057 case 1: 4058 trigstr = "enabled(ERR_FATAL)"; 4059 break; 4060 case 2: 4061 trigstr = "enabled(ERR_NONFATAL or ERR_FATAL)"; 4062 break; 4063 default: 4064 trigstr = "(reserverd)"; 4065 break; 4066 } 4067 printf(" DPC Trigger Enable: %s\n", trigstr); 4068 printf(" DPC Completion Control: %s Completion Status\n", 4069 (reg & PCI_DPCCTL_COMPCTL) 4070 ? "Unsupported Request(UR)" : "Completer Abort(CA)"); 4071 onoff("DPC Interrupt Enable", reg, PCI_DPCCTL_IE); 4072 onoff("DPC ERR_COR Enable", reg, PCI_DPCCTL_ERRCOREN); 4073 onoff("Poisoned TLP Egress Blocking Enable", reg, 4074 PCI_DPCCTL_POISONTLPEB); 4075 onoff("DPC Software Trigger", reg, PCI_DPCCTL_SWTRIG); 4076 onoff("DL_Active ERR_COR Enable", reg, PCI_DPCCTL_DLACTECOR); 4077 4078 reg = regs[o2i(extcapoff + PCI_DPC_STATESID)]; 4079 stat = reg & 0xffff; 4080 errsrc = reg >> 16; 4081 printf(" DPC Status register: 0x%04x\n", stat); 4082 onoff("DPC Trigger Status", reg, PCI_DPCSTAT_TSTAT); 4083 switch (PCIREG_SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 4084 case 0: 4085 trigstr = "an unmasked uncorrectable error"; 4086 break; 4087 case 1: 4088 trigstr = "receiving an ERR_NONFATAL"; 4089 break; 4090 case 2: 4091 trigstr = "receiving an ERR_FATAL"; 4092 break; 4093 case 3: 4094 trigstr = "DPC Trigger Reason Extension field"; 4095 break; 4096 } 4097 printf(" DPC Trigger Reason: Due to %s\n", trigstr); 4098 onoff("DPC Interrupt Status", reg, PCI_DPCSTAT_ISTAT); 4099 if (rpext) 4100 onoff("DPC RP Busy", reg, PCI_DPCSTAT_RPBUSY); 4101 switch (PCIREG_SHIFTOUT(reg, PCI_DPCSTAT_TREASON)) { 4102 case 0: 4103 trigstr = "Due to RP PIO error"; 4104 break; 4105 case 1: 4106 trigstr = "Due to the DPC Software trigger bit"; 4107 break; 4108 default: 4109 trigstr = "(reserved)"; 4110 break; 4111 } 4112 printf(" DPC Trigger Reason Extension: %s\n", trigstr); 4113 if (rpext) 4114 printf(" RP PIO First Error Pointer: 0x%02x\n", 4115 PCIREG_SHIFTOUT(reg, PCI_DPCSTAT_RPPIOFEP)); 4116 printf(" DPC Error Source ID register: 0x%04x\n", errsrc); 4117 4118 if (!rpext) 4119 return; 4120 /* 4121 * All of the following registers are implemented by a device which has 4122 * RP Extensions for DPC 4123 */ 4124 4125 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_STAT)]; 4126 printf(" RP PIO Status Register: 0x%08x\n", reg); 4127 pci_conf_print_dpc_pio(reg); 4128 4129 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_MASK)]; 4130 printf(" RP PIO Mask Register: 0x%08x\n", reg); 4131 pci_conf_print_dpc_pio(reg); 4132 4133 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SEVE)]; 4134 printf(" RP PIO Severity Register: 0x%08x\n", reg); 4135 pci_conf_print_dpc_pio(reg); 4136 4137 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SYSERR)]; 4138 printf(" RP PIO SysError Register: 0x%08x\n", reg); 4139 pci_conf_print_dpc_pio(reg); 4140 4141 reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_EXCPT)]; 4142 printf(" RP PIO Exception Register: 0x%08x\n", reg); 4143 pci_conf_print_dpc_pio(reg); 4144 4145 printf(" RP PIO Header Log Register: start from 0x%03x\n", 4146 extcapoff + PCI_DPC_RPPIO_HLOG); 4147 printf(" RP PIO ImpSpec Log Register: start from 0x%03x\n", 4148 extcapoff + PCI_DPC_RPPIO_IMPSLOG); 4149 printf(" RP PIO TLP Prefix Log Register: start from 0x%03x\n", 4150 extcapoff + PCI_DPC_RPPIO_TLPPLOG); 4151 } 4152 4153 4154 static int 4155 pci_conf_l1pm_cap_tposcale(unsigned char scale) 4156 { 4157 4158 /* Return scale in us */ 4159 switch (scale) { 4160 case 0x0: 4161 return 2; 4162 case 0x1: 4163 return 10; 4164 case 0x2: 4165 return 100; 4166 default: 4167 return -1; 4168 } 4169 } 4170 4171 static void 4172 pci_conf_print_l1pm_cap(const pcireg_t *regs, int extcapoff) 4173 { 4174 pcireg_t reg; 4175 int scale, val; 4176 int pcie_capoff; 4177 4178 printf("\n L1 PM Substates\n"); 4179 4180 reg = regs[o2i(extcapoff + PCI_L1PM_CAP)]; 4181 printf(" L1 PM Substates Capability register: 0x%08x\n", reg); 4182 onoff("PCI-PM L1.2 Supported", reg, PCI_L1PM_CAP_PCIPM12); 4183 onoff("PCI-PM L1.1 Supported", reg, PCI_L1PM_CAP_PCIPM11); 4184 onoff("ASPM L1.2 Supported", reg, PCI_L1PM_CAP_ASPM12); 4185 onoff("ASPM L1.1 Supported", reg, PCI_L1PM_CAP_ASPM11); 4186 onoff("L1 PM Substates Supported", reg, PCI_L1PM_CAP_L1PM); 4187 /* The Link Activation Supported bit is only for Downstream Port */ 4188 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) { 4189 uint32_t t = regs[o2i(pcie_capoff)]; 4190 4191 if ((t == PCIE_XCAP_TYPE_RP) || (t == PCIE_XCAP_TYPE_DOWN)) 4192 onoff("Link Activation Supported", reg, 4193 PCI_L1PM_CAP_LA); 4194 } 4195 printf(" Port Common Mode Restore Time: %uus\n", 4196 PCIREG_SHIFTOUT(reg, PCI_L1PM_CAP_PCMRT)); 4197 scale = pci_conf_l1pm_cap_tposcale( 4198 PCIREG_SHIFTOUT(reg, PCI_L1PM_CAP_PTPOSCALE)); 4199 val = PCIREG_SHIFTOUT(reg, PCI_L1PM_CAP_PTPOVAL); 4200 printf(" Port T_POWER_ON: "); 4201 if (scale == -1) 4202 printf("unknown\n"); 4203 else 4204 printf("%dus\n", val * scale); 4205 4206 reg = regs[o2i(extcapoff + PCI_L1PM_CTL1)]; 4207 printf(" L1 PM Substates Control register 1: 0x%08x\n", reg); 4208 onoff("PCI-PM L1.2 Enable", reg, PCI_L1PM_CTL1_PCIPM12_EN); 4209 onoff("PCI-PM L1.1 Enable", reg, PCI_L1PM_CTL1_PCIPM11_EN); 4210 onoff("ASPM L1.2 Enable", reg, PCI_L1PM_CTL1_ASPM12_EN); 4211 onoff("ASPM L1.1 Enable", reg, PCI_L1PM_CTL1_ASPM11_EN); 4212 onoff("Link Activation Interrupt Enable", reg, PCI_L1PM_CTL1_LAIE); 4213 onoff("Link Activation Control", reg, PCI_L1PM_CTL1_LA); 4214 printf(" Common Mode Restore Time: %uus\n", 4215 PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL1_CMRT)); 4216 scale = PCI_LTR_SCALETONS(PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHSCALE)); 4217 val = PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL1_LTRTHVAL); 4218 printf(" LTR L1.2 THRESHOLD: %dus\n", val * scale); 4219 4220 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 4221 printf(" L1 PM Substates Control register 2: 0x%08x\n", reg); 4222 scale = pci_conf_l1pm_cap_tposcale( 4223 PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL2_TPOSCALE)); 4224 val = PCIREG_SHIFTOUT(reg, PCI_L1PM_CTL2_TPOVAL); 4225 printf(" T_POWER_ON: "); 4226 if (scale == -1) 4227 printf("unknown\n"); 4228 else 4229 printf("%dus\n", val * scale); 4230 4231 if (PCI_EXTCAPLIST_VERSION(regs[o2i(extcapoff)]) >= 2) { 4232 reg = regs[o2i(extcapoff + PCI_L1PM_CTL2)]; 4233 printf(" L1 PM Substates Status register: 0x%08x\n", reg); 4234 onoff("Link Activation Status", reg, PCI_L1PM_STAT_LA); 4235 } 4236 } 4237 4238 static void 4239 pci_conf_print_ptm_cap(const pcireg_t *regs, int extcapoff) 4240 { 4241 pcireg_t reg; 4242 uint32_t val; 4243 4244 printf("\n Precision Time Measurement\n"); 4245 4246 reg = regs[o2i(extcapoff + PCI_PTM_CAP)]; 4247 printf(" PTM Capability register: 0x%08x\n", reg); 4248 onoff("PTM Requester Capable", reg, PCI_PTM_CAP_REQ); 4249 onoff("PTM Responder Capable", reg, PCI_PTM_CAP_RESP); 4250 onoff("PTM Root Capable", reg, PCI_PTM_CAP_ROOT); 4251 printf(" Local Clock Granularity: "); 4252 val = PCIREG_SHIFTOUT(reg, PCI_PTM_CAP_LCLCLKGRNL); 4253 switch (val) { 4254 case 0: 4255 printf("Not implemented\n"); 4256 break; 4257 case 0xffff: 4258 printf("> 254ns\n"); 4259 break; 4260 default: 4261 printf("%uns\n", val); 4262 break; 4263 } 4264 4265 reg = regs[o2i(extcapoff + PCI_PTM_CTL)]; 4266 printf(" PTM Control register: 0x%08x\n", reg); 4267 onoff("PTM Enable", reg, PCI_PTM_CTL_EN); 4268 onoff("Root Select", reg, PCI_PTM_CTL_ROOTSEL); 4269 printf(" Effective Granularity: "); 4270 val = PCIREG_SHIFTOUT(reg, PCI_PTM_CTL_EFCTGRNL); 4271 switch (val) { 4272 case 0: 4273 printf("Unknown\n"); 4274 break; 4275 case 0xffff: 4276 printf("> 254ns\n"); 4277 break; 4278 default: 4279 printf("%uns\n", val); 4280 break; 4281 } 4282 } 4283 4284 /* XXX pci_conf_print_mpcie_cap */ 4285 /* XXX pci_conf_print_frsq_cap */ 4286 /* XXX pci_conf_print_rtr_cap */ 4287 /* XXX pci_conf_print_desigvndsp_cap */ 4288 /* XXX pci_conf_print_vf_resizbar_cap */ 4289 4290 static void 4291 pci_conf_print_dlf_cap(const pcireg_t *regs, int extcapoff) 4292 { 4293 pcireg_t reg; 4294 4295 printf("\n Data link Feature Register\n"); 4296 reg = regs[o2i(extcapoff + PCI_DLF_CAP)]; 4297 printf(" Capability register: 0x%08x\n", reg); 4298 onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL); 4299 onoff("DLF Exchange enable", reg, PCI_DLF_CAP_XCHG); 4300 4301 reg = regs[o2i(extcapoff + PCI_DLF_STAT)]; 4302 printf(" Status register: 0x%08x\n", reg); 4303 onoff("Scaled Flow Control", reg, PCI_DLF_LFEAT_SCLFCTL); 4304 onoff("Remote DLF supported Valid", reg, PCI_DLF_STAT_RMTVALID); 4305 } 4306 4307 static void 4308 pci_conf_print_pl16g_cap(const pcireg_t *regs, int extcapoff) 4309 { 4310 pcireg_t reg, lwidth; 4311 int pcie_capoff; 4312 unsigned int i, j; 4313 4314 printf("\n Physical Layer 16.0 GT/s\n"); 4315 reg = regs[o2i(extcapoff + PCI_PL16G_CAP)]; 4316 printf(" Capability register: 0x%08x\n", reg); 4317 4318 reg = regs[o2i(extcapoff + PCI_PL16G_CTL)]; 4319 printf(" Control register: 0x%08x\n", reg); 4320 4321 reg = regs[o2i(extcapoff + PCI_PL16G_STAT)]; 4322 printf(" Status register: 0x%08x\n", reg); 4323 onoff("Equalization 16.0 GT/s Complete", reg, PCI_PL16G_STAT_EQ_COMPL); 4324 onoff("Equalization 16.0 GT/s Phase 1 Successful", reg, 4325 PCI_PL16G_STAT_EQ_P1S); 4326 onoff("Equalization 16.0 GT/s Phase 2 Successful", reg, 4327 PCI_PL16G_STAT_EQ_P2S); 4328 onoff("Equalization 16.0 GT/s Phase 3 Successful", reg, 4329 PCI_PL16G_STAT_EQ_P3S); 4330 4331 reg = regs[o2i(extcapoff + PCI_PL16G_LDPMS)]; 4332 printf(" Local Data Parity Mismatch Status register: 0x%08x\n", 4333 reg); 4334 4335 reg = regs[o2i(extcapoff + PCI_PL16G_FRDPMS)]; 4336 printf(" First Retimer Data Parity Mismatch Status register:" 4337 " 0x%08x\n", reg); 4338 4339 reg = regs[o2i(extcapoff + PCI_PL16G_SRDPMS)]; 4340 printf(" Second Retimer Data Parity Mismatch Status register:" 4341 " 0x%08x\n", reg); 4342 4343 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff) == 0) 4344 return; /* error */ 4345 4346 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 4347 lwidth = PCIREG_SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 4348 4349 for (i = 0; i < lwidth;) { 4350 reg = regs[o2i(extcapoff + PCI_PL16G_LEC + i)]; 4351 4352 for (j = 0; j < 4; j++) { 4353 pcireg_t up, down; 4354 4355 down = reg & 0x0000000f; 4356 up = (reg >> 4) & 0x0000000f; 4357 printf(" Lane %d downstream: ", i); 4358 pci_print_pcie_link_preset_preshoot_deemphasis(down); 4359 printf("\n Lane %d upstream: ", i); 4360 pci_print_pcie_link_preset_preshoot_deemphasis(up); 4361 printf("\n"); 4362 4363 reg >>= 8; 4364 i++; 4365 if (i >= lwidth) 4366 break; 4367 } 4368 } 4369 } 4370 4371 static const char * const pcie_receive_number_dp[] = { 4372 [0] = ("Broadcast " 4373 "(Downstream Port Receiver and all Retimer Pseudo Port Receiver)"), 4374 [1] = "Rx(A) (Downstream Port Receiver)", 4375 [2] = "Rx(B) (Retimer X or Z Upstream Pseudo Port Receiver)", 4376 [3] = "Rx(C) (Retimer X or Z Downstream Pseudo Port Receiver)", 4377 [4] = "Rx(D) (Retimer Y Upstream Pseudo Port Receiver)", 4378 [5] = "Rx(E) (Retimer Y Downstream Pseudo Port Receiver)", 4379 [6] = "Reserved", 4380 [7] = "Reserved" 4381 }; 4382 4383 static const char * const pcie_receive_number_up[] = { 4384 "Broadcast (Upstream Port Receiver)", 4385 "Reserved", 4386 "Reserved", 4387 "Reserved", 4388 "Reserved", 4389 "Reserved", 4390 "Rx(F) (Upstream Port Receiver)", 4391 "Reserved" 4392 }; 4393 4394 /* 4395 * Print PCI_LMR_LANECSR. This function is used for both control and status 4396 * register. The reg argument in the lower 16bit has the control or status 4397 * register. The encoding is the same except the receive number, so use _LCTL_ 4398 * macro. 4399 */ 4400 static void 4401 pci_conf_print_lmr_lcsr(pcireg_t reg, bool up, bool dp) 4402 { 4403 int rnum; 4404 4405 printf(" Receive Number: "); 4406 rnum = PCIREG_SHIFTOUT(reg, PCI_LMR_LCTL_RNUM); 4407 if (up) 4408 printf("%s\n", pcie_receive_number_up[rnum]); 4409 else if (dp) 4410 printf("%s\n", pcie_receive_number_dp[rnum]); 4411 else 4412 printf("%x\n", rnum); 4413 4414 printf(" Margin Type: %x\n", 4415 PCIREG_SHIFTOUT(reg, PCI_LMR_LCTL_MTYPE)); 4416 printf(" Usage Model: %s\n", 4417 (PCIREG_SHIFTOUT(reg, PCI_LMR_LCTL_UMODEL) == 0) 4418 ? "Lane Margining at Receiver" : "Reserved Encoding"); 4419 printf(" Margin Payload: 0x%02x\n", 4420 PCIREG_SHIFTOUT(reg, PCI_LMR_LCTL_MPAYLOAD)); 4421 } 4422 4423 static void 4424 pci_conf_print_lmr_cap(const pcireg_t *regs, int extcapoff) 4425 { 4426 pcireg_t reg, lwidth; 4427 int pcie_capoff; 4428 int pcie_devtype; 4429 unsigned int i; 4430 bool up, dp; 4431 4432 printf("\n Lane Margining at the Receiver\n"); 4433 reg = regs[o2i(extcapoff + PCI_LMR_PCAPSTAT)]; 4434 printf(" Port Capability register: 0x%04x\n", reg & 0xffff); 4435 onoff("Margining uses Driver Software", reg, PCI_LMR_PCAP_MUDS); 4436 printf(" Port Status register: 0x%04x\n", (reg >> 16) & 0xffff); 4437 onoff("Margining Ready", reg, PCI_LMR_PSTAT_MR); 4438 onoff("Margining Software Ready", reg, PCI_LMR_PSTAT_MSR); 4439 4440 if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff) == 0) 4441 return; /* error */ 4442 4443 up = dp = false; 4444 reg = regs[o2i(pcie_capoff)]; 4445 pcie_devtype = PCIE_XCAP_TYPE(reg); 4446 switch (pcie_devtype) { 4447 case PCIE_XCAP_TYPE_PCIE_DEV: /* 0x0 */ 4448 case PCIE_XCAP_TYPE_PCI_DEV: /* 0x1 */ 4449 case PCIE_XCAP_TYPE_UP: /* 0x5 */ 4450 case PCIE_XCAP_TYPE_PCIE2PCI: /* 0x7 */ 4451 up = true; 4452 break; 4453 case PCIE_XCAP_TYPE_RP: /* 0x4 */ 4454 case PCIE_XCAP_TYPE_DOWN: /* 0x6 */ 4455 dp = true; 4456 break; 4457 default: 4458 printf("neither upstream nor downstream?(%x)\n", pcie_devtype); 4459 break; 4460 } 4461 4462 reg = regs[o2i(pcie_capoff + PCIE_LCAP)]; 4463 lwidth = PCIREG_SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH); 4464 4465 for (i = 0; i < lwidth; i++) { 4466 pcireg_t lctl, lstat; 4467 4468 reg = regs[o2i(extcapoff + PCI_LMR_LANECSR + (i * 4))]; 4469 4470 lctl = reg & 0xffff; 4471 printf(" Lane %d control: 0x%04x\n", i, lctl); 4472 pci_conf_print_lmr_lcsr(lctl, up, dp); 4473 4474 lstat = (reg >> 16) & 0xffff; 4475 printf(" Lane %d status: 0x%04x\n", i, lstat); 4476 pci_conf_print_lmr_lcsr(lstat, up, dp); 4477 } 4478 } 4479 4480 /* XXX pci_conf_print_hierarchyid_cap */ 4481 /* XXX pci_conf_print_npem_cap */ 4482 4483 #undef MS 4484 #undef SM 4485 #undef RW 4486 4487 static struct { 4488 pcireg_t cap; 4489 const char *name; 4490 void (*printfunc)(const pcireg_t *, int); 4491 } pci_extcaptab[] = { 4492 { 0, "reserved", 4493 NULL }, 4494 { PCI_EXTCAP_AER, "Advanced Error Reporting", 4495 pci_conf_print_aer_cap }, 4496 { PCI_EXTCAP_VC, "Virtual Channel", 4497 pci_conf_print_vc_cap }, 4498 { PCI_EXTCAP_SERNUM, "Device Serial Number", 4499 pci_conf_print_sernum_cap }, 4500 { PCI_EXTCAP_PWRBDGT, "Power Budgeting", 4501 pci_conf_print_pwrbdgt_cap }, 4502 { PCI_EXTCAP_RCLINK_DCL,"Root Complex Link Declaration", 4503 pci_conf_print_rclink_dcl_cap }, 4504 { PCI_EXTCAP_RCLINK_CTL,"Root Complex Internal Link Control", 4505 NULL }, 4506 { PCI_EXTCAP_RCEC_ASSOC,"Root Complex Event Collector Association", 4507 pci_conf_print_rcec_assoc_cap }, 4508 { PCI_EXTCAP_MFVC, "Multi-Function Virtual Channel", 4509 NULL }, 4510 { PCI_EXTCAP_VC2, "Virtual Channel", 4511 NULL }, 4512 { PCI_EXTCAP_RCRB, "RCRB Header", 4513 NULL }, 4514 { PCI_EXTCAP_VENDOR, "Vendor Unique", 4515 NULL }, 4516 { PCI_EXTCAP_CAC, "Configuration Access Correction", 4517 NULL }, 4518 { PCI_EXTCAP_ACS, "Access Control Services", 4519 pci_conf_print_acs_cap }, 4520 { PCI_EXTCAP_ARI, "Alternative Routing-ID Interpretation", 4521 pci_conf_print_ari_cap }, 4522 { PCI_EXTCAP_ATS, "Address Translation Services", 4523 pci_conf_print_ats_cap }, 4524 { PCI_EXTCAP_SRIOV, "Single Root IO Virtualization", 4525 pci_conf_print_sriov_cap }, 4526 { PCI_EXTCAP_MRIOV, "Multiple Root IO Virtualization", 4527 NULL }, 4528 { PCI_EXTCAP_MCAST, "Multicast", 4529 pci_conf_print_multicast_cap }, 4530 { PCI_EXTCAP_PAGE_REQ, "Page Request", 4531 pci_conf_print_page_req_cap }, 4532 { PCI_EXTCAP_AMD, "Reserved for AMD", 4533 NULL }, 4534 { PCI_EXTCAP_RESIZBAR, "Resizable BAR", 4535 pci_conf_print_resizbar_cap }, 4536 { PCI_EXTCAP_DPA, "Dynamic Power Allocation", 4537 pci_conf_print_dpa_cap }, 4538 { PCI_EXTCAP_TPH_REQ, "TPH Requester", 4539 pci_conf_print_tph_req_cap }, 4540 { PCI_EXTCAP_LTR, "Latency Tolerance Reporting", 4541 pci_conf_print_ltr_cap }, 4542 { PCI_EXTCAP_SEC_PCIE, "Secondary PCI Express", 4543 pci_conf_print_sec_pcie_cap }, 4544 { PCI_EXTCAP_PMUX, "Protocol Multiplexing", 4545 NULL }, 4546 { PCI_EXTCAP_PASID, "Process Address Space ID", 4547 pci_conf_print_pasid_cap }, 4548 { PCI_EXTCAP_LNR, "LN Requester", 4549 pci_conf_print_lnr_cap }, 4550 { PCI_EXTCAP_DPC, "Downstream Port Containment", 4551 pci_conf_print_dpc_cap }, 4552 { PCI_EXTCAP_L1PM, "L1 PM Substates", 4553 pci_conf_print_l1pm_cap }, 4554 { PCI_EXTCAP_PTM, "Precision Time Measurement", 4555 pci_conf_print_ptm_cap }, 4556 { PCI_EXTCAP_MPCIE, "M-PCIe", 4557 NULL }, 4558 { PCI_EXTCAP_FRSQ, "Function Reading Status Queueing", 4559 NULL }, 4560 { PCI_EXTCAP_RTR, "Readiness Time Reporting", 4561 NULL }, 4562 { PCI_EXTCAP_DESIGVNDSP, "Designated Vendor-Specific", 4563 NULL }, 4564 { PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs", 4565 NULL }, 4566 { PCI_EXTCAP_DLF, "Data link Feature", pci_conf_print_dlf_cap }, 4567 { PCI_EXTCAP_PL16G, "Physical Layer 16.0 GT/s", 4568 pci_conf_print_pl16g_cap }, 4569 { PCI_EXTCAP_LMR, "Lane Margining at the Receiver", 4570 pci_conf_print_lmr_cap }, 4571 { PCI_EXTCAP_HIERARCHYID, "Hierarchy ID", 4572 NULL }, 4573 { PCI_EXTCAP_NPEM, "Native PCIe Enclosure Management", 4574 NULL }, 4575 { PCI_EXTCAP_PL32G, "Physical Layer 32.0 GT/s", 4576 NULL }, 4577 { PCI_EXTCAP_AP, "Alternate Protocol", 4578 NULL }, 4579 { PCI_EXTCAP_SFI, "System Firmware Intermediary", 4580 NULL }, 4581 }; 4582 4583 static int 4584 pci_conf_find_extcap(const pcireg_t *regs, unsigned int capid, int *offsetp) 4585 { 4586 int off; 4587 pcireg_t rval; 4588 4589 for (off = PCI_EXTCAPLIST_BASE; 4590 off != 0; 4591 off = PCI_EXTCAPLIST_NEXT(rval)) { 4592 rval = regs[o2i(off)]; 4593 if (capid == PCI_EXTCAPLIST_CAP(rval)) { 4594 if (offsetp != NULL) 4595 *offsetp = off; 4596 return 1; 4597 } 4598 } 4599 return 0; 4600 } 4601 4602 static void 4603 pci_conf_print_extcaplist( 4604 #ifdef _KERNEL 4605 pci_chipset_tag_t pc, pcitag_t tag, 4606 #endif 4607 const pcireg_t *regs) 4608 { 4609 int off; 4610 pcireg_t foundcap; 4611 pcireg_t rval; 4612 bool foundtable[__arraycount(pci_extcaptab)]; 4613 unsigned int i; 4614 4615 /* Check Extended capability structure */ 4616 off = PCI_EXTCAPLIST_BASE; 4617 rval = regs[o2i(off)]; 4618 if (rval == 0xffffffff || rval == 0) 4619 return; 4620 4621 /* Clear table */ 4622 for (i = 0; i < __arraycount(pci_extcaptab); i++) 4623 foundtable[i] = false; 4624 4625 /* Print extended capability register's offset and the type first */ 4626 for (;;) { 4627 printf(" Extended Capability Register at 0x%02x\n", off); 4628 4629 foundcap = PCI_EXTCAPLIST_CAP(rval); 4630 printf(" type: 0x%04x (", foundcap); 4631 if (foundcap < __arraycount(pci_extcaptab)) { 4632 printf("%s)\n", pci_extcaptab[foundcap].name); 4633 /* Mark as found */ 4634 foundtable[foundcap] = true; 4635 } else 4636 printf("unknown)\n"); 4637 printf(" version: %d\n", PCI_EXTCAPLIST_VERSION(rval)); 4638 4639 off = PCI_EXTCAPLIST_NEXT(rval); 4640 if (off == 0) 4641 break; 4642 else if (off <= PCI_CONF_SIZE) { 4643 printf(" next pointer: 0x%03x (incorrect)\n", off); 4644 return; 4645 } 4646 rval = regs[o2i(off)]; 4647 } 4648 4649 /* 4650 * And then, print the detail of each capability registers 4651 * in capability value's order. 4652 */ 4653 for (i = 0; i < __arraycount(pci_extcaptab); i++) { 4654 if (foundtable[i] == false) 4655 continue; 4656 4657 /* 4658 * The type was found. Search capability list again and 4659 * print all capabilities that the capability type is 4660 * the same. 4661 */ 4662 if (pci_conf_find_extcap(regs, i, &off) == 0) 4663 continue; 4664 rval = regs[o2i(off)]; 4665 if ((PCI_EXTCAPLIST_VERSION(rval) <= 0) 4666 || (pci_extcaptab[i].printfunc == NULL)) 4667 continue; 4668 4669 pci_extcaptab[i].printfunc(regs, off); 4670 4671 } 4672 } 4673 4674 /* Print the Secondary Status Register. */ 4675 static void 4676 pci_conf_print_ssr(pcireg_t rval) 4677 { 4678 pcireg_t devsel; 4679 4680 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 4681 onoff("66 MHz capable", rval, __BIT(5)); 4682 onoff("User Definable Features (UDF) support", rval, __BIT(6)); 4683 onoff("Fast back-to-back capable", rval, __BIT(7)); 4684 onoff("Data parity error detected", rval, __BIT(8)); 4685 4686 printf(" DEVSEL timing: "); 4687 devsel = PCIREG_SHIFTOUT(rval, __BITS(10, 9)); 4688 switch (devsel) { 4689 case 0: 4690 printf("fast"); 4691 break; 4692 case 1: 4693 printf("medium"); 4694 break; 4695 case 2: 4696 printf("slow"); 4697 break; 4698 default: 4699 printf("unknown/reserved"); /* XXX */ 4700 break; 4701 } 4702 printf(" (0x%x)\n", devsel); 4703 4704 onoff("Signalled target abort", rval, __BIT(11)); 4705 onoff("Received target abort", rval, __BIT(12)); 4706 onoff("Received master abort", rval, __BIT(13)); 4707 onoff("Received system error", rval, __BIT(14)); 4708 onoff("Detected parity error", rval, __BIT(15)); 4709 } 4710 4711 static void 4712 pci_conf_print_type0( 4713 #ifdef _KERNEL 4714 pci_chipset_tag_t pc, pcitag_t tag, 4715 #endif 4716 const pcireg_t *regs) 4717 { 4718 int off, width; 4719 pcireg_t rval; 4720 const char *str; 4721 4722 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 4723 #ifdef _KERNEL 4724 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4725 #else 4726 width = pci_conf_print_bar(regs, off, NULL); 4727 #endif 4728 } 4729 4730 printf(" Cardbus CIS Pointer: 0x%08x\n", 4731 regs[o2i(PCI_CARDBUS_CIS_REG)]); 4732 4733 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 4734 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 4735 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 4736 4737 rval = regs[o2i(PCI_MAPREG_ROM)]; 4738 printf(" Expansion ROM Base Address Register: 0x%08x\n", rval); 4739 printf(" base: 0x%08x\n", (uint32_t)PCI_MAPREG_ROM_ADDR(rval)); 4740 onoff("Expansion ROM Enable", rval, PCI_MAPREG_ROM_ENABLE); 4741 printf(" Validation Status: "); 4742 switch (PCIREG_SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_STAT)) { 4743 case PCI_MAPREG_ROM_VSTAT_NOTSUPP: 4744 str = "Validation not supported"; 4745 break; 4746 case PCI_MAPREG_ROM_VSTAT_INPROG: 4747 str = "Validation in Progress"; 4748 break; 4749 case PCI_MAPREG_ROM_VSTAT_VPASS: 4750 str = "Validation Pass. " 4751 "Valid contents, trust test was not performed"; 4752 break; 4753 case PCI_MAPREG_ROM_VSTAT_VPASSTRUST: 4754 str = "Validation Pass. Valid and trusted contents"; 4755 break; 4756 case PCI_MAPREG_ROM_VSTAT_VFAIL: 4757 str = "Validation Fail. Invalid contents"; 4758 break; 4759 case PCI_MAPREG_ROM_VSTAT_VFAILUNTRUST: 4760 str = "Validation Fail. Valid but untrusted contents"; 4761 break; 4762 case PCI_MAPREG_ROM_VSTAT_WPASS: 4763 str = "Warning Pass. Validation passed with warning. " 4764 "Valid contents, trust test was not performed"; 4765 break; 4766 case PCI_MAPREG_ROM_VSTAT_WPASSTRUST: 4767 str = "Warning Pass. Validation passed with warning. " 4768 "Valid and trusted contents"; 4769 break; 4770 } 4771 printf("%s\n", str); 4772 printf(" Validation Details: 0x%x\n", 4773 PCIREG_SHIFTOUT(rval, PCI_MAPREG_ROM_VALID_DETAIL)); 4774 4775 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 4776 printf(" Capability list pointer: 0x%02x\n", 4777 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4778 else 4779 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4780 4781 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 4782 4783 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4784 printf(" Maximum Latency: 0x%02x\n", PCI_MAX_LAT(rval)); 4785 printf(" Minimum Grant: 0x%02x\n", PCI_MIN_GNT(rval)); 4786 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 4787 switch (PCI_INTERRUPT_PIN(rval)) { 4788 case PCI_INTERRUPT_PIN_NONE: 4789 printf("(none)"); 4790 break; 4791 case PCI_INTERRUPT_PIN_A: 4792 printf("(pin A)"); 4793 break; 4794 case PCI_INTERRUPT_PIN_B: 4795 printf("(pin B)"); 4796 break; 4797 case PCI_INTERRUPT_PIN_C: 4798 printf("(pin C)"); 4799 break; 4800 case PCI_INTERRUPT_PIN_D: 4801 printf("(pin D)"); 4802 break; 4803 default: 4804 printf("(? ? ?)"); 4805 break; 4806 } 4807 printf("\n"); 4808 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 4809 } 4810 4811 static void 4812 pci_conf_print_type1( 4813 #ifdef _KERNEL 4814 pci_chipset_tag_t pc, pcitag_t tag, 4815 #endif 4816 const pcireg_t *regs) 4817 { 4818 int off, width; 4819 pcireg_t rval, csreg; 4820 uint32_t base, limit; 4821 uint32_t base_h, limit_h; 4822 uint64_t pbase, plimit; 4823 int use_upper; 4824 4825 /* 4826 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 4827 * Bridge chip documentation, and may not be correct with 4828 * respect to various standards. (XXX) 4829 */ 4830 4831 for (off = 0x10; off < 0x18; off += width) { 4832 #ifdef _KERNEL 4833 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 4834 #else 4835 width = pci_conf_print_bar(regs, off, NULL); 4836 #endif 4837 } 4838 4839 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 4840 printf(" Primary bus number: 0x%02x\n", 4841 PCI_BRIDGE_BUS_NUM_PRIMARY(rval)); 4842 printf(" Secondary bus number: 0x%02x\n", 4843 PCI_BRIDGE_BUS_NUM_SECONDARY(rval)); 4844 printf(" Subordinate bus number: 0x%02x\n", 4845 PCI_BRIDGE_BUS_NUM_SUBORDINATE(rval)); 4846 printf(" Secondary bus latency timer: 0x%02x\n", 4847 PCI_BRIDGE_BUS_SEC_LATTIMER_VAL(rval)); 4848 4849 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 4850 pci_conf_print_ssr(PCIREG_SHIFTOUT(rval, __BITS(31, 16))); 4851 4852 /* I/O region */ 4853 printf(" I/O region:\n"); 4854 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 4855 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 4856 if (PCI_BRIDGE_IO_32BITS(rval)) 4857 use_upper = 1; 4858 else 4859 use_upper = 0; 4860 onoff("32bit I/O", rval, use_upper); 4861 base = PCI_BRIDGE_STATIO_IOBASE_ADDR(rval); 4862 limit = PCI_BRIDGE_STATIO_IOLIMIT_ADDR(rval); 4863 4864 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 4865 base_h = PCIREG_SHIFTOUT(rval, PCI_BRIDGE_IOHIGH_BASE); 4866 limit_h = PCIREG_SHIFTOUT(rval, PCI_BRIDGE_IOHIGH_LIMIT); 4867 printf(" base upper 16 bits register: 0x%04x\n", base_h); 4868 printf(" limit upper 16 bits register: 0x%04x\n", limit_h); 4869 4870 if (use_upper == 1) { 4871 base |= base_h << 16; 4872 limit |= limit_h << 16; 4873 } 4874 if (base < limit) { 4875 if (use_upper == 1) 4876 printf(" range: 0x%08x-0x%08x\n", base, limit); 4877 else 4878 printf(" range: 0x%04x-0x%04x\n", base, limit); 4879 } else 4880 printf(" range: not set\n"); 4881 4882 /* Non-prefetchable memory region */ 4883 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 4884 printf(" Memory region:\n"); 4885 printf(" base register: 0x%04hx\n", 4886 (uint16_t)PCIREG_SHIFTOUT(rval, PCI_BRIDGE_MEMORY_BASE)); 4887 printf(" limit register: 0x%04hx\n", 4888 (uint16_t)PCIREG_SHIFTOUT(rval, PCI_BRIDGE_MEMORY_LIMIT)); 4889 base = PCI_BRIDGE_MEMORY_BASE_ADDR(rval); 4890 limit = PCI_BRIDGE_MEMORY_LIMIT_ADDR(rval); 4891 if (base < limit) 4892 printf(" range: 0x%08x-0x%08x\n", base, limit); 4893 else 4894 printf(" range: not set\n"); 4895 4896 /* Prefetchable memory region */ 4897 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 4898 printf(" Prefetchable memory region:\n"); 4899 printf(" base register: 0x%04x\n", 4900 (rval >> 0) & 0xffff); 4901 printf(" limit register: 0x%04x\n", 4902 (rval >> 16) & 0xffff); 4903 base_h = regs[o2i(PCI_BRIDGE_PREFETCHBASEUP32_REG)]; 4904 limit_h = regs[o2i(PCI_BRIDGE_PREFETCHLIMITUP32_REG)]; 4905 printf(" base upper 32 bits register: 0x%08x\n", 4906 base_h); 4907 printf(" limit upper 32 bits register: 0x%08x\n", 4908 limit_h); 4909 if (PCI_BRIDGE_PREFETCHMEM_64BITS(rval)) 4910 use_upper = 1; 4911 else 4912 use_upper = 0; 4913 onoff("64bit memory address", rval, use_upper); 4914 pbase = PCI_BRIDGE_PREFETCHMEM_BASE_ADDR(rval); 4915 plimit = PCI_BRIDGE_PREFETCHMEM_LIMIT_ADDR(rval); 4916 if (use_upper == 1) { 4917 pbase |= (uint64_t)base_h << 32; 4918 plimit |= (uint64_t)limit_h << 32; 4919 } 4920 if (pbase < plimit) { 4921 if (use_upper == 1) 4922 printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64 4923 "\n", pbase, plimit); 4924 else 4925 printf(" range: 0x%08x-0x%08x\n", 4926 (uint32_t)pbase, (uint32_t)plimit); 4927 } else 4928 printf(" range: not set\n"); 4929 4930 csreg = regs[o2i(PCI_COMMAND_STATUS_REG)]; 4931 if (csreg & PCI_STATUS_CAPLIST_SUPPORT) 4932 printf(" Capability list pointer: 0x%02x\n", 4933 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 4934 else 4935 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 4936 4937 printf(" Expansion ROM Base Address: 0x%08x\n", 4938 regs[o2i(PCI_BRIDGE_EXPROMADDR_REG)]); 4939 4940 rval = regs[o2i(PCI_INTERRUPT_REG)]; 4941 printf(" Interrupt line: 0x%02x\n", 4942 (rval >> 0) & 0xff); 4943 printf(" Interrupt pin: 0x%02x ", 4944 (rval >> 8) & 0xff); 4945 switch ((rval >> 8) & 0xff) { 4946 case PCI_INTERRUPT_PIN_NONE: 4947 printf("(none)"); 4948 break; 4949 case PCI_INTERRUPT_PIN_A: 4950 printf("(pin A)"); 4951 break; 4952 case PCI_INTERRUPT_PIN_B: 4953 printf("(pin B)"); 4954 break; 4955 case PCI_INTERRUPT_PIN_C: 4956 printf("(pin C)"); 4957 break; 4958 case PCI_INTERRUPT_PIN_D: 4959 printf("(pin D)"); 4960 break; 4961 default: 4962 printf("(? ? ?)"); 4963 break; 4964 } 4965 printf("\n"); 4966 rval = regs[o2i(PCI_BRIDGE_CONTROL_REG)]; 4967 printf(" Bridge control register: 0x%04hx\n", 4968 (uint16_t)PCIREG_SHIFTOUT(rval, PCI_BRIDGE_CONTROL)); 4969 onoff("Parity error response", rval, PCI_BRIDGE_CONTROL_PERE); 4970 onoff("Secondary SERR forwarding", rval, PCI_BRIDGE_CONTROL_SERR); 4971 onoff("ISA enable", rval, PCI_BRIDGE_CONTROL_ISA); 4972 onoff("VGA enable", rval, PCI_BRIDGE_CONTROL_VGA); 4973 /* 4974 * VGA 16bit decode bit has meaning if the VGA enable bit or the 4975 * VGA Palette Snoop Enable bit is set. 4976 */ 4977 if (((rval & PCI_BRIDGE_CONTROL_VGA) != 0) 4978 || ((csreg & PCI_COMMAND_PALETTE_ENABLE) != 0)) 4979 onoff("VGA 16bit enable", rval, PCI_BRIDGE_CONTROL_VGA16); 4980 onoff("Master abort reporting", rval, PCI_BRIDGE_CONTROL_MABRT); 4981 onoff("Secondary bus reset", rval, PCI_BRIDGE_CONTROL_SECBR); 4982 onoff("Fast back-to-back enable", rval, PCI_BRIDGE_CONTROL_SECFASTB2B); 4983 onoff("Primary Discard Timer", rval, 4984 PCI_BRIDGE_CONTROL_PRI_DISC_TIMER); 4985 onoff("Secondary Discard Timer", 4986 rval, PCI_BRIDGE_CONTROL_SEC_DISC_TIMER); 4987 onoff("Discard Timer Status", rval, 4988 PCI_BRIDGE_CONTROL_DISC_TIMER_STAT); 4989 onoff("Discard Timer SERR# Enable", rval, 4990 PCI_BRIDGE_CONTROL_DISC_TIMER_SERR); 4991 } 4992 4993 static void 4994 pci_conf_print_type2( 4995 #ifdef _KERNEL 4996 pci_chipset_tag_t pc, pcitag_t tag, 4997 #endif 4998 const pcireg_t *regs) 4999 { 5000 pcireg_t rval; 5001 5002 /* 5003 * XXX these need to be printed in more detail, need to be 5004 * XXX checked against specs/docs, etc. 5005 * 5006 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 5007 * controller chip documentation, and may not be correct with 5008 * respect to various standards. (XXX) 5009 */ 5010 5011 #ifdef _KERNEL 5012 pci_conf_print_bar(pc, tag, regs, 0x10, 5013 "CardBus socket/ExCA registers"); 5014 #else 5015 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 5016 #endif 5017 5018 /* Capability list pointer and secondary status register */ 5019 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 5020 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 5021 printf(" Capability list pointer: 0x%02x\n", 5022 PCI_CAPLIST_PTR(rval)); 5023 else 5024 printf(" Reserved @ 0x14: 0x%04x\n", 5025 PCIREG_SHIFTOUT(rval, __BITS(15, 0))); 5026 pci_conf_print_ssr(PCIREG_SHIFTOUT(rval, __BITS(31, 16))); 5027 5028 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 5029 printf(" PCI bus number: 0x%02x\n", 5030 (rval >> 0) & 0xff); 5031 printf(" CardBus bus number: 0x%02x\n", 5032 (rval >> 8) & 0xff); 5033 printf(" Subordinate bus number: 0x%02x\n", 5034 (rval >> 16) & 0xff); 5035 printf(" CardBus latency timer: 0x%02x\n", 5036 (rval >> 24) & 0xff); 5037 5038 /* XXX Print more prettily */ 5039 printf(" CardBus memory region 0:\n"); 5040 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 5041 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 5042 printf(" CardBus memory region 1:\n"); 5043 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 5044 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 5045 printf(" CardBus I/O region 0:\n"); 5046 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 5047 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 5048 printf(" CardBus I/O region 1:\n"); 5049 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 5050 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 5051 5052 rval = regs[o2i(PCI_INTERRUPT_REG)]; 5053 printf(" Interrupt line: 0x%02x\n", 5054 (rval >> 0) & 0xff); 5055 printf(" Interrupt pin: 0x%02x ", 5056 (rval >> 8) & 0xff); 5057 switch ((rval >> 8) & 0xff) { 5058 case PCI_INTERRUPT_PIN_NONE: 5059 printf("(none)"); 5060 break; 5061 case PCI_INTERRUPT_PIN_A: 5062 printf("(pin A)"); 5063 break; 5064 case PCI_INTERRUPT_PIN_B: 5065 printf("(pin B)"); 5066 break; 5067 case PCI_INTERRUPT_PIN_C: 5068 printf("(pin C)"); 5069 break; 5070 case PCI_INTERRUPT_PIN_D: 5071 printf("(pin D)"); 5072 break; 5073 default: 5074 printf("(? ? ?)"); 5075 break; 5076 } 5077 printf("\n"); 5078 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> 16) & 0xffff; 5079 printf(" Bridge control register: 0x%04x\n", rval); 5080 onoff("Parity error response", rval, __BIT(0)); 5081 onoff("SERR# enable", rval, __BIT(1)); 5082 onoff("ISA enable", rval, __BIT(2)); 5083 onoff("VGA enable", rval, __BIT(3)); 5084 onoff("Master abort mode", rval, __BIT(5)); 5085 onoff("Secondary (CardBus) bus reset", rval, __BIT(6)); 5086 onoff("Functional interrupts routed by ExCA registers", rval, 5087 __BIT(7)); 5088 onoff("Memory window 0 prefetchable", rval, __BIT(8)); 5089 onoff("Memory window 1 prefetchable", rval, __BIT(9)); 5090 onoff("Write posting enable", rval, __BIT(10)); 5091 5092 rval = regs[o2i(0x40)]; 5093 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 5094 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 5095 5096 #ifdef _KERNEL 5097 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers"); 5098 #else 5099 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 5100 #endif 5101 } 5102 5103 void 5104 pci_conf_print( 5105 #ifdef _KERNEL 5106 pci_chipset_tag_t pc, pcitag_t tag, 5107 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 5108 #else 5109 int pcifd, u_int bus, u_int dev, u_int func 5110 #endif 5111 ) 5112 { 5113 pcireg_t *regs; 5114 int off, capoff, endoff, hdrtype; 5115 const char *type_name; 5116 #ifdef _KERNEL 5117 void (*type_printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 5118 #else 5119 void (*type_printfn)(const pcireg_t *); 5120 #endif 5121 5122 regs = MALLOC(PCI_EXTCONF_SIZE); 5123 5124 printf("PCI configuration registers:\n"); 5125 5126 for (off = 0; off < PCI_EXTCONF_SIZE; off += 4) { 5127 #ifdef _KERNEL 5128 regs[o2i(off)] = pci_conf_read(pc, tag, off); 5129 #else 5130 if (pcibus_conf_read(pcifd, bus, dev, func, off, 5131 ®s[o2i(off)]) == -1) 5132 regs[o2i(off)] = 0; 5133 #endif 5134 } 5135 5136 /* common header */ 5137 printf(" Common header:\n"); 5138 pci_conf_print_regs(regs, 0, 16); 5139 5140 printf("\n"); 5141 #ifdef _KERNEL 5142 pci_conf_print_common(pc, tag, regs); 5143 #else 5144 pci_conf_print_common(regs); 5145 #endif 5146 printf("\n"); 5147 5148 /* type-dependent header */ 5149 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 5150 switch (hdrtype) { /* XXX make a table, eventually */ 5151 case 0: 5152 /* Standard device header */ 5153 type_name = "\"normal\" device"; 5154 type_printfn = &pci_conf_print_type0; 5155 capoff = PCI_CAPLISTPTR_REG; 5156 endoff = 64; 5157 break; 5158 case 1: 5159 /* PCI-PCI bridge header */ 5160 type_name = "PCI-PCI bridge"; 5161 type_printfn = &pci_conf_print_type1; 5162 capoff = PCI_CAPLISTPTR_REG; 5163 endoff = 64; 5164 break; 5165 case 2: 5166 /* PCI-CardBus bridge header */ 5167 type_name = "PCI-CardBus bridge"; 5168 type_printfn = &pci_conf_print_type2; 5169 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 5170 endoff = 72; 5171 break; 5172 default: 5173 type_name = NULL; 5174 type_printfn = 0; 5175 capoff = -1; 5176 endoff = 64; 5177 break; 5178 } 5179 printf(" Type %d ", hdrtype); 5180 if (type_name != NULL) 5181 printf("(%s) ", type_name); 5182 printf("header:\n"); 5183 pci_conf_print_regs(regs, 16, endoff); 5184 printf("\n"); 5185 if (type_printfn) { 5186 #ifdef _KERNEL 5187 (*type_printfn)(pc, tag, regs); 5188 #else 5189 (*type_printfn)(regs); 5190 #endif 5191 } else 5192 printf(" Don't know how to pretty-print type %d header.\n", 5193 hdrtype); 5194 printf("\n"); 5195 5196 /* capability list, if present */ 5197 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 5198 && (capoff > 0)) { 5199 #ifdef _KERNEL 5200 pci_conf_print_caplist(pc, tag, regs, capoff); 5201 #else 5202 pci_conf_print_caplist(regs, capoff); 5203 #endif 5204 printf("\n"); 5205 } 5206 5207 /* device-dependent header */ 5208 printf(" Device-dependent header:\n"); 5209 pci_conf_print_regs(regs, endoff, PCI_CONF_SIZE); 5210 #ifdef _KERNEL 5211 printf("\n"); 5212 if (printfn) 5213 (*printfn)(pc, tag, regs); 5214 else 5215 printf(" Don't know how to pretty-print device-dependent header.\n"); 5216 #endif /* _KERNEL */ 5217 5218 if (regs[o2i(PCI_EXTCAPLIST_BASE)] == 0xffffffff || 5219 regs[o2i(PCI_EXTCAPLIST_BASE)] == 0) 5220 goto out; 5221 5222 printf("\n"); 5223 #ifdef _KERNEL 5224 pci_conf_print_extcaplist(pc, tag, regs); 5225 #else 5226 pci_conf_print_extcaplist(regs); 5227 #endif 5228 printf("\n"); 5229 5230 /* Extended Configuration Space, if present */ 5231 printf(" Extended Configuration Space:\n"); 5232 pci_conf_print_regs(regs, PCI_EXTCAPLIST_BASE, PCI_EXTCONF_SIZE); 5233 5234 out: 5235 FREE(regs, PCI_EXTCONF_SIZE); 5236 } 5237
Indexes created Thu Sep 25 16:09:42 GMT 2025