pci_subr.c revision 1.28
1 /* $NetBSD: pci_subr.c,v 1.28 1998/06/26 17:53:09 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 */ 38 39 #include "opt_pciverbose.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 45 #include <machine/intr.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #ifdef PCIVERBOSE 50 #include <dev/pci/pcidevs.h> 51 #endif 52 53 static void pci_conf_print_common __P((pci_chipset_tag_t, pcitag_t, 54 const pcireg_t *regs)); 55 static void pci_conf_print_bar __P((pci_chipset_tag_t, pcitag_t, 56 const pcireg_t *regs, int, const char *)); 57 static void pci_conf_print_regs __P((const pcireg_t *regs, int first, 58 int pastlast)); 59 static void pci_conf_print_type0 __P((pci_chipset_tag_t, pcitag_t, 60 const pcireg_t *regs)); 61 static void pci_conf_print_type1 __P((pci_chipset_tag_t, pcitag_t, 62 const pcireg_t *regs)); 63 static void pci_conf_print_type2 __P((pci_chipset_tag_t, pcitag_t, 64 const pcireg_t *regs)); 65 66 /* 67 * Descriptions of known PCI classes and subclasses. 68 * 69 * Subclasses are described in the same way as classes, but have a 70 * NULL subclass pointer. 71 */ 72 struct pci_class { 73 char *name; 74 int val; /* as wide as pci_{,sub}class_t */ 75 struct pci_class *subclasses; 76 }; 77 78 struct pci_class pci_subclass_prehistoric[] = { 79 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, }, 80 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, }, 81 { 0 } 82 }; 83 84 struct pci_class pci_subclass_mass_storage[] = { 85 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, }, 86 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, }, 87 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, }, 88 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, }, 89 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, }, 90 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, }, 91 { 0 }, 92 }; 93 94 struct pci_class pci_subclass_network[] = { 95 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, }, 96 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, }, 97 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, }, 98 { "ATM", PCI_SUBCLASS_NETWORK_ATM, }, 99 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, }, 100 { 0 }, 101 }; 102 103 struct pci_class pci_subclass_display[] = { 104 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, }, 105 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, }, 106 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, }, 107 { 0 }, 108 }; 109 110 struct pci_class pci_subclass_multimedia[] = { 111 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, }, 112 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, }, 113 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, }, 114 { 0 }, 115 }; 116 117 struct pci_class pci_subclass_memory[] = { 118 { "RAM", PCI_SUBCLASS_MEMORY_RAM, }, 119 { "flash", PCI_SUBCLASS_MEMORY_FLASH, }, 120 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, }, 121 { 0 }, 122 }; 123 124 struct pci_class pci_subclass_bridge[] = { 125 { "host", PCI_SUBCLASS_BRIDGE_HOST, }, 126 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, }, 127 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, }, 128 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, }, 129 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, }, 130 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, }, 131 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, }, 132 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, }, 133 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, }, 134 { 0 }, 135 }; 136 137 struct pci_class pci_subclass_communications[] = { 138 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, }, 139 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, }, 140 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, }, 141 { 0 }, 142 }; 143 144 struct pci_class pci_subclass_system[] = { 145 { "8259 PIC", PCI_SUBCLASS_SYSTEM_PIC, }, 146 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, }, 147 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, }, 148 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, }, 149 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, }, 150 { 0 }, 151 }; 152 153 struct pci_class pci_subclass_input[] = { 154 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, }, 155 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, }, 156 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, }, 157 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, }, 158 { 0 }, 159 }; 160 161 struct pci_class pci_subclass_dock[] = { 162 { "generic", PCI_SUBCLASS_DOCK_GENERIC, }, 163 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, }, 164 { 0 }, 165 }; 166 167 struct pci_class pci_subclass_processor[] = { 168 { "386", PCI_SUBCLASS_PROCESSOR_386, }, 169 { "486", PCI_SUBCLASS_PROCESSOR_486, }, 170 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, }, 171 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, }, 172 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, }, 173 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, }, 174 { 0 }, 175 }; 176 177 struct pci_class pci_subclass_serialbus[] = { 178 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, }, 179 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, }, 180 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, }, 181 { "USB", PCI_SUBCLASS_SERIALBUS_USB, }, 182 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, }, 183 { 0 }, 184 }; 185 186 struct pci_class pci_class[] = { 187 { "prehistoric", PCI_CLASS_PREHISTORIC, 188 pci_subclass_prehistoric, }, 189 { "mass storage", PCI_CLASS_MASS_STORAGE, 190 pci_subclass_mass_storage, }, 191 { "network", PCI_CLASS_NETWORK, 192 pci_subclass_network, }, 193 { "display", PCI_CLASS_DISPLAY, 194 pci_subclass_display, }, 195 { "multimedia", PCI_CLASS_MULTIMEDIA, 196 pci_subclass_multimedia, }, 197 { "memory", PCI_CLASS_MEMORY, 198 pci_subclass_memory, }, 199 { "bridge", PCI_CLASS_BRIDGE, 200 pci_subclass_bridge, }, 201 { "communications", PCI_CLASS_COMMUNICATIONS, 202 pci_subclass_communications, }, 203 { "system", PCI_CLASS_SYSTEM, 204 pci_subclass_system, }, 205 { "input", PCI_CLASS_INPUT, 206 pci_subclass_input, }, 207 { "dock", PCI_CLASS_DOCK, 208 pci_subclass_dock, }, 209 { "processor", PCI_CLASS_PROCESSOR, 210 pci_subclass_processor, }, 211 { "serial bus", PCI_CLASS_SERIALBUS, 212 pci_subclass_serialbus, }, 213 { "undefined", PCI_CLASS_UNDEFINED, 214 0, }, 215 { 0 }, 216 }; 217 218 #ifdef PCIVERBOSE 219 /* 220 * Descriptions of of known vendors and devices ("products"). 221 */ 222 struct pci_knowndev { 223 pci_vendor_id_t vendor; 224 pci_product_id_t product; 225 int flags; 226 char *vendorname, *productname; 227 }; 228 #define PCI_KNOWNDEV_NOPROD 0x01 /* match on vendor only */ 229 230 #include <dev/pci/pcidevs_data.h> 231 #endif /* PCIVERBOSE */ 232 233 void 234 pci_devinfo(id_reg, class_reg, showclass, cp) 235 pcireg_t id_reg, class_reg; 236 int showclass; 237 char *cp; 238 { 239 pci_vendor_id_t vendor; 240 pci_product_id_t product; 241 pci_class_t class; 242 pci_subclass_t subclass; 243 pci_interface_t interface; 244 pci_revision_t revision; 245 char *vendor_namep, *product_namep; 246 struct pci_class *classp, *subclassp; 247 #ifdef PCIVERBOSE 248 struct pci_knowndev *kdp; 249 const char *unmatched = "unknown "; 250 #else 251 const char *unmatched = ""; 252 #endif 253 254 vendor = PCI_VENDOR(id_reg); 255 product = PCI_PRODUCT(id_reg); 256 257 class = PCI_CLASS(class_reg); 258 subclass = PCI_SUBCLASS(class_reg); 259 interface = PCI_INTERFACE(class_reg); 260 revision = PCI_REVISION(class_reg); 261 262 #ifdef PCIVERBOSE 263 kdp = pci_knowndevs; 264 while (kdp->vendorname != NULL) { /* all have vendor name */ 265 if (kdp->vendor == vendor && (kdp->product == product || 266 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) 267 break; 268 kdp++; 269 } 270 if (kdp->vendorname == NULL) 271 vendor_namep = product_namep = NULL; 272 else { 273 vendor_namep = kdp->vendorname; 274 product_namep = (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0 ? 275 kdp->productname : NULL; 276 } 277 #else /* PCIVERBOSE */ 278 vendor_namep = product_namep = NULL; 279 #endif /* PCIVERBOSE */ 280 281 classp = pci_class; 282 while (classp->name != NULL) { 283 if (class == classp->val) 284 break; 285 classp++; 286 } 287 288 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 289 while (subclassp && subclassp->name != NULL) { 290 if (subclass == subclassp->val) 291 break; 292 subclassp++; 293 } 294 295 if (vendor_namep == NULL) 296 cp += sprintf(cp, "%svendor 0x%04x product 0x%04x", 297 unmatched, vendor, product); 298 else if (product_namep != NULL) 299 cp += sprintf(cp, "%s %s", vendor_namep, product_namep); 300 else 301 cp += sprintf(cp, "%s product 0x%04x", 302 vendor_namep, product); 303 if (showclass) { 304 cp += sprintf(cp, " ("); 305 if (classp->name == NULL) 306 cp += sprintf(cp, "class 0x%02x, subclass 0x%02x", 307 class, subclass); 308 else { 309 if (subclassp == NULL || subclassp->name == NULL) 310 cp += sprintf(cp, 311 "%s subclass 0x%02x", 312 classp->name, subclass); 313 else 314 cp += sprintf(cp, "%s %s", 315 subclassp->name, classp->name); 316 } 317 if (interface != 0) 318 cp += sprintf(cp, ", interface 0x%02x", interface); 319 if (revision != 0) 320 cp += sprintf(cp, ", revision 0x%02x", revision); 321 cp += sprintf(cp, ")"); 322 } 323 } 324 325 /* 326 * Print out most of the PCI configuration registers. Typically used 327 * in a device attach routine like this: 328 * 329 * #ifdef MYDEV_DEBUG 330 * printf("%s: ", sc->sc_dev.dv_xname); 331 * pci_conf_print(pa->pa_pc, pa->pa_tag); 332 * #endif 333 */ 334 335 #define i2o(i) ((i) * 4) 336 #define o2i(o) ((o) / 4) 337 #define onoff(str, bit) \ 338 printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off"); 339 340 static void 341 pci_conf_print_common(pc, tag, regs) 342 pci_chipset_tag_t pc; 343 pcitag_t tag; 344 const pcireg_t *regs; 345 { 346 #ifdef PCIVERBOSE 347 struct pci_knowndev *kdp; 348 #endif 349 struct pci_class *classp, *subclassp; 350 pcireg_t rval; 351 352 rval = regs[o2i(PCI_ID_REG)]; 353 #ifndef PCIVERBOSE 354 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 355 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 356 #else 357 for (kdp = pci_knowndevs; kdp->vendorname != NULL; kdp++) { 358 if (kdp->vendor == PCI_VENDOR(rval) && 359 (kdp->product == PCI_PRODUCT(rval) || 360 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) { 361 break; 362 } 363 } 364 if (kdp->vendorname != NULL) 365 printf(" Vendor Name: %s (0x%04x)\n", kdp->vendorname, 366 PCI_VENDOR(rval)); 367 else 368 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 369 if (kdp->productname != NULL && (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0) 370 printf(" Device Name: %s (0x%04x)\n", kdp->productname, 371 PCI_PRODUCT(rval)); 372 else 373 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 374 #endif /* PCIVERBOSE */ 375 376 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 377 378 printf(" Command register: 0x%04x\n", rval & 0xffff); 379 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 380 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 381 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 382 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 383 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 384 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 385 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 386 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 387 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 388 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 389 390 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 391 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 392 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 393 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 394 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 395 396 printf(" DEVSEL timing: "); 397 switch (rval & PCI_STATUS_DEVSEL_MASK) { 398 case PCI_STATUS_DEVSEL_FAST: 399 printf("fast"); 400 break; 401 case PCI_STATUS_DEVSEL_MEDIUM: 402 printf("medium"); 403 break; 404 case PCI_STATUS_DEVSEL_SLOW: 405 printf("slow"); 406 break; 407 default: 408 printf("unknown/reserved"); /* XXX */ 409 break; 410 } 411 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 412 413 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 414 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 415 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 416 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 417 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 418 419 rval = regs[o2i(PCI_CLASS_REG)]; 420 for (classp = pci_class; classp->name != NULL; classp++) { 421 if (PCI_CLASS(rval) == classp->val) 422 break; 423 } 424 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 425 while (subclassp && subclassp->name != NULL) { 426 if (PCI_SUBCLASS(rval) == subclassp->val) 427 break; 428 subclassp++; 429 } 430 if (classp->name != NULL) { 431 printf(" Class Name: %s (0x%02x)\n", classp->name, 432 PCI_CLASS(rval)); 433 if (subclassp != NULL && subclassp->name != NULL) 434 printf(" Subclass Name: %s (0x%02x)\n", 435 subclassp->name, PCI_SUBCLASS(rval)); 436 else 437 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 438 } else { 439 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 440 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 441 } 442 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 443 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 444 445 rval = regs[o2i(PCI_BHLC_REG)]; 446 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 447 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 448 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 449 PCI_HDRTYPE(rval)); 450 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 451 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 452 } 453 454 static void 455 pci_conf_print_bar(pc, tag, regs, reg, name) 456 pci_chipset_tag_t pc; 457 pcitag_t tag; 458 const pcireg_t *regs; 459 int reg; 460 const char *name; 461 { 462 int s; 463 pcireg_t mask, rval; 464 465 /* 466 * Section 6.2.5.1, `Address Maps', tells us that: 467 * 468 * 1) The builtin software should have already mapped the 469 * device in a reasonable way. 470 * 471 * 2) A device which wants 2^n bytes of memory will hardwire 472 * the bottom n bits of the address to 0. As recommended, 473 * we write all 1s and see what we get back. 474 */ 475 rval = regs[o2i(reg)]; 476 if (rval != 0) { 477 /* 478 * The following sequence seems to make some devices 479 * (e.g. host bus bridges, which don't normally 480 * have their space mapped) very unhappy, to 481 * the point of crashing the system. 482 * 483 * Therefore, if the mapping register is zero to 484 * start out with, don't bother trying. 485 */ 486 s = splhigh(); 487 pci_conf_write(pc, tag, reg, 0xffffffff); 488 mask = pci_conf_read(pc, tag, reg); 489 pci_conf_write(pc, tag, reg, rval); 490 splx(s); 491 } else 492 mask = 0; 493 494 printf(" Base address register at 0x%02x", reg); 495 if (name) 496 printf(" (%s)", name); 497 printf("\n "); 498 if (rval == 0) { 499 printf("not implemented(?)\n"); 500 return; 501 } 502 printf("type: "); 503 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 504 const char *type, *cache; 505 506 switch (PCI_MAPREG_MEM_TYPE(rval)) { 507 case PCI_MAPREG_MEM_TYPE_32BIT: 508 type = "32-bit"; 509 break; 510 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 511 type = "32-bit-1M"; 512 break; 513 case PCI_MAPREG_MEM_TYPE_64BIT: 514 type = "64-bit"; 515 break; 516 default: 517 type = "unknown (XXX)"; 518 break; 519 } 520 if (PCI_MAPREG_MEM_CACHEABLE(rval)) 521 cache = ""; 522 else 523 cache = "non"; 524 printf("%s %scacheable memory\n", type, cache); 525 printf(" base: 0x%08x, size: 0x%08x\n", 526 PCI_MAPREG_MEM_ADDR(rval), 527 PCI_MAPREG_MEM_SIZE(mask)); 528 } else { 529 printf("i/o\n"); 530 printf(" base: 0x%08x, size: 0x%08x\n", 531 PCI_MAPREG_IO_ADDR(rval), 532 PCI_MAPREG_IO_SIZE(mask)); 533 } 534 } 535 536 static void 537 pci_conf_print_regs(regs, first, pastlast) 538 const pcireg_t *regs; 539 int first, pastlast; 540 { 541 int off, needaddr, neednl; 542 543 needaddr = 1; 544 neednl = 0; 545 for (off = first; off < pastlast; off += 4) { 546 if ((off % 16) == 0 || needaddr) { 547 printf(" 0x%02x:", off); 548 needaddr = 0; 549 } 550 printf(" 0x%08x", regs[o2i(off)]); 551 neednl = 1; 552 if ((off % 16) == 12) { 553 printf("\n"); 554 neednl = 0; 555 } 556 } 557 if (neednl) 558 printf("\n"); 559 } 560 561 static void 562 pci_conf_print_type0(pc, tag, regs) 563 pci_chipset_tag_t pc; 564 pcitag_t tag; 565 const pcireg_t *regs; 566 { 567 int off; 568 pcireg_t rval; 569 570 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += 4) 571 pci_conf_print_bar(pc, tag, regs, off, NULL); 572 573 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 574 575 rval = regs[o2i(0x2c)]; 576 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 577 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 578 579 /* XXX */ 580 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 581 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 582 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 583 584 rval = regs[o2i(PCI_INTERRUPT_REG)]; 585 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 586 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 587 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 588 switch (PCI_INTERRUPT_PIN(rval)) { 589 case PCI_INTERRUPT_PIN_NONE: 590 printf("(none)"); 591 break; 592 case PCI_INTERRUPT_PIN_A: 593 printf("(pin A)"); 594 break; 595 case PCI_INTERRUPT_PIN_B: 596 printf("(pin B)"); 597 break; 598 case PCI_INTERRUPT_PIN_C: 599 printf("(pin C)"); 600 break; 601 case PCI_INTERRUPT_PIN_D: 602 printf("(pin D)"); 603 break; 604 default: 605 printf("(???)"); 606 break; 607 } 608 printf("\n"); 609 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 610 } 611 612 static void 613 pci_conf_print_type1(pc, tag, regs) 614 pci_chipset_tag_t pc; 615 pcitag_t tag; 616 const pcireg_t *regs; 617 { 618 int off; 619 pcireg_t rval; 620 621 /* 622 * XXX these need to be printed in more detail, need to be 623 * XXX checked against specs/docs, etc. 624 * 625 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 626 * Bridge chip documentation, and may not be correct with 627 * respect to various standards. (XXX) 628 */ 629 630 for (off = 0x10; off < 0x18; off += 4) 631 pci_conf_print_bar(pc, tag, regs, off, NULL); 632 633 printf(" Primary bus number: 0x%02x\n", 634 (regs[o2i(0x18)] >> 0) & 0xff); 635 printf(" Secondary bus number: 0x%02x\n", 636 (regs[o2i(0x18)] >> 8) & 0xff); 637 printf(" Subordinate bus number: 0x%02x\n", 638 (regs[o2i(0x18)] >> 16) & 0xff); 639 printf(" Secondary bus latency timer: 0x%02x\n", 640 (regs[o2i(0x18)] >> 24) & 0xff); 641 642 rval = (regs[o2i(0x1c)] >> 16) & 0xffff; 643 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 644 onoff("66 MHz capable", 0x0020); 645 onoff("User Definable Features (UDF) support", 0x0040); 646 onoff("Fast back-to-back capable", 0x0080); 647 onoff("Data parity error detected", 0x0100); 648 649 printf(" DEVSEL timing: "); 650 switch (rval & 0x0600) { 651 case 0x0000: 652 printf("fast"); 653 break; 654 case 0x0200: 655 printf("medium"); 656 break; 657 case 0x0400: 658 printf("slow"); 659 break; 660 default: 661 printf("unknown/reserved"); /* XXX */ 662 break; 663 } 664 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 665 666 onoff("Signaled Target Abort", 0x0800); 667 onoff("Received Target Abort", 0x1000); 668 onoff("Received Master Abort", 0x2000); 669 onoff("System Error", 0x4000); 670 onoff("Parity Error", 0x8000); 671 672 /* XXX Print more prettily */ 673 printf(" I/O region:\n"); 674 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 675 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 676 printf(" base upper 16 bits register: 0x%04x\n", 677 (regs[o2i(0x30)] >> 0) & 0xffff); 678 printf(" limit upper 16 bits register: 0x%04x\n", 679 (regs[o2i(0x30)] >> 16) & 0xffff); 680 681 /* XXX Print more prettily */ 682 printf(" Memory region:\n"); 683 printf(" base register: 0x%04x\n", 684 (regs[o2i(0x20)] >> 0) & 0xffff); 685 printf(" limit register: 0x%04x\n", 686 (regs[o2i(0x20)] >> 16) & 0xffff); 687 688 /* XXX Print more prettily */ 689 printf(" Prefetchable memory region:\n"); 690 printf(" base register: 0x%04x\n", 691 (regs[o2i(0x24)] >> 0) & 0xffff); 692 printf(" limit register: 0x%04x\n", 693 (regs[o2i(0x24)] >> 16) & 0xffff); 694 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 695 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 696 697 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 698 /* XXX */ 699 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 700 701 printf(" Interrupt line: 0x%02x\n", 702 (regs[o2i(0x3c)] >> 0) & 0xff); 703 printf(" Interrupt pin: 0x%02x ", 704 (regs[o2i(0x3c)] >> 8) & 0xff); 705 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 706 case PCI_INTERRUPT_PIN_NONE: 707 printf("(none)"); 708 break; 709 case PCI_INTERRUPT_PIN_A: 710 printf("(pin A)"); 711 break; 712 case PCI_INTERRUPT_PIN_B: 713 printf("(pin B)"); 714 break; 715 case PCI_INTERRUPT_PIN_C: 716 printf("(pin C)"); 717 break; 718 case PCI_INTERRUPT_PIN_D: 719 printf("(pin D)"); 720 break; 721 default: 722 printf("(???)"); 723 break; 724 } 725 printf("\n"); 726 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 727 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 728 onoff("Parity error response", 0x0001); 729 onoff("Secondary SERR forwarding", 0x0002); 730 onoff("ISA enable", 0x0004); 731 onoff("VGA enable", 0x0008); 732 onoff("Master abort reporting", 0x0020); 733 onoff("Secondary bus reset", 0x0040); 734 onoff("Fast back-to-back capable", 0x0080); 735 } 736 737 static void 738 pci_conf_print_type2(pc, tag, regs) 739 pci_chipset_tag_t pc; 740 pcitag_t tag; 741 const pcireg_t *regs; 742 { 743 pcireg_t rval; 744 745 /* 746 * XXX these need to be printed in more detail, need to be 747 * XXX checked against specs/docs, etc. 748 * 749 * This layout was cribbed from the TI PCI1130 PCI-to-CardBus 750 * controller chip documentation, and may not be correct with 751 * respect to various standards. (XXX) 752 */ 753 754 pci_conf_print_bar(pc, tag, regs, 0x10, 755 "CardBus socket/ExCA registers"); 756 757 printf(" Reserved @ 0x14: 0x%04x\n", 758 (regs[o2i(0x14)] >> 0) & 0xffff); 759 rval = (regs[o2i(0x14)] >> 16) & 0xffff; 760 printf(" Secondary status register: 0x%04x\n", rval); 761 onoff("66 MHz capable", 0x0020); 762 onoff("User Definable Features (UDF) support", 0x0040); 763 onoff("Fast back-to-back capable", 0x0080); 764 onoff("Data parity error detection", 0x0100); 765 766 printf(" DEVSEL timing: "); 767 switch (rval & 0x0600) { 768 case 0x0000: 769 printf("fast"); 770 break; 771 case 0x0200: 772 printf("medium"); 773 break; 774 case 0x0400: 775 printf("slow"); 776 break; 777 default: 778 printf("unknown/reserved"); /* XXX */ 779 break; 780 } 781 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 782 onoff("PCI target aborts terminate CardBus bus master transactions", 783 0x0800); 784 onoff("CardBus target aborts terminate PCI bus master transactions", 785 0x1000); 786 onoff("Bus initiator aborts terminate initiator transactions", 787 0x2000); 788 onoff("System error", 0x4000); 789 onoff("Parity error", 0x8000); 790 791 printf(" PCI bus number: 0x%02x\n", 792 (regs[o2i(0x18)] >> 0) & 0xff); 793 printf(" CardBus bus number: 0x%02x\n", 794 (regs[o2i(0x18)] >> 8) & 0xff); 795 printf(" Subordinate bus number: 0x%02x\n", 796 (regs[o2i(0x18)] >> 16) & 0xff); 797 printf(" CardBus latency timer: 0x%02x\n", 798 (regs[o2i(0x18)] >> 24) & 0xff); 799 800 /* XXX Print more prettily */ 801 printf(" CardBus memory region 0:\n"); 802 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 803 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 804 printf(" CardBus memory region 1:\n"); 805 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 806 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 807 printf(" CardBus I/O region 0:\n"); 808 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 809 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 810 printf(" CardBus I/O region 1:\n"); 811 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 812 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 813 814 printf(" Interrupt line: 0x%02x\n", 815 (regs[o2i(0x3c)] >> 0) & 0xff); 816 printf(" Interrupt pin: 0x%02x ", 817 (regs[o2i(0x3c)] >> 8) & 0xff); 818 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 819 case PCI_INTERRUPT_PIN_NONE: 820 printf("(none)"); 821 break; 822 case PCI_INTERRUPT_PIN_A: 823 printf("(pin A)"); 824 break; 825 case PCI_INTERRUPT_PIN_B: 826 printf("(pin B)"); 827 break; 828 case PCI_INTERRUPT_PIN_C: 829 printf("(pin C)"); 830 break; 831 case PCI_INTERRUPT_PIN_D: 832 printf("(pin D)"); 833 break; 834 default: 835 printf("(???)"); 836 break; 837 } 838 printf("\n"); 839 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 840 printf(" Bridge control register: 0x%04x\n", rval); 841 onoff("Parity error response", 0x0001); 842 onoff("CardBus SERR forwarding", 0x0002); 843 onoff("ISA enable", 0x0004); 844 onoff("VGA enable", 0x0008); 845 onoff("CardBus master abort reporting", 0x0020); 846 onoff("CardBus reset", 0x0040); 847 onoff("Functional interrupts routed by ExCA registers", 0x0080); 848 onoff("Memory window 0 prefetchable", 0x0100); 849 onoff("Memory window 1 prefetchable", 0x0200); 850 onoff("Write posting enable", 0x0400); 851 852 rval = regs[o2i(0x40)]; 853 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 854 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 855 856 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers"); 857 } 858 859 void 860 pci_conf_print(pc, tag, printfn) 861 pci_chipset_tag_t pc; 862 pcitag_t tag; 863 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 864 { 865 pcireg_t regs[o2i(256)]; 866 int off, endoff, hdrtype; 867 const char *typename; 868 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 869 870 printf("PCI configuration registers:\n"); 871 872 for (off = 0; off < 256; off += 4) 873 regs[o2i(off)] = pci_conf_read(pc, tag, off); 874 875 /* common header */ 876 printf(" Common header:\n"); 877 pci_conf_print_regs(regs, 0, 16); 878 879 printf("\n"); 880 pci_conf_print_common(pc, tag, regs); 881 printf("\n"); 882 883 /* type-dependent header */ 884 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 885 switch (hdrtype) { /* XXX make a table, eventually */ 886 case 0: 887 /* Standard device header */ 888 typename = "\"normal\" device"; 889 typeprintfn = &pci_conf_print_type0; 890 endoff = 64; 891 break; 892 case 1: 893 /* PCI-PCI bridge header */ 894 typename = "PCI-PCI bridge"; 895 typeprintfn = &pci_conf_print_type1; 896 endoff = 64; 897 break; 898 case 2: 899 /* PCI-CardBus bridge header */ 900 typename = "PCI-CardBus bridge"; 901 typeprintfn = &pci_conf_print_type2; 902 endoff = 72; 903 break; 904 default: 905 typename = NULL; 906 typeprintfn = 0; 907 endoff = 64; 908 break; 909 } 910 printf(" Type %d ", hdrtype); 911 if (typename != NULL) 912 printf("(%s) ", typename); 913 printf("header:\n"); 914 pci_conf_print_regs(regs, 16, endoff); 915 printf("\n"); 916 if (typeprintfn) 917 (*typeprintfn)(pc, tag, regs); 918 else 919 printf(" Don't know how to pretty-print type %d header.\n", 920 hdrtype); 921 printf("\n"); 922 923 /* device-dependent header */ 924 printf(" Device-dependent header:\n"); 925 pci_conf_print_regs(regs, endoff, 256); 926 printf("\n"); 927 if (printfn) 928 (*printfn)(pc, tag, regs); 929 else 930 printf(" Don't know how to pretty-print device-dependent header.\n"); 931 printf("\n"); 932 } 933
Indexes created Fri Sep 26 20:09:58 GMT 2025