pci_subr.c revision 1.32
1 /* $NetBSD: pci_subr.c,v 1.32 1999/09/27 03:20:47 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 */ 38 39 #include "opt_pciverbose.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 45 #include <machine/intr.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #ifdef PCIVERBOSE 50 #include <dev/pci/pcidevs.h> 51 #endif 52 53 static void pci_conf_print_common __P((pci_chipset_tag_t, pcitag_t, 54 const pcireg_t *regs)); 55 static void pci_conf_print_bar __P((pci_chipset_tag_t, pcitag_t, 56 const pcireg_t *regs, int, const char *)); 57 static void pci_conf_print_regs __P((const pcireg_t *regs, int first, 58 int pastlast)); 59 static void pci_conf_print_type0 __P((pci_chipset_tag_t, pcitag_t, 60 const pcireg_t *regs)); 61 static void pci_conf_print_type1 __P((pci_chipset_tag_t, pcitag_t, 62 const pcireg_t *regs)); 63 static void pci_conf_print_type2 __P((pci_chipset_tag_t, pcitag_t, 64 const pcireg_t *regs)); 65 66 /* 67 * Descriptions of known PCI classes and subclasses. 68 * 69 * Subclasses are described in the same way as classes, but have a 70 * NULL subclass pointer. 71 */ 72 struct pci_class { 73 char *name; 74 int val; /* as wide as pci_{,sub}class_t */ 75 struct pci_class *subclasses; 76 }; 77 78 struct pci_class pci_subclass_prehistoric[] = { 79 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, }, 80 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, }, 81 { 0 } 82 }; 83 84 struct pci_class pci_subclass_mass_storage[] = { 85 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, }, 86 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, }, 87 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, }, 88 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, }, 89 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, }, 90 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, }, 91 { 0 }, 92 }; 93 94 struct pci_class pci_subclass_network[] = { 95 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, }, 96 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, }, 97 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, }, 98 { "ATM", PCI_SUBCLASS_NETWORK_ATM, }, 99 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, }, 100 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, }, 101 { 0 }, 102 }; 103 104 struct pci_class pci_subclass_display[] = { 105 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, }, 106 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, }, 107 { "3D", PCI_SUBCLASS_DISPLAY_3D, }, 108 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, }, 109 { 0 }, 110 }; 111 112 struct pci_class pci_subclass_multimedia[] = { 113 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, }, 114 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, }, 115 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, }, 116 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, }, 117 { 0 }, 118 }; 119 120 struct pci_class pci_subclass_memory[] = { 121 { "RAM", PCI_SUBCLASS_MEMORY_RAM, }, 122 { "flash", PCI_SUBCLASS_MEMORY_FLASH, }, 123 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, }, 124 { 0 }, 125 }; 126 127 struct pci_class pci_subclass_bridge[] = { 128 { "host", PCI_SUBCLASS_BRIDGE_HOST, }, 129 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, }, 130 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, }, 131 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, }, 132 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, }, 133 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, }, 134 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, }, 135 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, }, 136 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, }, 137 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, }, 138 { 0 }, 139 }; 140 141 struct pci_class pci_subclass_communications[] = { 142 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, }, 143 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, }, 144 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, }, 145 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, }, 146 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, }, 147 { 0 }, 148 }; 149 150 struct pci_class pci_subclass_system[] = { 151 { "8259 PIC", PCI_SUBCLASS_SYSTEM_PIC, }, 152 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, }, 153 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, }, 154 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, }, 155 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_RTC, }, 156 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, }, 157 { 0 }, 158 }; 159 160 struct pci_class pci_subclass_input[] = { 161 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, }, 162 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, }, 163 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, }, 164 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, }, 165 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, }, 166 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, }, 167 { 0 }, 168 }; 169 170 struct pci_class pci_subclass_dock[] = { 171 { "generic", PCI_SUBCLASS_DOCK_GENERIC, }, 172 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, }, 173 { 0 }, 174 }; 175 176 struct pci_class pci_subclass_processor[] = { 177 { "386", PCI_SUBCLASS_PROCESSOR_386, }, 178 { "486", PCI_SUBCLASS_PROCESSOR_486, }, 179 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, }, 180 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, }, 181 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, }, 182 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, }, 183 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, }, 184 { 0 }, 185 }; 186 187 struct pci_class pci_subclass_serialbus[] = { 188 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, }, 189 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, }, 190 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, }, 191 { "USB", PCI_SUBCLASS_SERIALBUS_USB, }, 192 /* XXX Fiber Channel/_FIBRECHANNEL */ 193 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, }, 194 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, }, 195 { 0 }, 196 }; 197 198 struct pci_class pci_subclass_wireless[] = { 199 { "iRDA", PCI_SUBCLASS_WIRELESS_IRDA, }, 200 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, }, 201 { "RF", PCI_SUBCLASS_WIRELESS_RF, }, 202 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, }, 203 { 0 }, 204 }; 205 206 struct pci_class pci_subclass_i2o[] = { 207 { "1.0", PCI_SUBCLASS_I2O_10, }, 208 { 0 }, 209 }; 210 211 struct pci_class pci_subclass_satcom[] = { 212 { "TV", PCI_SUBCLASS_SATCOM_TV, }, 213 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, }, 214 { "voice", PCI_SUBCLASS_SATCOM_VOICE, }, 215 { "data", PCI_SUBCLASS_SATCOM_DATA, }, 216 { 0 }, 217 }; 218 219 struct pci_class pci_subclass_crypto[] = { 220 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, }, 221 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, }, 222 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, }, 223 { 0 }, 224 }; 225 226 struct pci_class pci_subclass_dasp[] = { 227 { "DPIO", PCI_SUBCLASS_DASP_DPIO, }, 228 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, }, 229 { 0 }, 230 }; 231 232 struct pci_class pci_class[] = { 233 { "prehistoric", PCI_CLASS_PREHISTORIC, 234 pci_subclass_prehistoric, }, 235 { "mass storage", PCI_CLASS_MASS_STORAGE, 236 pci_subclass_mass_storage, }, 237 { "network", PCI_CLASS_NETWORK, 238 pci_subclass_network, }, 239 { "display", PCI_CLASS_DISPLAY, 240 pci_subclass_display, }, 241 { "multimedia", PCI_CLASS_MULTIMEDIA, 242 pci_subclass_multimedia, }, 243 { "memory", PCI_CLASS_MEMORY, 244 pci_subclass_memory, }, 245 { "bridge", PCI_CLASS_BRIDGE, 246 pci_subclass_bridge, }, 247 { "communications", PCI_CLASS_COMMUNICATIONS, 248 pci_subclass_communications, }, 249 { "system", PCI_CLASS_SYSTEM, 250 pci_subclass_system, }, 251 { "input", PCI_CLASS_INPUT, 252 pci_subclass_input, }, 253 { "dock", PCI_CLASS_DOCK, 254 pci_subclass_dock, }, 255 { "processor", PCI_CLASS_PROCESSOR, 256 pci_subclass_processor, }, 257 { "serial bus", PCI_CLASS_SERIALBUS, 258 pci_subclass_serialbus, }, 259 { "wireless", PCI_CLASS_WIRELESS, 260 pci_subclass_wireless, }, 261 { "I2O", PCI_CLASS_I2O, 262 pci_subclass_i2o, }, 263 { "satellite comm", PCI_CLASS_SATCOM, 264 pci_subclass_satcom, }, 265 { "crypto", PCI_CLASS_CRYPTO, 266 pci_subclass_crypto, }, 267 { "DASP", PCI_CLASS_DASP, 268 pci_subclass_dasp, }, 269 { "undefined", PCI_CLASS_UNDEFINED, 270 0, }, 271 { 0 }, 272 }; 273 274 #ifdef PCIVERBOSE 275 /* 276 * Descriptions of of known vendors and devices ("products"). 277 */ 278 struct pci_knowndev { 279 pci_vendor_id_t vendor; 280 pci_product_id_t product; 281 int flags; 282 char *vendorname, *productname; 283 }; 284 #define PCI_KNOWNDEV_NOPROD 0x01 /* match on vendor only */ 285 286 #include <dev/pci/pcidevs_data.h> 287 #endif /* PCIVERBOSE */ 288 289 char * 290 pci_findvendor(id_reg) 291 pcireg_t id_reg; 292 { 293 #ifdef PCIVERBOSE 294 pci_vendor_id_t vendor = PCI_VENDOR(id_reg); 295 struct pci_knowndev *kdp; 296 297 kdp = pci_knowndevs; 298 while (kdp->vendorname != NULL) { /* all have vendor name */ 299 if (kdp->vendor == vendor) 300 break; 301 kdp++; 302 } 303 return (kdp->vendorname); 304 #else 305 return (NULL); 306 #endif 307 } 308 309 void 310 pci_devinfo(id_reg, class_reg, showclass, cp) 311 pcireg_t id_reg, class_reg; 312 int showclass; 313 char *cp; 314 { 315 pci_vendor_id_t vendor; 316 pci_product_id_t product; 317 pci_class_t class; 318 pci_subclass_t subclass; 319 pci_interface_t interface; 320 pci_revision_t revision; 321 char *vendor_namep, *product_namep; 322 struct pci_class *classp, *subclassp; 323 #ifdef PCIVERBOSE 324 struct pci_knowndev *kdp; 325 const char *unmatched = "unknown "; 326 #else 327 const char *unmatched = ""; 328 #endif 329 330 vendor = PCI_VENDOR(id_reg); 331 product = PCI_PRODUCT(id_reg); 332 333 class = PCI_CLASS(class_reg); 334 subclass = PCI_SUBCLASS(class_reg); 335 interface = PCI_INTERFACE(class_reg); 336 revision = PCI_REVISION(class_reg); 337 338 #ifdef PCIVERBOSE 339 kdp = pci_knowndevs; 340 while (kdp->vendorname != NULL) { /* all have vendor name */ 341 if (kdp->vendor == vendor && (kdp->product == product || 342 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) 343 break; 344 kdp++; 345 } 346 if (kdp->vendorname == NULL) 347 vendor_namep = product_namep = NULL; 348 else { 349 vendor_namep = kdp->vendorname; 350 product_namep = (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0 ? 351 kdp->productname : NULL; 352 } 353 #else /* PCIVERBOSE */ 354 vendor_namep = product_namep = NULL; 355 #endif /* PCIVERBOSE */ 356 357 classp = pci_class; 358 while (classp->name != NULL) { 359 if (class == classp->val) 360 break; 361 classp++; 362 } 363 364 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 365 while (subclassp && subclassp->name != NULL) { 366 if (subclass == subclassp->val) 367 break; 368 subclassp++; 369 } 370 371 if (vendor_namep == NULL) 372 cp += sprintf(cp, "%svendor 0x%04x product 0x%04x", 373 unmatched, vendor, product); 374 else if (product_namep != NULL) 375 cp += sprintf(cp, "%s %s", vendor_namep, product_namep); 376 else 377 cp += sprintf(cp, "%s product 0x%04x", 378 vendor_namep, product); 379 if (showclass) { 380 cp += sprintf(cp, " ("); 381 if (classp->name == NULL) 382 cp += sprintf(cp, "class 0x%02x, subclass 0x%02x", 383 class, subclass); 384 else { 385 if (subclassp == NULL || subclassp->name == NULL) 386 cp += sprintf(cp, 387 "%s subclass 0x%02x", 388 classp->name, subclass); 389 else 390 cp += sprintf(cp, "%s %s", 391 subclassp->name, classp->name); 392 } 393 if (interface != 0) 394 cp += sprintf(cp, ", interface 0x%02x", interface); 395 if (revision != 0) 396 cp += sprintf(cp, ", revision 0x%02x", revision); 397 cp += sprintf(cp, ")"); 398 } 399 } 400 401 /* 402 * Print out most of the PCI configuration registers. Typically used 403 * in a device attach routine like this: 404 * 405 * #ifdef MYDEV_DEBUG 406 * printf("%s: ", sc->sc_dev.dv_xname); 407 * pci_conf_print(pa->pa_pc, pa->pa_tag); 408 * #endif 409 */ 410 411 #define i2o(i) ((i) * 4) 412 #define o2i(o) ((o) / 4) 413 #define onoff(str, bit) \ 414 printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off"); 415 416 static void 417 pci_conf_print_common(pc, tag, regs) 418 pci_chipset_tag_t pc; 419 pcitag_t tag; 420 const pcireg_t *regs; 421 { 422 #ifdef PCIVERBOSE 423 struct pci_knowndev *kdp; 424 #endif 425 struct pci_class *classp, *subclassp; 426 pcireg_t rval; 427 428 rval = regs[o2i(PCI_ID_REG)]; 429 #ifndef PCIVERBOSE 430 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 431 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 432 #else 433 for (kdp = pci_knowndevs; kdp->vendorname != NULL; kdp++) { 434 if (kdp->vendor == PCI_VENDOR(rval) && 435 (kdp->product == PCI_PRODUCT(rval) || 436 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) { 437 break; 438 } 439 } 440 if (kdp->vendorname != NULL) 441 printf(" Vendor Name: %s (0x%04x)\n", kdp->vendorname, 442 PCI_VENDOR(rval)); 443 else 444 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 445 if (kdp->productname != NULL && (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0) 446 printf(" Device Name: %s (0x%04x)\n", kdp->productname, 447 PCI_PRODUCT(rval)); 448 else 449 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 450 #endif /* PCIVERBOSE */ 451 452 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 453 454 printf(" Command register: 0x%04x\n", rval & 0xffff); 455 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 456 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 457 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 458 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 459 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 460 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 461 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 462 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 463 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 464 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 465 466 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 467 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 468 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 469 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 470 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 471 472 printf(" DEVSEL timing: "); 473 switch (rval & PCI_STATUS_DEVSEL_MASK) { 474 case PCI_STATUS_DEVSEL_FAST: 475 printf("fast"); 476 break; 477 case PCI_STATUS_DEVSEL_MEDIUM: 478 printf("medium"); 479 break; 480 case PCI_STATUS_DEVSEL_SLOW: 481 printf("slow"); 482 break; 483 default: 484 printf("unknown/reserved"); /* XXX */ 485 break; 486 } 487 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 488 489 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 490 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 491 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 492 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 493 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 494 495 rval = regs[o2i(PCI_CLASS_REG)]; 496 for (classp = pci_class; classp->name != NULL; classp++) { 497 if (PCI_CLASS(rval) == classp->val) 498 break; 499 } 500 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 501 while (subclassp && subclassp->name != NULL) { 502 if (PCI_SUBCLASS(rval) == subclassp->val) 503 break; 504 subclassp++; 505 } 506 if (classp->name != NULL) { 507 printf(" Class Name: %s (0x%02x)\n", classp->name, 508 PCI_CLASS(rval)); 509 if (subclassp != NULL && subclassp->name != NULL) 510 printf(" Subclass Name: %s (0x%02x)\n", 511 subclassp->name, PCI_SUBCLASS(rval)); 512 else 513 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 514 } else { 515 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 516 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 517 } 518 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 519 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 520 521 rval = regs[o2i(PCI_BHLC_REG)]; 522 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 523 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 524 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 525 PCI_HDRTYPE(rval)); 526 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 527 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 528 } 529 530 static void 531 pci_conf_print_bar(pc, tag, regs, reg, name) 532 pci_chipset_tag_t pc; 533 pcitag_t tag; 534 const pcireg_t *regs; 535 int reg; 536 const char *name; 537 { 538 int s; 539 pcireg_t mask, rval; 540 541 /* 542 * Section 6.2.5.1, `Address Maps', tells us that: 543 * 544 * 1) The builtin software should have already mapped the 545 * device in a reasonable way. 546 * 547 * 2) A device which wants 2^n bytes of memory will hardwire 548 * the bottom n bits of the address to 0. As recommended, 549 * we write all 1s and see what we get back. 550 */ 551 rval = regs[o2i(reg)]; 552 if (rval != 0) { 553 /* 554 * The following sequence seems to make some devices 555 * (e.g. host bus bridges, which don't normally 556 * have their space mapped) very unhappy, to 557 * the point of crashing the system. 558 * 559 * Therefore, if the mapping register is zero to 560 * start out with, don't bother trying. 561 */ 562 s = splhigh(); 563 pci_conf_write(pc, tag, reg, 0xffffffff); 564 mask = pci_conf_read(pc, tag, reg); 565 pci_conf_write(pc, tag, reg, rval); 566 splx(s); 567 } else 568 mask = 0; 569 570 printf(" Base address register at 0x%02x", reg); 571 if (name) 572 printf(" (%s)", name); 573 printf("\n "); 574 if (rval == 0) { 575 printf("not implemented(?)\n"); 576 return; 577 } 578 printf("type: "); 579 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 580 const char *type, *cache; 581 582 switch (PCI_MAPREG_MEM_TYPE(rval)) { 583 case PCI_MAPREG_MEM_TYPE_32BIT: 584 type = "32-bit"; 585 break; 586 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 587 type = "32-bit-1M"; 588 break; 589 case PCI_MAPREG_MEM_TYPE_64BIT: 590 type = "64-bit"; 591 break; 592 default: 593 type = "unknown (XXX)"; 594 break; 595 } 596 if (PCI_MAPREG_MEM_CACHEABLE(rval)) 597 cache = ""; 598 else 599 cache = "non"; 600 printf("%s %scacheable memory\n", type, cache); 601 printf(" base: 0x%08x, size: 0x%08x\n", 602 PCI_MAPREG_MEM_ADDR(rval), 603 PCI_MAPREG_MEM_SIZE(mask)); 604 } else { 605 printf("i/o\n"); 606 printf(" base: 0x%08x, size: 0x%08x\n", 607 PCI_MAPREG_IO_ADDR(rval), 608 PCI_MAPREG_IO_SIZE(mask)); 609 } 610 } 611 612 static void 613 pci_conf_print_regs(regs, first, pastlast) 614 const pcireg_t *regs; 615 int first, pastlast; 616 { 617 int off, needaddr, neednl; 618 619 needaddr = 1; 620 neednl = 0; 621 for (off = first; off < pastlast; off += 4) { 622 if ((off % 16) == 0 || needaddr) { 623 printf(" 0x%02x:", off); 624 needaddr = 0; 625 } 626 printf(" 0x%08x", regs[o2i(off)]); 627 neednl = 1; 628 if ((off % 16) == 12) { 629 printf("\n"); 630 neednl = 0; 631 } 632 } 633 if (neednl) 634 printf("\n"); 635 } 636 637 static void 638 pci_conf_print_type0(pc, tag, regs) 639 pci_chipset_tag_t pc; 640 pcitag_t tag; 641 const pcireg_t *regs; 642 { 643 int off; 644 pcireg_t rval; 645 646 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += 4) 647 pci_conf_print_bar(pc, tag, regs, off, NULL); 648 649 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 650 651 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 652 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 653 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 654 655 /* XXX */ 656 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 657 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 658 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 659 660 rval = regs[o2i(PCI_INTERRUPT_REG)]; 661 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 662 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 663 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 664 switch (PCI_INTERRUPT_PIN(rval)) { 665 case PCI_INTERRUPT_PIN_NONE: 666 printf("(none)"); 667 break; 668 case PCI_INTERRUPT_PIN_A: 669 printf("(pin A)"); 670 break; 671 case PCI_INTERRUPT_PIN_B: 672 printf("(pin B)"); 673 break; 674 case PCI_INTERRUPT_PIN_C: 675 printf("(pin C)"); 676 break; 677 case PCI_INTERRUPT_PIN_D: 678 printf("(pin D)"); 679 break; 680 default: 681 printf("(???)"); 682 break; 683 } 684 printf("\n"); 685 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 686 } 687 688 static void 689 pci_conf_print_type1(pc, tag, regs) 690 pci_chipset_tag_t pc; 691 pcitag_t tag; 692 const pcireg_t *regs; 693 { 694 int off; 695 pcireg_t rval; 696 697 /* 698 * XXX these need to be printed in more detail, need to be 699 * XXX checked against specs/docs, etc. 700 * 701 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 702 * Bridge chip documentation, and may not be correct with 703 * respect to various standards. (XXX) 704 */ 705 706 for (off = 0x10; off < 0x18; off += 4) 707 pci_conf_print_bar(pc, tag, regs, off, NULL); 708 709 printf(" Primary bus number: 0x%02x\n", 710 (regs[o2i(0x18)] >> 0) & 0xff); 711 printf(" Secondary bus number: 0x%02x\n", 712 (regs[o2i(0x18)] >> 8) & 0xff); 713 printf(" Subordinate bus number: 0x%02x\n", 714 (regs[o2i(0x18)] >> 16) & 0xff); 715 printf(" Secondary bus latency timer: 0x%02x\n", 716 (regs[o2i(0x18)] >> 24) & 0xff); 717 718 rval = (regs[o2i(0x1c)] >> 16) & 0xffff; 719 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 720 onoff("66 MHz capable", 0x0020); 721 onoff("User Definable Features (UDF) support", 0x0040); 722 onoff("Fast back-to-back capable", 0x0080); 723 onoff("Data parity error detected", 0x0100); 724 725 printf(" DEVSEL timing: "); 726 switch (rval & 0x0600) { 727 case 0x0000: 728 printf("fast"); 729 break; 730 case 0x0200: 731 printf("medium"); 732 break; 733 case 0x0400: 734 printf("slow"); 735 break; 736 default: 737 printf("unknown/reserved"); /* XXX */ 738 break; 739 } 740 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 741 742 onoff("Signaled Target Abort", 0x0800); 743 onoff("Received Target Abort", 0x1000); 744 onoff("Received Master Abort", 0x2000); 745 onoff("System Error", 0x4000); 746 onoff("Parity Error", 0x8000); 747 748 /* XXX Print more prettily */ 749 printf(" I/O region:\n"); 750 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 751 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 752 printf(" base upper 16 bits register: 0x%04x\n", 753 (regs[o2i(0x30)] >> 0) & 0xffff); 754 printf(" limit upper 16 bits register: 0x%04x\n", 755 (regs[o2i(0x30)] >> 16) & 0xffff); 756 757 /* XXX Print more prettily */ 758 printf(" Memory region:\n"); 759 printf(" base register: 0x%04x\n", 760 (regs[o2i(0x20)] >> 0) & 0xffff); 761 printf(" limit register: 0x%04x\n", 762 (regs[o2i(0x20)] >> 16) & 0xffff); 763 764 /* XXX Print more prettily */ 765 printf(" Prefetchable memory region:\n"); 766 printf(" base register: 0x%04x\n", 767 (regs[o2i(0x24)] >> 0) & 0xffff); 768 printf(" limit register: 0x%04x\n", 769 (regs[o2i(0x24)] >> 16) & 0xffff); 770 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 771 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 772 773 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 774 /* XXX */ 775 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 776 777 printf(" Interrupt line: 0x%02x\n", 778 (regs[o2i(0x3c)] >> 0) & 0xff); 779 printf(" Interrupt pin: 0x%02x ", 780 (regs[o2i(0x3c)] >> 8) & 0xff); 781 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 782 case PCI_INTERRUPT_PIN_NONE: 783 printf("(none)"); 784 break; 785 case PCI_INTERRUPT_PIN_A: 786 printf("(pin A)"); 787 break; 788 case PCI_INTERRUPT_PIN_B: 789 printf("(pin B)"); 790 break; 791 case PCI_INTERRUPT_PIN_C: 792 printf("(pin C)"); 793 break; 794 case PCI_INTERRUPT_PIN_D: 795 printf("(pin D)"); 796 break; 797 default: 798 printf("(???)"); 799 break; 800 } 801 printf("\n"); 802 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 803 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 804 onoff("Parity error response", 0x0001); 805 onoff("Secondary SERR forwarding", 0x0002); 806 onoff("ISA enable", 0x0004); 807 onoff("VGA enable", 0x0008); 808 onoff("Master abort reporting", 0x0020); 809 onoff("Secondary bus reset", 0x0040); 810 onoff("Fast back-to-back capable", 0x0080); 811 } 812 813 static void 814 pci_conf_print_type2(pc, tag, regs) 815 pci_chipset_tag_t pc; 816 pcitag_t tag; 817 const pcireg_t *regs; 818 { 819 pcireg_t rval; 820 821 /* 822 * XXX these need to be printed in more detail, need to be 823 * XXX checked against specs/docs, etc. 824 * 825 * This layout was cribbed from the TI PCI1130 PCI-to-CardBus 826 * controller chip documentation, and may not be correct with 827 * respect to various standards. (XXX) 828 */ 829 830 pci_conf_print_bar(pc, tag, regs, 0x10, 831 "CardBus socket/ExCA registers"); 832 833 printf(" Reserved @ 0x14: 0x%04x\n", 834 (regs[o2i(0x14)] >> 0) & 0xffff); 835 rval = (regs[o2i(0x14)] >> 16) & 0xffff; 836 printf(" Secondary status register: 0x%04x\n", rval); 837 onoff("66 MHz capable", 0x0020); 838 onoff("User Definable Features (UDF) support", 0x0040); 839 onoff("Fast back-to-back capable", 0x0080); 840 onoff("Data parity error detection", 0x0100); 841 842 printf(" DEVSEL timing: "); 843 switch (rval & 0x0600) { 844 case 0x0000: 845 printf("fast"); 846 break; 847 case 0x0200: 848 printf("medium"); 849 break; 850 case 0x0400: 851 printf("slow"); 852 break; 853 default: 854 printf("unknown/reserved"); /* XXX */ 855 break; 856 } 857 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 858 onoff("PCI target aborts terminate CardBus bus master transactions", 859 0x0800); 860 onoff("CardBus target aborts terminate PCI bus master transactions", 861 0x1000); 862 onoff("Bus initiator aborts terminate initiator transactions", 863 0x2000); 864 onoff("System error", 0x4000); 865 onoff("Parity error", 0x8000); 866 867 printf(" PCI bus number: 0x%02x\n", 868 (regs[o2i(0x18)] >> 0) & 0xff); 869 printf(" CardBus bus number: 0x%02x\n", 870 (regs[o2i(0x18)] >> 8) & 0xff); 871 printf(" Subordinate bus number: 0x%02x\n", 872 (regs[o2i(0x18)] >> 16) & 0xff); 873 printf(" CardBus latency timer: 0x%02x\n", 874 (regs[o2i(0x18)] >> 24) & 0xff); 875 876 /* XXX Print more prettily */ 877 printf(" CardBus memory region 0:\n"); 878 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 879 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 880 printf(" CardBus memory region 1:\n"); 881 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 882 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 883 printf(" CardBus I/O region 0:\n"); 884 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 885 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 886 printf(" CardBus I/O region 1:\n"); 887 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 888 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 889 890 printf(" Interrupt line: 0x%02x\n", 891 (regs[o2i(0x3c)] >> 0) & 0xff); 892 printf(" Interrupt pin: 0x%02x ", 893 (regs[o2i(0x3c)] >> 8) & 0xff); 894 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 895 case PCI_INTERRUPT_PIN_NONE: 896 printf("(none)"); 897 break; 898 case PCI_INTERRUPT_PIN_A: 899 printf("(pin A)"); 900 break; 901 case PCI_INTERRUPT_PIN_B: 902 printf("(pin B)"); 903 break; 904 case PCI_INTERRUPT_PIN_C: 905 printf("(pin C)"); 906 break; 907 case PCI_INTERRUPT_PIN_D: 908 printf("(pin D)"); 909 break; 910 default: 911 printf("(???)"); 912 break; 913 } 914 printf("\n"); 915 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 916 printf(" Bridge control register: 0x%04x\n", rval); 917 onoff("Parity error response", 0x0001); 918 onoff("CardBus SERR forwarding", 0x0002); 919 onoff("ISA enable", 0x0004); 920 onoff("VGA enable", 0x0008); 921 onoff("CardBus master abort reporting", 0x0020); 922 onoff("CardBus reset", 0x0040); 923 onoff("Functional interrupts routed by ExCA registers", 0x0080); 924 onoff("Memory window 0 prefetchable", 0x0100); 925 onoff("Memory window 1 prefetchable", 0x0200); 926 onoff("Write posting enable", 0x0400); 927 928 rval = regs[o2i(0x40)]; 929 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 930 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 931 932 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers"); 933 } 934 935 void 936 pci_conf_print(pc, tag, printfn) 937 pci_chipset_tag_t pc; 938 pcitag_t tag; 939 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 940 { 941 pcireg_t regs[o2i(256)]; 942 int off, endoff, hdrtype; 943 const char *typename; 944 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 945 946 printf("PCI configuration registers:\n"); 947 948 for (off = 0; off < 256; off += 4) 949 regs[o2i(off)] = pci_conf_read(pc, tag, off); 950 951 /* common header */ 952 printf(" Common header:\n"); 953 pci_conf_print_regs(regs, 0, 16); 954 955 printf("\n"); 956 pci_conf_print_common(pc, tag, regs); 957 printf("\n"); 958 959 /* type-dependent header */ 960 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 961 switch (hdrtype) { /* XXX make a table, eventually */ 962 case 0: 963 /* Standard device header */ 964 typename = "\"normal\" device"; 965 typeprintfn = &pci_conf_print_type0; 966 endoff = 64; 967 break; 968 case 1: 969 /* PCI-PCI bridge header */ 970 typename = "PCI-PCI bridge"; 971 typeprintfn = &pci_conf_print_type1; 972 endoff = 64; 973 break; 974 case 2: 975 /* PCI-CardBus bridge header */ 976 typename = "PCI-CardBus bridge"; 977 typeprintfn = &pci_conf_print_type2; 978 endoff = 72; 979 break; 980 default: 981 typename = NULL; 982 typeprintfn = 0; 983 endoff = 64; 984 break; 985 } 986 printf(" Type %d ", hdrtype); 987 if (typename != NULL) 988 printf("(%s) ", typename); 989 printf("header:\n"); 990 pci_conf_print_regs(regs, 16, endoff); 991 printf("\n"); 992 if (typeprintfn) 993 (*typeprintfn)(pc, tag, regs); 994 else 995 printf(" Don't know how to pretty-print type %d header.\n", 996 hdrtype); 997 printf("\n"); 998 999 /* device-dependent header */ 1000 printf(" Device-dependent header:\n"); 1001 pci_conf_print_regs(regs, endoff, 256); 1002 printf("\n"); 1003 if (printfn) 1004 (*printfn)(pc, tag, regs); 1005 else 1006 printf(" Don't know how to pretty-print device-dependent header.\n"); 1007 printf("\n"); 1008 } 1009
Indexes created Thu Sep 25 08:09:54 GMT 2025