pci_subr.c revision 1.35.4.2
1 /* $NetBSD: pci_subr.c,v 1.35.4.2 2001/10/25 17:54:51 he Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 */ 38 39 #include "opt_pci.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 45 #include <machine/intr.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #ifdef PCIVERBOSE 50 #include <dev/pci/pcidevs.h> 51 #endif 52 53 static void pci_conf_print_common __P((pci_chipset_tag_t, pcitag_t, 54 const pcireg_t *regs)); 55 static int pci_conf_print_bar __P((pci_chipset_tag_t, pcitag_t, 56 const pcireg_t *regs, int, const char *)); 57 static void pci_conf_print_regs __P((const pcireg_t *regs, int first, 58 int pastlast)); 59 static void pci_conf_print_type0 __P((pci_chipset_tag_t, pcitag_t, 60 const pcireg_t *regs)); 61 static void pci_conf_print_type1 __P((pci_chipset_tag_t, pcitag_t, 62 const pcireg_t *regs)); 63 static void pci_conf_print_type2 __P((pci_chipset_tag_t, pcitag_t, 64 const pcireg_t *regs)); 65 66 /* 67 * Descriptions of known PCI classes and subclasses. 68 * 69 * Subclasses are described in the same way as classes, but have a 70 * NULL subclass pointer. 71 */ 72 struct pci_class { 73 char *name; 74 int val; /* as wide as pci_{,sub}class_t */ 75 struct pci_class *subclasses; 76 }; 77 78 struct pci_class pci_subclass_prehistoric[] = { 79 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, }, 80 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, }, 81 { 0 } 82 }; 83 84 struct pci_class pci_subclass_mass_storage[] = { 85 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, }, 86 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, }, 87 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, }, 88 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, }, 89 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, }, 90 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, }, 91 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, }, 92 { 0 }, 93 }; 94 95 struct pci_class pci_subclass_network[] = { 96 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, }, 97 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, }, 98 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, }, 99 { "ATM", PCI_SUBCLASS_NETWORK_ATM, }, 100 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, }, 101 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, }, 102 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, }, 103 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, }, 104 { 0 }, 105 }; 106 107 struct pci_class pci_subclass_display[] = { 108 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, }, 109 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, }, 110 { "3D", PCI_SUBCLASS_DISPLAY_3D, }, 111 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, }, 112 { 0 }, 113 }; 114 115 struct pci_class pci_subclass_multimedia[] = { 116 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, }, 117 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, }, 118 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, }, 119 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, }, 120 { 0 }, 121 }; 122 123 struct pci_class pci_subclass_memory[] = { 124 { "RAM", PCI_SUBCLASS_MEMORY_RAM, }, 125 { "flash", PCI_SUBCLASS_MEMORY_FLASH, }, 126 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, }, 127 { 0 }, 128 }; 129 130 struct pci_class pci_subclass_bridge[] = { 131 { "host", PCI_SUBCLASS_BRIDGE_HOST, }, 132 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, }, 133 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, }, 134 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, }, 135 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, }, 136 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, }, 137 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, }, 138 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, }, 139 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, }, 140 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, }, 141 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, }, 142 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, }, 143 { 0 }, 144 }; 145 146 struct pci_class pci_subclass_communications[] = { 147 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, }, 148 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, }, 149 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, }, 150 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, }, 151 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, }, 152 { 0 }, 153 }; 154 155 struct pci_class pci_subclass_system[] = { 156 { "8259 PIC", PCI_SUBCLASS_SYSTEM_PIC, }, 157 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, }, 158 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, }, 159 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, }, 160 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_RTC, }, 161 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, }, 162 { 0 }, 163 }; 164 165 struct pci_class pci_subclass_input[] = { 166 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, }, 167 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, }, 168 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, }, 169 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, }, 170 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, }, 171 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, }, 172 { 0 }, 173 }; 174 175 struct pci_class pci_subclass_dock[] = { 176 { "generic", PCI_SUBCLASS_DOCK_GENERIC, }, 177 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, }, 178 { 0 }, 179 }; 180 181 struct pci_class pci_subclass_processor[] = { 182 { "386", PCI_SUBCLASS_PROCESSOR_386, }, 183 { "486", PCI_SUBCLASS_PROCESSOR_486, }, 184 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, }, 185 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, }, 186 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, }, 187 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, }, 188 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, }, 189 { 0 }, 190 }; 191 192 struct pci_class pci_subclass_serialbus[] = { 193 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, }, 194 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, }, 195 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, }, 196 { "USB", PCI_SUBCLASS_SERIALBUS_USB, }, 197 /* XXX Fiber Channel/_FIBRECHANNEL */ 198 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, }, 199 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, }, 200 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, }, 201 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, }, 202 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, }, 203 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, }, 204 { 0 }, 205 }; 206 207 struct pci_class pci_subclass_wireless[] = { 208 { "iRDA", PCI_SUBCLASS_WIRELESS_IRDA, }, 209 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, }, 210 { "RF", PCI_SUBCLASS_WIRELESS_RF, }, 211 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, }, 212 { 0 }, 213 }; 214 215 struct pci_class pci_subclass_i2o[] = { 216 { "standard", PCI_SUBCLASS_I2O_STANDARD, }, 217 { 0 }, 218 }; 219 220 struct pci_class pci_subclass_satcom[] = { 221 { "TV", PCI_SUBCLASS_SATCOM_TV, }, 222 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, }, 223 { "voice", PCI_SUBCLASS_SATCOM_VOICE, }, 224 { "data", PCI_SUBCLASS_SATCOM_DATA, }, 225 { 0 }, 226 }; 227 228 struct pci_class pci_subclass_crypto[] = { 229 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, }, 230 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, }, 231 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, }, 232 { 0 }, 233 }; 234 235 struct pci_class pci_subclass_dasp[] = { 236 { "DPIO", PCI_SUBCLASS_DASP_DPIO, }, 237 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, }, 238 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, }, 239 { 0 }, 240 }; 241 242 struct pci_class pci_class[] = { 243 { "prehistoric", PCI_CLASS_PREHISTORIC, 244 pci_subclass_prehistoric, }, 245 { "mass storage", PCI_CLASS_MASS_STORAGE, 246 pci_subclass_mass_storage, }, 247 { "network", PCI_CLASS_NETWORK, 248 pci_subclass_network, }, 249 { "display", PCI_CLASS_DISPLAY, 250 pci_subclass_display, }, 251 { "multimedia", PCI_CLASS_MULTIMEDIA, 252 pci_subclass_multimedia, }, 253 { "memory", PCI_CLASS_MEMORY, 254 pci_subclass_memory, }, 255 { "bridge", PCI_CLASS_BRIDGE, 256 pci_subclass_bridge, }, 257 { "communications", PCI_CLASS_COMMUNICATIONS, 258 pci_subclass_communications, }, 259 { "system", PCI_CLASS_SYSTEM, 260 pci_subclass_system, }, 261 { "input", PCI_CLASS_INPUT, 262 pci_subclass_input, }, 263 { "dock", PCI_CLASS_DOCK, 264 pci_subclass_dock, }, 265 { "processor", PCI_CLASS_PROCESSOR, 266 pci_subclass_processor, }, 267 { "serial bus", PCI_CLASS_SERIALBUS, 268 pci_subclass_serialbus, }, 269 { "wireless", PCI_CLASS_WIRELESS, 270 pci_subclass_wireless, }, 271 { "I2O", PCI_CLASS_I2O, 272 pci_subclass_i2o, }, 273 { "satellite comm", PCI_CLASS_SATCOM, 274 pci_subclass_satcom, }, 275 { "crypto", PCI_CLASS_CRYPTO, 276 pci_subclass_crypto, }, 277 { "DASP", PCI_CLASS_DASP, 278 pci_subclass_dasp, }, 279 { "undefined", PCI_CLASS_UNDEFINED, 280 0, }, 281 { 0 }, 282 }; 283 284 #ifdef PCIVERBOSE 285 /* 286 * Descriptions of of known vendors and devices ("products"). 287 */ 288 struct pci_knowndev { 289 pci_vendor_id_t vendor; 290 pci_product_id_t product; 291 int flags; 292 char *vendorname, *productname; 293 }; 294 #define PCI_KNOWNDEV_NOPROD 0x01 /* match on vendor only */ 295 296 #include <dev/pci/pcidevs_data.h> 297 #endif /* PCIVERBOSE */ 298 299 char * 300 pci_findvendor(id_reg) 301 pcireg_t id_reg; 302 { 303 #ifdef PCIVERBOSE 304 pci_vendor_id_t vendor = PCI_VENDOR(id_reg); 305 struct pci_knowndev *kdp; 306 307 kdp = pci_knowndevs; 308 while (kdp->vendorname != NULL) { /* all have vendor name */ 309 if (kdp->vendor == vendor) 310 break; 311 kdp++; 312 } 313 return (kdp->vendorname); 314 #else 315 return (NULL); 316 #endif 317 } 318 319 void 320 pci_devinfo(id_reg, class_reg, showclass, cp) 321 pcireg_t id_reg, class_reg; 322 int showclass; 323 char *cp; 324 { 325 pci_vendor_id_t vendor; 326 pci_product_id_t product; 327 pci_class_t class; 328 pci_subclass_t subclass; 329 pci_interface_t interface; 330 pci_revision_t revision; 331 char *vendor_namep, *product_namep; 332 struct pci_class *classp, *subclassp; 333 #ifdef PCIVERBOSE 334 struct pci_knowndev *kdp; 335 const char *unmatched = "unknown "; 336 #else 337 const char *unmatched = ""; 338 #endif 339 340 vendor = PCI_VENDOR(id_reg); 341 product = PCI_PRODUCT(id_reg); 342 343 class = PCI_CLASS(class_reg); 344 subclass = PCI_SUBCLASS(class_reg); 345 interface = PCI_INTERFACE(class_reg); 346 revision = PCI_REVISION(class_reg); 347 348 #ifdef PCIVERBOSE 349 kdp = pci_knowndevs; 350 while (kdp->vendorname != NULL) { /* all have vendor name */ 351 if (kdp->vendor == vendor && (kdp->product == product || 352 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) 353 break; 354 kdp++; 355 } 356 if (kdp->vendorname == NULL) 357 vendor_namep = product_namep = NULL; 358 else { 359 vendor_namep = kdp->vendorname; 360 product_namep = (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0 ? 361 kdp->productname : NULL; 362 } 363 #else /* PCIVERBOSE */ 364 vendor_namep = product_namep = NULL; 365 #endif /* PCIVERBOSE */ 366 367 classp = pci_class; 368 while (classp->name != NULL) { 369 if (class == classp->val) 370 break; 371 classp++; 372 } 373 374 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 375 while (subclassp && subclassp->name != NULL) { 376 if (subclass == subclassp->val) 377 break; 378 subclassp++; 379 } 380 381 if (vendor_namep == NULL) 382 cp += sprintf(cp, "%svendor 0x%04x product 0x%04x", 383 unmatched, vendor, product); 384 else if (product_namep != NULL) 385 cp += sprintf(cp, "%s %s", vendor_namep, product_namep); 386 else 387 cp += sprintf(cp, "%s product 0x%04x", 388 vendor_namep, product); 389 if (showclass) { 390 cp += sprintf(cp, " ("); 391 if (classp->name == NULL) 392 cp += sprintf(cp, "class 0x%02x, subclass 0x%02x", 393 class, subclass); 394 else { 395 if (subclassp == NULL || subclassp->name == NULL) 396 cp += sprintf(cp, 397 "%s subclass 0x%02x", 398 classp->name, subclass); 399 else 400 cp += sprintf(cp, "%s %s", 401 subclassp->name, classp->name); 402 } 403 if (interface != 0) 404 cp += sprintf(cp, ", interface 0x%02x", interface); 405 if (revision != 0) 406 cp += sprintf(cp, ", revision 0x%02x", revision); 407 cp += sprintf(cp, ")"); 408 } 409 } 410 411 /* 412 * Print out most of the PCI configuration registers. Typically used 413 * in a device attach routine like this: 414 * 415 * #ifdef MYDEV_DEBUG 416 * printf("%s: ", sc->sc_dev.dv_xname); 417 * pci_conf_print(pa->pa_pc, pa->pa_tag); 418 * #endif 419 */ 420 421 #define i2o(i) ((i) * 4) 422 #define o2i(o) ((o) / 4) 423 #define onoff(str, bit) \ 424 printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off"); 425 426 static void 427 pci_conf_print_common(pc, tag, regs) 428 pci_chipset_tag_t pc; 429 pcitag_t tag; 430 const pcireg_t *regs; 431 { 432 #ifdef PCIVERBOSE 433 struct pci_knowndev *kdp; 434 #endif 435 struct pci_class *classp, *subclassp; 436 pcireg_t rval; 437 438 rval = regs[o2i(PCI_ID_REG)]; 439 #ifndef PCIVERBOSE 440 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 441 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 442 #else 443 for (kdp = pci_knowndevs; kdp->vendorname != NULL; kdp++) { 444 if (kdp->vendor == PCI_VENDOR(rval) && 445 (kdp->product == PCI_PRODUCT(rval) || 446 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) { 447 break; 448 } 449 } 450 if (kdp->vendorname != NULL) 451 printf(" Vendor Name: %s (0x%04x)\n", kdp->vendorname, 452 PCI_VENDOR(rval)); 453 else 454 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 455 if (kdp->productname != NULL && (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0) 456 printf(" Device Name: %s (0x%04x)\n", kdp->productname, 457 PCI_PRODUCT(rval)); 458 else 459 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 460 #endif /* PCIVERBOSE */ 461 462 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 463 464 printf(" Command register: 0x%04x\n", rval & 0xffff); 465 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 466 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 467 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 468 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 469 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 470 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 471 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 472 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 473 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 474 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 475 476 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 477 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 478 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 479 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 480 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 481 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 482 483 printf(" DEVSEL timing: "); 484 switch (rval & PCI_STATUS_DEVSEL_MASK) { 485 case PCI_STATUS_DEVSEL_FAST: 486 printf("fast"); 487 break; 488 case PCI_STATUS_DEVSEL_MEDIUM: 489 printf("medium"); 490 break; 491 case PCI_STATUS_DEVSEL_SLOW: 492 printf("slow"); 493 break; 494 default: 495 printf("unknown/reserved"); /* XXX */ 496 break; 497 } 498 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 499 500 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 501 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 502 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 503 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 504 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 505 506 rval = regs[o2i(PCI_CLASS_REG)]; 507 for (classp = pci_class; classp->name != NULL; classp++) { 508 if (PCI_CLASS(rval) == classp->val) 509 break; 510 } 511 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 512 while (subclassp && subclassp->name != NULL) { 513 if (PCI_SUBCLASS(rval) == subclassp->val) 514 break; 515 subclassp++; 516 } 517 if (classp->name != NULL) { 518 printf(" Class Name: %s (0x%02x)\n", classp->name, 519 PCI_CLASS(rval)); 520 if (subclassp != NULL && subclassp->name != NULL) 521 printf(" Subclass Name: %s (0x%02x)\n", 522 subclassp->name, PCI_SUBCLASS(rval)); 523 else 524 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 525 } else { 526 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 527 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 528 } 529 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 530 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 531 532 rval = regs[o2i(PCI_BHLC_REG)]; 533 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 534 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 535 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 536 PCI_HDRTYPE(rval)); 537 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 538 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 539 } 540 541 static int 542 pci_conf_print_bar(pc, tag, regs, reg, name) 543 pci_chipset_tag_t pc; 544 pcitag_t tag; 545 const pcireg_t *regs; 546 int reg; 547 const char *name; 548 { 549 int s, width; 550 pcireg_t mask, rval; 551 pcireg_t mask64h, rval64h; 552 553 width = 4; 554 555 /* 556 * Section 6.2.5.1, `Address Maps', tells us that: 557 * 558 * 1) The builtin software should have already mapped the 559 * device in a reasonable way. 560 * 561 * 2) A device which wants 2^n bytes of memory will hardwire 562 * the bottom n bits of the address to 0. As recommended, 563 * we write all 1s and see what we get back. 564 */ 565 rval = regs[o2i(reg)]; 566 if (rval != 0) { 567 /* 568 * The following sequence seems to make some devices 569 * (e.g. host bus bridges, which don't normally 570 * have their space mapped) very unhappy, to 571 * the point of crashing the system. 572 * 573 * Therefore, if the mapping register is zero to 574 * start out with, don't bother trying. 575 */ 576 s = splhigh(); 577 pci_conf_write(pc, tag, reg, 0xffffffff); 578 mask = pci_conf_read(pc, tag, reg); 579 pci_conf_write(pc, tag, reg, rval); 580 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 581 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 582 rval64h = regs[o2i(reg + 4)]; 583 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 584 mask64h = pci_conf_read(pc, tag, reg + 4); 585 pci_conf_write(pc, tag, reg + 4, rval64h); 586 width = 8; 587 } 588 splx(s); 589 } else 590 mask = 0; 591 592 printf(" Base address register at 0x%02x", reg); 593 if (name) 594 printf(" (%s)", name); 595 printf("\n "); 596 if (rval == 0) { 597 printf("not implemented(?)\n"); 598 return width; 599 } 600 printf("type: "); 601 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 602 const char *type, *prefetch; 603 604 switch (PCI_MAPREG_MEM_TYPE(rval)) { 605 case PCI_MAPREG_MEM_TYPE_32BIT: 606 type = "32-bit"; 607 break; 608 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 609 type = "32-bit-1M"; 610 break; 611 case PCI_MAPREG_MEM_TYPE_64BIT: 612 type = "64-bit"; 613 break; 614 default: 615 type = "unknown (XXX)"; 616 break; 617 } 618 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 619 prefetch = ""; 620 else 621 prefetch = "non"; 622 printf("%s %sprefetchable memory\n", type, prefetch); 623 switch (PCI_MAPREG_MEM_TYPE(rval)) { 624 case PCI_MAPREG_MEM_TYPE_64BIT: 625 printf(" base: 0x%016llx, size: 0x%016llx\n", 626 PCI_MAPREG_MEM64_ADDR( 627 ((((long long) rval64h) << 32) | rval)), 628 PCI_MAPREG_MEM64_SIZE( 629 ((((long long) mask64h) << 32) | mask))); 630 break; 631 case PCI_MAPREG_MEM_TYPE_32BIT: 632 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 633 default: 634 printf(" base: 0x%08x, size: 0x%08x\n", 635 PCI_MAPREG_MEM_ADDR(rval), 636 PCI_MAPREG_MEM_SIZE(mask)); 637 break; 638 } 639 640 } else { 641 printf("i/o\n"); 642 printf(" base: 0x%08x, size: 0x%08x\n", 643 PCI_MAPREG_IO_ADDR(rval), 644 PCI_MAPREG_IO_SIZE(mask)); 645 } 646 647 return width; 648 } 649 650 static void 651 pci_conf_print_regs(regs, first, pastlast) 652 const pcireg_t *regs; 653 int first, pastlast; 654 { 655 int off, needaddr, neednl; 656 657 needaddr = 1; 658 neednl = 0; 659 for (off = first; off < pastlast; off += 4) { 660 if ((off % 16) == 0 || needaddr) { 661 printf(" 0x%02x:", off); 662 needaddr = 0; 663 } 664 printf(" 0x%08x", regs[o2i(off)]); 665 neednl = 1; 666 if ((off % 16) == 12) { 667 printf("\n"); 668 neednl = 0; 669 } 670 } 671 if (neednl) 672 printf("\n"); 673 } 674 675 static void 676 pci_conf_print_type0(pc, tag, regs) 677 pci_chipset_tag_t pc; 678 pcitag_t tag; 679 const pcireg_t *regs; 680 { 681 int off, width; 682 pcireg_t rval; 683 684 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) 685 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 686 687 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 688 689 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 690 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 691 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 692 693 /* XXX */ 694 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 695 696 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 697 printf(" Capability list pointer: 0x%02x\n", 698 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 699 else 700 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 701 702 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 703 704 rval = regs[o2i(PCI_INTERRUPT_REG)]; 705 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 706 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 707 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 708 switch (PCI_INTERRUPT_PIN(rval)) { 709 case PCI_INTERRUPT_PIN_NONE: 710 printf("(none)"); 711 break; 712 case PCI_INTERRUPT_PIN_A: 713 printf("(pin A)"); 714 break; 715 case PCI_INTERRUPT_PIN_B: 716 printf("(pin B)"); 717 break; 718 case PCI_INTERRUPT_PIN_C: 719 printf("(pin C)"); 720 break; 721 case PCI_INTERRUPT_PIN_D: 722 printf("(pin D)"); 723 break; 724 default: 725 printf("(? ? ?)"); 726 break; 727 } 728 printf("\n"); 729 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 730 731 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) { 732 for (off = PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]); 733 off != 0; 734 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 735 rval = regs[o2i(off)]; 736 printf(" Capability register at 0x%02x\n", off); 737 738 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 739 switch (PCI_CAPLIST_CAP(rval)) { 740 case PCI_CAP_RESERVED0: 741 printf("reserved"); 742 break; 743 case PCI_CAP_PWRMGMT: 744 printf("Power Management, rev. %d.0", 745 (rval >> 0) & 0x07); /* XXX not clear */ 746 break; 747 case PCI_CAP_AGP: 748 printf("AGP, rev. %d.%d", 749 (rval >> 24) & 0x0f, 750 (rval >> 20) & 0x0f); 751 break; 752 case PCI_CAP_VPD: 753 printf("VPD"); 754 break; 755 case PCI_CAP_SLOTID: 756 printf("SlotID"); 757 break; 758 case PCI_CAP_MBI: 759 printf("MBI"); 760 break; 761 case PCI_CAP_CPCI_HOTSWAP: 762 printf("CompactPCI Hot-swapping"); 763 break; 764 case PCI_CAP_PCIX: 765 printf("PCI-X"); 766 break; 767 case PCI_CAP_LDT: 768 printf("LDT"); 769 break; 770 case PCI_CAP_VENDSPEC: 771 printf("Vendor-specific"); 772 break; 773 case PCI_CAP_DEBUGPORT: 774 printf("Debug Port"); 775 break; 776 case PCI_CAP_CPCI_RSRCCTL: 777 printf("CompactPCI Resource Control"); 778 break; 779 case PCI_CAP_HOTPLUG: 780 printf("Hot-Plug"); 781 break; 782 default: 783 printf("unknown"); 784 } 785 printf(")\n"); 786 } 787 } 788 } 789 790 static void 791 pci_conf_print_type1(pc, tag, regs) 792 pci_chipset_tag_t pc; 793 pcitag_t tag; 794 const pcireg_t *regs; 795 { 796 int off, width; 797 pcireg_t rval; 798 799 /* 800 * XXX these need to be printed in more detail, need to be 801 * XXX checked against specs/docs, etc. 802 * 803 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 804 * Bridge chip documentation, and may not be correct with 805 * respect to various standards. (XXX) 806 */ 807 808 for (off = 0x10; off < 0x18; off += width) 809 width = pci_conf_print_bar(pc, tag, regs, off, NULL); 810 811 printf(" Primary bus number: 0x%02x\n", 812 (regs[o2i(0x18)] >> 0) & 0xff); 813 printf(" Secondary bus number: 0x%02x\n", 814 (regs[o2i(0x18)] >> 8) & 0xff); 815 printf(" Subordinate bus number: 0x%02x\n", 816 (regs[o2i(0x18)] >> 16) & 0xff); 817 printf(" Secondary bus latency timer: 0x%02x\n", 818 (regs[o2i(0x18)] >> 24) & 0xff); 819 820 rval = (regs[o2i(0x1c)] >> 16) & 0xffff; 821 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 822 onoff("66 MHz capable", 0x0020); 823 onoff("User Definable Features (UDF) support", 0x0040); 824 onoff("Fast back-to-back capable", 0x0080); 825 onoff("Data parity error detected", 0x0100); 826 827 printf(" DEVSEL timing: "); 828 switch (rval & 0x0600) { 829 case 0x0000: 830 printf("fast"); 831 break; 832 case 0x0200: 833 printf("medium"); 834 break; 835 case 0x0400: 836 printf("slow"); 837 break; 838 default: 839 printf("unknown/reserved"); /* XXX */ 840 break; 841 } 842 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 843 844 onoff("Signaled Target Abort", 0x0800); 845 onoff("Received Target Abort", 0x1000); 846 onoff("Received Master Abort", 0x2000); 847 onoff("System Error", 0x4000); 848 onoff("Parity Error", 0x8000); 849 850 /* XXX Print more prettily */ 851 printf(" I/O region:\n"); 852 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 853 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 854 printf(" base upper 16 bits register: 0x%04x\n", 855 (regs[o2i(0x30)] >> 0) & 0xffff); 856 printf(" limit upper 16 bits register: 0x%04x\n", 857 (regs[o2i(0x30)] >> 16) & 0xffff); 858 859 /* XXX Print more prettily */ 860 printf(" Memory region:\n"); 861 printf(" base register: 0x%04x\n", 862 (regs[o2i(0x20)] >> 0) & 0xffff); 863 printf(" limit register: 0x%04x\n", 864 (regs[o2i(0x20)] >> 16) & 0xffff); 865 866 /* XXX Print more prettily */ 867 printf(" Prefetchable memory region:\n"); 868 printf(" base register: 0x%04x\n", 869 (regs[o2i(0x24)] >> 0) & 0xffff); 870 printf(" limit register: 0x%04x\n", 871 (regs[o2i(0x24)] >> 16) & 0xffff); 872 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 873 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 874 875 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 876 /* XXX */ 877 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 878 879 printf(" Interrupt line: 0x%02x\n", 880 (regs[o2i(0x3c)] >> 0) & 0xff); 881 printf(" Interrupt pin: 0x%02x ", 882 (regs[o2i(0x3c)] >> 8) & 0xff); 883 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 884 case PCI_INTERRUPT_PIN_NONE: 885 printf("(none)"); 886 break; 887 case PCI_INTERRUPT_PIN_A: 888 printf("(pin A)"); 889 break; 890 case PCI_INTERRUPT_PIN_B: 891 printf("(pin B)"); 892 break; 893 case PCI_INTERRUPT_PIN_C: 894 printf("(pin C)"); 895 break; 896 case PCI_INTERRUPT_PIN_D: 897 printf("(pin D)"); 898 break; 899 default: 900 printf("(? ? ?)"); 901 break; 902 } 903 printf("\n"); 904 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 905 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 906 onoff("Parity error response", 0x0001); 907 onoff("Secondary SERR forwarding", 0x0002); 908 onoff("ISA enable", 0x0004); 909 onoff("VGA enable", 0x0008); 910 onoff("Master abort reporting", 0x0020); 911 onoff("Secondary bus reset", 0x0040); 912 onoff("Fast back-to-back capable", 0x0080); 913 } 914 915 static void 916 pci_conf_print_type2(pc, tag, regs) 917 pci_chipset_tag_t pc; 918 pcitag_t tag; 919 const pcireg_t *regs; 920 { 921 pcireg_t rval; 922 923 /* 924 * XXX these need to be printed in more detail, need to be 925 * XXX checked against specs/docs, etc. 926 * 927 * This layout was cribbed from the TI PCI1130 PCI-to-CardBus 928 * controller chip documentation, and may not be correct with 929 * respect to various standards. (XXX) 930 */ 931 932 pci_conf_print_bar(pc, tag, regs, 0x10, 933 "CardBus socket/ExCA registers"); 934 935 printf(" Reserved @ 0x14: 0x%04x\n", 936 (regs[o2i(0x14)] >> 0) & 0xffff); 937 rval = (regs[o2i(0x14)] >> 16) & 0xffff; 938 printf(" Secondary status register: 0x%04x\n", rval); 939 onoff("66 MHz capable", 0x0020); 940 onoff("User Definable Features (UDF) support", 0x0040); 941 onoff("Fast back-to-back capable", 0x0080); 942 onoff("Data parity error detection", 0x0100); 943 944 printf(" DEVSEL timing: "); 945 switch (rval & 0x0600) { 946 case 0x0000: 947 printf("fast"); 948 break; 949 case 0x0200: 950 printf("medium"); 951 break; 952 case 0x0400: 953 printf("slow"); 954 break; 955 default: 956 printf("unknown/reserved"); /* XXX */ 957 break; 958 } 959 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 960 onoff("PCI target aborts terminate CardBus bus master transactions", 961 0x0800); 962 onoff("CardBus target aborts terminate PCI bus master transactions", 963 0x1000); 964 onoff("Bus initiator aborts terminate initiator transactions", 965 0x2000); 966 onoff("System error", 0x4000); 967 onoff("Parity error", 0x8000); 968 969 printf(" PCI bus number: 0x%02x\n", 970 (regs[o2i(0x18)] >> 0) & 0xff); 971 printf(" CardBus bus number: 0x%02x\n", 972 (regs[o2i(0x18)] >> 8) & 0xff); 973 printf(" Subordinate bus number: 0x%02x\n", 974 (regs[o2i(0x18)] >> 16) & 0xff); 975 printf(" CardBus latency timer: 0x%02x\n", 976 (regs[o2i(0x18)] >> 24) & 0xff); 977 978 /* XXX Print more prettily */ 979 printf(" CardBus memory region 0:\n"); 980 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 981 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 982 printf(" CardBus memory region 1:\n"); 983 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 984 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 985 printf(" CardBus I/O region 0:\n"); 986 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 987 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 988 printf(" CardBus I/O region 1:\n"); 989 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 990 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 991 992 printf(" Interrupt line: 0x%02x\n", 993 (regs[o2i(0x3c)] >> 0) & 0xff); 994 printf(" Interrupt pin: 0x%02x ", 995 (regs[o2i(0x3c)] >> 8) & 0xff); 996 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 997 case PCI_INTERRUPT_PIN_NONE: 998 printf("(none)"); 999 break; 1000 case PCI_INTERRUPT_PIN_A: 1001 printf("(pin A)"); 1002 break; 1003 case PCI_INTERRUPT_PIN_B: 1004 printf("(pin B)"); 1005 break; 1006 case PCI_INTERRUPT_PIN_C: 1007 printf("(pin C)"); 1008 break; 1009 case PCI_INTERRUPT_PIN_D: 1010 printf("(pin D)"); 1011 break; 1012 default: 1013 printf("(? ? ?)"); 1014 break; 1015 } 1016 printf("\n"); 1017 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1018 printf(" Bridge control register: 0x%04x\n", rval); 1019 onoff("Parity error response", 0x0001); 1020 onoff("CardBus SERR forwarding", 0x0002); 1021 onoff("ISA enable", 0x0004); 1022 onoff("VGA enable", 0x0008); 1023 onoff("CardBus master abort reporting", 0x0020); 1024 onoff("CardBus reset", 0x0040); 1025 onoff("Functional interrupts routed by ExCA registers", 0x0080); 1026 onoff("Memory window 0 prefetchable", 0x0100); 1027 onoff("Memory window 1 prefetchable", 0x0200); 1028 onoff("Write posting enable", 0x0400); 1029 1030 rval = regs[o2i(0x40)]; 1031 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1032 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1033 1034 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers"); 1035 } 1036 1037 void 1038 pci_conf_print(pc, tag, printfn) 1039 pci_chipset_tag_t pc; 1040 pcitag_t tag; 1041 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 1042 { 1043 pcireg_t regs[o2i(256)]; 1044 int off, endoff, hdrtype; 1045 const char *typename; 1046 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 1047 1048 printf("PCI configuration registers:\n"); 1049 1050 for (off = 0; off < 256; off += 4) 1051 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1052 1053 /* common header */ 1054 printf(" Common header:\n"); 1055 pci_conf_print_regs(regs, 0, 16); 1056 1057 printf("\n"); 1058 pci_conf_print_common(pc, tag, regs); 1059 printf("\n"); 1060 1061 /* type-dependent header */ 1062 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1063 switch (hdrtype) { /* XXX make a table, eventually */ 1064 case 0: 1065 /* Standard device header */ 1066 typename = "\"normal\" device"; 1067 typeprintfn = &pci_conf_print_type0; 1068 endoff = 64; 1069 break; 1070 case 1: 1071 /* PCI-PCI bridge header */ 1072 typename = "PCI-PCI bridge"; 1073 typeprintfn = &pci_conf_print_type1; 1074 endoff = 64; 1075 break; 1076 case 2: 1077 /* PCI-CardBus bridge header */ 1078 typename = "PCI-CardBus bridge"; 1079 typeprintfn = &pci_conf_print_type2; 1080 endoff = 72; 1081 break; 1082 default: 1083 typename = NULL; 1084 typeprintfn = 0; 1085 endoff = 64; 1086 break; 1087 } 1088 printf(" Type %d ", hdrtype); 1089 if (typename != NULL) 1090 printf("(%s) ", typename); 1091 printf("header:\n"); 1092 pci_conf_print_regs(regs, 16, endoff); 1093 printf("\n"); 1094 if (typeprintfn) 1095 (*typeprintfn)(pc, tag, regs); 1096 else 1097 printf(" Don't know how to pretty-print type %d header.\n", 1098 hdrtype); 1099 printf("\n"); 1100 1101 /* device-dependent header */ 1102 printf(" Device-dependent header:\n"); 1103 pci_conf_print_regs(regs, endoff, 256); 1104 printf("\n"); 1105 if (printfn) 1106 (*printfn)(pc, tag, regs); 1107 else 1108 printf(" Don't know how to pretty-print device-dependent header.\n"); 1109 printf("\n"); 1110 } 1111
Indexes created Tue Sep 30 11:09:46 GMT 2025