pci_subr.c revision 1.38
1 /* $NetBSD: pci_subr.c,v 1.38 2000/09/02 00:48:20 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 */ 38 39 #include "opt_pci.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 45 #include <machine/intr.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #ifdef PCIVERBOSE 50 #include <dev/pci/pcidevs.h> 51 #endif 52 53 static void pci_conf_print_common __P((pci_chipset_tag_t, pcitag_t, 54 const pcireg_t *regs)); 55 static int pci_conf_print_bar __P((pci_chipset_tag_t, pcitag_t, 56 const pcireg_t *regs, int, const char *, int)); 57 static void pci_conf_print_regs __P((const pcireg_t *regs, int first, 58 int pastlast)); 59 static void pci_conf_print_type0 __P((pci_chipset_tag_t, pcitag_t, 60 const pcireg_t *regs, int sizebars)); 61 static void pci_conf_print_type1 __P((pci_chipset_tag_t, pcitag_t, 62 const pcireg_t *regs, int sizebars)); 63 static void pci_conf_print_type2 __P((pci_chipset_tag_t, pcitag_t, 64 const pcireg_t *regs, int sizebars)); 65 66 /* 67 * Descriptions of known PCI classes and subclasses. 68 * 69 * Subclasses are described in the same way as classes, but have a 70 * NULL subclass pointer. 71 */ 72 struct pci_class { 73 char *name; 74 int val; /* as wide as pci_{,sub}class_t */ 75 struct pci_class *subclasses; 76 }; 77 78 struct pci_class pci_subclass_prehistoric[] = { 79 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, }, 80 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, }, 81 { 0 } 82 }; 83 84 struct pci_class pci_subclass_mass_storage[] = { 85 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, }, 86 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, }, 87 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, }, 88 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, }, 89 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, }, 90 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, }, 91 { 0 }, 92 }; 93 94 struct pci_class pci_subclass_network[] = { 95 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, }, 96 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, }, 97 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, }, 98 { "ATM", PCI_SUBCLASS_NETWORK_ATM, }, 99 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, }, 100 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, }, 101 { 0 }, 102 }; 103 104 struct pci_class pci_subclass_display[] = { 105 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, }, 106 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, }, 107 { "3D", PCI_SUBCLASS_DISPLAY_3D, }, 108 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, }, 109 { 0 }, 110 }; 111 112 struct pci_class pci_subclass_multimedia[] = { 113 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, }, 114 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, }, 115 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, }, 116 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, }, 117 { 0 }, 118 }; 119 120 struct pci_class pci_subclass_memory[] = { 121 { "RAM", PCI_SUBCLASS_MEMORY_RAM, }, 122 { "flash", PCI_SUBCLASS_MEMORY_FLASH, }, 123 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, }, 124 { 0 }, 125 }; 126 127 struct pci_class pci_subclass_bridge[] = { 128 { "host", PCI_SUBCLASS_BRIDGE_HOST, }, 129 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, }, 130 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, }, 131 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, }, 132 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, }, 133 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, }, 134 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, }, 135 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, }, 136 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, }, 137 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, }, 138 { 0 }, 139 }; 140 141 struct pci_class pci_subclass_communications[] = { 142 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, }, 143 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, }, 144 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, }, 145 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, }, 146 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, }, 147 { 0 }, 148 }; 149 150 struct pci_class pci_subclass_system[] = { 151 { "8259 PIC", PCI_SUBCLASS_SYSTEM_PIC, }, 152 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, }, 153 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, }, 154 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, }, 155 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_RTC, }, 156 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, }, 157 { 0 }, 158 }; 159 160 struct pci_class pci_subclass_input[] = { 161 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, }, 162 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, }, 163 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, }, 164 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, }, 165 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, }, 166 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, }, 167 { 0 }, 168 }; 169 170 struct pci_class pci_subclass_dock[] = { 171 { "generic", PCI_SUBCLASS_DOCK_GENERIC, }, 172 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, }, 173 { 0 }, 174 }; 175 176 struct pci_class pci_subclass_processor[] = { 177 { "386", PCI_SUBCLASS_PROCESSOR_386, }, 178 { "486", PCI_SUBCLASS_PROCESSOR_486, }, 179 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, }, 180 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, }, 181 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, }, 182 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, }, 183 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, }, 184 { 0 }, 185 }; 186 187 struct pci_class pci_subclass_serialbus[] = { 188 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, }, 189 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, }, 190 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, }, 191 { "USB", PCI_SUBCLASS_SERIALBUS_USB, }, 192 /* XXX Fiber Channel/_FIBRECHANNEL */ 193 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, }, 194 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, }, 195 { 0 }, 196 }; 197 198 struct pci_class pci_subclass_wireless[] = { 199 { "iRDA", PCI_SUBCLASS_WIRELESS_IRDA, }, 200 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, }, 201 { "RF", PCI_SUBCLASS_WIRELESS_RF, }, 202 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, }, 203 { 0 }, 204 }; 205 206 struct pci_class pci_subclass_i2o[] = { 207 { "1.0", PCI_SUBCLASS_I2O_10, }, 208 { 0 }, 209 }; 210 211 struct pci_class pci_subclass_satcom[] = { 212 { "TV", PCI_SUBCLASS_SATCOM_TV, }, 213 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, }, 214 { "voice", PCI_SUBCLASS_SATCOM_VOICE, }, 215 { "data", PCI_SUBCLASS_SATCOM_DATA, }, 216 { 0 }, 217 }; 218 219 struct pci_class pci_subclass_crypto[] = { 220 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, }, 221 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, }, 222 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, }, 223 { 0 }, 224 }; 225 226 struct pci_class pci_subclass_dasp[] = { 227 { "DPIO", PCI_SUBCLASS_DASP_DPIO, }, 228 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, }, 229 { 0 }, 230 }; 231 232 struct pci_class pci_class[] = { 233 { "prehistoric", PCI_CLASS_PREHISTORIC, 234 pci_subclass_prehistoric, }, 235 { "mass storage", PCI_CLASS_MASS_STORAGE, 236 pci_subclass_mass_storage, }, 237 { "network", PCI_CLASS_NETWORK, 238 pci_subclass_network, }, 239 { "display", PCI_CLASS_DISPLAY, 240 pci_subclass_display, }, 241 { "multimedia", PCI_CLASS_MULTIMEDIA, 242 pci_subclass_multimedia, }, 243 { "memory", PCI_CLASS_MEMORY, 244 pci_subclass_memory, }, 245 { "bridge", PCI_CLASS_BRIDGE, 246 pci_subclass_bridge, }, 247 { "communications", PCI_CLASS_COMMUNICATIONS, 248 pci_subclass_communications, }, 249 { "system", PCI_CLASS_SYSTEM, 250 pci_subclass_system, }, 251 { "input", PCI_CLASS_INPUT, 252 pci_subclass_input, }, 253 { "dock", PCI_CLASS_DOCK, 254 pci_subclass_dock, }, 255 { "processor", PCI_CLASS_PROCESSOR, 256 pci_subclass_processor, }, 257 { "serial bus", PCI_CLASS_SERIALBUS, 258 pci_subclass_serialbus, }, 259 { "wireless", PCI_CLASS_WIRELESS, 260 pci_subclass_wireless, }, 261 { "I2O", PCI_CLASS_I2O, 262 pci_subclass_i2o, }, 263 { "satellite comm", PCI_CLASS_SATCOM, 264 pci_subclass_satcom, }, 265 { "crypto", PCI_CLASS_CRYPTO, 266 pci_subclass_crypto, }, 267 { "DASP", PCI_CLASS_DASP, 268 pci_subclass_dasp, }, 269 { "undefined", PCI_CLASS_UNDEFINED, 270 0, }, 271 { 0 }, 272 }; 273 274 #ifdef PCIVERBOSE 275 /* 276 * Descriptions of of known vendors and devices ("products"). 277 */ 278 struct pci_knowndev { 279 pci_vendor_id_t vendor; 280 pci_product_id_t product; 281 int flags; 282 char *vendorname, *productname; 283 }; 284 #define PCI_KNOWNDEV_NOPROD 0x01 /* match on vendor only */ 285 286 #include <dev/pci/pcidevs_data.h> 287 #endif /* PCIVERBOSE */ 288 289 char * 290 pci_findvendor(id_reg) 291 pcireg_t id_reg; 292 { 293 #ifdef PCIVERBOSE 294 pci_vendor_id_t vendor = PCI_VENDOR(id_reg); 295 struct pci_knowndev *kdp; 296 297 kdp = pci_knowndevs; 298 while (kdp->vendorname != NULL) { /* all have vendor name */ 299 if (kdp->vendor == vendor) 300 break; 301 kdp++; 302 } 303 return (kdp->vendorname); 304 #else 305 return (NULL); 306 #endif 307 } 308 309 void 310 pci_devinfo(id_reg, class_reg, showclass, cp) 311 pcireg_t id_reg, class_reg; 312 int showclass; 313 char *cp; 314 { 315 pci_vendor_id_t vendor; 316 pci_product_id_t product; 317 pci_class_t class; 318 pci_subclass_t subclass; 319 pci_interface_t interface; 320 pci_revision_t revision; 321 char *vendor_namep, *product_namep; 322 struct pci_class *classp, *subclassp; 323 #ifdef PCIVERBOSE 324 struct pci_knowndev *kdp; 325 const char *unmatched = "unknown "; 326 #else 327 const char *unmatched = ""; 328 #endif 329 330 vendor = PCI_VENDOR(id_reg); 331 product = PCI_PRODUCT(id_reg); 332 333 class = PCI_CLASS(class_reg); 334 subclass = PCI_SUBCLASS(class_reg); 335 interface = PCI_INTERFACE(class_reg); 336 revision = PCI_REVISION(class_reg); 337 338 #ifdef PCIVERBOSE 339 kdp = pci_knowndevs; 340 while (kdp->vendorname != NULL) { /* all have vendor name */ 341 if (kdp->vendor == vendor && (kdp->product == product || 342 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) 343 break; 344 kdp++; 345 } 346 if (kdp->vendorname == NULL) 347 vendor_namep = product_namep = NULL; 348 else { 349 vendor_namep = kdp->vendorname; 350 product_namep = (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0 ? 351 kdp->productname : NULL; 352 } 353 #else /* PCIVERBOSE */ 354 vendor_namep = product_namep = NULL; 355 #endif /* PCIVERBOSE */ 356 357 classp = pci_class; 358 while (classp->name != NULL) { 359 if (class == classp->val) 360 break; 361 classp++; 362 } 363 364 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 365 while (subclassp && subclassp->name != NULL) { 366 if (subclass == subclassp->val) 367 break; 368 subclassp++; 369 } 370 371 if (vendor_namep == NULL) 372 cp += sprintf(cp, "%svendor 0x%04x product 0x%04x", 373 unmatched, vendor, product); 374 else if (product_namep != NULL) 375 cp += sprintf(cp, "%s %s", vendor_namep, product_namep); 376 else 377 cp += sprintf(cp, "%s product 0x%04x", 378 vendor_namep, product); 379 if (showclass) { 380 cp += sprintf(cp, " ("); 381 if (classp->name == NULL) 382 cp += sprintf(cp, "class 0x%02x, subclass 0x%02x", 383 class, subclass); 384 else { 385 if (subclassp == NULL || subclassp->name == NULL) 386 cp += sprintf(cp, 387 "%s subclass 0x%02x", 388 classp->name, subclass); 389 else 390 cp += sprintf(cp, "%s %s", 391 subclassp->name, classp->name); 392 } 393 if (interface != 0) 394 cp += sprintf(cp, ", interface 0x%02x", interface); 395 if (revision != 0) 396 cp += sprintf(cp, ", revision 0x%02x", revision); 397 cp += sprintf(cp, ")"); 398 } 399 } 400 401 /* 402 * Print out most of the PCI configuration registers. Typically used 403 * in a device attach routine like this: 404 * 405 * #ifdef MYDEV_DEBUG 406 * printf("%s: ", sc->sc_dev.dv_xname); 407 * pci_conf_print(pa->pa_pc, pa->pa_tag); 408 * #endif 409 */ 410 411 #define i2o(i) ((i) * 4) 412 #define o2i(o) ((o) / 4) 413 #define onoff(str, bit) \ 414 printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off"); 415 416 static void 417 pci_conf_print_common(pc, tag, regs) 418 pci_chipset_tag_t pc; 419 pcitag_t tag; 420 const pcireg_t *regs; 421 { 422 #ifdef PCIVERBOSE 423 struct pci_knowndev *kdp; 424 #endif 425 struct pci_class *classp, *subclassp; 426 pcireg_t rval; 427 428 rval = regs[o2i(PCI_ID_REG)]; 429 #ifndef PCIVERBOSE 430 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 431 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 432 #else 433 for (kdp = pci_knowndevs; kdp->vendorname != NULL; kdp++) { 434 if (kdp->vendor == PCI_VENDOR(rval) && 435 (kdp->product == PCI_PRODUCT(rval) || 436 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) { 437 break; 438 } 439 } 440 if (kdp->vendorname != NULL) 441 printf(" Vendor Name: %s (0x%04x)\n", kdp->vendorname, 442 PCI_VENDOR(rval)); 443 else 444 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 445 if (kdp->productname != NULL && (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0) 446 printf(" Device Name: %s (0x%04x)\n", kdp->productname, 447 PCI_PRODUCT(rval)); 448 else 449 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 450 #endif /* PCIVERBOSE */ 451 452 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 453 454 printf(" Command register: 0x%04x\n", rval & 0xffff); 455 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 456 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 457 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 458 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 459 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 460 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 461 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 462 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 463 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 464 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 465 466 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 467 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 468 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 469 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 470 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 471 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 472 473 printf(" DEVSEL timing: "); 474 switch (rval & PCI_STATUS_DEVSEL_MASK) { 475 case PCI_STATUS_DEVSEL_FAST: 476 printf("fast"); 477 break; 478 case PCI_STATUS_DEVSEL_MEDIUM: 479 printf("medium"); 480 break; 481 case PCI_STATUS_DEVSEL_SLOW: 482 printf("slow"); 483 break; 484 default: 485 printf("unknown/reserved"); /* XXX */ 486 break; 487 } 488 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 489 490 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 491 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 492 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 493 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 494 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 495 496 rval = regs[o2i(PCI_CLASS_REG)]; 497 for (classp = pci_class; classp->name != NULL; classp++) { 498 if (PCI_CLASS(rval) == classp->val) 499 break; 500 } 501 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 502 while (subclassp && subclassp->name != NULL) { 503 if (PCI_SUBCLASS(rval) == subclassp->val) 504 break; 505 subclassp++; 506 } 507 if (classp->name != NULL) { 508 printf(" Class Name: %s (0x%02x)\n", classp->name, 509 PCI_CLASS(rval)); 510 if (subclassp != NULL && subclassp->name != NULL) 511 printf(" Subclass Name: %s (0x%02x)\n", 512 subclassp->name, PCI_SUBCLASS(rval)); 513 else 514 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 515 } else { 516 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 517 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 518 } 519 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 520 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 521 522 rval = regs[o2i(PCI_BHLC_REG)]; 523 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 524 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 525 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 526 PCI_HDRTYPE(rval)); 527 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 528 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 529 } 530 531 static int 532 pci_conf_print_bar(pc, tag, regs, reg, name, sizebar) 533 pci_chipset_tag_t pc; 534 pcitag_t tag; 535 const pcireg_t *regs; 536 int reg; 537 const char *name; 538 int sizebar; 539 { 540 int s, width; 541 pcireg_t mask, rval; 542 pcireg_t mask64h, rval64h; 543 544 width = 4; 545 546 /* 547 * Section 6.2.5.1, `Address Maps', tells us that: 548 * 549 * 1) The builtin software should have already mapped the 550 * device in a reasonable way. 551 * 552 * 2) A device which wants 2^n bytes of memory will hardwire 553 * the bottom n bits of the address to 0. As recommended, 554 * we write all 1s and see what we get back. 555 */ 556 rval = regs[o2i(reg)]; 557 /* XXX don't size unknown memory type? */ 558 if (rval != 0 && sizebar) { 559 /* 560 * The following sequence seems to make some devices 561 * (e.g. host bus bridges, which don't normally 562 * have their space mapped) very unhappy, to 563 * the point of crashing the system. 564 * 565 * Therefore, if the mapping register is zero to 566 * start out with, don't bother trying. 567 */ 568 s = splhigh(); 569 pci_conf_write(pc, tag, reg, 0xffffffff); 570 mask = pci_conf_read(pc, tag, reg); 571 pci_conf_write(pc, tag, reg, rval); 572 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 573 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 574 rval64h = regs[o2i(reg + 4)]; 575 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 576 mask64h = pci_conf_read(pc, tag, reg + 4); 577 pci_conf_write(pc, tag, reg + 4, rval64h); 578 width = 8; 579 } 580 splx(s); 581 } else 582 mask = 0; 583 584 printf(" Base address register at 0x%02x", reg); 585 if (name) 586 printf(" (%s)", name); 587 printf("\n "); 588 if (rval == 0) { 589 printf("not implemented(?)\n"); 590 return width; 591 } 592 printf("type: "); 593 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 594 const char *type, *prefetch; 595 596 switch (PCI_MAPREG_MEM_TYPE(rval)) { 597 case PCI_MAPREG_MEM_TYPE_32BIT: 598 type = "32-bit"; 599 break; 600 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 601 type = "32-bit-1M"; 602 break; 603 case PCI_MAPREG_MEM_TYPE_64BIT: 604 type = "64-bit"; 605 break; 606 default: 607 type = "unknown (XXX)"; 608 break; 609 } 610 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 611 prefetch = ""; 612 else 613 prefetch = "non"; 614 printf("%s %sprefetchable memory\n", type, prefetch); 615 switch (PCI_MAPREG_MEM_TYPE(rval)) { 616 case PCI_MAPREG_MEM_TYPE_64BIT: 617 printf(" base: 0x%016llx, ", 618 PCI_MAPREG_MEM64_ADDR( 619 ((((long long) rval64h) << 32) | rval))); 620 if (sizebar) 621 printf("size: 0x%016llx", 622 PCI_MAPREG_MEM64_SIZE( 623 ((((long long) mask64h) << 32) | mask))); 624 else 625 printf("not sized"); 626 printf("\n"); 627 break; 628 case PCI_MAPREG_MEM_TYPE_32BIT: 629 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 630 default: 631 printf(" base: 0x%08x, ", 632 PCI_MAPREG_MEM_ADDR(rval)); 633 if (sizebar) 634 printf("size: 0x%08x", 635 PCI_MAPREG_MEM_SIZE(mask)); 636 else 637 printf("not sized"); 638 printf("\n"); 639 break; 640 } 641 } else { 642 if (sizebar) 643 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 644 printf("i/o\n"); 645 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 646 if (sizebar) 647 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 648 else 649 printf("not sized"); 650 printf("\n"); 651 } 652 653 return width; 654 } 655 656 static void 657 pci_conf_print_regs(regs, first, pastlast) 658 const pcireg_t *regs; 659 int first, pastlast; 660 { 661 int off, needaddr, neednl; 662 663 needaddr = 1; 664 neednl = 0; 665 for (off = first; off < pastlast; off += 4) { 666 if ((off % 16) == 0 || needaddr) { 667 printf(" 0x%02x:", off); 668 needaddr = 0; 669 } 670 printf(" 0x%08x", regs[o2i(off)]); 671 neednl = 1; 672 if ((off % 16) == 12) { 673 printf("\n"); 674 neednl = 0; 675 } 676 } 677 if (neednl) 678 printf("\n"); 679 } 680 681 static void 682 pci_conf_print_type0(pc, tag, regs, sizebars) 683 pci_chipset_tag_t pc; 684 pcitag_t tag; 685 const pcireg_t *regs; 686 int sizebars; 687 { 688 int off, width; 689 pcireg_t rval; 690 691 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) 692 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 693 694 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 695 696 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 697 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 698 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 699 700 /* XXX */ 701 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 702 703 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 704 printf(" Capability list pointer: 0x%02x\n", 705 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 706 else 707 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 708 709 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 710 711 rval = regs[o2i(PCI_INTERRUPT_REG)]; 712 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 713 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 714 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 715 switch (PCI_INTERRUPT_PIN(rval)) { 716 case PCI_INTERRUPT_PIN_NONE: 717 printf("(none)"); 718 break; 719 case PCI_INTERRUPT_PIN_A: 720 printf("(pin A)"); 721 break; 722 case PCI_INTERRUPT_PIN_B: 723 printf("(pin B)"); 724 break; 725 case PCI_INTERRUPT_PIN_C: 726 printf("(pin C)"); 727 break; 728 case PCI_INTERRUPT_PIN_D: 729 printf("(pin D)"); 730 break; 731 default: 732 printf("(? ? ?)"); 733 break; 734 } 735 printf("\n"); 736 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 737 738 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) { 739 for (off = PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]); 740 off != 0; 741 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 742 rval = regs[o2i(off)]; 743 printf(" Capability register at 0x%02x\n", off); 744 745 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 746 switch (PCI_CAPLIST_CAP(rval)) { 747 case PCI_CAP_PWRMGMT: 748 printf("Power Management, rev. %d.0", 749 (rval >> 0) & 0x07); /* XXX not clear */ 750 break; 751 case PCI_CAP_AGP: 752 printf("AGP, rev. %d.%d", 753 (rval >> 24) & 0x0f, 754 (rval >> 20) & 0x0f); 755 break; 756 case PCI_CAP_VPD: 757 printf("VPD"); 758 break; 759 case PCI_CAP_SLOTID: 760 printf("SlotID"); 761 break; 762 case PCI_CAP_MBI: 763 printf("MBI"); 764 break; 765 case PCI_CAP_HOTSWAP: 766 printf("Hot-swapping"); 767 break; 768 default: 769 printf("unknown/reserved"); 770 } 771 printf(")\n"); 772 } 773 } 774 } 775 776 static void 777 pci_conf_print_type1(pc, tag, regs, sizebars) 778 pci_chipset_tag_t pc; 779 pcitag_t tag; 780 const pcireg_t *regs; 781 int sizebars; 782 { 783 int off, width; 784 pcireg_t rval; 785 786 /* 787 * XXX these need to be printed in more detail, need to be 788 * XXX checked against specs/docs, etc. 789 * 790 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 791 * Bridge chip documentation, and may not be correct with 792 * respect to various standards. (XXX) 793 */ 794 795 for (off = 0x10; off < 0x18; off += width) 796 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 797 798 printf(" Primary bus number: 0x%02x\n", 799 (regs[o2i(0x18)] >> 0) & 0xff); 800 printf(" Secondary bus number: 0x%02x\n", 801 (regs[o2i(0x18)] >> 8) & 0xff); 802 printf(" Subordinate bus number: 0x%02x\n", 803 (regs[o2i(0x18)] >> 16) & 0xff); 804 printf(" Secondary bus latency timer: 0x%02x\n", 805 (regs[o2i(0x18)] >> 24) & 0xff); 806 807 rval = (regs[o2i(0x1c)] >> 16) & 0xffff; 808 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 809 onoff("66 MHz capable", 0x0020); 810 onoff("User Definable Features (UDF) support", 0x0040); 811 onoff("Fast back-to-back capable", 0x0080); 812 onoff("Data parity error detected", 0x0100); 813 814 printf(" DEVSEL timing: "); 815 switch (rval & 0x0600) { 816 case 0x0000: 817 printf("fast"); 818 break; 819 case 0x0200: 820 printf("medium"); 821 break; 822 case 0x0400: 823 printf("slow"); 824 break; 825 default: 826 printf("unknown/reserved"); /* XXX */ 827 break; 828 } 829 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 830 831 onoff("Signaled Target Abort", 0x0800); 832 onoff("Received Target Abort", 0x1000); 833 onoff("Received Master Abort", 0x2000); 834 onoff("System Error", 0x4000); 835 onoff("Parity Error", 0x8000); 836 837 /* XXX Print more prettily */ 838 printf(" I/O region:\n"); 839 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 840 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 841 printf(" base upper 16 bits register: 0x%04x\n", 842 (regs[o2i(0x30)] >> 0) & 0xffff); 843 printf(" limit upper 16 bits register: 0x%04x\n", 844 (regs[o2i(0x30)] >> 16) & 0xffff); 845 846 /* XXX Print more prettily */ 847 printf(" Memory region:\n"); 848 printf(" base register: 0x%04x\n", 849 (regs[o2i(0x20)] >> 0) & 0xffff); 850 printf(" limit register: 0x%04x\n", 851 (regs[o2i(0x20)] >> 16) & 0xffff); 852 853 /* XXX Print more prettily */ 854 printf(" Prefetchable memory region:\n"); 855 printf(" base register: 0x%04x\n", 856 (regs[o2i(0x24)] >> 0) & 0xffff); 857 printf(" limit register: 0x%04x\n", 858 (regs[o2i(0x24)] >> 16) & 0xffff); 859 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 860 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 861 862 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 863 /* XXX */ 864 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 865 866 printf(" Interrupt line: 0x%02x\n", 867 (regs[o2i(0x3c)] >> 0) & 0xff); 868 printf(" Interrupt pin: 0x%02x ", 869 (regs[o2i(0x3c)] >> 8) & 0xff); 870 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 871 case PCI_INTERRUPT_PIN_NONE: 872 printf("(none)"); 873 break; 874 case PCI_INTERRUPT_PIN_A: 875 printf("(pin A)"); 876 break; 877 case PCI_INTERRUPT_PIN_B: 878 printf("(pin B)"); 879 break; 880 case PCI_INTERRUPT_PIN_C: 881 printf("(pin C)"); 882 break; 883 case PCI_INTERRUPT_PIN_D: 884 printf("(pin D)"); 885 break; 886 default: 887 printf("(? ? ?)"); 888 break; 889 } 890 printf("\n"); 891 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 892 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 893 onoff("Parity error response", 0x0001); 894 onoff("Secondary SERR forwarding", 0x0002); 895 onoff("ISA enable", 0x0004); 896 onoff("VGA enable", 0x0008); 897 onoff("Master abort reporting", 0x0020); 898 onoff("Secondary bus reset", 0x0040); 899 onoff("Fast back-to-back capable", 0x0080); 900 } 901 902 static void 903 pci_conf_print_type2(pc, tag, regs, sizebars) 904 pci_chipset_tag_t pc; 905 pcitag_t tag; 906 const pcireg_t *regs; 907 int sizebars; 908 { 909 pcireg_t rval; 910 911 /* 912 * XXX these need to be printed in more detail, need to be 913 * XXX checked against specs/docs, etc. 914 * 915 * This layout was cribbed from the TI PCI1130 PCI-to-CardBus 916 * controller chip documentation, and may not be correct with 917 * respect to various standards. (XXX) 918 */ 919 920 pci_conf_print_bar(pc, tag, regs, 0x10, 921 "CardBus socket/ExCA registers", sizebars); 922 923 printf(" Reserved @ 0x14: 0x%04x\n", 924 (regs[o2i(0x14)] >> 0) & 0xffff); 925 rval = (regs[o2i(0x14)] >> 16) & 0xffff; 926 printf(" Secondary status register: 0x%04x\n", rval); 927 onoff("66 MHz capable", 0x0020); 928 onoff("User Definable Features (UDF) support", 0x0040); 929 onoff("Fast back-to-back capable", 0x0080); 930 onoff("Data parity error detection", 0x0100); 931 932 printf(" DEVSEL timing: "); 933 switch (rval & 0x0600) { 934 case 0x0000: 935 printf("fast"); 936 break; 937 case 0x0200: 938 printf("medium"); 939 break; 940 case 0x0400: 941 printf("slow"); 942 break; 943 default: 944 printf("unknown/reserved"); /* XXX */ 945 break; 946 } 947 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 948 onoff("PCI target aborts terminate CardBus bus master transactions", 949 0x0800); 950 onoff("CardBus target aborts terminate PCI bus master transactions", 951 0x1000); 952 onoff("Bus initiator aborts terminate initiator transactions", 953 0x2000); 954 onoff("System error", 0x4000); 955 onoff("Parity error", 0x8000); 956 957 printf(" PCI bus number: 0x%02x\n", 958 (regs[o2i(0x18)] >> 0) & 0xff); 959 printf(" CardBus bus number: 0x%02x\n", 960 (regs[o2i(0x18)] >> 8) & 0xff); 961 printf(" Subordinate bus number: 0x%02x\n", 962 (regs[o2i(0x18)] >> 16) & 0xff); 963 printf(" CardBus latency timer: 0x%02x\n", 964 (regs[o2i(0x18)] >> 24) & 0xff); 965 966 /* XXX Print more prettily */ 967 printf(" CardBus memory region 0:\n"); 968 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 969 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 970 printf(" CardBus memory region 1:\n"); 971 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 972 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 973 printf(" CardBus I/O region 0:\n"); 974 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 975 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 976 printf(" CardBus I/O region 1:\n"); 977 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 978 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 979 980 printf(" Interrupt line: 0x%02x\n", 981 (regs[o2i(0x3c)] >> 0) & 0xff); 982 printf(" Interrupt pin: 0x%02x ", 983 (regs[o2i(0x3c)] >> 8) & 0xff); 984 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 985 case PCI_INTERRUPT_PIN_NONE: 986 printf("(none)"); 987 break; 988 case PCI_INTERRUPT_PIN_A: 989 printf("(pin A)"); 990 break; 991 case PCI_INTERRUPT_PIN_B: 992 printf("(pin B)"); 993 break; 994 case PCI_INTERRUPT_PIN_C: 995 printf("(pin C)"); 996 break; 997 case PCI_INTERRUPT_PIN_D: 998 printf("(pin D)"); 999 break; 1000 default: 1001 printf("(? ? ?)"); 1002 break; 1003 } 1004 printf("\n"); 1005 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1006 printf(" Bridge control register: 0x%04x\n", rval); 1007 onoff("Parity error response", 0x0001); 1008 onoff("CardBus SERR forwarding", 0x0002); 1009 onoff("ISA enable", 0x0004); 1010 onoff("VGA enable", 0x0008); 1011 onoff("CardBus master abort reporting", 0x0020); 1012 onoff("CardBus reset", 0x0040); 1013 onoff("Functional interrupts routed by ExCA registers", 0x0080); 1014 onoff("Memory window 0 prefetchable", 0x0100); 1015 onoff("Memory window 1 prefetchable", 0x0200); 1016 onoff("Write posting enable", 0x0400); 1017 1018 rval = regs[o2i(0x40)]; 1019 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1020 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1021 1022 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1023 sizebars); 1024 } 1025 1026 void 1027 pci_conf_print(pc, tag, printfn) 1028 pci_chipset_tag_t pc; 1029 pcitag_t tag; 1030 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 1031 { 1032 pcireg_t regs[o2i(256)]; 1033 int off, endoff, hdrtype; 1034 const char *typename; 1035 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1036 int sizebars; 1037 1038 printf("PCI configuration registers:\n"); 1039 1040 for (off = 0; off < 256; off += 4) 1041 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1042 1043 sizebars = 1; 1044 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1045 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1046 sizebars = 0; 1047 1048 /* common header */ 1049 printf(" Common header:\n"); 1050 pci_conf_print_regs(regs, 0, 16); 1051 1052 printf("\n"); 1053 pci_conf_print_common(pc, tag, regs); 1054 printf("\n"); 1055 1056 /* type-dependent header */ 1057 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1058 switch (hdrtype) { /* XXX make a table, eventually */ 1059 case 0: 1060 /* Standard device header */ 1061 typename = "\"normal\" device"; 1062 typeprintfn = &pci_conf_print_type0; 1063 endoff = 64; 1064 break; 1065 case 1: 1066 /* PCI-PCI bridge header */ 1067 typename = "PCI-PCI bridge"; 1068 typeprintfn = &pci_conf_print_type1; 1069 endoff = 64; 1070 break; 1071 case 2: 1072 /* PCI-CardBus bridge header */ 1073 typename = "PCI-CardBus bridge"; 1074 typeprintfn = &pci_conf_print_type2; 1075 endoff = 72; 1076 break; 1077 default: 1078 typename = NULL; 1079 typeprintfn = 0; 1080 endoff = 64; 1081 break; 1082 } 1083 printf(" Type %d ", hdrtype); 1084 if (typename != NULL) 1085 printf("(%s) ", typename); 1086 printf("header:\n"); 1087 pci_conf_print_regs(regs, 16, endoff); 1088 printf("\n"); 1089 if (typeprintfn) 1090 (*typeprintfn)(pc, tag, regs, sizebars); 1091 else 1092 printf(" Don't know how to pretty-print type %d header.\n", 1093 hdrtype); 1094 printf("\n"); 1095 1096 /* device-dependent header */ 1097 printf(" Device-dependent header:\n"); 1098 pci_conf_print_regs(regs, endoff, 256); 1099 printf("\n"); 1100 if (printfn) 1101 (*printfn)(pc, tag, regs); 1102 else 1103 printf(" Don't know how to pretty-print device-dependent header.\n"); 1104 printf("\n"); 1105 } 1106
Indexes created Thu Sep 25 16:09:42 GMT 2025