pci_subr.c revision 1.40
1 /* $NetBSD: pci_subr.c,v 1.40 2000/10/07 18:58:13 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 */ 38 39 #include "opt_pci.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 45 #include <machine/intr.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #ifdef PCIVERBOSE 50 #include <dev/pci/pcidevs.h> 51 #endif 52 53 static void pci_conf_print_common __P((pci_chipset_tag_t, pcitag_t, 54 const pcireg_t *regs)); 55 static int pci_conf_print_bar __P((pci_chipset_tag_t, pcitag_t, 56 const pcireg_t *regs, int, const char *, int)); 57 static void pci_conf_print_regs __P((const pcireg_t *regs, int first, 58 int pastlast)); 59 static void pci_conf_print_type0 __P((pci_chipset_tag_t, pcitag_t, 60 const pcireg_t *regs, int sizebars)); 61 static void pci_conf_print_type1 __P((pci_chipset_tag_t, pcitag_t, 62 const pcireg_t *regs, int sizebars)); 63 static void pci_conf_print_type2 __P((pci_chipset_tag_t, pcitag_t, 64 const pcireg_t *regs, int sizebars)); 65 66 /* 67 * Descriptions of known PCI classes and subclasses. 68 * 69 * Subclasses are described in the same way as classes, but have a 70 * NULL subclass pointer. 71 */ 72 struct pci_class { 73 char *name; 74 int val; /* as wide as pci_{,sub}class_t */ 75 struct pci_class *subclasses; 76 }; 77 78 struct pci_class pci_subclass_prehistoric[] = { 79 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, }, 80 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, }, 81 { 0 } 82 }; 83 84 struct pci_class pci_subclass_mass_storage[] = { 85 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, }, 86 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, }, 87 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, }, 88 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, }, 89 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, }, 90 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, }, 91 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, }, 92 { 0 }, 93 }; 94 95 struct pci_class pci_subclass_network[] = { 96 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, }, 97 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, }, 98 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, }, 99 { "ATM", PCI_SUBCLASS_NETWORK_ATM, }, 100 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, }, 101 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, }, 102 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, }, 103 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, }, 104 { 0 }, 105 }; 106 107 struct pci_class pci_subclass_display[] = { 108 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, }, 109 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, }, 110 { "3D", PCI_SUBCLASS_DISPLAY_3D, }, 111 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, }, 112 { 0 }, 113 }; 114 115 struct pci_class pci_subclass_multimedia[] = { 116 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, }, 117 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, }, 118 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, }, 119 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, }, 120 { 0 }, 121 }; 122 123 struct pci_class pci_subclass_memory[] = { 124 { "RAM", PCI_SUBCLASS_MEMORY_RAM, }, 125 { "flash", PCI_SUBCLASS_MEMORY_FLASH, }, 126 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, }, 127 { 0 }, 128 }; 129 130 struct pci_class pci_subclass_bridge[] = { 131 { "host", PCI_SUBCLASS_BRIDGE_HOST, }, 132 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, }, 133 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, }, 134 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, }, 135 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, }, 136 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, }, 137 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, }, 138 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, }, 139 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, }, 140 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, }, 141 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, }, 142 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, }, 143 { 0 }, 144 }; 145 146 struct pci_class pci_subclass_communications[] = { 147 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, }, 148 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, }, 149 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, }, 150 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, }, 151 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, }, 152 { 0 }, 153 }; 154 155 struct pci_class pci_subclass_system[] = { 156 { "8259 PIC", PCI_SUBCLASS_SYSTEM_PIC, }, 157 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, }, 158 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, }, 159 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, }, 160 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_RTC, }, 161 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, }, 162 { 0 }, 163 }; 164 165 struct pci_class pci_subclass_input[] = { 166 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, }, 167 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, }, 168 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, }, 169 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, }, 170 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, }, 171 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, }, 172 { 0 }, 173 }; 174 175 struct pci_class pci_subclass_dock[] = { 176 { "generic", PCI_SUBCLASS_DOCK_GENERIC, }, 177 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, }, 178 { 0 }, 179 }; 180 181 struct pci_class pci_subclass_processor[] = { 182 { "386", PCI_SUBCLASS_PROCESSOR_386, }, 183 { "486", PCI_SUBCLASS_PROCESSOR_486, }, 184 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, }, 185 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, }, 186 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, }, 187 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, }, 188 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, }, 189 { 0 }, 190 }; 191 192 struct pci_class pci_subclass_serialbus[] = { 193 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, }, 194 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, }, 195 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, }, 196 { "USB", PCI_SUBCLASS_SERIALBUS_USB, }, 197 /* XXX Fiber Channel/_FIBRECHANNEL */ 198 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, }, 199 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, }, 200 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, }, 201 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, }, 202 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, }, 203 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, }, 204 { 0 }, 205 }; 206 207 struct pci_class pci_subclass_wireless[] = { 208 { "iRDA", PCI_SUBCLASS_WIRELESS_IRDA, }, 209 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, }, 210 { "RF", PCI_SUBCLASS_WIRELESS_RF, }, 211 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, }, 212 { 0 }, 213 }; 214 215 struct pci_class pci_subclass_i2o[] = { 216 { "standard", PCI_SUBCLASS_I2O_STANDARD, }, 217 { 0 }, 218 }; 219 220 struct pci_class pci_subclass_satcom[] = { 221 { "TV", PCI_SUBCLASS_SATCOM_TV, }, 222 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, }, 223 { "voice", PCI_SUBCLASS_SATCOM_VOICE, }, 224 { "data", PCI_SUBCLASS_SATCOM_DATA, }, 225 { 0 }, 226 }; 227 228 struct pci_class pci_subclass_crypto[] = { 229 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, }, 230 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, }, 231 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, }, 232 { 0 }, 233 }; 234 235 struct pci_class pci_subclass_dasp[] = { 236 { "DPIO", PCI_SUBCLASS_DASP_DPIO, }, 237 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, }, 238 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, }, 239 { 0 }, 240 }; 241 242 struct pci_class pci_class[] = { 243 { "prehistoric", PCI_CLASS_PREHISTORIC, 244 pci_subclass_prehistoric, }, 245 { "mass storage", PCI_CLASS_MASS_STORAGE, 246 pci_subclass_mass_storage, }, 247 { "network", PCI_CLASS_NETWORK, 248 pci_subclass_network, }, 249 { "display", PCI_CLASS_DISPLAY, 250 pci_subclass_display, }, 251 { "multimedia", PCI_CLASS_MULTIMEDIA, 252 pci_subclass_multimedia, }, 253 { "memory", PCI_CLASS_MEMORY, 254 pci_subclass_memory, }, 255 { "bridge", PCI_CLASS_BRIDGE, 256 pci_subclass_bridge, }, 257 { "communications", PCI_CLASS_COMMUNICATIONS, 258 pci_subclass_communications, }, 259 { "system", PCI_CLASS_SYSTEM, 260 pci_subclass_system, }, 261 { "input", PCI_CLASS_INPUT, 262 pci_subclass_input, }, 263 { "dock", PCI_CLASS_DOCK, 264 pci_subclass_dock, }, 265 { "processor", PCI_CLASS_PROCESSOR, 266 pci_subclass_processor, }, 267 { "serial bus", PCI_CLASS_SERIALBUS, 268 pci_subclass_serialbus, }, 269 { "wireless", PCI_CLASS_WIRELESS, 270 pci_subclass_wireless, }, 271 { "I2O", PCI_CLASS_I2O, 272 pci_subclass_i2o, }, 273 { "satellite comm", PCI_CLASS_SATCOM, 274 pci_subclass_satcom, }, 275 { "crypto", PCI_CLASS_CRYPTO, 276 pci_subclass_crypto, }, 277 { "DASP", PCI_CLASS_DASP, 278 pci_subclass_dasp, }, 279 { "undefined", PCI_CLASS_UNDEFINED, 280 0, }, 281 { 0 }, 282 }; 283 284 #ifdef PCIVERBOSE 285 /* 286 * Descriptions of of known vendors and devices ("products"). 287 */ 288 struct pci_knowndev { 289 pci_vendor_id_t vendor; 290 pci_product_id_t product; 291 int flags; 292 char *vendorname, *productname; 293 }; 294 #define PCI_KNOWNDEV_NOPROD 0x01 /* match on vendor only */ 295 296 #include <dev/pci/pcidevs_data.h> 297 #endif /* PCIVERBOSE */ 298 299 char * 300 pci_findvendor(id_reg) 301 pcireg_t id_reg; 302 { 303 #ifdef PCIVERBOSE 304 pci_vendor_id_t vendor = PCI_VENDOR(id_reg); 305 struct pci_knowndev *kdp; 306 307 kdp = pci_knowndevs; 308 while (kdp->vendorname != NULL) { /* all have vendor name */ 309 if (kdp->vendor == vendor) 310 break; 311 kdp++; 312 } 313 return (kdp->vendorname); 314 #else 315 return (NULL); 316 #endif 317 } 318 319 void 320 pci_devinfo(id_reg, class_reg, showclass, cp) 321 pcireg_t id_reg, class_reg; 322 int showclass; 323 char *cp; 324 { 325 pci_vendor_id_t vendor; 326 pci_product_id_t product; 327 pci_class_t class; 328 pci_subclass_t subclass; 329 pci_interface_t interface; 330 pci_revision_t revision; 331 char *vendor_namep, *product_namep; 332 struct pci_class *classp, *subclassp; 333 #ifdef PCIVERBOSE 334 struct pci_knowndev *kdp; 335 const char *unmatched = "unknown "; 336 #else 337 const char *unmatched = ""; 338 #endif 339 340 vendor = PCI_VENDOR(id_reg); 341 product = PCI_PRODUCT(id_reg); 342 343 class = PCI_CLASS(class_reg); 344 subclass = PCI_SUBCLASS(class_reg); 345 interface = PCI_INTERFACE(class_reg); 346 revision = PCI_REVISION(class_reg); 347 348 #ifdef PCIVERBOSE 349 kdp = pci_knowndevs; 350 while (kdp->vendorname != NULL) { /* all have vendor name */ 351 if (kdp->vendor == vendor && (kdp->product == product || 352 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) 353 break; 354 kdp++; 355 } 356 if (kdp->vendorname == NULL) 357 vendor_namep = product_namep = NULL; 358 else { 359 vendor_namep = kdp->vendorname; 360 product_namep = (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0 ? 361 kdp->productname : NULL; 362 } 363 #else /* PCIVERBOSE */ 364 vendor_namep = product_namep = NULL; 365 #endif /* PCIVERBOSE */ 366 367 classp = pci_class; 368 while (classp->name != NULL) { 369 if (class == classp->val) 370 break; 371 classp++; 372 } 373 374 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 375 while (subclassp && subclassp->name != NULL) { 376 if (subclass == subclassp->val) 377 break; 378 subclassp++; 379 } 380 381 if (vendor_namep == NULL) 382 cp += sprintf(cp, "%svendor 0x%04x product 0x%04x", 383 unmatched, vendor, product); 384 else if (product_namep != NULL) 385 cp += sprintf(cp, "%s %s", vendor_namep, product_namep); 386 else 387 cp += sprintf(cp, "%s product 0x%04x", 388 vendor_namep, product); 389 if (showclass) { 390 cp += sprintf(cp, " ("); 391 if (classp->name == NULL) 392 cp += sprintf(cp, "class 0x%02x, subclass 0x%02x", 393 class, subclass); 394 else { 395 if (subclassp == NULL || subclassp->name == NULL) 396 cp += sprintf(cp, 397 "%s subclass 0x%02x", 398 classp->name, subclass); 399 else 400 cp += sprintf(cp, "%s %s", 401 subclassp->name, classp->name); 402 } 403 if (interface != 0) 404 cp += sprintf(cp, ", interface 0x%02x", interface); 405 if (revision != 0) 406 cp += sprintf(cp, ", revision 0x%02x", revision); 407 cp += sprintf(cp, ")"); 408 } 409 } 410 411 /* 412 * Print out most of the PCI configuration registers. Typically used 413 * in a device attach routine like this: 414 * 415 * #ifdef MYDEV_DEBUG 416 * printf("%s: ", sc->sc_dev.dv_xname); 417 * pci_conf_print(pa->pa_pc, pa->pa_tag); 418 * #endif 419 */ 420 421 #define i2o(i) ((i) * 4) 422 #define o2i(o) ((o) / 4) 423 #define onoff(str, bit) \ 424 printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off"); 425 426 static void 427 pci_conf_print_common(pc, tag, regs) 428 pci_chipset_tag_t pc; 429 pcitag_t tag; 430 const pcireg_t *regs; 431 { 432 #ifdef PCIVERBOSE 433 struct pci_knowndev *kdp; 434 #endif 435 struct pci_class *classp, *subclassp; 436 pcireg_t rval; 437 438 rval = regs[o2i(PCI_ID_REG)]; 439 #ifndef PCIVERBOSE 440 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 441 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 442 #else 443 for (kdp = pci_knowndevs; kdp->vendorname != NULL; kdp++) { 444 if (kdp->vendor == PCI_VENDOR(rval) && 445 (kdp->product == PCI_PRODUCT(rval) || 446 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) { 447 break; 448 } 449 } 450 if (kdp->vendorname != NULL) 451 printf(" Vendor Name: %s (0x%04x)\n", kdp->vendorname, 452 PCI_VENDOR(rval)); 453 else 454 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 455 if (kdp->productname != NULL && (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0) 456 printf(" Device Name: %s (0x%04x)\n", kdp->productname, 457 PCI_PRODUCT(rval)); 458 else 459 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 460 #endif /* PCIVERBOSE */ 461 462 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 463 464 printf(" Command register: 0x%04x\n", rval & 0xffff); 465 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 466 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 467 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 468 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 469 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 470 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 471 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 472 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 473 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 474 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 475 476 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 477 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 478 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 479 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 480 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 481 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 482 483 printf(" DEVSEL timing: "); 484 switch (rval & PCI_STATUS_DEVSEL_MASK) { 485 case PCI_STATUS_DEVSEL_FAST: 486 printf("fast"); 487 break; 488 case PCI_STATUS_DEVSEL_MEDIUM: 489 printf("medium"); 490 break; 491 case PCI_STATUS_DEVSEL_SLOW: 492 printf("slow"); 493 break; 494 default: 495 printf("unknown/reserved"); /* XXX */ 496 break; 497 } 498 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 499 500 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 501 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 502 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 503 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 504 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 505 506 rval = regs[o2i(PCI_CLASS_REG)]; 507 for (classp = pci_class; classp->name != NULL; classp++) { 508 if (PCI_CLASS(rval) == classp->val) 509 break; 510 } 511 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 512 while (subclassp && subclassp->name != NULL) { 513 if (PCI_SUBCLASS(rval) == subclassp->val) 514 break; 515 subclassp++; 516 } 517 if (classp->name != NULL) { 518 printf(" Class Name: %s (0x%02x)\n", classp->name, 519 PCI_CLASS(rval)); 520 if (subclassp != NULL && subclassp->name != NULL) 521 printf(" Subclass Name: %s (0x%02x)\n", 522 subclassp->name, PCI_SUBCLASS(rval)); 523 else 524 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 525 } else { 526 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 527 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 528 } 529 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 530 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 531 532 rval = regs[o2i(PCI_BHLC_REG)]; 533 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 534 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 535 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 536 PCI_HDRTYPE(rval)); 537 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 538 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 539 } 540 541 static int 542 pci_conf_print_bar(pc, tag, regs, reg, name, sizebar) 543 pci_chipset_tag_t pc; 544 pcitag_t tag; 545 const pcireg_t *regs; 546 int reg; 547 const char *name; 548 int sizebar; 549 { 550 int s, width; 551 pcireg_t mask, rval; 552 pcireg_t mask64h, rval64h; 553 554 width = 4; 555 556 /* 557 * Section 6.2.5.1, `Address Maps', tells us that: 558 * 559 * 1) The builtin software should have already mapped the 560 * device in a reasonable way. 561 * 562 * 2) A device which wants 2^n bytes of memory will hardwire 563 * the bottom n bits of the address to 0. As recommended, 564 * we write all 1s and see what we get back. 565 */ 566 rval = regs[o2i(reg)]; 567 /* XXX don't size unknown memory type? */ 568 if (rval != 0 && sizebar) { 569 /* 570 * The following sequence seems to make some devices 571 * (e.g. host bus bridges, which don't normally 572 * have their space mapped) very unhappy, to 573 * the point of crashing the system. 574 * 575 * Therefore, if the mapping register is zero to 576 * start out with, don't bother trying. 577 */ 578 s = splhigh(); 579 pci_conf_write(pc, tag, reg, 0xffffffff); 580 mask = pci_conf_read(pc, tag, reg); 581 pci_conf_write(pc, tag, reg, rval); 582 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 583 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 584 rval64h = regs[o2i(reg + 4)]; 585 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 586 mask64h = pci_conf_read(pc, tag, reg + 4); 587 pci_conf_write(pc, tag, reg + 4, rval64h); 588 width = 8; 589 } 590 splx(s); 591 } else 592 mask = 0; 593 594 printf(" Base address register at 0x%02x", reg); 595 if (name) 596 printf(" (%s)", name); 597 printf("\n "); 598 if (rval == 0) { 599 printf("not implemented(?)\n"); 600 return width; 601 } 602 printf("type: "); 603 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 604 const char *type, *prefetch; 605 606 switch (PCI_MAPREG_MEM_TYPE(rval)) { 607 case PCI_MAPREG_MEM_TYPE_32BIT: 608 type = "32-bit"; 609 break; 610 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 611 type = "32-bit-1M"; 612 break; 613 case PCI_MAPREG_MEM_TYPE_64BIT: 614 type = "64-bit"; 615 break; 616 default: 617 type = "unknown (XXX)"; 618 break; 619 } 620 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 621 prefetch = ""; 622 else 623 prefetch = "non"; 624 printf("%s %sprefetchable memory\n", type, prefetch); 625 switch (PCI_MAPREG_MEM_TYPE(rval)) { 626 case PCI_MAPREG_MEM_TYPE_64BIT: 627 printf(" base: 0x%016llx, ", 628 PCI_MAPREG_MEM64_ADDR( 629 ((((long long) rval64h) << 32) | rval))); 630 if (sizebar) 631 printf("size: 0x%016llx", 632 PCI_MAPREG_MEM64_SIZE( 633 ((((long long) mask64h) << 32) | mask))); 634 else 635 printf("not sized"); 636 printf("\n"); 637 break; 638 case PCI_MAPREG_MEM_TYPE_32BIT: 639 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 640 default: 641 printf(" base: 0x%08x, ", 642 PCI_MAPREG_MEM_ADDR(rval)); 643 if (sizebar) 644 printf("size: 0x%08x", 645 PCI_MAPREG_MEM_SIZE(mask)); 646 else 647 printf("not sized"); 648 printf("\n"); 649 break; 650 } 651 } else { 652 if (sizebar) 653 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 654 printf("i/o\n"); 655 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 656 if (sizebar) 657 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 658 else 659 printf("not sized"); 660 printf("\n"); 661 } 662 663 return width; 664 } 665 666 static void 667 pci_conf_print_regs(regs, first, pastlast) 668 const pcireg_t *regs; 669 int first, pastlast; 670 { 671 int off, needaddr, neednl; 672 673 needaddr = 1; 674 neednl = 0; 675 for (off = first; off < pastlast; off += 4) { 676 if ((off % 16) == 0 || needaddr) { 677 printf(" 0x%02x:", off); 678 needaddr = 0; 679 } 680 printf(" 0x%08x", regs[o2i(off)]); 681 neednl = 1; 682 if ((off % 16) == 12) { 683 printf("\n"); 684 neednl = 0; 685 } 686 } 687 if (neednl) 688 printf("\n"); 689 } 690 691 static void 692 pci_conf_print_type0(pc, tag, regs, sizebars) 693 pci_chipset_tag_t pc; 694 pcitag_t tag; 695 const pcireg_t *regs; 696 int sizebars; 697 { 698 int off, width; 699 pcireg_t rval; 700 701 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) 702 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 703 704 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 705 706 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 707 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 708 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 709 710 /* XXX */ 711 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 712 713 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 714 printf(" Capability list pointer: 0x%02x\n", 715 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 716 else 717 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 718 719 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 720 721 rval = regs[o2i(PCI_INTERRUPT_REG)]; 722 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 723 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 724 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 725 switch (PCI_INTERRUPT_PIN(rval)) { 726 case PCI_INTERRUPT_PIN_NONE: 727 printf("(none)"); 728 break; 729 case PCI_INTERRUPT_PIN_A: 730 printf("(pin A)"); 731 break; 732 case PCI_INTERRUPT_PIN_B: 733 printf("(pin B)"); 734 break; 735 case PCI_INTERRUPT_PIN_C: 736 printf("(pin C)"); 737 break; 738 case PCI_INTERRUPT_PIN_D: 739 printf("(pin D)"); 740 break; 741 default: 742 printf("(? ? ?)"); 743 break; 744 } 745 printf("\n"); 746 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 747 748 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) { 749 for (off = PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]); 750 off != 0; 751 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 752 rval = regs[o2i(off)]; 753 printf(" Capability register at 0x%02x\n", off); 754 755 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 756 switch (PCI_CAPLIST_CAP(rval)) { 757 case PCI_CAP_RESERVED0: 758 printf("reserved"); 759 break; 760 case PCI_CAP_PWRMGMT: 761 printf("Power Management, rev. %d.0", 762 (rval >> 0) & 0x07); /* XXX not clear */ 763 break; 764 case PCI_CAP_AGP: 765 printf("AGP, rev. %d.%d", 766 (rval >> 24) & 0x0f, 767 (rval >> 20) & 0x0f); 768 break; 769 case PCI_CAP_VPD: 770 printf("VPD"); 771 break; 772 case PCI_CAP_SLOTID: 773 printf("SlotID"); 774 break; 775 case PCI_CAP_MBI: 776 printf("MBI"); 777 break; 778 case PCI_CAP_CPCI_HOTSWAP: 779 printf("CompactPCI Hot-swapping"); 780 break; 781 case PCI_CAP_PCIX: 782 printf("PCI-X"); 783 break; 784 case PCI_CAP_LDT: 785 printf("LDT"); 786 break; 787 case PCI_CAP_VENDSPEC: 788 printf("Vendor-specific"); 789 break; 790 case PCI_CAP_DEBUGPORT: 791 printf("Debug Port"); 792 break; 793 case PCI_CAP_CPCI_RSRCCTL: 794 printf("CompactPCI Resource Control"); 795 break; 796 case PCI_CAP_HOTPLUG: 797 printf("Hot-Plug"); 798 break; 799 default: 800 printf("unknown"); 801 } 802 printf(")\n"); 803 } 804 } 805 } 806 807 static void 808 pci_conf_print_type1(pc, tag, regs, sizebars) 809 pci_chipset_tag_t pc; 810 pcitag_t tag; 811 const pcireg_t *regs; 812 int sizebars; 813 { 814 int off, width; 815 pcireg_t rval; 816 817 /* 818 * XXX these need to be printed in more detail, need to be 819 * XXX checked against specs/docs, etc. 820 * 821 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 822 * Bridge chip documentation, and may not be correct with 823 * respect to various standards. (XXX) 824 */ 825 826 for (off = 0x10; off < 0x18; off += width) 827 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 828 829 printf(" Primary bus number: 0x%02x\n", 830 (regs[o2i(0x18)] >> 0) & 0xff); 831 printf(" Secondary bus number: 0x%02x\n", 832 (regs[o2i(0x18)] >> 8) & 0xff); 833 printf(" Subordinate bus number: 0x%02x\n", 834 (regs[o2i(0x18)] >> 16) & 0xff); 835 printf(" Secondary bus latency timer: 0x%02x\n", 836 (regs[o2i(0x18)] >> 24) & 0xff); 837 838 rval = (regs[o2i(0x1c)] >> 16) & 0xffff; 839 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 840 onoff("66 MHz capable", 0x0020); 841 onoff("User Definable Features (UDF) support", 0x0040); 842 onoff("Fast back-to-back capable", 0x0080); 843 onoff("Data parity error detected", 0x0100); 844 845 printf(" DEVSEL timing: "); 846 switch (rval & 0x0600) { 847 case 0x0000: 848 printf("fast"); 849 break; 850 case 0x0200: 851 printf("medium"); 852 break; 853 case 0x0400: 854 printf("slow"); 855 break; 856 default: 857 printf("unknown/reserved"); /* XXX */ 858 break; 859 } 860 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 861 862 onoff("Signaled Target Abort", 0x0800); 863 onoff("Received Target Abort", 0x1000); 864 onoff("Received Master Abort", 0x2000); 865 onoff("System Error", 0x4000); 866 onoff("Parity Error", 0x8000); 867 868 /* XXX Print more prettily */ 869 printf(" I/O region:\n"); 870 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 871 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 872 printf(" base upper 16 bits register: 0x%04x\n", 873 (regs[o2i(0x30)] >> 0) & 0xffff); 874 printf(" limit upper 16 bits register: 0x%04x\n", 875 (regs[o2i(0x30)] >> 16) & 0xffff); 876 877 /* XXX Print more prettily */ 878 printf(" Memory region:\n"); 879 printf(" base register: 0x%04x\n", 880 (regs[o2i(0x20)] >> 0) & 0xffff); 881 printf(" limit register: 0x%04x\n", 882 (regs[o2i(0x20)] >> 16) & 0xffff); 883 884 /* XXX Print more prettily */ 885 printf(" Prefetchable memory region:\n"); 886 printf(" base register: 0x%04x\n", 887 (regs[o2i(0x24)] >> 0) & 0xffff); 888 printf(" limit register: 0x%04x\n", 889 (regs[o2i(0x24)] >> 16) & 0xffff); 890 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 891 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 892 893 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 894 /* XXX */ 895 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 896 897 printf(" Interrupt line: 0x%02x\n", 898 (regs[o2i(0x3c)] >> 0) & 0xff); 899 printf(" Interrupt pin: 0x%02x ", 900 (regs[o2i(0x3c)] >> 8) & 0xff); 901 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 902 case PCI_INTERRUPT_PIN_NONE: 903 printf("(none)"); 904 break; 905 case PCI_INTERRUPT_PIN_A: 906 printf("(pin A)"); 907 break; 908 case PCI_INTERRUPT_PIN_B: 909 printf("(pin B)"); 910 break; 911 case PCI_INTERRUPT_PIN_C: 912 printf("(pin C)"); 913 break; 914 case PCI_INTERRUPT_PIN_D: 915 printf("(pin D)"); 916 break; 917 default: 918 printf("(? ? ?)"); 919 break; 920 } 921 printf("\n"); 922 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 923 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 924 onoff("Parity error response", 0x0001); 925 onoff("Secondary SERR forwarding", 0x0002); 926 onoff("ISA enable", 0x0004); 927 onoff("VGA enable", 0x0008); 928 onoff("Master abort reporting", 0x0020); 929 onoff("Secondary bus reset", 0x0040); 930 onoff("Fast back-to-back capable", 0x0080); 931 } 932 933 static void 934 pci_conf_print_type2(pc, tag, regs, sizebars) 935 pci_chipset_tag_t pc; 936 pcitag_t tag; 937 const pcireg_t *regs; 938 int sizebars; 939 { 940 pcireg_t rval; 941 942 /* 943 * XXX these need to be printed in more detail, need to be 944 * XXX checked against specs/docs, etc. 945 * 946 * This layout was cribbed from the TI PCI1130 PCI-to-CardBus 947 * controller chip documentation, and may not be correct with 948 * respect to various standards. (XXX) 949 */ 950 951 pci_conf_print_bar(pc, tag, regs, 0x10, 952 "CardBus socket/ExCA registers", sizebars); 953 954 printf(" Reserved @ 0x14: 0x%04x\n", 955 (regs[o2i(0x14)] >> 0) & 0xffff); 956 rval = (regs[o2i(0x14)] >> 16) & 0xffff; 957 printf(" Secondary status register: 0x%04x\n", rval); 958 onoff("66 MHz capable", 0x0020); 959 onoff("User Definable Features (UDF) support", 0x0040); 960 onoff("Fast back-to-back capable", 0x0080); 961 onoff("Data parity error detection", 0x0100); 962 963 printf(" DEVSEL timing: "); 964 switch (rval & 0x0600) { 965 case 0x0000: 966 printf("fast"); 967 break; 968 case 0x0200: 969 printf("medium"); 970 break; 971 case 0x0400: 972 printf("slow"); 973 break; 974 default: 975 printf("unknown/reserved"); /* XXX */ 976 break; 977 } 978 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 979 onoff("PCI target aborts terminate CardBus bus master transactions", 980 0x0800); 981 onoff("CardBus target aborts terminate PCI bus master transactions", 982 0x1000); 983 onoff("Bus initiator aborts terminate initiator transactions", 984 0x2000); 985 onoff("System error", 0x4000); 986 onoff("Parity error", 0x8000); 987 988 printf(" PCI bus number: 0x%02x\n", 989 (regs[o2i(0x18)] >> 0) & 0xff); 990 printf(" CardBus bus number: 0x%02x\n", 991 (regs[o2i(0x18)] >> 8) & 0xff); 992 printf(" Subordinate bus number: 0x%02x\n", 993 (regs[o2i(0x18)] >> 16) & 0xff); 994 printf(" CardBus latency timer: 0x%02x\n", 995 (regs[o2i(0x18)] >> 24) & 0xff); 996 997 /* XXX Print more prettily */ 998 printf(" CardBus memory region 0:\n"); 999 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1000 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1001 printf(" CardBus memory region 1:\n"); 1002 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1003 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1004 printf(" CardBus I/O region 0:\n"); 1005 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1006 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1007 printf(" CardBus I/O region 1:\n"); 1008 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1009 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1010 1011 printf(" Interrupt line: 0x%02x\n", 1012 (regs[o2i(0x3c)] >> 0) & 0xff); 1013 printf(" Interrupt pin: 0x%02x ", 1014 (regs[o2i(0x3c)] >> 8) & 0xff); 1015 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1016 case PCI_INTERRUPT_PIN_NONE: 1017 printf("(none)"); 1018 break; 1019 case PCI_INTERRUPT_PIN_A: 1020 printf("(pin A)"); 1021 break; 1022 case PCI_INTERRUPT_PIN_B: 1023 printf("(pin B)"); 1024 break; 1025 case PCI_INTERRUPT_PIN_C: 1026 printf("(pin C)"); 1027 break; 1028 case PCI_INTERRUPT_PIN_D: 1029 printf("(pin D)"); 1030 break; 1031 default: 1032 printf("(? ? ?)"); 1033 break; 1034 } 1035 printf("\n"); 1036 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1037 printf(" Bridge control register: 0x%04x\n", rval); 1038 onoff("Parity error response", 0x0001); 1039 onoff("CardBus SERR forwarding", 0x0002); 1040 onoff("ISA enable", 0x0004); 1041 onoff("VGA enable", 0x0008); 1042 onoff("CardBus master abort reporting", 0x0020); 1043 onoff("CardBus reset", 0x0040); 1044 onoff("Functional interrupts routed by ExCA registers", 0x0080); 1045 onoff("Memory window 0 prefetchable", 0x0100); 1046 onoff("Memory window 1 prefetchable", 0x0200); 1047 onoff("Write posting enable", 0x0400); 1048 1049 rval = regs[o2i(0x40)]; 1050 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1051 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1052 1053 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1054 sizebars); 1055 } 1056 1057 void 1058 pci_conf_print(pc, tag, printfn) 1059 pci_chipset_tag_t pc; 1060 pcitag_t tag; 1061 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *); 1062 { 1063 pcireg_t regs[o2i(256)]; 1064 int off, endoff, hdrtype; 1065 const char *typename; 1066 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1067 int sizebars; 1068 1069 printf("PCI configuration registers:\n"); 1070 1071 for (off = 0; off < 256; off += 4) 1072 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1073 1074 sizebars = 1; 1075 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1076 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1077 sizebars = 0; 1078 1079 /* common header */ 1080 printf(" Common header:\n"); 1081 pci_conf_print_regs(regs, 0, 16); 1082 1083 printf("\n"); 1084 pci_conf_print_common(pc, tag, regs); 1085 printf("\n"); 1086 1087 /* type-dependent header */ 1088 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1089 switch (hdrtype) { /* XXX make a table, eventually */ 1090 case 0: 1091 /* Standard device header */ 1092 typename = "\"normal\" device"; 1093 typeprintfn = &pci_conf_print_type0; 1094 endoff = 64; 1095 break; 1096 case 1: 1097 /* PCI-PCI bridge header */ 1098 typename = "PCI-PCI bridge"; 1099 typeprintfn = &pci_conf_print_type1; 1100 endoff = 64; 1101 break; 1102 case 2: 1103 /* PCI-CardBus bridge header */ 1104 typename = "PCI-CardBus bridge"; 1105 typeprintfn = &pci_conf_print_type2; 1106 endoff = 72; 1107 break; 1108 default: 1109 typename = NULL; 1110 typeprintfn = 0; 1111 endoff = 64; 1112 break; 1113 } 1114 printf(" Type %d ", hdrtype); 1115 if (typename != NULL) 1116 printf("(%s) ", typename); 1117 printf("header:\n"); 1118 pci_conf_print_regs(regs, 16, endoff); 1119 printf("\n"); 1120 if (typeprintfn) 1121 (*typeprintfn)(pc, tag, regs, sizebars); 1122 else 1123 printf(" Don't know how to pretty-print type %d header.\n", 1124 hdrtype); 1125 printf("\n"); 1126 1127 /* device-dependent header */ 1128 printf(" Device-dependent header:\n"); 1129 pci_conf_print_regs(regs, endoff, 256); 1130 printf("\n"); 1131 if (printfn) 1132 (*printfn)(pc, tag, regs); 1133 else 1134 printf(" Don't know how to pretty-print device-dependent header.\n"); 1135 printf("\n"); 1136 } 1137
Indexes created Fri Sep 26 20:09:58 GMT 2025