pci_subr.c revision 1.44
1 /* $NetBSD: pci_subr.c,v 1.44 2001/09/13 18:25:45 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 */ 38 39 #include "opt_pci.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 45 #include <machine/intr.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #ifdef PCIVERBOSE 50 #include <dev/pci/pcidevs.h> 51 #endif 52 53 /* 54 * Descriptions of known PCI classes and subclasses. 55 * 56 * Subclasses are described in the same way as classes, but have a 57 * NULL subclass pointer. 58 */ 59 struct pci_class { 60 const char *name; 61 int val; /* as wide as pci_{,sub}class_t */ 62 const struct pci_class *subclasses; 63 }; 64 65 const struct pci_class pci_subclass_prehistoric[] = { 66 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, }, 67 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, }, 68 { 0 } 69 }; 70 71 const struct pci_class pci_subclass_mass_storage[] = { 72 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, }, 73 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, }, 74 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, }, 75 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, }, 76 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, }, 77 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, }, 78 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, }, 79 { 0 }, 80 }; 81 82 const struct pci_class pci_subclass_network[] = { 83 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, }, 84 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, }, 85 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, }, 86 { "ATM", PCI_SUBCLASS_NETWORK_ATM, }, 87 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, }, 88 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, }, 89 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, }, 90 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, }, 91 { 0 }, 92 }; 93 94 const struct pci_class pci_subclass_display[] = { 95 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, }, 96 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, }, 97 { "3D", PCI_SUBCLASS_DISPLAY_3D, }, 98 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, }, 99 { 0 }, 100 }; 101 102 const struct pci_class pci_subclass_multimedia[] = { 103 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, }, 104 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, }, 105 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, }, 106 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, }, 107 { 0 }, 108 }; 109 110 const struct pci_class pci_subclass_memory[] = { 111 { "RAM", PCI_SUBCLASS_MEMORY_RAM, }, 112 { "flash", PCI_SUBCLASS_MEMORY_FLASH, }, 113 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, }, 114 { 0 }, 115 }; 116 117 const struct pci_class pci_subclass_bridge[] = { 118 { "host", PCI_SUBCLASS_BRIDGE_HOST, }, 119 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, }, 120 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, }, 121 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, }, 122 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, }, 123 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, }, 124 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, }, 125 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, }, 126 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, }, 127 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, }, 128 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, }, 129 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, }, 130 { 0 }, 131 }; 132 133 const struct pci_class pci_subclass_communications[] = { 134 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, }, 135 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, }, 136 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, }, 137 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, }, 138 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, }, 139 { 0 }, 140 }; 141 142 const struct pci_class pci_subclass_system[] = { 143 { "8259 PIC", PCI_SUBCLASS_SYSTEM_PIC, }, 144 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, }, 145 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, }, 146 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, }, 147 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_RTC, }, 148 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, }, 149 { 0 }, 150 }; 151 152 const struct pci_class pci_subclass_input[] = { 153 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, }, 154 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, }, 155 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, }, 156 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, }, 157 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, }, 158 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, }, 159 { 0 }, 160 }; 161 162 const struct pci_class pci_subclass_dock[] = { 163 { "generic", PCI_SUBCLASS_DOCK_GENERIC, }, 164 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, }, 165 { 0 }, 166 }; 167 168 const struct pci_class pci_subclass_processor[] = { 169 { "386", PCI_SUBCLASS_PROCESSOR_386, }, 170 { "486", PCI_SUBCLASS_PROCESSOR_486, }, 171 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, }, 172 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, }, 173 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, }, 174 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, }, 175 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, }, 176 { 0 }, 177 }; 178 179 const struct pci_class pci_subclass_serialbus[] = { 180 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, }, 181 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, }, 182 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, }, 183 { "USB", PCI_SUBCLASS_SERIALBUS_USB, }, 184 /* XXX Fiber Channel/_FIBRECHANNEL */ 185 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, }, 186 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, }, 187 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, }, 188 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, }, 189 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, }, 190 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, }, 191 { 0 }, 192 }; 193 194 const struct pci_class pci_subclass_wireless[] = { 195 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, }, 196 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, }, 197 { "RF", PCI_SUBCLASS_WIRELESS_RF, }, 198 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, }, 199 { 0 }, 200 }; 201 202 const struct pci_class pci_subclass_i2o[] = { 203 { "standard", PCI_SUBCLASS_I2O_STANDARD, }, 204 { 0 }, 205 }; 206 207 const struct pci_class pci_subclass_satcom[] = { 208 { "TV", PCI_SUBCLASS_SATCOM_TV, }, 209 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, }, 210 { "voice", PCI_SUBCLASS_SATCOM_VOICE, }, 211 { "data", PCI_SUBCLASS_SATCOM_DATA, }, 212 { 0 }, 213 }; 214 215 const struct pci_class pci_subclass_crypto[] = { 216 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, }, 217 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, }, 218 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, }, 219 { 0 }, 220 }; 221 222 const struct pci_class pci_subclass_dasp[] = { 223 { "DPIO", PCI_SUBCLASS_DASP_DPIO, }, 224 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, }, 225 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, }, 226 { 0 }, 227 }; 228 229 const struct pci_class pci_class[] = { 230 { "prehistoric", PCI_CLASS_PREHISTORIC, 231 pci_subclass_prehistoric, }, 232 { "mass storage", PCI_CLASS_MASS_STORAGE, 233 pci_subclass_mass_storage, }, 234 { "network", PCI_CLASS_NETWORK, 235 pci_subclass_network, }, 236 { "display", PCI_CLASS_DISPLAY, 237 pci_subclass_display, }, 238 { "multimedia", PCI_CLASS_MULTIMEDIA, 239 pci_subclass_multimedia, }, 240 { "memory", PCI_CLASS_MEMORY, 241 pci_subclass_memory, }, 242 { "bridge", PCI_CLASS_BRIDGE, 243 pci_subclass_bridge, }, 244 { "communications", PCI_CLASS_COMMUNICATIONS, 245 pci_subclass_communications, }, 246 { "system", PCI_CLASS_SYSTEM, 247 pci_subclass_system, }, 248 { "input", PCI_CLASS_INPUT, 249 pci_subclass_input, }, 250 { "dock", PCI_CLASS_DOCK, 251 pci_subclass_dock, }, 252 { "processor", PCI_CLASS_PROCESSOR, 253 pci_subclass_processor, }, 254 { "serial bus", PCI_CLASS_SERIALBUS, 255 pci_subclass_serialbus, }, 256 { "wireless", PCI_CLASS_WIRELESS, 257 pci_subclass_wireless, }, 258 { "I2O", PCI_CLASS_I2O, 259 pci_subclass_i2o, }, 260 { "satellite comm", PCI_CLASS_SATCOM, 261 pci_subclass_satcom, }, 262 { "crypto", PCI_CLASS_CRYPTO, 263 pci_subclass_crypto, }, 264 { "DASP", PCI_CLASS_DASP, 265 pci_subclass_dasp, }, 266 { "undefined", PCI_CLASS_UNDEFINED, 267 0, }, 268 { 0 }, 269 }; 270 271 #ifdef PCIVERBOSE 272 /* 273 * Descriptions of of known vendors and devices ("products"). 274 */ 275 struct pci_knowndev { 276 pci_vendor_id_t vendor; 277 pci_product_id_t product; 278 int flags; 279 char *vendorname, *productname; 280 }; 281 #define PCI_KNOWNDEV_NOPROD 0x01 /* match on vendor only */ 282 283 #include <dev/pci/pcidevs_data.h> 284 #endif /* PCIVERBOSE */ 285 286 char * 287 pci_findvendor(pcireg_t id_reg) 288 { 289 #ifdef PCIVERBOSE 290 pci_vendor_id_t vendor = PCI_VENDOR(id_reg); 291 const struct pci_knowndev *kdp; 292 293 kdp = pci_knowndevs; 294 while (kdp->vendorname != NULL) { /* all have vendor name */ 295 if (kdp->vendor == vendor) 296 break; 297 kdp++; 298 } 299 return (kdp->vendorname); 300 #else 301 return (NULL); 302 #endif 303 } 304 305 void 306 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp) 307 { 308 pci_vendor_id_t vendor; 309 pci_product_id_t product; 310 pci_class_t class; 311 pci_subclass_t subclass; 312 pci_interface_t interface; 313 pci_revision_t revision; 314 char *vendor_namep, *product_namep; 315 const struct pci_class *classp, *subclassp; 316 #ifdef PCIVERBOSE 317 const struct pci_knowndev *kdp; 318 const char *unmatched = "unknown "; 319 #else 320 const char *unmatched = ""; 321 #endif 322 323 vendor = PCI_VENDOR(id_reg); 324 product = PCI_PRODUCT(id_reg); 325 326 class = PCI_CLASS(class_reg); 327 subclass = PCI_SUBCLASS(class_reg); 328 interface = PCI_INTERFACE(class_reg); 329 revision = PCI_REVISION(class_reg); 330 331 #ifdef PCIVERBOSE 332 kdp = pci_knowndevs; 333 while (kdp->vendorname != NULL) { /* all have vendor name */ 334 if (kdp->vendor == vendor && (kdp->product == product || 335 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) 336 break; 337 kdp++; 338 } 339 if (kdp->vendorname == NULL) 340 vendor_namep = product_namep = NULL; 341 else { 342 vendor_namep = kdp->vendorname; 343 product_namep = (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0 ? 344 kdp->productname : NULL; 345 } 346 #else /* PCIVERBOSE */ 347 vendor_namep = product_namep = NULL; 348 #endif /* PCIVERBOSE */ 349 350 classp = pci_class; 351 while (classp->name != NULL) { 352 if (class == classp->val) 353 break; 354 classp++; 355 } 356 357 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 358 while (subclassp && subclassp->name != NULL) { 359 if (subclass == subclassp->val) 360 break; 361 subclassp++; 362 } 363 364 if (vendor_namep == NULL) 365 cp += sprintf(cp, "%svendor 0x%04x product 0x%04x", 366 unmatched, vendor, product); 367 else if (product_namep != NULL) 368 cp += sprintf(cp, "%s %s", vendor_namep, product_namep); 369 else 370 cp += sprintf(cp, "%s product 0x%04x", 371 vendor_namep, product); 372 if (showclass) { 373 cp += sprintf(cp, " ("); 374 if (classp->name == NULL) 375 cp += sprintf(cp, "class 0x%02x, subclass 0x%02x", 376 class, subclass); 377 else { 378 if (subclassp == NULL || subclassp->name == NULL) 379 cp += sprintf(cp, 380 "%s subclass 0x%02x", 381 classp->name, subclass); 382 else 383 cp += sprintf(cp, "%s %s", 384 subclassp->name, classp->name); 385 } 386 if (interface != 0) 387 cp += sprintf(cp, ", interface 0x%02x", interface); 388 if (revision != 0) 389 cp += sprintf(cp, ", revision 0x%02x", revision); 390 cp += sprintf(cp, ")"); 391 } 392 } 393 394 /* 395 * Print out most of the PCI configuration registers. Typically used 396 * in a device attach routine like this: 397 * 398 * #ifdef MYDEV_DEBUG 399 * printf("%s: ", sc->sc_dev.dv_xname); 400 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 401 * #endif 402 */ 403 404 #define i2o(i) ((i) * 4) 405 #define o2i(o) ((o) / 4) 406 #define onoff(str, bit) \ 407 printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off"); 408 409 static void 410 pci_conf_print_common(pci_chipset_tag_t pc, pcitag_t tag, const pcireg_t *regs) 411 { 412 #ifdef PCIVERBOSE 413 const struct pci_knowndev *kdp; 414 #endif 415 const struct pci_class *classp, *subclassp; 416 pcireg_t rval; 417 418 rval = regs[o2i(PCI_ID_REG)]; 419 #ifndef PCIVERBOSE 420 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 421 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 422 #else 423 for (kdp = pci_knowndevs; kdp->vendorname != NULL; kdp++) { 424 if (kdp->vendor == PCI_VENDOR(rval) && 425 (kdp->product == PCI_PRODUCT(rval) || 426 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) { 427 break; 428 } 429 } 430 if (kdp->vendorname != NULL) 431 printf(" Vendor Name: %s (0x%04x)\n", kdp->vendorname, 432 PCI_VENDOR(rval)); 433 else 434 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 435 if (kdp->productname != NULL && (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0) 436 printf(" Device Name: %s (0x%04x)\n", kdp->productname, 437 PCI_PRODUCT(rval)); 438 else 439 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 440 #endif /* PCIVERBOSE */ 441 442 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 443 444 printf(" Command register: 0x%04x\n", rval & 0xffff); 445 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 446 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 447 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 448 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 449 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 450 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 451 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 452 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 453 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 454 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 455 456 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 457 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 458 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 459 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 460 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 461 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 462 463 printf(" DEVSEL timing: "); 464 switch (rval & PCI_STATUS_DEVSEL_MASK) { 465 case PCI_STATUS_DEVSEL_FAST: 466 printf("fast"); 467 break; 468 case PCI_STATUS_DEVSEL_MEDIUM: 469 printf("medium"); 470 break; 471 case PCI_STATUS_DEVSEL_SLOW: 472 printf("slow"); 473 break; 474 default: 475 printf("unknown/reserved"); /* XXX */ 476 break; 477 } 478 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 479 480 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 481 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 482 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 483 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 484 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 485 486 rval = regs[o2i(PCI_CLASS_REG)]; 487 for (classp = pci_class; classp->name != NULL; classp++) { 488 if (PCI_CLASS(rval) == classp->val) 489 break; 490 } 491 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 492 while (subclassp && subclassp->name != NULL) { 493 if (PCI_SUBCLASS(rval) == subclassp->val) 494 break; 495 subclassp++; 496 } 497 if (classp->name != NULL) { 498 printf(" Class Name: %s (0x%02x)\n", classp->name, 499 PCI_CLASS(rval)); 500 if (subclassp != NULL && subclassp->name != NULL) 501 printf(" Subclass Name: %s (0x%02x)\n", 502 subclassp->name, PCI_SUBCLASS(rval)); 503 else 504 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 505 } else { 506 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 507 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 508 } 509 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 510 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 511 512 rval = regs[o2i(PCI_BHLC_REG)]; 513 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 514 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 515 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 516 PCI_HDRTYPE(rval)); 517 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 518 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 519 } 520 521 static int 522 pci_conf_print_bar(pci_chipset_tag_t pc, pcitag_t tag, const pcireg_t *regs, 523 int reg, const char *name, int sizebar) 524 { 525 int s, width; 526 pcireg_t mask, rval; 527 pcireg_t mask64h, rval64h; 528 529 width = 4; 530 531 /* 532 * Section 6.2.5.1, `Address Maps', tells us that: 533 * 534 * 1) The builtin software should have already mapped the 535 * device in a reasonable way. 536 * 537 * 2) A device which wants 2^n bytes of memory will hardwire 538 * the bottom n bits of the address to 0. As recommended, 539 * we write all 1s and see what we get back. 540 */ 541 rval = regs[o2i(reg)]; 542 /* XXX don't size unknown memory type? */ 543 if (rval != 0 && sizebar) { 544 /* 545 * The following sequence seems to make some devices 546 * (e.g. host bus bridges, which don't normally 547 * have their space mapped) very unhappy, to 548 * the point of crashing the system. 549 * 550 * Therefore, if the mapping register is zero to 551 * start out with, don't bother trying. 552 */ 553 s = splhigh(); 554 pci_conf_write(pc, tag, reg, 0xffffffff); 555 mask = pci_conf_read(pc, tag, reg); 556 pci_conf_write(pc, tag, reg, rval); 557 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 558 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 559 rval64h = regs[o2i(reg + 4)]; 560 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 561 mask64h = pci_conf_read(pc, tag, reg + 4); 562 pci_conf_write(pc, tag, reg + 4, rval64h); 563 width = 8; 564 } 565 splx(s); 566 } else 567 mask = 0; 568 569 printf(" Base address register at 0x%02x", reg); 570 if (name) 571 printf(" (%s)", name); 572 printf("\n "); 573 if (rval == 0) { 574 printf("not implemented(?)\n"); 575 return width; 576 } 577 printf("type: "); 578 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 579 const char *type, *prefetch; 580 581 switch (PCI_MAPREG_MEM_TYPE(rval)) { 582 case PCI_MAPREG_MEM_TYPE_32BIT: 583 type = "32-bit"; 584 break; 585 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 586 type = "32-bit-1M"; 587 break; 588 case PCI_MAPREG_MEM_TYPE_64BIT: 589 type = "64-bit"; 590 break; 591 default: 592 type = "unknown (XXX)"; 593 break; 594 } 595 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 596 prefetch = ""; 597 else 598 prefetch = "non"; 599 printf("%s %sprefetchable memory\n", type, prefetch); 600 switch (PCI_MAPREG_MEM_TYPE(rval)) { 601 case PCI_MAPREG_MEM_TYPE_64BIT: 602 printf(" base: 0x%016llx, ", 603 PCI_MAPREG_MEM64_ADDR( 604 ((((long long) rval64h) << 32) | rval))); 605 if (sizebar) 606 printf("size: 0x%016llx", 607 PCI_MAPREG_MEM64_SIZE( 608 ((((long long) mask64h) << 32) | mask))); 609 else 610 printf("not sized"); 611 printf("\n"); 612 break; 613 case PCI_MAPREG_MEM_TYPE_32BIT: 614 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 615 default: 616 printf(" base: 0x%08x, ", 617 PCI_MAPREG_MEM_ADDR(rval)); 618 if (sizebar) 619 printf("size: 0x%08x", 620 PCI_MAPREG_MEM_SIZE(mask)); 621 else 622 printf("not sized"); 623 printf("\n"); 624 break; 625 } 626 } else { 627 if (sizebar) 628 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 629 printf("i/o\n"); 630 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 631 if (sizebar) 632 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 633 else 634 printf("not sized"); 635 printf("\n"); 636 } 637 638 return width; 639 } 640 641 static void 642 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 643 { 644 int off, needaddr, neednl; 645 646 needaddr = 1; 647 neednl = 0; 648 for (off = first; off < pastlast; off += 4) { 649 if ((off % 16) == 0 || needaddr) { 650 printf(" 0x%02x:", off); 651 needaddr = 0; 652 } 653 printf(" 0x%08x", regs[o2i(off)]); 654 neednl = 1; 655 if ((off % 16) == 12) { 656 printf("\n"); 657 neednl = 0; 658 } 659 } 660 if (neednl) 661 printf("\n"); 662 } 663 664 static void 665 pci_conf_print_type0(pci_chipset_tag_t pc, pcitag_t tag, const pcireg_t *regs, 666 int sizebars) 667 { 668 int off, width; 669 pcireg_t rval; 670 671 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) 672 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 673 674 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 675 676 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 677 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 678 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 679 680 /* XXX */ 681 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 682 683 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 684 printf(" Capability list pointer: 0x%02x\n", 685 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 686 else 687 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 688 689 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 690 691 rval = regs[o2i(PCI_INTERRUPT_REG)]; 692 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 693 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 694 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 695 switch (PCI_INTERRUPT_PIN(rval)) { 696 case PCI_INTERRUPT_PIN_NONE: 697 printf("(none)"); 698 break; 699 case PCI_INTERRUPT_PIN_A: 700 printf("(pin A)"); 701 break; 702 case PCI_INTERRUPT_PIN_B: 703 printf("(pin B)"); 704 break; 705 case PCI_INTERRUPT_PIN_C: 706 printf("(pin C)"); 707 break; 708 case PCI_INTERRUPT_PIN_D: 709 printf("(pin D)"); 710 break; 711 default: 712 printf("(? ? ?)"); 713 break; 714 } 715 printf("\n"); 716 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 717 718 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) { 719 for (off = PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]); 720 off != 0; 721 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 722 rval = regs[o2i(off)]; 723 printf(" Capability register at 0x%02x\n", off); 724 725 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 726 switch (PCI_CAPLIST_CAP(rval)) { 727 case PCI_CAP_RESERVED0: 728 printf("reserved"); 729 break; 730 case PCI_CAP_PWRMGMT: 731 printf("Power Management, rev. %d.0", 732 (rval >> 0) & 0x07); /* XXX not clear */ 733 break; 734 case PCI_CAP_AGP: 735 printf("AGP, rev. %d.%d", 736 (rval >> 24) & 0x0f, 737 (rval >> 20) & 0x0f); 738 break; 739 case PCI_CAP_VPD: 740 printf("VPD"); 741 break; 742 case PCI_CAP_SLOTID: 743 printf("SlotID"); 744 break; 745 case PCI_CAP_MBI: 746 printf("MBI"); 747 break; 748 case PCI_CAP_CPCI_HOTSWAP: 749 printf("CompactPCI Hot-swapping"); 750 break; 751 case PCI_CAP_PCIX: 752 printf("PCI-X"); 753 break; 754 case PCI_CAP_LDT: 755 printf("LDT"); 756 break; 757 case PCI_CAP_VENDSPEC: 758 printf("Vendor-specific"); 759 break; 760 case PCI_CAP_DEBUGPORT: 761 printf("Debug Port"); 762 break; 763 case PCI_CAP_CPCI_RSRCCTL: 764 printf("CompactPCI Resource Control"); 765 break; 766 case PCI_CAP_HOTPLUG: 767 printf("Hot-Plug"); 768 break; 769 default: 770 printf("unknown"); 771 } 772 printf(")\n"); 773 } 774 } 775 } 776 777 static void 778 pci_conf_print_type1(pci_chipset_tag_t pc, pcitag_t tag, const pcireg_t *regs, 779 int sizebars) 780 { 781 int off, width; 782 pcireg_t rval; 783 784 /* 785 * XXX these need to be printed in more detail, need to be 786 * XXX checked against specs/docs, etc. 787 * 788 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 789 * Bridge chip documentation, and may not be correct with 790 * respect to various standards. (XXX) 791 */ 792 793 for (off = 0x10; off < 0x18; off += width) 794 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 795 796 printf(" Primary bus number: 0x%02x\n", 797 (regs[o2i(0x18)] >> 0) & 0xff); 798 printf(" Secondary bus number: 0x%02x\n", 799 (regs[o2i(0x18)] >> 8) & 0xff); 800 printf(" Subordinate bus number: 0x%02x\n", 801 (regs[o2i(0x18)] >> 16) & 0xff); 802 printf(" Secondary bus latency timer: 0x%02x\n", 803 (regs[o2i(0x18)] >> 24) & 0xff); 804 805 rval = (regs[o2i(0x1c)] >> 16) & 0xffff; 806 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 807 onoff("66 MHz capable", 0x0020); 808 onoff("User Definable Features (UDF) support", 0x0040); 809 onoff("Fast back-to-back capable", 0x0080); 810 onoff("Data parity error detected", 0x0100); 811 812 printf(" DEVSEL timing: "); 813 switch (rval & 0x0600) { 814 case 0x0000: 815 printf("fast"); 816 break; 817 case 0x0200: 818 printf("medium"); 819 break; 820 case 0x0400: 821 printf("slow"); 822 break; 823 default: 824 printf("unknown/reserved"); /* XXX */ 825 break; 826 } 827 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 828 829 onoff("Signaled Target Abort", 0x0800); 830 onoff("Received Target Abort", 0x1000); 831 onoff("Received Master Abort", 0x2000); 832 onoff("System Error", 0x4000); 833 onoff("Parity Error", 0x8000); 834 835 /* XXX Print more prettily */ 836 printf(" I/O region:\n"); 837 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 838 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 839 printf(" base upper 16 bits register: 0x%04x\n", 840 (regs[o2i(0x30)] >> 0) & 0xffff); 841 printf(" limit upper 16 bits register: 0x%04x\n", 842 (regs[o2i(0x30)] >> 16) & 0xffff); 843 844 /* XXX Print more prettily */ 845 printf(" Memory region:\n"); 846 printf(" base register: 0x%04x\n", 847 (regs[o2i(0x20)] >> 0) & 0xffff); 848 printf(" limit register: 0x%04x\n", 849 (regs[o2i(0x20)] >> 16) & 0xffff); 850 851 /* XXX Print more prettily */ 852 printf(" Prefetchable memory region:\n"); 853 printf(" base register: 0x%04x\n", 854 (regs[o2i(0x24)] >> 0) & 0xffff); 855 printf(" limit register: 0x%04x\n", 856 (regs[o2i(0x24)] >> 16) & 0xffff); 857 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 858 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 859 860 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 861 /* XXX */ 862 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 863 864 printf(" Interrupt line: 0x%02x\n", 865 (regs[o2i(0x3c)] >> 0) & 0xff); 866 printf(" Interrupt pin: 0x%02x ", 867 (regs[o2i(0x3c)] >> 8) & 0xff); 868 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 869 case PCI_INTERRUPT_PIN_NONE: 870 printf("(none)"); 871 break; 872 case PCI_INTERRUPT_PIN_A: 873 printf("(pin A)"); 874 break; 875 case PCI_INTERRUPT_PIN_B: 876 printf("(pin B)"); 877 break; 878 case PCI_INTERRUPT_PIN_C: 879 printf("(pin C)"); 880 break; 881 case PCI_INTERRUPT_PIN_D: 882 printf("(pin D)"); 883 break; 884 default: 885 printf("(? ? ?)"); 886 break; 887 } 888 printf("\n"); 889 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 890 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 891 onoff("Parity error response", 0x0001); 892 onoff("Secondary SERR forwarding", 0x0002); 893 onoff("ISA enable", 0x0004); 894 onoff("VGA enable", 0x0008); 895 onoff("Master abort reporting", 0x0020); 896 onoff("Secondary bus reset", 0x0040); 897 onoff("Fast back-to-back capable", 0x0080); 898 } 899 900 static void 901 pci_conf_print_type2(pci_chipset_tag_t pc, pcitag_t tag, const pcireg_t *regs, 902 int sizebars) 903 { 904 pcireg_t rval; 905 906 /* 907 * XXX these need to be printed in more detail, need to be 908 * XXX checked against specs/docs, etc. 909 * 910 * This layout was cribbed from the TI PCI1130 PCI-to-CardBus 911 * controller chip documentation, and may not be correct with 912 * respect to various standards. (XXX) 913 */ 914 915 pci_conf_print_bar(pc, tag, regs, 0x10, 916 "CardBus socket/ExCA registers", sizebars); 917 918 printf(" Reserved @ 0x14: 0x%04x\n", 919 (regs[o2i(0x14)] >> 0) & 0xffff); 920 rval = (regs[o2i(0x14)] >> 16) & 0xffff; 921 printf(" Secondary status register: 0x%04x\n", rval); 922 onoff("66 MHz capable", 0x0020); 923 onoff("User Definable Features (UDF) support", 0x0040); 924 onoff("Fast back-to-back capable", 0x0080); 925 onoff("Data parity error detection", 0x0100); 926 927 printf(" DEVSEL timing: "); 928 switch (rval & 0x0600) { 929 case 0x0000: 930 printf("fast"); 931 break; 932 case 0x0200: 933 printf("medium"); 934 break; 935 case 0x0400: 936 printf("slow"); 937 break; 938 default: 939 printf("unknown/reserved"); /* XXX */ 940 break; 941 } 942 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 943 onoff("PCI target aborts terminate CardBus bus master transactions", 944 0x0800); 945 onoff("CardBus target aborts terminate PCI bus master transactions", 946 0x1000); 947 onoff("Bus initiator aborts terminate initiator transactions", 948 0x2000); 949 onoff("System error", 0x4000); 950 onoff("Parity error", 0x8000); 951 952 printf(" PCI bus number: 0x%02x\n", 953 (regs[o2i(0x18)] >> 0) & 0xff); 954 printf(" CardBus bus number: 0x%02x\n", 955 (regs[o2i(0x18)] >> 8) & 0xff); 956 printf(" Subordinate bus number: 0x%02x\n", 957 (regs[o2i(0x18)] >> 16) & 0xff); 958 printf(" CardBus latency timer: 0x%02x\n", 959 (regs[o2i(0x18)] >> 24) & 0xff); 960 961 /* XXX Print more prettily */ 962 printf(" CardBus memory region 0:\n"); 963 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 964 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 965 printf(" CardBus memory region 1:\n"); 966 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 967 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 968 printf(" CardBus I/O region 0:\n"); 969 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 970 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 971 printf(" CardBus I/O region 1:\n"); 972 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 973 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 974 975 printf(" Interrupt line: 0x%02x\n", 976 (regs[o2i(0x3c)] >> 0) & 0xff); 977 printf(" Interrupt pin: 0x%02x ", 978 (regs[o2i(0x3c)] >> 8) & 0xff); 979 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 980 case PCI_INTERRUPT_PIN_NONE: 981 printf("(none)"); 982 break; 983 case PCI_INTERRUPT_PIN_A: 984 printf("(pin A)"); 985 break; 986 case PCI_INTERRUPT_PIN_B: 987 printf("(pin B)"); 988 break; 989 case PCI_INTERRUPT_PIN_C: 990 printf("(pin C)"); 991 break; 992 case PCI_INTERRUPT_PIN_D: 993 printf("(pin D)"); 994 break; 995 default: 996 printf("(? ? ?)"); 997 break; 998 } 999 printf("\n"); 1000 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1001 printf(" Bridge control register: 0x%04x\n", rval); 1002 onoff("Parity error response", 0x0001); 1003 onoff("CardBus SERR forwarding", 0x0002); 1004 onoff("ISA enable", 0x0004); 1005 onoff("VGA enable", 0x0008); 1006 onoff("CardBus master abort reporting", 0x0020); 1007 onoff("CardBus reset", 0x0040); 1008 onoff("Functional interrupts routed by ExCA registers", 0x0080); 1009 onoff("Memory window 0 prefetchable", 0x0100); 1010 onoff("Memory window 1 prefetchable", 0x0200); 1011 onoff("Write posting enable", 0x0400); 1012 1013 rval = regs[o2i(0x40)]; 1014 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1015 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1016 1017 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1018 sizebars); 1019 } 1020 1021 void 1022 pci_conf_print(pci_chipset_tag_t pc, pcitag_t tag, 1023 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *)) 1024 { 1025 pcireg_t regs[o2i(256)]; 1026 int off, endoff, hdrtype; 1027 const char *typename; 1028 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1029 int sizebars; 1030 1031 printf("PCI configuration registers:\n"); 1032 1033 for (off = 0; off < 256; off += 4) 1034 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1035 1036 sizebars = 1; 1037 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1038 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1039 sizebars = 0; 1040 1041 /* common header */ 1042 printf(" Common header:\n"); 1043 pci_conf_print_regs(regs, 0, 16); 1044 1045 printf("\n"); 1046 pci_conf_print_common(pc, tag, regs); 1047 printf("\n"); 1048 1049 /* type-dependent header */ 1050 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1051 switch (hdrtype) { /* XXX make a table, eventually */ 1052 case 0: 1053 /* Standard device header */ 1054 typename = "\"normal\" device"; 1055 typeprintfn = &pci_conf_print_type0; 1056 endoff = 64; 1057 break; 1058 case 1: 1059 /* PCI-PCI bridge header */ 1060 typename = "PCI-PCI bridge"; 1061 typeprintfn = &pci_conf_print_type1; 1062 endoff = 64; 1063 break; 1064 case 2: 1065 /* PCI-CardBus bridge header */ 1066 typename = "PCI-CardBus bridge"; 1067 typeprintfn = &pci_conf_print_type2; 1068 endoff = 72; 1069 break; 1070 default: 1071 typename = NULL; 1072 typeprintfn = 0; 1073 endoff = 64; 1074 break; 1075 } 1076 printf(" Type %d ", hdrtype); 1077 if (typename != NULL) 1078 printf("(%s) ", typename); 1079 printf("header:\n"); 1080 pci_conf_print_regs(regs, 16, endoff); 1081 printf("\n"); 1082 if (typeprintfn) 1083 (*typeprintfn)(pc, tag, regs, sizebars); 1084 else 1085 printf(" Don't know how to pretty-print type %d header.\n", 1086 hdrtype); 1087 printf("\n"); 1088 1089 /* device-dependent header */ 1090 printf(" Device-dependent header:\n"); 1091 pci_conf_print_regs(regs, endoff, 256); 1092 printf("\n"); 1093 if (printfn) 1094 (*printfn)(pc, tag, regs); 1095 else 1096 printf(" Don't know how to pretty-print device-dependent header.\n"); 1097 printf("\n"); 1098 } 1099
Indexes created Tue Sep 23 23:09:58 GMT 2025