pci_subr.c revision 1.45
1 /* $NetBSD: pci_subr.c,v 1.45 2001/09/13 21:42:57 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #ifdef _KERNEL_OPT 43 #include "opt_pci.h" 44 #endif 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 49 #ifdef _KERNEL 50 #include <machine/intr.h> 51 #else 52 #include <pci.h> 53 #endif 54 55 #include <dev/pci/pcireg.h> 56 #ifdef _KERNEL 57 #include <dev/pci/pcivar.h> 58 #endif 59 #ifdef PCIVERBOSE 60 #include <dev/pci/pcidevs.h> 61 #endif 62 63 /* 64 * Descriptions of known PCI classes and subclasses. 65 * 66 * Subclasses are described in the same way as classes, but have a 67 * NULL subclass pointer. 68 */ 69 struct pci_class { 70 const char *name; 71 int val; /* as wide as pci_{,sub}class_t */ 72 const struct pci_class *subclasses; 73 }; 74 75 const struct pci_class pci_subclass_prehistoric[] = { 76 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, }, 77 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, }, 78 { 0 } 79 }; 80 81 const struct pci_class pci_subclass_mass_storage[] = { 82 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, }, 83 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, }, 84 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, }, 85 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, }, 86 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, }, 87 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, }, 88 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, }, 89 { 0 }, 90 }; 91 92 const struct pci_class pci_subclass_network[] = { 93 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, }, 94 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, }, 95 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, }, 96 { "ATM", PCI_SUBCLASS_NETWORK_ATM, }, 97 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, }, 98 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, }, 99 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, }, 100 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, }, 101 { 0 }, 102 }; 103 104 const struct pci_class pci_subclass_display[] = { 105 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, }, 106 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, }, 107 { "3D", PCI_SUBCLASS_DISPLAY_3D, }, 108 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, }, 109 { 0 }, 110 }; 111 112 const struct pci_class pci_subclass_multimedia[] = { 113 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, }, 114 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, }, 115 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, }, 116 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, }, 117 { 0 }, 118 }; 119 120 const struct pci_class pci_subclass_memory[] = { 121 { "RAM", PCI_SUBCLASS_MEMORY_RAM, }, 122 { "flash", PCI_SUBCLASS_MEMORY_FLASH, }, 123 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, }, 124 { 0 }, 125 }; 126 127 const struct pci_class pci_subclass_bridge[] = { 128 { "host", PCI_SUBCLASS_BRIDGE_HOST, }, 129 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, }, 130 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, }, 131 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, }, 132 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, }, 133 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, }, 134 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, }, 135 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, }, 136 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, }, 137 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, }, 138 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, }, 139 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, }, 140 { 0 }, 141 }; 142 143 const struct pci_class pci_subclass_communications[] = { 144 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, }, 145 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, }, 146 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, }, 147 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, }, 148 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, }, 149 { 0 }, 150 }; 151 152 const struct pci_class pci_subclass_system[] = { 153 { "8259 PIC", PCI_SUBCLASS_SYSTEM_PIC, }, 154 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, }, 155 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, }, 156 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, }, 157 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_RTC, }, 158 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, }, 159 { 0 }, 160 }; 161 162 const struct pci_class pci_subclass_input[] = { 163 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, }, 164 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, }, 165 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, }, 166 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, }, 167 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, }, 168 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, }, 169 { 0 }, 170 }; 171 172 const struct pci_class pci_subclass_dock[] = { 173 { "generic", PCI_SUBCLASS_DOCK_GENERIC, }, 174 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, }, 175 { 0 }, 176 }; 177 178 const struct pci_class pci_subclass_processor[] = { 179 { "386", PCI_SUBCLASS_PROCESSOR_386, }, 180 { "486", PCI_SUBCLASS_PROCESSOR_486, }, 181 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, }, 182 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, }, 183 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, }, 184 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, }, 185 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, }, 186 { 0 }, 187 }; 188 189 const struct pci_class pci_subclass_serialbus[] = { 190 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, }, 191 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, }, 192 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, }, 193 { "USB", PCI_SUBCLASS_SERIALBUS_USB, }, 194 /* XXX Fiber Channel/_FIBRECHANNEL */ 195 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, }, 196 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, }, 197 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, }, 198 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, }, 199 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, }, 200 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, }, 201 { 0 }, 202 }; 203 204 const struct pci_class pci_subclass_wireless[] = { 205 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, }, 206 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, }, 207 { "RF", PCI_SUBCLASS_WIRELESS_RF, }, 208 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, }, 209 { 0 }, 210 }; 211 212 const struct pci_class pci_subclass_i2o[] = { 213 { "standard", PCI_SUBCLASS_I2O_STANDARD, }, 214 { 0 }, 215 }; 216 217 const struct pci_class pci_subclass_satcom[] = { 218 { "TV", PCI_SUBCLASS_SATCOM_TV, }, 219 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, }, 220 { "voice", PCI_SUBCLASS_SATCOM_VOICE, }, 221 { "data", PCI_SUBCLASS_SATCOM_DATA, }, 222 { 0 }, 223 }; 224 225 const struct pci_class pci_subclass_crypto[] = { 226 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, }, 227 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, }, 228 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, }, 229 { 0 }, 230 }; 231 232 const struct pci_class pci_subclass_dasp[] = { 233 { "DPIO", PCI_SUBCLASS_DASP_DPIO, }, 234 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, }, 235 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, }, 236 { 0 }, 237 }; 238 239 const struct pci_class pci_class[] = { 240 { "prehistoric", PCI_CLASS_PREHISTORIC, 241 pci_subclass_prehistoric, }, 242 { "mass storage", PCI_CLASS_MASS_STORAGE, 243 pci_subclass_mass_storage, }, 244 { "network", PCI_CLASS_NETWORK, 245 pci_subclass_network, }, 246 { "display", PCI_CLASS_DISPLAY, 247 pci_subclass_display, }, 248 { "multimedia", PCI_CLASS_MULTIMEDIA, 249 pci_subclass_multimedia, }, 250 { "memory", PCI_CLASS_MEMORY, 251 pci_subclass_memory, }, 252 { "bridge", PCI_CLASS_BRIDGE, 253 pci_subclass_bridge, }, 254 { "communications", PCI_CLASS_COMMUNICATIONS, 255 pci_subclass_communications, }, 256 { "system", PCI_CLASS_SYSTEM, 257 pci_subclass_system, }, 258 { "input", PCI_CLASS_INPUT, 259 pci_subclass_input, }, 260 { "dock", PCI_CLASS_DOCK, 261 pci_subclass_dock, }, 262 { "processor", PCI_CLASS_PROCESSOR, 263 pci_subclass_processor, }, 264 { "serial bus", PCI_CLASS_SERIALBUS, 265 pci_subclass_serialbus, }, 266 { "wireless", PCI_CLASS_WIRELESS, 267 pci_subclass_wireless, }, 268 { "I2O", PCI_CLASS_I2O, 269 pci_subclass_i2o, }, 270 { "satellite comm", PCI_CLASS_SATCOM, 271 pci_subclass_satcom, }, 272 { "crypto", PCI_CLASS_CRYPTO, 273 pci_subclass_crypto, }, 274 { "DASP", PCI_CLASS_DASP, 275 pci_subclass_dasp, }, 276 { "undefined", PCI_CLASS_UNDEFINED, 277 0, }, 278 { 0 }, 279 }; 280 281 #ifdef PCIVERBOSE 282 /* 283 * Descriptions of of known vendors and devices ("products"). 284 */ 285 struct pci_knowndev { 286 pci_vendor_id_t vendor; 287 pci_product_id_t product; 288 int flags; 289 char *vendorname, *productname; 290 }; 291 #define PCI_KNOWNDEV_NOPROD 0x01 /* match on vendor only */ 292 293 #include <dev/pci/pcidevs_data.h> 294 #endif /* PCIVERBOSE */ 295 296 char * 297 pci_findvendor(pcireg_t id_reg) 298 { 299 #ifdef PCIVERBOSE 300 pci_vendor_id_t vendor = PCI_VENDOR(id_reg); 301 const struct pci_knowndev *kdp; 302 303 kdp = pci_knowndevs; 304 while (kdp->vendorname != NULL) { /* all have vendor name */ 305 if (kdp->vendor == vendor) 306 break; 307 kdp++; 308 } 309 return (kdp->vendorname); 310 #else 311 return (NULL); 312 #endif 313 } 314 315 void 316 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp) 317 { 318 pci_vendor_id_t vendor; 319 pci_product_id_t product; 320 pci_class_t class; 321 pci_subclass_t subclass; 322 pci_interface_t interface; 323 pci_revision_t revision; 324 char *vendor_namep, *product_namep; 325 const struct pci_class *classp, *subclassp; 326 #ifdef PCIVERBOSE 327 const struct pci_knowndev *kdp; 328 const char *unmatched = "unknown "; 329 #else 330 const char *unmatched = ""; 331 #endif 332 333 vendor = PCI_VENDOR(id_reg); 334 product = PCI_PRODUCT(id_reg); 335 336 class = PCI_CLASS(class_reg); 337 subclass = PCI_SUBCLASS(class_reg); 338 interface = PCI_INTERFACE(class_reg); 339 revision = PCI_REVISION(class_reg); 340 341 #ifdef PCIVERBOSE 342 kdp = pci_knowndevs; 343 while (kdp->vendorname != NULL) { /* all have vendor name */ 344 if (kdp->vendor == vendor && (kdp->product == product || 345 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) 346 break; 347 kdp++; 348 } 349 if (kdp->vendorname == NULL) 350 vendor_namep = product_namep = NULL; 351 else { 352 vendor_namep = kdp->vendorname; 353 product_namep = (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0 ? 354 kdp->productname : NULL; 355 } 356 #else /* PCIVERBOSE */ 357 vendor_namep = product_namep = NULL; 358 #endif /* PCIVERBOSE */ 359 360 classp = pci_class; 361 while (classp->name != NULL) { 362 if (class == classp->val) 363 break; 364 classp++; 365 } 366 367 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 368 while (subclassp && subclassp->name != NULL) { 369 if (subclass == subclassp->val) 370 break; 371 subclassp++; 372 } 373 374 if (vendor_namep == NULL) 375 cp += sprintf(cp, "%svendor 0x%04x product 0x%04x", 376 unmatched, vendor, product); 377 else if (product_namep != NULL) 378 cp += sprintf(cp, "%s %s", vendor_namep, product_namep); 379 else 380 cp += sprintf(cp, "%s product 0x%04x", 381 vendor_namep, product); 382 if (showclass) { 383 cp += sprintf(cp, " ("); 384 if (classp->name == NULL) 385 cp += sprintf(cp, "class 0x%02x, subclass 0x%02x", 386 class, subclass); 387 else { 388 if (subclassp == NULL || subclassp->name == NULL) 389 cp += sprintf(cp, 390 "%s subclass 0x%02x", 391 classp->name, subclass); 392 else 393 cp += sprintf(cp, "%s %s", 394 subclassp->name, classp->name); 395 } 396 if (interface != 0) 397 cp += sprintf(cp, ", interface 0x%02x", interface); 398 if (revision != 0) 399 cp += sprintf(cp, ", revision 0x%02x", revision); 400 cp += sprintf(cp, ")"); 401 } 402 } 403 404 /* 405 * Print out most of the PCI configuration registers. Typically used 406 * in a device attach routine like this: 407 * 408 * #ifdef MYDEV_DEBUG 409 * printf("%s: ", sc->sc_dev.dv_xname); 410 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 411 * #endif 412 */ 413 414 #define i2o(i) ((i) * 4) 415 #define o2i(o) ((o) / 4) 416 #define onoff(str, bit) \ 417 printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off"); 418 419 static void 420 pci_conf_print_common( 421 #ifdef _KERNEL 422 pci_chipset_tag_t pc, pcitag_t tag, 423 #endif 424 const pcireg_t *regs) 425 { 426 #ifdef PCIVERBOSE 427 const struct pci_knowndev *kdp; 428 #endif 429 const struct pci_class *classp, *subclassp; 430 pcireg_t rval; 431 432 rval = regs[o2i(PCI_ID_REG)]; 433 #ifndef PCIVERBOSE 434 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 435 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 436 #else 437 for (kdp = pci_knowndevs; kdp->vendorname != NULL; kdp++) { 438 if (kdp->vendor == PCI_VENDOR(rval) && 439 (kdp->product == PCI_PRODUCT(rval) || 440 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) { 441 break; 442 } 443 } 444 if (kdp->vendorname != NULL) 445 printf(" Vendor Name: %s (0x%04x)\n", kdp->vendorname, 446 PCI_VENDOR(rval)); 447 else 448 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 449 if (kdp->productname != NULL && (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0) 450 printf(" Device Name: %s (0x%04x)\n", kdp->productname, 451 PCI_PRODUCT(rval)); 452 else 453 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 454 #endif /* PCIVERBOSE */ 455 456 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 457 458 printf(" Command register: 0x%04x\n", rval & 0xffff); 459 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 460 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 461 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 462 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 463 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 464 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 465 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 466 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 467 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 468 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 469 470 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 471 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 472 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 473 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 474 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 475 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 476 477 printf(" DEVSEL timing: "); 478 switch (rval & PCI_STATUS_DEVSEL_MASK) { 479 case PCI_STATUS_DEVSEL_FAST: 480 printf("fast"); 481 break; 482 case PCI_STATUS_DEVSEL_MEDIUM: 483 printf("medium"); 484 break; 485 case PCI_STATUS_DEVSEL_SLOW: 486 printf("slow"); 487 break; 488 default: 489 printf("unknown/reserved"); /* XXX */ 490 break; 491 } 492 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 493 494 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 495 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 496 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 497 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 498 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 499 500 rval = regs[o2i(PCI_CLASS_REG)]; 501 for (classp = pci_class; classp->name != NULL; classp++) { 502 if (PCI_CLASS(rval) == classp->val) 503 break; 504 } 505 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 506 while (subclassp && subclassp->name != NULL) { 507 if (PCI_SUBCLASS(rval) == subclassp->val) 508 break; 509 subclassp++; 510 } 511 if (classp->name != NULL) { 512 printf(" Class Name: %s (0x%02x)\n", classp->name, 513 PCI_CLASS(rval)); 514 if (subclassp != NULL && subclassp->name != NULL) 515 printf(" Subclass Name: %s (0x%02x)\n", 516 subclassp->name, PCI_SUBCLASS(rval)); 517 else 518 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 519 } else { 520 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 521 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 522 } 523 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 524 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 525 526 rval = regs[o2i(PCI_BHLC_REG)]; 527 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 528 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 529 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 530 PCI_HDRTYPE(rval)); 531 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 532 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 533 } 534 535 static int 536 pci_conf_print_bar( 537 #ifdef _KERNEL 538 pci_chipset_tag_t pc, pcitag_t tag, 539 #endif 540 const pcireg_t *regs, int reg, const char *name 541 #ifdef _KERNEL 542 , int sizebar 543 #endif 544 ) 545 { 546 int width; 547 pcireg_t rval, rval64h; 548 #ifdef _KERNEL 549 int s; 550 pcireg_t mask, mask64h; 551 #endif 552 553 width = 4; 554 555 /* 556 * Section 6.2.5.1, `Address Maps', tells us that: 557 * 558 * 1) The builtin software should have already mapped the 559 * device in a reasonable way. 560 * 561 * 2) A device which wants 2^n bytes of memory will hardwire 562 * the bottom n bits of the address to 0. As recommended, 563 * we write all 1s and see what we get back. 564 */ 565 566 rval = regs[o2i(reg)]; 567 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 568 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 569 rval64h = regs[o2i(reg + 4)]; 570 width = 8; 571 } else 572 rval64h = 0; 573 574 #ifdef _KERNEL 575 /* XXX don't size unknown memory type? */ 576 if (rval != 0 && sizebar) { 577 /* 578 * The following sequence seems to make some devices 579 * (e.g. host bus bridges, which don't normally 580 * have their space mapped) very unhappy, to 581 * the point of crashing the system. 582 * 583 * Therefore, if the mapping register is zero to 584 * start out with, don't bother trying. 585 */ 586 s = splhigh(); 587 pci_conf_write(pc, tag, reg, 0xffffffff); 588 mask = pci_conf_read(pc, tag, reg); 589 pci_conf_write(pc, tag, reg, rval); 590 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 591 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 592 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 593 mask64h = pci_conf_read(pc, tag, reg + 4); 594 pci_conf_write(pc, tag, reg + 4, rval64h); 595 } 596 splx(s); 597 } else 598 mask = 0; 599 #endif /* _KERNEL */ 600 601 printf(" Base address register at 0x%02x", reg); 602 if (name) 603 printf(" (%s)", name); 604 printf("\n "); 605 if (rval == 0) { 606 printf("not implemented(?)\n"); 607 return width; 608 } 609 printf("type: "); 610 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 611 const char *type, *prefetch; 612 613 switch (PCI_MAPREG_MEM_TYPE(rval)) { 614 case PCI_MAPREG_MEM_TYPE_32BIT: 615 type = "32-bit"; 616 break; 617 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 618 type = "32-bit-1M"; 619 break; 620 case PCI_MAPREG_MEM_TYPE_64BIT: 621 type = "64-bit"; 622 break; 623 default: 624 type = "unknown (XXX)"; 625 break; 626 } 627 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 628 prefetch = ""; 629 else 630 prefetch = "non"; 631 printf("%s %sprefetchable memory\n", type, prefetch); 632 switch (PCI_MAPREG_MEM_TYPE(rval)) { 633 case PCI_MAPREG_MEM_TYPE_64BIT: 634 printf(" base: 0x%016llx, ", 635 PCI_MAPREG_MEM64_ADDR( 636 ((((long long) rval64h) << 32) | rval))); 637 #ifdef _KERNEL 638 if (sizebar) 639 printf("size: 0x%016llx", 640 PCI_MAPREG_MEM64_SIZE( 641 ((((long long) mask64h) << 32) | mask))); 642 else 643 #endif /* _KERNEL */ 644 printf("not sized"); 645 printf("\n"); 646 break; 647 case PCI_MAPREG_MEM_TYPE_32BIT: 648 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 649 default: 650 printf(" base: 0x%08x, ", 651 PCI_MAPREG_MEM_ADDR(rval)); 652 #ifdef _KERNEL 653 if (sizebar) 654 printf("size: 0x%08x", 655 PCI_MAPREG_MEM_SIZE(mask)); 656 else 657 #endif /* _KERNEL */ 658 printf("not sized"); 659 printf("\n"); 660 break; 661 } 662 } else { 663 #ifdef _KERNEL 664 if (sizebar) 665 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 666 #endif /* _KERNEL */ 667 printf("i/o\n"); 668 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 669 #ifdef _KERNEL 670 if (sizebar) 671 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 672 else 673 #endif /* _KERNEL */ 674 printf("not sized"); 675 printf("\n"); 676 } 677 678 return width; 679 } 680 681 static void 682 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 683 { 684 int off, needaddr, neednl; 685 686 needaddr = 1; 687 neednl = 0; 688 for (off = first; off < pastlast; off += 4) { 689 if ((off % 16) == 0 || needaddr) { 690 printf(" 0x%02x:", off); 691 needaddr = 0; 692 } 693 printf(" 0x%08x", regs[o2i(off)]); 694 neednl = 1; 695 if ((off % 16) == 12) { 696 printf("\n"); 697 neednl = 0; 698 } 699 } 700 if (neednl) 701 printf("\n"); 702 } 703 704 static void 705 pci_conf_print_type0( 706 #ifdef _KERNEL 707 pci_chipset_tag_t pc, pcitag_t tag, 708 #endif 709 const pcireg_t *regs 710 #ifdef _KERNEL 711 , int sizebars 712 #endif 713 ) 714 { 715 int off, width; 716 pcireg_t rval; 717 718 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 719 #ifdef _KERNEL 720 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 721 #else 722 width = pci_conf_print_bar(regs, off, NULL); 723 #endif 724 } 725 726 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 727 728 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 729 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 730 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 731 732 /* XXX */ 733 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 734 735 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 736 printf(" Capability list pointer: 0x%02x\n", 737 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 738 else 739 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 740 741 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 742 743 rval = regs[o2i(PCI_INTERRUPT_REG)]; 744 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 745 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 746 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 747 switch (PCI_INTERRUPT_PIN(rval)) { 748 case PCI_INTERRUPT_PIN_NONE: 749 printf("(none)"); 750 break; 751 case PCI_INTERRUPT_PIN_A: 752 printf("(pin A)"); 753 break; 754 case PCI_INTERRUPT_PIN_B: 755 printf("(pin B)"); 756 break; 757 case PCI_INTERRUPT_PIN_C: 758 printf("(pin C)"); 759 break; 760 case PCI_INTERRUPT_PIN_D: 761 printf("(pin D)"); 762 break; 763 default: 764 printf("(? ? ?)"); 765 break; 766 } 767 printf("\n"); 768 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 769 770 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) { 771 for (off = PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]); 772 off != 0; 773 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 774 rval = regs[o2i(off)]; 775 printf(" Capability register at 0x%02x\n", off); 776 777 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 778 switch (PCI_CAPLIST_CAP(rval)) { 779 case PCI_CAP_RESERVED0: 780 printf("reserved"); 781 break; 782 case PCI_CAP_PWRMGMT: 783 printf("Power Management, rev. %d.0", 784 (rval >> 0) & 0x07); /* XXX not clear */ 785 break; 786 case PCI_CAP_AGP: 787 printf("AGP, rev. %d.%d", 788 (rval >> 24) & 0x0f, 789 (rval >> 20) & 0x0f); 790 break; 791 case PCI_CAP_VPD: 792 printf("VPD"); 793 break; 794 case PCI_CAP_SLOTID: 795 printf("SlotID"); 796 break; 797 case PCI_CAP_MBI: 798 printf("MBI"); 799 break; 800 case PCI_CAP_CPCI_HOTSWAP: 801 printf("CompactPCI Hot-swapping"); 802 break; 803 case PCI_CAP_PCIX: 804 printf("PCI-X"); 805 break; 806 case PCI_CAP_LDT: 807 printf("LDT"); 808 break; 809 case PCI_CAP_VENDSPEC: 810 printf("Vendor-specific"); 811 break; 812 case PCI_CAP_DEBUGPORT: 813 printf("Debug Port"); 814 break; 815 case PCI_CAP_CPCI_RSRCCTL: 816 printf("CompactPCI Resource Control"); 817 break; 818 case PCI_CAP_HOTPLUG: 819 printf("Hot-Plug"); 820 break; 821 default: 822 printf("unknown"); 823 } 824 printf(")\n"); 825 } 826 } 827 } 828 829 static void 830 pci_conf_print_type1( 831 #ifdef _KERNEL 832 pci_chipset_tag_t pc, pcitag_t tag, 833 #endif 834 const pcireg_t *regs 835 #ifdef _KERNEL 836 , int sizebars 837 #endif 838 ) 839 { 840 int off, width; 841 pcireg_t rval; 842 843 /* 844 * XXX these need to be printed in more detail, need to be 845 * XXX checked against specs/docs, etc. 846 * 847 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 848 * Bridge chip documentation, and may not be correct with 849 * respect to various standards. (XXX) 850 */ 851 852 for (off = 0x10; off < 0x18; off += width) { 853 #ifdef _KERNEL 854 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 855 #else 856 width = pci_conf_print_bar(regs, off, NULL); 857 #endif 858 } 859 860 printf(" Primary bus number: 0x%02x\n", 861 (regs[o2i(0x18)] >> 0) & 0xff); 862 printf(" Secondary bus number: 0x%02x\n", 863 (regs[o2i(0x18)] >> 8) & 0xff); 864 printf(" Subordinate bus number: 0x%02x\n", 865 (regs[o2i(0x18)] >> 16) & 0xff); 866 printf(" Secondary bus latency timer: 0x%02x\n", 867 (regs[o2i(0x18)] >> 24) & 0xff); 868 869 rval = (regs[o2i(0x1c)] >> 16) & 0xffff; 870 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 871 onoff("66 MHz capable", 0x0020); 872 onoff("User Definable Features (UDF) support", 0x0040); 873 onoff("Fast back-to-back capable", 0x0080); 874 onoff("Data parity error detected", 0x0100); 875 876 printf(" DEVSEL timing: "); 877 switch (rval & 0x0600) { 878 case 0x0000: 879 printf("fast"); 880 break; 881 case 0x0200: 882 printf("medium"); 883 break; 884 case 0x0400: 885 printf("slow"); 886 break; 887 default: 888 printf("unknown/reserved"); /* XXX */ 889 break; 890 } 891 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 892 893 onoff("Signaled Target Abort", 0x0800); 894 onoff("Received Target Abort", 0x1000); 895 onoff("Received Master Abort", 0x2000); 896 onoff("System Error", 0x4000); 897 onoff("Parity Error", 0x8000); 898 899 /* XXX Print more prettily */ 900 printf(" I/O region:\n"); 901 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 902 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 903 printf(" base upper 16 bits register: 0x%04x\n", 904 (regs[o2i(0x30)] >> 0) & 0xffff); 905 printf(" limit upper 16 bits register: 0x%04x\n", 906 (regs[o2i(0x30)] >> 16) & 0xffff); 907 908 /* XXX Print more prettily */ 909 printf(" Memory region:\n"); 910 printf(" base register: 0x%04x\n", 911 (regs[o2i(0x20)] >> 0) & 0xffff); 912 printf(" limit register: 0x%04x\n", 913 (regs[o2i(0x20)] >> 16) & 0xffff); 914 915 /* XXX Print more prettily */ 916 printf(" Prefetchable memory region:\n"); 917 printf(" base register: 0x%04x\n", 918 (regs[o2i(0x24)] >> 0) & 0xffff); 919 printf(" limit register: 0x%04x\n", 920 (regs[o2i(0x24)] >> 16) & 0xffff); 921 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 922 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 923 924 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 925 /* XXX */ 926 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 927 928 printf(" Interrupt line: 0x%02x\n", 929 (regs[o2i(0x3c)] >> 0) & 0xff); 930 printf(" Interrupt pin: 0x%02x ", 931 (regs[o2i(0x3c)] >> 8) & 0xff); 932 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 933 case PCI_INTERRUPT_PIN_NONE: 934 printf("(none)"); 935 break; 936 case PCI_INTERRUPT_PIN_A: 937 printf("(pin A)"); 938 break; 939 case PCI_INTERRUPT_PIN_B: 940 printf("(pin B)"); 941 break; 942 case PCI_INTERRUPT_PIN_C: 943 printf("(pin C)"); 944 break; 945 case PCI_INTERRUPT_PIN_D: 946 printf("(pin D)"); 947 break; 948 default: 949 printf("(? ? ?)"); 950 break; 951 } 952 printf("\n"); 953 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 954 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 955 onoff("Parity error response", 0x0001); 956 onoff("Secondary SERR forwarding", 0x0002); 957 onoff("ISA enable", 0x0004); 958 onoff("VGA enable", 0x0008); 959 onoff("Master abort reporting", 0x0020); 960 onoff("Secondary bus reset", 0x0040); 961 onoff("Fast back-to-back capable", 0x0080); 962 } 963 964 static void 965 pci_conf_print_type2( 966 #ifdef _KERNEL 967 pci_chipset_tag_t pc, pcitag_t tag, 968 #endif 969 const pcireg_t *regs 970 #ifdef _KERNEL 971 , int sizebars 972 #endif 973 ) 974 { 975 pcireg_t rval; 976 977 /* 978 * XXX these need to be printed in more detail, need to be 979 * XXX checked against specs/docs, etc. 980 * 981 * This layout was cribbed from the TI PCI1130 PCI-to-CardBus 982 * controller chip documentation, and may not be correct with 983 * respect to various standards. (XXX) 984 */ 985 986 #ifdef _KERNEL 987 pci_conf_print_bar(pc, tag, regs, 0x10, 988 "CardBus socket/ExCA registers", sizebars); 989 #else 990 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 991 #endif 992 993 printf(" Reserved @ 0x14: 0x%04x\n", 994 (regs[o2i(0x14)] >> 0) & 0xffff); 995 rval = (regs[o2i(0x14)] >> 16) & 0xffff; 996 printf(" Secondary status register: 0x%04x\n", rval); 997 onoff("66 MHz capable", 0x0020); 998 onoff("User Definable Features (UDF) support", 0x0040); 999 onoff("Fast back-to-back capable", 0x0080); 1000 onoff("Data parity error detection", 0x0100); 1001 1002 printf(" DEVSEL timing: "); 1003 switch (rval & 0x0600) { 1004 case 0x0000: 1005 printf("fast"); 1006 break; 1007 case 0x0200: 1008 printf("medium"); 1009 break; 1010 case 0x0400: 1011 printf("slow"); 1012 break; 1013 default: 1014 printf("unknown/reserved"); /* XXX */ 1015 break; 1016 } 1017 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 1018 onoff("PCI target aborts terminate CardBus bus master transactions", 1019 0x0800); 1020 onoff("CardBus target aborts terminate PCI bus master transactions", 1021 0x1000); 1022 onoff("Bus initiator aborts terminate initiator transactions", 1023 0x2000); 1024 onoff("System error", 0x4000); 1025 onoff("Parity error", 0x8000); 1026 1027 printf(" PCI bus number: 0x%02x\n", 1028 (regs[o2i(0x18)] >> 0) & 0xff); 1029 printf(" CardBus bus number: 0x%02x\n", 1030 (regs[o2i(0x18)] >> 8) & 0xff); 1031 printf(" Subordinate bus number: 0x%02x\n", 1032 (regs[o2i(0x18)] >> 16) & 0xff); 1033 printf(" CardBus latency timer: 0x%02x\n", 1034 (regs[o2i(0x18)] >> 24) & 0xff); 1035 1036 /* XXX Print more prettily */ 1037 printf(" CardBus memory region 0:\n"); 1038 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1039 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1040 printf(" CardBus memory region 1:\n"); 1041 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1042 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1043 printf(" CardBus I/O region 0:\n"); 1044 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1045 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1046 printf(" CardBus I/O region 1:\n"); 1047 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1048 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1049 1050 printf(" Interrupt line: 0x%02x\n", 1051 (regs[o2i(0x3c)] >> 0) & 0xff); 1052 printf(" Interrupt pin: 0x%02x ", 1053 (regs[o2i(0x3c)] >> 8) & 0xff); 1054 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1055 case PCI_INTERRUPT_PIN_NONE: 1056 printf("(none)"); 1057 break; 1058 case PCI_INTERRUPT_PIN_A: 1059 printf("(pin A)"); 1060 break; 1061 case PCI_INTERRUPT_PIN_B: 1062 printf("(pin B)"); 1063 break; 1064 case PCI_INTERRUPT_PIN_C: 1065 printf("(pin C)"); 1066 break; 1067 case PCI_INTERRUPT_PIN_D: 1068 printf("(pin D)"); 1069 break; 1070 default: 1071 printf("(? ? ?)"); 1072 break; 1073 } 1074 printf("\n"); 1075 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1076 printf(" Bridge control register: 0x%04x\n", rval); 1077 onoff("Parity error response", 0x0001); 1078 onoff("CardBus SERR forwarding", 0x0002); 1079 onoff("ISA enable", 0x0004); 1080 onoff("VGA enable", 0x0008); 1081 onoff("CardBus master abort reporting", 0x0020); 1082 onoff("CardBus reset", 0x0040); 1083 onoff("Functional interrupts routed by ExCA registers", 0x0080); 1084 onoff("Memory window 0 prefetchable", 0x0100); 1085 onoff("Memory window 1 prefetchable", 0x0200); 1086 onoff("Write posting enable", 0x0400); 1087 1088 rval = regs[o2i(0x40)]; 1089 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1090 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1091 1092 #ifdef _KERNEL 1093 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1094 sizebars); 1095 #else 1096 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 1097 #endif 1098 } 1099 1100 void 1101 pci_conf_print( 1102 #ifdef _KERNEL 1103 pci_chipset_tag_t pc, pcitag_t tag, 1104 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 1105 #else 1106 int pcifd, u_int bus, u_int dev, u_int func 1107 #endif 1108 ) 1109 { 1110 pcireg_t regs[o2i(256)]; 1111 int off, endoff, hdrtype; 1112 const char *typename; 1113 #ifdef _KERNEL 1114 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1115 int sizebars; 1116 #else 1117 void (*typeprintfn)(const pcireg_t *); 1118 #endif 1119 1120 printf("PCI configuration registers:\n"); 1121 1122 for (off = 0; off < 256; off += 4) { 1123 #ifdef _KERNEL 1124 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1125 #else 1126 if (pcibus_conf_read(pcifd, bus, dev, func, off, 1127 ®s[o2i(off)]) == -1) 1128 regs[o2i(off)] = 0; 1129 #endif 1130 } 1131 1132 #ifdef _KERNEL 1133 sizebars = 1; 1134 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1135 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1136 sizebars = 0; 1137 #endif 1138 1139 /* common header */ 1140 printf(" Common header:\n"); 1141 pci_conf_print_regs(regs, 0, 16); 1142 1143 printf("\n"); 1144 #ifdef _KERNEL 1145 pci_conf_print_common(pc, tag, regs); 1146 #else 1147 pci_conf_print_common(regs); 1148 #endif 1149 printf("\n"); 1150 1151 /* type-dependent header */ 1152 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1153 switch (hdrtype) { /* XXX make a table, eventually */ 1154 case 0: 1155 /* Standard device header */ 1156 typename = "\"normal\" device"; 1157 typeprintfn = &pci_conf_print_type0; 1158 endoff = 64; 1159 break; 1160 case 1: 1161 /* PCI-PCI bridge header */ 1162 typename = "PCI-PCI bridge"; 1163 typeprintfn = &pci_conf_print_type1; 1164 endoff = 64; 1165 break; 1166 case 2: 1167 /* PCI-CardBus bridge header */ 1168 typename = "PCI-CardBus bridge"; 1169 typeprintfn = &pci_conf_print_type2; 1170 endoff = 72; 1171 break; 1172 default: 1173 typename = NULL; 1174 typeprintfn = 0; 1175 endoff = 64; 1176 break; 1177 } 1178 printf(" Type %d ", hdrtype); 1179 if (typename != NULL) 1180 printf("(%s) ", typename); 1181 printf("header:\n"); 1182 pci_conf_print_regs(regs, 16, endoff); 1183 printf("\n"); 1184 if (typeprintfn) { 1185 #ifdef _KERNEL 1186 (*typeprintfn)(pc, tag, regs, sizebars); 1187 #else 1188 (*typeprintfn)(regs); 1189 #endif 1190 } else 1191 printf(" Don't know how to pretty-print type %d header.\n", 1192 hdrtype); 1193 printf("\n"); 1194 1195 #ifdef _KERNEL 1196 /* device-dependent header */ 1197 printf(" Device-dependent header:\n"); 1198 pci_conf_print_regs(regs, endoff, 256); 1199 printf("\n"); 1200 if (printfn) 1201 (*printfn)(pc, tag, regs); 1202 else 1203 printf(" Don't know how to pretty-print device-dependent header.\n"); 1204 printf("\n"); 1205 #endif /* _KERNEL */ 1206 } 1207
Indexes created Fri Sep 26 08:10:20 GMT 2025