pci_subr.c revision 1.46
1 /* $NetBSD: pci_subr.c,v 1.46 2001/11/13 03:12:44 enami Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #ifdef _KERNEL_OPT 43 #include "opt_pci.h" 44 #endif 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 49 #ifdef _KERNEL 50 #include <machine/intr.h> 51 #else 52 #include <pci.h> 53 #include <stdio.h> 54 #endif 55 56 #include <dev/pci/pcireg.h> 57 #ifdef _KERNEL 58 #include <dev/pci/pcivar.h> 59 #endif 60 #ifdef PCIVERBOSE 61 #include <dev/pci/pcidevs.h> 62 #endif 63 64 /* 65 * Descriptions of known PCI classes and subclasses. 66 * 67 * Subclasses are described in the same way as classes, but have a 68 * NULL subclass pointer. 69 */ 70 struct pci_class { 71 const char *name; 72 int val; /* as wide as pci_{,sub}class_t */ 73 const struct pci_class *subclasses; 74 }; 75 76 const struct pci_class pci_subclass_prehistoric[] = { 77 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, }, 78 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, }, 79 { 0 } 80 }; 81 82 const struct pci_class pci_subclass_mass_storage[] = { 83 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, }, 84 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, }, 85 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, }, 86 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, }, 87 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, }, 88 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, }, 89 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, }, 90 { 0 }, 91 }; 92 93 const struct pci_class pci_subclass_network[] = { 94 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, }, 95 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, }, 96 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, }, 97 { "ATM", PCI_SUBCLASS_NETWORK_ATM, }, 98 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, }, 99 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, }, 100 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, }, 101 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, }, 102 { 0 }, 103 }; 104 105 const struct pci_class pci_subclass_display[] = { 106 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, }, 107 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, }, 108 { "3D", PCI_SUBCLASS_DISPLAY_3D, }, 109 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, }, 110 { 0 }, 111 }; 112 113 const struct pci_class pci_subclass_multimedia[] = { 114 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, }, 115 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, }, 116 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, }, 117 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, }, 118 { 0 }, 119 }; 120 121 const struct pci_class pci_subclass_memory[] = { 122 { "RAM", PCI_SUBCLASS_MEMORY_RAM, }, 123 { "flash", PCI_SUBCLASS_MEMORY_FLASH, }, 124 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, }, 125 { 0 }, 126 }; 127 128 const struct pci_class pci_subclass_bridge[] = { 129 { "host", PCI_SUBCLASS_BRIDGE_HOST, }, 130 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, }, 131 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, }, 132 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, }, 133 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, }, 134 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, }, 135 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, }, 136 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, }, 137 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, }, 138 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, }, 139 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, }, 140 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, }, 141 { 0 }, 142 }; 143 144 const struct pci_class pci_subclass_communications[] = { 145 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, }, 146 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, }, 147 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, }, 148 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, }, 149 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, }, 150 { 0 }, 151 }; 152 153 const struct pci_class pci_subclass_system[] = { 154 { "8259 PIC", PCI_SUBCLASS_SYSTEM_PIC, }, 155 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, }, 156 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, }, 157 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, }, 158 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_RTC, }, 159 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, }, 160 { 0 }, 161 }; 162 163 const struct pci_class pci_subclass_input[] = { 164 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, }, 165 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, }, 166 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, }, 167 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, }, 168 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, }, 169 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, }, 170 { 0 }, 171 }; 172 173 const struct pci_class pci_subclass_dock[] = { 174 { "generic", PCI_SUBCLASS_DOCK_GENERIC, }, 175 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, }, 176 { 0 }, 177 }; 178 179 const struct pci_class pci_subclass_processor[] = { 180 { "386", PCI_SUBCLASS_PROCESSOR_386, }, 181 { "486", PCI_SUBCLASS_PROCESSOR_486, }, 182 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, }, 183 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, }, 184 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, }, 185 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, }, 186 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, }, 187 { 0 }, 188 }; 189 190 const struct pci_class pci_subclass_serialbus[] = { 191 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, }, 192 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, }, 193 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, }, 194 { "USB", PCI_SUBCLASS_SERIALBUS_USB, }, 195 /* XXX Fiber Channel/_FIBRECHANNEL */ 196 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, }, 197 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, }, 198 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, }, 199 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, }, 200 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, }, 201 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, }, 202 { 0 }, 203 }; 204 205 const struct pci_class pci_subclass_wireless[] = { 206 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, }, 207 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, }, 208 { "RF", PCI_SUBCLASS_WIRELESS_RF, }, 209 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, }, 210 { 0 }, 211 }; 212 213 const struct pci_class pci_subclass_i2o[] = { 214 { "standard", PCI_SUBCLASS_I2O_STANDARD, }, 215 { 0 }, 216 }; 217 218 const struct pci_class pci_subclass_satcom[] = { 219 { "TV", PCI_SUBCLASS_SATCOM_TV, }, 220 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, }, 221 { "voice", PCI_SUBCLASS_SATCOM_VOICE, }, 222 { "data", PCI_SUBCLASS_SATCOM_DATA, }, 223 { 0 }, 224 }; 225 226 const struct pci_class pci_subclass_crypto[] = { 227 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, }, 228 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, }, 229 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, }, 230 { 0 }, 231 }; 232 233 const struct pci_class pci_subclass_dasp[] = { 234 { "DPIO", PCI_SUBCLASS_DASP_DPIO, }, 235 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, }, 236 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, }, 237 { 0 }, 238 }; 239 240 const struct pci_class pci_class[] = { 241 { "prehistoric", PCI_CLASS_PREHISTORIC, 242 pci_subclass_prehistoric, }, 243 { "mass storage", PCI_CLASS_MASS_STORAGE, 244 pci_subclass_mass_storage, }, 245 { "network", PCI_CLASS_NETWORK, 246 pci_subclass_network, }, 247 { "display", PCI_CLASS_DISPLAY, 248 pci_subclass_display, }, 249 { "multimedia", PCI_CLASS_MULTIMEDIA, 250 pci_subclass_multimedia, }, 251 { "memory", PCI_CLASS_MEMORY, 252 pci_subclass_memory, }, 253 { "bridge", PCI_CLASS_BRIDGE, 254 pci_subclass_bridge, }, 255 { "communications", PCI_CLASS_COMMUNICATIONS, 256 pci_subclass_communications, }, 257 { "system", PCI_CLASS_SYSTEM, 258 pci_subclass_system, }, 259 { "input", PCI_CLASS_INPUT, 260 pci_subclass_input, }, 261 { "dock", PCI_CLASS_DOCK, 262 pci_subclass_dock, }, 263 { "processor", PCI_CLASS_PROCESSOR, 264 pci_subclass_processor, }, 265 { "serial bus", PCI_CLASS_SERIALBUS, 266 pci_subclass_serialbus, }, 267 { "wireless", PCI_CLASS_WIRELESS, 268 pci_subclass_wireless, }, 269 { "I2O", PCI_CLASS_I2O, 270 pci_subclass_i2o, }, 271 { "satellite comm", PCI_CLASS_SATCOM, 272 pci_subclass_satcom, }, 273 { "crypto", PCI_CLASS_CRYPTO, 274 pci_subclass_crypto, }, 275 { "DASP", PCI_CLASS_DASP, 276 pci_subclass_dasp, }, 277 { "undefined", PCI_CLASS_UNDEFINED, 278 0, }, 279 { 0 }, 280 }; 281 282 #ifdef PCIVERBOSE 283 /* 284 * Descriptions of of known vendors and devices ("products"). 285 */ 286 struct pci_knowndev { 287 pci_vendor_id_t vendor; 288 pci_product_id_t product; 289 int flags; 290 char *vendorname, *productname; 291 }; 292 #define PCI_KNOWNDEV_NOPROD 0x01 /* match on vendor only */ 293 294 #include <dev/pci/pcidevs_data.h> 295 #endif /* PCIVERBOSE */ 296 297 char * 298 pci_findvendor(pcireg_t id_reg) 299 { 300 #ifdef PCIVERBOSE 301 pci_vendor_id_t vendor = PCI_VENDOR(id_reg); 302 const struct pci_knowndev *kdp; 303 304 kdp = pci_knowndevs; 305 while (kdp->vendorname != NULL) { /* all have vendor name */ 306 if (kdp->vendor == vendor) 307 break; 308 kdp++; 309 } 310 return (kdp->vendorname); 311 #else 312 return (NULL); 313 #endif 314 } 315 316 void 317 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp) 318 { 319 pci_vendor_id_t vendor; 320 pci_product_id_t product; 321 pci_class_t class; 322 pci_subclass_t subclass; 323 pci_interface_t interface; 324 pci_revision_t revision; 325 char *vendor_namep, *product_namep; 326 const struct pci_class *classp, *subclassp; 327 #ifdef PCIVERBOSE 328 const struct pci_knowndev *kdp; 329 const char *unmatched = "unknown "; 330 #else 331 const char *unmatched = ""; 332 #endif 333 334 vendor = PCI_VENDOR(id_reg); 335 product = PCI_PRODUCT(id_reg); 336 337 class = PCI_CLASS(class_reg); 338 subclass = PCI_SUBCLASS(class_reg); 339 interface = PCI_INTERFACE(class_reg); 340 revision = PCI_REVISION(class_reg); 341 342 #ifdef PCIVERBOSE 343 kdp = pci_knowndevs; 344 while (kdp->vendorname != NULL) { /* all have vendor name */ 345 if (kdp->vendor == vendor && (kdp->product == product || 346 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) 347 break; 348 kdp++; 349 } 350 if (kdp->vendorname == NULL) 351 vendor_namep = product_namep = NULL; 352 else { 353 vendor_namep = kdp->vendorname; 354 product_namep = (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0 ? 355 kdp->productname : NULL; 356 } 357 #else /* PCIVERBOSE */ 358 vendor_namep = product_namep = NULL; 359 #endif /* PCIVERBOSE */ 360 361 classp = pci_class; 362 while (classp->name != NULL) { 363 if (class == classp->val) 364 break; 365 classp++; 366 } 367 368 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 369 while (subclassp && subclassp->name != NULL) { 370 if (subclass == subclassp->val) 371 break; 372 subclassp++; 373 } 374 375 if (vendor_namep == NULL) 376 cp += sprintf(cp, "%svendor 0x%04x product 0x%04x", 377 unmatched, vendor, product); 378 else if (product_namep != NULL) 379 cp += sprintf(cp, "%s %s", vendor_namep, product_namep); 380 else 381 cp += sprintf(cp, "%s product 0x%04x", 382 vendor_namep, product); 383 if (showclass) { 384 cp += sprintf(cp, " ("); 385 if (classp->name == NULL) 386 cp += sprintf(cp, "class 0x%02x, subclass 0x%02x", 387 class, subclass); 388 else { 389 if (subclassp == NULL || subclassp->name == NULL) 390 cp += sprintf(cp, 391 "%s subclass 0x%02x", 392 classp->name, subclass); 393 else 394 cp += sprintf(cp, "%s %s", 395 subclassp->name, classp->name); 396 } 397 if (interface != 0) 398 cp += sprintf(cp, ", interface 0x%02x", interface); 399 if (revision != 0) 400 cp += sprintf(cp, ", revision 0x%02x", revision); 401 cp += sprintf(cp, ")"); 402 } 403 } 404 405 /* 406 * Print out most of the PCI configuration registers. Typically used 407 * in a device attach routine like this: 408 * 409 * #ifdef MYDEV_DEBUG 410 * printf("%s: ", sc->sc_dev.dv_xname); 411 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 412 * #endif 413 */ 414 415 #define i2o(i) ((i) * 4) 416 #define o2i(o) ((o) / 4) 417 #define onoff(str, bit) \ 418 printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off"); 419 420 static void 421 pci_conf_print_common( 422 #ifdef _KERNEL 423 pci_chipset_tag_t pc, pcitag_t tag, 424 #endif 425 const pcireg_t *regs) 426 { 427 #ifdef PCIVERBOSE 428 const struct pci_knowndev *kdp; 429 #endif 430 const struct pci_class *classp, *subclassp; 431 pcireg_t rval; 432 433 rval = regs[o2i(PCI_ID_REG)]; 434 #ifndef PCIVERBOSE 435 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 436 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 437 #else 438 for (kdp = pci_knowndevs; kdp->vendorname != NULL; kdp++) { 439 if (kdp->vendor == PCI_VENDOR(rval) && 440 (kdp->product == PCI_PRODUCT(rval) || 441 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) { 442 break; 443 } 444 } 445 if (kdp->vendorname != NULL) 446 printf(" Vendor Name: %s (0x%04x)\n", kdp->vendorname, 447 PCI_VENDOR(rval)); 448 else 449 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 450 if (kdp->productname != NULL && (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0) 451 printf(" Device Name: %s (0x%04x)\n", kdp->productname, 452 PCI_PRODUCT(rval)); 453 else 454 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 455 #endif /* PCIVERBOSE */ 456 457 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 458 459 printf(" Command register: 0x%04x\n", rval & 0xffff); 460 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 461 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 462 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 463 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 464 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 465 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 466 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 467 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 468 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 469 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 470 471 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 472 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 473 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 474 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 475 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 476 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 477 478 printf(" DEVSEL timing: "); 479 switch (rval & PCI_STATUS_DEVSEL_MASK) { 480 case PCI_STATUS_DEVSEL_FAST: 481 printf("fast"); 482 break; 483 case PCI_STATUS_DEVSEL_MEDIUM: 484 printf("medium"); 485 break; 486 case PCI_STATUS_DEVSEL_SLOW: 487 printf("slow"); 488 break; 489 default: 490 printf("unknown/reserved"); /* XXX */ 491 break; 492 } 493 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 494 495 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 496 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 497 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 498 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 499 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 500 501 rval = regs[o2i(PCI_CLASS_REG)]; 502 for (classp = pci_class; classp->name != NULL; classp++) { 503 if (PCI_CLASS(rval) == classp->val) 504 break; 505 } 506 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 507 while (subclassp && subclassp->name != NULL) { 508 if (PCI_SUBCLASS(rval) == subclassp->val) 509 break; 510 subclassp++; 511 } 512 if (classp->name != NULL) { 513 printf(" Class Name: %s (0x%02x)\n", classp->name, 514 PCI_CLASS(rval)); 515 if (subclassp != NULL && subclassp->name != NULL) 516 printf(" Subclass Name: %s (0x%02x)\n", 517 subclassp->name, PCI_SUBCLASS(rval)); 518 else 519 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 520 } else { 521 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 522 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 523 } 524 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 525 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 526 527 rval = regs[o2i(PCI_BHLC_REG)]; 528 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 529 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 530 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 531 PCI_HDRTYPE(rval)); 532 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 533 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 534 } 535 536 static int 537 pci_conf_print_bar( 538 #ifdef _KERNEL 539 pci_chipset_tag_t pc, pcitag_t tag, 540 #endif 541 const pcireg_t *regs, int reg, const char *name 542 #ifdef _KERNEL 543 , int sizebar 544 #endif 545 ) 546 { 547 int width; 548 pcireg_t rval, rval64h; 549 #ifdef _KERNEL 550 int s; 551 pcireg_t mask, mask64h; 552 #endif 553 554 width = 4; 555 556 /* 557 * Section 6.2.5.1, `Address Maps', tells us that: 558 * 559 * 1) The builtin software should have already mapped the 560 * device in a reasonable way. 561 * 562 * 2) A device which wants 2^n bytes of memory will hardwire 563 * the bottom n bits of the address to 0. As recommended, 564 * we write all 1s and see what we get back. 565 */ 566 567 rval = regs[o2i(reg)]; 568 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 569 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 570 rval64h = regs[o2i(reg + 4)]; 571 width = 8; 572 } else 573 rval64h = 0; 574 575 #ifdef _KERNEL 576 /* XXX don't size unknown memory type? */ 577 if (rval != 0 && sizebar) { 578 /* 579 * The following sequence seems to make some devices 580 * (e.g. host bus bridges, which don't normally 581 * have their space mapped) very unhappy, to 582 * the point of crashing the system. 583 * 584 * Therefore, if the mapping register is zero to 585 * start out with, don't bother trying. 586 */ 587 s = splhigh(); 588 pci_conf_write(pc, tag, reg, 0xffffffff); 589 mask = pci_conf_read(pc, tag, reg); 590 pci_conf_write(pc, tag, reg, rval); 591 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 592 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 593 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 594 mask64h = pci_conf_read(pc, tag, reg + 4); 595 pci_conf_write(pc, tag, reg + 4, rval64h); 596 } 597 splx(s); 598 } else 599 mask = 0; 600 #endif /* _KERNEL */ 601 602 printf(" Base address register at 0x%02x", reg); 603 if (name) 604 printf(" (%s)", name); 605 printf("\n "); 606 if (rval == 0) { 607 printf("not implemented(?)\n"); 608 return width; 609 } 610 printf("type: "); 611 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 612 const char *type, *prefetch; 613 614 switch (PCI_MAPREG_MEM_TYPE(rval)) { 615 case PCI_MAPREG_MEM_TYPE_32BIT: 616 type = "32-bit"; 617 break; 618 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 619 type = "32-bit-1M"; 620 break; 621 case PCI_MAPREG_MEM_TYPE_64BIT: 622 type = "64-bit"; 623 break; 624 default: 625 type = "unknown (XXX)"; 626 break; 627 } 628 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 629 prefetch = ""; 630 else 631 prefetch = "non"; 632 printf("%s %sprefetchable memory\n", type, prefetch); 633 switch (PCI_MAPREG_MEM_TYPE(rval)) { 634 case PCI_MAPREG_MEM_TYPE_64BIT: 635 printf(" base: 0x%016llx, ", 636 PCI_MAPREG_MEM64_ADDR( 637 ((((long long) rval64h) << 32) | rval))); 638 #ifdef _KERNEL 639 if (sizebar) 640 printf("size: 0x%016llx", 641 PCI_MAPREG_MEM64_SIZE( 642 ((((long long) mask64h) << 32) | mask))); 643 else 644 #endif /* _KERNEL */ 645 printf("not sized"); 646 printf("\n"); 647 break; 648 case PCI_MAPREG_MEM_TYPE_32BIT: 649 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 650 default: 651 printf(" base: 0x%08x, ", 652 PCI_MAPREG_MEM_ADDR(rval)); 653 #ifdef _KERNEL 654 if (sizebar) 655 printf("size: 0x%08x", 656 PCI_MAPREG_MEM_SIZE(mask)); 657 else 658 #endif /* _KERNEL */ 659 printf("not sized"); 660 printf("\n"); 661 break; 662 } 663 } else { 664 #ifdef _KERNEL 665 if (sizebar) 666 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 667 #endif /* _KERNEL */ 668 printf("i/o\n"); 669 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 670 #ifdef _KERNEL 671 if (sizebar) 672 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 673 else 674 #endif /* _KERNEL */ 675 printf("not sized"); 676 printf("\n"); 677 } 678 679 return width; 680 } 681 682 static void 683 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 684 { 685 int off, needaddr, neednl; 686 687 needaddr = 1; 688 neednl = 0; 689 for (off = first; off < pastlast; off += 4) { 690 if ((off % 16) == 0 || needaddr) { 691 printf(" 0x%02x:", off); 692 needaddr = 0; 693 } 694 printf(" 0x%08x", regs[o2i(off)]); 695 neednl = 1; 696 if ((off % 16) == 12) { 697 printf("\n"); 698 neednl = 0; 699 } 700 } 701 if (neednl) 702 printf("\n"); 703 } 704 705 static void 706 pci_conf_print_type0( 707 #ifdef _KERNEL 708 pci_chipset_tag_t pc, pcitag_t tag, 709 #endif 710 const pcireg_t *regs 711 #ifdef _KERNEL 712 , int sizebars 713 #endif 714 ) 715 { 716 int off, width; 717 pcireg_t rval; 718 719 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 720 #ifdef _KERNEL 721 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 722 #else 723 width = pci_conf_print_bar(regs, off, NULL); 724 #endif 725 } 726 727 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 728 729 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 730 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 731 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 732 733 /* XXX */ 734 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 735 736 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 737 printf(" Capability list pointer: 0x%02x\n", 738 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 739 else 740 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 741 742 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 743 744 rval = regs[o2i(PCI_INTERRUPT_REG)]; 745 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 746 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 747 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 748 switch (PCI_INTERRUPT_PIN(rval)) { 749 case PCI_INTERRUPT_PIN_NONE: 750 printf("(none)"); 751 break; 752 case PCI_INTERRUPT_PIN_A: 753 printf("(pin A)"); 754 break; 755 case PCI_INTERRUPT_PIN_B: 756 printf("(pin B)"); 757 break; 758 case PCI_INTERRUPT_PIN_C: 759 printf("(pin C)"); 760 break; 761 case PCI_INTERRUPT_PIN_D: 762 printf("(pin D)"); 763 break; 764 default: 765 printf("(? ? ?)"); 766 break; 767 } 768 printf("\n"); 769 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 770 771 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) { 772 for (off = PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]); 773 off != 0; 774 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 775 rval = regs[o2i(off)]; 776 printf(" Capability register at 0x%02x\n", off); 777 778 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 779 switch (PCI_CAPLIST_CAP(rval)) { 780 case PCI_CAP_RESERVED0: 781 printf("reserved"); 782 break; 783 case PCI_CAP_PWRMGMT: 784 printf("Power Management, rev. %d.0", 785 (rval >> 0) & 0x07); /* XXX not clear */ 786 break; 787 case PCI_CAP_AGP: 788 printf("AGP, rev. %d.%d", 789 (rval >> 24) & 0x0f, 790 (rval >> 20) & 0x0f); 791 break; 792 case PCI_CAP_VPD: 793 printf("VPD"); 794 break; 795 case PCI_CAP_SLOTID: 796 printf("SlotID"); 797 break; 798 case PCI_CAP_MBI: 799 printf("MBI"); 800 break; 801 case PCI_CAP_CPCI_HOTSWAP: 802 printf("CompactPCI Hot-swapping"); 803 break; 804 case PCI_CAP_PCIX: 805 printf("PCI-X"); 806 break; 807 case PCI_CAP_LDT: 808 printf("LDT"); 809 break; 810 case PCI_CAP_VENDSPEC: 811 printf("Vendor-specific"); 812 break; 813 case PCI_CAP_DEBUGPORT: 814 printf("Debug Port"); 815 break; 816 case PCI_CAP_CPCI_RSRCCTL: 817 printf("CompactPCI Resource Control"); 818 break; 819 case PCI_CAP_HOTPLUG: 820 printf("Hot-Plug"); 821 break; 822 default: 823 printf("unknown"); 824 } 825 printf(")\n"); 826 } 827 } 828 } 829 830 static void 831 pci_conf_print_type1( 832 #ifdef _KERNEL 833 pci_chipset_tag_t pc, pcitag_t tag, 834 #endif 835 const pcireg_t *regs 836 #ifdef _KERNEL 837 , int sizebars 838 #endif 839 ) 840 { 841 int off, width; 842 pcireg_t rval; 843 844 /* 845 * XXX these need to be printed in more detail, need to be 846 * XXX checked against specs/docs, etc. 847 * 848 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 849 * Bridge chip documentation, and may not be correct with 850 * respect to various standards. (XXX) 851 */ 852 853 for (off = 0x10; off < 0x18; off += width) { 854 #ifdef _KERNEL 855 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 856 #else 857 width = pci_conf_print_bar(regs, off, NULL); 858 #endif 859 } 860 861 printf(" Primary bus number: 0x%02x\n", 862 (regs[o2i(0x18)] >> 0) & 0xff); 863 printf(" Secondary bus number: 0x%02x\n", 864 (regs[o2i(0x18)] >> 8) & 0xff); 865 printf(" Subordinate bus number: 0x%02x\n", 866 (regs[o2i(0x18)] >> 16) & 0xff); 867 printf(" Secondary bus latency timer: 0x%02x\n", 868 (regs[o2i(0x18)] >> 24) & 0xff); 869 870 rval = (regs[o2i(0x1c)] >> 16) & 0xffff; 871 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 872 onoff("66 MHz capable", 0x0020); 873 onoff("User Definable Features (UDF) support", 0x0040); 874 onoff("Fast back-to-back capable", 0x0080); 875 onoff("Data parity error detected", 0x0100); 876 877 printf(" DEVSEL timing: "); 878 switch (rval & 0x0600) { 879 case 0x0000: 880 printf("fast"); 881 break; 882 case 0x0200: 883 printf("medium"); 884 break; 885 case 0x0400: 886 printf("slow"); 887 break; 888 default: 889 printf("unknown/reserved"); /* XXX */ 890 break; 891 } 892 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 893 894 onoff("Signaled Target Abort", 0x0800); 895 onoff("Received Target Abort", 0x1000); 896 onoff("Received Master Abort", 0x2000); 897 onoff("System Error", 0x4000); 898 onoff("Parity Error", 0x8000); 899 900 /* XXX Print more prettily */ 901 printf(" I/O region:\n"); 902 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 903 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 904 printf(" base upper 16 bits register: 0x%04x\n", 905 (regs[o2i(0x30)] >> 0) & 0xffff); 906 printf(" limit upper 16 bits register: 0x%04x\n", 907 (regs[o2i(0x30)] >> 16) & 0xffff); 908 909 /* XXX Print more prettily */ 910 printf(" Memory region:\n"); 911 printf(" base register: 0x%04x\n", 912 (regs[o2i(0x20)] >> 0) & 0xffff); 913 printf(" limit register: 0x%04x\n", 914 (regs[o2i(0x20)] >> 16) & 0xffff); 915 916 /* XXX Print more prettily */ 917 printf(" Prefetchable memory region:\n"); 918 printf(" base register: 0x%04x\n", 919 (regs[o2i(0x24)] >> 0) & 0xffff); 920 printf(" limit register: 0x%04x\n", 921 (regs[o2i(0x24)] >> 16) & 0xffff); 922 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 923 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 924 925 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 926 /* XXX */ 927 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 928 929 printf(" Interrupt line: 0x%02x\n", 930 (regs[o2i(0x3c)] >> 0) & 0xff); 931 printf(" Interrupt pin: 0x%02x ", 932 (regs[o2i(0x3c)] >> 8) & 0xff); 933 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 934 case PCI_INTERRUPT_PIN_NONE: 935 printf("(none)"); 936 break; 937 case PCI_INTERRUPT_PIN_A: 938 printf("(pin A)"); 939 break; 940 case PCI_INTERRUPT_PIN_B: 941 printf("(pin B)"); 942 break; 943 case PCI_INTERRUPT_PIN_C: 944 printf("(pin C)"); 945 break; 946 case PCI_INTERRUPT_PIN_D: 947 printf("(pin D)"); 948 break; 949 default: 950 printf("(? ? ?)"); 951 break; 952 } 953 printf("\n"); 954 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 955 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 956 onoff("Parity error response", 0x0001); 957 onoff("Secondary SERR forwarding", 0x0002); 958 onoff("ISA enable", 0x0004); 959 onoff("VGA enable", 0x0008); 960 onoff("Master abort reporting", 0x0020); 961 onoff("Secondary bus reset", 0x0040); 962 onoff("Fast back-to-back capable", 0x0080); 963 } 964 965 static void 966 pci_conf_print_type2( 967 #ifdef _KERNEL 968 pci_chipset_tag_t pc, pcitag_t tag, 969 #endif 970 const pcireg_t *regs 971 #ifdef _KERNEL 972 , int sizebars 973 #endif 974 ) 975 { 976 pcireg_t rval; 977 978 /* 979 * XXX these need to be printed in more detail, need to be 980 * XXX checked against specs/docs, etc. 981 * 982 * This layout was cribbed from the TI PCI1130 PCI-to-CardBus 983 * controller chip documentation, and may not be correct with 984 * respect to various standards. (XXX) 985 */ 986 987 #ifdef _KERNEL 988 pci_conf_print_bar(pc, tag, regs, 0x10, 989 "CardBus socket/ExCA registers", sizebars); 990 #else 991 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 992 #endif 993 994 printf(" Reserved @ 0x14: 0x%04x\n", 995 (regs[o2i(0x14)] >> 0) & 0xffff); 996 rval = (regs[o2i(0x14)] >> 16) & 0xffff; 997 printf(" Secondary status register: 0x%04x\n", rval); 998 onoff("66 MHz capable", 0x0020); 999 onoff("User Definable Features (UDF) support", 0x0040); 1000 onoff("Fast back-to-back capable", 0x0080); 1001 onoff("Data parity error detection", 0x0100); 1002 1003 printf(" DEVSEL timing: "); 1004 switch (rval & 0x0600) { 1005 case 0x0000: 1006 printf("fast"); 1007 break; 1008 case 0x0200: 1009 printf("medium"); 1010 break; 1011 case 0x0400: 1012 printf("slow"); 1013 break; 1014 default: 1015 printf("unknown/reserved"); /* XXX */ 1016 break; 1017 } 1018 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 1019 onoff("PCI target aborts terminate CardBus bus master transactions", 1020 0x0800); 1021 onoff("CardBus target aborts terminate PCI bus master transactions", 1022 0x1000); 1023 onoff("Bus initiator aborts terminate initiator transactions", 1024 0x2000); 1025 onoff("System error", 0x4000); 1026 onoff("Parity error", 0x8000); 1027 1028 printf(" PCI bus number: 0x%02x\n", 1029 (regs[o2i(0x18)] >> 0) & 0xff); 1030 printf(" CardBus bus number: 0x%02x\n", 1031 (regs[o2i(0x18)] >> 8) & 0xff); 1032 printf(" Subordinate bus number: 0x%02x\n", 1033 (regs[o2i(0x18)] >> 16) & 0xff); 1034 printf(" CardBus latency timer: 0x%02x\n", 1035 (regs[o2i(0x18)] >> 24) & 0xff); 1036 1037 /* XXX Print more prettily */ 1038 printf(" CardBus memory region 0:\n"); 1039 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1040 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1041 printf(" CardBus memory region 1:\n"); 1042 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1043 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1044 printf(" CardBus I/O region 0:\n"); 1045 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1046 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1047 printf(" CardBus I/O region 1:\n"); 1048 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1049 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1050 1051 printf(" Interrupt line: 0x%02x\n", 1052 (regs[o2i(0x3c)] >> 0) & 0xff); 1053 printf(" Interrupt pin: 0x%02x ", 1054 (regs[o2i(0x3c)] >> 8) & 0xff); 1055 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1056 case PCI_INTERRUPT_PIN_NONE: 1057 printf("(none)"); 1058 break; 1059 case PCI_INTERRUPT_PIN_A: 1060 printf("(pin A)"); 1061 break; 1062 case PCI_INTERRUPT_PIN_B: 1063 printf("(pin B)"); 1064 break; 1065 case PCI_INTERRUPT_PIN_C: 1066 printf("(pin C)"); 1067 break; 1068 case PCI_INTERRUPT_PIN_D: 1069 printf("(pin D)"); 1070 break; 1071 default: 1072 printf("(? ? ?)"); 1073 break; 1074 } 1075 printf("\n"); 1076 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1077 printf(" Bridge control register: 0x%04x\n", rval); 1078 onoff("Parity error response", 0x0001); 1079 onoff("CardBus SERR forwarding", 0x0002); 1080 onoff("ISA enable", 0x0004); 1081 onoff("VGA enable", 0x0008); 1082 onoff("CardBus master abort reporting", 0x0020); 1083 onoff("CardBus reset", 0x0040); 1084 onoff("Functional interrupts routed by ExCA registers", 0x0080); 1085 onoff("Memory window 0 prefetchable", 0x0100); 1086 onoff("Memory window 1 prefetchable", 0x0200); 1087 onoff("Write posting enable", 0x0400); 1088 1089 rval = regs[o2i(0x40)]; 1090 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1091 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1092 1093 #ifdef _KERNEL 1094 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1095 sizebars); 1096 #else 1097 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 1098 #endif 1099 } 1100 1101 void 1102 pci_conf_print( 1103 #ifdef _KERNEL 1104 pci_chipset_tag_t pc, pcitag_t tag, 1105 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 1106 #else 1107 int pcifd, u_int bus, u_int dev, u_int func 1108 #endif 1109 ) 1110 { 1111 pcireg_t regs[o2i(256)]; 1112 int off, endoff, hdrtype; 1113 const char *typename; 1114 #ifdef _KERNEL 1115 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1116 int sizebars; 1117 #else 1118 void (*typeprintfn)(const pcireg_t *); 1119 #endif 1120 1121 printf("PCI configuration registers:\n"); 1122 1123 for (off = 0; off < 256; off += 4) { 1124 #ifdef _KERNEL 1125 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1126 #else 1127 if (pcibus_conf_read(pcifd, bus, dev, func, off, 1128 ®s[o2i(off)]) == -1) 1129 regs[o2i(off)] = 0; 1130 #endif 1131 } 1132 1133 #ifdef _KERNEL 1134 sizebars = 1; 1135 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1136 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1137 sizebars = 0; 1138 #endif 1139 1140 /* common header */ 1141 printf(" Common header:\n"); 1142 pci_conf_print_regs(regs, 0, 16); 1143 1144 printf("\n"); 1145 #ifdef _KERNEL 1146 pci_conf_print_common(pc, tag, regs); 1147 #else 1148 pci_conf_print_common(regs); 1149 #endif 1150 printf("\n"); 1151 1152 /* type-dependent header */ 1153 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1154 switch (hdrtype) { /* XXX make a table, eventually */ 1155 case 0: 1156 /* Standard device header */ 1157 typename = "\"normal\" device"; 1158 typeprintfn = &pci_conf_print_type0; 1159 endoff = 64; 1160 break; 1161 case 1: 1162 /* PCI-PCI bridge header */ 1163 typename = "PCI-PCI bridge"; 1164 typeprintfn = &pci_conf_print_type1; 1165 endoff = 64; 1166 break; 1167 case 2: 1168 /* PCI-CardBus bridge header */ 1169 typename = "PCI-CardBus bridge"; 1170 typeprintfn = &pci_conf_print_type2; 1171 endoff = 72; 1172 break; 1173 default: 1174 typename = NULL; 1175 typeprintfn = 0; 1176 endoff = 64; 1177 break; 1178 } 1179 printf(" Type %d ", hdrtype); 1180 if (typename != NULL) 1181 printf("(%s) ", typename); 1182 printf("header:\n"); 1183 pci_conf_print_regs(regs, 16, endoff); 1184 printf("\n"); 1185 if (typeprintfn) { 1186 #ifdef _KERNEL 1187 (*typeprintfn)(pc, tag, regs, sizebars); 1188 #else 1189 (*typeprintfn)(regs); 1190 #endif 1191 } else 1192 printf(" Don't know how to pretty-print type %d header.\n", 1193 hdrtype); 1194 printf("\n"); 1195 1196 #ifdef _KERNEL 1197 /* device-dependent header */ 1198 printf(" Device-dependent header:\n"); 1199 pci_conf_print_regs(regs, endoff, 256); 1200 printf("\n"); 1201 if (printfn) 1202 (*printfn)(pc, tag, regs); 1203 else 1204 printf(" Don't know how to pretty-print device-dependent header.\n"); 1205 printf("\n"); 1206 #endif /* _KERNEL */ 1207 } 1208
Indexes created Fri Sep 26 08:10:20 GMT 2025