pci_subr.c revision 1.47
1 /* $NetBSD: pci_subr.c,v 1.47 2001/11/13 07:48:47 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.47 2001/11/13 07:48:47 lukem Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 52 #ifdef _KERNEL 53 #include <machine/intr.h> 54 #else 55 #include <pci.h> 56 #include <stdio.h> 57 #endif 58 59 #include <dev/pci/pcireg.h> 60 #ifdef _KERNEL 61 #include <dev/pci/pcivar.h> 62 #endif 63 #ifdef PCIVERBOSE 64 #include <dev/pci/pcidevs.h> 65 #endif 66 67 /* 68 * Descriptions of known PCI classes and subclasses. 69 * 70 * Subclasses are described in the same way as classes, but have a 71 * NULL subclass pointer. 72 */ 73 struct pci_class { 74 const char *name; 75 int val; /* as wide as pci_{,sub}class_t */ 76 const struct pci_class *subclasses; 77 }; 78 79 const struct pci_class pci_subclass_prehistoric[] = { 80 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, }, 81 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, }, 82 { 0 } 83 }; 84 85 const struct pci_class pci_subclass_mass_storage[] = { 86 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, }, 87 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, }, 88 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, }, 89 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, }, 90 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, }, 91 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, }, 92 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, }, 93 { 0 }, 94 }; 95 96 const struct pci_class pci_subclass_network[] = { 97 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, }, 98 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, }, 99 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, }, 100 { "ATM", PCI_SUBCLASS_NETWORK_ATM, }, 101 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, }, 102 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, }, 103 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, }, 104 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, }, 105 { 0 }, 106 }; 107 108 const struct pci_class pci_subclass_display[] = { 109 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, }, 110 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, }, 111 { "3D", PCI_SUBCLASS_DISPLAY_3D, }, 112 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, }, 113 { 0 }, 114 }; 115 116 const struct pci_class pci_subclass_multimedia[] = { 117 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, }, 118 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, }, 119 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, }, 120 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, }, 121 { 0 }, 122 }; 123 124 const struct pci_class pci_subclass_memory[] = { 125 { "RAM", PCI_SUBCLASS_MEMORY_RAM, }, 126 { "flash", PCI_SUBCLASS_MEMORY_FLASH, }, 127 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, }, 128 { 0 }, 129 }; 130 131 const struct pci_class pci_subclass_bridge[] = { 132 { "host", PCI_SUBCLASS_BRIDGE_HOST, }, 133 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, }, 134 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, }, 135 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, }, 136 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, }, 137 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, }, 138 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, }, 139 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, }, 140 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, }, 141 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, }, 142 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, }, 143 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, }, 144 { 0 }, 145 }; 146 147 const struct pci_class pci_subclass_communications[] = { 148 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, }, 149 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, }, 150 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, }, 151 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, }, 152 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, }, 153 { 0 }, 154 }; 155 156 const struct pci_class pci_subclass_system[] = { 157 { "8259 PIC", PCI_SUBCLASS_SYSTEM_PIC, }, 158 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, }, 159 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, }, 160 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, }, 161 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_RTC, }, 162 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, }, 163 { 0 }, 164 }; 165 166 const struct pci_class pci_subclass_input[] = { 167 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, }, 168 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, }, 169 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, }, 170 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, }, 171 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, }, 172 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, }, 173 { 0 }, 174 }; 175 176 const struct pci_class pci_subclass_dock[] = { 177 { "generic", PCI_SUBCLASS_DOCK_GENERIC, }, 178 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, }, 179 { 0 }, 180 }; 181 182 const struct pci_class pci_subclass_processor[] = { 183 { "386", PCI_SUBCLASS_PROCESSOR_386, }, 184 { "486", PCI_SUBCLASS_PROCESSOR_486, }, 185 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, }, 186 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, }, 187 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, }, 188 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, }, 189 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, }, 190 { 0 }, 191 }; 192 193 const struct pci_class pci_subclass_serialbus[] = { 194 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, }, 195 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, }, 196 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, }, 197 { "USB", PCI_SUBCLASS_SERIALBUS_USB, }, 198 /* XXX Fiber Channel/_FIBRECHANNEL */ 199 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, }, 200 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, }, 201 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, }, 202 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, }, 203 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, }, 204 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, }, 205 { 0 }, 206 }; 207 208 const struct pci_class pci_subclass_wireless[] = { 209 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, }, 210 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, }, 211 { "RF", PCI_SUBCLASS_WIRELESS_RF, }, 212 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, }, 213 { 0 }, 214 }; 215 216 const struct pci_class pci_subclass_i2o[] = { 217 { "standard", PCI_SUBCLASS_I2O_STANDARD, }, 218 { 0 }, 219 }; 220 221 const struct pci_class pci_subclass_satcom[] = { 222 { "TV", PCI_SUBCLASS_SATCOM_TV, }, 223 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, }, 224 { "voice", PCI_SUBCLASS_SATCOM_VOICE, }, 225 { "data", PCI_SUBCLASS_SATCOM_DATA, }, 226 { 0 }, 227 }; 228 229 const struct pci_class pci_subclass_crypto[] = { 230 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, }, 231 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, }, 232 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, }, 233 { 0 }, 234 }; 235 236 const struct pci_class pci_subclass_dasp[] = { 237 { "DPIO", PCI_SUBCLASS_DASP_DPIO, }, 238 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, }, 239 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, }, 240 { 0 }, 241 }; 242 243 const struct pci_class pci_class[] = { 244 { "prehistoric", PCI_CLASS_PREHISTORIC, 245 pci_subclass_prehistoric, }, 246 { "mass storage", PCI_CLASS_MASS_STORAGE, 247 pci_subclass_mass_storage, }, 248 { "network", PCI_CLASS_NETWORK, 249 pci_subclass_network, }, 250 { "display", PCI_CLASS_DISPLAY, 251 pci_subclass_display, }, 252 { "multimedia", PCI_CLASS_MULTIMEDIA, 253 pci_subclass_multimedia, }, 254 { "memory", PCI_CLASS_MEMORY, 255 pci_subclass_memory, }, 256 { "bridge", PCI_CLASS_BRIDGE, 257 pci_subclass_bridge, }, 258 { "communications", PCI_CLASS_COMMUNICATIONS, 259 pci_subclass_communications, }, 260 { "system", PCI_CLASS_SYSTEM, 261 pci_subclass_system, }, 262 { "input", PCI_CLASS_INPUT, 263 pci_subclass_input, }, 264 { "dock", PCI_CLASS_DOCK, 265 pci_subclass_dock, }, 266 { "processor", PCI_CLASS_PROCESSOR, 267 pci_subclass_processor, }, 268 { "serial bus", PCI_CLASS_SERIALBUS, 269 pci_subclass_serialbus, }, 270 { "wireless", PCI_CLASS_WIRELESS, 271 pci_subclass_wireless, }, 272 { "I2O", PCI_CLASS_I2O, 273 pci_subclass_i2o, }, 274 { "satellite comm", PCI_CLASS_SATCOM, 275 pci_subclass_satcom, }, 276 { "crypto", PCI_CLASS_CRYPTO, 277 pci_subclass_crypto, }, 278 { "DASP", PCI_CLASS_DASP, 279 pci_subclass_dasp, }, 280 { "undefined", PCI_CLASS_UNDEFINED, 281 0, }, 282 { 0 }, 283 }; 284 285 #ifdef PCIVERBOSE 286 /* 287 * Descriptions of of known vendors and devices ("products"). 288 */ 289 struct pci_knowndev { 290 pci_vendor_id_t vendor; 291 pci_product_id_t product; 292 int flags; 293 char *vendorname, *productname; 294 }; 295 #define PCI_KNOWNDEV_NOPROD 0x01 /* match on vendor only */ 296 297 #include <dev/pci/pcidevs_data.h> 298 #endif /* PCIVERBOSE */ 299 300 char * 301 pci_findvendor(pcireg_t id_reg) 302 { 303 #ifdef PCIVERBOSE 304 pci_vendor_id_t vendor = PCI_VENDOR(id_reg); 305 const struct pci_knowndev *kdp; 306 307 kdp = pci_knowndevs; 308 while (kdp->vendorname != NULL) { /* all have vendor name */ 309 if (kdp->vendor == vendor) 310 break; 311 kdp++; 312 } 313 return (kdp->vendorname); 314 #else 315 return (NULL); 316 #endif 317 } 318 319 void 320 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp) 321 { 322 pci_vendor_id_t vendor; 323 pci_product_id_t product; 324 pci_class_t class; 325 pci_subclass_t subclass; 326 pci_interface_t interface; 327 pci_revision_t revision; 328 char *vendor_namep, *product_namep; 329 const struct pci_class *classp, *subclassp; 330 #ifdef PCIVERBOSE 331 const struct pci_knowndev *kdp; 332 const char *unmatched = "unknown "; 333 #else 334 const char *unmatched = ""; 335 #endif 336 337 vendor = PCI_VENDOR(id_reg); 338 product = PCI_PRODUCT(id_reg); 339 340 class = PCI_CLASS(class_reg); 341 subclass = PCI_SUBCLASS(class_reg); 342 interface = PCI_INTERFACE(class_reg); 343 revision = PCI_REVISION(class_reg); 344 345 #ifdef PCIVERBOSE 346 kdp = pci_knowndevs; 347 while (kdp->vendorname != NULL) { /* all have vendor name */ 348 if (kdp->vendor == vendor && (kdp->product == product || 349 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) 350 break; 351 kdp++; 352 } 353 if (kdp->vendorname == NULL) 354 vendor_namep = product_namep = NULL; 355 else { 356 vendor_namep = kdp->vendorname; 357 product_namep = (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0 ? 358 kdp->productname : NULL; 359 } 360 #else /* PCIVERBOSE */ 361 vendor_namep = product_namep = NULL; 362 #endif /* PCIVERBOSE */ 363 364 classp = pci_class; 365 while (classp->name != NULL) { 366 if (class == classp->val) 367 break; 368 classp++; 369 } 370 371 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 372 while (subclassp && subclassp->name != NULL) { 373 if (subclass == subclassp->val) 374 break; 375 subclassp++; 376 } 377 378 if (vendor_namep == NULL) 379 cp += sprintf(cp, "%svendor 0x%04x product 0x%04x", 380 unmatched, vendor, product); 381 else if (product_namep != NULL) 382 cp += sprintf(cp, "%s %s", vendor_namep, product_namep); 383 else 384 cp += sprintf(cp, "%s product 0x%04x", 385 vendor_namep, product); 386 if (showclass) { 387 cp += sprintf(cp, " ("); 388 if (classp->name == NULL) 389 cp += sprintf(cp, "class 0x%02x, subclass 0x%02x", 390 class, subclass); 391 else { 392 if (subclassp == NULL || subclassp->name == NULL) 393 cp += sprintf(cp, 394 "%s subclass 0x%02x", 395 classp->name, subclass); 396 else 397 cp += sprintf(cp, "%s %s", 398 subclassp->name, classp->name); 399 } 400 if (interface != 0) 401 cp += sprintf(cp, ", interface 0x%02x", interface); 402 if (revision != 0) 403 cp += sprintf(cp, ", revision 0x%02x", revision); 404 cp += sprintf(cp, ")"); 405 } 406 } 407 408 /* 409 * Print out most of the PCI configuration registers. Typically used 410 * in a device attach routine like this: 411 * 412 * #ifdef MYDEV_DEBUG 413 * printf("%s: ", sc->sc_dev.dv_xname); 414 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 415 * #endif 416 */ 417 418 #define i2o(i) ((i) * 4) 419 #define o2i(o) ((o) / 4) 420 #define onoff(str, bit) \ 421 printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off"); 422 423 static void 424 pci_conf_print_common( 425 #ifdef _KERNEL 426 pci_chipset_tag_t pc, pcitag_t tag, 427 #endif 428 const pcireg_t *regs) 429 { 430 #ifdef PCIVERBOSE 431 const struct pci_knowndev *kdp; 432 #endif 433 const struct pci_class *classp, *subclassp; 434 pcireg_t rval; 435 436 rval = regs[o2i(PCI_ID_REG)]; 437 #ifndef PCIVERBOSE 438 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 439 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 440 #else 441 for (kdp = pci_knowndevs; kdp->vendorname != NULL; kdp++) { 442 if (kdp->vendor == PCI_VENDOR(rval) && 443 (kdp->product == PCI_PRODUCT(rval) || 444 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) { 445 break; 446 } 447 } 448 if (kdp->vendorname != NULL) 449 printf(" Vendor Name: %s (0x%04x)\n", kdp->vendorname, 450 PCI_VENDOR(rval)); 451 else 452 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 453 if (kdp->productname != NULL && (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0) 454 printf(" Device Name: %s (0x%04x)\n", kdp->productname, 455 PCI_PRODUCT(rval)); 456 else 457 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 458 #endif /* PCIVERBOSE */ 459 460 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 461 462 printf(" Command register: 0x%04x\n", rval & 0xffff); 463 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 464 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 465 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 466 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 467 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 468 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 469 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 470 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 471 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 472 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 473 474 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 475 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 476 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 477 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 478 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 479 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 480 481 printf(" DEVSEL timing: "); 482 switch (rval & PCI_STATUS_DEVSEL_MASK) { 483 case PCI_STATUS_DEVSEL_FAST: 484 printf("fast"); 485 break; 486 case PCI_STATUS_DEVSEL_MEDIUM: 487 printf("medium"); 488 break; 489 case PCI_STATUS_DEVSEL_SLOW: 490 printf("slow"); 491 break; 492 default: 493 printf("unknown/reserved"); /* XXX */ 494 break; 495 } 496 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 497 498 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 499 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 500 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 501 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 502 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 503 504 rval = regs[o2i(PCI_CLASS_REG)]; 505 for (classp = pci_class; classp->name != NULL; classp++) { 506 if (PCI_CLASS(rval) == classp->val) 507 break; 508 } 509 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 510 while (subclassp && subclassp->name != NULL) { 511 if (PCI_SUBCLASS(rval) == subclassp->val) 512 break; 513 subclassp++; 514 } 515 if (classp->name != NULL) { 516 printf(" Class Name: %s (0x%02x)\n", classp->name, 517 PCI_CLASS(rval)); 518 if (subclassp != NULL && subclassp->name != NULL) 519 printf(" Subclass Name: %s (0x%02x)\n", 520 subclassp->name, PCI_SUBCLASS(rval)); 521 else 522 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 523 } else { 524 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 525 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 526 } 527 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 528 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 529 530 rval = regs[o2i(PCI_BHLC_REG)]; 531 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 532 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 533 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 534 PCI_HDRTYPE(rval)); 535 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 536 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 537 } 538 539 static int 540 pci_conf_print_bar( 541 #ifdef _KERNEL 542 pci_chipset_tag_t pc, pcitag_t tag, 543 #endif 544 const pcireg_t *regs, int reg, const char *name 545 #ifdef _KERNEL 546 , int sizebar 547 #endif 548 ) 549 { 550 int width; 551 pcireg_t rval, rval64h; 552 #ifdef _KERNEL 553 int s; 554 pcireg_t mask, mask64h; 555 #endif 556 557 width = 4; 558 559 /* 560 * Section 6.2.5.1, `Address Maps', tells us that: 561 * 562 * 1) The builtin software should have already mapped the 563 * device in a reasonable way. 564 * 565 * 2) A device which wants 2^n bytes of memory will hardwire 566 * the bottom n bits of the address to 0. As recommended, 567 * we write all 1s and see what we get back. 568 */ 569 570 rval = regs[o2i(reg)]; 571 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 572 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 573 rval64h = regs[o2i(reg + 4)]; 574 width = 8; 575 } else 576 rval64h = 0; 577 578 #ifdef _KERNEL 579 /* XXX don't size unknown memory type? */ 580 if (rval != 0 && sizebar) { 581 /* 582 * The following sequence seems to make some devices 583 * (e.g. host bus bridges, which don't normally 584 * have their space mapped) very unhappy, to 585 * the point of crashing the system. 586 * 587 * Therefore, if the mapping register is zero to 588 * start out with, don't bother trying. 589 */ 590 s = splhigh(); 591 pci_conf_write(pc, tag, reg, 0xffffffff); 592 mask = pci_conf_read(pc, tag, reg); 593 pci_conf_write(pc, tag, reg, rval); 594 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 595 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 596 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 597 mask64h = pci_conf_read(pc, tag, reg + 4); 598 pci_conf_write(pc, tag, reg + 4, rval64h); 599 } 600 splx(s); 601 } else 602 mask = 0; 603 #endif /* _KERNEL */ 604 605 printf(" Base address register at 0x%02x", reg); 606 if (name) 607 printf(" (%s)", name); 608 printf("\n "); 609 if (rval == 0) { 610 printf("not implemented(?)\n"); 611 return width; 612 } 613 printf("type: "); 614 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 615 const char *type, *prefetch; 616 617 switch (PCI_MAPREG_MEM_TYPE(rval)) { 618 case PCI_MAPREG_MEM_TYPE_32BIT: 619 type = "32-bit"; 620 break; 621 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 622 type = "32-bit-1M"; 623 break; 624 case PCI_MAPREG_MEM_TYPE_64BIT: 625 type = "64-bit"; 626 break; 627 default: 628 type = "unknown (XXX)"; 629 break; 630 } 631 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 632 prefetch = ""; 633 else 634 prefetch = "non"; 635 printf("%s %sprefetchable memory\n", type, prefetch); 636 switch (PCI_MAPREG_MEM_TYPE(rval)) { 637 case PCI_MAPREG_MEM_TYPE_64BIT: 638 printf(" base: 0x%016llx, ", 639 PCI_MAPREG_MEM64_ADDR( 640 ((((long long) rval64h) << 32) | rval))); 641 #ifdef _KERNEL 642 if (sizebar) 643 printf("size: 0x%016llx", 644 PCI_MAPREG_MEM64_SIZE( 645 ((((long long) mask64h) << 32) | mask))); 646 else 647 #endif /* _KERNEL */ 648 printf("not sized"); 649 printf("\n"); 650 break; 651 case PCI_MAPREG_MEM_TYPE_32BIT: 652 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 653 default: 654 printf(" base: 0x%08x, ", 655 PCI_MAPREG_MEM_ADDR(rval)); 656 #ifdef _KERNEL 657 if (sizebar) 658 printf("size: 0x%08x", 659 PCI_MAPREG_MEM_SIZE(mask)); 660 else 661 #endif /* _KERNEL */ 662 printf("not sized"); 663 printf("\n"); 664 break; 665 } 666 } else { 667 #ifdef _KERNEL 668 if (sizebar) 669 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 670 #endif /* _KERNEL */ 671 printf("i/o\n"); 672 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 673 #ifdef _KERNEL 674 if (sizebar) 675 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 676 else 677 #endif /* _KERNEL */ 678 printf("not sized"); 679 printf("\n"); 680 } 681 682 return width; 683 } 684 685 static void 686 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 687 { 688 int off, needaddr, neednl; 689 690 needaddr = 1; 691 neednl = 0; 692 for (off = first; off < pastlast; off += 4) { 693 if ((off % 16) == 0 || needaddr) { 694 printf(" 0x%02x:", off); 695 needaddr = 0; 696 } 697 printf(" 0x%08x", regs[o2i(off)]); 698 neednl = 1; 699 if ((off % 16) == 12) { 700 printf("\n"); 701 neednl = 0; 702 } 703 } 704 if (neednl) 705 printf("\n"); 706 } 707 708 static void 709 pci_conf_print_type0( 710 #ifdef _KERNEL 711 pci_chipset_tag_t pc, pcitag_t tag, 712 #endif 713 const pcireg_t *regs 714 #ifdef _KERNEL 715 , int sizebars 716 #endif 717 ) 718 { 719 int off, width; 720 pcireg_t rval; 721 722 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 723 #ifdef _KERNEL 724 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 725 #else 726 width = pci_conf_print_bar(regs, off, NULL); 727 #endif 728 } 729 730 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 731 732 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 733 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 734 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 735 736 /* XXX */ 737 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 738 739 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 740 printf(" Capability list pointer: 0x%02x\n", 741 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 742 else 743 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 744 745 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 746 747 rval = regs[o2i(PCI_INTERRUPT_REG)]; 748 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 749 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 750 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 751 switch (PCI_INTERRUPT_PIN(rval)) { 752 case PCI_INTERRUPT_PIN_NONE: 753 printf("(none)"); 754 break; 755 case PCI_INTERRUPT_PIN_A: 756 printf("(pin A)"); 757 break; 758 case PCI_INTERRUPT_PIN_B: 759 printf("(pin B)"); 760 break; 761 case PCI_INTERRUPT_PIN_C: 762 printf("(pin C)"); 763 break; 764 case PCI_INTERRUPT_PIN_D: 765 printf("(pin D)"); 766 break; 767 default: 768 printf("(? ? ?)"); 769 break; 770 } 771 printf("\n"); 772 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 773 774 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) { 775 for (off = PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]); 776 off != 0; 777 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 778 rval = regs[o2i(off)]; 779 printf(" Capability register at 0x%02x\n", off); 780 781 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 782 switch (PCI_CAPLIST_CAP(rval)) { 783 case PCI_CAP_RESERVED0: 784 printf("reserved"); 785 break; 786 case PCI_CAP_PWRMGMT: 787 printf("Power Management, rev. %d.0", 788 (rval >> 0) & 0x07); /* XXX not clear */ 789 break; 790 case PCI_CAP_AGP: 791 printf("AGP, rev. %d.%d", 792 (rval >> 24) & 0x0f, 793 (rval >> 20) & 0x0f); 794 break; 795 case PCI_CAP_VPD: 796 printf("VPD"); 797 break; 798 case PCI_CAP_SLOTID: 799 printf("SlotID"); 800 break; 801 case PCI_CAP_MBI: 802 printf("MBI"); 803 break; 804 case PCI_CAP_CPCI_HOTSWAP: 805 printf("CompactPCI Hot-swapping"); 806 break; 807 case PCI_CAP_PCIX: 808 printf("PCI-X"); 809 break; 810 case PCI_CAP_LDT: 811 printf("LDT"); 812 break; 813 case PCI_CAP_VENDSPEC: 814 printf("Vendor-specific"); 815 break; 816 case PCI_CAP_DEBUGPORT: 817 printf("Debug Port"); 818 break; 819 case PCI_CAP_CPCI_RSRCCTL: 820 printf("CompactPCI Resource Control"); 821 break; 822 case PCI_CAP_HOTPLUG: 823 printf("Hot-Plug"); 824 break; 825 default: 826 printf("unknown"); 827 } 828 printf(")\n"); 829 } 830 } 831 } 832 833 static void 834 pci_conf_print_type1( 835 #ifdef _KERNEL 836 pci_chipset_tag_t pc, pcitag_t tag, 837 #endif 838 const pcireg_t *regs 839 #ifdef _KERNEL 840 , int sizebars 841 #endif 842 ) 843 { 844 int off, width; 845 pcireg_t rval; 846 847 /* 848 * XXX these need to be printed in more detail, need to be 849 * XXX checked against specs/docs, etc. 850 * 851 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 852 * Bridge chip documentation, and may not be correct with 853 * respect to various standards. (XXX) 854 */ 855 856 for (off = 0x10; off < 0x18; off += width) { 857 #ifdef _KERNEL 858 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 859 #else 860 width = pci_conf_print_bar(regs, off, NULL); 861 #endif 862 } 863 864 printf(" Primary bus number: 0x%02x\n", 865 (regs[o2i(0x18)] >> 0) & 0xff); 866 printf(" Secondary bus number: 0x%02x\n", 867 (regs[o2i(0x18)] >> 8) & 0xff); 868 printf(" Subordinate bus number: 0x%02x\n", 869 (regs[o2i(0x18)] >> 16) & 0xff); 870 printf(" Secondary bus latency timer: 0x%02x\n", 871 (regs[o2i(0x18)] >> 24) & 0xff); 872 873 rval = (regs[o2i(0x1c)] >> 16) & 0xffff; 874 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 875 onoff("66 MHz capable", 0x0020); 876 onoff("User Definable Features (UDF) support", 0x0040); 877 onoff("Fast back-to-back capable", 0x0080); 878 onoff("Data parity error detected", 0x0100); 879 880 printf(" DEVSEL timing: "); 881 switch (rval & 0x0600) { 882 case 0x0000: 883 printf("fast"); 884 break; 885 case 0x0200: 886 printf("medium"); 887 break; 888 case 0x0400: 889 printf("slow"); 890 break; 891 default: 892 printf("unknown/reserved"); /* XXX */ 893 break; 894 } 895 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 896 897 onoff("Signaled Target Abort", 0x0800); 898 onoff("Received Target Abort", 0x1000); 899 onoff("Received Master Abort", 0x2000); 900 onoff("System Error", 0x4000); 901 onoff("Parity Error", 0x8000); 902 903 /* XXX Print more prettily */ 904 printf(" I/O region:\n"); 905 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 906 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 907 printf(" base upper 16 bits register: 0x%04x\n", 908 (regs[o2i(0x30)] >> 0) & 0xffff); 909 printf(" limit upper 16 bits register: 0x%04x\n", 910 (regs[o2i(0x30)] >> 16) & 0xffff); 911 912 /* XXX Print more prettily */ 913 printf(" Memory region:\n"); 914 printf(" base register: 0x%04x\n", 915 (regs[o2i(0x20)] >> 0) & 0xffff); 916 printf(" limit register: 0x%04x\n", 917 (regs[o2i(0x20)] >> 16) & 0xffff); 918 919 /* XXX Print more prettily */ 920 printf(" Prefetchable memory region:\n"); 921 printf(" base register: 0x%04x\n", 922 (regs[o2i(0x24)] >> 0) & 0xffff); 923 printf(" limit register: 0x%04x\n", 924 (regs[o2i(0x24)] >> 16) & 0xffff); 925 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 926 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 927 928 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 929 /* XXX */ 930 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 931 932 printf(" Interrupt line: 0x%02x\n", 933 (regs[o2i(0x3c)] >> 0) & 0xff); 934 printf(" Interrupt pin: 0x%02x ", 935 (regs[o2i(0x3c)] >> 8) & 0xff); 936 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 937 case PCI_INTERRUPT_PIN_NONE: 938 printf("(none)"); 939 break; 940 case PCI_INTERRUPT_PIN_A: 941 printf("(pin A)"); 942 break; 943 case PCI_INTERRUPT_PIN_B: 944 printf("(pin B)"); 945 break; 946 case PCI_INTERRUPT_PIN_C: 947 printf("(pin C)"); 948 break; 949 case PCI_INTERRUPT_PIN_D: 950 printf("(pin D)"); 951 break; 952 default: 953 printf("(? ? ?)"); 954 break; 955 } 956 printf("\n"); 957 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 958 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 959 onoff("Parity error response", 0x0001); 960 onoff("Secondary SERR forwarding", 0x0002); 961 onoff("ISA enable", 0x0004); 962 onoff("VGA enable", 0x0008); 963 onoff("Master abort reporting", 0x0020); 964 onoff("Secondary bus reset", 0x0040); 965 onoff("Fast back-to-back capable", 0x0080); 966 } 967 968 static void 969 pci_conf_print_type2( 970 #ifdef _KERNEL 971 pci_chipset_tag_t pc, pcitag_t tag, 972 #endif 973 const pcireg_t *regs 974 #ifdef _KERNEL 975 , int sizebars 976 #endif 977 ) 978 { 979 pcireg_t rval; 980 981 /* 982 * XXX these need to be printed in more detail, need to be 983 * XXX checked against specs/docs, etc. 984 * 985 * This layout was cribbed from the TI PCI1130 PCI-to-CardBus 986 * controller chip documentation, and may not be correct with 987 * respect to various standards. (XXX) 988 */ 989 990 #ifdef _KERNEL 991 pci_conf_print_bar(pc, tag, regs, 0x10, 992 "CardBus socket/ExCA registers", sizebars); 993 #else 994 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 995 #endif 996 997 printf(" Reserved @ 0x14: 0x%04x\n", 998 (regs[o2i(0x14)] >> 0) & 0xffff); 999 rval = (regs[o2i(0x14)] >> 16) & 0xffff; 1000 printf(" Secondary status register: 0x%04x\n", rval); 1001 onoff("66 MHz capable", 0x0020); 1002 onoff("User Definable Features (UDF) support", 0x0040); 1003 onoff("Fast back-to-back capable", 0x0080); 1004 onoff("Data parity error detection", 0x0100); 1005 1006 printf(" DEVSEL timing: "); 1007 switch (rval & 0x0600) { 1008 case 0x0000: 1009 printf("fast"); 1010 break; 1011 case 0x0200: 1012 printf("medium"); 1013 break; 1014 case 0x0400: 1015 printf("slow"); 1016 break; 1017 default: 1018 printf("unknown/reserved"); /* XXX */ 1019 break; 1020 } 1021 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 1022 onoff("PCI target aborts terminate CardBus bus master transactions", 1023 0x0800); 1024 onoff("CardBus target aborts terminate PCI bus master transactions", 1025 0x1000); 1026 onoff("Bus initiator aborts terminate initiator transactions", 1027 0x2000); 1028 onoff("System error", 0x4000); 1029 onoff("Parity error", 0x8000); 1030 1031 printf(" PCI bus number: 0x%02x\n", 1032 (regs[o2i(0x18)] >> 0) & 0xff); 1033 printf(" CardBus bus number: 0x%02x\n", 1034 (regs[o2i(0x18)] >> 8) & 0xff); 1035 printf(" Subordinate bus number: 0x%02x\n", 1036 (regs[o2i(0x18)] >> 16) & 0xff); 1037 printf(" CardBus latency timer: 0x%02x\n", 1038 (regs[o2i(0x18)] >> 24) & 0xff); 1039 1040 /* XXX Print more prettily */ 1041 printf(" CardBus memory region 0:\n"); 1042 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1043 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1044 printf(" CardBus memory region 1:\n"); 1045 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1046 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1047 printf(" CardBus I/O region 0:\n"); 1048 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1049 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1050 printf(" CardBus I/O region 1:\n"); 1051 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1052 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1053 1054 printf(" Interrupt line: 0x%02x\n", 1055 (regs[o2i(0x3c)] >> 0) & 0xff); 1056 printf(" Interrupt pin: 0x%02x ", 1057 (regs[o2i(0x3c)] >> 8) & 0xff); 1058 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1059 case PCI_INTERRUPT_PIN_NONE: 1060 printf("(none)"); 1061 break; 1062 case PCI_INTERRUPT_PIN_A: 1063 printf("(pin A)"); 1064 break; 1065 case PCI_INTERRUPT_PIN_B: 1066 printf("(pin B)"); 1067 break; 1068 case PCI_INTERRUPT_PIN_C: 1069 printf("(pin C)"); 1070 break; 1071 case PCI_INTERRUPT_PIN_D: 1072 printf("(pin D)"); 1073 break; 1074 default: 1075 printf("(? ? ?)"); 1076 break; 1077 } 1078 printf("\n"); 1079 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1080 printf(" Bridge control register: 0x%04x\n", rval); 1081 onoff("Parity error response", 0x0001); 1082 onoff("CardBus SERR forwarding", 0x0002); 1083 onoff("ISA enable", 0x0004); 1084 onoff("VGA enable", 0x0008); 1085 onoff("CardBus master abort reporting", 0x0020); 1086 onoff("CardBus reset", 0x0040); 1087 onoff("Functional interrupts routed by ExCA registers", 0x0080); 1088 onoff("Memory window 0 prefetchable", 0x0100); 1089 onoff("Memory window 1 prefetchable", 0x0200); 1090 onoff("Write posting enable", 0x0400); 1091 1092 rval = regs[o2i(0x40)]; 1093 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1094 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1095 1096 #ifdef _KERNEL 1097 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1098 sizebars); 1099 #else 1100 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 1101 #endif 1102 } 1103 1104 void 1105 pci_conf_print( 1106 #ifdef _KERNEL 1107 pci_chipset_tag_t pc, pcitag_t tag, 1108 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 1109 #else 1110 int pcifd, u_int bus, u_int dev, u_int func 1111 #endif 1112 ) 1113 { 1114 pcireg_t regs[o2i(256)]; 1115 int off, endoff, hdrtype; 1116 const char *typename; 1117 #ifdef _KERNEL 1118 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1119 int sizebars; 1120 #else 1121 void (*typeprintfn)(const pcireg_t *); 1122 #endif 1123 1124 printf("PCI configuration registers:\n"); 1125 1126 for (off = 0; off < 256; off += 4) { 1127 #ifdef _KERNEL 1128 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1129 #else 1130 if (pcibus_conf_read(pcifd, bus, dev, func, off, 1131 ®s[o2i(off)]) == -1) 1132 regs[o2i(off)] = 0; 1133 #endif 1134 } 1135 1136 #ifdef _KERNEL 1137 sizebars = 1; 1138 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1139 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1140 sizebars = 0; 1141 #endif 1142 1143 /* common header */ 1144 printf(" Common header:\n"); 1145 pci_conf_print_regs(regs, 0, 16); 1146 1147 printf("\n"); 1148 #ifdef _KERNEL 1149 pci_conf_print_common(pc, tag, regs); 1150 #else 1151 pci_conf_print_common(regs); 1152 #endif 1153 printf("\n"); 1154 1155 /* type-dependent header */ 1156 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1157 switch (hdrtype) { /* XXX make a table, eventually */ 1158 case 0: 1159 /* Standard device header */ 1160 typename = "\"normal\" device"; 1161 typeprintfn = &pci_conf_print_type0; 1162 endoff = 64; 1163 break; 1164 case 1: 1165 /* PCI-PCI bridge header */ 1166 typename = "PCI-PCI bridge"; 1167 typeprintfn = &pci_conf_print_type1; 1168 endoff = 64; 1169 break; 1170 case 2: 1171 /* PCI-CardBus bridge header */ 1172 typename = "PCI-CardBus bridge"; 1173 typeprintfn = &pci_conf_print_type2; 1174 endoff = 72; 1175 break; 1176 default: 1177 typename = NULL; 1178 typeprintfn = 0; 1179 endoff = 64; 1180 break; 1181 } 1182 printf(" Type %d ", hdrtype); 1183 if (typename != NULL) 1184 printf("(%s) ", typename); 1185 printf("header:\n"); 1186 pci_conf_print_regs(regs, 16, endoff); 1187 printf("\n"); 1188 if (typeprintfn) { 1189 #ifdef _KERNEL 1190 (*typeprintfn)(pc, tag, regs, sizebars); 1191 #else 1192 (*typeprintfn)(regs); 1193 #endif 1194 } else 1195 printf(" Don't know how to pretty-print type %d header.\n", 1196 hdrtype); 1197 printf("\n"); 1198 1199 #ifdef _KERNEL 1200 /* device-dependent header */ 1201 printf(" Device-dependent header:\n"); 1202 pci_conf_print_regs(regs, endoff, 256); 1203 printf("\n"); 1204 if (printfn) 1205 (*printfn)(pc, tag, regs); 1206 else 1207 printf(" Don't know how to pretty-print device-dependent header.\n"); 1208 printf("\n"); 1209 #endif /* _KERNEL */ 1210 } 1211
Indexes created Tue Sep 23 22:09:46 GMT 2025