pci_subr.c revision 1.48
1 /* $NetBSD: pci_subr.c,v 1.48 2002/03/22 20:03:20 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.48 2002/03/22 20:03:20 drochner Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 52 #ifdef _KERNEL 53 #include <machine/intr.h> 54 #else 55 #include <pci.h> 56 #include <stdio.h> 57 #endif 58 59 #include <dev/pci/pcireg.h> 60 #ifdef _KERNEL 61 #include <dev/pci/pcivar.h> 62 #endif 63 #ifdef PCIVERBOSE 64 #include <dev/pci/pcidevs.h> 65 #endif 66 67 /* 68 * Descriptions of known PCI classes and subclasses. 69 * 70 * Subclasses are described in the same way as classes, but have a 71 * NULL subclass pointer. 72 */ 73 struct pci_class { 74 const char *name; 75 int val; /* as wide as pci_{,sub}class_t */ 76 const struct pci_class *subclasses; 77 }; 78 79 const struct pci_class pci_subclass_prehistoric[] = { 80 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, }, 81 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, }, 82 { 0 } 83 }; 84 85 const struct pci_class pci_subclass_mass_storage[] = { 86 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, }, 87 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, }, 88 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, }, 89 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, }, 90 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, }, 91 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, }, 92 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, }, 93 { 0 }, 94 }; 95 96 const struct pci_class pci_subclass_network[] = { 97 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, }, 98 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, }, 99 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, }, 100 { "ATM", PCI_SUBCLASS_NETWORK_ATM, }, 101 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, }, 102 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, }, 103 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, }, 104 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, }, 105 { 0 }, 106 }; 107 108 const struct pci_class pci_subclass_display[] = { 109 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, }, 110 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, }, 111 { "3D", PCI_SUBCLASS_DISPLAY_3D, }, 112 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, }, 113 { 0 }, 114 }; 115 116 const struct pci_class pci_subclass_multimedia[] = { 117 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, }, 118 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, }, 119 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, }, 120 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, }, 121 { 0 }, 122 }; 123 124 const struct pci_class pci_subclass_memory[] = { 125 { "RAM", PCI_SUBCLASS_MEMORY_RAM, }, 126 { "flash", PCI_SUBCLASS_MEMORY_FLASH, }, 127 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, }, 128 { 0 }, 129 }; 130 131 const struct pci_class pci_subclass_bridge[] = { 132 { "host", PCI_SUBCLASS_BRIDGE_HOST, }, 133 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, }, 134 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, }, 135 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, }, 136 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, }, 137 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, }, 138 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, }, 139 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, }, 140 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, }, 141 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, }, 142 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, }, 143 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, }, 144 { 0 }, 145 }; 146 147 const struct pci_class pci_subclass_communications[] = { 148 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, }, 149 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, }, 150 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, }, 151 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, }, 152 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, }, 153 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, }, 154 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, }, 155 { 0 }, 156 }; 157 158 const struct pci_class pci_subclass_system[] = { 159 { "8259 PIC", PCI_SUBCLASS_SYSTEM_PIC, }, 160 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, }, 161 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, }, 162 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, }, 163 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_RTC, }, 164 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, }, 165 { 0 }, 166 }; 167 168 const struct pci_class pci_subclass_input[] = { 169 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, }, 170 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, }, 171 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, }, 172 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, }, 173 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, }, 174 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, }, 175 { 0 }, 176 }; 177 178 const struct pci_class pci_subclass_dock[] = { 179 { "generic", PCI_SUBCLASS_DOCK_GENERIC, }, 180 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, }, 181 { 0 }, 182 }; 183 184 const struct pci_class pci_subclass_processor[] = { 185 { "386", PCI_SUBCLASS_PROCESSOR_386, }, 186 { "486", PCI_SUBCLASS_PROCESSOR_486, }, 187 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, }, 188 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, }, 189 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, }, 190 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, }, 191 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, }, 192 { 0 }, 193 }; 194 195 const struct pci_class pci_subclass_serialbus[] = { 196 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, }, 197 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, }, 198 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, }, 199 { "USB", PCI_SUBCLASS_SERIALBUS_USB, }, 200 /* XXX Fiber Channel/_FIBRECHANNEL */ 201 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, }, 202 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, }, 203 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, }, 204 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, }, 205 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, }, 206 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, }, 207 { 0 }, 208 }; 209 210 const struct pci_class pci_subclass_wireless[] = { 211 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, }, 212 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, }, 213 { "RF", PCI_SUBCLASS_WIRELESS_RF, }, 214 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, }, 215 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, }, 216 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, }, 217 { 0 }, 218 }; 219 220 const struct pci_class pci_subclass_i2o[] = { 221 { "standard", PCI_SUBCLASS_I2O_STANDARD, }, 222 { 0 }, 223 }; 224 225 const struct pci_class pci_subclass_satcom[] = { 226 { "TV", PCI_SUBCLASS_SATCOM_TV, }, 227 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, }, 228 { "voice", PCI_SUBCLASS_SATCOM_VOICE, }, 229 { "data", PCI_SUBCLASS_SATCOM_DATA, }, 230 { 0 }, 231 }; 232 233 const struct pci_class pci_subclass_crypto[] = { 234 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, }, 235 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, }, 236 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, }, 237 { 0 }, 238 }; 239 240 const struct pci_class pci_subclass_dasp[] = { 241 { "DPIO", PCI_SUBCLASS_DASP_DPIO, }, 242 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, }, 243 { "synchronization", PCI_SUBCLASS_DASP_SYNC, }, 244 { "management", PCI_SUBCLASS_DASP_MGMT, }, 245 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, }, 246 { 0 }, 247 }; 248 249 const struct pci_class pci_class[] = { 250 { "prehistoric", PCI_CLASS_PREHISTORIC, 251 pci_subclass_prehistoric, }, 252 { "mass storage", PCI_CLASS_MASS_STORAGE, 253 pci_subclass_mass_storage, }, 254 { "network", PCI_CLASS_NETWORK, 255 pci_subclass_network, }, 256 { "display", PCI_CLASS_DISPLAY, 257 pci_subclass_display, }, 258 { "multimedia", PCI_CLASS_MULTIMEDIA, 259 pci_subclass_multimedia, }, 260 { "memory", PCI_CLASS_MEMORY, 261 pci_subclass_memory, }, 262 { "bridge", PCI_CLASS_BRIDGE, 263 pci_subclass_bridge, }, 264 { "communications", PCI_CLASS_COMMUNICATIONS, 265 pci_subclass_communications, }, 266 { "system", PCI_CLASS_SYSTEM, 267 pci_subclass_system, }, 268 { "input", PCI_CLASS_INPUT, 269 pci_subclass_input, }, 270 { "dock", PCI_CLASS_DOCK, 271 pci_subclass_dock, }, 272 { "processor", PCI_CLASS_PROCESSOR, 273 pci_subclass_processor, }, 274 { "serial bus", PCI_CLASS_SERIALBUS, 275 pci_subclass_serialbus, }, 276 { "wireless", PCI_CLASS_WIRELESS, 277 pci_subclass_wireless, }, 278 { "I2O", PCI_CLASS_I2O, 279 pci_subclass_i2o, }, 280 { "satellite comm", PCI_CLASS_SATCOM, 281 pci_subclass_satcom, }, 282 { "crypto", PCI_CLASS_CRYPTO, 283 pci_subclass_crypto, }, 284 { "DASP", PCI_CLASS_DASP, 285 pci_subclass_dasp, }, 286 { "undefined", PCI_CLASS_UNDEFINED, 287 0, }, 288 { 0 }, 289 }; 290 291 #ifdef PCIVERBOSE 292 /* 293 * Descriptions of of known vendors and devices ("products"). 294 */ 295 struct pci_knowndev { 296 pci_vendor_id_t vendor; 297 pci_product_id_t product; 298 int flags; 299 char *vendorname, *productname; 300 }; 301 #define PCI_KNOWNDEV_NOPROD 0x01 /* match on vendor only */ 302 303 #include <dev/pci/pcidevs_data.h> 304 #endif /* PCIVERBOSE */ 305 306 char * 307 pci_findvendor(pcireg_t id_reg) 308 { 309 #ifdef PCIVERBOSE 310 pci_vendor_id_t vendor = PCI_VENDOR(id_reg); 311 const struct pci_knowndev *kdp; 312 313 kdp = pci_knowndevs; 314 while (kdp->vendorname != NULL) { /* all have vendor name */ 315 if (kdp->vendor == vendor) 316 break; 317 kdp++; 318 } 319 return (kdp->vendorname); 320 #else 321 return (NULL); 322 #endif 323 } 324 325 void 326 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp) 327 { 328 pci_vendor_id_t vendor; 329 pci_product_id_t product; 330 pci_class_t class; 331 pci_subclass_t subclass; 332 pci_interface_t interface; 333 pci_revision_t revision; 334 char *vendor_namep, *product_namep; 335 const struct pci_class *classp, *subclassp; 336 #ifdef PCIVERBOSE 337 const struct pci_knowndev *kdp; 338 const char *unmatched = "unknown "; 339 #else 340 const char *unmatched = ""; 341 #endif 342 343 vendor = PCI_VENDOR(id_reg); 344 product = PCI_PRODUCT(id_reg); 345 346 class = PCI_CLASS(class_reg); 347 subclass = PCI_SUBCLASS(class_reg); 348 interface = PCI_INTERFACE(class_reg); 349 revision = PCI_REVISION(class_reg); 350 351 #ifdef PCIVERBOSE 352 kdp = pci_knowndevs; 353 while (kdp->vendorname != NULL) { /* all have vendor name */ 354 if (kdp->vendor == vendor && (kdp->product == product || 355 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) 356 break; 357 kdp++; 358 } 359 if (kdp->vendorname == NULL) 360 vendor_namep = product_namep = NULL; 361 else { 362 vendor_namep = kdp->vendorname; 363 product_namep = (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0 ? 364 kdp->productname : NULL; 365 } 366 #else /* PCIVERBOSE */ 367 vendor_namep = product_namep = NULL; 368 #endif /* PCIVERBOSE */ 369 370 classp = pci_class; 371 while (classp->name != NULL) { 372 if (class == classp->val) 373 break; 374 classp++; 375 } 376 377 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 378 while (subclassp && subclassp->name != NULL) { 379 if (subclass == subclassp->val) 380 break; 381 subclassp++; 382 } 383 384 if (vendor_namep == NULL) 385 cp += sprintf(cp, "%svendor 0x%04x product 0x%04x", 386 unmatched, vendor, product); 387 else if (product_namep != NULL) 388 cp += sprintf(cp, "%s %s", vendor_namep, product_namep); 389 else 390 cp += sprintf(cp, "%s product 0x%04x", 391 vendor_namep, product); 392 if (showclass) { 393 cp += sprintf(cp, " ("); 394 if (classp->name == NULL) 395 cp += sprintf(cp, "class 0x%02x, subclass 0x%02x", 396 class, subclass); 397 else { 398 if (subclassp == NULL || subclassp->name == NULL) 399 cp += sprintf(cp, 400 "%s subclass 0x%02x", 401 classp->name, subclass); 402 else 403 cp += sprintf(cp, "%s %s", 404 subclassp->name, classp->name); 405 } 406 if (interface != 0) 407 cp += sprintf(cp, ", interface 0x%02x", interface); 408 if (revision != 0) 409 cp += sprintf(cp, ", revision 0x%02x", revision); 410 cp += sprintf(cp, ")"); 411 } 412 } 413 414 /* 415 * Print out most of the PCI configuration registers. Typically used 416 * in a device attach routine like this: 417 * 418 * #ifdef MYDEV_DEBUG 419 * printf("%s: ", sc->sc_dev.dv_xname); 420 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 421 * #endif 422 */ 423 424 #define i2o(i) ((i) * 4) 425 #define o2i(o) ((o) / 4) 426 #define onoff(str, bit) \ 427 printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off"); 428 429 static void 430 pci_conf_print_common( 431 #ifdef _KERNEL 432 pci_chipset_tag_t pc, pcitag_t tag, 433 #endif 434 const pcireg_t *regs) 435 { 436 #ifdef PCIVERBOSE 437 const struct pci_knowndev *kdp; 438 #endif 439 const struct pci_class *classp, *subclassp; 440 pcireg_t rval; 441 442 rval = regs[o2i(PCI_ID_REG)]; 443 #ifndef PCIVERBOSE 444 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 445 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 446 #else 447 for (kdp = pci_knowndevs; kdp->vendorname != NULL; kdp++) { 448 if (kdp->vendor == PCI_VENDOR(rval) && 449 (kdp->product == PCI_PRODUCT(rval) || 450 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) { 451 break; 452 } 453 } 454 if (kdp->vendorname != NULL) 455 printf(" Vendor Name: %s (0x%04x)\n", kdp->vendorname, 456 PCI_VENDOR(rval)); 457 else 458 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 459 if (kdp->productname != NULL && (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0) 460 printf(" Device Name: %s (0x%04x)\n", kdp->productname, 461 PCI_PRODUCT(rval)); 462 else 463 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 464 #endif /* PCIVERBOSE */ 465 466 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 467 468 printf(" Command register: 0x%04x\n", rval & 0xffff); 469 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 470 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 471 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 472 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 473 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 474 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 475 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 476 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 477 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 478 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 479 480 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 481 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 482 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 483 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 484 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 485 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 486 487 printf(" DEVSEL timing: "); 488 switch (rval & PCI_STATUS_DEVSEL_MASK) { 489 case PCI_STATUS_DEVSEL_FAST: 490 printf("fast"); 491 break; 492 case PCI_STATUS_DEVSEL_MEDIUM: 493 printf("medium"); 494 break; 495 case PCI_STATUS_DEVSEL_SLOW: 496 printf("slow"); 497 break; 498 default: 499 printf("unknown/reserved"); /* XXX */ 500 break; 501 } 502 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 503 504 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 505 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 506 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 507 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 508 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 509 510 rval = regs[o2i(PCI_CLASS_REG)]; 511 for (classp = pci_class; classp->name != NULL; classp++) { 512 if (PCI_CLASS(rval) == classp->val) 513 break; 514 } 515 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 516 while (subclassp && subclassp->name != NULL) { 517 if (PCI_SUBCLASS(rval) == subclassp->val) 518 break; 519 subclassp++; 520 } 521 if (classp->name != NULL) { 522 printf(" Class Name: %s (0x%02x)\n", classp->name, 523 PCI_CLASS(rval)); 524 if (subclassp != NULL && subclassp->name != NULL) 525 printf(" Subclass Name: %s (0x%02x)\n", 526 subclassp->name, PCI_SUBCLASS(rval)); 527 else 528 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 529 } else { 530 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 531 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 532 } 533 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 534 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 535 536 rval = regs[o2i(PCI_BHLC_REG)]; 537 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 538 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 539 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 540 PCI_HDRTYPE(rval)); 541 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 542 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 543 } 544 545 static int 546 pci_conf_print_bar( 547 #ifdef _KERNEL 548 pci_chipset_tag_t pc, pcitag_t tag, 549 #endif 550 const pcireg_t *regs, int reg, const char *name 551 #ifdef _KERNEL 552 , int sizebar 553 #endif 554 ) 555 { 556 int width; 557 pcireg_t rval, rval64h; 558 #ifdef _KERNEL 559 int s; 560 pcireg_t mask, mask64h; 561 #endif 562 563 width = 4; 564 565 /* 566 * Section 6.2.5.1, `Address Maps', tells us that: 567 * 568 * 1) The builtin software should have already mapped the 569 * device in a reasonable way. 570 * 571 * 2) A device which wants 2^n bytes of memory will hardwire 572 * the bottom n bits of the address to 0. As recommended, 573 * we write all 1s and see what we get back. 574 */ 575 576 rval = regs[o2i(reg)]; 577 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 578 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 579 rval64h = regs[o2i(reg + 4)]; 580 width = 8; 581 } else 582 rval64h = 0; 583 584 #ifdef _KERNEL 585 /* XXX don't size unknown memory type? */ 586 if (rval != 0 && sizebar) { 587 /* 588 * The following sequence seems to make some devices 589 * (e.g. host bus bridges, which don't normally 590 * have their space mapped) very unhappy, to 591 * the point of crashing the system. 592 * 593 * Therefore, if the mapping register is zero to 594 * start out with, don't bother trying. 595 */ 596 s = splhigh(); 597 pci_conf_write(pc, tag, reg, 0xffffffff); 598 mask = pci_conf_read(pc, tag, reg); 599 pci_conf_write(pc, tag, reg, rval); 600 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 601 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 602 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 603 mask64h = pci_conf_read(pc, tag, reg + 4); 604 pci_conf_write(pc, tag, reg + 4, rval64h); 605 } 606 splx(s); 607 } else 608 mask = 0; 609 #endif /* _KERNEL */ 610 611 printf(" Base address register at 0x%02x", reg); 612 if (name) 613 printf(" (%s)", name); 614 printf("\n "); 615 if (rval == 0) { 616 printf("not implemented(?)\n"); 617 return width; 618 } 619 printf("type: "); 620 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 621 const char *type, *prefetch; 622 623 switch (PCI_MAPREG_MEM_TYPE(rval)) { 624 case PCI_MAPREG_MEM_TYPE_32BIT: 625 type = "32-bit"; 626 break; 627 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 628 type = "32-bit-1M"; 629 break; 630 case PCI_MAPREG_MEM_TYPE_64BIT: 631 type = "64-bit"; 632 break; 633 default: 634 type = "unknown (XXX)"; 635 break; 636 } 637 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 638 prefetch = ""; 639 else 640 prefetch = "non"; 641 printf("%s %sprefetchable memory\n", type, prefetch); 642 switch (PCI_MAPREG_MEM_TYPE(rval)) { 643 case PCI_MAPREG_MEM_TYPE_64BIT: 644 printf(" base: 0x%016llx, ", 645 PCI_MAPREG_MEM64_ADDR( 646 ((((long long) rval64h) << 32) | rval))); 647 #ifdef _KERNEL 648 if (sizebar) 649 printf("size: 0x%016llx", 650 PCI_MAPREG_MEM64_SIZE( 651 ((((long long) mask64h) << 32) | mask))); 652 else 653 #endif /* _KERNEL */ 654 printf("not sized"); 655 printf("\n"); 656 break; 657 case PCI_MAPREG_MEM_TYPE_32BIT: 658 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 659 default: 660 printf(" base: 0x%08x, ", 661 PCI_MAPREG_MEM_ADDR(rval)); 662 #ifdef _KERNEL 663 if (sizebar) 664 printf("size: 0x%08x", 665 PCI_MAPREG_MEM_SIZE(mask)); 666 else 667 #endif /* _KERNEL */ 668 printf("not sized"); 669 printf("\n"); 670 break; 671 } 672 } else { 673 #ifdef _KERNEL 674 if (sizebar) 675 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 676 #endif /* _KERNEL */ 677 printf("i/o\n"); 678 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 679 #ifdef _KERNEL 680 if (sizebar) 681 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 682 else 683 #endif /* _KERNEL */ 684 printf("not sized"); 685 printf("\n"); 686 } 687 688 return width; 689 } 690 691 static void 692 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 693 { 694 int off, needaddr, neednl; 695 696 needaddr = 1; 697 neednl = 0; 698 for (off = first; off < pastlast; off += 4) { 699 if ((off % 16) == 0 || needaddr) { 700 printf(" 0x%02x:", off); 701 needaddr = 0; 702 } 703 printf(" 0x%08x", regs[o2i(off)]); 704 neednl = 1; 705 if ((off % 16) == 12) { 706 printf("\n"); 707 neednl = 0; 708 } 709 } 710 if (neednl) 711 printf("\n"); 712 } 713 714 static void 715 pci_conf_print_type0( 716 #ifdef _KERNEL 717 pci_chipset_tag_t pc, pcitag_t tag, 718 #endif 719 const pcireg_t *regs 720 #ifdef _KERNEL 721 , int sizebars 722 #endif 723 ) 724 { 725 int off, width; 726 pcireg_t rval; 727 728 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 729 #ifdef _KERNEL 730 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 731 #else 732 width = pci_conf_print_bar(regs, off, NULL); 733 #endif 734 } 735 736 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 737 738 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 739 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 740 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 741 742 /* XXX */ 743 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 744 745 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 746 printf(" Capability list pointer: 0x%02x\n", 747 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 748 else 749 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 750 751 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 752 753 rval = regs[o2i(PCI_INTERRUPT_REG)]; 754 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 755 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 756 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 757 switch (PCI_INTERRUPT_PIN(rval)) { 758 case PCI_INTERRUPT_PIN_NONE: 759 printf("(none)"); 760 break; 761 case PCI_INTERRUPT_PIN_A: 762 printf("(pin A)"); 763 break; 764 case PCI_INTERRUPT_PIN_B: 765 printf("(pin B)"); 766 break; 767 case PCI_INTERRUPT_PIN_C: 768 printf("(pin C)"); 769 break; 770 case PCI_INTERRUPT_PIN_D: 771 printf("(pin D)"); 772 break; 773 default: 774 printf("(? ? ?)"); 775 break; 776 } 777 printf("\n"); 778 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 779 780 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) { 781 for (off = PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)]); 782 off != 0; 783 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 784 rval = regs[o2i(off)]; 785 printf(" Capability register at 0x%02x\n", off); 786 787 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 788 switch (PCI_CAPLIST_CAP(rval)) { 789 case PCI_CAP_RESERVED0: 790 printf("reserved"); 791 break; 792 case PCI_CAP_PWRMGMT: 793 printf("Power Management, rev. %d.0", 794 (rval >> 0) & 0x07); /* XXX not clear */ 795 break; 796 case PCI_CAP_AGP: 797 printf("AGP, rev. %d.%d", 798 (rval >> 24) & 0x0f, 799 (rval >> 20) & 0x0f); 800 break; 801 case PCI_CAP_VPD: 802 printf("VPD"); 803 break; 804 case PCI_CAP_SLOTID: 805 printf("SlotID"); 806 break; 807 case PCI_CAP_MBI: 808 printf("MBI"); 809 break; 810 case PCI_CAP_CPCI_HOTSWAP: 811 printf("CompactPCI Hot-swapping"); 812 break; 813 case PCI_CAP_PCIX: 814 printf("PCI-X"); 815 break; 816 case PCI_CAP_LDT: 817 printf("LDT"); 818 break; 819 case PCI_CAP_VENDSPEC: 820 printf("Vendor-specific"); 821 break; 822 case PCI_CAP_DEBUGPORT: 823 printf("Debug Port"); 824 break; 825 case PCI_CAP_CPCI_RSRCCTL: 826 printf("CompactPCI Resource Control"); 827 break; 828 case PCI_CAP_HOTPLUG: 829 printf("Hot-Plug"); 830 break; 831 default: 832 printf("unknown"); 833 } 834 printf(")\n"); 835 } 836 } 837 } 838 839 static void 840 pci_conf_print_type1( 841 #ifdef _KERNEL 842 pci_chipset_tag_t pc, pcitag_t tag, 843 #endif 844 const pcireg_t *regs 845 #ifdef _KERNEL 846 , int sizebars 847 #endif 848 ) 849 { 850 int off, width; 851 pcireg_t rval; 852 853 /* 854 * XXX these need to be printed in more detail, need to be 855 * XXX checked against specs/docs, etc. 856 * 857 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 858 * Bridge chip documentation, and may not be correct with 859 * respect to various standards. (XXX) 860 */ 861 862 for (off = 0x10; off < 0x18; off += width) { 863 #ifdef _KERNEL 864 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 865 #else 866 width = pci_conf_print_bar(regs, off, NULL); 867 #endif 868 } 869 870 printf(" Primary bus number: 0x%02x\n", 871 (regs[o2i(0x18)] >> 0) & 0xff); 872 printf(" Secondary bus number: 0x%02x\n", 873 (regs[o2i(0x18)] >> 8) & 0xff); 874 printf(" Subordinate bus number: 0x%02x\n", 875 (regs[o2i(0x18)] >> 16) & 0xff); 876 printf(" Secondary bus latency timer: 0x%02x\n", 877 (regs[o2i(0x18)] >> 24) & 0xff); 878 879 rval = (regs[o2i(0x1c)] >> 16) & 0xffff; 880 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 881 onoff("66 MHz capable", 0x0020); 882 onoff("User Definable Features (UDF) support", 0x0040); 883 onoff("Fast back-to-back capable", 0x0080); 884 onoff("Data parity error detected", 0x0100); 885 886 printf(" DEVSEL timing: "); 887 switch (rval & 0x0600) { 888 case 0x0000: 889 printf("fast"); 890 break; 891 case 0x0200: 892 printf("medium"); 893 break; 894 case 0x0400: 895 printf("slow"); 896 break; 897 default: 898 printf("unknown/reserved"); /* XXX */ 899 break; 900 } 901 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 902 903 onoff("Signaled Target Abort", 0x0800); 904 onoff("Received Target Abort", 0x1000); 905 onoff("Received Master Abort", 0x2000); 906 onoff("System Error", 0x4000); 907 onoff("Parity Error", 0x8000); 908 909 /* XXX Print more prettily */ 910 printf(" I/O region:\n"); 911 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 912 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 913 printf(" base upper 16 bits register: 0x%04x\n", 914 (regs[o2i(0x30)] >> 0) & 0xffff); 915 printf(" limit upper 16 bits register: 0x%04x\n", 916 (regs[o2i(0x30)] >> 16) & 0xffff); 917 918 /* XXX Print more prettily */ 919 printf(" Memory region:\n"); 920 printf(" base register: 0x%04x\n", 921 (regs[o2i(0x20)] >> 0) & 0xffff); 922 printf(" limit register: 0x%04x\n", 923 (regs[o2i(0x20)] >> 16) & 0xffff); 924 925 /* XXX Print more prettily */ 926 printf(" Prefetchable memory region:\n"); 927 printf(" base register: 0x%04x\n", 928 (regs[o2i(0x24)] >> 0) & 0xffff); 929 printf(" limit register: 0x%04x\n", 930 (regs[o2i(0x24)] >> 16) & 0xffff); 931 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 932 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 933 934 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 935 /* XXX */ 936 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 937 938 printf(" Interrupt line: 0x%02x\n", 939 (regs[o2i(0x3c)] >> 0) & 0xff); 940 printf(" Interrupt pin: 0x%02x ", 941 (regs[o2i(0x3c)] >> 8) & 0xff); 942 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 943 case PCI_INTERRUPT_PIN_NONE: 944 printf("(none)"); 945 break; 946 case PCI_INTERRUPT_PIN_A: 947 printf("(pin A)"); 948 break; 949 case PCI_INTERRUPT_PIN_B: 950 printf("(pin B)"); 951 break; 952 case PCI_INTERRUPT_PIN_C: 953 printf("(pin C)"); 954 break; 955 case PCI_INTERRUPT_PIN_D: 956 printf("(pin D)"); 957 break; 958 default: 959 printf("(? ? ?)"); 960 break; 961 } 962 printf("\n"); 963 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 964 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 965 onoff("Parity error response", 0x0001); 966 onoff("Secondary SERR forwarding", 0x0002); 967 onoff("ISA enable", 0x0004); 968 onoff("VGA enable", 0x0008); 969 onoff("Master abort reporting", 0x0020); 970 onoff("Secondary bus reset", 0x0040); 971 onoff("Fast back-to-back capable", 0x0080); 972 } 973 974 static void 975 pci_conf_print_type2( 976 #ifdef _KERNEL 977 pci_chipset_tag_t pc, pcitag_t tag, 978 #endif 979 const pcireg_t *regs 980 #ifdef _KERNEL 981 , int sizebars 982 #endif 983 ) 984 { 985 pcireg_t rval; 986 987 /* 988 * XXX these need to be printed in more detail, need to be 989 * XXX checked against specs/docs, etc. 990 * 991 * This layout was cribbed from the TI PCI1130 PCI-to-CardBus 992 * controller chip documentation, and may not be correct with 993 * respect to various standards. (XXX) 994 */ 995 996 #ifdef _KERNEL 997 pci_conf_print_bar(pc, tag, regs, 0x10, 998 "CardBus socket/ExCA registers", sizebars); 999 #else 1000 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 1001 #endif 1002 1003 printf(" Reserved @ 0x14: 0x%04x\n", 1004 (regs[o2i(0x14)] >> 0) & 0xffff); 1005 rval = (regs[o2i(0x14)] >> 16) & 0xffff; 1006 printf(" Secondary status register: 0x%04x\n", rval); 1007 onoff("66 MHz capable", 0x0020); 1008 onoff("User Definable Features (UDF) support", 0x0040); 1009 onoff("Fast back-to-back capable", 0x0080); 1010 onoff("Data parity error detection", 0x0100); 1011 1012 printf(" DEVSEL timing: "); 1013 switch (rval & 0x0600) { 1014 case 0x0000: 1015 printf("fast"); 1016 break; 1017 case 0x0200: 1018 printf("medium"); 1019 break; 1020 case 0x0400: 1021 printf("slow"); 1022 break; 1023 default: 1024 printf("unknown/reserved"); /* XXX */ 1025 break; 1026 } 1027 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 1028 onoff("PCI target aborts terminate CardBus bus master transactions", 1029 0x0800); 1030 onoff("CardBus target aborts terminate PCI bus master transactions", 1031 0x1000); 1032 onoff("Bus initiator aborts terminate initiator transactions", 1033 0x2000); 1034 onoff("System error", 0x4000); 1035 onoff("Parity error", 0x8000); 1036 1037 printf(" PCI bus number: 0x%02x\n", 1038 (regs[o2i(0x18)] >> 0) & 0xff); 1039 printf(" CardBus bus number: 0x%02x\n", 1040 (regs[o2i(0x18)] >> 8) & 0xff); 1041 printf(" Subordinate bus number: 0x%02x\n", 1042 (regs[o2i(0x18)] >> 16) & 0xff); 1043 printf(" CardBus latency timer: 0x%02x\n", 1044 (regs[o2i(0x18)] >> 24) & 0xff); 1045 1046 /* XXX Print more prettily */ 1047 printf(" CardBus memory region 0:\n"); 1048 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1049 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1050 printf(" CardBus memory region 1:\n"); 1051 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1052 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1053 printf(" CardBus I/O region 0:\n"); 1054 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1055 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1056 printf(" CardBus I/O region 1:\n"); 1057 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1058 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1059 1060 printf(" Interrupt line: 0x%02x\n", 1061 (regs[o2i(0x3c)] >> 0) & 0xff); 1062 printf(" Interrupt pin: 0x%02x ", 1063 (regs[o2i(0x3c)] >> 8) & 0xff); 1064 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1065 case PCI_INTERRUPT_PIN_NONE: 1066 printf("(none)"); 1067 break; 1068 case PCI_INTERRUPT_PIN_A: 1069 printf("(pin A)"); 1070 break; 1071 case PCI_INTERRUPT_PIN_B: 1072 printf("(pin B)"); 1073 break; 1074 case PCI_INTERRUPT_PIN_C: 1075 printf("(pin C)"); 1076 break; 1077 case PCI_INTERRUPT_PIN_D: 1078 printf("(pin D)"); 1079 break; 1080 default: 1081 printf("(? ? ?)"); 1082 break; 1083 } 1084 printf("\n"); 1085 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1086 printf(" Bridge control register: 0x%04x\n", rval); 1087 onoff("Parity error response", 0x0001); 1088 onoff("CardBus SERR forwarding", 0x0002); 1089 onoff("ISA enable", 0x0004); 1090 onoff("VGA enable", 0x0008); 1091 onoff("CardBus master abort reporting", 0x0020); 1092 onoff("CardBus reset", 0x0040); 1093 onoff("Functional interrupts routed by ExCA registers", 0x0080); 1094 onoff("Memory window 0 prefetchable", 0x0100); 1095 onoff("Memory window 1 prefetchable", 0x0200); 1096 onoff("Write posting enable", 0x0400); 1097 1098 rval = regs[o2i(0x40)]; 1099 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1100 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1101 1102 #ifdef _KERNEL 1103 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1104 sizebars); 1105 #else 1106 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 1107 #endif 1108 } 1109 1110 void 1111 pci_conf_print( 1112 #ifdef _KERNEL 1113 pci_chipset_tag_t pc, pcitag_t tag, 1114 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 1115 #else 1116 int pcifd, u_int bus, u_int dev, u_int func 1117 #endif 1118 ) 1119 { 1120 pcireg_t regs[o2i(256)]; 1121 int off, endoff, hdrtype; 1122 const char *typename; 1123 #ifdef _KERNEL 1124 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1125 int sizebars; 1126 #else 1127 void (*typeprintfn)(const pcireg_t *); 1128 #endif 1129 1130 printf("PCI configuration registers:\n"); 1131 1132 for (off = 0; off < 256; off += 4) { 1133 #ifdef _KERNEL 1134 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1135 #else 1136 if (pcibus_conf_read(pcifd, bus, dev, func, off, 1137 ®s[o2i(off)]) == -1) 1138 regs[o2i(off)] = 0; 1139 #endif 1140 } 1141 1142 #ifdef _KERNEL 1143 sizebars = 1; 1144 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1145 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1146 sizebars = 0; 1147 #endif 1148 1149 /* common header */ 1150 printf(" Common header:\n"); 1151 pci_conf_print_regs(regs, 0, 16); 1152 1153 printf("\n"); 1154 #ifdef _KERNEL 1155 pci_conf_print_common(pc, tag, regs); 1156 #else 1157 pci_conf_print_common(regs); 1158 #endif 1159 printf("\n"); 1160 1161 /* type-dependent header */ 1162 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1163 switch (hdrtype) { /* XXX make a table, eventually */ 1164 case 0: 1165 /* Standard device header */ 1166 typename = "\"normal\" device"; 1167 typeprintfn = &pci_conf_print_type0; 1168 endoff = 64; 1169 break; 1170 case 1: 1171 /* PCI-PCI bridge header */ 1172 typename = "PCI-PCI bridge"; 1173 typeprintfn = &pci_conf_print_type1; 1174 endoff = 64; 1175 break; 1176 case 2: 1177 /* PCI-CardBus bridge header */ 1178 typename = "PCI-CardBus bridge"; 1179 typeprintfn = &pci_conf_print_type2; 1180 endoff = 72; 1181 break; 1182 default: 1183 typename = NULL; 1184 typeprintfn = 0; 1185 endoff = 64; 1186 break; 1187 } 1188 printf(" Type %d ", hdrtype); 1189 if (typename != NULL) 1190 printf("(%s) ", typename); 1191 printf("header:\n"); 1192 pci_conf_print_regs(regs, 16, endoff); 1193 printf("\n"); 1194 if (typeprintfn) { 1195 #ifdef _KERNEL 1196 (*typeprintfn)(pc, tag, regs, sizebars); 1197 #else 1198 (*typeprintfn)(regs); 1199 #endif 1200 } else 1201 printf(" Don't know how to pretty-print type %d header.\n", 1202 hdrtype); 1203 printf("\n"); 1204 1205 #ifdef _KERNEL 1206 /* device-dependent header */ 1207 printf(" Device-dependent header:\n"); 1208 pci_conf_print_regs(regs, endoff, 256); 1209 printf("\n"); 1210 if (printfn) 1211 (*printfn)(pc, tag, regs); 1212 else 1213 printf(" Don't know how to pretty-print device-dependent header.\n"); 1214 printf("\n"); 1215 #endif /* _KERNEL */ 1216 } 1217
Indexes created Thu Sep 25 16:09:42 GMT 2025