pci_subr.c revision 1.55
1 /* $NetBSD: pci_subr.c,v 1.55 2003/06/29 14:41:11 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.55 2003/06/29 14:41:11 jdolecek Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 52 #ifdef _KERNEL 53 #include <machine/intr.h> 54 #else 55 #include <pci.h> 56 #include <stdio.h> 57 #endif 58 59 #include <dev/pci/pcireg.h> 60 #ifdef _KERNEL 61 #include <dev/pci/pcivar.h> 62 #endif 63 #ifdef PCIVERBOSE 64 #include <dev/pci/pcidevs.h> 65 #endif 66 67 /* 68 * Descriptions of known PCI classes and subclasses. 69 * 70 * Subclasses are described in the same way as classes, but have a 71 * NULL subclass pointer. 72 */ 73 struct pci_class { 74 const char *name; 75 int val; /* as wide as pci_{,sub}class_t */ 76 const struct pci_class *subclasses; 77 }; 78 79 const struct pci_class pci_subclass_prehistoric[] = { 80 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, }, 81 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, }, 82 { 0 } 83 }; 84 85 const struct pci_class pci_subclass_mass_storage[] = { 86 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, }, 87 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, }, 88 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, }, 89 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, }, 90 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, }, 91 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, }, 92 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, }, 93 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, }, 94 { 0 }, 95 }; 96 97 const struct pci_class pci_subclass_network[] = { 98 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, }, 99 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, }, 100 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, }, 101 { "ATM", PCI_SUBCLASS_NETWORK_ATM, }, 102 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, }, 103 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, }, 104 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, }, 105 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, }, 106 { 0 }, 107 }; 108 109 const struct pci_class pci_subclass_display[] = { 110 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, }, 111 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, }, 112 { "3D", PCI_SUBCLASS_DISPLAY_3D, }, 113 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, }, 114 { 0 }, 115 }; 116 117 const struct pci_class pci_subclass_multimedia[] = { 118 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, }, 119 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, }, 120 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, }, 121 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, }, 122 { 0 }, 123 }; 124 125 const struct pci_class pci_subclass_memory[] = { 126 { "RAM", PCI_SUBCLASS_MEMORY_RAM, }, 127 { "flash", PCI_SUBCLASS_MEMORY_FLASH, }, 128 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, }, 129 { 0 }, 130 }; 131 132 const struct pci_class pci_subclass_bridge[] = { 133 { "host", PCI_SUBCLASS_BRIDGE_HOST, }, 134 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, }, 135 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, }, 136 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, }, 137 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, }, 138 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, }, 139 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, }, 140 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, }, 141 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, }, 142 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, }, 143 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, }, 144 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, }, 145 { 0 }, 146 }; 147 148 const struct pci_class pci_subclass_communications[] = { 149 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, }, 150 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, }, 151 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, }, 152 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, }, 153 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, }, 154 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, }, 155 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, }, 156 { 0 }, 157 }; 158 159 const struct pci_class pci_subclass_system[] = { 160 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, }, 161 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, }, 162 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, }, 163 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, }, 164 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_RTC, }, 165 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, }, 166 { 0 }, 167 }; 168 169 const struct pci_class pci_subclass_input[] = { 170 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, }, 171 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, }, 172 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, }, 173 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, }, 174 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, }, 175 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, }, 176 { 0 }, 177 }; 178 179 const struct pci_class pci_subclass_dock[] = { 180 { "generic", PCI_SUBCLASS_DOCK_GENERIC, }, 181 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, }, 182 { 0 }, 183 }; 184 185 const struct pci_class pci_subclass_processor[] = { 186 { "386", PCI_SUBCLASS_PROCESSOR_386, }, 187 { "486", PCI_SUBCLASS_PROCESSOR_486, }, 188 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, }, 189 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, }, 190 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, }, 191 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, }, 192 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, }, 193 { 0 }, 194 }; 195 196 const struct pci_class pci_subclass_serialbus[] = { 197 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, }, 198 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, }, 199 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, }, 200 { "USB", PCI_SUBCLASS_SERIALBUS_USB, }, 201 /* XXX Fiber Channel/_FIBRECHANNEL */ 202 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, }, 203 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, }, 204 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, }, 205 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, }, 206 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, }, 207 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, }, 208 { 0 }, 209 }; 210 211 const struct pci_class pci_subclass_wireless[] = { 212 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, }, 213 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, }, 214 { "RF", PCI_SUBCLASS_WIRELESS_RF, }, 215 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, }, 216 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, }, 217 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, }, 218 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, }, 219 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, }, 220 { 0 }, 221 }; 222 223 const struct pci_class pci_subclass_i2o[] = { 224 { "standard", PCI_SUBCLASS_I2O_STANDARD, }, 225 { 0 }, 226 }; 227 228 const struct pci_class pci_subclass_satcom[] = { 229 { "TV", PCI_SUBCLASS_SATCOM_TV, }, 230 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, }, 231 { "voice", PCI_SUBCLASS_SATCOM_VOICE, }, 232 { "data", PCI_SUBCLASS_SATCOM_DATA, }, 233 { 0 }, 234 }; 235 236 const struct pci_class pci_subclass_crypto[] = { 237 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, }, 238 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, }, 239 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, }, 240 { 0 }, 241 }; 242 243 const struct pci_class pci_subclass_dasp[] = { 244 { "DPIO", PCI_SUBCLASS_DASP_DPIO, }, 245 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, }, 246 { "synchronization", PCI_SUBCLASS_DASP_SYNC, }, 247 { "management", PCI_SUBCLASS_DASP_MGMT, }, 248 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, }, 249 { 0 }, 250 }; 251 252 const struct pci_class pci_class[] = { 253 { "prehistoric", PCI_CLASS_PREHISTORIC, 254 pci_subclass_prehistoric, }, 255 { "mass storage", PCI_CLASS_MASS_STORAGE, 256 pci_subclass_mass_storage, }, 257 { "network", PCI_CLASS_NETWORK, 258 pci_subclass_network, }, 259 { "display", PCI_CLASS_DISPLAY, 260 pci_subclass_display, }, 261 { "multimedia", PCI_CLASS_MULTIMEDIA, 262 pci_subclass_multimedia, }, 263 { "memory", PCI_CLASS_MEMORY, 264 pci_subclass_memory, }, 265 { "bridge", PCI_CLASS_BRIDGE, 266 pci_subclass_bridge, }, 267 { "communications", PCI_CLASS_COMMUNICATIONS, 268 pci_subclass_communications, }, 269 { "system", PCI_CLASS_SYSTEM, 270 pci_subclass_system, }, 271 { "input", PCI_CLASS_INPUT, 272 pci_subclass_input, }, 273 { "dock", PCI_CLASS_DOCK, 274 pci_subclass_dock, }, 275 { "processor", PCI_CLASS_PROCESSOR, 276 pci_subclass_processor, }, 277 { "serial bus", PCI_CLASS_SERIALBUS, 278 pci_subclass_serialbus, }, 279 { "wireless", PCI_CLASS_WIRELESS, 280 pci_subclass_wireless, }, 281 { "I2O", PCI_CLASS_I2O, 282 pci_subclass_i2o, }, 283 { "satellite comm", PCI_CLASS_SATCOM, 284 pci_subclass_satcom, }, 285 { "crypto", PCI_CLASS_CRYPTO, 286 pci_subclass_crypto, }, 287 { "DASP", PCI_CLASS_DASP, 288 pci_subclass_dasp, }, 289 { "undefined", PCI_CLASS_UNDEFINED, 290 0, }, 291 { 0 }, 292 }; 293 294 #ifdef PCIVERBOSE 295 /* 296 * Descriptions of of known vendors and devices ("products"). 297 */ 298 struct pci_knowndev { 299 pci_vendor_id_t vendor; 300 pci_product_id_t product; 301 int flags; 302 char *vendorname, *productname; 303 }; 304 #define PCI_KNOWNDEV_NOPROD 0x01 /* match on vendor only */ 305 306 #include <dev/pci/pcidevs_data.h> 307 #endif /* PCIVERBOSE */ 308 309 char * 310 pci_findvendor(pcireg_t id_reg) 311 { 312 #ifdef PCIVERBOSE 313 pci_vendor_id_t vendor = PCI_VENDOR(id_reg); 314 const struct pci_knowndev *kdp; 315 316 kdp = pci_knowndevs; 317 while (kdp->vendorname != NULL) { /* all have vendor name */ 318 if (kdp->vendor == vendor) 319 break; 320 kdp++; 321 } 322 return (kdp->vendorname); 323 #else 324 return (NULL); 325 #endif 326 } 327 328 void 329 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp) 330 { 331 pci_vendor_id_t vendor; 332 pci_product_id_t product; 333 pci_class_t class; 334 pci_subclass_t subclass; 335 pci_interface_t interface; 336 pci_revision_t revision; 337 char *vendor_namep, *product_namep; 338 const struct pci_class *classp, *subclassp; 339 #ifdef PCIVERBOSE 340 const struct pci_knowndev *kdp; 341 const char *unmatched = "unknown "; 342 #else 343 const char *unmatched = ""; 344 #endif 345 346 vendor = PCI_VENDOR(id_reg); 347 product = PCI_PRODUCT(id_reg); 348 349 class = PCI_CLASS(class_reg); 350 subclass = PCI_SUBCLASS(class_reg); 351 interface = PCI_INTERFACE(class_reg); 352 revision = PCI_REVISION(class_reg); 353 354 #ifdef PCIVERBOSE 355 kdp = pci_knowndevs; 356 while (kdp->vendorname != NULL) { /* all have vendor name */ 357 if (kdp->vendor == vendor && (kdp->product == product || 358 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) 359 break; 360 kdp++; 361 } 362 if (kdp->vendorname == NULL) 363 vendor_namep = product_namep = NULL; 364 else { 365 vendor_namep = kdp->vendorname; 366 product_namep = (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0 ? 367 kdp->productname : NULL; 368 } 369 #else /* PCIVERBOSE */ 370 vendor_namep = product_namep = NULL; 371 #endif /* PCIVERBOSE */ 372 373 classp = pci_class; 374 while (classp->name != NULL) { 375 if (class == classp->val) 376 break; 377 classp++; 378 } 379 380 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 381 while (subclassp && subclassp->name != NULL) { 382 if (subclass == subclassp->val) 383 break; 384 subclassp++; 385 } 386 387 if (vendor_namep == NULL) 388 cp += sprintf(cp, "%svendor 0x%04x product 0x%04x", 389 unmatched, vendor, product); 390 else if (product_namep != NULL) 391 cp += sprintf(cp, "%s %s", vendor_namep, product_namep); 392 else 393 cp += sprintf(cp, "%s product 0x%04x", 394 vendor_namep, product); 395 if (showclass) { 396 cp += sprintf(cp, " ("); 397 if (classp->name == NULL) 398 cp += sprintf(cp, "class 0x%02x, subclass 0x%02x", 399 class, subclass); 400 else { 401 if (subclassp == NULL || subclassp->name == NULL) 402 cp += sprintf(cp, 403 "%s subclass 0x%02x", 404 classp->name, subclass); 405 else 406 cp += sprintf(cp, "%s %s", 407 subclassp->name, classp->name); 408 } 409 if (interface != 0) 410 cp += sprintf(cp, ", interface 0x%02x", interface); 411 if (revision != 0) 412 cp += sprintf(cp, ", revision 0x%02x", revision); 413 cp += sprintf(cp, ")"); 414 } 415 } 416 417 /* 418 * Print out most of the PCI configuration registers. Typically used 419 * in a device attach routine like this: 420 * 421 * #ifdef MYDEV_DEBUG 422 * printf("%s: ", sc->sc_dev.dv_xname); 423 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 424 * #endif 425 */ 426 427 #define i2o(i) ((i) * 4) 428 #define o2i(o) ((o) / 4) 429 #define onoff(str, bit) \ 430 printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off"); 431 432 static void 433 pci_conf_print_common( 434 #ifdef _KERNEL 435 pci_chipset_tag_t pc, pcitag_t tag, 436 #endif 437 const pcireg_t *regs) 438 { 439 #ifdef PCIVERBOSE 440 const struct pci_knowndev *kdp; 441 #endif 442 const struct pci_class *classp, *subclassp; 443 pcireg_t rval; 444 445 rval = regs[o2i(PCI_ID_REG)]; 446 #ifndef PCIVERBOSE 447 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 448 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 449 #else 450 for (kdp = pci_knowndevs; kdp->vendorname != NULL; kdp++) { 451 if (kdp->vendor == PCI_VENDOR(rval) && 452 (kdp->product == PCI_PRODUCT(rval) || 453 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) { 454 break; 455 } 456 } 457 if (kdp->vendorname != NULL) 458 printf(" Vendor Name: %s (0x%04x)\n", kdp->vendorname, 459 PCI_VENDOR(rval)); 460 else 461 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 462 if (kdp->productname != NULL && (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0) 463 printf(" Device Name: %s (0x%04x)\n", kdp->productname, 464 PCI_PRODUCT(rval)); 465 else 466 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 467 #endif /* PCIVERBOSE */ 468 469 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 470 471 printf(" Command register: 0x%04x\n", rval & 0xffff); 472 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 473 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 474 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 475 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 476 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 477 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 478 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 479 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 480 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 481 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 482 483 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 484 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 485 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 486 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 487 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 488 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 489 490 printf(" DEVSEL timing: "); 491 switch (rval & PCI_STATUS_DEVSEL_MASK) { 492 case PCI_STATUS_DEVSEL_FAST: 493 printf("fast"); 494 break; 495 case PCI_STATUS_DEVSEL_MEDIUM: 496 printf("medium"); 497 break; 498 case PCI_STATUS_DEVSEL_SLOW: 499 printf("slow"); 500 break; 501 default: 502 printf("unknown/reserved"); /* XXX */ 503 break; 504 } 505 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 506 507 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 508 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 509 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 510 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 511 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 512 513 rval = regs[o2i(PCI_CLASS_REG)]; 514 for (classp = pci_class; classp->name != NULL; classp++) { 515 if (PCI_CLASS(rval) == classp->val) 516 break; 517 } 518 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 519 while (subclassp && subclassp->name != NULL) { 520 if (PCI_SUBCLASS(rval) == subclassp->val) 521 break; 522 subclassp++; 523 } 524 if (classp->name != NULL) { 525 printf(" Class Name: %s (0x%02x)\n", classp->name, 526 PCI_CLASS(rval)); 527 if (subclassp != NULL && subclassp->name != NULL) 528 printf(" Subclass Name: %s (0x%02x)\n", 529 subclassp->name, PCI_SUBCLASS(rval)); 530 else 531 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 532 } else { 533 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 534 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 535 } 536 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 537 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 538 539 rval = regs[o2i(PCI_BHLC_REG)]; 540 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 541 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 542 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 543 PCI_HDRTYPE(rval)); 544 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 545 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 546 } 547 548 static int 549 pci_conf_print_bar( 550 #ifdef _KERNEL 551 pci_chipset_tag_t pc, pcitag_t tag, 552 #endif 553 const pcireg_t *regs, int reg, const char *name 554 #ifdef _KERNEL 555 , int sizebar 556 #endif 557 ) 558 { 559 int width; 560 pcireg_t rval, rval64h; 561 #ifdef _KERNEL 562 int s; 563 pcireg_t mask, mask64h; 564 #endif 565 566 width = 4; 567 568 /* 569 * Section 6.2.5.1, `Address Maps', tells us that: 570 * 571 * 1) The builtin software should have already mapped the 572 * device in a reasonable way. 573 * 574 * 2) A device which wants 2^n bytes of memory will hardwire 575 * the bottom n bits of the address to 0. As recommended, 576 * we write all 1s and see what we get back. 577 */ 578 579 rval = regs[o2i(reg)]; 580 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 581 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 582 rval64h = regs[o2i(reg + 4)]; 583 width = 8; 584 } else 585 rval64h = 0; 586 587 #ifdef _KERNEL 588 /* XXX don't size unknown memory type? */ 589 if (rval != 0 && sizebar) { 590 /* 591 * The following sequence seems to make some devices 592 * (e.g. host bus bridges, which don't normally 593 * have their space mapped) very unhappy, to 594 * the point of crashing the system. 595 * 596 * Therefore, if the mapping register is zero to 597 * start out with, don't bother trying. 598 */ 599 s = splhigh(); 600 pci_conf_write(pc, tag, reg, 0xffffffff); 601 mask = pci_conf_read(pc, tag, reg); 602 pci_conf_write(pc, tag, reg, rval); 603 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 604 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 605 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 606 mask64h = pci_conf_read(pc, tag, reg + 4); 607 pci_conf_write(pc, tag, reg + 4, rval64h); 608 } else 609 mask64h = 0; 610 splx(s); 611 } else 612 mask = mask64h = 0; 613 #endif /* _KERNEL */ 614 615 printf(" Base address register at 0x%02x", reg); 616 if (name) 617 printf(" (%s)", name); 618 printf("\n "); 619 if (rval == 0) { 620 printf("not implemented(?)\n"); 621 return width; 622 } 623 printf("type: "); 624 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 625 const char *type, *prefetch; 626 627 switch (PCI_MAPREG_MEM_TYPE(rval)) { 628 case PCI_MAPREG_MEM_TYPE_32BIT: 629 type = "32-bit"; 630 break; 631 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 632 type = "32-bit-1M"; 633 break; 634 case PCI_MAPREG_MEM_TYPE_64BIT: 635 type = "64-bit"; 636 break; 637 default: 638 type = "unknown (XXX)"; 639 break; 640 } 641 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 642 prefetch = ""; 643 else 644 prefetch = "non"; 645 printf("%s %sprefetchable memory\n", type, prefetch); 646 switch (PCI_MAPREG_MEM_TYPE(rval)) { 647 case PCI_MAPREG_MEM_TYPE_64BIT: 648 printf(" base: 0x%016llx, ", 649 PCI_MAPREG_MEM64_ADDR( 650 ((((long long) rval64h) << 32) | rval))); 651 #ifdef _KERNEL 652 if (sizebar) 653 printf("size: 0x%016llx", 654 PCI_MAPREG_MEM64_SIZE( 655 ((((long long) mask64h) << 32) | mask))); 656 else 657 #endif /* _KERNEL */ 658 printf("not sized"); 659 printf("\n"); 660 break; 661 case PCI_MAPREG_MEM_TYPE_32BIT: 662 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 663 default: 664 printf(" base: 0x%08x, ", 665 PCI_MAPREG_MEM_ADDR(rval)); 666 #ifdef _KERNEL 667 if (sizebar) 668 printf("size: 0x%08x", 669 PCI_MAPREG_MEM_SIZE(mask)); 670 else 671 #endif /* _KERNEL */ 672 printf("not sized"); 673 printf("\n"); 674 break; 675 } 676 } else { 677 #ifdef _KERNEL 678 if (sizebar) 679 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 680 #endif /* _KERNEL */ 681 printf("i/o\n"); 682 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 683 #ifdef _KERNEL 684 if (sizebar) 685 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 686 else 687 #endif /* _KERNEL */ 688 printf("not sized"); 689 printf("\n"); 690 } 691 692 return width; 693 } 694 695 static void 696 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 697 { 698 int off, needaddr, neednl; 699 700 needaddr = 1; 701 neednl = 0; 702 for (off = first; off < pastlast; off += 4) { 703 if ((off % 16) == 0 || needaddr) { 704 printf(" 0x%02x:", off); 705 needaddr = 0; 706 } 707 printf(" 0x%08x", regs[o2i(off)]); 708 neednl = 1; 709 if ((off % 16) == 12) { 710 printf("\n"); 711 neednl = 0; 712 } 713 } 714 if (neednl) 715 printf("\n"); 716 } 717 718 static void 719 pci_conf_print_type0( 720 #ifdef _KERNEL 721 pci_chipset_tag_t pc, pcitag_t tag, 722 #endif 723 const pcireg_t *regs 724 #ifdef _KERNEL 725 , int sizebars 726 #endif 727 ) 728 { 729 int off, width; 730 pcireg_t rval; 731 732 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 733 #ifdef _KERNEL 734 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 735 #else 736 width = pci_conf_print_bar(regs, off, NULL); 737 #endif 738 } 739 740 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 741 742 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 743 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 744 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 745 746 /* XXX */ 747 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 748 749 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 750 printf(" Capability list pointer: 0x%02x\n", 751 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 752 else 753 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 754 755 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 756 757 rval = regs[o2i(PCI_INTERRUPT_REG)]; 758 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 759 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 760 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 761 switch (PCI_INTERRUPT_PIN(rval)) { 762 case PCI_INTERRUPT_PIN_NONE: 763 printf("(none)"); 764 break; 765 case PCI_INTERRUPT_PIN_A: 766 printf("(pin A)"); 767 break; 768 case PCI_INTERRUPT_PIN_B: 769 printf("(pin B)"); 770 break; 771 case PCI_INTERRUPT_PIN_C: 772 printf("(pin C)"); 773 break; 774 case PCI_INTERRUPT_PIN_D: 775 printf("(pin D)"); 776 break; 777 default: 778 printf("(? ? ?)"); 779 break; 780 } 781 printf("\n"); 782 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 783 } 784 785 static void 786 pci_conf_print_caplist( 787 #ifdef _KERNEL 788 pci_chipset_tag_t pc, pcitag_t tag, 789 #endif 790 const pcireg_t *regs, int capoff) 791 { 792 int off; 793 pcireg_t rval; 794 795 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 796 off != 0; 797 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 798 rval = regs[o2i(off)]; 799 printf(" Capability register at 0x%02x\n", off); 800 801 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 802 switch (PCI_CAPLIST_CAP(rval)) { 803 case PCI_CAP_RESERVED0: 804 printf("reserved"); 805 break; 806 case PCI_CAP_PWRMGMT: 807 printf("Power Management, rev. %d.0", 808 (rval >> 0) & 0x07); /* XXX not clear */ 809 break; 810 case PCI_CAP_AGP: 811 printf("AGP, rev. %d.%d", 812 (rval >> 24) & 0x0f, 813 (rval >> 20) & 0x0f); 814 break; 815 case PCI_CAP_VPD: 816 printf("VPD"); 817 break; 818 case PCI_CAP_SLOTID: 819 printf("SlotID"); 820 break; 821 case PCI_CAP_MSI: 822 printf("MSI"); 823 break; 824 case PCI_CAP_CPCI_HOTSWAP: 825 printf("CompactPCI Hot-swapping"); 826 break; 827 case PCI_CAP_PCIX: 828 printf("PCI-X"); 829 break; 830 case PCI_CAP_LDT: 831 printf("LDT"); 832 break; 833 case PCI_CAP_VENDSPEC: 834 printf("Vendor-specific"); 835 break; 836 case PCI_CAP_DEBUGPORT: 837 printf("Debug Port"); 838 break; 839 case PCI_CAP_CPCI_RSRCCTL: 840 printf("CompactPCI Resource Control"); 841 break; 842 case PCI_CAP_HOTPLUG: 843 printf("Hot-Plug"); 844 break; 845 case PCI_CAP_AGP8: 846 printf("AGP 8x"); 847 break; 848 case PCI_CAP_SECURE: 849 printf("Secure Device"); 850 break; 851 case PCI_CAP_PCIEXPRESS: 852 printf("PCI Express"); 853 break; 854 case PCI_CAP_MSIX: 855 printf("MSI-X"); 856 break; 857 default: 858 printf("unknown"); 859 } 860 printf(")\n"); 861 } 862 } 863 864 static void 865 pci_conf_print_type1( 866 #ifdef _KERNEL 867 pci_chipset_tag_t pc, pcitag_t tag, 868 #endif 869 const pcireg_t *regs 870 #ifdef _KERNEL 871 , int sizebars 872 #endif 873 ) 874 { 875 int off, width; 876 pcireg_t rval; 877 878 /* 879 * XXX these need to be printed in more detail, need to be 880 * XXX checked against specs/docs, etc. 881 * 882 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 883 * Bridge chip documentation, and may not be correct with 884 * respect to various standards. (XXX) 885 */ 886 887 for (off = 0x10; off < 0x18; off += width) { 888 #ifdef _KERNEL 889 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 890 #else 891 width = pci_conf_print_bar(regs, off, NULL); 892 #endif 893 } 894 895 printf(" Primary bus number: 0x%02x\n", 896 (regs[o2i(0x18)] >> 0) & 0xff); 897 printf(" Secondary bus number: 0x%02x\n", 898 (regs[o2i(0x18)] >> 8) & 0xff); 899 printf(" Subordinate bus number: 0x%02x\n", 900 (regs[o2i(0x18)] >> 16) & 0xff); 901 printf(" Secondary bus latency timer: 0x%02x\n", 902 (regs[o2i(0x18)] >> 24) & 0xff); 903 904 rval = (regs[o2i(0x1c)] >> 16) & 0xffff; 905 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 906 onoff("66 MHz capable", 0x0020); 907 onoff("User Definable Features (UDF) support", 0x0040); 908 onoff("Fast back-to-back capable", 0x0080); 909 onoff("Data parity error detected", 0x0100); 910 911 printf(" DEVSEL timing: "); 912 switch (rval & 0x0600) { 913 case 0x0000: 914 printf("fast"); 915 break; 916 case 0x0200: 917 printf("medium"); 918 break; 919 case 0x0400: 920 printf("slow"); 921 break; 922 default: 923 printf("unknown/reserved"); /* XXX */ 924 break; 925 } 926 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 927 928 onoff("Signaled Target Abort", 0x0800); 929 onoff("Received Target Abort", 0x1000); 930 onoff("Received Master Abort", 0x2000); 931 onoff("System Error", 0x4000); 932 onoff("Parity Error", 0x8000); 933 934 /* XXX Print more prettily */ 935 printf(" I/O region:\n"); 936 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 937 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 938 printf(" base upper 16 bits register: 0x%04x\n", 939 (regs[o2i(0x30)] >> 0) & 0xffff); 940 printf(" limit upper 16 bits register: 0x%04x\n", 941 (regs[o2i(0x30)] >> 16) & 0xffff); 942 943 /* XXX Print more prettily */ 944 printf(" Memory region:\n"); 945 printf(" base register: 0x%04x\n", 946 (regs[o2i(0x20)] >> 0) & 0xffff); 947 printf(" limit register: 0x%04x\n", 948 (regs[o2i(0x20)] >> 16) & 0xffff); 949 950 /* XXX Print more prettily */ 951 printf(" Prefetchable memory region:\n"); 952 printf(" base register: 0x%04x\n", 953 (regs[o2i(0x24)] >> 0) & 0xffff); 954 printf(" limit register: 0x%04x\n", 955 (regs[o2i(0x24)] >> 16) & 0xffff); 956 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 957 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 958 959 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 960 printf(" Capability list pointer: 0x%02x\n", 961 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 962 else 963 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 964 965 /* XXX */ 966 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 967 968 printf(" Interrupt line: 0x%02x\n", 969 (regs[o2i(0x3c)] >> 0) & 0xff); 970 printf(" Interrupt pin: 0x%02x ", 971 (regs[o2i(0x3c)] >> 8) & 0xff); 972 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 973 case PCI_INTERRUPT_PIN_NONE: 974 printf("(none)"); 975 break; 976 case PCI_INTERRUPT_PIN_A: 977 printf("(pin A)"); 978 break; 979 case PCI_INTERRUPT_PIN_B: 980 printf("(pin B)"); 981 break; 982 case PCI_INTERRUPT_PIN_C: 983 printf("(pin C)"); 984 break; 985 case PCI_INTERRUPT_PIN_D: 986 printf("(pin D)"); 987 break; 988 default: 989 printf("(? ? ?)"); 990 break; 991 } 992 printf("\n"); 993 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 994 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 995 onoff("Parity error response", 0x0001); 996 onoff("Secondary SERR forwarding", 0x0002); 997 onoff("ISA enable", 0x0004); 998 onoff("VGA enable", 0x0008); 999 onoff("Master abort reporting", 0x0020); 1000 onoff("Secondary bus reset", 0x0040); 1001 onoff("Fast back-to-back capable", 0x0080); 1002 } 1003 1004 static void 1005 pci_conf_print_type2( 1006 #ifdef _KERNEL 1007 pci_chipset_tag_t pc, pcitag_t tag, 1008 #endif 1009 const pcireg_t *regs 1010 #ifdef _KERNEL 1011 , int sizebars 1012 #endif 1013 ) 1014 { 1015 pcireg_t rval; 1016 1017 /* 1018 * XXX these need to be printed in more detail, need to be 1019 * XXX checked against specs/docs, etc. 1020 * 1021 * This layout was cribbed from the TI PCI1130 PCI-to-CardBus 1022 * controller chip documentation, and may not be correct with 1023 * respect to various standards. (XXX) 1024 */ 1025 1026 #ifdef _KERNEL 1027 pci_conf_print_bar(pc, tag, regs, 0x10, 1028 "CardBus socket/ExCA registers", sizebars); 1029 #else 1030 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 1031 #endif 1032 1033 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1034 printf(" Capability list pointer: 0x%02x\n", 1035 PCI_CAPLIST_PTR(regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)])); 1036 else 1037 printf(" Reserved @ 0x14: 0x%04x\n", 1038 (regs[o2i(0x14)] >> 0) & 0xffff); 1039 rval = (regs[o2i(0x14)] >> 16) & 0xffff; 1040 printf(" Secondary status register: 0x%04x\n", rval); 1041 onoff("66 MHz capable", 0x0020); 1042 onoff("User Definable Features (UDF) support", 0x0040); 1043 onoff("Fast back-to-back capable", 0x0080); 1044 onoff("Data parity error detection", 0x0100); 1045 1046 printf(" DEVSEL timing: "); 1047 switch (rval & 0x0600) { 1048 case 0x0000: 1049 printf("fast"); 1050 break; 1051 case 0x0200: 1052 printf("medium"); 1053 break; 1054 case 0x0400: 1055 printf("slow"); 1056 break; 1057 default: 1058 printf("unknown/reserved"); /* XXX */ 1059 break; 1060 } 1061 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 1062 onoff("PCI target aborts terminate CardBus bus master transactions", 1063 0x0800); 1064 onoff("CardBus target aborts terminate PCI bus master transactions", 1065 0x1000); 1066 onoff("Bus initiator aborts terminate initiator transactions", 1067 0x2000); 1068 onoff("System error", 0x4000); 1069 onoff("Parity error", 0x8000); 1070 1071 printf(" PCI bus number: 0x%02x\n", 1072 (regs[o2i(0x18)] >> 0) & 0xff); 1073 printf(" CardBus bus number: 0x%02x\n", 1074 (regs[o2i(0x18)] >> 8) & 0xff); 1075 printf(" Subordinate bus number: 0x%02x\n", 1076 (regs[o2i(0x18)] >> 16) & 0xff); 1077 printf(" CardBus latency timer: 0x%02x\n", 1078 (regs[o2i(0x18)] >> 24) & 0xff); 1079 1080 /* XXX Print more prettily */ 1081 printf(" CardBus memory region 0:\n"); 1082 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1083 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1084 printf(" CardBus memory region 1:\n"); 1085 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1086 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1087 printf(" CardBus I/O region 0:\n"); 1088 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1089 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1090 printf(" CardBus I/O region 1:\n"); 1091 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1092 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1093 1094 printf(" Interrupt line: 0x%02x\n", 1095 (regs[o2i(0x3c)] >> 0) & 0xff); 1096 printf(" Interrupt pin: 0x%02x ", 1097 (regs[o2i(0x3c)] >> 8) & 0xff); 1098 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1099 case PCI_INTERRUPT_PIN_NONE: 1100 printf("(none)"); 1101 break; 1102 case PCI_INTERRUPT_PIN_A: 1103 printf("(pin A)"); 1104 break; 1105 case PCI_INTERRUPT_PIN_B: 1106 printf("(pin B)"); 1107 break; 1108 case PCI_INTERRUPT_PIN_C: 1109 printf("(pin C)"); 1110 break; 1111 case PCI_INTERRUPT_PIN_D: 1112 printf("(pin D)"); 1113 break; 1114 default: 1115 printf("(? ? ?)"); 1116 break; 1117 } 1118 printf("\n"); 1119 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1120 printf(" Bridge control register: 0x%04x\n", rval); 1121 onoff("Parity error response", 0x0001); 1122 onoff("CardBus SERR forwarding", 0x0002); 1123 onoff("ISA enable", 0x0004); 1124 onoff("VGA enable", 0x0008); 1125 onoff("CardBus master abort reporting", 0x0020); 1126 onoff("CardBus reset", 0x0040); 1127 onoff("Functional interrupts routed by ExCA registers", 0x0080); 1128 onoff("Memory window 0 prefetchable", 0x0100); 1129 onoff("Memory window 1 prefetchable", 0x0200); 1130 onoff("Write posting enable", 0x0400); 1131 1132 rval = regs[o2i(0x40)]; 1133 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1134 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1135 1136 #ifdef _KERNEL 1137 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1138 sizebars); 1139 #else 1140 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 1141 #endif 1142 } 1143 1144 void 1145 pci_conf_print( 1146 #ifdef _KERNEL 1147 pci_chipset_tag_t pc, pcitag_t tag, 1148 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 1149 #else 1150 int pcifd, u_int bus, u_int dev, u_int func 1151 #endif 1152 ) 1153 { 1154 pcireg_t regs[o2i(256)]; 1155 int off, capoff, endoff, hdrtype; 1156 const char *typename; 1157 #ifdef _KERNEL 1158 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1159 int sizebars; 1160 #else 1161 void (*typeprintfn)(const pcireg_t *); 1162 #endif 1163 1164 printf("PCI configuration registers:\n"); 1165 1166 for (off = 0; off < 256; off += 4) { 1167 #ifdef _KERNEL 1168 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1169 #else 1170 if (pcibus_conf_read(pcifd, bus, dev, func, off, 1171 ®s[o2i(off)]) == -1) 1172 regs[o2i(off)] = 0; 1173 #endif 1174 } 1175 1176 #ifdef _KERNEL 1177 sizebars = 1; 1178 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1179 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1180 sizebars = 0; 1181 #endif 1182 1183 /* common header */ 1184 printf(" Common header:\n"); 1185 pci_conf_print_regs(regs, 0, 16); 1186 1187 printf("\n"); 1188 #ifdef _KERNEL 1189 pci_conf_print_common(pc, tag, regs); 1190 #else 1191 pci_conf_print_common(regs); 1192 #endif 1193 printf("\n"); 1194 1195 /* type-dependent header */ 1196 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1197 switch (hdrtype) { /* XXX make a table, eventually */ 1198 case 0: 1199 /* Standard device header */ 1200 typename = "\"normal\" device"; 1201 typeprintfn = &pci_conf_print_type0; 1202 capoff = PCI_CAPLISTPTR_REG; 1203 endoff = 64; 1204 break; 1205 case 1: 1206 /* PCI-PCI bridge header */ 1207 typename = "PCI-PCI bridge"; 1208 typeprintfn = &pci_conf_print_type1; 1209 capoff = PCI_CAPLISTPTR_REG; 1210 endoff = 64; 1211 break; 1212 case 2: 1213 /* PCI-CardBus bridge header */ 1214 typename = "PCI-CardBus bridge"; 1215 typeprintfn = &pci_conf_print_type2; 1216 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 1217 endoff = 72; 1218 break; 1219 default: 1220 typename = NULL; 1221 typeprintfn = 0; 1222 capoff = -1; 1223 endoff = 64; 1224 break; 1225 } 1226 printf(" Type %d ", hdrtype); 1227 if (typename != NULL) 1228 printf("(%s) ", typename); 1229 printf("header:\n"); 1230 pci_conf_print_regs(regs, 16, endoff); 1231 printf("\n"); 1232 if (typeprintfn) { 1233 #ifdef _KERNEL 1234 (*typeprintfn)(pc, tag, regs, sizebars); 1235 #else 1236 (*typeprintfn)(regs); 1237 #endif 1238 } else 1239 printf(" Don't know how to pretty-print type %d header.\n", 1240 hdrtype); 1241 printf("\n"); 1242 1243 /* capability list, if present */ 1244 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1245 && (capoff > 0)) { 1246 #ifdef _KERNEL 1247 pci_conf_print_caplist(pc, tag, regs, capoff); 1248 #else 1249 pci_conf_print_caplist(regs, capoff); 1250 #endif 1251 printf("\n"); 1252 } 1253 1254 /* device-dependent header */ 1255 printf(" Device-dependent header:\n"); 1256 pci_conf_print_regs(regs, endoff, 256); 1257 printf("\n"); 1258 #ifdef _KERNEL 1259 if (printfn) 1260 (*printfn)(pc, tag, regs); 1261 else 1262 printf(" Don't know how to pretty-print device-dependent header.\n"); 1263 printf("\n"); 1264 #endif /* _KERNEL */ 1265 } 1266
Indexes created Tue Sep 23 23:09:58 GMT 2025