pci_subr.c revision 1.58
1 /* $NetBSD: pci_subr.c,v 1.58 2004/04/23 21:13:07 itojun Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.58 2004/04/23 21:13:07 itojun Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 52 #ifdef _KERNEL 53 #include <machine/intr.h> 54 #else 55 #include <pci.h> 56 #include <stdio.h> 57 #endif 58 59 #include <dev/pci/pcireg.h> 60 #ifdef _KERNEL 61 #include <dev/pci/pcivar.h> 62 #endif 63 #ifdef PCIVERBOSE 64 #include <dev/pci/pcidevs.h> 65 #endif 66 67 /* 68 * Descriptions of known PCI classes and subclasses. 69 * 70 * Subclasses are described in the same way as classes, but have a 71 * NULL subclass pointer. 72 */ 73 struct pci_class { 74 const char *name; 75 int val; /* as wide as pci_{,sub}class_t */ 76 const struct pci_class *subclasses; 77 }; 78 79 const struct pci_class pci_subclass_prehistoric[] = { 80 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, }, 81 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, }, 82 { 0 } 83 }; 84 85 const struct pci_class pci_subclass_mass_storage[] = { 86 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, }, 87 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, }, 88 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, }, 89 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, }, 90 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, }, 91 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, }, 92 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, }, 93 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, }, 94 { 0 }, 95 }; 96 97 const struct pci_class pci_subclass_network[] = { 98 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, }, 99 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, }, 100 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, }, 101 { "ATM", PCI_SUBCLASS_NETWORK_ATM, }, 102 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, }, 103 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, }, 104 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, }, 105 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, }, 106 { 0 }, 107 }; 108 109 const struct pci_class pci_subclass_display[] = { 110 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, }, 111 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, }, 112 { "3D", PCI_SUBCLASS_DISPLAY_3D, }, 113 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, }, 114 { 0 }, 115 }; 116 117 const struct pci_class pci_subclass_multimedia[] = { 118 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, }, 119 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, }, 120 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, }, 121 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, }, 122 { 0 }, 123 }; 124 125 const struct pci_class pci_subclass_memory[] = { 126 { "RAM", PCI_SUBCLASS_MEMORY_RAM, }, 127 { "flash", PCI_SUBCLASS_MEMORY_FLASH, }, 128 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, }, 129 { 0 }, 130 }; 131 132 const struct pci_class pci_subclass_bridge[] = { 133 { "host", PCI_SUBCLASS_BRIDGE_HOST, }, 134 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, }, 135 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, }, 136 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, }, 137 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, }, 138 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, }, 139 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, }, 140 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, }, 141 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, }, 142 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, }, 143 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, }, 144 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, }, 145 { 0 }, 146 }; 147 148 const struct pci_class pci_subclass_communications[] = { 149 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, }, 150 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, }, 151 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, }, 152 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, }, 153 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, }, 154 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, }, 155 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, }, 156 { 0 }, 157 }; 158 159 const struct pci_class pci_subclass_system[] = { 160 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, }, 161 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, }, 162 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, }, 163 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, }, 164 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_RTC, }, 165 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, }, 166 { 0 }, 167 }; 168 169 const struct pci_class pci_subclass_input[] = { 170 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, }, 171 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, }, 172 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, }, 173 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, }, 174 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, }, 175 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, }, 176 { 0 }, 177 }; 178 179 const struct pci_class pci_subclass_dock[] = { 180 { "generic", PCI_SUBCLASS_DOCK_GENERIC, }, 181 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, }, 182 { 0 }, 183 }; 184 185 const struct pci_class pci_subclass_processor[] = { 186 { "386", PCI_SUBCLASS_PROCESSOR_386, }, 187 { "486", PCI_SUBCLASS_PROCESSOR_486, }, 188 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, }, 189 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, }, 190 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, }, 191 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, }, 192 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, }, 193 { 0 }, 194 }; 195 196 const struct pci_class pci_subclass_serialbus[] = { 197 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, }, 198 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, }, 199 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, }, 200 { "USB", PCI_SUBCLASS_SERIALBUS_USB, }, 201 /* XXX Fiber Channel/_FIBRECHANNEL */ 202 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, }, 203 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, }, 204 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, }, 205 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, }, 206 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, }, 207 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, }, 208 { 0 }, 209 }; 210 211 const struct pci_class pci_subclass_wireless[] = { 212 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, }, 213 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, }, 214 { "RF", PCI_SUBCLASS_WIRELESS_RF, }, 215 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, }, 216 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, }, 217 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, }, 218 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, }, 219 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, }, 220 { 0 }, 221 }; 222 223 const struct pci_class pci_subclass_i2o[] = { 224 { "standard", PCI_SUBCLASS_I2O_STANDARD, }, 225 { 0 }, 226 }; 227 228 const struct pci_class pci_subclass_satcom[] = { 229 { "TV", PCI_SUBCLASS_SATCOM_TV, }, 230 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, }, 231 { "voice", PCI_SUBCLASS_SATCOM_VOICE, }, 232 { "data", PCI_SUBCLASS_SATCOM_DATA, }, 233 { 0 }, 234 }; 235 236 const struct pci_class pci_subclass_crypto[] = { 237 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, }, 238 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, }, 239 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, }, 240 { 0 }, 241 }; 242 243 const struct pci_class pci_subclass_dasp[] = { 244 { "DPIO", PCI_SUBCLASS_DASP_DPIO, }, 245 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, }, 246 { "synchronization", PCI_SUBCLASS_DASP_SYNC, }, 247 { "management", PCI_SUBCLASS_DASP_MGMT, }, 248 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, }, 249 { 0 }, 250 }; 251 252 const struct pci_class pci_class[] = { 253 { "prehistoric", PCI_CLASS_PREHISTORIC, 254 pci_subclass_prehistoric, }, 255 { "mass storage", PCI_CLASS_MASS_STORAGE, 256 pci_subclass_mass_storage, }, 257 { "network", PCI_CLASS_NETWORK, 258 pci_subclass_network, }, 259 { "display", PCI_CLASS_DISPLAY, 260 pci_subclass_display, }, 261 { "multimedia", PCI_CLASS_MULTIMEDIA, 262 pci_subclass_multimedia, }, 263 { "memory", PCI_CLASS_MEMORY, 264 pci_subclass_memory, }, 265 { "bridge", PCI_CLASS_BRIDGE, 266 pci_subclass_bridge, }, 267 { "communications", PCI_CLASS_COMMUNICATIONS, 268 pci_subclass_communications, }, 269 { "system", PCI_CLASS_SYSTEM, 270 pci_subclass_system, }, 271 { "input", PCI_CLASS_INPUT, 272 pci_subclass_input, }, 273 { "dock", PCI_CLASS_DOCK, 274 pci_subclass_dock, }, 275 { "processor", PCI_CLASS_PROCESSOR, 276 pci_subclass_processor, }, 277 { "serial bus", PCI_CLASS_SERIALBUS, 278 pci_subclass_serialbus, }, 279 { "wireless", PCI_CLASS_WIRELESS, 280 pci_subclass_wireless, }, 281 { "I2O", PCI_CLASS_I2O, 282 pci_subclass_i2o, }, 283 { "satellite comm", PCI_CLASS_SATCOM, 284 pci_subclass_satcom, }, 285 { "crypto", PCI_CLASS_CRYPTO, 286 pci_subclass_crypto, }, 287 { "DASP", PCI_CLASS_DASP, 288 pci_subclass_dasp, }, 289 { "undefined", PCI_CLASS_UNDEFINED, 290 0, }, 291 { 0 }, 292 }; 293 294 #ifdef PCIVERBOSE 295 /* 296 * Descriptions of of known vendors and devices ("products"). 297 */ 298 struct pci_knowndev { 299 pci_vendor_id_t vendor; 300 pci_product_id_t product; 301 int flags; 302 char *vendorname, *productname; 303 }; 304 #define PCI_KNOWNDEV_NOPROD 0x01 /* match on vendor only */ 305 306 #include <dev/pci/pcidevs_data.h> 307 #endif /* PCIVERBOSE */ 308 309 char * 310 pci_findvendor(pcireg_t id_reg) 311 { 312 #ifdef PCIVERBOSE 313 pci_vendor_id_t vendor = PCI_VENDOR(id_reg); 314 const struct pci_knowndev *kdp; 315 316 kdp = pci_knowndevs; 317 while (kdp->vendorname != NULL) { /* all have vendor name */ 318 if (kdp->vendor == vendor) 319 break; 320 kdp++; 321 } 322 return (kdp->vendorname); 323 #else 324 return (NULL); 325 #endif 326 } 327 328 void 329 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 330 size_t l) 331 { 332 pci_vendor_id_t vendor; 333 pci_product_id_t product; 334 pci_class_t class; 335 pci_subclass_t subclass; 336 pci_interface_t interface; 337 pci_revision_t revision; 338 char *vendor_namep, *product_namep; 339 const struct pci_class *classp, *subclassp; 340 #ifdef PCIVERBOSE 341 const struct pci_knowndev *kdp; 342 const char *unmatched = "unknown "; 343 #else 344 const char *unmatched = ""; 345 #endif 346 char *ep; 347 348 ep = cp + l; 349 350 vendor = PCI_VENDOR(id_reg); 351 product = PCI_PRODUCT(id_reg); 352 353 class = PCI_CLASS(class_reg); 354 subclass = PCI_SUBCLASS(class_reg); 355 interface = PCI_INTERFACE(class_reg); 356 revision = PCI_REVISION(class_reg); 357 358 #ifdef PCIVERBOSE 359 kdp = pci_knowndevs; 360 while (kdp->vendorname != NULL) { /* all have vendor name */ 361 if (kdp->vendor == vendor && (kdp->product == product || 362 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) 363 break; 364 kdp++; 365 } 366 if (kdp->vendorname == NULL) 367 vendor_namep = product_namep = NULL; 368 else { 369 vendor_namep = kdp->vendorname; 370 product_namep = (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0 ? 371 kdp->productname : NULL; 372 } 373 #else /* PCIVERBOSE */ 374 vendor_namep = product_namep = NULL; 375 #endif /* PCIVERBOSE */ 376 377 classp = pci_class; 378 while (classp->name != NULL) { 379 if (class == classp->val) 380 break; 381 classp++; 382 } 383 384 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 385 while (subclassp && subclassp->name != NULL) { 386 if (subclass == subclassp->val) 387 break; 388 subclassp++; 389 } 390 391 if (vendor_namep == NULL) 392 cp += snprintf(cp, ep - cp, "%svendor 0x%04x product 0x%04x", 393 unmatched, vendor, product); 394 else if (product_namep != NULL) 395 cp += snprintf(cp, ep - cp, "%s %s", vendor_namep, 396 product_namep); 397 else 398 cp += snprintf(cp, ep - cp, "%s product 0x%04x", 399 vendor_namep, product); 400 if (showclass) { 401 cp += snprintf(cp, ep - cp, " ("); 402 if (classp->name == NULL) 403 cp += snprintf(cp, ep - cp, 404 "class 0x%02x, subclass 0x%02x", class, subclass); 405 else { 406 if (subclassp == NULL || subclassp->name == NULL) 407 cp += snprintf(cp, ep - cp, 408 "%s subclass 0x%02x", 409 classp->name, subclass); 410 else 411 cp += snprintf(cp, ep - cp, "%s %s", 412 subclassp->name, classp->name); 413 } 414 if (interface != 0) 415 cp += snprintf(cp, ep - cp, ", interface 0x%02x", 416 interface); 417 if (revision != 0) 418 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 419 revision); 420 cp += snprintf(cp, ep - cp, ")"); 421 } 422 } 423 424 /* 425 * Print out most of the PCI configuration registers. Typically used 426 * in a device attach routine like this: 427 * 428 * #ifdef MYDEV_DEBUG 429 * printf("%s: ", sc->sc_dev.dv_xname); 430 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 431 * #endif 432 */ 433 434 #define i2o(i) ((i) * 4) 435 #define o2i(o) ((o) / 4) 436 #define onoff(str, bit) \ 437 printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off"); 438 439 static void 440 pci_conf_print_common( 441 #ifdef _KERNEL 442 pci_chipset_tag_t pc, pcitag_t tag, 443 #endif 444 const pcireg_t *regs) 445 { 446 #ifdef PCIVERBOSE 447 const struct pci_knowndev *kdp; 448 #endif 449 const struct pci_class *classp, *subclassp; 450 pcireg_t rval; 451 452 rval = regs[o2i(PCI_ID_REG)]; 453 #ifndef PCIVERBOSE 454 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 455 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 456 #else 457 for (kdp = pci_knowndevs; kdp->vendorname != NULL; kdp++) { 458 if (kdp->vendor == PCI_VENDOR(rval) && 459 (kdp->product == PCI_PRODUCT(rval) || 460 (kdp->flags & PCI_KNOWNDEV_NOPROD) != 0)) { 461 break; 462 } 463 } 464 if (kdp->vendorname != NULL) 465 printf(" Vendor Name: %s (0x%04x)\n", kdp->vendorname, 466 PCI_VENDOR(rval)); 467 else 468 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 469 if (kdp->productname != NULL && (kdp->flags & PCI_KNOWNDEV_NOPROD) == 0) 470 printf(" Device Name: %s (0x%04x)\n", kdp->productname, 471 PCI_PRODUCT(rval)); 472 else 473 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 474 #endif /* PCIVERBOSE */ 475 476 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 477 478 printf(" Command register: 0x%04x\n", rval & 0xffff); 479 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 480 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 481 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 482 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 483 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 484 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 485 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 486 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 487 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 488 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 489 490 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 491 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 492 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 493 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 494 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 495 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 496 497 printf(" DEVSEL timing: "); 498 switch (rval & PCI_STATUS_DEVSEL_MASK) { 499 case PCI_STATUS_DEVSEL_FAST: 500 printf("fast"); 501 break; 502 case PCI_STATUS_DEVSEL_MEDIUM: 503 printf("medium"); 504 break; 505 case PCI_STATUS_DEVSEL_SLOW: 506 printf("slow"); 507 break; 508 default: 509 printf("unknown/reserved"); /* XXX */ 510 break; 511 } 512 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 513 514 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 515 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 516 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 517 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 518 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 519 520 rval = regs[o2i(PCI_CLASS_REG)]; 521 for (classp = pci_class; classp->name != NULL; classp++) { 522 if (PCI_CLASS(rval) == classp->val) 523 break; 524 } 525 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 526 while (subclassp && subclassp->name != NULL) { 527 if (PCI_SUBCLASS(rval) == subclassp->val) 528 break; 529 subclassp++; 530 } 531 if (classp->name != NULL) { 532 printf(" Class Name: %s (0x%02x)\n", classp->name, 533 PCI_CLASS(rval)); 534 if (subclassp != NULL && subclassp->name != NULL) 535 printf(" Subclass Name: %s (0x%02x)\n", 536 subclassp->name, PCI_SUBCLASS(rval)); 537 else 538 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 539 } else { 540 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 541 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 542 } 543 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 544 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 545 546 rval = regs[o2i(PCI_BHLC_REG)]; 547 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 548 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 549 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 550 PCI_HDRTYPE(rval)); 551 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 552 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 553 } 554 555 static int 556 pci_conf_print_bar( 557 #ifdef _KERNEL 558 pci_chipset_tag_t pc, pcitag_t tag, 559 #endif 560 const pcireg_t *regs, int reg, const char *name 561 #ifdef _KERNEL 562 , int sizebar 563 #endif 564 ) 565 { 566 int width; 567 pcireg_t rval, rval64h; 568 #ifdef _KERNEL 569 int s; 570 pcireg_t mask, mask64h; 571 #endif 572 573 width = 4; 574 575 /* 576 * Section 6.2.5.1, `Address Maps', tells us that: 577 * 578 * 1) The builtin software should have already mapped the 579 * device in a reasonable way. 580 * 581 * 2) A device which wants 2^n bytes of memory will hardwire 582 * the bottom n bits of the address to 0. As recommended, 583 * we write all 1s and see what we get back. 584 */ 585 586 rval = regs[o2i(reg)]; 587 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 588 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 589 rval64h = regs[o2i(reg + 4)]; 590 width = 8; 591 } else 592 rval64h = 0; 593 594 #ifdef _KERNEL 595 /* XXX don't size unknown memory type? */ 596 if (rval != 0 && sizebar) { 597 /* 598 * The following sequence seems to make some devices 599 * (e.g. host bus bridges, which don't normally 600 * have their space mapped) very unhappy, to 601 * the point of crashing the system. 602 * 603 * Therefore, if the mapping register is zero to 604 * start out with, don't bother trying. 605 */ 606 s = splhigh(); 607 pci_conf_write(pc, tag, reg, 0xffffffff); 608 mask = pci_conf_read(pc, tag, reg); 609 pci_conf_write(pc, tag, reg, rval); 610 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 611 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 612 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 613 mask64h = pci_conf_read(pc, tag, reg + 4); 614 pci_conf_write(pc, tag, reg + 4, rval64h); 615 } else 616 mask64h = 0; 617 splx(s); 618 } else 619 mask = mask64h = 0; 620 #endif /* _KERNEL */ 621 622 printf(" Base address register at 0x%02x", reg); 623 if (name) 624 printf(" (%s)", name); 625 printf("\n "); 626 if (rval == 0) { 627 printf("not implemented(?)\n"); 628 return width; 629 } 630 printf("type: "); 631 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 632 const char *type, *prefetch; 633 634 switch (PCI_MAPREG_MEM_TYPE(rval)) { 635 case PCI_MAPREG_MEM_TYPE_32BIT: 636 type = "32-bit"; 637 break; 638 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 639 type = "32-bit-1M"; 640 break; 641 case PCI_MAPREG_MEM_TYPE_64BIT: 642 type = "64-bit"; 643 break; 644 default: 645 type = "unknown (XXX)"; 646 break; 647 } 648 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 649 prefetch = ""; 650 else 651 prefetch = "non"; 652 printf("%s %sprefetchable memory\n", type, prefetch); 653 switch (PCI_MAPREG_MEM_TYPE(rval)) { 654 case PCI_MAPREG_MEM_TYPE_64BIT: 655 printf(" base: 0x%016llx, ", 656 PCI_MAPREG_MEM64_ADDR( 657 ((((long long) rval64h) << 32) | rval))); 658 #ifdef _KERNEL 659 if (sizebar) 660 printf("size: 0x%016llx", 661 PCI_MAPREG_MEM64_SIZE( 662 ((((long long) mask64h) << 32) | mask))); 663 else 664 #endif /* _KERNEL */ 665 printf("not sized"); 666 printf("\n"); 667 break; 668 case PCI_MAPREG_MEM_TYPE_32BIT: 669 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 670 default: 671 printf(" base: 0x%08x, ", 672 PCI_MAPREG_MEM_ADDR(rval)); 673 #ifdef _KERNEL 674 if (sizebar) 675 printf("size: 0x%08x", 676 PCI_MAPREG_MEM_SIZE(mask)); 677 else 678 #endif /* _KERNEL */ 679 printf("not sized"); 680 printf("\n"); 681 break; 682 } 683 } else { 684 #ifdef _KERNEL 685 if (sizebar) 686 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 687 #endif /* _KERNEL */ 688 printf("i/o\n"); 689 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 690 #ifdef _KERNEL 691 if (sizebar) 692 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 693 else 694 #endif /* _KERNEL */ 695 printf("not sized"); 696 printf("\n"); 697 } 698 699 return width; 700 } 701 702 static void 703 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 704 { 705 int off, needaddr, neednl; 706 707 needaddr = 1; 708 neednl = 0; 709 for (off = first; off < pastlast; off += 4) { 710 if ((off % 16) == 0 || needaddr) { 711 printf(" 0x%02x:", off); 712 needaddr = 0; 713 } 714 printf(" 0x%08x", regs[o2i(off)]); 715 neednl = 1; 716 if ((off % 16) == 12) { 717 printf("\n"); 718 neednl = 0; 719 } 720 } 721 if (neednl) 722 printf("\n"); 723 } 724 725 static void 726 pci_conf_print_type0( 727 #ifdef _KERNEL 728 pci_chipset_tag_t pc, pcitag_t tag, 729 #endif 730 const pcireg_t *regs 731 #ifdef _KERNEL 732 , int sizebars 733 #endif 734 ) 735 { 736 int off, width; 737 pcireg_t rval; 738 739 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 740 #ifdef _KERNEL 741 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 742 #else 743 width = pci_conf_print_bar(regs, off, NULL); 744 #endif 745 } 746 747 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 748 749 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 750 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 751 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 752 753 /* XXX */ 754 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 755 756 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 757 printf(" Capability list pointer: 0x%02x\n", 758 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 759 else 760 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 761 762 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 763 764 rval = regs[o2i(PCI_INTERRUPT_REG)]; 765 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 766 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 767 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 768 switch (PCI_INTERRUPT_PIN(rval)) { 769 case PCI_INTERRUPT_PIN_NONE: 770 printf("(none)"); 771 break; 772 case PCI_INTERRUPT_PIN_A: 773 printf("(pin A)"); 774 break; 775 case PCI_INTERRUPT_PIN_B: 776 printf("(pin B)"); 777 break; 778 case PCI_INTERRUPT_PIN_C: 779 printf("(pin C)"); 780 break; 781 case PCI_INTERRUPT_PIN_D: 782 printf("(pin D)"); 783 break; 784 default: 785 printf("(? ? ?)"); 786 break; 787 } 788 printf("\n"); 789 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 790 } 791 792 static void 793 pci_conf_print_caplist( 794 #ifdef _KERNEL 795 pci_chipset_tag_t pc, pcitag_t tag, 796 #endif 797 const pcireg_t *regs, int capoff) 798 { 799 int off; 800 pcireg_t rval; 801 802 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 803 off != 0; 804 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 805 rval = regs[o2i(off)]; 806 printf(" Capability register at 0x%02x\n", off); 807 808 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 809 switch (PCI_CAPLIST_CAP(rval)) { 810 case PCI_CAP_RESERVED0: 811 printf("reserved"); 812 break; 813 case PCI_CAP_PWRMGMT: 814 printf("Power Management, rev. %d.0", 815 (rval >> 0) & 0x07); /* XXX not clear */ 816 break; 817 case PCI_CAP_AGP: 818 printf("AGP, rev. %d.%d", 819 PCI_CAP_AGP_MAJOR(rval), 820 PCI_CAP_AGP_MINOR(rval)); 821 break; 822 case PCI_CAP_VPD: 823 printf("VPD"); 824 break; 825 case PCI_CAP_SLOTID: 826 printf("SlotID"); 827 break; 828 case PCI_CAP_MSI: 829 printf("MSI"); 830 break; 831 case PCI_CAP_CPCI_HOTSWAP: 832 printf("CompactPCI Hot-swapping"); 833 break; 834 case PCI_CAP_PCIX: 835 printf("PCI-X"); 836 break; 837 case PCI_CAP_LDT: 838 printf("LDT"); 839 break; 840 case PCI_CAP_VENDSPEC: 841 printf("Vendor-specific"); 842 break; 843 case PCI_CAP_DEBUGPORT: 844 printf("Debug Port"); 845 break; 846 case PCI_CAP_CPCI_RSRCCTL: 847 printf("CompactPCI Resource Control"); 848 break; 849 case PCI_CAP_HOTPLUG: 850 printf("Hot-Plug"); 851 break; 852 case PCI_CAP_AGP8: 853 printf("AGP 8x"); 854 break; 855 case PCI_CAP_SECURE: 856 printf("Secure Device"); 857 break; 858 case PCI_CAP_PCIEXPRESS: 859 printf("PCI Express"); 860 break; 861 case PCI_CAP_MSIX: 862 printf("MSI-X"); 863 break; 864 default: 865 printf("unknown"); 866 } 867 printf(")\n"); 868 } 869 } 870 871 static void 872 pci_conf_print_type1( 873 #ifdef _KERNEL 874 pci_chipset_tag_t pc, pcitag_t tag, 875 #endif 876 const pcireg_t *regs 877 #ifdef _KERNEL 878 , int sizebars 879 #endif 880 ) 881 { 882 int off, width; 883 pcireg_t rval; 884 885 /* 886 * XXX these need to be printed in more detail, need to be 887 * XXX checked against specs/docs, etc. 888 * 889 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 890 * Bridge chip documentation, and may not be correct with 891 * respect to various standards. (XXX) 892 */ 893 894 for (off = 0x10; off < 0x18; off += width) { 895 #ifdef _KERNEL 896 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 897 #else 898 width = pci_conf_print_bar(regs, off, NULL); 899 #endif 900 } 901 902 printf(" Primary bus number: 0x%02x\n", 903 (regs[o2i(0x18)] >> 0) & 0xff); 904 printf(" Secondary bus number: 0x%02x\n", 905 (regs[o2i(0x18)] >> 8) & 0xff); 906 printf(" Subordinate bus number: 0x%02x\n", 907 (regs[o2i(0x18)] >> 16) & 0xff); 908 printf(" Secondary bus latency timer: 0x%02x\n", 909 (regs[o2i(0x18)] >> 24) & 0xff); 910 911 rval = (regs[o2i(0x1c)] >> 16) & 0xffff; 912 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 913 onoff("66 MHz capable", 0x0020); 914 onoff("User Definable Features (UDF) support", 0x0040); 915 onoff("Fast back-to-back capable", 0x0080); 916 onoff("Data parity error detected", 0x0100); 917 918 printf(" DEVSEL timing: "); 919 switch (rval & 0x0600) { 920 case 0x0000: 921 printf("fast"); 922 break; 923 case 0x0200: 924 printf("medium"); 925 break; 926 case 0x0400: 927 printf("slow"); 928 break; 929 default: 930 printf("unknown/reserved"); /* XXX */ 931 break; 932 } 933 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 934 935 onoff("Signaled Target Abort", 0x0800); 936 onoff("Received Target Abort", 0x1000); 937 onoff("Received Master Abort", 0x2000); 938 onoff("System Error", 0x4000); 939 onoff("Parity Error", 0x8000); 940 941 /* XXX Print more prettily */ 942 printf(" I/O region:\n"); 943 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 944 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 945 printf(" base upper 16 bits register: 0x%04x\n", 946 (regs[o2i(0x30)] >> 0) & 0xffff); 947 printf(" limit upper 16 bits register: 0x%04x\n", 948 (regs[o2i(0x30)] >> 16) & 0xffff); 949 950 /* XXX Print more prettily */ 951 printf(" Memory region:\n"); 952 printf(" base register: 0x%04x\n", 953 (regs[o2i(0x20)] >> 0) & 0xffff); 954 printf(" limit register: 0x%04x\n", 955 (regs[o2i(0x20)] >> 16) & 0xffff); 956 957 /* XXX Print more prettily */ 958 printf(" Prefetchable memory region:\n"); 959 printf(" base register: 0x%04x\n", 960 (regs[o2i(0x24)] >> 0) & 0xffff); 961 printf(" limit register: 0x%04x\n", 962 (regs[o2i(0x24)] >> 16) & 0xffff); 963 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 964 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 965 966 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 967 printf(" Capability list pointer: 0x%02x\n", 968 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 969 else 970 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 971 972 /* XXX */ 973 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 974 975 printf(" Interrupt line: 0x%02x\n", 976 (regs[o2i(0x3c)] >> 0) & 0xff); 977 printf(" Interrupt pin: 0x%02x ", 978 (regs[o2i(0x3c)] >> 8) & 0xff); 979 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 980 case PCI_INTERRUPT_PIN_NONE: 981 printf("(none)"); 982 break; 983 case PCI_INTERRUPT_PIN_A: 984 printf("(pin A)"); 985 break; 986 case PCI_INTERRUPT_PIN_B: 987 printf("(pin B)"); 988 break; 989 case PCI_INTERRUPT_PIN_C: 990 printf("(pin C)"); 991 break; 992 case PCI_INTERRUPT_PIN_D: 993 printf("(pin D)"); 994 break; 995 default: 996 printf("(? ? ?)"); 997 break; 998 } 999 printf("\n"); 1000 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1001 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 1002 onoff("Parity error response", 0x0001); 1003 onoff("Secondary SERR forwarding", 0x0002); 1004 onoff("ISA enable", 0x0004); 1005 onoff("VGA enable", 0x0008); 1006 onoff("Master abort reporting", 0x0020); 1007 onoff("Secondary bus reset", 0x0040); 1008 onoff("Fast back-to-back capable", 0x0080); 1009 } 1010 1011 static void 1012 pci_conf_print_type2( 1013 #ifdef _KERNEL 1014 pci_chipset_tag_t pc, pcitag_t tag, 1015 #endif 1016 const pcireg_t *regs 1017 #ifdef _KERNEL 1018 , int sizebars 1019 #endif 1020 ) 1021 { 1022 pcireg_t rval; 1023 1024 /* 1025 * XXX these need to be printed in more detail, need to be 1026 * XXX checked against specs/docs, etc. 1027 * 1028 * This layout was cribbed from the TI PCI1130 PCI-to-CardBus 1029 * controller chip documentation, and may not be correct with 1030 * respect to various standards. (XXX) 1031 */ 1032 1033 #ifdef _KERNEL 1034 pci_conf_print_bar(pc, tag, regs, 0x10, 1035 "CardBus socket/ExCA registers", sizebars); 1036 #else 1037 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 1038 #endif 1039 1040 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1041 printf(" Capability list pointer: 0x%02x\n", 1042 PCI_CAPLIST_PTR(regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)])); 1043 else 1044 printf(" Reserved @ 0x14: 0x%04x\n", 1045 (regs[o2i(0x14)] >> 0) & 0xffff); 1046 rval = (regs[o2i(0x14)] >> 16) & 0xffff; 1047 printf(" Secondary status register: 0x%04x\n", rval); 1048 onoff("66 MHz capable", 0x0020); 1049 onoff("User Definable Features (UDF) support", 0x0040); 1050 onoff("Fast back-to-back capable", 0x0080); 1051 onoff("Data parity error detection", 0x0100); 1052 1053 printf(" DEVSEL timing: "); 1054 switch (rval & 0x0600) { 1055 case 0x0000: 1056 printf("fast"); 1057 break; 1058 case 0x0200: 1059 printf("medium"); 1060 break; 1061 case 0x0400: 1062 printf("slow"); 1063 break; 1064 default: 1065 printf("unknown/reserved"); /* XXX */ 1066 break; 1067 } 1068 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 1069 onoff("PCI target aborts terminate CardBus bus master transactions", 1070 0x0800); 1071 onoff("CardBus target aborts terminate PCI bus master transactions", 1072 0x1000); 1073 onoff("Bus initiator aborts terminate initiator transactions", 1074 0x2000); 1075 onoff("System error", 0x4000); 1076 onoff("Parity error", 0x8000); 1077 1078 printf(" PCI bus number: 0x%02x\n", 1079 (regs[o2i(0x18)] >> 0) & 0xff); 1080 printf(" CardBus bus number: 0x%02x\n", 1081 (regs[o2i(0x18)] >> 8) & 0xff); 1082 printf(" Subordinate bus number: 0x%02x\n", 1083 (regs[o2i(0x18)] >> 16) & 0xff); 1084 printf(" CardBus latency timer: 0x%02x\n", 1085 (regs[o2i(0x18)] >> 24) & 0xff); 1086 1087 /* XXX Print more prettily */ 1088 printf(" CardBus memory region 0:\n"); 1089 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1090 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1091 printf(" CardBus memory region 1:\n"); 1092 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1093 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1094 printf(" CardBus I/O region 0:\n"); 1095 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1096 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1097 printf(" CardBus I/O region 1:\n"); 1098 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1099 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1100 1101 printf(" Interrupt line: 0x%02x\n", 1102 (regs[o2i(0x3c)] >> 0) & 0xff); 1103 printf(" Interrupt pin: 0x%02x ", 1104 (regs[o2i(0x3c)] >> 8) & 0xff); 1105 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1106 case PCI_INTERRUPT_PIN_NONE: 1107 printf("(none)"); 1108 break; 1109 case PCI_INTERRUPT_PIN_A: 1110 printf("(pin A)"); 1111 break; 1112 case PCI_INTERRUPT_PIN_B: 1113 printf("(pin B)"); 1114 break; 1115 case PCI_INTERRUPT_PIN_C: 1116 printf("(pin C)"); 1117 break; 1118 case PCI_INTERRUPT_PIN_D: 1119 printf("(pin D)"); 1120 break; 1121 default: 1122 printf("(? ? ?)"); 1123 break; 1124 } 1125 printf("\n"); 1126 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1127 printf(" Bridge control register: 0x%04x\n", rval); 1128 onoff("Parity error response", 0x0001); 1129 onoff("CardBus SERR forwarding", 0x0002); 1130 onoff("ISA enable", 0x0004); 1131 onoff("VGA enable", 0x0008); 1132 onoff("CardBus master abort reporting", 0x0020); 1133 onoff("CardBus reset", 0x0040); 1134 onoff("Functional interrupts routed by ExCA registers", 0x0080); 1135 onoff("Memory window 0 prefetchable", 0x0100); 1136 onoff("Memory window 1 prefetchable", 0x0200); 1137 onoff("Write posting enable", 0x0400); 1138 1139 rval = regs[o2i(0x40)]; 1140 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1141 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1142 1143 #ifdef _KERNEL 1144 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1145 sizebars); 1146 #else 1147 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 1148 #endif 1149 } 1150 1151 void 1152 pci_conf_print( 1153 #ifdef _KERNEL 1154 pci_chipset_tag_t pc, pcitag_t tag, 1155 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 1156 #else 1157 int pcifd, u_int bus, u_int dev, u_int func 1158 #endif 1159 ) 1160 { 1161 pcireg_t regs[o2i(256)]; 1162 int off, capoff, endoff, hdrtype; 1163 const char *typename; 1164 #ifdef _KERNEL 1165 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1166 int sizebars; 1167 #else 1168 void (*typeprintfn)(const pcireg_t *); 1169 #endif 1170 1171 printf("PCI configuration registers:\n"); 1172 1173 for (off = 0; off < 256; off += 4) { 1174 #ifdef _KERNEL 1175 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1176 #else 1177 if (pcibus_conf_read(pcifd, bus, dev, func, off, 1178 ®s[o2i(off)]) == -1) 1179 regs[o2i(off)] = 0; 1180 #endif 1181 } 1182 1183 #ifdef _KERNEL 1184 sizebars = 1; 1185 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1186 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1187 sizebars = 0; 1188 #endif 1189 1190 /* common header */ 1191 printf(" Common header:\n"); 1192 pci_conf_print_regs(regs, 0, 16); 1193 1194 printf("\n"); 1195 #ifdef _KERNEL 1196 pci_conf_print_common(pc, tag, regs); 1197 #else 1198 pci_conf_print_common(regs); 1199 #endif 1200 printf("\n"); 1201 1202 /* type-dependent header */ 1203 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1204 switch (hdrtype) { /* XXX make a table, eventually */ 1205 case 0: 1206 /* Standard device header */ 1207 typename = "\"normal\" device"; 1208 typeprintfn = &pci_conf_print_type0; 1209 capoff = PCI_CAPLISTPTR_REG; 1210 endoff = 64; 1211 break; 1212 case 1: 1213 /* PCI-PCI bridge header */ 1214 typename = "PCI-PCI bridge"; 1215 typeprintfn = &pci_conf_print_type1; 1216 capoff = PCI_CAPLISTPTR_REG; 1217 endoff = 64; 1218 break; 1219 case 2: 1220 /* PCI-CardBus bridge header */ 1221 typename = "PCI-CardBus bridge"; 1222 typeprintfn = &pci_conf_print_type2; 1223 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 1224 endoff = 72; 1225 break; 1226 default: 1227 typename = NULL; 1228 typeprintfn = 0; 1229 capoff = -1; 1230 endoff = 64; 1231 break; 1232 } 1233 printf(" Type %d ", hdrtype); 1234 if (typename != NULL) 1235 printf("(%s) ", typename); 1236 printf("header:\n"); 1237 pci_conf_print_regs(regs, 16, endoff); 1238 printf("\n"); 1239 if (typeprintfn) { 1240 #ifdef _KERNEL 1241 (*typeprintfn)(pc, tag, regs, sizebars); 1242 #else 1243 (*typeprintfn)(regs); 1244 #endif 1245 } else 1246 printf(" Don't know how to pretty-print type %d header.\n", 1247 hdrtype); 1248 printf("\n"); 1249 1250 /* capability list, if present */ 1251 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1252 && (capoff > 0)) { 1253 #ifdef _KERNEL 1254 pci_conf_print_caplist(pc, tag, regs, capoff); 1255 #else 1256 pci_conf_print_caplist(regs, capoff); 1257 #endif 1258 printf("\n"); 1259 } 1260 1261 /* device-dependent header */ 1262 printf(" Device-dependent header:\n"); 1263 pci_conf_print_regs(regs, endoff, 256); 1264 printf("\n"); 1265 #ifdef _KERNEL 1266 if (printfn) 1267 (*printfn)(pc, tag, regs); 1268 else 1269 printf(" Don't know how to pretty-print device-dependent header.\n"); 1270 printf("\n"); 1271 #endif /* _KERNEL */ 1272 } 1273
Indexes created Wed Sep 24 05:09:52 GMT 2025