pci_subr.c revision 1.68
1 /* $NetBSD: pci_subr.c,v 1.68 2006/10/13 20:53:59 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.68 2006/10/13 20:53:59 christos Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <machine/intr.h> 54 #else 55 #include <pci.h> 56 #include <stdio.h> 57 #endif 58 59 #include <dev/pci/pcireg.h> 60 #ifdef _KERNEL 61 #include <dev/pci/pcivar.h> 62 #endif 63 #ifdef PCIVERBOSE 64 #include <dev/pci/pcidevs.h> 65 #endif 66 67 /* 68 * Descriptions of known PCI classes and subclasses. 69 * 70 * Subclasses are described in the same way as classes, but have a 71 * NULL subclass pointer. 72 */ 73 struct pci_class { 74 const char *name; 75 int val; /* as wide as pci_{,sub}class_t */ 76 const struct pci_class *subclasses; 77 }; 78 79 static const struct pci_class pci_subclass_prehistoric[] = { 80 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 81 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 82 { NULL, 0, NULL, }, 83 }; 84 85 static const struct pci_class pci_subclass_mass_storage[] = { 86 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 87 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 88 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 89 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 90 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 91 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, NULL, }, 92 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, NULL, }, 93 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 94 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 95 { NULL, 0, NULL, }, 96 }; 97 98 static const struct pci_class pci_subclass_network[] = { 99 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 100 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 101 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 102 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 103 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 104 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 105 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 106 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 107 { NULL, 0, NULL, }, 108 }; 109 110 static const struct pci_class pci_subclass_display[] = { 111 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, NULL, }, 112 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 113 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 114 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 115 { NULL, 0, NULL, }, 116 }; 117 118 static const struct pci_class pci_subclass_multimedia[] = { 119 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 120 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 121 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 122 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 123 { NULL, 0, NULL, }, 124 }; 125 126 static const struct pci_class pci_subclass_memory[] = { 127 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 128 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 129 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 130 { NULL, 0, NULL, }, 131 }; 132 133 static const struct pci_class pci_subclass_bridge[] = { 134 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 135 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 136 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 137 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 138 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, NULL, }, 139 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 140 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 141 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 142 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 143 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, NULL, }, 144 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 145 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 146 { NULL, 0, NULL, }, 147 }; 148 149 static const struct pci_class pci_subclass_communications[] = { 150 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, NULL, }, 151 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, NULL, }, 152 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL, }, 153 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, NULL, }, 154 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL, }, 155 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL, }, 156 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL, }, 157 { NULL, 0, NULL, }, 158 }; 159 160 static const struct pci_class pci_subclass_system[] = { 161 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, NULL, }, 162 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, NULL, }, 163 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, NULL, }, 164 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, NULL, }, 165 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 166 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 167 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 168 { NULL, 0, NULL, }, 169 }; 170 171 static const struct pci_class pci_subclass_input[] = { 172 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 173 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 174 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 175 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 176 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, NULL, }, 177 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 178 { NULL, 0, NULL, }, 179 }; 180 181 static const struct pci_class pci_subclass_dock[] = { 182 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 183 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 184 { NULL, 0, NULL, }, 185 }; 186 187 static const struct pci_class pci_subclass_processor[] = { 188 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 189 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 190 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 191 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 192 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 193 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 194 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 195 { NULL, 0, NULL, }, 196 }; 197 198 static const struct pci_class pci_subclass_serialbus[] = { 199 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, NULL, }, 200 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 201 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 202 { "USB", PCI_SUBCLASS_SERIALBUS_USB, NULL, }, 203 /* XXX Fiber Channel/_FIBRECHANNEL */ 204 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 205 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 206 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 207 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, NULL, }, 208 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 209 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 210 { NULL, 0, NULL, }, 211 }; 212 213 static const struct pci_class pci_subclass_wireless[] = { 214 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 215 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 216 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 217 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 218 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 219 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 220 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 221 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 222 { NULL, 0, NULL, }, 223 }; 224 225 static const struct pci_class pci_subclass_i2o[] = { 226 { "standard", PCI_SUBCLASS_I2O_STANDARD, NULL, }, 227 { NULL, 0, NULL, }, 228 }; 229 230 static const struct pci_class pci_subclass_satcom[] = { 231 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 232 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 233 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 234 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 235 { NULL, 0, NULL, }, 236 }; 237 238 static const struct pci_class pci_subclass_crypto[] = { 239 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 240 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 241 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 242 { NULL, 0, NULL, }, 243 }; 244 245 static const struct pci_class pci_subclass_dasp[] = { 246 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 247 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 248 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 249 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 250 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 251 { NULL, 0, NULL, }, 252 }; 253 254 static const struct pci_class pci_class[] = { 255 { "prehistoric", PCI_CLASS_PREHISTORIC, 256 pci_subclass_prehistoric, }, 257 { "mass storage", PCI_CLASS_MASS_STORAGE, 258 pci_subclass_mass_storage, }, 259 { "network", PCI_CLASS_NETWORK, 260 pci_subclass_network, }, 261 { "display", PCI_CLASS_DISPLAY, 262 pci_subclass_display, }, 263 { "multimedia", PCI_CLASS_MULTIMEDIA, 264 pci_subclass_multimedia, }, 265 { "memory", PCI_CLASS_MEMORY, 266 pci_subclass_memory, }, 267 { "bridge", PCI_CLASS_BRIDGE, 268 pci_subclass_bridge, }, 269 { "communications", PCI_CLASS_COMMUNICATIONS, 270 pci_subclass_communications, }, 271 { "system", PCI_CLASS_SYSTEM, 272 pci_subclass_system, }, 273 { "input", PCI_CLASS_INPUT, 274 pci_subclass_input, }, 275 { "dock", PCI_CLASS_DOCK, 276 pci_subclass_dock, }, 277 { "processor", PCI_CLASS_PROCESSOR, 278 pci_subclass_processor, }, 279 { "serial bus", PCI_CLASS_SERIALBUS, 280 pci_subclass_serialbus, }, 281 { "wireless", PCI_CLASS_WIRELESS, 282 pci_subclass_wireless, }, 283 { "I2O", PCI_CLASS_I2O, 284 pci_subclass_i2o, }, 285 { "satellite comm", PCI_CLASS_SATCOM, 286 pci_subclass_satcom, }, 287 { "crypto", PCI_CLASS_CRYPTO, 288 pci_subclass_crypto, }, 289 { "DASP", PCI_CLASS_DASP, 290 pci_subclass_dasp, }, 291 { "undefined", PCI_CLASS_UNDEFINED, 292 NULL, }, 293 { NULL, 0, 294 NULL, }, 295 }; 296 297 #ifdef PCIVERBOSE 298 /* 299 * Descriptions of of known vendors and devices ("products"). 300 */ 301 struct pci_vendor { 302 pci_vendor_id_t vendor; 303 const char *vendorname; 304 }; 305 struct pci_product { 306 pci_vendor_id_t vendor; 307 pci_product_id_t product; 308 const char *productname; 309 }; 310 311 #include <dev/pci/pcidevs_data.h> 312 #endif /* PCIVERBOSE */ 313 314 const char * 315 pci_findvendor(pcireg_t id_reg __unused) 316 { 317 #ifdef PCIVERBOSE 318 pci_vendor_id_t vendor = PCI_VENDOR(id_reg); 319 int n; 320 321 for (n = 0; n < pci_nvendors; n++) 322 if (pci_vendors[n].vendor == vendor) 323 return (pci_vendors[n].vendorname); 324 #else 325 do { if (&id_reg) {} } while (/* CONSTCOND */ 0); 326 #endif 327 return (NULL); 328 } 329 330 const char * 331 pci_findproduct(pcireg_t id_reg __unused) 332 { 333 #ifdef PCIVERBOSE 334 pci_vendor_id_t vendor = PCI_VENDOR(id_reg); 335 pci_product_id_t product = PCI_PRODUCT(id_reg); 336 int n; 337 338 for (n = 0; n < pci_nproducts; n++) 339 if (pci_products[n].vendor == vendor && 340 pci_products[n].product == product) 341 return (pci_products[n].productname); 342 #else 343 do { if (&id_reg) {} } while (/* CONSTCOND */ 0); 344 #endif 345 return (NULL); 346 } 347 348 void 349 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 350 size_t l) 351 { 352 pci_vendor_id_t vendor; 353 pci_product_id_t product; 354 pci_class_t class; 355 pci_subclass_t subclass; 356 pci_interface_t interface; 357 pci_revision_t revision; 358 const char *vendor_namep, *product_namep; 359 const struct pci_class *classp, *subclassp; 360 #ifdef PCIVERBOSE 361 const char *unmatched = "unknown "; 362 #else 363 const char *unmatched = ""; 364 #endif 365 char *ep; 366 367 ep = cp + l; 368 369 vendor = PCI_VENDOR(id_reg); 370 product = PCI_PRODUCT(id_reg); 371 372 class = PCI_CLASS(class_reg); 373 subclass = PCI_SUBCLASS(class_reg); 374 interface = PCI_INTERFACE(class_reg); 375 revision = PCI_REVISION(class_reg); 376 377 vendor_namep = pci_findvendor(id_reg); 378 product_namep = pci_findproduct(id_reg); 379 380 classp = pci_class; 381 while (classp->name != NULL) { 382 if (class == classp->val) 383 break; 384 classp++; 385 } 386 387 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 388 while (subclassp && subclassp->name != NULL) { 389 if (subclass == subclassp->val) 390 break; 391 subclassp++; 392 } 393 394 if (vendor_namep == NULL) 395 cp += snprintf(cp, ep - cp, "%svendor 0x%04x product 0x%04x", 396 unmatched, vendor, product); 397 else if (product_namep != NULL) 398 cp += snprintf(cp, ep - cp, "%s %s", vendor_namep, 399 product_namep); 400 else 401 cp += snprintf(cp, ep - cp, "%s product 0x%04x", 402 vendor_namep, product); 403 if (showclass) { 404 cp += snprintf(cp, ep - cp, " ("); 405 if (classp->name == NULL) 406 cp += snprintf(cp, ep - cp, 407 "class 0x%02x, subclass 0x%02x", class, subclass); 408 else { 409 if (subclassp == NULL || subclassp->name == NULL) 410 cp += snprintf(cp, ep - cp, 411 "%s subclass 0x%02x", 412 classp->name, subclass); 413 else 414 cp += snprintf(cp, ep - cp, "%s %s", 415 subclassp->name, classp->name); 416 } 417 if (interface != 0) 418 cp += snprintf(cp, ep - cp, ", interface 0x%02x", 419 interface); 420 if (revision != 0) 421 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 422 revision); 423 cp += snprintf(cp, ep - cp, ")"); 424 } 425 } 426 427 /* 428 * Print out most of the PCI configuration registers. Typically used 429 * in a device attach routine like this: 430 * 431 * #ifdef MYDEV_DEBUG 432 * printf("%s: ", sc->sc_dev.dv_xname); 433 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 434 * #endif 435 */ 436 437 #define i2o(i) ((i) * 4) 438 #define o2i(o) ((o) / 4) 439 #define onoff(str, bit) \ 440 printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off"); 441 442 static void 443 pci_conf_print_common( 444 #ifdef _KERNEL 445 pci_chipset_tag_t pc __unused, pcitag_t tag __unused, 446 #endif 447 const pcireg_t *regs) 448 { 449 const char *name; 450 const struct pci_class *classp, *subclassp; 451 pcireg_t rval; 452 453 rval = regs[o2i(PCI_ID_REG)]; 454 name = pci_findvendor(rval); 455 if (name) 456 printf(" Vendor Name: %s (0x%04x)\n", name, 457 PCI_VENDOR(rval)); 458 else 459 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 460 name = pci_findproduct(rval); 461 if (name) 462 printf(" Device Name: %s (0x%04x)\n", name, 463 PCI_PRODUCT(rval)); 464 else 465 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 466 467 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 468 469 printf(" Command register: 0x%04x\n", rval & 0xffff); 470 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 471 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 472 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 473 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 474 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 475 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 476 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 477 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 478 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 479 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 480 481 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 482 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 483 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 484 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 485 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 486 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 487 488 printf(" DEVSEL timing: "); 489 switch (rval & PCI_STATUS_DEVSEL_MASK) { 490 case PCI_STATUS_DEVSEL_FAST: 491 printf("fast"); 492 break; 493 case PCI_STATUS_DEVSEL_MEDIUM: 494 printf("medium"); 495 break; 496 case PCI_STATUS_DEVSEL_SLOW: 497 printf("slow"); 498 break; 499 default: 500 printf("unknown/reserved"); /* XXX */ 501 break; 502 } 503 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 504 505 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 506 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 507 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 508 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 509 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 510 511 rval = regs[o2i(PCI_CLASS_REG)]; 512 for (classp = pci_class; classp->name != NULL; classp++) { 513 if (PCI_CLASS(rval) == classp->val) 514 break; 515 } 516 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 517 while (subclassp && subclassp->name != NULL) { 518 if (PCI_SUBCLASS(rval) == subclassp->val) 519 break; 520 subclassp++; 521 } 522 if (classp->name != NULL) { 523 printf(" Class Name: %s (0x%02x)\n", classp->name, 524 PCI_CLASS(rval)); 525 if (subclassp != NULL && subclassp->name != NULL) 526 printf(" Subclass Name: %s (0x%02x)\n", 527 subclassp->name, PCI_SUBCLASS(rval)); 528 else 529 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 530 } else { 531 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 532 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 533 } 534 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 535 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 536 537 rval = regs[o2i(PCI_BHLC_REG)]; 538 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 539 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 540 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 541 PCI_HDRTYPE(rval)); 542 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 543 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 544 } 545 546 static int 547 pci_conf_print_bar( 548 #ifdef _KERNEL 549 pci_chipset_tag_t pc, pcitag_t tag, 550 #endif 551 const pcireg_t *regs, int reg, const char *name 552 #ifdef _KERNEL 553 , int sizebar 554 #endif 555 ) 556 { 557 int width; 558 pcireg_t rval, rval64h; 559 #ifdef _KERNEL 560 int s; 561 pcireg_t mask, mask64h; 562 #endif 563 564 width = 4; 565 566 /* 567 * Section 6.2.5.1, `Address Maps', tells us that: 568 * 569 * 1) The builtin software should have already mapped the 570 * device in a reasonable way. 571 * 572 * 2) A device which wants 2^n bytes of memory will hardwire 573 * the bottom n bits of the address to 0. As recommended, 574 * we write all 1s and see what we get back. 575 */ 576 577 rval = regs[o2i(reg)]; 578 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 579 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 580 rval64h = regs[o2i(reg + 4)]; 581 width = 8; 582 } else 583 rval64h = 0; 584 585 #ifdef _KERNEL 586 /* XXX don't size unknown memory type? */ 587 if (rval != 0 && sizebar) { 588 /* 589 * The following sequence seems to make some devices 590 * (e.g. host bus bridges, which don't normally 591 * have their space mapped) very unhappy, to 592 * the point of crashing the system. 593 * 594 * Therefore, if the mapping register is zero to 595 * start out with, don't bother trying. 596 */ 597 s = splhigh(); 598 pci_conf_write(pc, tag, reg, 0xffffffff); 599 mask = pci_conf_read(pc, tag, reg); 600 pci_conf_write(pc, tag, reg, rval); 601 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 602 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 603 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 604 mask64h = pci_conf_read(pc, tag, reg + 4); 605 pci_conf_write(pc, tag, reg + 4, rval64h); 606 } else 607 mask64h = 0; 608 splx(s); 609 } else 610 mask = mask64h = 0; 611 #endif /* _KERNEL */ 612 613 printf(" Base address register at 0x%02x", reg); 614 if (name) 615 printf(" (%s)", name); 616 printf("\n "); 617 if (rval == 0) { 618 printf("not implemented(?)\n"); 619 return width; 620 } 621 printf("type: "); 622 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 623 const char *type, *prefetch; 624 625 switch (PCI_MAPREG_MEM_TYPE(rval)) { 626 case PCI_MAPREG_MEM_TYPE_32BIT: 627 type = "32-bit"; 628 break; 629 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 630 type = "32-bit-1M"; 631 break; 632 case PCI_MAPREG_MEM_TYPE_64BIT: 633 type = "64-bit"; 634 break; 635 default: 636 type = "unknown (XXX)"; 637 break; 638 } 639 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 640 prefetch = ""; 641 else 642 prefetch = "non"; 643 printf("%s %sprefetchable memory\n", type, prefetch); 644 switch (PCI_MAPREG_MEM_TYPE(rval)) { 645 case PCI_MAPREG_MEM_TYPE_64BIT: 646 printf(" base: 0x%016llx, ", 647 PCI_MAPREG_MEM64_ADDR( 648 ((((long long) rval64h) << 32) | rval))); 649 #ifdef _KERNEL 650 if (sizebar) 651 printf("size: 0x%016llx", 652 PCI_MAPREG_MEM64_SIZE( 653 ((((long long) mask64h) << 32) | mask))); 654 else 655 #endif /* _KERNEL */ 656 printf("not sized"); 657 printf("\n"); 658 break; 659 case PCI_MAPREG_MEM_TYPE_32BIT: 660 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 661 default: 662 printf(" base: 0x%08x, ", 663 PCI_MAPREG_MEM_ADDR(rval)); 664 #ifdef _KERNEL 665 if (sizebar) 666 printf("size: 0x%08x", 667 PCI_MAPREG_MEM_SIZE(mask)); 668 else 669 #endif /* _KERNEL */ 670 printf("not sized"); 671 printf("\n"); 672 break; 673 } 674 } else { 675 #ifdef _KERNEL 676 if (sizebar) 677 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 678 #endif /* _KERNEL */ 679 printf("i/o\n"); 680 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 681 #ifdef _KERNEL 682 if (sizebar) 683 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 684 else 685 #endif /* _KERNEL */ 686 printf("not sized"); 687 printf("\n"); 688 } 689 690 return width; 691 } 692 693 static void 694 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 695 { 696 int off, needaddr, neednl; 697 698 needaddr = 1; 699 neednl = 0; 700 for (off = first; off < pastlast; off += 4) { 701 if ((off % 16) == 0 || needaddr) { 702 printf(" 0x%02x:", off); 703 needaddr = 0; 704 } 705 printf(" 0x%08x", regs[o2i(off)]); 706 neednl = 1; 707 if ((off % 16) == 12) { 708 printf("\n"); 709 neednl = 0; 710 } 711 } 712 if (neednl) 713 printf("\n"); 714 } 715 716 static void 717 pci_conf_print_type0( 718 #ifdef _KERNEL 719 pci_chipset_tag_t pc, pcitag_t tag, 720 #endif 721 const pcireg_t *regs 722 #ifdef _KERNEL 723 , int sizebars 724 #endif 725 ) 726 { 727 int off, width; 728 pcireg_t rval; 729 730 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 731 #ifdef _KERNEL 732 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 733 #else 734 width = pci_conf_print_bar(regs, off, NULL); 735 #endif 736 } 737 738 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 739 740 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 741 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 742 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 743 744 /* XXX */ 745 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 746 747 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 748 printf(" Capability list pointer: 0x%02x\n", 749 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 750 else 751 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 752 753 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 754 755 rval = regs[o2i(PCI_INTERRUPT_REG)]; 756 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 757 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 758 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 759 switch (PCI_INTERRUPT_PIN(rval)) { 760 case PCI_INTERRUPT_PIN_NONE: 761 printf("(none)"); 762 break; 763 case PCI_INTERRUPT_PIN_A: 764 printf("(pin A)"); 765 break; 766 case PCI_INTERRUPT_PIN_B: 767 printf("(pin B)"); 768 break; 769 case PCI_INTERRUPT_PIN_C: 770 printf("(pin C)"); 771 break; 772 case PCI_INTERRUPT_PIN_D: 773 printf("(pin D)"); 774 break; 775 default: 776 printf("(? ? ?)"); 777 break; 778 } 779 printf("\n"); 780 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 781 } 782 783 static void 784 pci_conf_print_caplist( 785 #ifdef _KERNEL 786 pci_chipset_tag_t pc __unused, pcitag_t tag __unused, 787 #endif 788 const pcireg_t *regs, int capoff) 789 { 790 static const char unk[] = "unknown"; 791 static const char *pmrev[8] = { 792 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 793 }; 794 int off; 795 pcireg_t rval; 796 797 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 798 off != 0; 799 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 800 rval = regs[o2i(off)]; 801 printf(" Capability register at 0x%02x\n", off); 802 803 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 804 switch (PCI_CAPLIST_CAP(rval)) { 805 case PCI_CAP_RESERVED0: 806 printf("reserved"); 807 break; 808 case PCI_CAP_PWRMGMT: 809 printf("Power Management, rev. %s", 810 pmrev[(rval >> 0) & 0x07]); 811 break; 812 case PCI_CAP_AGP: 813 printf("AGP, rev. %d.%d", 814 PCI_CAP_AGP_MAJOR(rval), 815 PCI_CAP_AGP_MINOR(rval)); 816 break; 817 case PCI_CAP_VPD: 818 printf("VPD"); 819 break; 820 case PCI_CAP_SLOTID: 821 printf("SlotID"); 822 break; 823 case PCI_CAP_MSI: 824 printf("MSI"); 825 break; 826 case PCI_CAP_CPCI_HOTSWAP: 827 printf("CompactPCI Hot-swapping"); 828 break; 829 case PCI_CAP_PCIX: 830 printf("PCI-X"); 831 break; 832 case PCI_CAP_LDT: 833 printf("LDT"); 834 break; 835 case PCI_CAP_VENDSPEC: 836 printf("Vendor-specific"); 837 break; 838 case PCI_CAP_DEBUGPORT: 839 printf("Debug Port"); 840 break; 841 case PCI_CAP_CPCI_RSRCCTL: 842 printf("CompactPCI Resource Control"); 843 break; 844 case PCI_CAP_HOTPLUG: 845 printf("Hot-Plug"); 846 break; 847 case PCI_CAP_AGP8: 848 printf("AGP 8x"); 849 break; 850 case PCI_CAP_SECURE: 851 printf("Secure Device"); 852 break; 853 case PCI_CAP_PCIEXPRESS: 854 printf("PCI Express"); 855 break; 856 case PCI_CAP_MSIX: 857 printf("MSI-X"); 858 break; 859 default: 860 printf("unknown"); 861 } 862 printf(")\n"); 863 } 864 } 865 866 static void 867 pci_conf_print_type1( 868 #ifdef _KERNEL 869 pci_chipset_tag_t pc, pcitag_t tag, 870 #endif 871 const pcireg_t *regs 872 #ifdef _KERNEL 873 , int sizebars 874 #endif 875 ) 876 { 877 int off, width; 878 pcireg_t rval; 879 880 /* 881 * XXX these need to be printed in more detail, need to be 882 * XXX checked against specs/docs, etc. 883 * 884 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 885 * Bridge chip documentation, and may not be correct with 886 * respect to various standards. (XXX) 887 */ 888 889 for (off = 0x10; off < 0x18; off += width) { 890 #ifdef _KERNEL 891 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 892 #else 893 width = pci_conf_print_bar(regs, off, NULL); 894 #endif 895 } 896 897 printf(" Primary bus number: 0x%02x\n", 898 (regs[o2i(0x18)] >> 0) & 0xff); 899 printf(" Secondary bus number: 0x%02x\n", 900 (regs[o2i(0x18)] >> 8) & 0xff); 901 printf(" Subordinate bus number: 0x%02x\n", 902 (regs[o2i(0x18)] >> 16) & 0xff); 903 printf(" Secondary bus latency timer: 0x%02x\n", 904 (regs[o2i(0x18)] >> 24) & 0xff); 905 906 rval = (regs[o2i(0x1c)] >> 16) & 0xffff; 907 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 908 onoff("66 MHz capable", 0x0020); 909 onoff("User Definable Features (UDF) support", 0x0040); 910 onoff("Fast back-to-back capable", 0x0080); 911 onoff("Data parity error detected", 0x0100); 912 913 printf(" DEVSEL timing: "); 914 switch (rval & 0x0600) { 915 case 0x0000: 916 printf("fast"); 917 break; 918 case 0x0200: 919 printf("medium"); 920 break; 921 case 0x0400: 922 printf("slow"); 923 break; 924 default: 925 printf("unknown/reserved"); /* XXX */ 926 break; 927 } 928 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 929 930 onoff("Signaled Target Abort", 0x0800); 931 onoff("Received Target Abort", 0x1000); 932 onoff("Received Master Abort", 0x2000); 933 onoff("System Error", 0x4000); 934 onoff("Parity Error", 0x8000); 935 936 /* XXX Print more prettily */ 937 printf(" I/O region:\n"); 938 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 939 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 940 printf(" base upper 16 bits register: 0x%04x\n", 941 (regs[o2i(0x30)] >> 0) & 0xffff); 942 printf(" limit upper 16 bits register: 0x%04x\n", 943 (regs[o2i(0x30)] >> 16) & 0xffff); 944 945 /* XXX Print more prettily */ 946 printf(" Memory region:\n"); 947 printf(" base register: 0x%04x\n", 948 (regs[o2i(0x20)] >> 0) & 0xffff); 949 printf(" limit register: 0x%04x\n", 950 (regs[o2i(0x20)] >> 16) & 0xffff); 951 952 /* XXX Print more prettily */ 953 printf(" Prefetchable memory region:\n"); 954 printf(" base register: 0x%04x\n", 955 (regs[o2i(0x24)] >> 0) & 0xffff); 956 printf(" limit register: 0x%04x\n", 957 (regs[o2i(0x24)] >> 16) & 0xffff); 958 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 959 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 960 961 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 962 printf(" Capability list pointer: 0x%02x\n", 963 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 964 else 965 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 966 967 /* XXX */ 968 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 969 970 printf(" Interrupt line: 0x%02x\n", 971 (regs[o2i(0x3c)] >> 0) & 0xff); 972 printf(" Interrupt pin: 0x%02x ", 973 (regs[o2i(0x3c)] >> 8) & 0xff); 974 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 975 case PCI_INTERRUPT_PIN_NONE: 976 printf("(none)"); 977 break; 978 case PCI_INTERRUPT_PIN_A: 979 printf("(pin A)"); 980 break; 981 case PCI_INTERRUPT_PIN_B: 982 printf("(pin B)"); 983 break; 984 case PCI_INTERRUPT_PIN_C: 985 printf("(pin C)"); 986 break; 987 case PCI_INTERRUPT_PIN_D: 988 printf("(pin D)"); 989 break; 990 default: 991 printf("(? ? ?)"); 992 break; 993 } 994 printf("\n"); 995 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 996 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 997 onoff("Parity error response", 0x0001); 998 onoff("Secondary SERR forwarding", 0x0002); 999 onoff("ISA enable", 0x0004); 1000 onoff("VGA enable", 0x0008); 1001 onoff("Master abort reporting", 0x0020); 1002 onoff("Secondary bus reset", 0x0040); 1003 onoff("Fast back-to-back capable", 0x0080); 1004 } 1005 1006 static void 1007 pci_conf_print_type2( 1008 #ifdef _KERNEL 1009 pci_chipset_tag_t pc, pcitag_t tag, 1010 #endif 1011 const pcireg_t *regs 1012 #ifdef _KERNEL 1013 , int sizebars 1014 #endif 1015 ) 1016 { 1017 pcireg_t rval; 1018 1019 /* 1020 * XXX these need to be printed in more detail, need to be 1021 * XXX checked against specs/docs, etc. 1022 * 1023 * This layout was cribbed from the TI PCI1130 PCI-to-CardBus 1024 * controller chip documentation, and may not be correct with 1025 * respect to various standards. (XXX) 1026 */ 1027 1028 #ifdef _KERNEL 1029 pci_conf_print_bar(pc, tag, regs, 0x10, 1030 "CardBus socket/ExCA registers", sizebars); 1031 #else 1032 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 1033 #endif 1034 1035 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1036 printf(" Capability list pointer: 0x%02x\n", 1037 PCI_CAPLIST_PTR(regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)])); 1038 else 1039 printf(" Reserved @ 0x14: 0x%04x\n", 1040 (regs[o2i(0x14)] >> 0) & 0xffff); 1041 rval = (regs[o2i(0x14)] >> 16) & 0xffff; 1042 printf(" Secondary status register: 0x%04x\n", rval); 1043 onoff("66 MHz capable", 0x0020); 1044 onoff("User Definable Features (UDF) support", 0x0040); 1045 onoff("Fast back-to-back capable", 0x0080); 1046 onoff("Data parity error detection", 0x0100); 1047 1048 printf(" DEVSEL timing: "); 1049 switch (rval & 0x0600) { 1050 case 0x0000: 1051 printf("fast"); 1052 break; 1053 case 0x0200: 1054 printf("medium"); 1055 break; 1056 case 0x0400: 1057 printf("slow"); 1058 break; 1059 default: 1060 printf("unknown/reserved"); /* XXX */ 1061 break; 1062 } 1063 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 1064 onoff("PCI target aborts terminate CardBus bus master transactions", 1065 0x0800); 1066 onoff("CardBus target aborts terminate PCI bus master transactions", 1067 0x1000); 1068 onoff("Bus initiator aborts terminate initiator transactions", 1069 0x2000); 1070 onoff("System error", 0x4000); 1071 onoff("Parity error", 0x8000); 1072 1073 printf(" PCI bus number: 0x%02x\n", 1074 (regs[o2i(0x18)] >> 0) & 0xff); 1075 printf(" CardBus bus number: 0x%02x\n", 1076 (regs[o2i(0x18)] >> 8) & 0xff); 1077 printf(" Subordinate bus number: 0x%02x\n", 1078 (regs[o2i(0x18)] >> 16) & 0xff); 1079 printf(" CardBus latency timer: 0x%02x\n", 1080 (regs[o2i(0x18)] >> 24) & 0xff); 1081 1082 /* XXX Print more prettily */ 1083 printf(" CardBus memory region 0:\n"); 1084 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1085 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1086 printf(" CardBus memory region 1:\n"); 1087 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1088 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1089 printf(" CardBus I/O region 0:\n"); 1090 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1091 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1092 printf(" CardBus I/O region 1:\n"); 1093 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1094 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1095 1096 printf(" Interrupt line: 0x%02x\n", 1097 (regs[o2i(0x3c)] >> 0) & 0xff); 1098 printf(" Interrupt pin: 0x%02x ", 1099 (regs[o2i(0x3c)] >> 8) & 0xff); 1100 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1101 case PCI_INTERRUPT_PIN_NONE: 1102 printf("(none)"); 1103 break; 1104 case PCI_INTERRUPT_PIN_A: 1105 printf("(pin A)"); 1106 break; 1107 case PCI_INTERRUPT_PIN_B: 1108 printf("(pin B)"); 1109 break; 1110 case PCI_INTERRUPT_PIN_C: 1111 printf("(pin C)"); 1112 break; 1113 case PCI_INTERRUPT_PIN_D: 1114 printf("(pin D)"); 1115 break; 1116 default: 1117 printf("(? ? ?)"); 1118 break; 1119 } 1120 printf("\n"); 1121 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1122 printf(" Bridge control register: 0x%04x\n", rval); 1123 onoff("Parity error response", 0x0001); 1124 onoff("CardBus SERR forwarding", 0x0002); 1125 onoff("ISA enable", 0x0004); 1126 onoff("VGA enable", 0x0008); 1127 onoff("CardBus master abort reporting", 0x0020); 1128 onoff("CardBus reset", 0x0040); 1129 onoff("Functional interrupts routed by ExCA registers", 0x0080); 1130 onoff("Memory window 0 prefetchable", 0x0100); 1131 onoff("Memory window 1 prefetchable", 0x0200); 1132 onoff("Write posting enable", 0x0400); 1133 1134 rval = regs[o2i(0x40)]; 1135 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1136 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1137 1138 #ifdef _KERNEL 1139 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1140 sizebars); 1141 #else 1142 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 1143 #endif 1144 } 1145 1146 void 1147 pci_conf_print( 1148 #ifdef _KERNEL 1149 pci_chipset_tag_t pc, pcitag_t tag, 1150 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 1151 #else 1152 int pcifd, u_int bus, u_int dev, u_int func 1153 #endif 1154 ) 1155 { 1156 pcireg_t regs[o2i(256)]; 1157 int off, capoff, endoff, hdrtype; 1158 const char *typename; 1159 #ifdef _KERNEL 1160 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1161 int sizebars; 1162 #else 1163 void (*typeprintfn)(const pcireg_t *); 1164 #endif 1165 1166 printf("PCI configuration registers:\n"); 1167 1168 for (off = 0; off < 256; off += 4) { 1169 #ifdef _KERNEL 1170 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1171 #else 1172 if (pcibus_conf_read(pcifd, bus, dev, func, off, 1173 ®s[o2i(off)]) == -1) 1174 regs[o2i(off)] = 0; 1175 #endif 1176 } 1177 1178 #ifdef _KERNEL 1179 sizebars = 1; 1180 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1181 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1182 sizebars = 0; 1183 #endif 1184 1185 /* common header */ 1186 printf(" Common header:\n"); 1187 pci_conf_print_regs(regs, 0, 16); 1188 1189 printf("\n"); 1190 #ifdef _KERNEL 1191 pci_conf_print_common(pc, tag, regs); 1192 #else 1193 pci_conf_print_common(regs); 1194 #endif 1195 printf("\n"); 1196 1197 /* type-dependent header */ 1198 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1199 switch (hdrtype) { /* XXX make a table, eventually */ 1200 case 0: 1201 /* Standard device header */ 1202 typename = "\"normal\" device"; 1203 typeprintfn = &pci_conf_print_type0; 1204 capoff = PCI_CAPLISTPTR_REG; 1205 endoff = 64; 1206 break; 1207 case 1: 1208 /* PCI-PCI bridge header */ 1209 typename = "PCI-PCI bridge"; 1210 typeprintfn = &pci_conf_print_type1; 1211 capoff = PCI_CAPLISTPTR_REG; 1212 endoff = 64; 1213 break; 1214 case 2: 1215 /* PCI-CardBus bridge header */ 1216 typename = "PCI-CardBus bridge"; 1217 typeprintfn = &pci_conf_print_type2; 1218 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 1219 endoff = 72; 1220 break; 1221 default: 1222 typename = NULL; 1223 typeprintfn = 0; 1224 capoff = -1; 1225 endoff = 64; 1226 break; 1227 } 1228 printf(" Type %d ", hdrtype); 1229 if (typename != NULL) 1230 printf("(%s) ", typename); 1231 printf("header:\n"); 1232 pci_conf_print_regs(regs, 16, endoff); 1233 printf("\n"); 1234 if (typeprintfn) { 1235 #ifdef _KERNEL 1236 (*typeprintfn)(pc, tag, regs, sizebars); 1237 #else 1238 (*typeprintfn)(regs); 1239 #endif 1240 } else 1241 printf(" Don't know how to pretty-print type %d header.\n", 1242 hdrtype); 1243 printf("\n"); 1244 1245 /* capability list, if present */ 1246 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1247 && (capoff > 0)) { 1248 #ifdef _KERNEL 1249 pci_conf_print_caplist(pc, tag, regs, capoff); 1250 #else 1251 pci_conf_print_caplist(regs, capoff); 1252 #endif 1253 printf("\n"); 1254 } 1255 1256 /* device-dependent header */ 1257 printf(" Device-dependent header:\n"); 1258 pci_conf_print_regs(regs, endoff, 256); 1259 printf("\n"); 1260 #ifdef _KERNEL 1261 if (printfn) 1262 (*printfn)(pc, tag, regs); 1263 else 1264 printf(" Don't know how to pretty-print device-dependent header.\n"); 1265 printf("\n"); 1266 #endif /* _KERNEL */ 1267 } 1268
Indexes created Tue Sep 30 11:09:46 GMT 2025