pci_subr.c revision 1.70
1 /* $NetBSD: pci_subr.c,v 1.70 2006/11/08 18:44:16 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.70 2006/11/08 18:44:16 drochner Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <machine/intr.h> 54 #else 55 #include <pci.h> 56 #include <stdio.h> 57 #endif 58 59 #include <dev/pci/pcireg.h> 60 #ifdef _KERNEL 61 #include <dev/pci/pcivar.h> 62 #endif 63 #ifdef PCIVERBOSE 64 #include <dev/pci/pcidevs.h> 65 #endif 66 67 /* 68 * Descriptions of known PCI classes and subclasses. 69 * 70 * Subclasses are described in the same way as classes, but have a 71 * NULL subclass pointer. 72 */ 73 struct pci_class { 74 const char *name; 75 int val; /* as wide as pci_{,sub}class_t */ 76 const struct pci_class *subclasses; 77 }; 78 79 static const struct pci_class pci_subclass_prehistoric[] = { 80 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 81 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 82 { NULL, 0, NULL, }, 83 }; 84 85 static const struct pci_class pci_subclass_mass_storage[] = { 86 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 87 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 88 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 89 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 90 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 91 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, NULL, }, 92 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, NULL, }, 93 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 94 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 95 { NULL, 0, NULL, }, 96 }; 97 98 static const struct pci_class pci_subclass_network[] = { 99 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 100 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 101 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 102 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 103 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 104 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 105 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 106 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 107 { NULL, 0, NULL, }, 108 }; 109 110 static const struct pci_class pci_subclass_display[] = { 111 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, NULL, }, 112 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 113 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 114 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 115 { NULL, 0, NULL, }, 116 }; 117 118 static const struct pci_class pci_subclass_multimedia[] = { 119 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 120 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 121 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 122 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 123 { NULL, 0, NULL, }, 124 }; 125 126 static const struct pci_class pci_subclass_memory[] = { 127 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 128 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 129 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 130 { NULL, 0, NULL, }, 131 }; 132 133 static const struct pci_class pci_subclass_bridge[] = { 134 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 135 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 136 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 137 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 138 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, NULL, }, 139 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 140 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 141 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 142 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 143 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, NULL, }, 144 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 145 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 146 { NULL, 0, NULL, }, 147 }; 148 149 static const struct pci_class pci_subclass_communications[] = { 150 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, NULL, }, 151 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, NULL, }, 152 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL, }, 153 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, NULL, }, 154 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL, }, 155 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL, }, 156 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL, }, 157 { NULL, 0, NULL, }, 158 }; 159 160 static const struct pci_class pci_subclass_system[] = { 161 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, NULL, }, 162 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, NULL, }, 163 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, NULL, }, 164 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, NULL, }, 165 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 166 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 167 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 168 { NULL, 0, NULL, }, 169 }; 170 171 static const struct pci_class pci_subclass_input[] = { 172 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 173 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 174 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 175 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 176 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, NULL, }, 177 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 178 { NULL, 0, NULL, }, 179 }; 180 181 static const struct pci_class pci_subclass_dock[] = { 182 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 183 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 184 { NULL, 0, NULL, }, 185 }; 186 187 static const struct pci_class pci_subclass_processor[] = { 188 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 189 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 190 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 191 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 192 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 193 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 194 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 195 { NULL, 0, NULL, }, 196 }; 197 198 static const struct pci_class pci_subclass_serialbus[] = { 199 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, NULL, }, 200 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 201 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 202 { "USB", PCI_SUBCLASS_SERIALBUS_USB, NULL, }, 203 /* XXX Fiber Channel/_FIBRECHANNEL */ 204 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 205 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 206 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 207 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, NULL, }, 208 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 209 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 210 { NULL, 0, NULL, }, 211 }; 212 213 static const struct pci_class pci_subclass_wireless[] = { 214 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 215 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 216 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 217 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 218 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 219 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 220 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 221 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 222 { NULL, 0, NULL, }, 223 }; 224 225 static const struct pci_class pci_subclass_i2o[] = { 226 { "standard", PCI_SUBCLASS_I2O_STANDARD, NULL, }, 227 { NULL, 0, NULL, }, 228 }; 229 230 static const struct pci_class pci_subclass_satcom[] = { 231 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 232 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 233 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 234 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 235 { NULL, 0, NULL, }, 236 }; 237 238 static const struct pci_class pci_subclass_crypto[] = { 239 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 240 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 241 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 242 { NULL, 0, NULL, }, 243 }; 244 245 static const struct pci_class pci_subclass_dasp[] = { 246 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 247 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 248 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 249 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 250 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 251 { NULL, 0, NULL, }, 252 }; 253 254 static const struct pci_class pci_class[] = { 255 { "prehistoric", PCI_CLASS_PREHISTORIC, 256 pci_subclass_prehistoric, }, 257 { "mass storage", PCI_CLASS_MASS_STORAGE, 258 pci_subclass_mass_storage, }, 259 { "network", PCI_CLASS_NETWORK, 260 pci_subclass_network, }, 261 { "display", PCI_CLASS_DISPLAY, 262 pci_subclass_display, }, 263 { "multimedia", PCI_CLASS_MULTIMEDIA, 264 pci_subclass_multimedia, }, 265 { "memory", PCI_CLASS_MEMORY, 266 pci_subclass_memory, }, 267 { "bridge", PCI_CLASS_BRIDGE, 268 pci_subclass_bridge, }, 269 { "communications", PCI_CLASS_COMMUNICATIONS, 270 pci_subclass_communications, }, 271 { "system", PCI_CLASS_SYSTEM, 272 pci_subclass_system, }, 273 { "input", PCI_CLASS_INPUT, 274 pci_subclass_input, }, 275 { "dock", PCI_CLASS_DOCK, 276 pci_subclass_dock, }, 277 { "processor", PCI_CLASS_PROCESSOR, 278 pci_subclass_processor, }, 279 { "serial bus", PCI_CLASS_SERIALBUS, 280 pci_subclass_serialbus, }, 281 { "wireless", PCI_CLASS_WIRELESS, 282 pci_subclass_wireless, }, 283 { "I2O", PCI_CLASS_I2O, 284 pci_subclass_i2o, }, 285 { "satellite comm", PCI_CLASS_SATCOM, 286 pci_subclass_satcom, }, 287 { "crypto", PCI_CLASS_CRYPTO, 288 pci_subclass_crypto, }, 289 { "DASP", PCI_CLASS_DASP, 290 pci_subclass_dasp, }, 291 { "undefined", PCI_CLASS_UNDEFINED, 292 NULL, }, 293 { NULL, 0, 294 NULL, }, 295 }; 296 297 #ifdef PCIVERBOSE 298 /* 299 * Descriptions of of known vendors and devices ("products"). 300 */ 301 struct pci_vendor { 302 pci_vendor_id_t vendor; 303 const char *vendorname; 304 }; 305 struct pci_product { 306 pci_vendor_id_t vendor; 307 pci_product_id_t product; 308 const char *productname; 309 }; 310 311 #include <dev/pci/pcidevs_data.h> 312 #endif /* PCIVERBOSE */ 313 314 const char * 315 pci_findvendor(pcireg_t id_reg __unused) 316 { 317 #ifdef PCIVERBOSE 318 pci_vendor_id_t vendor = PCI_VENDOR(id_reg); 319 int n; 320 321 for (n = 0; n < pci_nvendors; n++) 322 if (pci_vendors[n].vendor == vendor) 323 return (pci_vendors[n].vendorname); 324 #endif 325 return (NULL); 326 } 327 328 const char * 329 pci_findproduct(pcireg_t id_reg __unused) 330 { 331 #ifdef PCIVERBOSE 332 pci_vendor_id_t vendor = PCI_VENDOR(id_reg); 333 pci_product_id_t product = PCI_PRODUCT(id_reg); 334 int n; 335 336 for (n = 0; n < pci_nproducts; n++) 337 if (pci_products[n].vendor == vendor && 338 pci_products[n].product == product) 339 return (pci_products[n].productname); 340 #endif 341 return (NULL); 342 } 343 344 void 345 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 346 size_t l) 347 { 348 pci_vendor_id_t vendor; 349 pci_product_id_t product; 350 pci_class_t class; 351 pci_subclass_t subclass; 352 pci_interface_t interface; 353 pci_revision_t revision; 354 const char *vendor_namep, *product_namep; 355 const struct pci_class *classp, *subclassp; 356 #ifdef PCIVERBOSE 357 const char *unmatched = "unknown "; 358 #else 359 const char *unmatched = ""; 360 #endif 361 char *ep; 362 363 ep = cp + l; 364 365 vendor = PCI_VENDOR(id_reg); 366 product = PCI_PRODUCT(id_reg); 367 368 class = PCI_CLASS(class_reg); 369 subclass = PCI_SUBCLASS(class_reg); 370 interface = PCI_INTERFACE(class_reg); 371 revision = PCI_REVISION(class_reg); 372 373 vendor_namep = pci_findvendor(id_reg); 374 product_namep = pci_findproduct(id_reg); 375 376 classp = pci_class; 377 while (classp->name != NULL) { 378 if (class == classp->val) 379 break; 380 classp++; 381 } 382 383 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 384 while (subclassp && subclassp->name != NULL) { 385 if (subclass == subclassp->val) 386 break; 387 subclassp++; 388 } 389 390 if (vendor_namep == NULL) 391 cp += snprintf(cp, ep - cp, "%svendor 0x%04x product 0x%04x", 392 unmatched, vendor, product); 393 else if (product_namep != NULL) 394 cp += snprintf(cp, ep - cp, "%s %s", vendor_namep, 395 product_namep); 396 else 397 cp += snprintf(cp, ep - cp, "%s product 0x%04x", 398 vendor_namep, product); 399 if (showclass) { 400 cp += snprintf(cp, ep - cp, " ("); 401 if (classp->name == NULL) 402 cp += snprintf(cp, ep - cp, 403 "class 0x%02x, subclass 0x%02x", class, subclass); 404 else { 405 if (subclassp == NULL || subclassp->name == NULL) 406 cp += snprintf(cp, ep - cp, 407 "%s subclass 0x%02x", 408 classp->name, subclass); 409 else 410 cp += snprintf(cp, ep - cp, "%s %s", 411 subclassp->name, classp->name); 412 } 413 if (interface != 0) 414 cp += snprintf(cp, ep - cp, ", interface 0x%02x", 415 interface); 416 if (revision != 0) 417 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 418 revision); 419 cp += snprintf(cp, ep - cp, ")"); 420 } 421 } 422 423 /* 424 * Print out most of the PCI configuration registers. Typically used 425 * in a device attach routine like this: 426 * 427 * #ifdef MYDEV_DEBUG 428 * printf("%s: ", sc->sc_dev.dv_xname); 429 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 430 * #endif 431 */ 432 433 #define i2o(i) ((i) * 4) 434 #define o2i(o) ((o) / 4) 435 #define onoff(str, bit) \ 436 printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off"); 437 438 static void 439 pci_conf_print_common( 440 #ifdef _KERNEL 441 pci_chipset_tag_t pc __unused, pcitag_t tag __unused, 442 #endif 443 const pcireg_t *regs) 444 { 445 const char *name; 446 const struct pci_class *classp, *subclassp; 447 pcireg_t rval; 448 449 rval = regs[o2i(PCI_ID_REG)]; 450 name = pci_findvendor(rval); 451 if (name) 452 printf(" Vendor Name: %s (0x%04x)\n", name, 453 PCI_VENDOR(rval)); 454 else 455 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 456 name = pci_findproduct(rval); 457 if (name) 458 printf(" Device Name: %s (0x%04x)\n", name, 459 PCI_PRODUCT(rval)); 460 else 461 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 462 463 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 464 465 printf(" Command register: 0x%04x\n", rval & 0xffff); 466 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 467 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 468 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 469 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 470 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 471 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 472 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 473 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 474 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 475 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 476 onoff("Interrupt disable", PCI_COMMAND_INTERRUPT_DISABLE); 477 478 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 479 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 480 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 481 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 482 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 483 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 484 485 printf(" DEVSEL timing: "); 486 switch (rval & PCI_STATUS_DEVSEL_MASK) { 487 case PCI_STATUS_DEVSEL_FAST: 488 printf("fast"); 489 break; 490 case PCI_STATUS_DEVSEL_MEDIUM: 491 printf("medium"); 492 break; 493 case PCI_STATUS_DEVSEL_SLOW: 494 printf("slow"); 495 break; 496 default: 497 printf("unknown/reserved"); /* XXX */ 498 break; 499 } 500 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 501 502 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 503 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 504 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 505 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 506 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 507 508 rval = regs[o2i(PCI_CLASS_REG)]; 509 for (classp = pci_class; classp->name != NULL; classp++) { 510 if (PCI_CLASS(rval) == classp->val) 511 break; 512 } 513 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 514 while (subclassp && subclassp->name != NULL) { 515 if (PCI_SUBCLASS(rval) == subclassp->val) 516 break; 517 subclassp++; 518 } 519 if (classp->name != NULL) { 520 printf(" Class Name: %s (0x%02x)\n", classp->name, 521 PCI_CLASS(rval)); 522 if (subclassp != NULL && subclassp->name != NULL) 523 printf(" Subclass Name: %s (0x%02x)\n", 524 subclassp->name, PCI_SUBCLASS(rval)); 525 else 526 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 527 } else { 528 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 529 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 530 } 531 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 532 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 533 534 rval = regs[o2i(PCI_BHLC_REG)]; 535 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 536 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 537 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 538 PCI_HDRTYPE(rval)); 539 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 540 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 541 } 542 543 static int 544 pci_conf_print_bar( 545 #ifdef _KERNEL 546 pci_chipset_tag_t pc, pcitag_t tag, 547 #endif 548 const pcireg_t *regs, int reg, const char *name 549 #ifdef _KERNEL 550 , int sizebar 551 #endif 552 ) 553 { 554 int width; 555 pcireg_t rval, rval64h; 556 #ifdef _KERNEL 557 int s; 558 pcireg_t mask, mask64h; 559 #endif 560 561 width = 4; 562 563 /* 564 * Section 6.2.5.1, `Address Maps', tells us that: 565 * 566 * 1) The builtin software should have already mapped the 567 * device in a reasonable way. 568 * 569 * 2) A device which wants 2^n bytes of memory will hardwire 570 * the bottom n bits of the address to 0. As recommended, 571 * we write all 1s and see what we get back. 572 */ 573 574 rval = regs[o2i(reg)]; 575 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 576 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 577 rval64h = regs[o2i(reg + 4)]; 578 width = 8; 579 } else 580 rval64h = 0; 581 582 #ifdef _KERNEL 583 /* XXX don't size unknown memory type? */ 584 if (rval != 0 && sizebar) { 585 /* 586 * The following sequence seems to make some devices 587 * (e.g. host bus bridges, which don't normally 588 * have their space mapped) very unhappy, to 589 * the point of crashing the system. 590 * 591 * Therefore, if the mapping register is zero to 592 * start out with, don't bother trying. 593 */ 594 s = splhigh(); 595 pci_conf_write(pc, tag, reg, 0xffffffff); 596 mask = pci_conf_read(pc, tag, reg); 597 pci_conf_write(pc, tag, reg, rval); 598 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 599 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 600 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 601 mask64h = pci_conf_read(pc, tag, reg + 4); 602 pci_conf_write(pc, tag, reg + 4, rval64h); 603 } else 604 mask64h = 0; 605 splx(s); 606 } else 607 mask = mask64h = 0; 608 #endif /* _KERNEL */ 609 610 printf(" Base address register at 0x%02x", reg); 611 if (name) 612 printf(" (%s)", name); 613 printf("\n "); 614 if (rval == 0) { 615 printf("not implemented(?)\n"); 616 return width; 617 } 618 printf("type: "); 619 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 620 const char *type, *prefetch; 621 622 switch (PCI_MAPREG_MEM_TYPE(rval)) { 623 case PCI_MAPREG_MEM_TYPE_32BIT: 624 type = "32-bit"; 625 break; 626 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 627 type = "32-bit-1M"; 628 break; 629 case PCI_MAPREG_MEM_TYPE_64BIT: 630 type = "64-bit"; 631 break; 632 default: 633 type = "unknown (XXX)"; 634 break; 635 } 636 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 637 prefetch = ""; 638 else 639 prefetch = "non"; 640 printf("%s %sprefetchable memory\n", type, prefetch); 641 switch (PCI_MAPREG_MEM_TYPE(rval)) { 642 case PCI_MAPREG_MEM_TYPE_64BIT: 643 printf(" base: 0x%016llx, ", 644 PCI_MAPREG_MEM64_ADDR( 645 ((((long long) rval64h) << 32) | rval))); 646 #ifdef _KERNEL 647 if (sizebar) 648 printf("size: 0x%016llx", 649 PCI_MAPREG_MEM64_SIZE( 650 ((((long long) mask64h) << 32) | mask))); 651 else 652 #endif /* _KERNEL */ 653 printf("not sized"); 654 printf("\n"); 655 break; 656 case PCI_MAPREG_MEM_TYPE_32BIT: 657 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 658 default: 659 printf(" base: 0x%08x, ", 660 PCI_MAPREG_MEM_ADDR(rval)); 661 #ifdef _KERNEL 662 if (sizebar) 663 printf("size: 0x%08x", 664 PCI_MAPREG_MEM_SIZE(mask)); 665 else 666 #endif /* _KERNEL */ 667 printf("not sized"); 668 printf("\n"); 669 break; 670 } 671 } else { 672 #ifdef _KERNEL 673 if (sizebar) 674 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 675 #endif /* _KERNEL */ 676 printf("i/o\n"); 677 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 678 #ifdef _KERNEL 679 if (sizebar) 680 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 681 else 682 #endif /* _KERNEL */ 683 printf("not sized"); 684 printf("\n"); 685 } 686 687 return width; 688 } 689 690 static void 691 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 692 { 693 int off, needaddr, neednl; 694 695 needaddr = 1; 696 neednl = 0; 697 for (off = first; off < pastlast; off += 4) { 698 if ((off % 16) == 0 || needaddr) { 699 printf(" 0x%02x:", off); 700 needaddr = 0; 701 } 702 printf(" 0x%08x", regs[o2i(off)]); 703 neednl = 1; 704 if ((off % 16) == 12) { 705 printf("\n"); 706 neednl = 0; 707 } 708 } 709 if (neednl) 710 printf("\n"); 711 } 712 713 static void 714 pci_conf_print_type0( 715 #ifdef _KERNEL 716 pci_chipset_tag_t pc, pcitag_t tag, 717 #endif 718 const pcireg_t *regs 719 #ifdef _KERNEL 720 , int sizebars 721 #endif 722 ) 723 { 724 int off, width; 725 pcireg_t rval; 726 727 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 728 #ifdef _KERNEL 729 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 730 #else 731 width = pci_conf_print_bar(regs, off, NULL); 732 #endif 733 } 734 735 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 736 737 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 738 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 739 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 740 741 /* XXX */ 742 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 743 744 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 745 printf(" Capability list pointer: 0x%02x\n", 746 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 747 else 748 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 749 750 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 751 752 rval = regs[o2i(PCI_INTERRUPT_REG)]; 753 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 754 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 755 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 756 switch (PCI_INTERRUPT_PIN(rval)) { 757 case PCI_INTERRUPT_PIN_NONE: 758 printf("(none)"); 759 break; 760 case PCI_INTERRUPT_PIN_A: 761 printf("(pin A)"); 762 break; 763 case PCI_INTERRUPT_PIN_B: 764 printf("(pin B)"); 765 break; 766 case PCI_INTERRUPT_PIN_C: 767 printf("(pin C)"); 768 break; 769 case PCI_INTERRUPT_PIN_D: 770 printf("(pin D)"); 771 break; 772 default: 773 printf("(? ? ?)"); 774 break; 775 } 776 printf("\n"); 777 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 778 } 779 780 static void 781 pci_conf_print_caplist( 782 #ifdef _KERNEL 783 pci_chipset_tag_t pc __unused, pcitag_t tag __unused, 784 #endif 785 const pcireg_t *regs, int capoff) 786 { 787 static const char unk[] = "unknown"; 788 static const char *pmrev[8] = { 789 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 790 }; 791 int off; 792 pcireg_t rval; 793 794 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 795 off != 0; 796 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 797 rval = regs[o2i(off)]; 798 printf(" Capability register at 0x%02x\n", off); 799 800 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 801 switch (PCI_CAPLIST_CAP(rval)) { 802 case PCI_CAP_RESERVED0: 803 printf("reserved"); 804 break; 805 case PCI_CAP_PWRMGMT: 806 printf("Power Management, rev. %s", 807 pmrev[(rval >> 0) & 0x07]); 808 break; 809 case PCI_CAP_AGP: 810 printf("AGP, rev. %d.%d", 811 PCI_CAP_AGP_MAJOR(rval), 812 PCI_CAP_AGP_MINOR(rval)); 813 break; 814 case PCI_CAP_VPD: 815 printf("VPD"); 816 break; 817 case PCI_CAP_SLOTID: 818 printf("SlotID"); 819 break; 820 case PCI_CAP_MSI: 821 printf("MSI"); 822 break; 823 case PCI_CAP_CPCI_HOTSWAP: 824 printf("CompactPCI Hot-swapping"); 825 break; 826 case PCI_CAP_PCIX: 827 printf("PCI-X"); 828 break; 829 case PCI_CAP_LDT: 830 printf("LDT"); 831 break; 832 case PCI_CAP_VENDSPEC: 833 printf("Vendor-specific"); 834 break; 835 case PCI_CAP_DEBUGPORT: 836 printf("Debug Port"); 837 break; 838 case PCI_CAP_CPCI_RSRCCTL: 839 printf("CompactPCI Resource Control"); 840 break; 841 case PCI_CAP_HOTPLUG: 842 printf("Hot-Plug"); 843 break; 844 case PCI_CAP_AGP8: 845 printf("AGP 8x"); 846 break; 847 case PCI_CAP_SECURE: 848 printf("Secure Device"); 849 break; 850 case PCI_CAP_PCIEXPRESS: 851 printf("PCI Express"); 852 break; 853 case PCI_CAP_MSIX: 854 printf("MSI-X"); 855 break; 856 default: 857 printf("unknown"); 858 } 859 printf(")\n"); 860 } 861 } 862 863 static void 864 pci_conf_print_type1( 865 #ifdef _KERNEL 866 pci_chipset_tag_t pc, pcitag_t tag, 867 #endif 868 const pcireg_t *regs 869 #ifdef _KERNEL 870 , int sizebars 871 #endif 872 ) 873 { 874 int off, width; 875 pcireg_t rval; 876 877 /* 878 * XXX these need to be printed in more detail, need to be 879 * XXX checked against specs/docs, etc. 880 * 881 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 882 * Bridge chip documentation, and may not be correct with 883 * respect to various standards. (XXX) 884 */ 885 886 for (off = 0x10; off < 0x18; off += width) { 887 #ifdef _KERNEL 888 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 889 #else 890 width = pci_conf_print_bar(regs, off, NULL); 891 #endif 892 } 893 894 printf(" Primary bus number: 0x%02x\n", 895 (regs[o2i(0x18)] >> 0) & 0xff); 896 printf(" Secondary bus number: 0x%02x\n", 897 (regs[o2i(0x18)] >> 8) & 0xff); 898 printf(" Subordinate bus number: 0x%02x\n", 899 (regs[o2i(0x18)] >> 16) & 0xff); 900 printf(" Secondary bus latency timer: 0x%02x\n", 901 (regs[o2i(0x18)] >> 24) & 0xff); 902 903 rval = (regs[o2i(0x1c)] >> 16) & 0xffff; 904 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 905 onoff("66 MHz capable", 0x0020); 906 onoff("User Definable Features (UDF) support", 0x0040); 907 onoff("Fast back-to-back capable", 0x0080); 908 onoff("Data parity error detected", 0x0100); 909 910 printf(" DEVSEL timing: "); 911 switch (rval & 0x0600) { 912 case 0x0000: 913 printf("fast"); 914 break; 915 case 0x0200: 916 printf("medium"); 917 break; 918 case 0x0400: 919 printf("slow"); 920 break; 921 default: 922 printf("unknown/reserved"); /* XXX */ 923 break; 924 } 925 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 926 927 onoff("Signaled Target Abort", 0x0800); 928 onoff("Received Target Abort", 0x1000); 929 onoff("Received Master Abort", 0x2000); 930 onoff("System Error", 0x4000); 931 onoff("Parity Error", 0x8000); 932 933 /* XXX Print more prettily */ 934 printf(" I/O region:\n"); 935 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 936 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 937 printf(" base upper 16 bits register: 0x%04x\n", 938 (regs[o2i(0x30)] >> 0) & 0xffff); 939 printf(" limit upper 16 bits register: 0x%04x\n", 940 (regs[o2i(0x30)] >> 16) & 0xffff); 941 942 /* XXX Print more prettily */ 943 printf(" Memory region:\n"); 944 printf(" base register: 0x%04x\n", 945 (regs[o2i(0x20)] >> 0) & 0xffff); 946 printf(" limit register: 0x%04x\n", 947 (regs[o2i(0x20)] >> 16) & 0xffff); 948 949 /* XXX Print more prettily */ 950 printf(" Prefetchable memory region:\n"); 951 printf(" base register: 0x%04x\n", 952 (regs[o2i(0x24)] >> 0) & 0xffff); 953 printf(" limit register: 0x%04x\n", 954 (regs[o2i(0x24)] >> 16) & 0xffff); 955 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 956 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 957 958 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 959 printf(" Capability list pointer: 0x%02x\n", 960 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 961 else 962 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 963 964 /* XXX */ 965 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 966 967 printf(" Interrupt line: 0x%02x\n", 968 (regs[o2i(0x3c)] >> 0) & 0xff); 969 printf(" Interrupt pin: 0x%02x ", 970 (regs[o2i(0x3c)] >> 8) & 0xff); 971 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 972 case PCI_INTERRUPT_PIN_NONE: 973 printf("(none)"); 974 break; 975 case PCI_INTERRUPT_PIN_A: 976 printf("(pin A)"); 977 break; 978 case PCI_INTERRUPT_PIN_B: 979 printf("(pin B)"); 980 break; 981 case PCI_INTERRUPT_PIN_C: 982 printf("(pin C)"); 983 break; 984 case PCI_INTERRUPT_PIN_D: 985 printf("(pin D)"); 986 break; 987 default: 988 printf("(? ? ?)"); 989 break; 990 } 991 printf("\n"); 992 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 993 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 994 onoff("Parity error response", 0x0001); 995 onoff("Secondary SERR forwarding", 0x0002); 996 onoff("ISA enable", 0x0004); 997 onoff("VGA enable", 0x0008); 998 onoff("Master abort reporting", 0x0020); 999 onoff("Secondary bus reset", 0x0040); 1000 onoff("Fast back-to-back capable", 0x0080); 1001 } 1002 1003 static void 1004 pci_conf_print_type2( 1005 #ifdef _KERNEL 1006 pci_chipset_tag_t pc, pcitag_t tag, 1007 #endif 1008 const pcireg_t *regs 1009 #ifdef _KERNEL 1010 , int sizebars 1011 #endif 1012 ) 1013 { 1014 pcireg_t rval; 1015 1016 /* 1017 * XXX these need to be printed in more detail, need to be 1018 * XXX checked against specs/docs, etc. 1019 * 1020 * This layout was cribbed from the TI PCI1130 PCI-to-CardBus 1021 * controller chip documentation, and may not be correct with 1022 * respect to various standards. (XXX) 1023 */ 1024 1025 #ifdef _KERNEL 1026 pci_conf_print_bar(pc, tag, regs, 0x10, 1027 "CardBus socket/ExCA registers", sizebars); 1028 #else 1029 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 1030 #endif 1031 1032 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1033 printf(" Capability list pointer: 0x%02x\n", 1034 PCI_CAPLIST_PTR(regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)])); 1035 else 1036 printf(" Reserved @ 0x14: 0x%04x\n", 1037 (regs[o2i(0x14)] >> 0) & 0xffff); 1038 rval = (regs[o2i(0x14)] >> 16) & 0xffff; 1039 printf(" Secondary status register: 0x%04x\n", rval); 1040 onoff("66 MHz capable", 0x0020); 1041 onoff("User Definable Features (UDF) support", 0x0040); 1042 onoff("Fast back-to-back capable", 0x0080); 1043 onoff("Data parity error detection", 0x0100); 1044 1045 printf(" DEVSEL timing: "); 1046 switch (rval & 0x0600) { 1047 case 0x0000: 1048 printf("fast"); 1049 break; 1050 case 0x0200: 1051 printf("medium"); 1052 break; 1053 case 0x0400: 1054 printf("slow"); 1055 break; 1056 default: 1057 printf("unknown/reserved"); /* XXX */ 1058 break; 1059 } 1060 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 1061 onoff("PCI target aborts terminate CardBus bus master transactions", 1062 0x0800); 1063 onoff("CardBus target aborts terminate PCI bus master transactions", 1064 0x1000); 1065 onoff("Bus initiator aborts terminate initiator transactions", 1066 0x2000); 1067 onoff("System error", 0x4000); 1068 onoff("Parity error", 0x8000); 1069 1070 printf(" PCI bus number: 0x%02x\n", 1071 (regs[o2i(0x18)] >> 0) & 0xff); 1072 printf(" CardBus bus number: 0x%02x\n", 1073 (regs[o2i(0x18)] >> 8) & 0xff); 1074 printf(" Subordinate bus number: 0x%02x\n", 1075 (regs[o2i(0x18)] >> 16) & 0xff); 1076 printf(" CardBus latency timer: 0x%02x\n", 1077 (regs[o2i(0x18)] >> 24) & 0xff); 1078 1079 /* XXX Print more prettily */ 1080 printf(" CardBus memory region 0:\n"); 1081 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1082 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1083 printf(" CardBus memory region 1:\n"); 1084 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1085 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1086 printf(" CardBus I/O region 0:\n"); 1087 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1088 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1089 printf(" CardBus I/O region 1:\n"); 1090 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1091 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1092 1093 printf(" Interrupt line: 0x%02x\n", 1094 (regs[o2i(0x3c)] >> 0) & 0xff); 1095 printf(" Interrupt pin: 0x%02x ", 1096 (regs[o2i(0x3c)] >> 8) & 0xff); 1097 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1098 case PCI_INTERRUPT_PIN_NONE: 1099 printf("(none)"); 1100 break; 1101 case PCI_INTERRUPT_PIN_A: 1102 printf("(pin A)"); 1103 break; 1104 case PCI_INTERRUPT_PIN_B: 1105 printf("(pin B)"); 1106 break; 1107 case PCI_INTERRUPT_PIN_C: 1108 printf("(pin C)"); 1109 break; 1110 case PCI_INTERRUPT_PIN_D: 1111 printf("(pin D)"); 1112 break; 1113 default: 1114 printf("(? ? ?)"); 1115 break; 1116 } 1117 printf("\n"); 1118 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1119 printf(" Bridge control register: 0x%04x\n", rval); 1120 onoff("Parity error response", 0x0001); 1121 onoff("CardBus SERR forwarding", 0x0002); 1122 onoff("ISA enable", 0x0004); 1123 onoff("VGA enable", 0x0008); 1124 onoff("CardBus master abort reporting", 0x0020); 1125 onoff("CardBus reset", 0x0040); 1126 onoff("Functional interrupts routed by ExCA registers", 0x0080); 1127 onoff("Memory window 0 prefetchable", 0x0100); 1128 onoff("Memory window 1 prefetchable", 0x0200); 1129 onoff("Write posting enable", 0x0400); 1130 1131 rval = regs[o2i(0x40)]; 1132 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1133 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1134 1135 #ifdef _KERNEL 1136 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1137 sizebars); 1138 #else 1139 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 1140 #endif 1141 } 1142 1143 void 1144 pci_conf_print( 1145 #ifdef _KERNEL 1146 pci_chipset_tag_t pc, pcitag_t tag, 1147 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 1148 #else 1149 int pcifd, u_int bus, u_int dev, u_int func 1150 #endif 1151 ) 1152 { 1153 pcireg_t regs[o2i(256)]; 1154 int off, capoff, endoff, hdrtype; 1155 const char *typename; 1156 #ifdef _KERNEL 1157 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1158 int sizebars; 1159 #else 1160 void (*typeprintfn)(const pcireg_t *); 1161 #endif 1162 1163 printf("PCI configuration registers:\n"); 1164 1165 for (off = 0; off < 256; off += 4) { 1166 #ifdef _KERNEL 1167 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1168 #else 1169 if (pcibus_conf_read(pcifd, bus, dev, func, off, 1170 ®s[o2i(off)]) == -1) 1171 regs[o2i(off)] = 0; 1172 #endif 1173 } 1174 1175 #ifdef _KERNEL 1176 sizebars = 1; 1177 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1178 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1179 sizebars = 0; 1180 #endif 1181 1182 /* common header */ 1183 printf(" Common header:\n"); 1184 pci_conf_print_regs(regs, 0, 16); 1185 1186 printf("\n"); 1187 #ifdef _KERNEL 1188 pci_conf_print_common(pc, tag, regs); 1189 #else 1190 pci_conf_print_common(regs); 1191 #endif 1192 printf("\n"); 1193 1194 /* type-dependent header */ 1195 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1196 switch (hdrtype) { /* XXX make a table, eventually */ 1197 case 0: 1198 /* Standard device header */ 1199 typename = "\"normal\" device"; 1200 typeprintfn = &pci_conf_print_type0; 1201 capoff = PCI_CAPLISTPTR_REG; 1202 endoff = 64; 1203 break; 1204 case 1: 1205 /* PCI-PCI bridge header */ 1206 typename = "PCI-PCI bridge"; 1207 typeprintfn = &pci_conf_print_type1; 1208 capoff = PCI_CAPLISTPTR_REG; 1209 endoff = 64; 1210 break; 1211 case 2: 1212 /* PCI-CardBus bridge header */ 1213 typename = "PCI-CardBus bridge"; 1214 typeprintfn = &pci_conf_print_type2; 1215 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 1216 endoff = 72; 1217 break; 1218 default: 1219 typename = NULL; 1220 typeprintfn = 0; 1221 capoff = -1; 1222 endoff = 64; 1223 break; 1224 } 1225 printf(" Type %d ", hdrtype); 1226 if (typename != NULL) 1227 printf("(%s) ", typename); 1228 printf("header:\n"); 1229 pci_conf_print_regs(regs, 16, endoff); 1230 printf("\n"); 1231 if (typeprintfn) { 1232 #ifdef _KERNEL 1233 (*typeprintfn)(pc, tag, regs, sizebars); 1234 #else 1235 (*typeprintfn)(regs); 1236 #endif 1237 } else 1238 printf(" Don't know how to pretty-print type %d header.\n", 1239 hdrtype); 1240 printf("\n"); 1241 1242 /* capability list, if present */ 1243 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1244 && (capoff > 0)) { 1245 #ifdef _KERNEL 1246 pci_conf_print_caplist(pc, tag, regs, capoff); 1247 #else 1248 pci_conf_print_caplist(regs, capoff); 1249 #endif 1250 printf("\n"); 1251 } 1252 1253 /* device-dependent header */ 1254 printf(" Device-dependent header:\n"); 1255 pci_conf_print_regs(regs, endoff, 256); 1256 printf("\n"); 1257 #ifdef _KERNEL 1258 if (printfn) 1259 (*printfn)(pc, tag, regs); 1260 else 1261 printf(" Don't know how to pretty-print device-dependent header.\n"); 1262 printf("\n"); 1263 #endif /* _KERNEL */ 1264 } 1265
Indexes created Wed Sep 24 14:09:57 GMT 2025