pci_subr.c revision 1.75.10.1
1 /* $NetBSD: pci_subr.c,v 1.75.10.1 2009/02/24 03:50:48 snj Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.75.10.1 2009/02/24 03:50:48 snj Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #else 55 #include <pci.h> 56 #include <stdbool.h> 57 #include <stdio.h> 58 #endif 59 60 #include <dev/pci/pcireg.h> 61 #ifdef _KERNEL 62 #include <dev/pci/pcivar.h> 63 #endif 64 #ifdef PCIVERBOSE 65 #include <dev/pci/pcidevs.h> 66 #endif 67 68 /* 69 * Descriptions of known PCI classes and subclasses. 70 * 71 * Subclasses are described in the same way as classes, but have a 72 * NULL subclass pointer. 73 */ 74 struct pci_class { 75 const char *name; 76 int val; /* as wide as pci_{,sub}class_t */ 77 const struct pci_class *subclasses; 78 }; 79 80 static const struct pci_class pci_subclass_prehistoric[] = { 81 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 82 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 83 { NULL, 0, NULL, }, 84 }; 85 86 static const struct pci_class pci_subclass_mass_storage[] = { 87 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 88 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 89 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 90 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 91 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 92 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, NULL, }, 93 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, NULL, }, 94 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 95 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 96 { NULL, 0, NULL, }, 97 }; 98 99 static const struct pci_class pci_subclass_network[] = { 100 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 101 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 102 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 103 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 104 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 105 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 106 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 107 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 108 { NULL, 0, NULL, }, 109 }; 110 111 static const struct pci_class pci_subclass_display[] = { 112 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, NULL, }, 113 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 114 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 115 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 116 { NULL, 0, NULL, }, 117 }; 118 119 static const struct pci_class pci_subclass_multimedia[] = { 120 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 121 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 122 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 123 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 124 { NULL, 0, NULL, }, 125 }; 126 127 static const struct pci_class pci_subclass_memory[] = { 128 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 129 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 130 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 131 { NULL, 0, NULL, }, 132 }; 133 134 static const struct pci_class pci_subclass_bridge[] = { 135 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 136 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 137 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 138 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 139 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, NULL, }, 140 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 141 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 142 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 143 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 144 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, NULL, }, 145 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 146 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 147 { NULL, 0, NULL, }, 148 }; 149 150 static const struct pci_class pci_subclass_communications[] = { 151 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, NULL, }, 152 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, NULL, }, 153 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL, }, 154 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, NULL, }, 155 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL, }, 156 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL, }, 157 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL, }, 158 { NULL, 0, NULL, }, 159 }; 160 161 static const struct pci_class pci_subclass_system[] = { 162 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, NULL, }, 163 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, NULL, }, 164 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, NULL, }, 165 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, NULL, }, 166 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 167 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 168 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 169 { NULL, 0, NULL, }, 170 }; 171 172 static const struct pci_class pci_subclass_input[] = { 173 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 174 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 175 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 176 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 177 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, NULL, }, 178 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 179 { NULL, 0, NULL, }, 180 }; 181 182 static const struct pci_class pci_subclass_dock[] = { 183 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 184 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 185 { NULL, 0, NULL, }, 186 }; 187 188 static const struct pci_class pci_subclass_processor[] = { 189 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 190 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 191 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 192 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 193 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 194 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 195 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 196 { NULL, 0, NULL, }, 197 }; 198 199 static const struct pci_class pci_subclass_serialbus[] = { 200 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, NULL, }, 201 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 202 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 203 { "USB", PCI_SUBCLASS_SERIALBUS_USB, NULL, }, 204 /* XXX Fiber Channel/_FIBRECHANNEL */ 205 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 206 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 207 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 208 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, NULL, }, 209 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 210 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 211 { NULL, 0, NULL, }, 212 }; 213 214 static const struct pci_class pci_subclass_wireless[] = { 215 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 216 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 217 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 218 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 219 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 220 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 221 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 222 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 223 { NULL, 0, NULL, }, 224 }; 225 226 static const struct pci_class pci_subclass_i2o[] = { 227 { "standard", PCI_SUBCLASS_I2O_STANDARD, NULL, }, 228 { NULL, 0, NULL, }, 229 }; 230 231 static const struct pci_class pci_subclass_satcom[] = { 232 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 233 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 234 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 235 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 236 { NULL, 0, NULL, }, 237 }; 238 239 static const struct pci_class pci_subclass_crypto[] = { 240 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 241 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 242 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 243 { NULL, 0, NULL, }, 244 }; 245 246 static const struct pci_class pci_subclass_dasp[] = { 247 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 248 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 249 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 250 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 251 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 252 { NULL, 0, NULL, }, 253 }; 254 255 static const struct pci_class pci_class[] = { 256 { "prehistoric", PCI_CLASS_PREHISTORIC, 257 pci_subclass_prehistoric, }, 258 { "mass storage", PCI_CLASS_MASS_STORAGE, 259 pci_subclass_mass_storage, }, 260 { "network", PCI_CLASS_NETWORK, 261 pci_subclass_network, }, 262 { "display", PCI_CLASS_DISPLAY, 263 pci_subclass_display, }, 264 { "multimedia", PCI_CLASS_MULTIMEDIA, 265 pci_subclass_multimedia, }, 266 { "memory", PCI_CLASS_MEMORY, 267 pci_subclass_memory, }, 268 { "bridge", PCI_CLASS_BRIDGE, 269 pci_subclass_bridge, }, 270 { "communications", PCI_CLASS_COMMUNICATIONS, 271 pci_subclass_communications, }, 272 { "system", PCI_CLASS_SYSTEM, 273 pci_subclass_system, }, 274 { "input", PCI_CLASS_INPUT, 275 pci_subclass_input, }, 276 { "dock", PCI_CLASS_DOCK, 277 pci_subclass_dock, }, 278 { "processor", PCI_CLASS_PROCESSOR, 279 pci_subclass_processor, }, 280 { "serial bus", PCI_CLASS_SERIALBUS, 281 pci_subclass_serialbus, }, 282 { "wireless", PCI_CLASS_WIRELESS, 283 pci_subclass_wireless, }, 284 { "I2O", PCI_CLASS_I2O, 285 pci_subclass_i2o, }, 286 { "satellite comm", PCI_CLASS_SATCOM, 287 pci_subclass_satcom, }, 288 { "crypto", PCI_CLASS_CRYPTO, 289 pci_subclass_crypto, }, 290 { "DASP", PCI_CLASS_DASP, 291 pci_subclass_dasp, }, 292 { "undefined", PCI_CLASS_UNDEFINED, 293 NULL, }, 294 { NULL, 0, 295 NULL, }, 296 }; 297 298 #ifdef PCIVERBOSE 299 /* 300 * Descriptions of of known vendors and devices ("products"). 301 */ 302 struct pci_vendor { 303 pci_vendor_id_t vendor; 304 const char *vendorname; 305 }; 306 struct pci_product { 307 pci_vendor_id_t vendor; 308 pci_product_id_t product; 309 const char *productname; 310 }; 311 312 #include <dev/pci/pcidevs_data.h> 313 #endif /* PCIVERBOSE */ 314 315 const char * 316 pci_findvendor(pcireg_t id_reg) 317 { 318 #ifdef PCIVERBOSE 319 pci_vendor_id_t vendor = PCI_VENDOR(id_reg); 320 int n; 321 322 for (n = 0; n < pci_nvendors; n++) 323 if (pci_vendors[n].vendor == vendor) 324 return (pci_vendors[n].vendorname); 325 #endif 326 return (NULL); 327 } 328 329 const char * 330 pci_findproduct(pcireg_t id_reg) 331 { 332 #ifdef PCIVERBOSE 333 pci_vendor_id_t vendor = PCI_VENDOR(id_reg); 334 pci_product_id_t product = PCI_PRODUCT(id_reg); 335 int n; 336 337 for (n = 0; n < pci_nproducts; n++) 338 if (pci_products[n].vendor == vendor && 339 pci_products[n].product == product) 340 return (pci_products[n].productname); 341 #endif 342 return (NULL); 343 } 344 345 void 346 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 347 size_t l) 348 { 349 pci_vendor_id_t vendor; 350 pci_product_id_t product; 351 pci_class_t class; 352 pci_subclass_t subclass; 353 pci_interface_t interface; 354 pci_revision_t revision; 355 const char *vendor_namep, *product_namep; 356 const struct pci_class *classp, *subclassp; 357 #ifdef PCIVERBOSE 358 const char *unmatched = "unknown "; 359 #else 360 const char *unmatched = ""; 361 #endif 362 char *ep; 363 364 ep = cp + l; 365 366 vendor = PCI_VENDOR(id_reg); 367 product = PCI_PRODUCT(id_reg); 368 369 class = PCI_CLASS(class_reg); 370 subclass = PCI_SUBCLASS(class_reg); 371 interface = PCI_INTERFACE(class_reg); 372 revision = PCI_REVISION(class_reg); 373 374 vendor_namep = pci_findvendor(id_reg); 375 product_namep = pci_findproduct(id_reg); 376 377 classp = pci_class; 378 while (classp->name != NULL) { 379 if (class == classp->val) 380 break; 381 classp++; 382 } 383 384 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 385 while (subclassp && subclassp->name != NULL) { 386 if (subclass == subclassp->val) 387 break; 388 subclassp++; 389 } 390 391 if (vendor_namep == NULL) 392 cp += snprintf(cp, ep - cp, "%svendor 0x%04x product 0x%04x", 393 unmatched, vendor, product); 394 else if (product_namep != NULL) 395 cp += snprintf(cp, ep - cp, "%s %s", vendor_namep, 396 product_namep); 397 else 398 cp += snprintf(cp, ep - cp, "%s product 0x%04x", 399 vendor_namep, product); 400 if (showclass) { 401 cp += snprintf(cp, ep - cp, " ("); 402 if (classp->name == NULL) 403 cp += snprintf(cp, ep - cp, 404 "class 0x%02x, subclass 0x%02x", class, subclass); 405 else { 406 if (subclassp == NULL || subclassp->name == NULL) 407 cp += snprintf(cp, ep - cp, 408 "%s subclass 0x%02x", 409 classp->name, subclass); 410 else 411 cp += snprintf(cp, ep - cp, "%s %s", 412 subclassp->name, classp->name); 413 } 414 if (interface != 0) 415 cp += snprintf(cp, ep - cp, ", interface 0x%02x", 416 interface); 417 if (revision != 0) 418 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 419 revision); 420 cp += snprintf(cp, ep - cp, ")"); 421 } 422 } 423 424 /* 425 * Print out most of the PCI configuration registers. Typically used 426 * in a device attach routine like this: 427 * 428 * #ifdef MYDEV_DEBUG 429 * printf("%s: ", device_xname(&sc->sc_dev)); 430 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 431 * #endif 432 */ 433 434 #define i2o(i) ((i) * 4) 435 #define o2i(o) ((o) / 4) 436 #define onoff(str, bit) \ 437 printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off"); 438 439 static void 440 pci_conf_print_common( 441 #ifdef _KERNEL 442 pci_chipset_tag_t pc, pcitag_t tag, 443 #endif 444 const pcireg_t *regs) 445 { 446 const char *name; 447 const struct pci_class *classp, *subclassp; 448 pcireg_t rval; 449 450 rval = regs[o2i(PCI_ID_REG)]; 451 name = pci_findvendor(rval); 452 if (name) 453 printf(" Vendor Name: %s (0x%04x)\n", name, 454 PCI_VENDOR(rval)); 455 else 456 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 457 name = pci_findproduct(rval); 458 if (name) 459 printf(" Device Name: %s (0x%04x)\n", name, 460 PCI_PRODUCT(rval)); 461 else 462 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 463 464 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 465 466 printf(" Command register: 0x%04x\n", rval & 0xffff); 467 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 468 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 469 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 470 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 471 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 472 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 473 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 474 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 475 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 476 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 477 onoff("Interrupt disable", PCI_COMMAND_INTERRUPT_DISABLE); 478 479 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 480 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 481 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 482 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 483 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 484 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 485 486 printf(" DEVSEL timing: "); 487 switch (rval & PCI_STATUS_DEVSEL_MASK) { 488 case PCI_STATUS_DEVSEL_FAST: 489 printf("fast"); 490 break; 491 case PCI_STATUS_DEVSEL_MEDIUM: 492 printf("medium"); 493 break; 494 case PCI_STATUS_DEVSEL_SLOW: 495 printf("slow"); 496 break; 497 default: 498 printf("unknown/reserved"); /* XXX */ 499 break; 500 } 501 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 502 503 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 504 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 505 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 506 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 507 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 508 509 rval = regs[o2i(PCI_CLASS_REG)]; 510 for (classp = pci_class; classp->name != NULL; classp++) { 511 if (PCI_CLASS(rval) == classp->val) 512 break; 513 } 514 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 515 while (subclassp && subclassp->name != NULL) { 516 if (PCI_SUBCLASS(rval) == subclassp->val) 517 break; 518 subclassp++; 519 } 520 if (classp->name != NULL) { 521 printf(" Class Name: %s (0x%02x)\n", classp->name, 522 PCI_CLASS(rval)); 523 if (subclassp != NULL && subclassp->name != NULL) 524 printf(" Subclass Name: %s (0x%02x)\n", 525 subclassp->name, PCI_SUBCLASS(rval)); 526 else 527 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 528 } else { 529 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 530 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 531 } 532 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 533 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 534 535 rval = regs[o2i(PCI_BHLC_REG)]; 536 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 537 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 538 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 539 PCI_HDRTYPE(rval)); 540 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 541 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 542 } 543 544 static int 545 pci_conf_print_bar( 546 #ifdef _KERNEL 547 pci_chipset_tag_t pc, pcitag_t tag, 548 #endif 549 const pcireg_t *regs, int reg, const char *name 550 #ifdef _KERNEL 551 , int sizebar 552 #endif 553 ) 554 { 555 int width; 556 pcireg_t rval, rval64h; 557 #ifdef _KERNEL 558 int s; 559 pcireg_t mask, mask64h; 560 #endif 561 562 width = 4; 563 564 /* 565 * Section 6.2.5.1, `Address Maps', tells us that: 566 * 567 * 1) The builtin software should have already mapped the 568 * device in a reasonable way. 569 * 570 * 2) A device which wants 2^n bytes of memory will hardwire 571 * the bottom n bits of the address to 0. As recommended, 572 * we write all 1s and see what we get back. 573 */ 574 575 rval = regs[o2i(reg)]; 576 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 577 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 578 rval64h = regs[o2i(reg + 4)]; 579 width = 8; 580 } else 581 rval64h = 0; 582 583 #ifdef _KERNEL 584 /* XXX don't size unknown memory type? */ 585 if (rval != 0 && sizebar) { 586 /* 587 * The following sequence seems to make some devices 588 * (e.g. host bus bridges, which don't normally 589 * have their space mapped) very unhappy, to 590 * the point of crashing the system. 591 * 592 * Therefore, if the mapping register is zero to 593 * start out with, don't bother trying. 594 */ 595 s = splhigh(); 596 pci_conf_write(pc, tag, reg, 0xffffffff); 597 mask = pci_conf_read(pc, tag, reg); 598 pci_conf_write(pc, tag, reg, rval); 599 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 600 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 601 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 602 mask64h = pci_conf_read(pc, tag, reg + 4); 603 pci_conf_write(pc, tag, reg + 4, rval64h); 604 } else 605 mask64h = 0; 606 splx(s); 607 } else 608 mask = mask64h = 0; 609 #endif /* _KERNEL */ 610 611 printf(" Base address register at 0x%02x", reg); 612 if (name) 613 printf(" (%s)", name); 614 printf("\n "); 615 if (rval == 0) { 616 printf("not implemented(?)\n"); 617 return width; 618 } 619 printf("type: "); 620 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 621 const char *type, *prefetch; 622 623 switch (PCI_MAPREG_MEM_TYPE(rval)) { 624 case PCI_MAPREG_MEM_TYPE_32BIT: 625 type = "32-bit"; 626 break; 627 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 628 type = "32-bit-1M"; 629 break; 630 case PCI_MAPREG_MEM_TYPE_64BIT: 631 type = "64-bit"; 632 break; 633 default: 634 type = "unknown (XXX)"; 635 break; 636 } 637 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 638 prefetch = ""; 639 else 640 prefetch = "non"; 641 printf("%s %sprefetchable memory\n", type, prefetch); 642 switch (PCI_MAPREG_MEM_TYPE(rval)) { 643 case PCI_MAPREG_MEM_TYPE_64BIT: 644 printf(" base: 0x%016llx, ", 645 PCI_MAPREG_MEM64_ADDR( 646 ((((long long) rval64h) << 32) | rval))); 647 #ifdef _KERNEL 648 if (sizebar) 649 printf("size: 0x%016llx", 650 PCI_MAPREG_MEM64_SIZE( 651 ((((long long) mask64h) << 32) | mask))); 652 else 653 #endif /* _KERNEL */ 654 printf("not sized"); 655 printf("\n"); 656 break; 657 case PCI_MAPREG_MEM_TYPE_32BIT: 658 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 659 default: 660 printf(" base: 0x%08x, ", 661 PCI_MAPREG_MEM_ADDR(rval)); 662 #ifdef _KERNEL 663 if (sizebar) 664 printf("size: 0x%08x", 665 PCI_MAPREG_MEM_SIZE(mask)); 666 else 667 #endif /* _KERNEL */ 668 printf("not sized"); 669 printf("\n"); 670 break; 671 } 672 } else { 673 #ifdef _KERNEL 674 if (sizebar) 675 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 676 #endif /* _KERNEL */ 677 printf("i/o\n"); 678 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 679 #ifdef _KERNEL 680 if (sizebar) 681 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 682 else 683 #endif /* _KERNEL */ 684 printf("not sized"); 685 printf("\n"); 686 } 687 688 return width; 689 } 690 691 static void 692 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 693 { 694 int off, needaddr, neednl; 695 696 needaddr = 1; 697 neednl = 0; 698 for (off = first; off < pastlast; off += 4) { 699 if ((off % 16) == 0 || needaddr) { 700 printf(" 0x%02x:", off); 701 needaddr = 0; 702 } 703 printf(" 0x%08x", regs[o2i(off)]); 704 neednl = 1; 705 if ((off % 16) == 12) { 706 printf("\n"); 707 neednl = 0; 708 } 709 } 710 if (neednl) 711 printf("\n"); 712 } 713 714 static void 715 pci_conf_print_type0( 716 #ifdef _KERNEL 717 pci_chipset_tag_t pc, pcitag_t tag, 718 #endif 719 const pcireg_t *regs 720 #ifdef _KERNEL 721 , int sizebars 722 #endif 723 ) 724 { 725 int off, width; 726 pcireg_t rval; 727 728 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 729 #ifdef _KERNEL 730 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 731 #else 732 width = pci_conf_print_bar(regs, off, NULL); 733 #endif 734 } 735 736 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 737 738 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 739 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 740 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 741 742 /* XXX */ 743 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 744 745 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 746 printf(" Capability list pointer: 0x%02x\n", 747 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 748 else 749 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 750 751 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 752 753 rval = regs[o2i(PCI_INTERRUPT_REG)]; 754 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 755 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 756 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 757 switch (PCI_INTERRUPT_PIN(rval)) { 758 case PCI_INTERRUPT_PIN_NONE: 759 printf("(none)"); 760 break; 761 case PCI_INTERRUPT_PIN_A: 762 printf("(pin A)"); 763 break; 764 case PCI_INTERRUPT_PIN_B: 765 printf("(pin B)"); 766 break; 767 case PCI_INTERRUPT_PIN_C: 768 printf("(pin C)"); 769 break; 770 case PCI_INTERRUPT_PIN_D: 771 printf("(pin D)"); 772 break; 773 default: 774 printf("(? ? ?)"); 775 break; 776 } 777 printf("\n"); 778 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 779 } 780 781 static void 782 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 783 { 784 bool check_slot = false; 785 786 printf("\n PCI Express Capabilities Register\n"); 787 printf(" Capability version: %x\n", 788 (unsigned int)((regs[o2i(capoff)] & 0x000f0000) >> 16)); 789 printf(" Device type: "); 790 switch ((regs[o2i(capoff)] & 0x00f00000) >> 20) { 791 case 0x0: 792 printf("PCI Express Endpoint device\n"); 793 break; 794 case 0x1: 795 printf("Legacy PCI Express Endpoint device\n"); 796 break; 797 case 0x4: 798 printf("Root Port of PCI Express Root Complex\n"); 799 check_slot = true; 800 break; 801 case 0x5: 802 printf("Upstream Port of PCI Express Switch\n"); 803 break; 804 case 0x6: 805 printf("Downstream Port of PCI Express Switch\n"); 806 check_slot = true; 807 break; 808 case 0x7: 809 printf("PCI Express to PCI/PCI-X Bridge\n"); 810 break; 811 case 0x8: 812 printf("PCI/PCI-X to PCI Express Bridge\n"); 813 break; 814 default: 815 printf("unknown\n"); 816 break; 817 } 818 if (check_slot && (regs[o2i(capoff)] & 0x01000000) != 0) 819 printf(" Slot implemented\n"); 820 printf(" Interrupt Message Number: %x\n", 821 (unsigned int)((regs[o2i(capoff)] & 0x4e000000) >> 27)); 822 if ((regs[o2i(capoff + 0x18)] & 0x07ff) != 0) { 823 printf(" Slot Control Register:\n"); 824 if ((regs[o2i(capoff + 0x18)] & 0x0001) != 0) 825 printf(" Attention Button Pressed Enabled\n"); 826 if ((regs[o2i(capoff + 0x18)] & 0x0002) != 0) 827 printf(" Power Fault Detected Enabled\n"); 828 if ((regs[o2i(capoff + 0x18)] & 0x0004) != 0) 829 printf(" MRL Sensor Changed Enabled\n"); 830 if ((regs[o2i(capoff + 0x18)] & 0x0008) != 0) 831 printf(" Presense Detected Changed Enabled\n"); 832 if ((regs[o2i(capoff + 0x18)] & 0x0010) != 0) 833 printf(" Command Completed Interrupt Enabled\n"); 834 if ((regs[o2i(capoff + 0x18)] & 0x0020) != 0) 835 printf(" Hot-Plug Interrupt Enabled\n"); 836 printf(" Attention Indictor Control: "); 837 switch ((regs[o2i(capoff + 0x18)] & 0x00a0) >> 6) { 838 case 0x0: 839 printf("reserved\n"); 840 break; 841 case 0x1: 842 printf("on\n"); 843 break; 844 case 0x2: 845 printf("blink\n"); 846 break; 847 case 0x3: 848 printf("off\n"); 849 break; 850 } 851 printf(" Power Indictor Control: "); 852 switch ((regs[o2i(capoff + 0x18)] & 0x0300) >> 8) { 853 case 0x0: 854 printf("reserved\n"); 855 break; 856 case 0x1: 857 printf("on\n"); 858 break; 859 case 0x2: 860 printf("blink\n"); 861 break; 862 case 0x3: 863 printf("off\n"); 864 break; 865 } 866 printf(" Power Controller Control: "); 867 if ((regs[o2i(capoff + 0x18)] & 0x0400) != 0) 868 printf("off\n"); 869 else 870 printf("on\n"); 871 } 872 } 873 874 static const char * 875 pci_conf_print_pcipm_cap_aux(uint16_t caps) 876 { 877 switch ((caps >> 6) & 7) { 878 case 0: return "self-powered"; 879 case 1: return "55 mA"; 880 case 2: return "100 mA"; 881 case 3: return "160 mA"; 882 case 4: return "220 mA"; 883 case 5: return "270 mA"; 884 case 6: return "320 mA"; 885 case 7: 886 default: return "375 mA"; 887 } 888 } 889 890 static const char * 891 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 892 { 893 static const char unk[] = "unknown"; 894 static const char *pmrev[8] = { 895 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 896 }; 897 if (val > 7) 898 return unk; 899 return pmrev[val]; 900 } 901 902 static void 903 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 904 { 905 uint16_t caps, pmcsr; 906 907 caps = regs[o2i(capoff)] >> 16; 908 pmcsr = regs[o2i(capoff + 0x04)] & 0xffff; 909 910 printf("\n PCI Power Management Capabilities Register\n"); 911 912 printf(" Capabilities register: 0x%04x\n", caps); 913 printf(" Version: %s\n", 914 pci_conf_print_pcipm_cap_pmrev(caps & 0x3)); 915 printf(" PME# clock: %s\n", caps & 0x4 ? "on" : "off"); 916 printf(" Device specific initialization: %s\n", 917 caps & 0x20 ? "on" : "off"); 918 printf(" 3.3V auxiliary current: %s\n", 919 pci_conf_print_pcipm_cap_aux(caps)); 920 printf(" D1 power management state support: %s\n", 921 (caps >> 9) & 1 ? "on" : "off"); 922 printf(" D2 power management state support: %s\n", 923 (caps >> 10) & 1 ? "on" : "off"); 924 printf(" PME# support: 0x%02x\n", caps >> 11); 925 926 printf(" Control/status register: 0x%04x\n", pmcsr); 927 printf(" Power state: D%d\n", pmcsr & 3); 928 printf(" PCI Express reserved: %s\n", 929 (pmcsr >> 2) & 1 ? "on" : "off"); 930 printf(" No soft reset: %s\n", (pmcsr >> 3) & 1 ? "on" : "off"); 931 printf(" PME# assertion %sabled\n", 932 (pmcsr >> 8) & 1 ? "en" : "dis"); 933 printf(" PME# status: %s\n", (pmcsr >> 15) ? "on" : "off"); 934 } 935 936 static void 937 pci_conf_print_caplist( 938 #ifdef _KERNEL 939 pci_chipset_tag_t pc, pcitag_t tag, 940 #endif 941 const pcireg_t *regs, int capoff) 942 { 943 int off; 944 pcireg_t rval; 945 int pcie_off = -1, pcipm_off = -1; 946 947 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 948 off != 0; 949 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 950 rval = regs[o2i(off)]; 951 printf(" Capability register at 0x%02x\n", off); 952 953 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 954 switch (PCI_CAPLIST_CAP(rval)) { 955 case PCI_CAP_RESERVED0: 956 printf("reserved"); 957 break; 958 case PCI_CAP_PWRMGMT: 959 printf("Power Management, rev. %s", 960 pci_conf_print_pcipm_cap_pmrev((rval >> 0) & 0x07)); 961 pcipm_off = off; 962 break; 963 case PCI_CAP_AGP: 964 printf("AGP, rev. %d.%d", 965 PCI_CAP_AGP_MAJOR(rval), 966 PCI_CAP_AGP_MINOR(rval)); 967 break; 968 case PCI_CAP_VPD: 969 printf("VPD"); 970 break; 971 case PCI_CAP_SLOTID: 972 printf("SlotID"); 973 break; 974 case PCI_CAP_MSI: 975 printf("MSI"); 976 break; 977 case PCI_CAP_CPCI_HOTSWAP: 978 printf("CompactPCI Hot-swapping"); 979 break; 980 case PCI_CAP_PCIX: 981 printf("PCI-X"); 982 break; 983 case PCI_CAP_LDT: 984 printf("LDT"); 985 break; 986 case PCI_CAP_VENDSPEC: 987 printf("Vendor-specific"); 988 break; 989 case PCI_CAP_DEBUGPORT: 990 printf("Debug Port"); 991 break; 992 case PCI_CAP_CPCI_RSRCCTL: 993 printf("CompactPCI Resource Control"); 994 break; 995 case PCI_CAP_HOTPLUG: 996 printf("Hot-Plug"); 997 break; 998 case PCI_CAP_AGP8: 999 printf("AGP 8x"); 1000 break; 1001 case PCI_CAP_SECURE: 1002 printf("Secure Device"); 1003 break; 1004 case PCI_CAP_PCIEXPRESS: 1005 printf("PCI Express"); 1006 pcie_off = off; 1007 break; 1008 case PCI_CAP_MSIX: 1009 printf("MSI-X"); 1010 break; 1011 default: 1012 printf("unknown"); 1013 } 1014 printf(")\n"); 1015 } 1016 if (pcipm_off != -1) 1017 pci_conf_print_pcipm_cap(regs, pcipm_off); 1018 if (pcie_off != -1) 1019 pci_conf_print_pcie_cap(regs, pcie_off); 1020 } 1021 1022 static void 1023 pci_conf_print_type1( 1024 #ifdef _KERNEL 1025 pci_chipset_tag_t pc, pcitag_t tag, 1026 #endif 1027 const pcireg_t *regs 1028 #ifdef _KERNEL 1029 , int sizebars 1030 #endif 1031 ) 1032 { 1033 int off, width; 1034 pcireg_t rval; 1035 1036 /* 1037 * XXX these need to be printed in more detail, need to be 1038 * XXX checked against specs/docs, etc. 1039 * 1040 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 1041 * Bridge chip documentation, and may not be correct with 1042 * respect to various standards. (XXX) 1043 */ 1044 1045 for (off = 0x10; off < 0x18; off += width) { 1046 #ifdef _KERNEL 1047 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 1048 #else 1049 width = pci_conf_print_bar(regs, off, NULL); 1050 #endif 1051 } 1052 1053 printf(" Primary bus number: 0x%02x\n", 1054 (regs[o2i(0x18)] >> 0) & 0xff); 1055 printf(" Secondary bus number: 0x%02x\n", 1056 (regs[o2i(0x18)] >> 8) & 0xff); 1057 printf(" Subordinate bus number: 0x%02x\n", 1058 (regs[o2i(0x18)] >> 16) & 0xff); 1059 printf(" Secondary bus latency timer: 0x%02x\n", 1060 (regs[o2i(0x18)] >> 24) & 0xff); 1061 1062 rval = (regs[o2i(0x1c)] >> 16) & 0xffff; 1063 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 1064 onoff("66 MHz capable", 0x0020); 1065 onoff("User Definable Features (UDF) support", 0x0040); 1066 onoff("Fast back-to-back capable", 0x0080); 1067 onoff("Data parity error detected", 0x0100); 1068 1069 printf(" DEVSEL timing: "); 1070 switch (rval & 0x0600) { 1071 case 0x0000: 1072 printf("fast"); 1073 break; 1074 case 0x0200: 1075 printf("medium"); 1076 break; 1077 case 0x0400: 1078 printf("slow"); 1079 break; 1080 default: 1081 printf("unknown/reserved"); /* XXX */ 1082 break; 1083 } 1084 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 1085 1086 onoff("Signaled Target Abort", 0x0800); 1087 onoff("Received Target Abort", 0x1000); 1088 onoff("Received Master Abort", 0x2000); 1089 onoff("System Error", 0x4000); 1090 onoff("Parity Error", 0x8000); 1091 1092 /* XXX Print more prettily */ 1093 printf(" I/O region:\n"); 1094 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 1095 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 1096 printf(" base upper 16 bits register: 0x%04x\n", 1097 (regs[o2i(0x30)] >> 0) & 0xffff); 1098 printf(" limit upper 16 bits register: 0x%04x\n", 1099 (regs[o2i(0x30)] >> 16) & 0xffff); 1100 1101 /* XXX Print more prettily */ 1102 printf(" Memory region:\n"); 1103 printf(" base register: 0x%04x\n", 1104 (regs[o2i(0x20)] >> 0) & 0xffff); 1105 printf(" limit register: 0x%04x\n", 1106 (regs[o2i(0x20)] >> 16) & 0xffff); 1107 1108 /* XXX Print more prettily */ 1109 printf(" Prefetchable memory region:\n"); 1110 printf(" base register: 0x%04x\n", 1111 (regs[o2i(0x24)] >> 0) & 0xffff); 1112 printf(" limit register: 0x%04x\n", 1113 (regs[o2i(0x24)] >> 16) & 0xffff); 1114 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 1115 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 1116 1117 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1118 printf(" Capability list pointer: 0x%02x\n", 1119 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 1120 else 1121 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 1122 1123 /* XXX */ 1124 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 1125 1126 printf(" Interrupt line: 0x%02x\n", 1127 (regs[o2i(0x3c)] >> 0) & 0xff); 1128 printf(" Interrupt pin: 0x%02x ", 1129 (regs[o2i(0x3c)] >> 8) & 0xff); 1130 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1131 case PCI_INTERRUPT_PIN_NONE: 1132 printf("(none)"); 1133 break; 1134 case PCI_INTERRUPT_PIN_A: 1135 printf("(pin A)"); 1136 break; 1137 case PCI_INTERRUPT_PIN_B: 1138 printf("(pin B)"); 1139 break; 1140 case PCI_INTERRUPT_PIN_C: 1141 printf("(pin C)"); 1142 break; 1143 case PCI_INTERRUPT_PIN_D: 1144 printf("(pin D)"); 1145 break; 1146 default: 1147 printf("(? ? ?)"); 1148 break; 1149 } 1150 printf("\n"); 1151 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1152 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 1153 onoff("Parity error response", 0x0001); 1154 onoff("Secondary SERR forwarding", 0x0002); 1155 onoff("ISA enable", 0x0004); 1156 onoff("VGA enable", 0x0008); 1157 onoff("Master abort reporting", 0x0020); 1158 onoff("Secondary bus reset", 0x0040); 1159 onoff("Fast back-to-back capable", 0x0080); 1160 } 1161 1162 static void 1163 pci_conf_print_type2( 1164 #ifdef _KERNEL 1165 pci_chipset_tag_t pc, pcitag_t tag, 1166 #endif 1167 const pcireg_t *regs 1168 #ifdef _KERNEL 1169 , int sizebars 1170 #endif 1171 ) 1172 { 1173 pcireg_t rval; 1174 1175 /* 1176 * XXX these need to be printed in more detail, need to be 1177 * XXX checked against specs/docs, etc. 1178 * 1179 * This layout was cribbed from the TI PCI1130 PCI-to-CardBus 1180 * controller chip documentation, and may not be correct with 1181 * respect to various standards. (XXX) 1182 */ 1183 1184 #ifdef _KERNEL 1185 pci_conf_print_bar(pc, tag, regs, 0x10, 1186 "CardBus socket/ExCA registers", sizebars); 1187 #else 1188 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 1189 #endif 1190 1191 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1192 printf(" Capability list pointer: 0x%02x\n", 1193 PCI_CAPLIST_PTR(regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)])); 1194 else 1195 printf(" Reserved @ 0x14: 0x%04x\n", 1196 (regs[o2i(0x14)] >> 0) & 0xffff); 1197 rval = (regs[o2i(0x14)] >> 16) & 0xffff; 1198 printf(" Secondary status register: 0x%04x\n", rval); 1199 onoff("66 MHz capable", 0x0020); 1200 onoff("User Definable Features (UDF) support", 0x0040); 1201 onoff("Fast back-to-back capable", 0x0080); 1202 onoff("Data parity error detection", 0x0100); 1203 1204 printf(" DEVSEL timing: "); 1205 switch (rval & 0x0600) { 1206 case 0x0000: 1207 printf("fast"); 1208 break; 1209 case 0x0200: 1210 printf("medium"); 1211 break; 1212 case 0x0400: 1213 printf("slow"); 1214 break; 1215 default: 1216 printf("unknown/reserved"); /* XXX */ 1217 break; 1218 } 1219 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 1220 onoff("PCI target aborts terminate CardBus bus master transactions", 1221 0x0800); 1222 onoff("CardBus target aborts terminate PCI bus master transactions", 1223 0x1000); 1224 onoff("Bus initiator aborts terminate initiator transactions", 1225 0x2000); 1226 onoff("System error", 0x4000); 1227 onoff("Parity error", 0x8000); 1228 1229 printf(" PCI bus number: 0x%02x\n", 1230 (regs[o2i(0x18)] >> 0) & 0xff); 1231 printf(" CardBus bus number: 0x%02x\n", 1232 (regs[o2i(0x18)] >> 8) & 0xff); 1233 printf(" Subordinate bus number: 0x%02x\n", 1234 (regs[o2i(0x18)] >> 16) & 0xff); 1235 printf(" CardBus latency timer: 0x%02x\n", 1236 (regs[o2i(0x18)] >> 24) & 0xff); 1237 1238 /* XXX Print more prettily */ 1239 printf(" CardBus memory region 0:\n"); 1240 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1241 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1242 printf(" CardBus memory region 1:\n"); 1243 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1244 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1245 printf(" CardBus I/O region 0:\n"); 1246 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1247 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1248 printf(" CardBus I/O region 1:\n"); 1249 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1250 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1251 1252 printf(" Interrupt line: 0x%02x\n", 1253 (regs[o2i(0x3c)] >> 0) & 0xff); 1254 printf(" Interrupt pin: 0x%02x ", 1255 (regs[o2i(0x3c)] >> 8) & 0xff); 1256 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1257 case PCI_INTERRUPT_PIN_NONE: 1258 printf("(none)"); 1259 break; 1260 case PCI_INTERRUPT_PIN_A: 1261 printf("(pin A)"); 1262 break; 1263 case PCI_INTERRUPT_PIN_B: 1264 printf("(pin B)"); 1265 break; 1266 case PCI_INTERRUPT_PIN_C: 1267 printf("(pin C)"); 1268 break; 1269 case PCI_INTERRUPT_PIN_D: 1270 printf("(pin D)"); 1271 break; 1272 default: 1273 printf("(? ? ?)"); 1274 break; 1275 } 1276 printf("\n"); 1277 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1278 printf(" Bridge control register: 0x%04x\n", rval); 1279 onoff("Parity error response", 0x0001); 1280 onoff("CardBus SERR forwarding", 0x0002); 1281 onoff("ISA enable", 0x0004); 1282 onoff("VGA enable", 0x0008); 1283 onoff("CardBus master abort reporting", 0x0020); 1284 onoff("CardBus reset", 0x0040); 1285 onoff("Functional interrupts routed by ExCA registers", 0x0080); 1286 onoff("Memory window 0 prefetchable", 0x0100); 1287 onoff("Memory window 1 prefetchable", 0x0200); 1288 onoff("Write posting enable", 0x0400); 1289 1290 rval = regs[o2i(0x40)]; 1291 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1292 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1293 1294 #ifdef _KERNEL 1295 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1296 sizebars); 1297 #else 1298 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 1299 #endif 1300 } 1301 1302 void 1303 pci_conf_print( 1304 #ifdef _KERNEL 1305 pci_chipset_tag_t pc, pcitag_t tag, 1306 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 1307 #else 1308 int pcifd, u_int bus, u_int dev, u_int func 1309 #endif 1310 ) 1311 { 1312 pcireg_t regs[o2i(256)]; 1313 int off, capoff, endoff, hdrtype; 1314 const char *typename; 1315 #ifdef _KERNEL 1316 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1317 int sizebars; 1318 #else 1319 void (*typeprintfn)(const pcireg_t *); 1320 #endif 1321 1322 printf("PCI configuration registers:\n"); 1323 1324 for (off = 0; off < 256; off += 4) { 1325 #ifdef _KERNEL 1326 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1327 #else 1328 if (pcibus_conf_read(pcifd, bus, dev, func, off, 1329 ®s[o2i(off)]) == -1) 1330 regs[o2i(off)] = 0; 1331 #endif 1332 } 1333 1334 #ifdef _KERNEL 1335 sizebars = 1; 1336 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1337 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1338 sizebars = 0; 1339 #endif 1340 1341 /* common header */ 1342 printf(" Common header:\n"); 1343 pci_conf_print_regs(regs, 0, 16); 1344 1345 printf("\n"); 1346 #ifdef _KERNEL 1347 pci_conf_print_common(pc, tag, regs); 1348 #else 1349 pci_conf_print_common(regs); 1350 #endif 1351 printf("\n"); 1352 1353 /* type-dependent header */ 1354 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1355 switch (hdrtype) { /* XXX make a table, eventually */ 1356 case 0: 1357 /* Standard device header */ 1358 typename = "\"normal\" device"; 1359 typeprintfn = &pci_conf_print_type0; 1360 capoff = PCI_CAPLISTPTR_REG; 1361 endoff = 64; 1362 break; 1363 case 1: 1364 /* PCI-PCI bridge header */ 1365 typename = "PCI-PCI bridge"; 1366 typeprintfn = &pci_conf_print_type1; 1367 capoff = PCI_CAPLISTPTR_REG; 1368 endoff = 64; 1369 break; 1370 case 2: 1371 /* PCI-CardBus bridge header */ 1372 typename = "PCI-CardBus bridge"; 1373 typeprintfn = &pci_conf_print_type2; 1374 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 1375 endoff = 72; 1376 break; 1377 default: 1378 typename = NULL; 1379 typeprintfn = 0; 1380 capoff = -1; 1381 endoff = 64; 1382 break; 1383 } 1384 printf(" Type %d ", hdrtype); 1385 if (typename != NULL) 1386 printf("(%s) ", typename); 1387 printf("header:\n"); 1388 pci_conf_print_regs(regs, 16, endoff); 1389 printf("\n"); 1390 if (typeprintfn) { 1391 #ifdef _KERNEL 1392 (*typeprintfn)(pc, tag, regs, sizebars); 1393 #else 1394 (*typeprintfn)(regs); 1395 #endif 1396 } else 1397 printf(" Don't know how to pretty-print type %d header.\n", 1398 hdrtype); 1399 printf("\n"); 1400 1401 /* capability list, if present */ 1402 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1403 && (capoff > 0)) { 1404 #ifdef _KERNEL 1405 pci_conf_print_caplist(pc, tag, regs, capoff); 1406 #else 1407 pci_conf_print_caplist(regs, capoff); 1408 #endif 1409 printf("\n"); 1410 } 1411 1412 /* device-dependent header */ 1413 printf(" Device-dependent header:\n"); 1414 pci_conf_print_regs(regs, endoff, 256); 1415 printf("\n"); 1416 #ifdef _KERNEL 1417 if (printfn) 1418 (*printfn)(pc, tag, regs); 1419 else 1420 printf(" Don't know how to pretty-print device-dependent header.\n"); 1421 printf("\n"); 1422 #endif /* _KERNEL */ 1423 } 1424
Indexes created Tue Sep 30 11:09:46 GMT 2025