pci_subr.c revision 1.76
1 /* $NetBSD: pci_subr.c,v 1.76 2008/11/17 23:33:41 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.76 2008/11/17 23:33:41 matt Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #else 55 #include <pci.h> 56 #include <stdbool.h> 57 #include <stdio.h> 58 #endif 59 60 #include <dev/pci/pcireg.h> 61 #ifdef _KERNEL 62 #include <dev/pci/pcivar.h> 63 #endif 64 #ifdef PCIVERBOSE 65 #include <dev/pci/pcidevs.h> 66 #endif 67 68 /* 69 * Descriptions of known PCI classes and subclasses. 70 * 71 * Subclasses are described in the same way as classes, but have a 72 * NULL subclass pointer. 73 */ 74 struct pci_class { 75 const char *name; 76 int val; /* as wide as pci_{,sub}class_t */ 77 const struct pci_class *subclasses; 78 }; 79 80 static const struct pci_class pci_subclass_prehistoric[] = { 81 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 82 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 83 { NULL, 0, NULL, }, 84 }; 85 86 static const struct pci_class pci_subclass_mass_storage[] = { 87 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 88 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 89 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 90 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 91 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 92 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, NULL, }, 93 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, NULL, }, 94 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 95 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 96 { NULL, 0, NULL, }, 97 }; 98 99 static const struct pci_class pci_subclass_network[] = { 100 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 101 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 102 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 103 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 104 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 105 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 106 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 107 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 108 { NULL, 0, NULL, }, 109 }; 110 111 static const struct pci_class pci_subclass_display[] = { 112 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, NULL, }, 113 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 114 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 115 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 116 { NULL, 0, NULL, }, 117 }; 118 119 static const struct pci_class pci_subclass_multimedia[] = { 120 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 121 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 122 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 123 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 124 { NULL, 0, NULL, }, 125 }; 126 127 static const struct pci_class pci_subclass_memory[] = { 128 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 129 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 130 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 131 { NULL, 0, NULL, }, 132 }; 133 134 static const struct pci_class pci_subclass_bridge[] = { 135 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 136 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 137 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 138 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 139 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, NULL, }, 140 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 141 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 142 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 143 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 144 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, NULL, }, 145 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 146 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 147 { NULL, 0, NULL, }, 148 }; 149 150 static const struct pci_class pci_subclass_communications[] = { 151 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, NULL, }, 152 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, NULL, }, 153 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL, }, 154 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, NULL, }, 155 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL, }, 156 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL, }, 157 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL, }, 158 { NULL, 0, NULL, }, 159 }; 160 161 static const struct pci_class pci_subclass_system[] = { 162 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, NULL, }, 163 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, NULL, }, 164 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, NULL, }, 165 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, NULL, }, 166 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 167 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 168 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 169 { NULL, 0, NULL, }, 170 }; 171 172 static const struct pci_class pci_subclass_input[] = { 173 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 174 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 175 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 176 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 177 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, NULL, }, 178 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 179 { NULL, 0, NULL, }, 180 }; 181 182 static const struct pci_class pci_subclass_dock[] = { 183 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 184 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 185 { NULL, 0, NULL, }, 186 }; 187 188 static const struct pci_class pci_subclass_processor[] = { 189 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 190 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 191 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 192 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 193 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 194 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 195 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 196 { NULL, 0, NULL, }, 197 }; 198 199 static const struct pci_class pci_subclass_serialbus[] = { 200 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, NULL, }, 201 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 202 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 203 { "USB", PCI_SUBCLASS_SERIALBUS_USB, NULL, }, 204 /* XXX Fiber Channel/_FIBRECHANNEL */ 205 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 206 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 207 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 208 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, NULL, }, 209 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 210 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 211 { NULL, 0, NULL, }, 212 }; 213 214 static const struct pci_class pci_subclass_wireless[] = { 215 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 216 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 217 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 218 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 219 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 220 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 221 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 222 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 223 { NULL, 0, NULL, }, 224 }; 225 226 static const struct pci_class pci_subclass_i2o[] = { 227 { "standard", PCI_SUBCLASS_I2O_STANDARD, NULL, }, 228 { NULL, 0, NULL, }, 229 }; 230 231 static const struct pci_class pci_subclass_satcom[] = { 232 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 233 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 234 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 235 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 236 { NULL, 0, NULL, }, 237 }; 238 239 static const struct pci_class pci_subclass_crypto[] = { 240 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 241 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 242 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 243 { NULL, 0, NULL, }, 244 }; 245 246 static const struct pci_class pci_subclass_dasp[] = { 247 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 248 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 249 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 250 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 251 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 252 { NULL, 0, NULL, }, 253 }; 254 255 static const struct pci_class pci_class[] = { 256 { "prehistoric", PCI_CLASS_PREHISTORIC, 257 pci_subclass_prehistoric, }, 258 { "mass storage", PCI_CLASS_MASS_STORAGE, 259 pci_subclass_mass_storage, }, 260 { "network", PCI_CLASS_NETWORK, 261 pci_subclass_network, }, 262 { "display", PCI_CLASS_DISPLAY, 263 pci_subclass_display, }, 264 { "multimedia", PCI_CLASS_MULTIMEDIA, 265 pci_subclass_multimedia, }, 266 { "memory", PCI_CLASS_MEMORY, 267 pci_subclass_memory, }, 268 { "bridge", PCI_CLASS_BRIDGE, 269 pci_subclass_bridge, }, 270 { "communications", PCI_CLASS_COMMUNICATIONS, 271 pci_subclass_communications, }, 272 { "system", PCI_CLASS_SYSTEM, 273 pci_subclass_system, }, 274 { "input", PCI_CLASS_INPUT, 275 pci_subclass_input, }, 276 { "dock", PCI_CLASS_DOCK, 277 pci_subclass_dock, }, 278 { "processor", PCI_CLASS_PROCESSOR, 279 pci_subclass_processor, }, 280 { "serial bus", PCI_CLASS_SERIALBUS, 281 pci_subclass_serialbus, }, 282 { "wireless", PCI_CLASS_WIRELESS, 283 pci_subclass_wireless, }, 284 { "I2O", PCI_CLASS_I2O, 285 pci_subclass_i2o, }, 286 { "satellite comm", PCI_CLASS_SATCOM, 287 pci_subclass_satcom, }, 288 { "crypto", PCI_CLASS_CRYPTO, 289 pci_subclass_crypto, }, 290 { "DASP", PCI_CLASS_DASP, 291 pci_subclass_dasp, }, 292 { "undefined", PCI_CLASS_UNDEFINED, 293 NULL, }, 294 { NULL, 0, 295 NULL, }, 296 }; 297 298 #ifdef PCIVERBOSE 299 /* 300 * Descriptions of of known vendors and devices ("products"). 301 */ 302 303 #include <dev/pci/pcidevs_data.h> 304 #endif /* PCIVERBOSE */ 305 306 #ifdef PCIVERBOSE 307 #ifndef _KERNEL 308 #include <string.h> 309 #endif 310 static const char * 311 pci_untokenstring(const uint16_t *token, char *buf, size_t len) 312 { 313 char *cp = buf; 314 315 buf[0] = '\0'; 316 for (; *token != 0; token++) { 317 cp = buf + strlcat(buf, pci_words + *token, len - 2); 318 cp[0] = ' '; 319 cp[1] = '\0'; 320 } 321 *cp = '\0'; 322 return cp != buf ? buf : NULL; 323 } 324 #endif /* PCIVERBOSE */ 325 326 const char * 327 pci_findvendor(pcireg_t id_reg) 328 { 329 #ifdef PCIVERBOSE 330 static char buf[256]; 331 pci_vendor_id_t vendor = PCI_VENDOR(id_reg); 332 size_t n; 333 334 for (n = 0; n < __arraycount(pci_vendors); n++) { 335 if (pci_vendors[n] == vendor) 336 return pci_untokenstring(&pci_vendors[n+1], buf, 337 sizeof(buf)); 338 339 /* Skip Tokens */ 340 n++; 341 while (pci_vendors[n] != 0 && n < __arraycount(pci_vendors)) 342 n++; 343 } 344 #endif 345 return (NULL); 346 } 347 348 const char * 349 pci_findproduct(pcireg_t id_reg) 350 { 351 #ifdef PCIVERBOSE 352 static char buf[256]; 353 pci_vendor_id_t vendor = PCI_VENDOR(id_reg); 354 pci_product_id_t product = PCI_PRODUCT(id_reg); 355 size_t n; 356 357 for (n = 0; n < __arraycount(pci_products); n++) { 358 if (pci_products[n] == vendor && pci_products[n+1] == product) 359 return pci_untokenstring(&pci_products[n+2], buf, 360 sizeof(buf)); 361 362 /* Skip Tokens */ 363 n += 2; 364 while (pci_products[n] != 0 && n < __arraycount(pci_products)) 365 n++; 366 } 367 #endif 368 return (NULL); 369 } 370 371 void 372 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 373 size_t l) 374 { 375 pci_vendor_id_t vendor; 376 pci_product_id_t product; 377 pci_class_t class; 378 pci_subclass_t subclass; 379 pci_interface_t interface; 380 pci_revision_t revision; 381 const char *vendor_namep, *product_namep; 382 const struct pci_class *classp, *subclassp; 383 #ifdef PCIVERBOSE 384 const char *unmatched = "unknown "; 385 #else 386 const char *unmatched = ""; 387 #endif 388 char *ep; 389 390 ep = cp + l; 391 392 vendor = PCI_VENDOR(id_reg); 393 product = PCI_PRODUCT(id_reg); 394 395 class = PCI_CLASS(class_reg); 396 subclass = PCI_SUBCLASS(class_reg); 397 interface = PCI_INTERFACE(class_reg); 398 revision = PCI_REVISION(class_reg); 399 400 vendor_namep = pci_findvendor(id_reg); 401 product_namep = pci_findproduct(id_reg); 402 403 classp = pci_class; 404 while (classp->name != NULL) { 405 if (class == classp->val) 406 break; 407 classp++; 408 } 409 410 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 411 while (subclassp && subclassp->name != NULL) { 412 if (subclass == subclassp->val) 413 break; 414 subclassp++; 415 } 416 417 if (vendor_namep == NULL) 418 cp += snprintf(cp, ep - cp, "%svendor 0x%04x product 0x%04x", 419 unmatched, vendor, product); 420 else if (product_namep != NULL) 421 cp += snprintf(cp, ep - cp, "%s %s", vendor_namep, 422 product_namep); 423 else 424 cp += snprintf(cp, ep - cp, "%s product 0x%04x", 425 vendor_namep, product); 426 if (showclass) { 427 cp += snprintf(cp, ep - cp, " ("); 428 if (classp->name == NULL) 429 cp += snprintf(cp, ep - cp, 430 "class 0x%02x, subclass 0x%02x", class, subclass); 431 else { 432 if (subclassp == NULL || subclassp->name == NULL) 433 cp += snprintf(cp, ep - cp, 434 "%s subclass 0x%02x", 435 classp->name, subclass); 436 else 437 cp += snprintf(cp, ep - cp, "%s %s", 438 subclassp->name, classp->name); 439 } 440 if (interface != 0) 441 cp += snprintf(cp, ep - cp, ", interface 0x%02x", 442 interface); 443 if (revision != 0) 444 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 445 revision); 446 cp += snprintf(cp, ep - cp, ")"); 447 } 448 } 449 450 /* 451 * Print out most of the PCI configuration registers. Typically used 452 * in a device attach routine like this: 453 * 454 * #ifdef MYDEV_DEBUG 455 * printf("%s: ", device_xname(&sc->sc_dev)); 456 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 457 * #endif 458 */ 459 460 #define i2o(i) ((i) * 4) 461 #define o2i(o) ((o) / 4) 462 #define onoff(str, bit) \ 463 printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off"); 464 465 static void 466 pci_conf_print_common( 467 #ifdef _KERNEL 468 pci_chipset_tag_t pc, pcitag_t tag, 469 #endif 470 const pcireg_t *regs) 471 { 472 const char *name; 473 const struct pci_class *classp, *subclassp; 474 pcireg_t rval; 475 476 rval = regs[o2i(PCI_ID_REG)]; 477 name = pci_findvendor(rval); 478 if (name) 479 printf(" Vendor Name: %s (0x%04x)\n", name, 480 PCI_VENDOR(rval)); 481 else 482 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 483 name = pci_findproduct(rval); 484 if (name) 485 printf(" Device Name: %s (0x%04x)\n", name, 486 PCI_PRODUCT(rval)); 487 else 488 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 489 490 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 491 492 printf(" Command register: 0x%04x\n", rval & 0xffff); 493 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 494 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 495 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 496 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 497 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 498 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 499 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 500 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 501 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 502 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 503 onoff("Interrupt disable", PCI_COMMAND_INTERRUPT_DISABLE); 504 505 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 506 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 507 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 508 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 509 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 510 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 511 512 printf(" DEVSEL timing: "); 513 switch (rval & PCI_STATUS_DEVSEL_MASK) { 514 case PCI_STATUS_DEVSEL_FAST: 515 printf("fast"); 516 break; 517 case PCI_STATUS_DEVSEL_MEDIUM: 518 printf("medium"); 519 break; 520 case PCI_STATUS_DEVSEL_SLOW: 521 printf("slow"); 522 break; 523 default: 524 printf("unknown/reserved"); /* XXX */ 525 break; 526 } 527 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 528 529 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 530 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 531 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 532 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 533 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 534 535 rval = regs[o2i(PCI_CLASS_REG)]; 536 for (classp = pci_class; classp->name != NULL; classp++) { 537 if (PCI_CLASS(rval) == classp->val) 538 break; 539 } 540 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 541 while (subclassp && subclassp->name != NULL) { 542 if (PCI_SUBCLASS(rval) == subclassp->val) 543 break; 544 subclassp++; 545 } 546 if (classp->name != NULL) { 547 printf(" Class Name: %s (0x%02x)\n", classp->name, 548 PCI_CLASS(rval)); 549 if (subclassp != NULL && subclassp->name != NULL) 550 printf(" Subclass Name: %s (0x%02x)\n", 551 subclassp->name, PCI_SUBCLASS(rval)); 552 else 553 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 554 } else { 555 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 556 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 557 } 558 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 559 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 560 561 rval = regs[o2i(PCI_BHLC_REG)]; 562 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 563 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 564 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 565 PCI_HDRTYPE(rval)); 566 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 567 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 568 } 569 570 static int 571 pci_conf_print_bar( 572 #ifdef _KERNEL 573 pci_chipset_tag_t pc, pcitag_t tag, 574 #endif 575 const pcireg_t *regs, int reg, const char *name 576 #ifdef _KERNEL 577 , int sizebar 578 #endif 579 ) 580 { 581 int width; 582 pcireg_t rval, rval64h; 583 #ifdef _KERNEL 584 int s; 585 pcireg_t mask, mask64h; 586 #endif 587 588 width = 4; 589 590 /* 591 * Section 6.2.5.1, `Address Maps', tells us that: 592 * 593 * 1) The builtin software should have already mapped the 594 * device in a reasonable way. 595 * 596 * 2) A device which wants 2^n bytes of memory will hardwire 597 * the bottom n bits of the address to 0. As recommended, 598 * we write all 1s and see what we get back. 599 */ 600 601 rval = regs[o2i(reg)]; 602 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 603 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 604 rval64h = regs[o2i(reg + 4)]; 605 width = 8; 606 } else 607 rval64h = 0; 608 609 #ifdef _KERNEL 610 /* XXX don't size unknown memory type? */ 611 if (rval != 0 && sizebar) { 612 /* 613 * The following sequence seems to make some devices 614 * (e.g. host bus bridges, which don't normally 615 * have their space mapped) very unhappy, to 616 * the point of crashing the system. 617 * 618 * Therefore, if the mapping register is zero to 619 * start out with, don't bother trying. 620 */ 621 s = splhigh(); 622 pci_conf_write(pc, tag, reg, 0xffffffff); 623 mask = pci_conf_read(pc, tag, reg); 624 pci_conf_write(pc, tag, reg, rval); 625 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 626 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 627 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 628 mask64h = pci_conf_read(pc, tag, reg + 4); 629 pci_conf_write(pc, tag, reg + 4, rval64h); 630 } else 631 mask64h = 0; 632 splx(s); 633 } else 634 mask = mask64h = 0; 635 #endif /* _KERNEL */ 636 637 printf(" Base address register at 0x%02x", reg); 638 if (name) 639 printf(" (%s)", name); 640 printf("\n "); 641 if (rval == 0) { 642 printf("not implemented(?)\n"); 643 return width; 644 } 645 printf("type: "); 646 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 647 const char *type, *prefetch; 648 649 switch (PCI_MAPREG_MEM_TYPE(rval)) { 650 case PCI_MAPREG_MEM_TYPE_32BIT: 651 type = "32-bit"; 652 break; 653 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 654 type = "32-bit-1M"; 655 break; 656 case PCI_MAPREG_MEM_TYPE_64BIT: 657 type = "64-bit"; 658 break; 659 default: 660 type = "unknown (XXX)"; 661 break; 662 } 663 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 664 prefetch = ""; 665 else 666 prefetch = "non"; 667 printf("%s %sprefetchable memory\n", type, prefetch); 668 switch (PCI_MAPREG_MEM_TYPE(rval)) { 669 case PCI_MAPREG_MEM_TYPE_64BIT: 670 printf(" base: 0x%016llx, ", 671 PCI_MAPREG_MEM64_ADDR( 672 ((((long long) rval64h) << 32) | rval))); 673 #ifdef _KERNEL 674 if (sizebar) 675 printf("size: 0x%016llx", 676 PCI_MAPREG_MEM64_SIZE( 677 ((((long long) mask64h) << 32) | mask))); 678 else 679 #endif /* _KERNEL */ 680 printf("not sized"); 681 printf("\n"); 682 break; 683 case PCI_MAPREG_MEM_TYPE_32BIT: 684 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 685 default: 686 printf(" base: 0x%08x, ", 687 PCI_MAPREG_MEM_ADDR(rval)); 688 #ifdef _KERNEL 689 if (sizebar) 690 printf("size: 0x%08x", 691 PCI_MAPREG_MEM_SIZE(mask)); 692 else 693 #endif /* _KERNEL */ 694 printf("not sized"); 695 printf("\n"); 696 break; 697 } 698 } else { 699 #ifdef _KERNEL 700 if (sizebar) 701 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 702 #endif /* _KERNEL */ 703 printf("i/o\n"); 704 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 705 #ifdef _KERNEL 706 if (sizebar) 707 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 708 else 709 #endif /* _KERNEL */ 710 printf("not sized"); 711 printf("\n"); 712 } 713 714 return width; 715 } 716 717 static void 718 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 719 { 720 int off, needaddr, neednl; 721 722 needaddr = 1; 723 neednl = 0; 724 for (off = first; off < pastlast; off += 4) { 725 if ((off % 16) == 0 || needaddr) { 726 printf(" 0x%02x:", off); 727 needaddr = 0; 728 } 729 printf(" 0x%08x", regs[o2i(off)]); 730 neednl = 1; 731 if ((off % 16) == 12) { 732 printf("\n"); 733 neednl = 0; 734 } 735 } 736 if (neednl) 737 printf("\n"); 738 } 739 740 static void 741 pci_conf_print_type0( 742 #ifdef _KERNEL 743 pci_chipset_tag_t pc, pcitag_t tag, 744 #endif 745 const pcireg_t *regs 746 #ifdef _KERNEL 747 , int sizebars 748 #endif 749 ) 750 { 751 int off, width; 752 pcireg_t rval; 753 754 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 755 #ifdef _KERNEL 756 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 757 #else 758 width = pci_conf_print_bar(regs, off, NULL); 759 #endif 760 } 761 762 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 763 764 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 765 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 766 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 767 768 /* XXX */ 769 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 770 771 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 772 printf(" Capability list pointer: 0x%02x\n", 773 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 774 else 775 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 776 777 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 778 779 rval = regs[o2i(PCI_INTERRUPT_REG)]; 780 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 781 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 782 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 783 switch (PCI_INTERRUPT_PIN(rval)) { 784 case PCI_INTERRUPT_PIN_NONE: 785 printf("(none)"); 786 break; 787 case PCI_INTERRUPT_PIN_A: 788 printf("(pin A)"); 789 break; 790 case PCI_INTERRUPT_PIN_B: 791 printf("(pin B)"); 792 break; 793 case PCI_INTERRUPT_PIN_C: 794 printf("(pin C)"); 795 break; 796 case PCI_INTERRUPT_PIN_D: 797 printf("(pin D)"); 798 break; 799 default: 800 printf("(? ? ?)"); 801 break; 802 } 803 printf("\n"); 804 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 805 } 806 807 static void 808 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 809 { 810 bool check_slot = false; 811 812 printf("\n PCI Express Capabilities Register\n"); 813 printf(" Capability version: %x\n", 814 (unsigned int)((regs[o2i(capoff)] & 0x000f0000) >> 16)); 815 printf(" Device type: "); 816 switch ((regs[o2i(capoff)] & 0x00f00000) >> 20) { 817 case 0x0: 818 printf("PCI Express Endpoint device\n"); 819 break; 820 case 0x1: 821 printf("Legacy PCI Express Endpoint device\n"); 822 break; 823 case 0x4: 824 printf("Root Port of PCI Express Root Complex\n"); 825 check_slot = true; 826 break; 827 case 0x5: 828 printf("Upstream Port of PCI Express Switch\n"); 829 break; 830 case 0x6: 831 printf("Downstream Port of PCI Express Switch\n"); 832 check_slot = true; 833 break; 834 case 0x7: 835 printf("PCI Express to PCI/PCI-X Bridge\n"); 836 break; 837 case 0x8: 838 printf("PCI/PCI-X to PCI Express Bridge\n"); 839 break; 840 default: 841 printf("unknown\n"); 842 break; 843 } 844 if (check_slot && (regs[o2i(capoff)] & 0x01000000) != 0) 845 printf(" Slot implemented\n"); 846 printf(" Interrupt Message Number: %x\n", 847 (unsigned int)((regs[o2i(capoff)] & 0x4e000000) >> 27)); 848 if ((regs[o2i(capoff + 0x18)] & 0x07ff) != 0) { 849 printf(" Slot Control Register:\n"); 850 if ((regs[o2i(capoff + 0x18)] & 0x0001) != 0) 851 printf(" Attention Button Pressed Enabled\n"); 852 if ((regs[o2i(capoff + 0x18)] & 0x0002) != 0) 853 printf(" Power Fault Detected Enabled\n"); 854 if ((regs[o2i(capoff + 0x18)] & 0x0004) != 0) 855 printf(" MRL Sensor Changed Enabled\n"); 856 if ((regs[o2i(capoff + 0x18)] & 0x0008) != 0) 857 printf(" Presense Detected Changed Enabled\n"); 858 if ((regs[o2i(capoff + 0x18)] & 0x0010) != 0) 859 printf(" Command Completed Interrupt Enabled\n"); 860 if ((regs[o2i(capoff + 0x18)] & 0x0020) != 0) 861 printf(" Hot-Plug Interrupt Enabled\n"); 862 printf(" Attention Indictor Control: "); 863 switch ((regs[o2i(capoff + 0x18)] & 0x00a0) >> 6) { 864 case 0x0: 865 printf("reserved\n"); 866 break; 867 case 0x1: 868 printf("on\n"); 869 break; 870 case 0x2: 871 printf("blink\n"); 872 break; 873 case 0x3: 874 printf("off\n"); 875 break; 876 } 877 printf(" Power Indictor Control: "); 878 switch ((regs[o2i(capoff + 0x18)] & 0x0300) >> 8) { 879 case 0x0: 880 printf("reserved\n"); 881 break; 882 case 0x1: 883 printf("on\n"); 884 break; 885 case 0x2: 886 printf("blink\n"); 887 break; 888 case 0x3: 889 printf("off\n"); 890 break; 891 } 892 printf(" Power Controller Control: "); 893 if ((regs[o2i(capoff + 0x18)] & 0x0400) != 0) 894 printf("off\n"); 895 else 896 printf("on\n"); 897 } 898 } 899 900 static void 901 pci_conf_print_caplist( 902 #ifdef _KERNEL 903 pci_chipset_tag_t pc, pcitag_t tag, 904 #endif 905 const pcireg_t *regs, int capoff) 906 { 907 static const char unk[] = "unknown"; 908 static const char *pmrev[8] = { 909 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 910 }; 911 int off; 912 pcireg_t rval; 913 int pcie_off = -1; 914 915 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 916 off != 0; 917 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 918 rval = regs[o2i(off)]; 919 printf(" Capability register at 0x%02x\n", off); 920 921 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 922 switch (PCI_CAPLIST_CAP(rval)) { 923 case PCI_CAP_RESERVED0: 924 printf("reserved"); 925 break; 926 case PCI_CAP_PWRMGMT: 927 printf("Power Management, rev. %s", 928 pmrev[(rval >> 0) & 0x07]); 929 break; 930 case PCI_CAP_AGP: 931 printf("AGP, rev. %d.%d", 932 PCI_CAP_AGP_MAJOR(rval), 933 PCI_CAP_AGP_MINOR(rval)); 934 break; 935 case PCI_CAP_VPD: 936 printf("VPD"); 937 break; 938 case PCI_CAP_SLOTID: 939 printf("SlotID"); 940 break; 941 case PCI_CAP_MSI: 942 printf("MSI"); 943 break; 944 case PCI_CAP_CPCI_HOTSWAP: 945 printf("CompactPCI Hot-swapping"); 946 break; 947 case PCI_CAP_PCIX: 948 printf("PCI-X"); 949 break; 950 case PCI_CAP_LDT: 951 printf("LDT"); 952 break; 953 case PCI_CAP_VENDSPEC: 954 printf("Vendor-specific"); 955 break; 956 case PCI_CAP_DEBUGPORT: 957 printf("Debug Port"); 958 break; 959 case PCI_CAP_CPCI_RSRCCTL: 960 printf("CompactPCI Resource Control"); 961 break; 962 case PCI_CAP_HOTPLUG: 963 printf("Hot-Plug"); 964 break; 965 case PCI_CAP_AGP8: 966 printf("AGP 8x"); 967 break; 968 case PCI_CAP_SECURE: 969 printf("Secure Device"); 970 break; 971 case PCI_CAP_PCIEXPRESS: 972 printf("PCI Express"); 973 pcie_off = off; 974 break; 975 case PCI_CAP_MSIX: 976 printf("MSI-X"); 977 break; 978 default: 979 printf("unknown"); 980 } 981 printf(")\n"); 982 } 983 if (pcie_off != -1) 984 pci_conf_print_pcie_cap(regs, pcie_off); 985 } 986 987 static void 988 pci_conf_print_type1( 989 #ifdef _KERNEL 990 pci_chipset_tag_t pc, pcitag_t tag, 991 #endif 992 const pcireg_t *regs 993 #ifdef _KERNEL 994 , int sizebars 995 #endif 996 ) 997 { 998 int off, width; 999 pcireg_t rval; 1000 1001 /* 1002 * XXX these need to be printed in more detail, need to be 1003 * XXX checked against specs/docs, etc. 1004 * 1005 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 1006 * Bridge chip documentation, and may not be correct with 1007 * respect to various standards. (XXX) 1008 */ 1009 1010 for (off = 0x10; off < 0x18; off += width) { 1011 #ifdef _KERNEL 1012 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 1013 #else 1014 width = pci_conf_print_bar(regs, off, NULL); 1015 #endif 1016 } 1017 1018 printf(" Primary bus number: 0x%02x\n", 1019 (regs[o2i(0x18)] >> 0) & 0xff); 1020 printf(" Secondary bus number: 0x%02x\n", 1021 (regs[o2i(0x18)] >> 8) & 0xff); 1022 printf(" Subordinate bus number: 0x%02x\n", 1023 (regs[o2i(0x18)] >> 16) & 0xff); 1024 printf(" Secondary bus latency timer: 0x%02x\n", 1025 (regs[o2i(0x18)] >> 24) & 0xff); 1026 1027 rval = (regs[o2i(0x1c)] >> 16) & 0xffff; 1028 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 1029 onoff("66 MHz capable", 0x0020); 1030 onoff("User Definable Features (UDF) support", 0x0040); 1031 onoff("Fast back-to-back capable", 0x0080); 1032 onoff("Data parity error detected", 0x0100); 1033 1034 printf(" DEVSEL timing: "); 1035 switch (rval & 0x0600) { 1036 case 0x0000: 1037 printf("fast"); 1038 break; 1039 case 0x0200: 1040 printf("medium"); 1041 break; 1042 case 0x0400: 1043 printf("slow"); 1044 break; 1045 default: 1046 printf("unknown/reserved"); /* XXX */ 1047 break; 1048 } 1049 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 1050 1051 onoff("Signaled Target Abort", 0x0800); 1052 onoff("Received Target Abort", 0x1000); 1053 onoff("Received Master Abort", 0x2000); 1054 onoff("System Error", 0x4000); 1055 onoff("Parity Error", 0x8000); 1056 1057 /* XXX Print more prettily */ 1058 printf(" I/O region:\n"); 1059 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 1060 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 1061 printf(" base upper 16 bits register: 0x%04x\n", 1062 (regs[o2i(0x30)] >> 0) & 0xffff); 1063 printf(" limit upper 16 bits register: 0x%04x\n", 1064 (regs[o2i(0x30)] >> 16) & 0xffff); 1065 1066 /* XXX Print more prettily */ 1067 printf(" Memory region:\n"); 1068 printf(" base register: 0x%04x\n", 1069 (regs[o2i(0x20)] >> 0) & 0xffff); 1070 printf(" limit register: 0x%04x\n", 1071 (regs[o2i(0x20)] >> 16) & 0xffff); 1072 1073 /* XXX Print more prettily */ 1074 printf(" Prefetchable memory region:\n"); 1075 printf(" base register: 0x%04x\n", 1076 (regs[o2i(0x24)] >> 0) & 0xffff); 1077 printf(" limit register: 0x%04x\n", 1078 (regs[o2i(0x24)] >> 16) & 0xffff); 1079 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 1080 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 1081 1082 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1083 printf(" Capability list pointer: 0x%02x\n", 1084 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 1085 else 1086 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 1087 1088 /* XXX */ 1089 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 1090 1091 printf(" Interrupt line: 0x%02x\n", 1092 (regs[o2i(0x3c)] >> 0) & 0xff); 1093 printf(" Interrupt pin: 0x%02x ", 1094 (regs[o2i(0x3c)] >> 8) & 0xff); 1095 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1096 case PCI_INTERRUPT_PIN_NONE: 1097 printf("(none)"); 1098 break; 1099 case PCI_INTERRUPT_PIN_A: 1100 printf("(pin A)"); 1101 break; 1102 case PCI_INTERRUPT_PIN_B: 1103 printf("(pin B)"); 1104 break; 1105 case PCI_INTERRUPT_PIN_C: 1106 printf("(pin C)"); 1107 break; 1108 case PCI_INTERRUPT_PIN_D: 1109 printf("(pin D)"); 1110 break; 1111 default: 1112 printf("(? ? ?)"); 1113 break; 1114 } 1115 printf("\n"); 1116 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1117 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 1118 onoff("Parity error response", 0x0001); 1119 onoff("Secondary SERR forwarding", 0x0002); 1120 onoff("ISA enable", 0x0004); 1121 onoff("VGA enable", 0x0008); 1122 onoff("Master abort reporting", 0x0020); 1123 onoff("Secondary bus reset", 0x0040); 1124 onoff("Fast back-to-back capable", 0x0080); 1125 } 1126 1127 static void 1128 pci_conf_print_type2( 1129 #ifdef _KERNEL 1130 pci_chipset_tag_t pc, pcitag_t tag, 1131 #endif 1132 const pcireg_t *regs 1133 #ifdef _KERNEL 1134 , int sizebars 1135 #endif 1136 ) 1137 { 1138 pcireg_t rval; 1139 1140 /* 1141 * XXX these need to be printed in more detail, need to be 1142 * XXX checked against specs/docs, etc. 1143 * 1144 * This layout was cribbed from the TI PCI1130 PCI-to-CardBus 1145 * controller chip documentation, and may not be correct with 1146 * respect to various standards. (XXX) 1147 */ 1148 1149 #ifdef _KERNEL 1150 pci_conf_print_bar(pc, tag, regs, 0x10, 1151 "CardBus socket/ExCA registers", sizebars); 1152 #else 1153 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 1154 #endif 1155 1156 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1157 printf(" Capability list pointer: 0x%02x\n", 1158 PCI_CAPLIST_PTR(regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)])); 1159 else 1160 printf(" Reserved @ 0x14: 0x%04x\n", 1161 (regs[o2i(0x14)] >> 0) & 0xffff); 1162 rval = (regs[o2i(0x14)] >> 16) & 0xffff; 1163 printf(" Secondary status register: 0x%04x\n", rval); 1164 onoff("66 MHz capable", 0x0020); 1165 onoff("User Definable Features (UDF) support", 0x0040); 1166 onoff("Fast back-to-back capable", 0x0080); 1167 onoff("Data parity error detection", 0x0100); 1168 1169 printf(" DEVSEL timing: "); 1170 switch (rval & 0x0600) { 1171 case 0x0000: 1172 printf("fast"); 1173 break; 1174 case 0x0200: 1175 printf("medium"); 1176 break; 1177 case 0x0400: 1178 printf("slow"); 1179 break; 1180 default: 1181 printf("unknown/reserved"); /* XXX */ 1182 break; 1183 } 1184 printf(" (0x%x)\n", (rval & 0x0600) >> 9); 1185 onoff("PCI target aborts terminate CardBus bus master transactions", 1186 0x0800); 1187 onoff("CardBus target aborts terminate PCI bus master transactions", 1188 0x1000); 1189 onoff("Bus initiator aborts terminate initiator transactions", 1190 0x2000); 1191 onoff("System error", 0x4000); 1192 onoff("Parity error", 0x8000); 1193 1194 printf(" PCI bus number: 0x%02x\n", 1195 (regs[o2i(0x18)] >> 0) & 0xff); 1196 printf(" CardBus bus number: 0x%02x\n", 1197 (regs[o2i(0x18)] >> 8) & 0xff); 1198 printf(" Subordinate bus number: 0x%02x\n", 1199 (regs[o2i(0x18)] >> 16) & 0xff); 1200 printf(" CardBus latency timer: 0x%02x\n", 1201 (regs[o2i(0x18)] >> 24) & 0xff); 1202 1203 /* XXX Print more prettily */ 1204 printf(" CardBus memory region 0:\n"); 1205 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1206 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1207 printf(" CardBus memory region 1:\n"); 1208 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1209 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1210 printf(" CardBus I/O region 0:\n"); 1211 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1212 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1213 printf(" CardBus I/O region 1:\n"); 1214 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1215 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1216 1217 printf(" Interrupt line: 0x%02x\n", 1218 (regs[o2i(0x3c)] >> 0) & 0xff); 1219 printf(" Interrupt pin: 0x%02x ", 1220 (regs[o2i(0x3c)] >> 8) & 0xff); 1221 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1222 case PCI_INTERRUPT_PIN_NONE: 1223 printf("(none)"); 1224 break; 1225 case PCI_INTERRUPT_PIN_A: 1226 printf("(pin A)"); 1227 break; 1228 case PCI_INTERRUPT_PIN_B: 1229 printf("(pin B)"); 1230 break; 1231 case PCI_INTERRUPT_PIN_C: 1232 printf("(pin C)"); 1233 break; 1234 case PCI_INTERRUPT_PIN_D: 1235 printf("(pin D)"); 1236 break; 1237 default: 1238 printf("(? ? ?)"); 1239 break; 1240 } 1241 printf("\n"); 1242 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1243 printf(" Bridge control register: 0x%04x\n", rval); 1244 onoff("Parity error response", 0x0001); 1245 onoff("CardBus SERR forwarding", 0x0002); 1246 onoff("ISA enable", 0x0004); 1247 onoff("VGA enable", 0x0008); 1248 onoff("CardBus master abort reporting", 0x0020); 1249 onoff("CardBus reset", 0x0040); 1250 onoff("Functional interrupts routed by ExCA registers", 0x0080); 1251 onoff("Memory window 0 prefetchable", 0x0100); 1252 onoff("Memory window 1 prefetchable", 0x0200); 1253 onoff("Write posting enable", 0x0400); 1254 1255 rval = regs[o2i(0x40)]; 1256 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1257 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1258 1259 #ifdef _KERNEL 1260 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1261 sizebars); 1262 #else 1263 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 1264 #endif 1265 } 1266 1267 void 1268 pci_conf_print( 1269 #ifdef _KERNEL 1270 pci_chipset_tag_t pc, pcitag_t tag, 1271 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 1272 #else 1273 int pcifd, u_int bus, u_int dev, u_int func 1274 #endif 1275 ) 1276 { 1277 pcireg_t regs[o2i(256)]; 1278 int off, capoff, endoff, hdrtype; 1279 const char *typename; 1280 #ifdef _KERNEL 1281 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1282 int sizebars; 1283 #else 1284 void (*typeprintfn)(const pcireg_t *); 1285 #endif 1286 1287 printf("PCI configuration registers:\n"); 1288 1289 for (off = 0; off < 256; off += 4) { 1290 #ifdef _KERNEL 1291 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1292 #else 1293 if (pcibus_conf_read(pcifd, bus, dev, func, off, 1294 ®s[o2i(off)]) == -1) 1295 regs[o2i(off)] = 0; 1296 #endif 1297 } 1298 1299 #ifdef _KERNEL 1300 sizebars = 1; 1301 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1302 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1303 sizebars = 0; 1304 #endif 1305 1306 /* common header */ 1307 printf(" Common header:\n"); 1308 pci_conf_print_regs(regs, 0, 16); 1309 1310 printf("\n"); 1311 #ifdef _KERNEL 1312 pci_conf_print_common(pc, tag, regs); 1313 #else 1314 pci_conf_print_common(regs); 1315 #endif 1316 printf("\n"); 1317 1318 /* type-dependent header */ 1319 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1320 switch (hdrtype) { /* XXX make a table, eventually */ 1321 case 0: 1322 /* Standard device header */ 1323 typename = "\"normal\" device"; 1324 typeprintfn = &pci_conf_print_type0; 1325 capoff = PCI_CAPLISTPTR_REG; 1326 endoff = 64; 1327 break; 1328 case 1: 1329 /* PCI-PCI bridge header */ 1330 typename = "PCI-PCI bridge"; 1331 typeprintfn = &pci_conf_print_type1; 1332 capoff = PCI_CAPLISTPTR_REG; 1333 endoff = 64; 1334 break; 1335 case 2: 1336 /* PCI-CardBus bridge header */ 1337 typename = "PCI-CardBus bridge"; 1338 typeprintfn = &pci_conf_print_type2; 1339 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 1340 endoff = 72; 1341 break; 1342 default: 1343 typename = NULL; 1344 typeprintfn = 0; 1345 capoff = -1; 1346 endoff = 64; 1347 break; 1348 } 1349 printf(" Type %d ", hdrtype); 1350 if (typename != NULL) 1351 printf("(%s) ", typename); 1352 printf("header:\n"); 1353 pci_conf_print_regs(regs, 16, endoff); 1354 printf("\n"); 1355 if (typeprintfn) { 1356 #ifdef _KERNEL 1357 (*typeprintfn)(pc, tag, regs, sizebars); 1358 #else 1359 (*typeprintfn)(regs); 1360 #endif 1361 } else 1362 printf(" Don't know how to pretty-print type %d header.\n", 1363 hdrtype); 1364 printf("\n"); 1365 1366 /* capability list, if present */ 1367 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1368 && (capoff > 0)) { 1369 #ifdef _KERNEL 1370 pci_conf_print_caplist(pc, tag, regs, capoff); 1371 #else 1372 pci_conf_print_caplist(regs, capoff); 1373 #endif 1374 printf("\n"); 1375 } 1376 1377 /* device-dependent header */ 1378 printf(" Device-dependent header:\n"); 1379 pci_conf_print_regs(regs, endoff, 256); 1380 printf("\n"); 1381 #ifdef _KERNEL 1382 if (printfn) 1383 (*printfn)(pc, tag, regs); 1384 else 1385 printf(" Don't know how to pretty-print device-dependent header.\n"); 1386 printf("\n"); 1387 #endif /* _KERNEL */ 1388 } 1389
Indexes created Tue Sep 23 22:09:46 GMT 2025