pci_subr.c revision 1.82
1 /* $NetBSD: pci_subr.c,v 1.82 2010/05/26 09:42:42 martin Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.82 2010/05/26 09:42:42 martin Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdbool.h> 58 #include <stdio.h> 59 #endif 60 61 #include <dev/pci/pcireg.h> 62 #ifdef _KERNEL 63 #include <dev/pci/pcivar.h> 64 #else 65 const char *pci_null(pcireg_t); 66 #endif 67 68 /* 69 * Descriptions of known PCI classes and subclasses. 70 * 71 * Subclasses are described in the same way as classes, but have a 72 * NULL subclass pointer. 73 */ 74 struct pci_class { 75 const char *name; 76 int val; /* as wide as pci_{,sub}class_t */ 77 const struct pci_class *subclasses; 78 }; 79 80 static const struct pci_class pci_subclass_prehistoric[] = { 81 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 82 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 83 { NULL, 0, NULL, }, 84 }; 85 86 static const struct pci_class pci_subclass_mass_storage[] = { 87 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 88 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 89 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 90 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 91 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 92 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, NULL, }, 93 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, NULL, }, 94 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 95 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 96 { NULL, 0, NULL, }, 97 }; 98 99 static const struct pci_class pci_subclass_network[] = { 100 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 101 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 102 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 103 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 104 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 105 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 106 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 107 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 108 { NULL, 0, NULL, }, 109 }; 110 111 static const struct pci_class pci_subclass_display[] = { 112 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, NULL, }, 113 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 114 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 115 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 116 { NULL, 0, NULL, }, 117 }; 118 119 static const struct pci_class pci_subclass_multimedia[] = { 120 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 121 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 122 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 123 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 124 { NULL, 0, NULL, }, 125 }; 126 127 static const struct pci_class pci_subclass_memory[] = { 128 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 129 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 130 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 131 { NULL, 0, NULL, }, 132 }; 133 134 static const struct pci_class pci_subclass_bridge[] = { 135 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 136 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 137 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 138 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 139 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, NULL, }, 140 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 141 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 142 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 143 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 144 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, NULL, }, 145 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 146 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 147 { NULL, 0, NULL, }, 148 }; 149 150 static const struct pci_class pci_subclass_communications[] = { 151 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, NULL, }, 152 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, NULL, }, 153 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL, }, 154 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, NULL, }, 155 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL, }, 156 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL, }, 157 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL, }, 158 { NULL, 0, NULL, }, 159 }; 160 161 static const struct pci_class pci_subclass_system[] = { 162 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, NULL, }, 163 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, NULL, }, 164 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, NULL, }, 165 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, NULL, }, 166 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 167 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 168 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 169 { NULL, 0, NULL, }, 170 }; 171 172 static const struct pci_class pci_subclass_input[] = { 173 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 174 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 175 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 176 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 177 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, NULL, }, 178 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 179 { NULL, 0, NULL, }, 180 }; 181 182 static const struct pci_class pci_subclass_dock[] = { 183 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 184 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 185 { NULL, 0, NULL, }, 186 }; 187 188 static const struct pci_class pci_subclass_processor[] = { 189 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 190 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 191 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 192 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 193 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 194 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 195 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 196 { NULL, 0, NULL, }, 197 }; 198 199 static const struct pci_class pci_subclass_serialbus[] = { 200 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, NULL, }, 201 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 202 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 203 { "USB", PCI_SUBCLASS_SERIALBUS_USB, NULL, }, 204 /* XXX Fiber Channel/_FIBRECHANNEL */ 205 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 206 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 207 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 208 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, NULL, }, 209 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 210 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 211 { NULL, 0, NULL, }, 212 }; 213 214 static const struct pci_class pci_subclass_wireless[] = { 215 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 216 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 217 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 218 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 219 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 220 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 221 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 222 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 223 { NULL, 0, NULL, }, 224 }; 225 226 static const struct pci_class pci_subclass_i2o[] = { 227 { "standard", PCI_SUBCLASS_I2O_STANDARD, NULL, }, 228 { NULL, 0, NULL, }, 229 }; 230 231 static const struct pci_class pci_subclass_satcom[] = { 232 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 233 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 234 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 235 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 236 { NULL, 0, NULL, }, 237 }; 238 239 static const struct pci_class pci_subclass_crypto[] = { 240 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 241 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 242 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 243 { NULL, 0, NULL, }, 244 }; 245 246 static const struct pci_class pci_subclass_dasp[] = { 247 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 248 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 249 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 250 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 251 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 252 { NULL, 0, NULL, }, 253 }; 254 255 static const struct pci_class pci_class[] = { 256 { "prehistoric", PCI_CLASS_PREHISTORIC, 257 pci_subclass_prehistoric, }, 258 { "mass storage", PCI_CLASS_MASS_STORAGE, 259 pci_subclass_mass_storage, }, 260 { "network", PCI_CLASS_NETWORK, 261 pci_subclass_network, }, 262 { "display", PCI_CLASS_DISPLAY, 263 pci_subclass_display, }, 264 { "multimedia", PCI_CLASS_MULTIMEDIA, 265 pci_subclass_multimedia, }, 266 { "memory", PCI_CLASS_MEMORY, 267 pci_subclass_memory, }, 268 { "bridge", PCI_CLASS_BRIDGE, 269 pci_subclass_bridge, }, 270 { "communications", PCI_CLASS_COMMUNICATIONS, 271 pci_subclass_communications, }, 272 { "system", PCI_CLASS_SYSTEM, 273 pci_subclass_system, }, 274 { "input", PCI_CLASS_INPUT, 275 pci_subclass_input, }, 276 { "dock", PCI_CLASS_DOCK, 277 pci_subclass_dock, }, 278 { "processor", PCI_CLASS_PROCESSOR, 279 pci_subclass_processor, }, 280 { "serial bus", PCI_CLASS_SERIALBUS, 281 pci_subclass_serialbus, }, 282 { "wireless", PCI_CLASS_WIRELESS, 283 pci_subclass_wireless, }, 284 { "I2O", PCI_CLASS_I2O, 285 pci_subclass_i2o, }, 286 { "satellite comm", PCI_CLASS_SATCOM, 287 pci_subclass_satcom, }, 288 { "crypto", PCI_CLASS_CRYPTO, 289 pci_subclass_crypto, }, 290 { "DASP", PCI_CLASS_DASP, 291 pci_subclass_dasp, }, 292 { "undefined", PCI_CLASS_UNDEFINED, 293 NULL, }, 294 { NULL, 0, 295 NULL, }, 296 }; 297 298 #if defined(_KERNEL) 299 /* 300 * In kernel, these routines are provided and linked via the 301 * pciverbose module. 302 */ 303 const char *(*pci_findvendor)(pcireg_t id_reg) = pci_null; 304 const char *(*pci_findproduct)(pcireg_t id_reg) = pci_null; 305 const char *pci_unmatched = ""; 306 #else 307 /* 308 * For userland we just set the vectors here. 309 */ 310 const char *(*pci_findvendor)(pcireg_t id_reg) = pci_findvendor_real; 311 const char *(*pci_findproduct)(pcireg_t id_reg) = pci_findproduct_real; 312 const char *pci_unmatched = "unmatched "; 313 #endif 314 315 const char * 316 pci_null(pcireg_t id_reg) 317 { 318 return (NULL); 319 } 320 321 #if defined(_KERNEL) 322 /* 323 * Routine to load/unload the pciverbose kernel module as needed 324 */ 325 void pci_verbose_ctl(bool load) 326 { 327 static int loaded = 0; 328 329 if (load) { 330 if (loaded++ == 0) 331 if (module_load("pciverbose", MODCTL_LOAD_FORCE, NULL, 332 MODULE_CLASS_MISC) !=0 ) 333 loaded = 0; 334 return; 335 } 336 if (loaded == 0) 337 return; 338 if (--loaded == 0) 339 module_unload("pciverbose"); 340 } 341 #endif 342 343 void 344 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 345 size_t l) 346 { 347 pci_vendor_id_t vendor; 348 pci_product_id_t product; 349 pci_class_t class; 350 pci_subclass_t subclass; 351 pci_interface_t interface; 352 pci_revision_t revision; 353 const char *unmatched = pci_unmatched; 354 const char *vendor_namep, *product_namep; 355 const struct pci_class *classp, *subclassp; 356 char *ep; 357 358 ep = cp + l; 359 360 vendor = PCI_VENDOR(id_reg); 361 product = PCI_PRODUCT(id_reg); 362 363 class = PCI_CLASS(class_reg); 364 subclass = PCI_SUBCLASS(class_reg); 365 interface = PCI_INTERFACE(class_reg); 366 revision = PCI_REVISION(class_reg); 367 368 vendor_namep = pci_findvendor(id_reg); 369 product_namep = pci_findproduct(id_reg); 370 371 classp = pci_class; 372 while (classp->name != NULL) { 373 if (class == classp->val) 374 break; 375 classp++; 376 } 377 378 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 379 while (subclassp && subclassp->name != NULL) { 380 if (subclass == subclassp->val) 381 break; 382 subclassp++; 383 } 384 385 if (vendor_namep == NULL) 386 cp += snprintf(cp, ep - cp, "%svendor 0x%04x product 0x%04x", 387 unmatched, vendor, product); 388 else if (product_namep != NULL) 389 cp += snprintf(cp, ep - cp, "%s %s", vendor_namep, 390 product_namep); 391 else 392 cp += snprintf(cp, ep - cp, "%s product 0x%04x", 393 vendor_namep, product); 394 if (showclass) { 395 cp += snprintf(cp, ep - cp, " ("); 396 if (classp->name == NULL) 397 cp += snprintf(cp, ep - cp, 398 "class 0x%02x, subclass 0x%02x", class, subclass); 399 else { 400 if (subclassp == NULL || subclassp->name == NULL) 401 cp += snprintf(cp, ep - cp, 402 "%s, subclass 0x%02x", 403 classp->name, subclass); 404 else 405 cp += snprintf(cp, ep - cp, "%s %s", 406 subclassp->name, classp->name); 407 } 408 if (interface != 0) 409 cp += snprintf(cp, ep - cp, ", interface 0x%02x", 410 interface); 411 if (revision != 0) 412 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 413 revision); 414 cp += snprintf(cp, ep - cp, ")"); 415 } 416 } 417 418 /* 419 * Print out most of the PCI configuration registers. Typically used 420 * in a device attach routine like this: 421 * 422 * #ifdef MYDEV_DEBUG 423 * printf("%s: ", device_xname(&sc->sc_dev)); 424 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 425 * #endif 426 */ 427 428 #define i2o(i) ((i) * 4) 429 #define o2i(o) ((o) / 4) 430 #define onoff(str, bit) \ 431 printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off"); 432 433 static void 434 pci_conf_print_common( 435 #ifdef _KERNEL 436 pci_chipset_tag_t pc, pcitag_t tag, 437 #endif 438 const pcireg_t *regs) 439 { 440 const char *name; 441 const struct pci_class *classp, *subclassp; 442 pcireg_t rval; 443 444 rval = regs[o2i(PCI_ID_REG)]; 445 name = pci_findvendor(rval); 446 if (name) 447 printf(" Vendor Name: %s (0x%04x)\n", name, 448 PCI_VENDOR(rval)); 449 else 450 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 451 name = pci_findproduct(rval); 452 if (name) 453 printf(" Device Name: %s (0x%04x)\n", name, 454 PCI_PRODUCT(rval)); 455 else 456 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 457 458 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 459 460 printf(" Command register: 0x%04x\n", rval & 0xffff); 461 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 462 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 463 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 464 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 465 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 466 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 467 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 468 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 469 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 470 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 471 onoff("Interrupt disable", PCI_COMMAND_INTERRUPT_DISABLE); 472 473 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 474 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 475 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 476 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 477 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 478 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 479 480 printf(" DEVSEL timing: "); 481 switch (rval & PCI_STATUS_DEVSEL_MASK) { 482 case PCI_STATUS_DEVSEL_FAST: 483 printf("fast"); 484 break; 485 case PCI_STATUS_DEVSEL_MEDIUM: 486 printf("medium"); 487 break; 488 case PCI_STATUS_DEVSEL_SLOW: 489 printf("slow"); 490 break; 491 default: 492 printf("unknown/reserved"); /* XXX */ 493 break; 494 } 495 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 496 497 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 498 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 499 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 500 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 501 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 502 503 rval = regs[o2i(PCI_CLASS_REG)]; 504 for (classp = pci_class; classp->name != NULL; classp++) { 505 if (PCI_CLASS(rval) == classp->val) 506 break; 507 } 508 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 509 while (subclassp && subclassp->name != NULL) { 510 if (PCI_SUBCLASS(rval) == subclassp->val) 511 break; 512 subclassp++; 513 } 514 if (classp->name != NULL) { 515 printf(" Class Name: %s (0x%02x)\n", classp->name, 516 PCI_CLASS(rval)); 517 if (subclassp != NULL && subclassp->name != NULL) 518 printf(" Subclass Name: %s (0x%02x)\n", 519 subclassp->name, PCI_SUBCLASS(rval)); 520 else 521 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 522 } else { 523 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 524 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 525 } 526 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 527 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 528 529 rval = regs[o2i(PCI_BHLC_REG)]; 530 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 531 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 532 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 533 PCI_HDRTYPE(rval)); 534 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 535 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 536 } 537 538 static int 539 pci_conf_print_bar( 540 #ifdef _KERNEL 541 pci_chipset_tag_t pc, pcitag_t tag, 542 #endif 543 const pcireg_t *regs, int reg, const char *name 544 #ifdef _KERNEL 545 , int sizebar 546 #endif 547 ) 548 { 549 int width; 550 pcireg_t rval, rval64h; 551 #ifdef _KERNEL 552 int s; 553 pcireg_t mask, mask64h; 554 #endif 555 556 width = 4; 557 558 /* 559 * Section 6.2.5.1, `Address Maps', tells us that: 560 * 561 * 1) The builtin software should have already mapped the 562 * device in a reasonable way. 563 * 564 * 2) A device which wants 2^n bytes of memory will hardwire 565 * the bottom n bits of the address to 0. As recommended, 566 * we write all 1s and see what we get back. 567 */ 568 569 rval = regs[o2i(reg)]; 570 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 571 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 572 rval64h = regs[o2i(reg + 4)]; 573 width = 8; 574 } else 575 rval64h = 0; 576 577 #ifdef _KERNEL 578 /* XXX don't size unknown memory type? */ 579 if (rval != 0 && sizebar) { 580 /* 581 * The following sequence seems to make some devices 582 * (e.g. host bus bridges, which don't normally 583 * have their space mapped) very unhappy, to 584 * the point of crashing the system. 585 * 586 * Therefore, if the mapping register is zero to 587 * start out with, don't bother trying. 588 */ 589 s = splhigh(); 590 pci_conf_write(pc, tag, reg, 0xffffffff); 591 mask = pci_conf_read(pc, tag, reg); 592 pci_conf_write(pc, tag, reg, rval); 593 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 594 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 595 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 596 mask64h = pci_conf_read(pc, tag, reg + 4); 597 pci_conf_write(pc, tag, reg + 4, rval64h); 598 } else 599 mask64h = 0; 600 splx(s); 601 } else 602 mask = mask64h = 0; 603 #endif /* _KERNEL */ 604 605 printf(" Base address register at 0x%02x", reg); 606 if (name) 607 printf(" (%s)", name); 608 printf("\n "); 609 if (rval == 0) { 610 printf("not implemented(?)\n"); 611 return width; 612 } 613 printf("type: "); 614 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 615 const char *type, *prefetch; 616 617 switch (PCI_MAPREG_MEM_TYPE(rval)) { 618 case PCI_MAPREG_MEM_TYPE_32BIT: 619 type = "32-bit"; 620 break; 621 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 622 type = "32-bit-1M"; 623 break; 624 case PCI_MAPREG_MEM_TYPE_64BIT: 625 type = "64-bit"; 626 break; 627 default: 628 type = "unknown (XXX)"; 629 break; 630 } 631 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 632 prefetch = ""; 633 else 634 prefetch = "non"; 635 printf("%s %sprefetchable memory\n", type, prefetch); 636 switch (PCI_MAPREG_MEM_TYPE(rval)) { 637 case PCI_MAPREG_MEM_TYPE_64BIT: 638 printf(" base: 0x%016llx, ", 639 PCI_MAPREG_MEM64_ADDR( 640 ((((long long) rval64h) << 32) | rval))); 641 #ifdef _KERNEL 642 if (sizebar) 643 printf("size: 0x%016llx", 644 PCI_MAPREG_MEM64_SIZE( 645 ((((long long) mask64h) << 32) | mask))); 646 else 647 #endif /* _KERNEL */ 648 printf("not sized"); 649 printf("\n"); 650 break; 651 case PCI_MAPREG_MEM_TYPE_32BIT: 652 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 653 default: 654 printf(" base: 0x%08x, ", 655 PCI_MAPREG_MEM_ADDR(rval)); 656 #ifdef _KERNEL 657 if (sizebar) 658 printf("size: 0x%08x", 659 PCI_MAPREG_MEM_SIZE(mask)); 660 else 661 #endif /* _KERNEL */ 662 printf("not sized"); 663 printf("\n"); 664 break; 665 } 666 } else { 667 #ifdef _KERNEL 668 if (sizebar) 669 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 670 #endif /* _KERNEL */ 671 printf("i/o\n"); 672 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 673 #ifdef _KERNEL 674 if (sizebar) 675 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 676 else 677 #endif /* _KERNEL */ 678 printf("not sized"); 679 printf("\n"); 680 } 681 682 return width; 683 } 684 685 static void 686 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 687 { 688 int off, needaddr, neednl; 689 690 needaddr = 1; 691 neednl = 0; 692 for (off = first; off < pastlast; off += 4) { 693 if ((off % 16) == 0 || needaddr) { 694 printf(" 0x%02x:", off); 695 needaddr = 0; 696 } 697 printf(" 0x%08x", regs[o2i(off)]); 698 neednl = 1; 699 if ((off % 16) == 12) { 700 printf("\n"); 701 neednl = 0; 702 } 703 } 704 if (neednl) 705 printf("\n"); 706 } 707 708 static void 709 pci_conf_print_type0( 710 #ifdef _KERNEL 711 pci_chipset_tag_t pc, pcitag_t tag, 712 #endif 713 const pcireg_t *regs 714 #ifdef _KERNEL 715 , int sizebars 716 #endif 717 ) 718 { 719 int off, width; 720 pcireg_t rval; 721 722 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 723 #ifdef _KERNEL 724 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 725 #else 726 width = pci_conf_print_bar(regs, off, NULL); 727 #endif 728 } 729 730 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 731 732 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 733 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 734 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 735 736 /* XXX */ 737 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 738 739 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 740 printf(" Capability list pointer: 0x%02x\n", 741 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 742 else 743 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 744 745 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 746 747 rval = regs[o2i(PCI_INTERRUPT_REG)]; 748 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 749 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 750 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 751 switch (PCI_INTERRUPT_PIN(rval)) { 752 case PCI_INTERRUPT_PIN_NONE: 753 printf("(none)"); 754 break; 755 case PCI_INTERRUPT_PIN_A: 756 printf("(pin A)"); 757 break; 758 case PCI_INTERRUPT_PIN_B: 759 printf("(pin B)"); 760 break; 761 case PCI_INTERRUPT_PIN_C: 762 printf("(pin C)"); 763 break; 764 case PCI_INTERRUPT_PIN_D: 765 printf("(pin D)"); 766 break; 767 default: 768 printf("(? ? ?)"); 769 break; 770 } 771 printf("\n"); 772 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 773 } 774 775 static void 776 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 777 { 778 bool check_slot = false; 779 780 printf("\n PCI Express Capabilities Register\n"); 781 printf(" Capability version: %x\n", 782 (unsigned int)((regs[o2i(capoff)] & 0x000f0000) >> 16)); 783 printf(" Device type: "); 784 switch ((regs[o2i(capoff)] & 0x00f00000) >> 20) { 785 case 0x0: 786 printf("PCI Express Endpoint device\n"); 787 break; 788 case 0x1: 789 printf("Legacy PCI Express Endpoint device\n"); 790 break; 791 case 0x4: 792 printf("Root Port of PCI Express Root Complex\n"); 793 check_slot = true; 794 break; 795 case 0x5: 796 printf("Upstream Port of PCI Express Switch\n"); 797 break; 798 case 0x6: 799 printf("Downstream Port of PCI Express Switch\n"); 800 check_slot = true; 801 break; 802 case 0x7: 803 printf("PCI Express to PCI/PCI-X Bridge\n"); 804 break; 805 case 0x8: 806 printf("PCI/PCI-X to PCI Express Bridge\n"); 807 break; 808 default: 809 printf("unknown\n"); 810 break; 811 } 812 if (check_slot && (regs[o2i(capoff)] & 0x01000000) != 0) 813 printf(" Slot implemented\n"); 814 printf(" Interrupt Message Number: %x\n", 815 (unsigned int)((regs[o2i(capoff)] & 0x4e000000) >> 27)); 816 if ((regs[o2i(capoff + 0x18)] & 0x07ff) != 0) { 817 printf(" Slot Control Register:\n"); 818 if ((regs[o2i(capoff + 0x18)] & 0x0001) != 0) 819 printf(" Attention Button Pressed Enabled\n"); 820 if ((regs[o2i(capoff + 0x18)] & 0x0002) != 0) 821 printf(" Power Fault Detected Enabled\n"); 822 if ((regs[o2i(capoff + 0x18)] & 0x0004) != 0) 823 printf(" MRL Sensor Changed Enabled\n"); 824 if ((regs[o2i(capoff + 0x18)] & 0x0008) != 0) 825 printf(" Presense Detected Changed Enabled\n"); 826 if ((regs[o2i(capoff + 0x18)] & 0x0010) != 0) 827 printf(" Command Completed Interrupt Enabled\n"); 828 if ((regs[o2i(capoff + 0x18)] & 0x0020) != 0) 829 printf(" Hot-Plug Interrupt Enabled\n"); 830 printf(" Attention Indicator Control: "); 831 switch ((regs[o2i(capoff + 0x18)] & 0x00c0) >> 6) { 832 case 0x0: 833 printf("reserved\n"); 834 break; 835 case 0x1: 836 printf("on\n"); 837 break; 838 case 0x2: 839 printf("blink\n"); 840 break; 841 case 0x3: 842 printf("off\n"); 843 break; 844 } 845 printf(" Power Indicator Control: "); 846 switch ((regs[o2i(capoff + 0x18)] & 0x0300) >> 8) { 847 case 0x0: 848 printf("reserved\n"); 849 break; 850 case 0x1: 851 printf("on\n"); 852 break; 853 case 0x2: 854 printf("blink\n"); 855 break; 856 case 0x3: 857 printf("off\n"); 858 break; 859 } 860 printf(" Power Controller Control: "); 861 if ((regs[o2i(capoff + 0x18)] & 0x0400) != 0) 862 printf("off\n"); 863 else 864 printf("on\n"); 865 } 866 } 867 868 static const char * 869 pci_conf_print_pcipm_cap_aux(uint16_t caps) 870 { 871 switch ((caps >> 6) & 7) { 872 case 0: return "self-powered"; 873 case 1: return "55 mA"; 874 case 2: return "100 mA"; 875 case 3: return "160 mA"; 876 case 4: return "220 mA"; 877 case 5: return "270 mA"; 878 case 6: return "320 mA"; 879 case 7: 880 default: return "375 mA"; 881 } 882 } 883 884 static const char * 885 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 886 { 887 static const char unk[] = "unknown"; 888 static const char *pmrev[8] = { 889 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 890 }; 891 if (val > 7) 892 return unk; 893 return pmrev[val]; 894 } 895 896 static void 897 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 898 { 899 uint16_t caps, pmcsr; 900 901 caps = regs[o2i(capoff)] >> 16; 902 pmcsr = regs[o2i(capoff + 0x04)] & 0xffff; 903 904 printf("\n PCI Power Management Capabilities Register\n"); 905 906 printf(" Capabilities register: 0x%04x\n", caps); 907 printf(" Version: %s\n", 908 pci_conf_print_pcipm_cap_pmrev(caps & 0x3)); 909 printf(" PME# clock: %s\n", caps & 0x4 ? "on" : "off"); 910 printf(" Device specific initialization: %s\n", 911 caps & 0x20 ? "on" : "off"); 912 printf(" 3.3V auxiliary current: %s\n", 913 pci_conf_print_pcipm_cap_aux(caps)); 914 printf(" D1 power management state support: %s\n", 915 (caps >> 9) & 1 ? "on" : "off"); 916 printf(" D2 power management state support: %s\n", 917 (caps >> 10) & 1 ? "on" : "off"); 918 printf(" PME# support: 0x%02x\n", caps >> 11); 919 920 printf(" Control/status register: 0x%04x\n", pmcsr); 921 printf(" Power state: D%d\n", pmcsr & 3); 922 printf(" PCI Express reserved: %s\n", 923 (pmcsr >> 2) & 1 ? "on" : "off"); 924 printf(" No soft reset: %s\n", (pmcsr >> 3) & 1 ? "on" : "off"); 925 printf(" PME# assertion %sabled\n", 926 (pmcsr >> 8) & 1 ? "en" : "dis"); 927 printf(" PME# status: %s\n", (pmcsr >> 15) ? "on" : "off"); 928 } 929 930 static void 931 pci_conf_print_caplist( 932 #ifdef _KERNEL 933 pci_chipset_tag_t pc, pcitag_t tag, 934 #endif 935 const pcireg_t *regs, int capoff) 936 { 937 int off; 938 pcireg_t rval; 939 int pcie_off = -1, pcipm_off = -1; 940 941 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 942 off != 0; 943 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 944 rval = regs[o2i(off)]; 945 printf(" Capability register at 0x%02x\n", off); 946 947 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 948 switch (PCI_CAPLIST_CAP(rval)) { 949 case PCI_CAP_RESERVED0: 950 printf("reserved"); 951 break; 952 case PCI_CAP_PWRMGMT: 953 printf("Power Management, rev. %s", 954 pci_conf_print_pcipm_cap_pmrev((rval >> 0) & 0x07)); 955 pcipm_off = off; 956 break; 957 case PCI_CAP_AGP: 958 printf("AGP, rev. %d.%d", 959 PCI_CAP_AGP_MAJOR(rval), 960 PCI_CAP_AGP_MINOR(rval)); 961 break; 962 case PCI_CAP_VPD: 963 printf("VPD"); 964 break; 965 case PCI_CAP_SLOTID: 966 printf("SlotID"); 967 break; 968 case PCI_CAP_MSI: 969 printf("MSI"); 970 break; 971 case PCI_CAP_CPCI_HOTSWAP: 972 printf("CompactPCI Hot-swapping"); 973 break; 974 case PCI_CAP_PCIX: 975 printf("PCI-X"); 976 break; 977 case PCI_CAP_LDT: 978 printf("LDT"); 979 break; 980 case PCI_CAP_VENDSPEC: 981 printf("Vendor-specific"); 982 break; 983 case PCI_CAP_DEBUGPORT: 984 printf("Debug Port"); 985 break; 986 case PCI_CAP_CPCI_RSRCCTL: 987 printf("CompactPCI Resource Control"); 988 break; 989 case PCI_CAP_HOTPLUG: 990 printf("Hot-Plug"); 991 break; 992 case PCI_CAP_AGP8: 993 printf("AGP 8x"); 994 break; 995 case PCI_CAP_SECURE: 996 printf("Secure Device"); 997 break; 998 case PCI_CAP_PCIEXPRESS: 999 printf("PCI Express"); 1000 pcie_off = off; 1001 break; 1002 case PCI_CAP_MSIX: 1003 printf("MSI-X"); 1004 break; 1005 default: 1006 printf("unknown"); 1007 } 1008 printf(")\n"); 1009 } 1010 if (pcipm_off != -1) 1011 pci_conf_print_pcipm_cap(regs, pcipm_off); 1012 if (pcie_off != -1) 1013 pci_conf_print_pcie_cap(regs, pcie_off); 1014 } 1015 1016 /* Print the Secondary Status Register. */ 1017 static void 1018 pci_conf_print_ssr(pcireg_t rval) 1019 { 1020 pcireg_t devsel; 1021 1022 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 1023 onoff("66 MHz capable", __BIT(5)); 1024 onoff("User Definable Features (UDF) support", __BIT(6)); 1025 onoff("Fast back-to-back capable", __BIT(7)); 1026 onoff("Data parity error detected", __BIT(8)); 1027 1028 printf(" DEVSEL timing: "); 1029 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 1030 switch (devsel) { 1031 case 0: 1032 printf("fast"); 1033 break; 1034 case 1: 1035 printf("medium"); 1036 break; 1037 case 2: 1038 printf("slow"); 1039 break; 1040 default: 1041 printf("unknown/reserved"); /* XXX */ 1042 break; 1043 } 1044 printf(" (0x%x)\n", devsel); 1045 1046 onoff("Signalled target abort", __BIT(11)); 1047 onoff("Received target abort", __BIT(12)); 1048 onoff("Received master abort", __BIT(13)); 1049 onoff("Received system error", __BIT(14)); 1050 onoff("Detected parity error", __BIT(15)); 1051 } 1052 1053 static void 1054 pci_conf_print_type1( 1055 #ifdef _KERNEL 1056 pci_chipset_tag_t pc, pcitag_t tag, 1057 #endif 1058 const pcireg_t *regs 1059 #ifdef _KERNEL 1060 , int sizebars 1061 #endif 1062 ) 1063 { 1064 int off, width; 1065 pcireg_t rval; 1066 1067 /* 1068 * XXX these need to be printed in more detail, need to be 1069 * XXX checked against specs/docs, etc. 1070 * 1071 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 1072 * Bridge chip documentation, and may not be correct with 1073 * respect to various standards. (XXX) 1074 */ 1075 1076 for (off = 0x10; off < 0x18; off += width) { 1077 #ifdef _KERNEL 1078 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 1079 #else 1080 width = pci_conf_print_bar(regs, off, NULL); 1081 #endif 1082 } 1083 1084 printf(" Primary bus number: 0x%02x\n", 1085 (regs[o2i(0x18)] >> 0) & 0xff); 1086 printf(" Secondary bus number: 0x%02x\n", 1087 (regs[o2i(0x18)] >> 8) & 0xff); 1088 printf(" Subordinate bus number: 0x%02x\n", 1089 (regs[o2i(0x18)] >> 16) & 0xff); 1090 printf(" Secondary bus latency timer: 0x%02x\n", 1091 (regs[o2i(0x18)] >> 24) & 0xff); 1092 1093 pci_conf_print_ssr(__SHIFTOUT(regs[o2i(0x1c)], __BITS(31, 16))); 1094 1095 /* XXX Print more prettily */ 1096 printf(" I/O region:\n"); 1097 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 1098 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 1099 printf(" base upper 16 bits register: 0x%04x\n", 1100 (regs[o2i(0x30)] >> 0) & 0xffff); 1101 printf(" limit upper 16 bits register: 0x%04x\n", 1102 (regs[o2i(0x30)] >> 16) & 0xffff); 1103 1104 /* XXX Print more prettily */ 1105 printf(" Memory region:\n"); 1106 printf(" base register: 0x%04x\n", 1107 (regs[o2i(0x20)] >> 0) & 0xffff); 1108 printf(" limit register: 0x%04x\n", 1109 (regs[o2i(0x20)] >> 16) & 0xffff); 1110 1111 /* XXX Print more prettily */ 1112 printf(" Prefetchable memory region:\n"); 1113 printf(" base register: 0x%04x\n", 1114 (regs[o2i(0x24)] >> 0) & 0xffff); 1115 printf(" limit register: 0x%04x\n", 1116 (regs[o2i(0x24)] >> 16) & 0xffff); 1117 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 1118 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 1119 1120 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1121 printf(" Capability list pointer: 0x%02x\n", 1122 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 1123 else 1124 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 1125 1126 /* XXX */ 1127 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 1128 1129 printf(" Interrupt line: 0x%02x\n", 1130 (regs[o2i(0x3c)] >> 0) & 0xff); 1131 printf(" Interrupt pin: 0x%02x ", 1132 (regs[o2i(0x3c)] >> 8) & 0xff); 1133 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1134 case PCI_INTERRUPT_PIN_NONE: 1135 printf("(none)"); 1136 break; 1137 case PCI_INTERRUPT_PIN_A: 1138 printf("(pin A)"); 1139 break; 1140 case PCI_INTERRUPT_PIN_B: 1141 printf("(pin B)"); 1142 break; 1143 case PCI_INTERRUPT_PIN_C: 1144 printf("(pin C)"); 1145 break; 1146 case PCI_INTERRUPT_PIN_D: 1147 printf("(pin D)"); 1148 break; 1149 default: 1150 printf("(? ? ?)"); 1151 break; 1152 } 1153 printf("\n"); 1154 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1155 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 1156 onoff("Parity error response", 0x0001); 1157 onoff("Secondary SERR forwarding", 0x0002); 1158 onoff("ISA enable", 0x0004); 1159 onoff("VGA enable", 0x0008); 1160 onoff("Master abort reporting", 0x0020); 1161 onoff("Secondary bus reset", 0x0040); 1162 onoff("Fast back-to-back capable", 0x0080); 1163 } 1164 1165 static void 1166 pci_conf_print_type2( 1167 #ifdef _KERNEL 1168 pci_chipset_tag_t pc, pcitag_t tag, 1169 #endif 1170 const pcireg_t *regs 1171 #ifdef _KERNEL 1172 , int sizebars 1173 #endif 1174 ) 1175 { 1176 pcireg_t rval; 1177 1178 /* 1179 * XXX these need to be printed in more detail, need to be 1180 * XXX checked against specs/docs, etc. 1181 * 1182 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 1183 * controller chip documentation, and may not be correct with 1184 * respect to various standards. (XXX) 1185 */ 1186 1187 #ifdef _KERNEL 1188 pci_conf_print_bar(pc, tag, regs, 0x10, 1189 "CardBus socket/ExCA registers", sizebars); 1190 #else 1191 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 1192 #endif 1193 1194 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1195 printf(" Capability list pointer: 0x%02x\n", 1196 PCI_CAPLIST_PTR(regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)])); 1197 else 1198 printf(" Reserved @ 0x14: 0x%04" PRIxMAX "\n", 1199 __SHIFTOUT(regs[o2i(0x14)], __BITS(15, 0))); 1200 pci_conf_print_ssr(__SHIFTOUT(regs[o2i(0x14)], __BITS(31, 16))); 1201 1202 printf(" PCI bus number: 0x%02x\n", 1203 (regs[o2i(0x18)] >> 0) & 0xff); 1204 printf(" CardBus bus number: 0x%02x\n", 1205 (regs[o2i(0x18)] >> 8) & 0xff); 1206 printf(" Subordinate bus number: 0x%02x\n", 1207 (regs[o2i(0x18)] >> 16) & 0xff); 1208 printf(" CardBus latency timer: 0x%02x\n", 1209 (regs[o2i(0x18)] >> 24) & 0xff); 1210 1211 /* XXX Print more prettily */ 1212 printf(" CardBus memory region 0:\n"); 1213 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1214 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1215 printf(" CardBus memory region 1:\n"); 1216 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1217 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1218 printf(" CardBus I/O region 0:\n"); 1219 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1220 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1221 printf(" CardBus I/O region 1:\n"); 1222 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1223 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1224 1225 printf(" Interrupt line: 0x%02x\n", 1226 (regs[o2i(0x3c)] >> 0) & 0xff); 1227 printf(" Interrupt pin: 0x%02x ", 1228 (regs[o2i(0x3c)] >> 8) & 0xff); 1229 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1230 case PCI_INTERRUPT_PIN_NONE: 1231 printf("(none)"); 1232 break; 1233 case PCI_INTERRUPT_PIN_A: 1234 printf("(pin A)"); 1235 break; 1236 case PCI_INTERRUPT_PIN_B: 1237 printf("(pin B)"); 1238 break; 1239 case PCI_INTERRUPT_PIN_C: 1240 printf("(pin C)"); 1241 break; 1242 case PCI_INTERRUPT_PIN_D: 1243 printf("(pin D)"); 1244 break; 1245 default: 1246 printf("(? ? ?)"); 1247 break; 1248 } 1249 printf("\n"); 1250 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1251 printf(" Bridge control register: 0x%04x\n", rval); 1252 onoff("Parity error response", __BIT(0)); 1253 onoff("SERR# enable", __BIT(1)); 1254 onoff("ISA enable", __BIT(2)); 1255 onoff("VGA enable", __BIT(3)); 1256 onoff("Master abort mode", __BIT(5)); 1257 onoff("Secondary (CardBus) bus reset", __BIT(6)); 1258 onoff("Functional interrupts routed by ExCA registers", __BIT(7)); 1259 onoff("Memory window 0 prefetchable", __BIT(8)); 1260 onoff("Memory window 1 prefetchable", __BIT(9)); 1261 onoff("Write posting enable", __BIT(10)); 1262 1263 rval = regs[o2i(0x40)]; 1264 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1265 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1266 1267 #ifdef _KERNEL 1268 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1269 sizebars); 1270 #else 1271 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 1272 #endif 1273 } 1274 1275 void 1276 pci_conf_print( 1277 #ifdef _KERNEL 1278 pci_chipset_tag_t pc, pcitag_t tag, 1279 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 1280 #else 1281 int pcifd, u_int bus, u_int dev, u_int func 1282 #endif 1283 ) 1284 { 1285 pcireg_t regs[o2i(256)]; 1286 int off, capoff, endoff, hdrtype; 1287 const char *typename; 1288 #ifdef _KERNEL 1289 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1290 int sizebars; 1291 #else 1292 void (*typeprintfn)(const pcireg_t *); 1293 #endif 1294 1295 printf("PCI configuration registers:\n"); 1296 1297 for (off = 0; off < 256; off += 4) { 1298 #ifdef _KERNEL 1299 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1300 #else 1301 if (pcibus_conf_read(pcifd, bus, dev, func, off, 1302 ®s[o2i(off)]) == -1) 1303 regs[o2i(off)] = 0; 1304 #endif 1305 } 1306 1307 #ifdef _KERNEL 1308 sizebars = 1; 1309 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1310 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1311 sizebars = 0; 1312 #endif 1313 1314 /* common header */ 1315 printf(" Common header:\n"); 1316 pci_conf_print_regs(regs, 0, 16); 1317 1318 printf("\n"); 1319 #ifdef _KERNEL 1320 pci_conf_print_common(pc, tag, regs); 1321 #else 1322 pci_conf_print_common(regs); 1323 #endif 1324 printf("\n"); 1325 1326 /* type-dependent header */ 1327 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1328 switch (hdrtype) { /* XXX make a table, eventually */ 1329 case 0: 1330 /* Standard device header */ 1331 typename = "\"normal\" device"; 1332 typeprintfn = &pci_conf_print_type0; 1333 capoff = PCI_CAPLISTPTR_REG; 1334 endoff = 64; 1335 break; 1336 case 1: 1337 /* PCI-PCI bridge header */ 1338 typename = "PCI-PCI bridge"; 1339 typeprintfn = &pci_conf_print_type1; 1340 capoff = PCI_CAPLISTPTR_REG; 1341 endoff = 64; 1342 break; 1343 case 2: 1344 /* PCI-CardBus bridge header */ 1345 typename = "PCI-CardBus bridge"; 1346 typeprintfn = &pci_conf_print_type2; 1347 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 1348 endoff = 72; 1349 break; 1350 default: 1351 typename = NULL; 1352 typeprintfn = 0; 1353 capoff = -1; 1354 endoff = 64; 1355 break; 1356 } 1357 printf(" Type %d ", hdrtype); 1358 if (typename != NULL) 1359 printf("(%s) ", typename); 1360 printf("header:\n"); 1361 pci_conf_print_regs(regs, 16, endoff); 1362 printf("\n"); 1363 if (typeprintfn) { 1364 #ifdef _KERNEL 1365 (*typeprintfn)(pc, tag, regs, sizebars); 1366 #else 1367 (*typeprintfn)(regs); 1368 #endif 1369 } else 1370 printf(" Don't know how to pretty-print type %d header.\n", 1371 hdrtype); 1372 printf("\n"); 1373 1374 /* capability list, if present */ 1375 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1376 && (capoff > 0)) { 1377 #ifdef _KERNEL 1378 pci_conf_print_caplist(pc, tag, regs, capoff); 1379 #else 1380 pci_conf_print_caplist(regs, capoff); 1381 #endif 1382 printf("\n"); 1383 } 1384 1385 /* device-dependent header */ 1386 printf(" Device-dependent header:\n"); 1387 pci_conf_print_regs(regs, endoff, 256); 1388 printf("\n"); 1389 #ifdef _KERNEL 1390 if (printfn) 1391 (*printfn)(pc, tag, regs); 1392 else 1393 printf(" Don't know how to pretty-print device-dependent header.\n"); 1394 printf("\n"); 1395 #endif /* _KERNEL */ 1396 } 1397
Indexes created Tue Sep 30 11:09:46 GMT 2025