pci_subr.c revision 1.83
1 /* $NetBSD: pci_subr.c,v 1.83 2010/06/06 18:58:23 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.83 2010/06/06 18:58:23 pgoyette Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdbool.h> 58 #include <stdio.h> 59 #endif 60 61 #include <dev/pci/pcireg.h> 62 #ifdef _KERNEL 63 #include <dev/pci/pcivar.h> 64 #endif 65 66 /* 67 * Descriptions of known PCI classes and subclasses. 68 * 69 * Subclasses are described in the same way as classes, but have a 70 * NULL subclass pointer. 71 */ 72 struct pci_class { 73 const char *name; 74 int val; /* as wide as pci_{,sub}class_t */ 75 const struct pci_class *subclasses; 76 }; 77 78 static const struct pci_class pci_subclass_prehistoric[] = { 79 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 80 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 81 { NULL, 0, NULL, }, 82 }; 83 84 static const struct pci_class pci_subclass_mass_storage[] = { 85 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 86 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 87 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 88 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 89 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 90 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, NULL, }, 91 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, NULL, }, 92 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 93 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 94 { NULL, 0, NULL, }, 95 }; 96 97 static const struct pci_class pci_subclass_network[] = { 98 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 99 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 100 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 101 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 102 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 103 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 104 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 105 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 106 { NULL, 0, NULL, }, 107 }; 108 109 static const struct pci_class pci_subclass_display[] = { 110 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, NULL, }, 111 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 112 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 113 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 114 { NULL, 0, NULL, }, 115 }; 116 117 static const struct pci_class pci_subclass_multimedia[] = { 118 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 119 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 120 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 121 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 122 { NULL, 0, NULL, }, 123 }; 124 125 static const struct pci_class pci_subclass_memory[] = { 126 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 127 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 128 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 129 { NULL, 0, NULL, }, 130 }; 131 132 static const struct pci_class pci_subclass_bridge[] = { 133 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 134 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 135 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 136 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 137 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, NULL, }, 138 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 139 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 140 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 141 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 142 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, NULL, }, 143 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 144 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 145 { NULL, 0, NULL, }, 146 }; 147 148 static const struct pci_class pci_subclass_communications[] = { 149 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, NULL, }, 150 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, NULL, }, 151 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL, }, 152 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, NULL, }, 153 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL, }, 154 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL, }, 155 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL, }, 156 { NULL, 0, NULL, }, 157 }; 158 159 static const struct pci_class pci_subclass_system[] = { 160 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, NULL, }, 161 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, NULL, }, 162 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, NULL, }, 163 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, NULL, }, 164 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 165 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 166 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 167 { NULL, 0, NULL, }, 168 }; 169 170 static const struct pci_class pci_subclass_input[] = { 171 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 172 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 173 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 174 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 175 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, NULL, }, 176 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 177 { NULL, 0, NULL, }, 178 }; 179 180 static const struct pci_class pci_subclass_dock[] = { 181 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 182 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 183 { NULL, 0, NULL, }, 184 }; 185 186 static const struct pci_class pci_subclass_processor[] = { 187 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 188 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 189 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 190 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 191 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 192 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 193 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 194 { NULL, 0, NULL, }, 195 }; 196 197 static const struct pci_class pci_subclass_serialbus[] = { 198 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, NULL, }, 199 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 200 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 201 { "USB", PCI_SUBCLASS_SERIALBUS_USB, NULL, }, 202 /* XXX Fiber Channel/_FIBRECHANNEL */ 203 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 204 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 205 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 206 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, NULL, }, 207 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 208 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 209 { NULL, 0, NULL, }, 210 }; 211 212 static const struct pci_class pci_subclass_wireless[] = { 213 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 214 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 215 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 216 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 217 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 218 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 219 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 220 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 221 { NULL, 0, NULL, }, 222 }; 223 224 static const struct pci_class pci_subclass_i2o[] = { 225 { "standard", PCI_SUBCLASS_I2O_STANDARD, NULL, }, 226 { NULL, 0, NULL, }, 227 }; 228 229 static const struct pci_class pci_subclass_satcom[] = { 230 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 231 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 232 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 233 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 234 { NULL, 0, NULL, }, 235 }; 236 237 static const struct pci_class pci_subclass_crypto[] = { 238 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 239 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 240 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 241 { NULL, 0, NULL, }, 242 }; 243 244 static const struct pci_class pci_subclass_dasp[] = { 245 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 246 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 247 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 248 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 249 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 250 { NULL, 0, NULL, }, 251 }; 252 253 static const struct pci_class pci_class[] = { 254 { "prehistoric", PCI_CLASS_PREHISTORIC, 255 pci_subclass_prehistoric, }, 256 { "mass storage", PCI_CLASS_MASS_STORAGE, 257 pci_subclass_mass_storage, }, 258 { "network", PCI_CLASS_NETWORK, 259 pci_subclass_network, }, 260 { "display", PCI_CLASS_DISPLAY, 261 pci_subclass_display, }, 262 { "multimedia", PCI_CLASS_MULTIMEDIA, 263 pci_subclass_multimedia, }, 264 { "memory", PCI_CLASS_MEMORY, 265 pci_subclass_memory, }, 266 { "bridge", PCI_CLASS_BRIDGE, 267 pci_subclass_bridge, }, 268 { "communications", PCI_CLASS_COMMUNICATIONS, 269 pci_subclass_communications, }, 270 { "system", PCI_CLASS_SYSTEM, 271 pci_subclass_system, }, 272 { "input", PCI_CLASS_INPUT, 273 pci_subclass_input, }, 274 { "dock", PCI_CLASS_DOCK, 275 pci_subclass_dock, }, 276 { "processor", PCI_CLASS_PROCESSOR, 277 pci_subclass_processor, }, 278 { "serial bus", PCI_CLASS_SERIALBUS, 279 pci_subclass_serialbus, }, 280 { "wireless", PCI_CLASS_WIRELESS, 281 pci_subclass_wireless, }, 282 { "I2O", PCI_CLASS_I2O, 283 pci_subclass_i2o, }, 284 { "satellite comm", PCI_CLASS_SATCOM, 285 pci_subclass_satcom, }, 286 { "crypto", PCI_CLASS_CRYPTO, 287 pci_subclass_crypto, }, 288 { "DASP", PCI_CLASS_DASP, 289 pci_subclass_dasp, }, 290 { "undefined", PCI_CLASS_UNDEFINED, 291 NULL, }, 292 { NULL, 0, 293 NULL, }, 294 }; 295 296 void pci_load_verbose(void); 297 298 #if defined(_KERNEL) 299 /* 300 * In kernel, these routines are provided and linked via the 301 * pciverbose module. 302 */ 303 const char *pci_findvendor_stub(pcireg_t); 304 const char *pci_findproduct_stub(pcireg_t); 305 306 const char *(*pci_findvendor)(pcireg_t) = pci_findvendor_stub; 307 const char *(*pci_findproduct)(pcireg_t) = pci_findproduct_stub; 308 const char *pci_unmatched = ""; 309 #else 310 /* 311 * For userland we just set the vectors here. 312 */ 313 const char *(*pci_findvendor)(pcireg_t id_reg) = pci_findvendor_real; 314 const char *(*pci_findproduct)(pcireg_t id_reg) = pci_findproduct_real; 315 const char *pci_unmatched = "unmatched "; 316 #endif 317 318 int pciverbose_loaded = 0; 319 320 #if defined(_KERNEL) 321 /* 322 * Routine to load the pciverbose kernel module as needed 323 */ 324 void pci_load_verbose(void) 325 { 326 if (pciverbose_loaded) 327 return; 328 329 mutex_enter(&module_lock); 330 if (module_autoload("pciverbose", MODULE_CLASS_MISC) == 0 ) 331 pciverbose_loaded++; 332 mutex_exit(&module_lock); 333 } 334 335 const char *pci_findvendor_stub(pcireg_t id_reg) 336 { 337 pci_load_verbose(); 338 if (pciverbose_loaded) 339 return pci_findvendor(id_reg); 340 else 341 return NULL; 342 } 343 344 const char *pci_findproduct_stub(pcireg_t id_reg) 345 { 346 pci_load_verbose(); 347 if (pciverbose_loaded) 348 return pci_findproduct(id_reg); 349 else 350 return NULL; 351 } 352 #endif 353 354 void 355 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 356 size_t l) 357 { 358 pci_vendor_id_t vendor; 359 pci_product_id_t product; 360 pci_class_t class; 361 pci_subclass_t subclass; 362 pci_interface_t interface; 363 pci_revision_t revision; 364 const char *unmatched = pci_unmatched; 365 const char *vendor_namep, *product_namep; 366 const struct pci_class *classp, *subclassp; 367 char *ep; 368 369 ep = cp + l; 370 371 vendor = PCI_VENDOR(id_reg); 372 product = PCI_PRODUCT(id_reg); 373 374 class = PCI_CLASS(class_reg); 375 subclass = PCI_SUBCLASS(class_reg); 376 interface = PCI_INTERFACE(class_reg); 377 revision = PCI_REVISION(class_reg); 378 379 vendor_namep = pci_findvendor(id_reg); 380 product_namep = pci_findproduct(id_reg); 381 382 classp = pci_class; 383 while (classp->name != NULL) { 384 if (class == classp->val) 385 break; 386 classp++; 387 } 388 389 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 390 while (subclassp && subclassp->name != NULL) { 391 if (subclass == subclassp->val) 392 break; 393 subclassp++; 394 } 395 396 if (vendor_namep == NULL) 397 cp += snprintf(cp, ep - cp, "%svendor 0x%04x product 0x%04x", 398 unmatched, vendor, product); 399 else if (product_namep != NULL) 400 cp += snprintf(cp, ep - cp, "%s %s", vendor_namep, 401 product_namep); 402 else 403 cp += snprintf(cp, ep - cp, "%s product 0x%04x", 404 vendor_namep, product); 405 if (showclass) { 406 cp += snprintf(cp, ep - cp, " ("); 407 if (classp->name == NULL) 408 cp += snprintf(cp, ep - cp, 409 "class 0x%02x, subclass 0x%02x", class, subclass); 410 else { 411 if (subclassp == NULL || subclassp->name == NULL) 412 cp += snprintf(cp, ep - cp, 413 "%s, subclass 0x%02x", 414 classp->name, subclass); 415 else 416 cp += snprintf(cp, ep - cp, "%s %s", 417 subclassp->name, classp->name); 418 } 419 if (interface != 0) 420 cp += snprintf(cp, ep - cp, ", interface 0x%02x", 421 interface); 422 if (revision != 0) 423 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 424 revision); 425 cp += snprintf(cp, ep - cp, ")"); 426 } 427 } 428 429 /* 430 * Print out most of the PCI configuration registers. Typically used 431 * in a device attach routine like this: 432 * 433 * #ifdef MYDEV_DEBUG 434 * printf("%s: ", device_xname(&sc->sc_dev)); 435 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 436 * #endif 437 */ 438 439 #define i2o(i) ((i) * 4) 440 #define o2i(o) ((o) / 4) 441 #define onoff(str, bit) \ 442 printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off"); 443 444 static void 445 pci_conf_print_common( 446 #ifdef _KERNEL 447 pci_chipset_tag_t pc, pcitag_t tag, 448 #endif 449 const pcireg_t *regs) 450 { 451 const char *name; 452 const struct pci_class *classp, *subclassp; 453 pcireg_t rval; 454 455 rval = regs[o2i(PCI_ID_REG)]; 456 name = pci_findvendor(rval); 457 if (name) 458 printf(" Vendor Name: %s (0x%04x)\n", name, 459 PCI_VENDOR(rval)); 460 else 461 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 462 name = pci_findproduct(rval); 463 if (name) 464 printf(" Device Name: %s (0x%04x)\n", name, 465 PCI_PRODUCT(rval)); 466 else 467 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 468 469 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 470 471 printf(" Command register: 0x%04x\n", rval & 0xffff); 472 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 473 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 474 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 475 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 476 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 477 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 478 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 479 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 480 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 481 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 482 onoff("Interrupt disable", PCI_COMMAND_INTERRUPT_DISABLE); 483 484 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 485 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 486 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 487 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 488 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 489 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 490 491 printf(" DEVSEL timing: "); 492 switch (rval & PCI_STATUS_DEVSEL_MASK) { 493 case PCI_STATUS_DEVSEL_FAST: 494 printf("fast"); 495 break; 496 case PCI_STATUS_DEVSEL_MEDIUM: 497 printf("medium"); 498 break; 499 case PCI_STATUS_DEVSEL_SLOW: 500 printf("slow"); 501 break; 502 default: 503 printf("unknown/reserved"); /* XXX */ 504 break; 505 } 506 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 507 508 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 509 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 510 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 511 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 512 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 513 514 rval = regs[o2i(PCI_CLASS_REG)]; 515 for (classp = pci_class; classp->name != NULL; classp++) { 516 if (PCI_CLASS(rval) == classp->val) 517 break; 518 } 519 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 520 while (subclassp && subclassp->name != NULL) { 521 if (PCI_SUBCLASS(rval) == subclassp->val) 522 break; 523 subclassp++; 524 } 525 if (classp->name != NULL) { 526 printf(" Class Name: %s (0x%02x)\n", classp->name, 527 PCI_CLASS(rval)); 528 if (subclassp != NULL && subclassp->name != NULL) 529 printf(" Subclass Name: %s (0x%02x)\n", 530 subclassp->name, PCI_SUBCLASS(rval)); 531 else 532 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 533 } else { 534 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 535 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 536 } 537 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 538 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 539 540 rval = regs[o2i(PCI_BHLC_REG)]; 541 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 542 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 543 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 544 PCI_HDRTYPE(rval)); 545 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 546 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 547 } 548 549 static int 550 pci_conf_print_bar( 551 #ifdef _KERNEL 552 pci_chipset_tag_t pc, pcitag_t tag, 553 #endif 554 const pcireg_t *regs, int reg, const char *name 555 #ifdef _KERNEL 556 , int sizebar 557 #endif 558 ) 559 { 560 int width; 561 pcireg_t rval, rval64h; 562 #ifdef _KERNEL 563 int s; 564 pcireg_t mask, mask64h; 565 #endif 566 567 width = 4; 568 569 /* 570 * Section 6.2.5.1, `Address Maps', tells us that: 571 * 572 * 1) The builtin software should have already mapped the 573 * device in a reasonable way. 574 * 575 * 2) A device which wants 2^n bytes of memory will hardwire 576 * the bottom n bits of the address to 0. As recommended, 577 * we write all 1s and see what we get back. 578 */ 579 580 rval = regs[o2i(reg)]; 581 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 582 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 583 rval64h = regs[o2i(reg + 4)]; 584 width = 8; 585 } else 586 rval64h = 0; 587 588 #ifdef _KERNEL 589 /* XXX don't size unknown memory type? */ 590 if (rval != 0 && sizebar) { 591 /* 592 * The following sequence seems to make some devices 593 * (e.g. host bus bridges, which don't normally 594 * have their space mapped) very unhappy, to 595 * the point of crashing the system. 596 * 597 * Therefore, if the mapping register is zero to 598 * start out with, don't bother trying. 599 */ 600 s = splhigh(); 601 pci_conf_write(pc, tag, reg, 0xffffffff); 602 mask = pci_conf_read(pc, tag, reg); 603 pci_conf_write(pc, tag, reg, rval); 604 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 605 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 606 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 607 mask64h = pci_conf_read(pc, tag, reg + 4); 608 pci_conf_write(pc, tag, reg + 4, rval64h); 609 } else 610 mask64h = 0; 611 splx(s); 612 } else 613 mask = mask64h = 0; 614 #endif /* _KERNEL */ 615 616 printf(" Base address register at 0x%02x", reg); 617 if (name) 618 printf(" (%s)", name); 619 printf("\n "); 620 if (rval == 0) { 621 printf("not implemented(?)\n"); 622 return width; 623 } 624 printf("type: "); 625 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 626 const char *type, *prefetch; 627 628 switch (PCI_MAPREG_MEM_TYPE(rval)) { 629 case PCI_MAPREG_MEM_TYPE_32BIT: 630 type = "32-bit"; 631 break; 632 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 633 type = "32-bit-1M"; 634 break; 635 case PCI_MAPREG_MEM_TYPE_64BIT: 636 type = "64-bit"; 637 break; 638 default: 639 type = "unknown (XXX)"; 640 break; 641 } 642 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 643 prefetch = ""; 644 else 645 prefetch = "non"; 646 printf("%s %sprefetchable memory\n", type, prefetch); 647 switch (PCI_MAPREG_MEM_TYPE(rval)) { 648 case PCI_MAPREG_MEM_TYPE_64BIT: 649 printf(" base: 0x%016llx, ", 650 PCI_MAPREG_MEM64_ADDR( 651 ((((long long) rval64h) << 32) | rval))); 652 #ifdef _KERNEL 653 if (sizebar) 654 printf("size: 0x%016llx", 655 PCI_MAPREG_MEM64_SIZE( 656 ((((long long) mask64h) << 32) | mask))); 657 else 658 #endif /* _KERNEL */ 659 printf("not sized"); 660 printf("\n"); 661 break; 662 case PCI_MAPREG_MEM_TYPE_32BIT: 663 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 664 default: 665 printf(" base: 0x%08x, ", 666 PCI_MAPREG_MEM_ADDR(rval)); 667 #ifdef _KERNEL 668 if (sizebar) 669 printf("size: 0x%08x", 670 PCI_MAPREG_MEM_SIZE(mask)); 671 else 672 #endif /* _KERNEL */ 673 printf("not sized"); 674 printf("\n"); 675 break; 676 } 677 } else { 678 #ifdef _KERNEL 679 if (sizebar) 680 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 681 #endif /* _KERNEL */ 682 printf("i/o\n"); 683 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 684 #ifdef _KERNEL 685 if (sizebar) 686 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 687 else 688 #endif /* _KERNEL */ 689 printf("not sized"); 690 printf("\n"); 691 } 692 693 return width; 694 } 695 696 static void 697 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 698 { 699 int off, needaddr, neednl; 700 701 needaddr = 1; 702 neednl = 0; 703 for (off = first; off < pastlast; off += 4) { 704 if ((off % 16) == 0 || needaddr) { 705 printf(" 0x%02x:", off); 706 needaddr = 0; 707 } 708 printf(" 0x%08x", regs[o2i(off)]); 709 neednl = 1; 710 if ((off % 16) == 12) { 711 printf("\n"); 712 neednl = 0; 713 } 714 } 715 if (neednl) 716 printf("\n"); 717 } 718 719 static void 720 pci_conf_print_type0( 721 #ifdef _KERNEL 722 pci_chipset_tag_t pc, pcitag_t tag, 723 #endif 724 const pcireg_t *regs 725 #ifdef _KERNEL 726 , int sizebars 727 #endif 728 ) 729 { 730 int off, width; 731 pcireg_t rval; 732 733 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 734 #ifdef _KERNEL 735 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 736 #else 737 width = pci_conf_print_bar(regs, off, NULL); 738 #endif 739 } 740 741 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 742 743 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 744 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 745 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 746 747 /* XXX */ 748 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 749 750 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 751 printf(" Capability list pointer: 0x%02x\n", 752 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 753 else 754 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 755 756 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 757 758 rval = regs[o2i(PCI_INTERRUPT_REG)]; 759 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 760 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 761 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 762 switch (PCI_INTERRUPT_PIN(rval)) { 763 case PCI_INTERRUPT_PIN_NONE: 764 printf("(none)"); 765 break; 766 case PCI_INTERRUPT_PIN_A: 767 printf("(pin A)"); 768 break; 769 case PCI_INTERRUPT_PIN_B: 770 printf("(pin B)"); 771 break; 772 case PCI_INTERRUPT_PIN_C: 773 printf("(pin C)"); 774 break; 775 case PCI_INTERRUPT_PIN_D: 776 printf("(pin D)"); 777 break; 778 default: 779 printf("(? ? ?)"); 780 break; 781 } 782 printf("\n"); 783 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 784 } 785 786 static void 787 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 788 { 789 bool check_slot = false; 790 791 printf("\n PCI Express Capabilities Register\n"); 792 printf(" Capability version: %x\n", 793 (unsigned int)((regs[o2i(capoff)] & 0x000f0000) >> 16)); 794 printf(" Device type: "); 795 switch ((regs[o2i(capoff)] & 0x00f00000) >> 20) { 796 case 0x0: 797 printf("PCI Express Endpoint device\n"); 798 break; 799 case 0x1: 800 printf("Legacy PCI Express Endpoint device\n"); 801 break; 802 case 0x4: 803 printf("Root Port of PCI Express Root Complex\n"); 804 check_slot = true; 805 break; 806 case 0x5: 807 printf("Upstream Port of PCI Express Switch\n"); 808 break; 809 case 0x6: 810 printf("Downstream Port of PCI Express Switch\n"); 811 check_slot = true; 812 break; 813 case 0x7: 814 printf("PCI Express to PCI/PCI-X Bridge\n"); 815 break; 816 case 0x8: 817 printf("PCI/PCI-X to PCI Express Bridge\n"); 818 break; 819 default: 820 printf("unknown\n"); 821 break; 822 } 823 if (check_slot && (regs[o2i(capoff)] & 0x01000000) != 0) 824 printf(" Slot implemented\n"); 825 printf(" Interrupt Message Number: %x\n", 826 (unsigned int)((regs[o2i(capoff)] & 0x4e000000) >> 27)); 827 if ((regs[o2i(capoff + 0x18)] & 0x07ff) != 0) { 828 printf(" Slot Control Register:\n"); 829 if ((regs[o2i(capoff + 0x18)] & 0x0001) != 0) 830 printf(" Attention Button Pressed Enabled\n"); 831 if ((regs[o2i(capoff + 0x18)] & 0x0002) != 0) 832 printf(" Power Fault Detected Enabled\n"); 833 if ((regs[o2i(capoff + 0x18)] & 0x0004) != 0) 834 printf(" MRL Sensor Changed Enabled\n"); 835 if ((regs[o2i(capoff + 0x18)] & 0x0008) != 0) 836 printf(" Presense Detected Changed Enabled\n"); 837 if ((regs[o2i(capoff + 0x18)] & 0x0010) != 0) 838 printf(" Command Completed Interrupt Enabled\n"); 839 if ((regs[o2i(capoff + 0x18)] & 0x0020) != 0) 840 printf(" Hot-Plug Interrupt Enabled\n"); 841 printf(" Attention Indicator Control: "); 842 switch ((regs[o2i(capoff + 0x18)] & 0x00c0) >> 6) { 843 case 0x0: 844 printf("reserved\n"); 845 break; 846 case 0x1: 847 printf("on\n"); 848 break; 849 case 0x2: 850 printf("blink\n"); 851 break; 852 case 0x3: 853 printf("off\n"); 854 break; 855 } 856 printf(" Power Indicator Control: "); 857 switch ((regs[o2i(capoff + 0x18)] & 0x0300) >> 8) { 858 case 0x0: 859 printf("reserved\n"); 860 break; 861 case 0x1: 862 printf("on\n"); 863 break; 864 case 0x2: 865 printf("blink\n"); 866 break; 867 case 0x3: 868 printf("off\n"); 869 break; 870 } 871 printf(" Power Controller Control: "); 872 if ((regs[o2i(capoff + 0x18)] & 0x0400) != 0) 873 printf("off\n"); 874 else 875 printf("on\n"); 876 } 877 } 878 879 static const char * 880 pci_conf_print_pcipm_cap_aux(uint16_t caps) 881 { 882 switch ((caps >> 6) & 7) { 883 case 0: return "self-powered"; 884 case 1: return "55 mA"; 885 case 2: return "100 mA"; 886 case 3: return "160 mA"; 887 case 4: return "220 mA"; 888 case 5: return "270 mA"; 889 case 6: return "320 mA"; 890 case 7: 891 default: return "375 mA"; 892 } 893 } 894 895 static const char * 896 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 897 { 898 static const char unk[] = "unknown"; 899 static const char *pmrev[8] = { 900 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 901 }; 902 if (val > 7) 903 return unk; 904 return pmrev[val]; 905 } 906 907 static void 908 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 909 { 910 uint16_t caps, pmcsr; 911 912 caps = regs[o2i(capoff)] >> 16; 913 pmcsr = regs[o2i(capoff + 0x04)] & 0xffff; 914 915 printf("\n PCI Power Management Capabilities Register\n"); 916 917 printf(" Capabilities register: 0x%04x\n", caps); 918 printf(" Version: %s\n", 919 pci_conf_print_pcipm_cap_pmrev(caps & 0x3)); 920 printf(" PME# clock: %s\n", caps & 0x4 ? "on" : "off"); 921 printf(" Device specific initialization: %s\n", 922 caps & 0x20 ? "on" : "off"); 923 printf(" 3.3V auxiliary current: %s\n", 924 pci_conf_print_pcipm_cap_aux(caps)); 925 printf(" D1 power management state support: %s\n", 926 (caps >> 9) & 1 ? "on" : "off"); 927 printf(" D2 power management state support: %s\n", 928 (caps >> 10) & 1 ? "on" : "off"); 929 printf(" PME# support: 0x%02x\n", caps >> 11); 930 931 printf(" Control/status register: 0x%04x\n", pmcsr); 932 printf(" Power state: D%d\n", pmcsr & 3); 933 printf(" PCI Express reserved: %s\n", 934 (pmcsr >> 2) & 1 ? "on" : "off"); 935 printf(" No soft reset: %s\n", (pmcsr >> 3) & 1 ? "on" : "off"); 936 printf(" PME# assertion %sabled\n", 937 (pmcsr >> 8) & 1 ? "en" : "dis"); 938 printf(" PME# status: %s\n", (pmcsr >> 15) ? "on" : "off"); 939 } 940 941 static void 942 pci_conf_print_caplist( 943 #ifdef _KERNEL 944 pci_chipset_tag_t pc, pcitag_t tag, 945 #endif 946 const pcireg_t *regs, int capoff) 947 { 948 int off; 949 pcireg_t rval; 950 int pcie_off = -1, pcipm_off = -1; 951 952 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 953 off != 0; 954 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 955 rval = regs[o2i(off)]; 956 printf(" Capability register at 0x%02x\n", off); 957 958 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 959 switch (PCI_CAPLIST_CAP(rval)) { 960 case PCI_CAP_RESERVED0: 961 printf("reserved"); 962 break; 963 case PCI_CAP_PWRMGMT: 964 printf("Power Management, rev. %s", 965 pci_conf_print_pcipm_cap_pmrev((rval >> 0) & 0x07)); 966 pcipm_off = off; 967 break; 968 case PCI_CAP_AGP: 969 printf("AGP, rev. %d.%d", 970 PCI_CAP_AGP_MAJOR(rval), 971 PCI_CAP_AGP_MINOR(rval)); 972 break; 973 case PCI_CAP_VPD: 974 printf("VPD"); 975 break; 976 case PCI_CAP_SLOTID: 977 printf("SlotID"); 978 break; 979 case PCI_CAP_MSI: 980 printf("MSI"); 981 break; 982 case PCI_CAP_CPCI_HOTSWAP: 983 printf("CompactPCI Hot-swapping"); 984 break; 985 case PCI_CAP_PCIX: 986 printf("PCI-X"); 987 break; 988 case PCI_CAP_LDT: 989 printf("LDT"); 990 break; 991 case PCI_CAP_VENDSPEC: 992 printf("Vendor-specific"); 993 break; 994 case PCI_CAP_DEBUGPORT: 995 printf("Debug Port"); 996 break; 997 case PCI_CAP_CPCI_RSRCCTL: 998 printf("CompactPCI Resource Control"); 999 break; 1000 case PCI_CAP_HOTPLUG: 1001 printf("Hot-Plug"); 1002 break; 1003 case PCI_CAP_AGP8: 1004 printf("AGP 8x"); 1005 break; 1006 case PCI_CAP_SECURE: 1007 printf("Secure Device"); 1008 break; 1009 case PCI_CAP_PCIEXPRESS: 1010 printf("PCI Express"); 1011 pcie_off = off; 1012 break; 1013 case PCI_CAP_MSIX: 1014 printf("MSI-X"); 1015 break; 1016 default: 1017 printf("unknown"); 1018 } 1019 printf(")\n"); 1020 } 1021 if (pcipm_off != -1) 1022 pci_conf_print_pcipm_cap(regs, pcipm_off); 1023 if (pcie_off != -1) 1024 pci_conf_print_pcie_cap(regs, pcie_off); 1025 } 1026 1027 /* Print the Secondary Status Register. */ 1028 static void 1029 pci_conf_print_ssr(pcireg_t rval) 1030 { 1031 pcireg_t devsel; 1032 1033 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 1034 onoff("66 MHz capable", __BIT(5)); 1035 onoff("User Definable Features (UDF) support", __BIT(6)); 1036 onoff("Fast back-to-back capable", __BIT(7)); 1037 onoff("Data parity error detected", __BIT(8)); 1038 1039 printf(" DEVSEL timing: "); 1040 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 1041 switch (devsel) { 1042 case 0: 1043 printf("fast"); 1044 break; 1045 case 1: 1046 printf("medium"); 1047 break; 1048 case 2: 1049 printf("slow"); 1050 break; 1051 default: 1052 printf("unknown/reserved"); /* XXX */ 1053 break; 1054 } 1055 printf(" (0x%x)\n", devsel); 1056 1057 onoff("Signalled target abort", __BIT(11)); 1058 onoff("Received target abort", __BIT(12)); 1059 onoff("Received master abort", __BIT(13)); 1060 onoff("Received system error", __BIT(14)); 1061 onoff("Detected parity error", __BIT(15)); 1062 } 1063 1064 static void 1065 pci_conf_print_type1( 1066 #ifdef _KERNEL 1067 pci_chipset_tag_t pc, pcitag_t tag, 1068 #endif 1069 const pcireg_t *regs 1070 #ifdef _KERNEL 1071 , int sizebars 1072 #endif 1073 ) 1074 { 1075 int off, width; 1076 pcireg_t rval; 1077 1078 /* 1079 * XXX these need to be printed in more detail, need to be 1080 * XXX checked against specs/docs, etc. 1081 * 1082 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 1083 * Bridge chip documentation, and may not be correct with 1084 * respect to various standards. (XXX) 1085 */ 1086 1087 for (off = 0x10; off < 0x18; off += width) { 1088 #ifdef _KERNEL 1089 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 1090 #else 1091 width = pci_conf_print_bar(regs, off, NULL); 1092 #endif 1093 } 1094 1095 printf(" Primary bus number: 0x%02x\n", 1096 (regs[o2i(0x18)] >> 0) & 0xff); 1097 printf(" Secondary bus number: 0x%02x\n", 1098 (regs[o2i(0x18)] >> 8) & 0xff); 1099 printf(" Subordinate bus number: 0x%02x\n", 1100 (regs[o2i(0x18)] >> 16) & 0xff); 1101 printf(" Secondary bus latency timer: 0x%02x\n", 1102 (regs[o2i(0x18)] >> 24) & 0xff); 1103 1104 pci_conf_print_ssr(__SHIFTOUT(regs[o2i(0x1c)], __BITS(31, 16))); 1105 1106 /* XXX Print more prettily */ 1107 printf(" I/O region:\n"); 1108 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 1109 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 1110 printf(" base upper 16 bits register: 0x%04x\n", 1111 (regs[o2i(0x30)] >> 0) & 0xffff); 1112 printf(" limit upper 16 bits register: 0x%04x\n", 1113 (regs[o2i(0x30)] >> 16) & 0xffff); 1114 1115 /* XXX Print more prettily */ 1116 printf(" Memory region:\n"); 1117 printf(" base register: 0x%04x\n", 1118 (regs[o2i(0x20)] >> 0) & 0xffff); 1119 printf(" limit register: 0x%04x\n", 1120 (regs[o2i(0x20)] >> 16) & 0xffff); 1121 1122 /* XXX Print more prettily */ 1123 printf(" Prefetchable memory region:\n"); 1124 printf(" base register: 0x%04x\n", 1125 (regs[o2i(0x24)] >> 0) & 0xffff); 1126 printf(" limit register: 0x%04x\n", 1127 (regs[o2i(0x24)] >> 16) & 0xffff); 1128 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 1129 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 1130 1131 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1132 printf(" Capability list pointer: 0x%02x\n", 1133 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 1134 else 1135 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 1136 1137 /* XXX */ 1138 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 1139 1140 printf(" Interrupt line: 0x%02x\n", 1141 (regs[o2i(0x3c)] >> 0) & 0xff); 1142 printf(" Interrupt pin: 0x%02x ", 1143 (regs[o2i(0x3c)] >> 8) & 0xff); 1144 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1145 case PCI_INTERRUPT_PIN_NONE: 1146 printf("(none)"); 1147 break; 1148 case PCI_INTERRUPT_PIN_A: 1149 printf("(pin A)"); 1150 break; 1151 case PCI_INTERRUPT_PIN_B: 1152 printf("(pin B)"); 1153 break; 1154 case PCI_INTERRUPT_PIN_C: 1155 printf("(pin C)"); 1156 break; 1157 case PCI_INTERRUPT_PIN_D: 1158 printf("(pin D)"); 1159 break; 1160 default: 1161 printf("(? ? ?)"); 1162 break; 1163 } 1164 printf("\n"); 1165 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1166 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 1167 onoff("Parity error response", 0x0001); 1168 onoff("Secondary SERR forwarding", 0x0002); 1169 onoff("ISA enable", 0x0004); 1170 onoff("VGA enable", 0x0008); 1171 onoff("Master abort reporting", 0x0020); 1172 onoff("Secondary bus reset", 0x0040); 1173 onoff("Fast back-to-back capable", 0x0080); 1174 } 1175 1176 static void 1177 pci_conf_print_type2( 1178 #ifdef _KERNEL 1179 pci_chipset_tag_t pc, pcitag_t tag, 1180 #endif 1181 const pcireg_t *regs 1182 #ifdef _KERNEL 1183 , int sizebars 1184 #endif 1185 ) 1186 { 1187 pcireg_t rval; 1188 1189 /* 1190 * XXX these need to be printed in more detail, need to be 1191 * XXX checked against specs/docs, etc. 1192 * 1193 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 1194 * controller chip documentation, and may not be correct with 1195 * respect to various standards. (XXX) 1196 */ 1197 1198 #ifdef _KERNEL 1199 pci_conf_print_bar(pc, tag, regs, 0x10, 1200 "CardBus socket/ExCA registers", sizebars); 1201 #else 1202 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 1203 #endif 1204 1205 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1206 printf(" Capability list pointer: 0x%02x\n", 1207 PCI_CAPLIST_PTR(regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)])); 1208 else 1209 printf(" Reserved @ 0x14: 0x%04" PRIxMAX "\n", 1210 __SHIFTOUT(regs[o2i(0x14)], __BITS(15, 0))); 1211 pci_conf_print_ssr(__SHIFTOUT(regs[o2i(0x14)], __BITS(31, 16))); 1212 1213 printf(" PCI bus number: 0x%02x\n", 1214 (regs[o2i(0x18)] >> 0) & 0xff); 1215 printf(" CardBus bus number: 0x%02x\n", 1216 (regs[o2i(0x18)] >> 8) & 0xff); 1217 printf(" Subordinate bus number: 0x%02x\n", 1218 (regs[o2i(0x18)] >> 16) & 0xff); 1219 printf(" CardBus latency timer: 0x%02x\n", 1220 (regs[o2i(0x18)] >> 24) & 0xff); 1221 1222 /* XXX Print more prettily */ 1223 printf(" CardBus memory region 0:\n"); 1224 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1225 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1226 printf(" CardBus memory region 1:\n"); 1227 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1228 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1229 printf(" CardBus I/O region 0:\n"); 1230 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1231 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1232 printf(" CardBus I/O region 1:\n"); 1233 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1234 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1235 1236 printf(" Interrupt line: 0x%02x\n", 1237 (regs[o2i(0x3c)] >> 0) & 0xff); 1238 printf(" Interrupt pin: 0x%02x ", 1239 (regs[o2i(0x3c)] >> 8) & 0xff); 1240 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1241 case PCI_INTERRUPT_PIN_NONE: 1242 printf("(none)"); 1243 break; 1244 case PCI_INTERRUPT_PIN_A: 1245 printf("(pin A)"); 1246 break; 1247 case PCI_INTERRUPT_PIN_B: 1248 printf("(pin B)"); 1249 break; 1250 case PCI_INTERRUPT_PIN_C: 1251 printf("(pin C)"); 1252 break; 1253 case PCI_INTERRUPT_PIN_D: 1254 printf("(pin D)"); 1255 break; 1256 default: 1257 printf("(? ? ?)"); 1258 break; 1259 } 1260 printf("\n"); 1261 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1262 printf(" Bridge control register: 0x%04x\n", rval); 1263 onoff("Parity error response", __BIT(0)); 1264 onoff("SERR# enable", __BIT(1)); 1265 onoff("ISA enable", __BIT(2)); 1266 onoff("VGA enable", __BIT(3)); 1267 onoff("Master abort mode", __BIT(5)); 1268 onoff("Secondary (CardBus) bus reset", __BIT(6)); 1269 onoff("Functional interrupts routed by ExCA registers", __BIT(7)); 1270 onoff("Memory window 0 prefetchable", __BIT(8)); 1271 onoff("Memory window 1 prefetchable", __BIT(9)); 1272 onoff("Write posting enable", __BIT(10)); 1273 1274 rval = regs[o2i(0x40)]; 1275 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1276 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1277 1278 #ifdef _KERNEL 1279 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1280 sizebars); 1281 #else 1282 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 1283 #endif 1284 } 1285 1286 void 1287 pci_conf_print( 1288 #ifdef _KERNEL 1289 pci_chipset_tag_t pc, pcitag_t tag, 1290 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 1291 #else 1292 int pcifd, u_int bus, u_int dev, u_int func 1293 #endif 1294 ) 1295 { 1296 pcireg_t regs[o2i(256)]; 1297 int off, capoff, endoff, hdrtype; 1298 const char *typename; 1299 #ifdef _KERNEL 1300 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1301 int sizebars; 1302 #else 1303 void (*typeprintfn)(const pcireg_t *); 1304 #endif 1305 1306 printf("PCI configuration registers:\n"); 1307 1308 for (off = 0; off < 256; off += 4) { 1309 #ifdef _KERNEL 1310 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1311 #else 1312 if (pcibus_conf_read(pcifd, bus, dev, func, off, 1313 ®s[o2i(off)]) == -1) 1314 regs[o2i(off)] = 0; 1315 #endif 1316 } 1317 1318 #ifdef _KERNEL 1319 sizebars = 1; 1320 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1321 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1322 sizebars = 0; 1323 #endif 1324 1325 /* common header */ 1326 printf(" Common header:\n"); 1327 pci_conf_print_regs(regs, 0, 16); 1328 1329 printf("\n"); 1330 #ifdef _KERNEL 1331 pci_conf_print_common(pc, tag, regs); 1332 #else 1333 pci_conf_print_common(regs); 1334 #endif 1335 printf("\n"); 1336 1337 /* type-dependent header */ 1338 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1339 switch (hdrtype) { /* XXX make a table, eventually */ 1340 case 0: 1341 /* Standard device header */ 1342 typename = "\"normal\" device"; 1343 typeprintfn = &pci_conf_print_type0; 1344 capoff = PCI_CAPLISTPTR_REG; 1345 endoff = 64; 1346 break; 1347 case 1: 1348 /* PCI-PCI bridge header */ 1349 typename = "PCI-PCI bridge"; 1350 typeprintfn = &pci_conf_print_type1; 1351 capoff = PCI_CAPLISTPTR_REG; 1352 endoff = 64; 1353 break; 1354 case 2: 1355 /* PCI-CardBus bridge header */ 1356 typename = "PCI-CardBus bridge"; 1357 typeprintfn = &pci_conf_print_type2; 1358 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 1359 endoff = 72; 1360 break; 1361 default: 1362 typename = NULL; 1363 typeprintfn = 0; 1364 capoff = -1; 1365 endoff = 64; 1366 break; 1367 } 1368 printf(" Type %d ", hdrtype); 1369 if (typename != NULL) 1370 printf("(%s) ", typename); 1371 printf("header:\n"); 1372 pci_conf_print_regs(regs, 16, endoff); 1373 printf("\n"); 1374 if (typeprintfn) { 1375 #ifdef _KERNEL 1376 (*typeprintfn)(pc, tag, regs, sizebars); 1377 #else 1378 (*typeprintfn)(regs); 1379 #endif 1380 } else 1381 printf(" Don't know how to pretty-print type %d header.\n", 1382 hdrtype); 1383 printf("\n"); 1384 1385 /* capability list, if present */ 1386 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1387 && (capoff > 0)) { 1388 #ifdef _KERNEL 1389 pci_conf_print_caplist(pc, tag, regs, capoff); 1390 #else 1391 pci_conf_print_caplist(regs, capoff); 1392 #endif 1393 printf("\n"); 1394 } 1395 1396 /* device-dependent header */ 1397 printf(" Device-dependent header:\n"); 1398 pci_conf_print_regs(regs, endoff, 256); 1399 printf("\n"); 1400 #ifdef _KERNEL 1401 if (printfn) 1402 (*printfn)(pc, tag, regs); 1403 else 1404 printf(" Don't know how to pretty-print device-dependent header.\n"); 1405 printf("\n"); 1406 #endif /* _KERNEL */ 1407 } 1408
Indexes created Wed Sep 24 05:09:52 GMT 2025