pci_subr.c revision 1.84
1 /* $NetBSD: pci_subr.c,v 1.84 2010/07/25 14:14:25 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.84 2010/07/25 14:14:25 pgoyette Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdbool.h> 58 #include <stdio.h> 59 #endif 60 61 #include <dev/pci/pcireg.h> 62 #ifdef _KERNEL 63 #include <dev/pci/pcivar.h> 64 #endif 65 66 /* 67 * Descriptions of known PCI classes and subclasses. 68 * 69 * Subclasses are described in the same way as classes, but have a 70 * NULL subclass pointer. 71 */ 72 struct pci_class { 73 const char *name; 74 int val; /* as wide as pci_{,sub}class_t */ 75 const struct pci_class *subclasses; 76 }; 77 78 static const struct pci_class pci_subclass_prehistoric[] = { 79 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 80 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 81 { NULL, 0, NULL, }, 82 }; 83 84 static const struct pci_class pci_subclass_mass_storage[] = { 85 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 86 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 87 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 88 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 89 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 90 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, NULL, }, 91 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, NULL, }, 92 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 93 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 94 { NULL, 0, NULL, }, 95 }; 96 97 static const struct pci_class pci_subclass_network[] = { 98 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 99 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 100 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 101 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 102 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 103 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 104 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 105 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 106 { NULL, 0, NULL, }, 107 }; 108 109 static const struct pci_class pci_subclass_display[] = { 110 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, NULL, }, 111 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 112 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 113 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 114 { NULL, 0, NULL, }, 115 }; 116 117 static const struct pci_class pci_subclass_multimedia[] = { 118 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 119 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 120 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 121 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 122 { NULL, 0, NULL, }, 123 }; 124 125 static const struct pci_class pci_subclass_memory[] = { 126 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 127 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 128 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 129 { NULL, 0, NULL, }, 130 }; 131 132 static const struct pci_class pci_subclass_bridge[] = { 133 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 134 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 135 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 136 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 137 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, NULL, }, 138 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 139 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 140 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 141 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 142 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, NULL, }, 143 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 144 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 145 { NULL, 0, NULL, }, 146 }; 147 148 static const struct pci_class pci_subclass_communications[] = { 149 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, NULL, }, 150 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, NULL, }, 151 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL, }, 152 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, NULL, }, 153 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL, }, 154 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL, }, 155 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL, }, 156 { NULL, 0, NULL, }, 157 }; 158 159 static const struct pci_class pci_subclass_system[] = { 160 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, NULL, }, 161 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, NULL, }, 162 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, NULL, }, 163 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, NULL, }, 164 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 165 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 166 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 167 { NULL, 0, NULL, }, 168 }; 169 170 static const struct pci_class pci_subclass_input[] = { 171 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 172 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 173 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 174 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 175 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, NULL, }, 176 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 177 { NULL, 0, NULL, }, 178 }; 179 180 static const struct pci_class pci_subclass_dock[] = { 181 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 182 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 183 { NULL, 0, NULL, }, 184 }; 185 186 static const struct pci_class pci_subclass_processor[] = { 187 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 188 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 189 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 190 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 191 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 192 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 193 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 194 { NULL, 0, NULL, }, 195 }; 196 197 static const struct pci_class pci_subclass_serialbus[] = { 198 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, NULL, }, 199 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 200 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 201 { "USB", PCI_SUBCLASS_SERIALBUS_USB, NULL, }, 202 /* XXX Fiber Channel/_FIBRECHANNEL */ 203 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 204 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 205 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 206 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, NULL, }, 207 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 208 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 209 { NULL, 0, NULL, }, 210 }; 211 212 static const struct pci_class pci_subclass_wireless[] = { 213 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 214 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 215 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 216 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 217 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 218 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 219 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 220 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 221 { NULL, 0, NULL, }, 222 }; 223 224 static const struct pci_class pci_subclass_i2o[] = { 225 { "standard", PCI_SUBCLASS_I2O_STANDARD, NULL, }, 226 { NULL, 0, NULL, }, 227 }; 228 229 static const struct pci_class pci_subclass_satcom[] = { 230 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 231 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 232 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 233 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 234 { NULL, 0, NULL, }, 235 }; 236 237 static const struct pci_class pci_subclass_crypto[] = { 238 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 239 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 240 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 241 { NULL, 0, NULL, }, 242 }; 243 244 static const struct pci_class pci_subclass_dasp[] = { 245 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 246 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 247 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 248 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 249 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 250 { NULL, 0, NULL, }, 251 }; 252 253 static const struct pci_class pci_class[] = { 254 { "prehistoric", PCI_CLASS_PREHISTORIC, 255 pci_subclass_prehistoric, }, 256 { "mass storage", PCI_CLASS_MASS_STORAGE, 257 pci_subclass_mass_storage, }, 258 { "network", PCI_CLASS_NETWORK, 259 pci_subclass_network, }, 260 { "display", PCI_CLASS_DISPLAY, 261 pci_subclass_display, }, 262 { "multimedia", PCI_CLASS_MULTIMEDIA, 263 pci_subclass_multimedia, }, 264 { "memory", PCI_CLASS_MEMORY, 265 pci_subclass_memory, }, 266 { "bridge", PCI_CLASS_BRIDGE, 267 pci_subclass_bridge, }, 268 { "communications", PCI_CLASS_COMMUNICATIONS, 269 pci_subclass_communications, }, 270 { "system", PCI_CLASS_SYSTEM, 271 pci_subclass_system, }, 272 { "input", PCI_CLASS_INPUT, 273 pci_subclass_input, }, 274 { "dock", PCI_CLASS_DOCK, 275 pci_subclass_dock, }, 276 { "processor", PCI_CLASS_PROCESSOR, 277 pci_subclass_processor, }, 278 { "serial bus", PCI_CLASS_SERIALBUS, 279 pci_subclass_serialbus, }, 280 { "wireless", PCI_CLASS_WIRELESS, 281 pci_subclass_wireless, }, 282 { "I2O", PCI_CLASS_I2O, 283 pci_subclass_i2o, }, 284 { "satellite comm", PCI_CLASS_SATCOM, 285 pci_subclass_satcom, }, 286 { "crypto", PCI_CLASS_CRYPTO, 287 pci_subclass_crypto, }, 288 { "DASP", PCI_CLASS_DASP, 289 pci_subclass_dasp, }, 290 { "undefined", PCI_CLASS_UNDEFINED, 291 NULL, }, 292 { NULL, 0, 293 NULL, }, 294 }; 295 296 void pci_load_verbose(void); 297 298 #if defined(_KERNEL) 299 /* 300 * In kernel, these routines are provided and linked via the 301 * pciverbose module. 302 */ 303 const char *pci_findvendor_stub(pcireg_t); 304 const char *pci_findproduct_stub(pcireg_t); 305 306 const char *(*pci_findvendor)(pcireg_t) = pci_findvendor_stub; 307 const char *(*pci_findproduct)(pcireg_t) = pci_findproduct_stub; 308 const char *pci_unmatched = ""; 309 #else 310 /* 311 * For userland we just set the vectors here. 312 */ 313 const char *(*pci_findvendor)(pcireg_t id_reg) = pci_findvendor_real; 314 const char *(*pci_findproduct)(pcireg_t id_reg) = pci_findproduct_real; 315 const char *pci_unmatched = "unmatched "; 316 #endif 317 318 int pciverbose_loaded = 0; 319 320 #if defined(_KERNEL) 321 /* 322 * Routine to load the pciverbose kernel module as needed 323 */ 324 void pci_load_verbose(void) 325 { 326 if (pciverbose_loaded == 0) { 327 mutex_enter(&module_lock); 328 module_autoload("pciverbose", MODULE_CLASS_MISC); 329 mutex_exit(&module_lock); 330 } 331 } 332 333 const char *pci_findvendor_stub(pcireg_t id_reg) 334 { 335 pci_load_verbose(); 336 if (pciverbose_loaded) 337 return pci_findvendor(id_reg); 338 else 339 return NULL; 340 } 341 342 const char *pci_findproduct_stub(pcireg_t id_reg) 343 { 344 pci_load_verbose(); 345 if (pciverbose_loaded) 346 return pci_findproduct(id_reg); 347 else 348 return NULL; 349 } 350 #endif 351 352 void 353 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 354 size_t l) 355 { 356 pci_vendor_id_t vendor; 357 pci_product_id_t product; 358 pci_class_t class; 359 pci_subclass_t subclass; 360 pci_interface_t interface; 361 pci_revision_t revision; 362 const char *unmatched = pci_unmatched; 363 const char *vendor_namep, *product_namep; 364 const struct pci_class *classp, *subclassp; 365 char *ep; 366 367 ep = cp + l; 368 369 vendor = PCI_VENDOR(id_reg); 370 product = PCI_PRODUCT(id_reg); 371 372 class = PCI_CLASS(class_reg); 373 subclass = PCI_SUBCLASS(class_reg); 374 interface = PCI_INTERFACE(class_reg); 375 revision = PCI_REVISION(class_reg); 376 377 vendor_namep = pci_findvendor(id_reg); 378 product_namep = pci_findproduct(id_reg); 379 380 classp = pci_class; 381 while (classp->name != NULL) { 382 if (class == classp->val) 383 break; 384 classp++; 385 } 386 387 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 388 while (subclassp && subclassp->name != NULL) { 389 if (subclass == subclassp->val) 390 break; 391 subclassp++; 392 } 393 394 if (vendor_namep == NULL) 395 cp += snprintf(cp, ep - cp, "%svendor 0x%04x product 0x%04x", 396 unmatched, vendor, product); 397 else if (product_namep != NULL) 398 cp += snprintf(cp, ep - cp, "%s %s", vendor_namep, 399 product_namep); 400 else 401 cp += snprintf(cp, ep - cp, "%s product 0x%04x", 402 vendor_namep, product); 403 if (showclass) { 404 cp += snprintf(cp, ep - cp, " ("); 405 if (classp->name == NULL) 406 cp += snprintf(cp, ep - cp, 407 "class 0x%02x, subclass 0x%02x", class, subclass); 408 else { 409 if (subclassp == NULL || subclassp->name == NULL) 410 cp += snprintf(cp, ep - cp, 411 "%s, subclass 0x%02x", 412 classp->name, subclass); 413 else 414 cp += snprintf(cp, ep - cp, "%s %s", 415 subclassp->name, classp->name); 416 } 417 if (interface != 0) 418 cp += snprintf(cp, ep - cp, ", interface 0x%02x", 419 interface); 420 if (revision != 0) 421 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 422 revision); 423 cp += snprintf(cp, ep - cp, ")"); 424 } 425 } 426 427 /* 428 * Print out most of the PCI configuration registers. Typically used 429 * in a device attach routine like this: 430 * 431 * #ifdef MYDEV_DEBUG 432 * printf("%s: ", device_xname(&sc->sc_dev)); 433 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 434 * #endif 435 */ 436 437 #define i2o(i) ((i) * 4) 438 #define o2i(o) ((o) / 4) 439 #define onoff(str, bit) \ 440 printf(" %s: %s\n", (str), (rval & (bit)) ? "on" : "off"); 441 442 static void 443 pci_conf_print_common( 444 #ifdef _KERNEL 445 pci_chipset_tag_t pc, pcitag_t tag, 446 #endif 447 const pcireg_t *regs) 448 { 449 const char *name; 450 const struct pci_class *classp, *subclassp; 451 pcireg_t rval; 452 453 rval = regs[o2i(PCI_ID_REG)]; 454 name = pci_findvendor(rval); 455 if (name) 456 printf(" Vendor Name: %s (0x%04x)\n", name, 457 PCI_VENDOR(rval)); 458 else 459 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 460 name = pci_findproduct(rval); 461 if (name) 462 printf(" Device Name: %s (0x%04x)\n", name, 463 PCI_PRODUCT(rval)); 464 else 465 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 466 467 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 468 469 printf(" Command register: 0x%04x\n", rval & 0xffff); 470 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 471 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 472 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 473 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 474 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 475 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 476 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 477 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 478 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 479 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 480 onoff("Interrupt disable", PCI_COMMAND_INTERRUPT_DISABLE); 481 482 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 483 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 484 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 485 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 486 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 487 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 488 489 printf(" DEVSEL timing: "); 490 switch (rval & PCI_STATUS_DEVSEL_MASK) { 491 case PCI_STATUS_DEVSEL_FAST: 492 printf("fast"); 493 break; 494 case PCI_STATUS_DEVSEL_MEDIUM: 495 printf("medium"); 496 break; 497 case PCI_STATUS_DEVSEL_SLOW: 498 printf("slow"); 499 break; 500 default: 501 printf("unknown/reserved"); /* XXX */ 502 break; 503 } 504 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 505 506 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 507 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 508 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 509 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 510 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 511 512 rval = regs[o2i(PCI_CLASS_REG)]; 513 for (classp = pci_class; classp->name != NULL; classp++) { 514 if (PCI_CLASS(rval) == classp->val) 515 break; 516 } 517 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 518 while (subclassp && subclassp->name != NULL) { 519 if (PCI_SUBCLASS(rval) == subclassp->val) 520 break; 521 subclassp++; 522 } 523 if (classp->name != NULL) { 524 printf(" Class Name: %s (0x%02x)\n", classp->name, 525 PCI_CLASS(rval)); 526 if (subclassp != NULL && subclassp->name != NULL) 527 printf(" Subclass Name: %s (0x%02x)\n", 528 subclassp->name, PCI_SUBCLASS(rval)); 529 else 530 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 531 } else { 532 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 533 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 534 } 535 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 536 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 537 538 rval = regs[o2i(PCI_BHLC_REG)]; 539 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 540 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 541 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 542 PCI_HDRTYPE(rval)); 543 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 544 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 545 } 546 547 static int 548 pci_conf_print_bar( 549 #ifdef _KERNEL 550 pci_chipset_tag_t pc, pcitag_t tag, 551 #endif 552 const pcireg_t *regs, int reg, const char *name 553 #ifdef _KERNEL 554 , int sizebar 555 #endif 556 ) 557 { 558 int width; 559 pcireg_t rval, rval64h; 560 #ifdef _KERNEL 561 int s; 562 pcireg_t mask, mask64h; 563 #endif 564 565 width = 4; 566 567 /* 568 * Section 6.2.5.1, `Address Maps', tells us that: 569 * 570 * 1) The builtin software should have already mapped the 571 * device in a reasonable way. 572 * 573 * 2) A device which wants 2^n bytes of memory will hardwire 574 * the bottom n bits of the address to 0. As recommended, 575 * we write all 1s and see what we get back. 576 */ 577 578 rval = regs[o2i(reg)]; 579 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 580 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 581 rval64h = regs[o2i(reg + 4)]; 582 width = 8; 583 } else 584 rval64h = 0; 585 586 #ifdef _KERNEL 587 /* XXX don't size unknown memory type? */ 588 if (rval != 0 && sizebar) { 589 /* 590 * The following sequence seems to make some devices 591 * (e.g. host bus bridges, which don't normally 592 * have their space mapped) very unhappy, to 593 * the point of crashing the system. 594 * 595 * Therefore, if the mapping register is zero to 596 * start out with, don't bother trying. 597 */ 598 s = splhigh(); 599 pci_conf_write(pc, tag, reg, 0xffffffff); 600 mask = pci_conf_read(pc, tag, reg); 601 pci_conf_write(pc, tag, reg, rval); 602 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 603 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 604 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 605 mask64h = pci_conf_read(pc, tag, reg + 4); 606 pci_conf_write(pc, tag, reg + 4, rval64h); 607 } else 608 mask64h = 0; 609 splx(s); 610 } else 611 mask = mask64h = 0; 612 #endif /* _KERNEL */ 613 614 printf(" Base address register at 0x%02x", reg); 615 if (name) 616 printf(" (%s)", name); 617 printf("\n "); 618 if (rval == 0) { 619 printf("not implemented(?)\n"); 620 return width; 621 } 622 printf("type: "); 623 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 624 const char *type, *prefetch; 625 626 switch (PCI_MAPREG_MEM_TYPE(rval)) { 627 case PCI_MAPREG_MEM_TYPE_32BIT: 628 type = "32-bit"; 629 break; 630 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 631 type = "32-bit-1M"; 632 break; 633 case PCI_MAPREG_MEM_TYPE_64BIT: 634 type = "64-bit"; 635 break; 636 default: 637 type = "unknown (XXX)"; 638 break; 639 } 640 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 641 prefetch = ""; 642 else 643 prefetch = "non"; 644 printf("%s %sprefetchable memory\n", type, prefetch); 645 switch (PCI_MAPREG_MEM_TYPE(rval)) { 646 case PCI_MAPREG_MEM_TYPE_64BIT: 647 printf(" base: 0x%016llx, ", 648 PCI_MAPREG_MEM64_ADDR( 649 ((((long long) rval64h) << 32) | rval))); 650 #ifdef _KERNEL 651 if (sizebar) 652 printf("size: 0x%016llx", 653 PCI_MAPREG_MEM64_SIZE( 654 ((((long long) mask64h) << 32) | mask))); 655 else 656 #endif /* _KERNEL */ 657 printf("not sized"); 658 printf("\n"); 659 break; 660 case PCI_MAPREG_MEM_TYPE_32BIT: 661 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 662 default: 663 printf(" base: 0x%08x, ", 664 PCI_MAPREG_MEM_ADDR(rval)); 665 #ifdef _KERNEL 666 if (sizebar) 667 printf("size: 0x%08x", 668 PCI_MAPREG_MEM_SIZE(mask)); 669 else 670 #endif /* _KERNEL */ 671 printf("not sized"); 672 printf("\n"); 673 break; 674 } 675 } else { 676 #ifdef _KERNEL 677 if (sizebar) 678 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 679 #endif /* _KERNEL */ 680 printf("i/o\n"); 681 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 682 #ifdef _KERNEL 683 if (sizebar) 684 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 685 else 686 #endif /* _KERNEL */ 687 printf("not sized"); 688 printf("\n"); 689 } 690 691 return width; 692 } 693 694 static void 695 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 696 { 697 int off, needaddr, neednl; 698 699 needaddr = 1; 700 neednl = 0; 701 for (off = first; off < pastlast; off += 4) { 702 if ((off % 16) == 0 || needaddr) { 703 printf(" 0x%02x:", off); 704 needaddr = 0; 705 } 706 printf(" 0x%08x", regs[o2i(off)]); 707 neednl = 1; 708 if ((off % 16) == 12) { 709 printf("\n"); 710 neednl = 0; 711 } 712 } 713 if (neednl) 714 printf("\n"); 715 } 716 717 static void 718 pci_conf_print_type0( 719 #ifdef _KERNEL 720 pci_chipset_tag_t pc, pcitag_t tag, 721 #endif 722 const pcireg_t *regs 723 #ifdef _KERNEL 724 , int sizebars 725 #endif 726 ) 727 { 728 int off, width; 729 pcireg_t rval; 730 731 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 732 #ifdef _KERNEL 733 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 734 #else 735 width = pci_conf_print_bar(regs, off, NULL); 736 #endif 737 } 738 739 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 740 741 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 742 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 743 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 744 745 /* XXX */ 746 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 747 748 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 749 printf(" Capability list pointer: 0x%02x\n", 750 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 751 else 752 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 753 754 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 755 756 rval = regs[o2i(PCI_INTERRUPT_REG)]; 757 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 758 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 759 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 760 switch (PCI_INTERRUPT_PIN(rval)) { 761 case PCI_INTERRUPT_PIN_NONE: 762 printf("(none)"); 763 break; 764 case PCI_INTERRUPT_PIN_A: 765 printf("(pin A)"); 766 break; 767 case PCI_INTERRUPT_PIN_B: 768 printf("(pin B)"); 769 break; 770 case PCI_INTERRUPT_PIN_C: 771 printf("(pin C)"); 772 break; 773 case PCI_INTERRUPT_PIN_D: 774 printf("(pin D)"); 775 break; 776 default: 777 printf("(? ? ?)"); 778 break; 779 } 780 printf("\n"); 781 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 782 } 783 784 static void 785 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 786 { 787 bool check_slot = false; 788 789 printf("\n PCI Express Capabilities Register\n"); 790 printf(" Capability version: %x\n", 791 (unsigned int)((regs[o2i(capoff)] & 0x000f0000) >> 16)); 792 printf(" Device type: "); 793 switch ((regs[o2i(capoff)] & 0x00f00000) >> 20) { 794 case 0x0: 795 printf("PCI Express Endpoint device\n"); 796 break; 797 case 0x1: 798 printf("Legacy PCI Express Endpoint device\n"); 799 break; 800 case 0x4: 801 printf("Root Port of PCI Express Root Complex\n"); 802 check_slot = true; 803 break; 804 case 0x5: 805 printf("Upstream Port of PCI Express Switch\n"); 806 break; 807 case 0x6: 808 printf("Downstream Port of PCI Express Switch\n"); 809 check_slot = true; 810 break; 811 case 0x7: 812 printf("PCI Express to PCI/PCI-X Bridge\n"); 813 break; 814 case 0x8: 815 printf("PCI/PCI-X to PCI Express Bridge\n"); 816 break; 817 default: 818 printf("unknown\n"); 819 break; 820 } 821 if (check_slot && (regs[o2i(capoff)] & 0x01000000) != 0) 822 printf(" Slot implemented\n"); 823 printf(" Interrupt Message Number: %x\n", 824 (unsigned int)((regs[o2i(capoff)] & 0x4e000000) >> 27)); 825 if ((regs[o2i(capoff + 0x18)] & 0x07ff) != 0) { 826 printf(" Slot Control Register:\n"); 827 if ((regs[o2i(capoff + 0x18)] & 0x0001) != 0) 828 printf(" Attention Button Pressed Enabled\n"); 829 if ((regs[o2i(capoff + 0x18)] & 0x0002) != 0) 830 printf(" Power Fault Detected Enabled\n"); 831 if ((regs[o2i(capoff + 0x18)] & 0x0004) != 0) 832 printf(" MRL Sensor Changed Enabled\n"); 833 if ((regs[o2i(capoff + 0x18)] & 0x0008) != 0) 834 printf(" Presense Detected Changed Enabled\n"); 835 if ((regs[o2i(capoff + 0x18)] & 0x0010) != 0) 836 printf(" Command Completed Interrupt Enabled\n"); 837 if ((regs[o2i(capoff + 0x18)] & 0x0020) != 0) 838 printf(" Hot-Plug Interrupt Enabled\n"); 839 printf(" Attention Indicator Control: "); 840 switch ((regs[o2i(capoff + 0x18)] & 0x00c0) >> 6) { 841 case 0x0: 842 printf("reserved\n"); 843 break; 844 case 0x1: 845 printf("on\n"); 846 break; 847 case 0x2: 848 printf("blink\n"); 849 break; 850 case 0x3: 851 printf("off\n"); 852 break; 853 } 854 printf(" Power Indicator Control: "); 855 switch ((regs[o2i(capoff + 0x18)] & 0x0300) >> 8) { 856 case 0x0: 857 printf("reserved\n"); 858 break; 859 case 0x1: 860 printf("on\n"); 861 break; 862 case 0x2: 863 printf("blink\n"); 864 break; 865 case 0x3: 866 printf("off\n"); 867 break; 868 } 869 printf(" Power Controller Control: "); 870 if ((regs[o2i(capoff + 0x18)] & 0x0400) != 0) 871 printf("off\n"); 872 else 873 printf("on\n"); 874 } 875 } 876 877 static const char * 878 pci_conf_print_pcipm_cap_aux(uint16_t caps) 879 { 880 switch ((caps >> 6) & 7) { 881 case 0: return "self-powered"; 882 case 1: return "55 mA"; 883 case 2: return "100 mA"; 884 case 3: return "160 mA"; 885 case 4: return "220 mA"; 886 case 5: return "270 mA"; 887 case 6: return "320 mA"; 888 case 7: 889 default: return "375 mA"; 890 } 891 } 892 893 static const char * 894 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 895 { 896 static const char unk[] = "unknown"; 897 static const char *pmrev[8] = { 898 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 899 }; 900 if (val > 7) 901 return unk; 902 return pmrev[val]; 903 } 904 905 static void 906 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 907 { 908 uint16_t caps, pmcsr; 909 910 caps = regs[o2i(capoff)] >> 16; 911 pmcsr = regs[o2i(capoff + 0x04)] & 0xffff; 912 913 printf("\n PCI Power Management Capabilities Register\n"); 914 915 printf(" Capabilities register: 0x%04x\n", caps); 916 printf(" Version: %s\n", 917 pci_conf_print_pcipm_cap_pmrev(caps & 0x3)); 918 printf(" PME# clock: %s\n", caps & 0x4 ? "on" : "off"); 919 printf(" Device specific initialization: %s\n", 920 caps & 0x20 ? "on" : "off"); 921 printf(" 3.3V auxiliary current: %s\n", 922 pci_conf_print_pcipm_cap_aux(caps)); 923 printf(" D1 power management state support: %s\n", 924 (caps >> 9) & 1 ? "on" : "off"); 925 printf(" D2 power management state support: %s\n", 926 (caps >> 10) & 1 ? "on" : "off"); 927 printf(" PME# support: 0x%02x\n", caps >> 11); 928 929 printf(" Control/status register: 0x%04x\n", pmcsr); 930 printf(" Power state: D%d\n", pmcsr & 3); 931 printf(" PCI Express reserved: %s\n", 932 (pmcsr >> 2) & 1 ? "on" : "off"); 933 printf(" No soft reset: %s\n", (pmcsr >> 3) & 1 ? "on" : "off"); 934 printf(" PME# assertion %sabled\n", 935 (pmcsr >> 8) & 1 ? "en" : "dis"); 936 printf(" PME# status: %s\n", (pmcsr >> 15) ? "on" : "off"); 937 } 938 939 static void 940 pci_conf_print_caplist( 941 #ifdef _KERNEL 942 pci_chipset_tag_t pc, pcitag_t tag, 943 #endif 944 const pcireg_t *regs, int capoff) 945 { 946 int off; 947 pcireg_t rval; 948 int pcie_off = -1, pcipm_off = -1; 949 950 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 951 off != 0; 952 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 953 rval = regs[o2i(off)]; 954 printf(" Capability register at 0x%02x\n", off); 955 956 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 957 switch (PCI_CAPLIST_CAP(rval)) { 958 case PCI_CAP_RESERVED0: 959 printf("reserved"); 960 break; 961 case PCI_CAP_PWRMGMT: 962 printf("Power Management, rev. %s", 963 pci_conf_print_pcipm_cap_pmrev((rval >> 0) & 0x07)); 964 pcipm_off = off; 965 break; 966 case PCI_CAP_AGP: 967 printf("AGP, rev. %d.%d", 968 PCI_CAP_AGP_MAJOR(rval), 969 PCI_CAP_AGP_MINOR(rval)); 970 break; 971 case PCI_CAP_VPD: 972 printf("VPD"); 973 break; 974 case PCI_CAP_SLOTID: 975 printf("SlotID"); 976 break; 977 case PCI_CAP_MSI: 978 printf("MSI"); 979 break; 980 case PCI_CAP_CPCI_HOTSWAP: 981 printf("CompactPCI Hot-swapping"); 982 break; 983 case PCI_CAP_PCIX: 984 printf("PCI-X"); 985 break; 986 case PCI_CAP_LDT: 987 printf("LDT"); 988 break; 989 case PCI_CAP_VENDSPEC: 990 printf("Vendor-specific"); 991 break; 992 case PCI_CAP_DEBUGPORT: 993 printf("Debug Port"); 994 break; 995 case PCI_CAP_CPCI_RSRCCTL: 996 printf("CompactPCI Resource Control"); 997 break; 998 case PCI_CAP_HOTPLUG: 999 printf("Hot-Plug"); 1000 break; 1001 case PCI_CAP_AGP8: 1002 printf("AGP 8x"); 1003 break; 1004 case PCI_CAP_SECURE: 1005 printf("Secure Device"); 1006 break; 1007 case PCI_CAP_PCIEXPRESS: 1008 printf("PCI Express"); 1009 pcie_off = off; 1010 break; 1011 case PCI_CAP_MSIX: 1012 printf("MSI-X"); 1013 break; 1014 default: 1015 printf("unknown"); 1016 } 1017 printf(")\n"); 1018 } 1019 if (pcipm_off != -1) 1020 pci_conf_print_pcipm_cap(regs, pcipm_off); 1021 if (pcie_off != -1) 1022 pci_conf_print_pcie_cap(regs, pcie_off); 1023 } 1024 1025 /* Print the Secondary Status Register. */ 1026 static void 1027 pci_conf_print_ssr(pcireg_t rval) 1028 { 1029 pcireg_t devsel; 1030 1031 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 1032 onoff("66 MHz capable", __BIT(5)); 1033 onoff("User Definable Features (UDF) support", __BIT(6)); 1034 onoff("Fast back-to-back capable", __BIT(7)); 1035 onoff("Data parity error detected", __BIT(8)); 1036 1037 printf(" DEVSEL timing: "); 1038 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 1039 switch (devsel) { 1040 case 0: 1041 printf("fast"); 1042 break; 1043 case 1: 1044 printf("medium"); 1045 break; 1046 case 2: 1047 printf("slow"); 1048 break; 1049 default: 1050 printf("unknown/reserved"); /* XXX */ 1051 break; 1052 } 1053 printf(" (0x%x)\n", devsel); 1054 1055 onoff("Signalled target abort", __BIT(11)); 1056 onoff("Received target abort", __BIT(12)); 1057 onoff("Received master abort", __BIT(13)); 1058 onoff("Received system error", __BIT(14)); 1059 onoff("Detected parity error", __BIT(15)); 1060 } 1061 1062 static void 1063 pci_conf_print_type1( 1064 #ifdef _KERNEL 1065 pci_chipset_tag_t pc, pcitag_t tag, 1066 #endif 1067 const pcireg_t *regs 1068 #ifdef _KERNEL 1069 , int sizebars 1070 #endif 1071 ) 1072 { 1073 int off, width; 1074 pcireg_t rval; 1075 1076 /* 1077 * XXX these need to be printed in more detail, need to be 1078 * XXX checked against specs/docs, etc. 1079 * 1080 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 1081 * Bridge chip documentation, and may not be correct with 1082 * respect to various standards. (XXX) 1083 */ 1084 1085 for (off = 0x10; off < 0x18; off += width) { 1086 #ifdef _KERNEL 1087 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 1088 #else 1089 width = pci_conf_print_bar(regs, off, NULL); 1090 #endif 1091 } 1092 1093 printf(" Primary bus number: 0x%02x\n", 1094 (regs[o2i(0x18)] >> 0) & 0xff); 1095 printf(" Secondary bus number: 0x%02x\n", 1096 (regs[o2i(0x18)] >> 8) & 0xff); 1097 printf(" Subordinate bus number: 0x%02x\n", 1098 (regs[o2i(0x18)] >> 16) & 0xff); 1099 printf(" Secondary bus latency timer: 0x%02x\n", 1100 (regs[o2i(0x18)] >> 24) & 0xff); 1101 1102 pci_conf_print_ssr(__SHIFTOUT(regs[o2i(0x1c)], __BITS(31, 16))); 1103 1104 /* XXX Print more prettily */ 1105 printf(" I/O region:\n"); 1106 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 1107 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 1108 printf(" base upper 16 bits register: 0x%04x\n", 1109 (regs[o2i(0x30)] >> 0) & 0xffff); 1110 printf(" limit upper 16 bits register: 0x%04x\n", 1111 (regs[o2i(0x30)] >> 16) & 0xffff); 1112 1113 /* XXX Print more prettily */ 1114 printf(" Memory region:\n"); 1115 printf(" base register: 0x%04x\n", 1116 (regs[o2i(0x20)] >> 0) & 0xffff); 1117 printf(" limit register: 0x%04x\n", 1118 (regs[o2i(0x20)] >> 16) & 0xffff); 1119 1120 /* XXX Print more prettily */ 1121 printf(" Prefetchable memory region:\n"); 1122 printf(" base register: 0x%04x\n", 1123 (regs[o2i(0x24)] >> 0) & 0xffff); 1124 printf(" limit register: 0x%04x\n", 1125 (regs[o2i(0x24)] >> 16) & 0xffff); 1126 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 1127 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 1128 1129 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1130 printf(" Capability list pointer: 0x%02x\n", 1131 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 1132 else 1133 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 1134 1135 /* XXX */ 1136 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 1137 1138 printf(" Interrupt line: 0x%02x\n", 1139 (regs[o2i(0x3c)] >> 0) & 0xff); 1140 printf(" Interrupt pin: 0x%02x ", 1141 (regs[o2i(0x3c)] >> 8) & 0xff); 1142 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1143 case PCI_INTERRUPT_PIN_NONE: 1144 printf("(none)"); 1145 break; 1146 case PCI_INTERRUPT_PIN_A: 1147 printf("(pin A)"); 1148 break; 1149 case PCI_INTERRUPT_PIN_B: 1150 printf("(pin B)"); 1151 break; 1152 case PCI_INTERRUPT_PIN_C: 1153 printf("(pin C)"); 1154 break; 1155 case PCI_INTERRUPT_PIN_D: 1156 printf("(pin D)"); 1157 break; 1158 default: 1159 printf("(? ? ?)"); 1160 break; 1161 } 1162 printf("\n"); 1163 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1164 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 1165 onoff("Parity error response", 0x0001); 1166 onoff("Secondary SERR forwarding", 0x0002); 1167 onoff("ISA enable", 0x0004); 1168 onoff("VGA enable", 0x0008); 1169 onoff("Master abort reporting", 0x0020); 1170 onoff("Secondary bus reset", 0x0040); 1171 onoff("Fast back-to-back capable", 0x0080); 1172 } 1173 1174 static void 1175 pci_conf_print_type2( 1176 #ifdef _KERNEL 1177 pci_chipset_tag_t pc, pcitag_t tag, 1178 #endif 1179 const pcireg_t *regs 1180 #ifdef _KERNEL 1181 , int sizebars 1182 #endif 1183 ) 1184 { 1185 pcireg_t rval; 1186 1187 /* 1188 * XXX these need to be printed in more detail, need to be 1189 * XXX checked against specs/docs, etc. 1190 * 1191 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 1192 * controller chip documentation, and may not be correct with 1193 * respect to various standards. (XXX) 1194 */ 1195 1196 #ifdef _KERNEL 1197 pci_conf_print_bar(pc, tag, regs, 0x10, 1198 "CardBus socket/ExCA registers", sizebars); 1199 #else 1200 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 1201 #endif 1202 1203 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1204 printf(" Capability list pointer: 0x%02x\n", 1205 PCI_CAPLIST_PTR(regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)])); 1206 else 1207 printf(" Reserved @ 0x14: 0x%04" PRIxMAX "\n", 1208 __SHIFTOUT(regs[o2i(0x14)], __BITS(15, 0))); 1209 pci_conf_print_ssr(__SHIFTOUT(regs[o2i(0x14)], __BITS(31, 16))); 1210 1211 printf(" PCI bus number: 0x%02x\n", 1212 (regs[o2i(0x18)] >> 0) & 0xff); 1213 printf(" CardBus bus number: 0x%02x\n", 1214 (regs[o2i(0x18)] >> 8) & 0xff); 1215 printf(" Subordinate bus number: 0x%02x\n", 1216 (regs[o2i(0x18)] >> 16) & 0xff); 1217 printf(" CardBus latency timer: 0x%02x\n", 1218 (regs[o2i(0x18)] >> 24) & 0xff); 1219 1220 /* XXX Print more prettily */ 1221 printf(" CardBus memory region 0:\n"); 1222 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1223 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1224 printf(" CardBus memory region 1:\n"); 1225 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1226 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1227 printf(" CardBus I/O region 0:\n"); 1228 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1229 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1230 printf(" CardBus I/O region 1:\n"); 1231 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1232 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1233 1234 printf(" Interrupt line: 0x%02x\n", 1235 (regs[o2i(0x3c)] >> 0) & 0xff); 1236 printf(" Interrupt pin: 0x%02x ", 1237 (regs[o2i(0x3c)] >> 8) & 0xff); 1238 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1239 case PCI_INTERRUPT_PIN_NONE: 1240 printf("(none)"); 1241 break; 1242 case PCI_INTERRUPT_PIN_A: 1243 printf("(pin A)"); 1244 break; 1245 case PCI_INTERRUPT_PIN_B: 1246 printf("(pin B)"); 1247 break; 1248 case PCI_INTERRUPT_PIN_C: 1249 printf("(pin C)"); 1250 break; 1251 case PCI_INTERRUPT_PIN_D: 1252 printf("(pin D)"); 1253 break; 1254 default: 1255 printf("(? ? ?)"); 1256 break; 1257 } 1258 printf("\n"); 1259 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1260 printf(" Bridge control register: 0x%04x\n", rval); 1261 onoff("Parity error response", __BIT(0)); 1262 onoff("SERR# enable", __BIT(1)); 1263 onoff("ISA enable", __BIT(2)); 1264 onoff("VGA enable", __BIT(3)); 1265 onoff("Master abort mode", __BIT(5)); 1266 onoff("Secondary (CardBus) bus reset", __BIT(6)); 1267 onoff("Functional interrupts routed by ExCA registers", __BIT(7)); 1268 onoff("Memory window 0 prefetchable", __BIT(8)); 1269 onoff("Memory window 1 prefetchable", __BIT(9)); 1270 onoff("Write posting enable", __BIT(10)); 1271 1272 rval = regs[o2i(0x40)]; 1273 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1274 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1275 1276 #ifdef _KERNEL 1277 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1278 sizebars); 1279 #else 1280 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 1281 #endif 1282 } 1283 1284 void 1285 pci_conf_print( 1286 #ifdef _KERNEL 1287 pci_chipset_tag_t pc, pcitag_t tag, 1288 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 1289 #else 1290 int pcifd, u_int bus, u_int dev, u_int func 1291 #endif 1292 ) 1293 { 1294 pcireg_t regs[o2i(256)]; 1295 int off, capoff, endoff, hdrtype; 1296 const char *typename; 1297 #ifdef _KERNEL 1298 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1299 int sizebars; 1300 #else 1301 void (*typeprintfn)(const pcireg_t *); 1302 #endif 1303 1304 printf("PCI configuration registers:\n"); 1305 1306 for (off = 0; off < 256; off += 4) { 1307 #ifdef _KERNEL 1308 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1309 #else 1310 if (pcibus_conf_read(pcifd, bus, dev, func, off, 1311 ®s[o2i(off)]) == -1) 1312 regs[o2i(off)] = 0; 1313 #endif 1314 } 1315 1316 #ifdef _KERNEL 1317 sizebars = 1; 1318 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1319 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1320 sizebars = 0; 1321 #endif 1322 1323 /* common header */ 1324 printf(" Common header:\n"); 1325 pci_conf_print_regs(regs, 0, 16); 1326 1327 printf("\n"); 1328 #ifdef _KERNEL 1329 pci_conf_print_common(pc, tag, regs); 1330 #else 1331 pci_conf_print_common(regs); 1332 #endif 1333 printf("\n"); 1334 1335 /* type-dependent header */ 1336 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1337 switch (hdrtype) { /* XXX make a table, eventually */ 1338 case 0: 1339 /* Standard device header */ 1340 typename = "\"normal\" device"; 1341 typeprintfn = &pci_conf_print_type0; 1342 capoff = PCI_CAPLISTPTR_REG; 1343 endoff = 64; 1344 break; 1345 case 1: 1346 /* PCI-PCI bridge header */ 1347 typename = "PCI-PCI bridge"; 1348 typeprintfn = &pci_conf_print_type1; 1349 capoff = PCI_CAPLISTPTR_REG; 1350 endoff = 64; 1351 break; 1352 case 2: 1353 /* PCI-CardBus bridge header */ 1354 typename = "PCI-CardBus bridge"; 1355 typeprintfn = &pci_conf_print_type2; 1356 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 1357 endoff = 72; 1358 break; 1359 default: 1360 typename = NULL; 1361 typeprintfn = 0; 1362 capoff = -1; 1363 endoff = 64; 1364 break; 1365 } 1366 printf(" Type %d ", hdrtype); 1367 if (typename != NULL) 1368 printf("(%s) ", typename); 1369 printf("header:\n"); 1370 pci_conf_print_regs(regs, 16, endoff); 1371 printf("\n"); 1372 if (typeprintfn) { 1373 #ifdef _KERNEL 1374 (*typeprintfn)(pc, tag, regs, sizebars); 1375 #else 1376 (*typeprintfn)(regs); 1377 #endif 1378 } else 1379 printf(" Don't know how to pretty-print type %d header.\n", 1380 hdrtype); 1381 printf("\n"); 1382 1383 /* capability list, if present */ 1384 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1385 && (capoff > 0)) { 1386 #ifdef _KERNEL 1387 pci_conf_print_caplist(pc, tag, regs, capoff); 1388 #else 1389 pci_conf_print_caplist(regs, capoff); 1390 #endif 1391 printf("\n"); 1392 } 1393 1394 /* device-dependent header */ 1395 printf(" Device-dependent header:\n"); 1396 pci_conf_print_regs(regs, endoff, 256); 1397 printf("\n"); 1398 #ifdef _KERNEL 1399 if (printfn) 1400 (*printfn)(pc, tag, regs); 1401 else 1402 printf(" Don't know how to pretty-print device-dependent header.\n"); 1403 printf("\n"); 1404 #endif /* _KERNEL */ 1405 } 1406
Indexes created Wed Sep 24 14:09:57 GMT 2025