pci_subr.c revision 1.88
1 /* $NetBSD: pci_subr.c,v 1.88 2011/08/17 00:59:47 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.88 2011/08/17 00:59:47 dyoung Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdbool.h> 58 #include <stdio.h> 59 #endif 60 61 #include <dev/pci/pcireg.h> 62 #ifdef _KERNEL 63 #include <dev/pci/pcivar.h> 64 #endif 65 66 /* 67 * Descriptions of known PCI classes and subclasses. 68 * 69 * Subclasses are described in the same way as classes, but have a 70 * NULL subclass pointer. 71 */ 72 struct pci_class { 73 const char *name; 74 int val; /* as wide as pci_{,sub}class_t */ 75 const struct pci_class *subclasses; 76 }; 77 78 static const struct pci_class pci_subclass_prehistoric[] = { 79 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 80 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 81 { NULL, 0, NULL, }, 82 }; 83 84 static const struct pci_class pci_subclass_mass_storage[] = { 85 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 86 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 87 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 88 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 89 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 90 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, NULL, }, 91 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, NULL, }, 92 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 93 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 94 { NULL, 0, NULL, }, 95 }; 96 97 static const struct pci_class pci_subclass_network[] = { 98 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 99 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 100 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 101 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 102 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 103 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 104 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 105 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 106 { NULL, 0, NULL, }, 107 }; 108 109 static const struct pci_class pci_subclass_display[] = { 110 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, NULL, }, 111 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 112 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 113 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 114 { NULL, 0, NULL, }, 115 }; 116 117 static const struct pci_class pci_subclass_multimedia[] = { 118 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 119 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 120 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 121 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 122 { NULL, 0, NULL, }, 123 }; 124 125 static const struct pci_class pci_subclass_memory[] = { 126 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 127 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 128 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 129 { NULL, 0, NULL, }, 130 }; 131 132 static const struct pci_class pci_subclass_bridge[] = { 133 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 134 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 135 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 136 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 137 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, NULL, }, 138 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 139 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 140 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 141 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 142 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, NULL, }, 143 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 144 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 145 { NULL, 0, NULL, }, 146 }; 147 148 static const struct pci_class pci_subclass_communications[] = { 149 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, NULL, }, 150 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, NULL, }, 151 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL, }, 152 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, NULL, }, 153 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL, }, 154 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL, }, 155 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL, }, 156 { NULL, 0, NULL, }, 157 }; 158 159 static const struct pci_class pci_subclass_system[] = { 160 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, NULL, }, 161 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, NULL, }, 162 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, NULL, }, 163 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, NULL, }, 164 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 165 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 166 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 167 { NULL, 0, NULL, }, 168 }; 169 170 static const struct pci_class pci_subclass_input[] = { 171 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 172 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 173 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 174 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 175 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, NULL, }, 176 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 177 { NULL, 0, NULL, }, 178 }; 179 180 static const struct pci_class pci_subclass_dock[] = { 181 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 182 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 183 { NULL, 0, NULL, }, 184 }; 185 186 static const struct pci_class pci_subclass_processor[] = { 187 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 188 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 189 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 190 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 191 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 192 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 193 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 194 { NULL, 0, NULL, }, 195 }; 196 197 static const struct pci_class pci_subclass_serialbus[] = { 198 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, NULL, }, 199 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 200 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 201 { "USB", PCI_SUBCLASS_SERIALBUS_USB, NULL, }, 202 /* XXX Fiber Channel/_FIBRECHANNEL */ 203 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 204 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 205 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 206 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, NULL, }, 207 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 208 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 209 { NULL, 0, NULL, }, 210 }; 211 212 static const struct pci_class pci_subclass_wireless[] = { 213 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 214 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 215 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 216 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 217 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 218 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 219 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 220 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 221 { NULL, 0, NULL, }, 222 }; 223 224 static const struct pci_class pci_subclass_i2o[] = { 225 { "standard", PCI_SUBCLASS_I2O_STANDARD, NULL, }, 226 { NULL, 0, NULL, }, 227 }; 228 229 static const struct pci_class pci_subclass_satcom[] = { 230 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 231 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 232 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 233 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 234 { NULL, 0, NULL, }, 235 }; 236 237 static const struct pci_class pci_subclass_crypto[] = { 238 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 239 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 240 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 241 { NULL, 0, NULL, }, 242 }; 243 244 static const struct pci_class pci_subclass_dasp[] = { 245 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 246 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 247 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 248 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 249 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 250 { NULL, 0, NULL, }, 251 }; 252 253 static const struct pci_class pci_class[] = { 254 { "prehistoric", PCI_CLASS_PREHISTORIC, 255 pci_subclass_prehistoric, }, 256 { "mass storage", PCI_CLASS_MASS_STORAGE, 257 pci_subclass_mass_storage, }, 258 { "network", PCI_CLASS_NETWORK, 259 pci_subclass_network, }, 260 { "display", PCI_CLASS_DISPLAY, 261 pci_subclass_display, }, 262 { "multimedia", PCI_CLASS_MULTIMEDIA, 263 pci_subclass_multimedia, }, 264 { "memory", PCI_CLASS_MEMORY, 265 pci_subclass_memory, }, 266 { "bridge", PCI_CLASS_BRIDGE, 267 pci_subclass_bridge, }, 268 { "communications", PCI_CLASS_COMMUNICATIONS, 269 pci_subclass_communications, }, 270 { "system", PCI_CLASS_SYSTEM, 271 pci_subclass_system, }, 272 { "input", PCI_CLASS_INPUT, 273 pci_subclass_input, }, 274 { "dock", PCI_CLASS_DOCK, 275 pci_subclass_dock, }, 276 { "processor", PCI_CLASS_PROCESSOR, 277 pci_subclass_processor, }, 278 { "serial bus", PCI_CLASS_SERIALBUS, 279 pci_subclass_serialbus, }, 280 { "wireless", PCI_CLASS_WIRELESS, 281 pci_subclass_wireless, }, 282 { "I2O", PCI_CLASS_I2O, 283 pci_subclass_i2o, }, 284 { "satellite comm", PCI_CLASS_SATCOM, 285 pci_subclass_satcom, }, 286 { "crypto", PCI_CLASS_CRYPTO, 287 pci_subclass_crypto, }, 288 { "DASP", PCI_CLASS_DASP, 289 pci_subclass_dasp, }, 290 { "undefined", PCI_CLASS_UNDEFINED, 291 NULL, }, 292 { NULL, 0, 293 NULL, }, 294 }; 295 296 void pci_load_verbose(void); 297 298 #if defined(_KERNEL) 299 /* 300 * In kernel, these routines are provided and linked via the 301 * pciverbose module. 302 */ 303 const char *pci_findvendor_stub(pcireg_t); 304 const char *pci_findproduct_stub(pcireg_t); 305 306 const char *(*pci_findvendor)(pcireg_t) = pci_findvendor_stub; 307 const char *(*pci_findproduct)(pcireg_t) = pci_findproduct_stub; 308 const char *pci_unmatched = ""; 309 #else 310 /* 311 * For userland we just set the vectors here. 312 */ 313 const char *(*pci_findvendor)(pcireg_t id_reg) = pci_findvendor_real; 314 const char *(*pci_findproduct)(pcireg_t id_reg) = pci_findproduct_real; 315 const char *pci_unmatched = "unmatched "; 316 #endif 317 318 int pciverbose_loaded = 0; 319 320 #if defined(_KERNEL) 321 /* 322 * Routine to load the pciverbose kernel module as needed 323 */ 324 void pci_load_verbose(void) 325 { 326 if (pciverbose_loaded == 0) 327 module_autoload("pciverbose", MODULE_CLASS_MISC); 328 } 329 330 const char *pci_findvendor_stub(pcireg_t id_reg) 331 { 332 pci_load_verbose(); 333 if (pciverbose_loaded) 334 return pci_findvendor(id_reg); 335 else 336 return NULL; 337 } 338 339 const char *pci_findproduct_stub(pcireg_t id_reg) 340 { 341 pci_load_verbose(); 342 if (pciverbose_loaded) 343 return pci_findproduct(id_reg); 344 else 345 return NULL; 346 } 347 #endif 348 349 void 350 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 351 size_t l) 352 { 353 pci_vendor_id_t vendor; 354 pci_product_id_t product; 355 pci_class_t class; 356 pci_subclass_t subclass; 357 pci_interface_t interface; 358 pci_revision_t revision; 359 const char *unmatched = pci_unmatched; 360 const char *vendor_namep, *product_namep; 361 const struct pci_class *classp, *subclassp; 362 char *ep; 363 364 ep = cp + l; 365 366 vendor = PCI_VENDOR(id_reg); 367 product = PCI_PRODUCT(id_reg); 368 369 class = PCI_CLASS(class_reg); 370 subclass = PCI_SUBCLASS(class_reg); 371 interface = PCI_INTERFACE(class_reg); 372 revision = PCI_REVISION(class_reg); 373 374 vendor_namep = pci_findvendor(id_reg); 375 product_namep = pci_findproduct(id_reg); 376 377 classp = pci_class; 378 while (classp->name != NULL) { 379 if (class == classp->val) 380 break; 381 classp++; 382 } 383 384 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 385 while (subclassp && subclassp->name != NULL) { 386 if (subclass == subclassp->val) 387 break; 388 subclassp++; 389 } 390 391 if (vendor_namep == NULL) 392 cp += snprintf(cp, ep - cp, "%svendor 0x%04x product 0x%04x", 393 unmatched, vendor, product); 394 else if (product_namep != NULL) 395 cp += snprintf(cp, ep - cp, "%s %s", vendor_namep, 396 product_namep); 397 else 398 cp += snprintf(cp, ep - cp, "%s product 0x%04x", 399 vendor_namep, product); 400 if (showclass) { 401 cp += snprintf(cp, ep - cp, " ("); 402 if (classp->name == NULL) 403 cp += snprintf(cp, ep - cp, 404 "class 0x%02x, subclass 0x%02x", class, subclass); 405 else { 406 if (subclassp == NULL || subclassp->name == NULL) 407 cp += snprintf(cp, ep - cp, 408 "%s, subclass 0x%02x", 409 classp->name, subclass); 410 else 411 cp += snprintf(cp, ep - cp, "%s %s", 412 subclassp->name, classp->name); 413 } 414 if (interface != 0) 415 cp += snprintf(cp, ep - cp, ", interface 0x%02x", 416 interface); 417 if (revision != 0) 418 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 419 revision); 420 cp += snprintf(cp, ep - cp, ")"); 421 } 422 } 423 424 /* 425 * Print out most of the PCI configuration registers. Typically used 426 * in a device attach routine like this: 427 * 428 * #ifdef MYDEV_DEBUG 429 * printf("%s: ", device_xname(&sc->sc_dev)); 430 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 431 * #endif 432 */ 433 434 #define i2o(i) ((i) * 4) 435 #define o2i(o) ((o) / 4) 436 #define onoff2(str, bit, onstr, offstr) \ 437 printf(" %s: %s\n", (str), (rval & (bit)) ? onstr : offstr); 438 #define onoff(str, bit) onoff2(str, bit, "on", "off") 439 440 static void 441 pci_conf_print_common( 442 #ifdef _KERNEL 443 pci_chipset_tag_t pc, pcitag_t tag, 444 #endif 445 const pcireg_t *regs) 446 { 447 const char *name; 448 const struct pci_class *classp, *subclassp; 449 pcireg_t rval; 450 451 rval = regs[o2i(PCI_ID_REG)]; 452 name = pci_findvendor(rval); 453 if (name) 454 printf(" Vendor Name: %s (0x%04x)\n", name, 455 PCI_VENDOR(rval)); 456 else 457 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 458 name = pci_findproduct(rval); 459 if (name) 460 printf(" Device Name: %s (0x%04x)\n", name, 461 PCI_PRODUCT(rval)); 462 else 463 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 464 465 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 466 467 printf(" Command register: 0x%04x\n", rval & 0xffff); 468 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 469 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 470 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 471 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 472 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 473 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 474 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 475 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 476 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 477 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 478 onoff("Interrupt disable", PCI_COMMAND_INTERRUPT_DISABLE); 479 480 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 481 onoff2("Interrupt status", PCI_STATUS_INT_STATUS, "active", "inactive"); 482 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 483 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 484 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 485 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 486 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 487 488 printf(" DEVSEL timing: "); 489 switch (rval & PCI_STATUS_DEVSEL_MASK) { 490 case PCI_STATUS_DEVSEL_FAST: 491 printf("fast"); 492 break; 493 case PCI_STATUS_DEVSEL_MEDIUM: 494 printf("medium"); 495 break; 496 case PCI_STATUS_DEVSEL_SLOW: 497 printf("slow"); 498 break; 499 default: 500 printf("unknown/reserved"); /* XXX */ 501 break; 502 } 503 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 504 505 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 506 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 507 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 508 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 509 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 510 511 rval = regs[o2i(PCI_CLASS_REG)]; 512 for (classp = pci_class; classp->name != NULL; classp++) { 513 if (PCI_CLASS(rval) == classp->val) 514 break; 515 } 516 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 517 while (subclassp && subclassp->name != NULL) { 518 if (PCI_SUBCLASS(rval) == subclassp->val) 519 break; 520 subclassp++; 521 } 522 if (classp->name != NULL) { 523 printf(" Class Name: %s (0x%02x)\n", classp->name, 524 PCI_CLASS(rval)); 525 if (subclassp != NULL && subclassp->name != NULL) 526 printf(" Subclass Name: %s (0x%02x)\n", 527 subclassp->name, PCI_SUBCLASS(rval)); 528 else 529 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 530 } else { 531 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 532 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 533 } 534 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 535 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 536 537 rval = regs[o2i(PCI_BHLC_REG)]; 538 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 539 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 540 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 541 PCI_HDRTYPE(rval)); 542 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 543 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 544 } 545 546 static int 547 pci_conf_print_bar( 548 #ifdef _KERNEL 549 pci_chipset_tag_t pc, pcitag_t tag, 550 #endif 551 const pcireg_t *regs, int reg, const char *name 552 #ifdef _KERNEL 553 , int sizebar 554 #endif 555 ) 556 { 557 int width; 558 pcireg_t rval, rval64h; 559 #ifdef _KERNEL 560 int s; 561 pcireg_t mask, mask64h; 562 #endif 563 564 width = 4; 565 566 /* 567 * Section 6.2.5.1, `Address Maps', tells us that: 568 * 569 * 1) The builtin software should have already mapped the 570 * device in a reasonable way. 571 * 572 * 2) A device which wants 2^n bytes of memory will hardwire 573 * the bottom n bits of the address to 0. As recommended, 574 * we write all 1s and see what we get back. 575 */ 576 577 rval = regs[o2i(reg)]; 578 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 579 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 580 rval64h = regs[o2i(reg + 4)]; 581 width = 8; 582 } else 583 rval64h = 0; 584 585 #ifdef _KERNEL 586 /* XXX don't size unknown memory type? */ 587 if (rval != 0 && sizebar) { 588 /* 589 * The following sequence seems to make some devices 590 * (e.g. host bus bridges, which don't normally 591 * have their space mapped) very unhappy, to 592 * the point of crashing the system. 593 * 594 * Therefore, if the mapping register is zero to 595 * start out with, don't bother trying. 596 */ 597 s = splhigh(); 598 pci_conf_write(pc, tag, reg, 0xffffffff); 599 mask = pci_conf_read(pc, tag, reg); 600 pci_conf_write(pc, tag, reg, rval); 601 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 602 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 603 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 604 mask64h = pci_conf_read(pc, tag, reg + 4); 605 pci_conf_write(pc, tag, reg + 4, rval64h); 606 } else 607 mask64h = 0; 608 splx(s); 609 } else 610 mask = mask64h = 0; 611 #endif /* _KERNEL */ 612 613 printf(" Base address register at 0x%02x", reg); 614 if (name) 615 printf(" (%s)", name); 616 printf("\n "); 617 if (rval == 0) { 618 printf("not implemented(?)\n"); 619 return width; 620 } 621 printf("type: "); 622 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 623 const char *type, *prefetch; 624 625 switch (PCI_MAPREG_MEM_TYPE(rval)) { 626 case PCI_MAPREG_MEM_TYPE_32BIT: 627 type = "32-bit"; 628 break; 629 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 630 type = "32-bit-1M"; 631 break; 632 case PCI_MAPREG_MEM_TYPE_64BIT: 633 type = "64-bit"; 634 break; 635 default: 636 type = "unknown (XXX)"; 637 break; 638 } 639 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 640 prefetch = ""; 641 else 642 prefetch = "non"; 643 printf("%s %sprefetchable memory\n", type, prefetch); 644 switch (PCI_MAPREG_MEM_TYPE(rval)) { 645 case PCI_MAPREG_MEM_TYPE_64BIT: 646 printf(" base: 0x%016llx, ", 647 PCI_MAPREG_MEM64_ADDR( 648 ((((long long) rval64h) << 32) | rval))); 649 #ifdef _KERNEL 650 if (sizebar) 651 printf("size: 0x%016llx", 652 PCI_MAPREG_MEM64_SIZE( 653 ((((long long) mask64h) << 32) | mask))); 654 else 655 #endif /* _KERNEL */ 656 printf("not sized"); 657 printf("\n"); 658 break; 659 case PCI_MAPREG_MEM_TYPE_32BIT: 660 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 661 default: 662 printf(" base: 0x%08x, ", 663 PCI_MAPREG_MEM_ADDR(rval)); 664 #ifdef _KERNEL 665 if (sizebar) 666 printf("size: 0x%08x", 667 PCI_MAPREG_MEM_SIZE(mask)); 668 else 669 #endif /* _KERNEL */ 670 printf("not sized"); 671 printf("\n"); 672 break; 673 } 674 } else { 675 #ifdef _KERNEL 676 if (sizebar) 677 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 678 #endif /* _KERNEL */ 679 printf("i/o\n"); 680 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 681 #ifdef _KERNEL 682 if (sizebar) 683 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 684 else 685 #endif /* _KERNEL */ 686 printf("not sized"); 687 printf("\n"); 688 } 689 690 return width; 691 } 692 693 static void 694 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 695 { 696 int off, needaddr, neednl; 697 698 needaddr = 1; 699 neednl = 0; 700 for (off = first; off < pastlast; off += 4) { 701 if ((off % 16) == 0 || needaddr) { 702 printf(" 0x%02x:", off); 703 needaddr = 0; 704 } 705 printf(" 0x%08x", regs[o2i(off)]); 706 neednl = 1; 707 if ((off % 16) == 12) { 708 printf("\n"); 709 neednl = 0; 710 } 711 } 712 if (neednl) 713 printf("\n"); 714 } 715 716 static void 717 pci_conf_print_type0( 718 #ifdef _KERNEL 719 pci_chipset_tag_t pc, pcitag_t tag, 720 #endif 721 const pcireg_t *regs 722 #ifdef _KERNEL 723 , int sizebars 724 #endif 725 ) 726 { 727 int off, width; 728 pcireg_t rval; 729 730 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 731 #ifdef _KERNEL 732 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 733 #else 734 width = pci_conf_print_bar(regs, off, NULL); 735 #endif 736 } 737 738 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 739 740 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 741 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 742 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 743 744 /* XXX */ 745 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 746 747 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 748 printf(" Capability list pointer: 0x%02x\n", 749 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 750 else 751 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 752 753 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 754 755 rval = regs[o2i(PCI_INTERRUPT_REG)]; 756 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 757 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 758 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 759 switch (PCI_INTERRUPT_PIN(rval)) { 760 case PCI_INTERRUPT_PIN_NONE: 761 printf("(none)"); 762 break; 763 case PCI_INTERRUPT_PIN_A: 764 printf("(pin A)"); 765 break; 766 case PCI_INTERRUPT_PIN_B: 767 printf("(pin B)"); 768 break; 769 case PCI_INTERRUPT_PIN_C: 770 printf("(pin C)"); 771 break; 772 case PCI_INTERRUPT_PIN_D: 773 printf("(pin D)"); 774 break; 775 default: 776 printf("(? ? ?)"); 777 break; 778 } 779 printf("\n"); 780 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 781 } 782 783 static void 784 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 785 { 786 bool check_slot = false; 787 788 printf("\n PCI Express Capabilities Register\n"); 789 printf(" Capability version: %x\n", 790 (unsigned int)((regs[o2i(capoff)] & 0x000f0000) >> 16)); 791 printf(" Device type: "); 792 switch ((regs[o2i(capoff)] & 0x00f00000) >> 20) { 793 case 0x0: 794 printf("PCI Express Endpoint device\n"); 795 break; 796 case 0x1: 797 printf("Legacy PCI Express Endpoint device\n"); 798 break; 799 case 0x4: 800 printf("Root Port of PCI Express Root Complex\n"); 801 check_slot = true; 802 break; 803 case 0x5: 804 printf("Upstream Port of PCI Express Switch\n"); 805 break; 806 case 0x6: 807 printf("Downstream Port of PCI Express Switch\n"); 808 check_slot = true; 809 break; 810 case 0x7: 811 printf("PCI Express to PCI/PCI-X Bridge\n"); 812 break; 813 case 0x8: 814 printf("PCI/PCI-X to PCI Express Bridge\n"); 815 break; 816 default: 817 printf("unknown\n"); 818 break; 819 } 820 if (check_slot && (regs[o2i(capoff)] & 0x01000000) != 0) 821 printf(" Slot implemented\n"); 822 printf(" Interrupt Message Number: %x\n", 823 (unsigned int)((regs[o2i(capoff)] & 0x4e000000) >> 27)); 824 printf(" Link Capabilities Register: 0x%08x\n", 825 regs[o2i(capoff + 0x0c)]); 826 printf(" Maximum Link Speed: "); 827 if ((regs[o2i(capoff + 0x0c)] & 0x000f) != 1) { 828 printf("unknown %u value\n", 829 (regs[o2i(capoff + 0x0c)] & 0x000f)); 830 } else { 831 printf("2.5Gb/s\n"); 832 } 833 printf(" Maximum Link Width: x%u lanes\n", 834 (regs[o2i(capoff + 0x0c)] & 0x03f0) >> 4); 835 printf(" Port Number: %u\n", regs[o2i(capoff + 0x0c)] >> 24); 836 printf(" Link Status Register: 0x%04x\n", 837 regs[o2i(capoff + 0x10)] >> 16); 838 printf(" Negotiated Link Speed: "); 839 if (((regs[o2i(capoff + 0x10)] >> 16) & 0x000f) != 1) { 840 printf("unknown %u value\n", 841 (regs[o2i(capoff + 0x10)] >> 16) & 0x000f); 842 } else { 843 printf("2.5Gb/s\n"); 844 } 845 printf(" Negotiated Link Width: x%u lanes\n", 846 (regs[o2i(capoff + 0x10)] >> 20) & 0x003f); 847 if ((regs[o2i(capoff + 0x18)] & 0x07ff) != 0) { 848 printf(" Slot Control Register:\n"); 849 if ((regs[o2i(capoff + 0x18)] & 0x0001) != 0) 850 printf(" Attention Button Pressed Enabled\n"); 851 if ((regs[o2i(capoff + 0x18)] & 0x0002) != 0) 852 printf(" Power Fault Detected Enabled\n"); 853 if ((regs[o2i(capoff + 0x18)] & 0x0004) != 0) 854 printf(" MRL Sensor Changed Enabled\n"); 855 if ((regs[o2i(capoff + 0x18)] & 0x0008) != 0) 856 printf(" Presense Detected Changed Enabled\n"); 857 if ((regs[o2i(capoff + 0x18)] & 0x0010) != 0) 858 printf(" Command Completed Interrupt Enabled\n"); 859 if ((regs[o2i(capoff + 0x18)] & 0x0020) != 0) 860 printf(" Hot-Plug Interrupt Enabled\n"); 861 printf(" Attention Indicator Control: "); 862 switch ((regs[o2i(capoff + 0x18)] & 0x00c0) >> 6) { 863 case 0x0: 864 printf("reserved\n"); 865 break; 866 case 0x1: 867 printf("on\n"); 868 break; 869 case 0x2: 870 printf("blink\n"); 871 break; 872 case 0x3: 873 printf("off\n"); 874 break; 875 } 876 printf(" Power Indicator Control: "); 877 switch ((regs[o2i(capoff + 0x18)] & 0x0300) >> 8) { 878 case 0x0: 879 printf("reserved\n"); 880 break; 881 case 0x1: 882 printf("on\n"); 883 break; 884 case 0x2: 885 printf("blink\n"); 886 break; 887 case 0x3: 888 printf("off\n"); 889 break; 890 } 891 printf(" Power Controller Control: "); 892 if ((regs[o2i(capoff + 0x18)] & 0x0400) != 0) 893 printf("off\n"); 894 else 895 printf("on\n"); 896 } 897 } 898 899 static const char * 900 pci_conf_print_pcipm_cap_aux(uint16_t caps) 901 { 902 switch ((caps >> 6) & 7) { 903 case 0: return "self-powered"; 904 case 1: return "55 mA"; 905 case 2: return "100 mA"; 906 case 3: return "160 mA"; 907 case 4: return "220 mA"; 908 case 5: return "270 mA"; 909 case 6: return "320 mA"; 910 case 7: 911 default: return "375 mA"; 912 } 913 } 914 915 static const char * 916 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 917 { 918 static const char unk[] = "unknown"; 919 static const char *pmrev[8] = { 920 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 921 }; 922 if (val > 7) 923 return unk; 924 return pmrev[val]; 925 } 926 927 static void 928 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 929 { 930 uint16_t caps, pmcsr; 931 932 caps = regs[o2i(capoff)] >> 16; 933 pmcsr = regs[o2i(capoff + 0x04)] & 0xffff; 934 935 printf("\n PCI Power Management Capabilities Register\n"); 936 937 printf(" Capabilities register: 0x%04x\n", caps); 938 printf(" Version: %s\n", 939 pci_conf_print_pcipm_cap_pmrev(caps & 0x3)); 940 printf(" PME# clock: %s\n", caps & 0x4 ? "on" : "off"); 941 printf(" Device specific initialization: %s\n", 942 caps & 0x20 ? "on" : "off"); 943 printf(" 3.3V auxiliary current: %s\n", 944 pci_conf_print_pcipm_cap_aux(caps)); 945 printf(" D1 power management state support: %s\n", 946 (caps >> 9) & 1 ? "on" : "off"); 947 printf(" D2 power management state support: %s\n", 948 (caps >> 10) & 1 ? "on" : "off"); 949 printf(" PME# support: 0x%02x\n", caps >> 11); 950 951 printf(" Control/status register: 0x%04x\n", pmcsr); 952 printf(" Power state: D%d\n", pmcsr & 3); 953 printf(" PCI Express reserved: %s\n", 954 (pmcsr >> 2) & 1 ? "on" : "off"); 955 printf(" No soft reset: %s\n", (pmcsr >> 3) & 1 ? "on" : "off"); 956 printf(" PME# assertion %sabled\n", 957 (pmcsr >> 8) & 1 ? "en" : "dis"); 958 printf(" PME# status: %s\n", (pmcsr >> 15) ? "on" : "off"); 959 } 960 961 static void 962 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 963 { 964 uint32_t ctl, mmc, mme; 965 966 regs += o2i(capoff); 967 ctl = *regs++; 968 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 969 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 970 971 printf("\n PCI Message Signaled Interrupt\n"); 972 973 printf(" Message Control register: 0x%04x\n", ctl >> 16); 974 printf(" MSI Enabled: %s\n", 975 ctl & PCI_MSI_CTL_MSI_ENABLE ? "yes" : "no"); 976 printf(" Multiple Message Capable: %s (%d vector%s)\n", 977 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 978 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 979 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 980 printf(" 64 Bit Address Capable: %s\n", 981 ctl & PCI_MSI_CTL_64BIT_ADDR ? "yes" : "no"); 982 printf(" Per-Vector Masking Capable: %s\n", 983 ctl & PCI_MSI_CTL_PERVEC_MASK ? "yes" : "no"); 984 printf(" Message Address %sregister: 0x%08x\n", 985 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 986 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 987 printf(" Message Address %sregister: 0x%08x\n", 988 "(upper) ", *regs++); 989 } 990 printf(" Message Data register: 0x%08x\n", *regs++); 991 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 992 printf(" Vector Mask register: 0x%08x\n", *regs++); 993 printf(" Vector Pending register: 0x%08x\n", *regs++); 994 } 995 } 996 static void 997 pci_conf_print_caplist( 998 #ifdef _KERNEL 999 pci_chipset_tag_t pc, pcitag_t tag, 1000 #endif 1001 const pcireg_t *regs, int capoff) 1002 { 1003 int off; 1004 pcireg_t rval; 1005 int pcie_off = -1, pcipm_off = -1, msi_off = -1; 1006 1007 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1008 off != 0; 1009 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 1010 rval = regs[o2i(off)]; 1011 printf(" Capability register at 0x%02x\n", off); 1012 1013 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 1014 switch (PCI_CAPLIST_CAP(rval)) { 1015 case PCI_CAP_RESERVED0: 1016 printf("reserved"); 1017 break; 1018 case PCI_CAP_PWRMGMT: 1019 printf("Power Management, rev. %s", 1020 pci_conf_print_pcipm_cap_pmrev((rval >> 0) & 0x07)); 1021 pcipm_off = off; 1022 break; 1023 case PCI_CAP_AGP: 1024 printf("AGP, rev. %d.%d", 1025 PCI_CAP_AGP_MAJOR(rval), 1026 PCI_CAP_AGP_MINOR(rval)); 1027 break; 1028 case PCI_CAP_VPD: 1029 printf("VPD"); 1030 break; 1031 case PCI_CAP_SLOTID: 1032 printf("SlotID"); 1033 break; 1034 case PCI_CAP_MSI: 1035 printf("MSI"); 1036 msi_off = off; 1037 break; 1038 case PCI_CAP_CPCI_HOTSWAP: 1039 printf("CompactPCI Hot-swapping"); 1040 break; 1041 case PCI_CAP_PCIX: 1042 printf("PCI-X"); 1043 break; 1044 case PCI_CAP_LDT: 1045 printf("LDT"); 1046 break; 1047 case PCI_CAP_VENDSPEC: 1048 printf("Vendor-specific"); 1049 break; 1050 case PCI_CAP_DEBUGPORT: 1051 printf("Debug Port"); 1052 break; 1053 case PCI_CAP_CPCI_RSRCCTL: 1054 printf("CompactPCI Resource Control"); 1055 break; 1056 case PCI_CAP_HOTPLUG: 1057 printf("Hot-Plug"); 1058 break; 1059 case PCI_CAP_AGP8: 1060 printf("AGP 8x"); 1061 break; 1062 case PCI_CAP_SECURE: 1063 printf("Secure Device"); 1064 break; 1065 case PCI_CAP_PCIEXPRESS: 1066 printf("PCI Express"); 1067 pcie_off = off; 1068 break; 1069 case PCI_CAP_MSIX: 1070 printf("MSI-X"); 1071 break; 1072 case PCI_CAP_SATA: 1073 printf("SATA"); 1074 break; 1075 case PCI_CAP_PCIAF: 1076 printf("Advanced Features"); 1077 break; 1078 default: 1079 printf("unknown"); 1080 } 1081 printf(")\n"); 1082 } 1083 if (msi_off != -1) 1084 pci_conf_print_msi_cap(regs, msi_off); 1085 if (pcipm_off != -1) 1086 pci_conf_print_pcipm_cap(regs, pcipm_off); 1087 if (pcie_off != -1) 1088 pci_conf_print_pcie_cap(regs, pcie_off); 1089 } 1090 1091 /* Print the Secondary Status Register. */ 1092 static void 1093 pci_conf_print_ssr(pcireg_t rval) 1094 { 1095 pcireg_t devsel; 1096 1097 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 1098 onoff("66 MHz capable", __BIT(5)); 1099 onoff("User Definable Features (UDF) support", __BIT(6)); 1100 onoff("Fast back-to-back capable", __BIT(7)); 1101 onoff("Data parity error detected", __BIT(8)); 1102 1103 printf(" DEVSEL timing: "); 1104 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 1105 switch (devsel) { 1106 case 0: 1107 printf("fast"); 1108 break; 1109 case 1: 1110 printf("medium"); 1111 break; 1112 case 2: 1113 printf("slow"); 1114 break; 1115 default: 1116 printf("unknown/reserved"); /* XXX */ 1117 break; 1118 } 1119 printf(" (0x%x)\n", devsel); 1120 1121 onoff("Signalled target abort", __BIT(11)); 1122 onoff("Received target abort", __BIT(12)); 1123 onoff("Received master abort", __BIT(13)); 1124 onoff("Received system error", __BIT(14)); 1125 onoff("Detected parity error", __BIT(15)); 1126 } 1127 1128 static void 1129 pci_conf_print_type1( 1130 #ifdef _KERNEL 1131 pci_chipset_tag_t pc, pcitag_t tag, 1132 #endif 1133 const pcireg_t *regs 1134 #ifdef _KERNEL 1135 , int sizebars 1136 #endif 1137 ) 1138 { 1139 int off, width; 1140 pcireg_t rval; 1141 1142 /* 1143 * XXX these need to be printed in more detail, need to be 1144 * XXX checked against specs/docs, etc. 1145 * 1146 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 1147 * Bridge chip documentation, and may not be correct with 1148 * respect to various standards. (XXX) 1149 */ 1150 1151 for (off = 0x10; off < 0x18; off += width) { 1152 #ifdef _KERNEL 1153 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 1154 #else 1155 width = pci_conf_print_bar(regs, off, NULL); 1156 #endif 1157 } 1158 1159 printf(" Primary bus number: 0x%02x\n", 1160 (regs[o2i(0x18)] >> 0) & 0xff); 1161 printf(" Secondary bus number: 0x%02x\n", 1162 (regs[o2i(0x18)] >> 8) & 0xff); 1163 printf(" Subordinate bus number: 0x%02x\n", 1164 (regs[o2i(0x18)] >> 16) & 0xff); 1165 printf(" Secondary bus latency timer: 0x%02x\n", 1166 (regs[o2i(0x18)] >> 24) & 0xff); 1167 1168 pci_conf_print_ssr(__SHIFTOUT(regs[o2i(0x1c)], __BITS(31, 16))); 1169 1170 /* XXX Print more prettily */ 1171 printf(" I/O region:\n"); 1172 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 1173 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 1174 printf(" base upper 16 bits register: 0x%04x\n", 1175 (regs[o2i(0x30)] >> 0) & 0xffff); 1176 printf(" limit upper 16 bits register: 0x%04x\n", 1177 (regs[o2i(0x30)] >> 16) & 0xffff); 1178 1179 /* XXX Print more prettily */ 1180 printf(" Memory region:\n"); 1181 printf(" base register: 0x%04x\n", 1182 (regs[o2i(0x20)] >> 0) & 0xffff); 1183 printf(" limit register: 0x%04x\n", 1184 (regs[o2i(0x20)] >> 16) & 0xffff); 1185 1186 /* XXX Print more prettily */ 1187 printf(" Prefetchable memory region:\n"); 1188 printf(" base register: 0x%04x\n", 1189 (regs[o2i(0x24)] >> 0) & 0xffff); 1190 printf(" limit register: 0x%04x\n", 1191 (regs[o2i(0x24)] >> 16) & 0xffff); 1192 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 1193 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 1194 1195 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1196 printf(" Capability list pointer: 0x%02x\n", 1197 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 1198 else 1199 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 1200 1201 /* XXX */ 1202 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 1203 1204 printf(" Interrupt line: 0x%02x\n", 1205 (regs[o2i(0x3c)] >> 0) & 0xff); 1206 printf(" Interrupt pin: 0x%02x ", 1207 (regs[o2i(0x3c)] >> 8) & 0xff); 1208 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1209 case PCI_INTERRUPT_PIN_NONE: 1210 printf("(none)"); 1211 break; 1212 case PCI_INTERRUPT_PIN_A: 1213 printf("(pin A)"); 1214 break; 1215 case PCI_INTERRUPT_PIN_B: 1216 printf("(pin B)"); 1217 break; 1218 case PCI_INTERRUPT_PIN_C: 1219 printf("(pin C)"); 1220 break; 1221 case PCI_INTERRUPT_PIN_D: 1222 printf("(pin D)"); 1223 break; 1224 default: 1225 printf("(? ? ?)"); 1226 break; 1227 } 1228 printf("\n"); 1229 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1230 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 1231 onoff("Parity error response", 0x0001); 1232 onoff("Secondary SERR forwarding", 0x0002); 1233 onoff("ISA enable", 0x0004); 1234 onoff("VGA enable", 0x0008); 1235 onoff("Master abort reporting", 0x0020); 1236 onoff("Secondary bus reset", 0x0040); 1237 onoff("Fast back-to-back capable", 0x0080); 1238 } 1239 1240 static void 1241 pci_conf_print_type2( 1242 #ifdef _KERNEL 1243 pci_chipset_tag_t pc, pcitag_t tag, 1244 #endif 1245 const pcireg_t *regs 1246 #ifdef _KERNEL 1247 , int sizebars 1248 #endif 1249 ) 1250 { 1251 pcireg_t rval; 1252 1253 /* 1254 * XXX these need to be printed in more detail, need to be 1255 * XXX checked against specs/docs, etc. 1256 * 1257 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 1258 * controller chip documentation, and may not be correct with 1259 * respect to various standards. (XXX) 1260 */ 1261 1262 #ifdef _KERNEL 1263 pci_conf_print_bar(pc, tag, regs, 0x10, 1264 "CardBus socket/ExCA registers", sizebars); 1265 #else 1266 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 1267 #endif 1268 1269 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1270 printf(" Capability list pointer: 0x%02x\n", 1271 PCI_CAPLIST_PTR(regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)])); 1272 else 1273 printf(" Reserved @ 0x14: 0x%04" PRIxMAX "\n", 1274 __SHIFTOUT(regs[o2i(0x14)], __BITS(15, 0))); 1275 pci_conf_print_ssr(__SHIFTOUT(regs[o2i(0x14)], __BITS(31, 16))); 1276 1277 printf(" PCI bus number: 0x%02x\n", 1278 (regs[o2i(0x18)] >> 0) & 0xff); 1279 printf(" CardBus bus number: 0x%02x\n", 1280 (regs[o2i(0x18)] >> 8) & 0xff); 1281 printf(" Subordinate bus number: 0x%02x\n", 1282 (regs[o2i(0x18)] >> 16) & 0xff); 1283 printf(" CardBus latency timer: 0x%02x\n", 1284 (regs[o2i(0x18)] >> 24) & 0xff); 1285 1286 /* XXX Print more prettily */ 1287 printf(" CardBus memory region 0:\n"); 1288 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1289 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1290 printf(" CardBus memory region 1:\n"); 1291 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1292 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1293 printf(" CardBus I/O region 0:\n"); 1294 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1295 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1296 printf(" CardBus I/O region 1:\n"); 1297 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1298 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1299 1300 printf(" Interrupt line: 0x%02x\n", 1301 (regs[o2i(0x3c)] >> 0) & 0xff); 1302 printf(" Interrupt pin: 0x%02x ", 1303 (regs[o2i(0x3c)] >> 8) & 0xff); 1304 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1305 case PCI_INTERRUPT_PIN_NONE: 1306 printf("(none)"); 1307 break; 1308 case PCI_INTERRUPT_PIN_A: 1309 printf("(pin A)"); 1310 break; 1311 case PCI_INTERRUPT_PIN_B: 1312 printf("(pin B)"); 1313 break; 1314 case PCI_INTERRUPT_PIN_C: 1315 printf("(pin C)"); 1316 break; 1317 case PCI_INTERRUPT_PIN_D: 1318 printf("(pin D)"); 1319 break; 1320 default: 1321 printf("(? ? ?)"); 1322 break; 1323 } 1324 printf("\n"); 1325 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1326 printf(" Bridge control register: 0x%04x\n", rval); 1327 onoff("Parity error response", __BIT(0)); 1328 onoff("SERR# enable", __BIT(1)); 1329 onoff("ISA enable", __BIT(2)); 1330 onoff("VGA enable", __BIT(3)); 1331 onoff("Master abort mode", __BIT(5)); 1332 onoff("Secondary (CardBus) bus reset", __BIT(6)); 1333 onoff("Functional interrupts routed by ExCA registers", __BIT(7)); 1334 onoff("Memory window 0 prefetchable", __BIT(8)); 1335 onoff("Memory window 1 prefetchable", __BIT(9)); 1336 onoff("Write posting enable", __BIT(10)); 1337 1338 rval = regs[o2i(0x40)]; 1339 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1340 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1341 1342 #ifdef _KERNEL 1343 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1344 sizebars); 1345 #else 1346 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 1347 #endif 1348 } 1349 1350 void 1351 pci_conf_print( 1352 #ifdef _KERNEL 1353 pci_chipset_tag_t pc, pcitag_t tag, 1354 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 1355 #else 1356 int pcifd, u_int bus, u_int dev, u_int func 1357 #endif 1358 ) 1359 { 1360 pcireg_t regs[o2i(256)]; 1361 int off, capoff, endoff, hdrtype; 1362 const char *typename; 1363 #ifdef _KERNEL 1364 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1365 int sizebars; 1366 #else 1367 void (*typeprintfn)(const pcireg_t *); 1368 #endif 1369 1370 printf("PCI configuration registers:\n"); 1371 1372 for (off = 0; off < 256; off += 4) { 1373 #ifdef _KERNEL 1374 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1375 #else 1376 if (pcibus_conf_read(pcifd, bus, dev, func, off, 1377 ®s[o2i(off)]) == -1) 1378 regs[o2i(off)] = 0; 1379 #endif 1380 } 1381 1382 #ifdef _KERNEL 1383 sizebars = 1; 1384 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1385 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1386 sizebars = 0; 1387 #endif 1388 1389 /* common header */ 1390 printf(" Common header:\n"); 1391 pci_conf_print_regs(regs, 0, 16); 1392 1393 printf("\n"); 1394 #ifdef _KERNEL 1395 pci_conf_print_common(pc, tag, regs); 1396 #else 1397 pci_conf_print_common(regs); 1398 #endif 1399 printf("\n"); 1400 1401 /* type-dependent header */ 1402 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1403 switch (hdrtype) { /* XXX make a table, eventually */ 1404 case 0: 1405 /* Standard device header */ 1406 typename = "\"normal\" device"; 1407 typeprintfn = &pci_conf_print_type0; 1408 capoff = PCI_CAPLISTPTR_REG; 1409 endoff = 64; 1410 break; 1411 case 1: 1412 /* PCI-PCI bridge header */ 1413 typename = "PCI-PCI bridge"; 1414 typeprintfn = &pci_conf_print_type1; 1415 capoff = PCI_CAPLISTPTR_REG; 1416 endoff = 64; 1417 break; 1418 case 2: 1419 /* PCI-CardBus bridge header */ 1420 typename = "PCI-CardBus bridge"; 1421 typeprintfn = &pci_conf_print_type2; 1422 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 1423 endoff = 72; 1424 break; 1425 default: 1426 typename = NULL; 1427 typeprintfn = 0; 1428 capoff = -1; 1429 endoff = 64; 1430 break; 1431 } 1432 printf(" Type %d ", hdrtype); 1433 if (typename != NULL) 1434 printf("(%s) ", typename); 1435 printf("header:\n"); 1436 pci_conf_print_regs(regs, 16, endoff); 1437 printf("\n"); 1438 if (typeprintfn) { 1439 #ifdef _KERNEL 1440 (*typeprintfn)(pc, tag, regs, sizebars); 1441 #else 1442 (*typeprintfn)(regs); 1443 #endif 1444 } else 1445 printf(" Don't know how to pretty-print type %d header.\n", 1446 hdrtype); 1447 printf("\n"); 1448 1449 /* capability list, if present */ 1450 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1451 && (capoff > 0)) { 1452 #ifdef _KERNEL 1453 pci_conf_print_caplist(pc, tag, regs, capoff); 1454 #else 1455 pci_conf_print_caplist(regs, capoff); 1456 #endif 1457 printf("\n"); 1458 } 1459 1460 /* device-dependent header */ 1461 printf(" Device-dependent header:\n"); 1462 pci_conf_print_regs(regs, endoff, 256); 1463 printf("\n"); 1464 #ifdef _KERNEL 1465 if (printfn) 1466 (*printfn)(pc, tag, regs); 1467 else 1468 printf(" Don't know how to pretty-print device-dependent header.\n"); 1469 printf("\n"); 1470 #endif /* _KERNEL */ 1471 } 1472
Indexes created Wed Sep 24 05:09:52 GMT 2025