pci_subr.c revision 1.88.2.4
1 /* $NetBSD: pci_subr.c,v 1.88.2.4 2014/05/22 11:40:26 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.88.2.4 2014/05/22 11:40:26 yamt Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdbool.h> 58 #include <stdio.h> 59 #endif 60 61 #include <dev/pci/pcireg.h> 62 #ifdef _KERNEL 63 #include <dev/pci/pcivar.h> 64 #endif 65 66 /* 67 * Descriptions of known PCI classes and subclasses. 68 * 69 * Subclasses are described in the same way as classes, but have a 70 * NULL subclass pointer. 71 */ 72 struct pci_class { 73 const char *name; 74 u_int val; /* as wide as pci_{,sub}class_t */ 75 const struct pci_class *subclasses; 76 }; 77 78 static const struct pci_class pci_subclass_prehistoric[] = { 79 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 80 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 81 { NULL, 0, NULL, }, 82 }; 83 84 static const struct pci_class pci_subclass_mass_storage[] = { 85 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 86 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 87 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 88 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 89 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 90 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, NULL, }, 91 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, NULL, }, 92 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 93 { "NVM", PCI_SUBCLASS_MASS_STORAGE_NVM, NULL, }, 94 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 95 { NULL, 0, NULL, }, 96 }; 97 98 static const struct pci_class pci_subclass_network[] = { 99 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 100 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 101 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 102 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 103 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 104 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 105 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 106 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 107 { NULL, 0, NULL, }, 108 }; 109 110 static const struct pci_class pci_subclass_display[] = { 111 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, NULL, }, 112 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 113 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 114 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 115 { NULL, 0, NULL, }, 116 }; 117 118 static const struct pci_class pci_subclass_multimedia[] = { 119 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 120 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 121 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 122 { "HD audio", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, }, 123 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 124 { NULL, 0, NULL, }, 125 }; 126 127 static const struct pci_class pci_subclass_memory[] = { 128 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 129 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 130 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 131 { NULL, 0, NULL, }, 132 }; 133 134 static const struct pci_class pci_subclass_bridge[] = { 135 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 136 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 137 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 138 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 139 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, NULL, }, 140 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 141 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 142 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 143 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 144 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, NULL, }, 145 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 146 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 147 { NULL, 0, NULL, }, 148 }; 149 150 static const struct pci_class pci_subclass_communications[] = { 151 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, NULL, }, 152 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, NULL, }, 153 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL, }, 154 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, NULL, }, 155 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL, }, 156 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL, }, 157 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL, }, 158 { NULL, 0, NULL, }, 159 }; 160 161 static const struct pci_class pci_subclass_system[] = { 162 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, NULL, }, 163 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, NULL, }, 164 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, NULL, }, 165 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, NULL, }, 166 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 167 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 168 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 169 { NULL, 0, NULL, }, 170 }; 171 172 static const struct pci_class pci_subclass_input[] = { 173 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 174 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 175 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 176 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 177 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, NULL, }, 178 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 179 { NULL, 0, NULL, }, 180 }; 181 182 static const struct pci_class pci_subclass_dock[] = { 183 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 184 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 185 { NULL, 0, NULL, }, 186 }; 187 188 static const struct pci_class pci_subclass_processor[] = { 189 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 190 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 191 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 192 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 193 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 194 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 195 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 196 { NULL, 0, NULL, }, 197 }; 198 199 static const struct pci_class pci_subclass_serialbus[] = { 200 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, NULL, }, 201 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 202 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 203 { "USB", PCI_SUBCLASS_SERIALBUS_USB, NULL, }, 204 /* XXX Fiber Channel/_FIBRECHANNEL */ 205 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 206 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 207 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 208 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, NULL, }, 209 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 210 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 211 { NULL, 0, NULL, }, 212 }; 213 214 static const struct pci_class pci_subclass_wireless[] = { 215 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 216 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 217 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 218 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 219 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 220 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 221 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 222 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 223 { NULL, 0, NULL, }, 224 }; 225 226 static const struct pci_class pci_subclass_i2o[] = { 227 { "standard", PCI_SUBCLASS_I2O_STANDARD, NULL, }, 228 { NULL, 0, NULL, }, 229 }; 230 231 static const struct pci_class pci_subclass_satcom[] = { 232 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 233 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 234 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 235 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 236 { NULL, 0, NULL, }, 237 }; 238 239 static const struct pci_class pci_subclass_crypto[] = { 240 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 241 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 242 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 243 { NULL, 0, NULL, }, 244 }; 245 246 static const struct pci_class pci_subclass_dasp[] = { 247 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 248 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 249 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 250 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 251 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 252 { NULL, 0, NULL, }, 253 }; 254 255 static const struct pci_class pci_class[] = { 256 { "prehistoric", PCI_CLASS_PREHISTORIC, 257 pci_subclass_prehistoric, }, 258 { "mass storage", PCI_CLASS_MASS_STORAGE, 259 pci_subclass_mass_storage, }, 260 { "network", PCI_CLASS_NETWORK, 261 pci_subclass_network, }, 262 { "display", PCI_CLASS_DISPLAY, 263 pci_subclass_display, }, 264 { "multimedia", PCI_CLASS_MULTIMEDIA, 265 pci_subclass_multimedia, }, 266 { "memory", PCI_CLASS_MEMORY, 267 pci_subclass_memory, }, 268 { "bridge", PCI_CLASS_BRIDGE, 269 pci_subclass_bridge, }, 270 { "communications", PCI_CLASS_COMMUNICATIONS, 271 pci_subclass_communications, }, 272 { "system", PCI_CLASS_SYSTEM, 273 pci_subclass_system, }, 274 { "input", PCI_CLASS_INPUT, 275 pci_subclass_input, }, 276 { "dock", PCI_CLASS_DOCK, 277 pci_subclass_dock, }, 278 { "processor", PCI_CLASS_PROCESSOR, 279 pci_subclass_processor, }, 280 { "serial bus", PCI_CLASS_SERIALBUS, 281 pci_subclass_serialbus, }, 282 { "wireless", PCI_CLASS_WIRELESS, 283 pci_subclass_wireless, }, 284 { "I2O", PCI_CLASS_I2O, 285 pci_subclass_i2o, }, 286 { "satellite comm", PCI_CLASS_SATCOM, 287 pci_subclass_satcom, }, 288 { "crypto", PCI_CLASS_CRYPTO, 289 pci_subclass_crypto, }, 290 { "DASP", PCI_CLASS_DASP, 291 pci_subclass_dasp, }, 292 { "undefined", PCI_CLASS_UNDEFINED, 293 NULL, }, 294 { NULL, 0, 295 NULL, }, 296 }; 297 298 void pci_load_verbose(void); 299 300 #if defined(_KERNEL) 301 /* 302 * In kernel, these routines are provided and linked via the 303 * pciverbose module. 304 */ 305 const char *pci_findvendor_stub(pcireg_t); 306 const char *pci_findproduct_stub(pcireg_t); 307 308 const char *(*pci_findvendor)(pcireg_t) = pci_findvendor_stub; 309 const char *(*pci_findproduct)(pcireg_t) = pci_findproduct_stub; 310 const char *pci_unmatched = ""; 311 #else 312 /* 313 * For userland we just set the vectors here. 314 */ 315 const char *(*pci_findvendor)(pcireg_t id_reg) = pci_findvendor_real; 316 const char *(*pci_findproduct)(pcireg_t id_reg) = pci_findproduct_real; 317 const char *pci_unmatched = "unmatched "; 318 #endif 319 320 int pciverbose_loaded = 0; 321 322 #if defined(_KERNEL) 323 /* 324 * Routine to load the pciverbose kernel module as needed 325 */ 326 void pci_load_verbose(void) 327 { 328 if (pciverbose_loaded == 0) 329 module_autoload("pciverbose", MODULE_CLASS_MISC); 330 } 331 332 const char *pci_findvendor_stub(pcireg_t id_reg) 333 { 334 pci_load_verbose(); 335 if (pciverbose_loaded) 336 return pci_findvendor(id_reg); 337 else 338 return NULL; 339 } 340 341 const char *pci_findproduct_stub(pcireg_t id_reg) 342 { 343 pci_load_verbose(); 344 if (pciverbose_loaded) 345 return pci_findproduct(id_reg); 346 else 347 return NULL; 348 } 349 #endif 350 351 void 352 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 353 size_t l) 354 { 355 pci_vendor_id_t vendor; 356 pci_product_id_t product; 357 pci_class_t class; 358 pci_subclass_t subclass; 359 pci_interface_t interface; 360 pci_revision_t revision; 361 const char *unmatched = pci_unmatched; 362 const char *vendor_namep, *product_namep; 363 const struct pci_class *classp, *subclassp; 364 char *ep; 365 366 ep = cp + l; 367 368 vendor = PCI_VENDOR(id_reg); 369 product = PCI_PRODUCT(id_reg); 370 371 class = PCI_CLASS(class_reg); 372 subclass = PCI_SUBCLASS(class_reg); 373 interface = PCI_INTERFACE(class_reg); 374 revision = PCI_REVISION(class_reg); 375 376 vendor_namep = pci_findvendor(id_reg); 377 product_namep = pci_findproduct(id_reg); 378 379 classp = pci_class; 380 while (classp->name != NULL) { 381 if (class == classp->val) 382 break; 383 classp++; 384 } 385 386 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 387 while (subclassp && subclassp->name != NULL) { 388 if (subclass == subclassp->val) 389 break; 390 subclassp++; 391 } 392 393 if (vendor_namep == NULL) 394 cp += snprintf(cp, ep - cp, "%svendor 0x%04x product 0x%04x", 395 unmatched, vendor, product); 396 else if (product_namep != NULL) 397 cp += snprintf(cp, ep - cp, "%s %s", vendor_namep, 398 product_namep); 399 else 400 cp += snprintf(cp, ep - cp, "%s product 0x%04x", 401 vendor_namep, product); 402 if (showclass) { 403 cp += snprintf(cp, ep - cp, " ("); 404 if (classp->name == NULL) 405 cp += snprintf(cp, ep - cp, 406 "class 0x%02x, subclass 0x%02x", class, subclass); 407 else { 408 if (subclassp == NULL || subclassp->name == NULL) 409 cp += snprintf(cp, ep - cp, 410 "%s, subclass 0x%02x", 411 classp->name, subclass); 412 else 413 cp += snprintf(cp, ep - cp, "%s %s", 414 subclassp->name, classp->name); 415 } 416 if (interface != 0) 417 cp += snprintf(cp, ep - cp, ", interface 0x%02x", 418 interface); 419 if (revision != 0) 420 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 421 revision); 422 cp += snprintf(cp, ep - cp, ")"); 423 } 424 } 425 426 #ifdef _KERNEL 427 void 428 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 429 const char *known, int addrev) 430 { 431 char devinfo[256]; 432 433 if (known) { 434 aprint_normal(": %s", known); 435 if (addrev) 436 aprint_normal(" (rev. 0x%02x)", 437 PCI_REVISION(pa->pa_class)); 438 aprint_normal("\n"); 439 } else { 440 pci_devinfo(pa->pa_id, pa->pa_class, 0, 441 devinfo, sizeof(devinfo)); 442 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 443 PCI_REVISION(pa->pa_class)); 444 } 445 if (naive) 446 aprint_naive(": %s\n", naive); 447 else 448 aprint_naive("\n"); 449 } 450 #endif 451 452 /* 453 * Print out most of the PCI configuration registers. Typically used 454 * in a device attach routine like this: 455 * 456 * #ifdef MYDEV_DEBUG 457 * printf("%s: ", device_xname(sc->sc_dev)); 458 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 459 * #endif 460 */ 461 462 #define i2o(i) ((i) * 4) 463 #define o2i(o) ((o) / 4) 464 #define onoff2(str, bit, onstr, offstr) \ 465 printf(" %s: %s\n", (str), (rval & (bit)) ? onstr : offstr); 466 #define onoff(str, bit) onoff2(str, bit, "on", "off") 467 468 static void 469 pci_conf_print_common( 470 #ifdef _KERNEL 471 pci_chipset_tag_t pc, pcitag_t tag, 472 #endif 473 const pcireg_t *regs) 474 { 475 const char *name; 476 const struct pci_class *classp, *subclassp; 477 pcireg_t rval; 478 479 rval = regs[o2i(PCI_ID_REG)]; 480 name = pci_findvendor(rval); 481 if (name) 482 printf(" Vendor Name: %s (0x%04x)\n", name, 483 PCI_VENDOR(rval)); 484 else 485 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 486 name = pci_findproduct(rval); 487 if (name) 488 printf(" Device Name: %s (0x%04x)\n", name, 489 PCI_PRODUCT(rval)); 490 else 491 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 492 493 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 494 495 printf(" Command register: 0x%04x\n", rval & 0xffff); 496 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 497 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 498 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 499 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 500 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 501 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 502 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 503 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 504 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 505 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 506 onoff("Interrupt disable", PCI_COMMAND_INTERRUPT_DISABLE); 507 508 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 509 onoff2("Interrupt status", PCI_STATUS_INT_STATUS, "active", "inactive"); 510 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 511 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 512 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 513 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 514 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 515 516 printf(" DEVSEL timing: "); 517 switch (rval & PCI_STATUS_DEVSEL_MASK) { 518 case PCI_STATUS_DEVSEL_FAST: 519 printf("fast"); 520 break; 521 case PCI_STATUS_DEVSEL_MEDIUM: 522 printf("medium"); 523 break; 524 case PCI_STATUS_DEVSEL_SLOW: 525 printf("slow"); 526 break; 527 default: 528 printf("unknown/reserved"); /* XXX */ 529 break; 530 } 531 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 532 533 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 534 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 535 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 536 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 537 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 538 539 rval = regs[o2i(PCI_CLASS_REG)]; 540 for (classp = pci_class; classp->name != NULL; classp++) { 541 if (PCI_CLASS(rval) == classp->val) 542 break; 543 } 544 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 545 while (subclassp && subclassp->name != NULL) { 546 if (PCI_SUBCLASS(rval) == subclassp->val) 547 break; 548 subclassp++; 549 } 550 if (classp->name != NULL) { 551 printf(" Class Name: %s (0x%02x)\n", classp->name, 552 PCI_CLASS(rval)); 553 if (subclassp != NULL && subclassp->name != NULL) 554 printf(" Subclass Name: %s (0x%02x)\n", 555 subclassp->name, PCI_SUBCLASS(rval)); 556 else 557 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 558 } else { 559 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 560 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 561 } 562 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 563 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 564 565 rval = regs[o2i(PCI_BHLC_REG)]; 566 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 567 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 568 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 569 PCI_HDRTYPE(rval)); 570 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 571 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 572 } 573 574 static int 575 pci_conf_print_bar( 576 #ifdef _KERNEL 577 pci_chipset_tag_t pc, pcitag_t tag, 578 #endif 579 const pcireg_t *regs, int reg, const char *name 580 #ifdef _KERNEL 581 , int sizebar 582 #endif 583 ) 584 { 585 int width; 586 pcireg_t rval, rval64h; 587 #ifdef _KERNEL 588 int s; 589 pcireg_t mask, mask64h; 590 #endif 591 592 width = 4; 593 594 /* 595 * Section 6.2.5.1, `Address Maps', tells us that: 596 * 597 * 1) The builtin software should have already mapped the 598 * device in a reasonable way. 599 * 600 * 2) A device which wants 2^n bytes of memory will hardwire 601 * the bottom n bits of the address to 0. As recommended, 602 * we write all 1s and see what we get back. 603 */ 604 605 rval = regs[o2i(reg)]; 606 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 607 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 608 rval64h = regs[o2i(reg + 4)]; 609 width = 8; 610 } else 611 rval64h = 0; 612 613 #ifdef _KERNEL 614 /* XXX don't size unknown memory type? */ 615 if (rval != 0 && sizebar) { 616 /* 617 * The following sequence seems to make some devices 618 * (e.g. host bus bridges, which don't normally 619 * have their space mapped) very unhappy, to 620 * the point of crashing the system. 621 * 622 * Therefore, if the mapping register is zero to 623 * start out with, don't bother trying. 624 */ 625 s = splhigh(); 626 pci_conf_write(pc, tag, reg, 0xffffffff); 627 mask = pci_conf_read(pc, tag, reg); 628 pci_conf_write(pc, tag, reg, rval); 629 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 630 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 631 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 632 mask64h = pci_conf_read(pc, tag, reg + 4); 633 pci_conf_write(pc, tag, reg + 4, rval64h); 634 } else 635 mask64h = 0; 636 splx(s); 637 } else 638 mask = mask64h = 0; 639 #endif /* _KERNEL */ 640 641 printf(" Base address register at 0x%02x", reg); 642 if (name) 643 printf(" (%s)", name); 644 printf("\n "); 645 if (rval == 0) { 646 printf("not implemented(?)\n"); 647 return width; 648 } 649 printf("type: "); 650 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 651 const char *type, *prefetch; 652 653 switch (PCI_MAPREG_MEM_TYPE(rval)) { 654 case PCI_MAPREG_MEM_TYPE_32BIT: 655 type = "32-bit"; 656 break; 657 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 658 type = "32-bit-1M"; 659 break; 660 case PCI_MAPREG_MEM_TYPE_64BIT: 661 type = "64-bit"; 662 break; 663 default: 664 type = "unknown (XXX)"; 665 break; 666 } 667 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 668 prefetch = ""; 669 else 670 prefetch = "non"; 671 printf("%s %sprefetchable memory\n", type, prefetch); 672 switch (PCI_MAPREG_MEM_TYPE(rval)) { 673 case PCI_MAPREG_MEM_TYPE_64BIT: 674 printf(" base: 0x%016llx, ", 675 PCI_MAPREG_MEM64_ADDR( 676 ((((long long) rval64h) << 32) | rval))); 677 #ifdef _KERNEL 678 if (sizebar) 679 printf("size: 0x%016llx", 680 PCI_MAPREG_MEM64_SIZE( 681 ((((long long) mask64h) << 32) | mask))); 682 else 683 #endif /* _KERNEL */ 684 printf("not sized"); 685 printf("\n"); 686 break; 687 case PCI_MAPREG_MEM_TYPE_32BIT: 688 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 689 default: 690 printf(" base: 0x%08x, ", 691 PCI_MAPREG_MEM_ADDR(rval)); 692 #ifdef _KERNEL 693 if (sizebar) 694 printf("size: 0x%08x", 695 PCI_MAPREG_MEM_SIZE(mask)); 696 else 697 #endif /* _KERNEL */ 698 printf("not sized"); 699 printf("\n"); 700 break; 701 } 702 } else { 703 #ifdef _KERNEL 704 if (sizebar) 705 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 706 #endif /* _KERNEL */ 707 printf("i/o\n"); 708 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 709 #ifdef _KERNEL 710 if (sizebar) 711 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 712 else 713 #endif /* _KERNEL */ 714 printf("not sized"); 715 printf("\n"); 716 } 717 718 return width; 719 } 720 721 static void 722 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 723 { 724 int off, needaddr, neednl; 725 726 needaddr = 1; 727 neednl = 0; 728 for (off = first; off < pastlast; off += 4) { 729 if ((off % 16) == 0 || needaddr) { 730 printf(" 0x%02x:", off); 731 needaddr = 0; 732 } 733 printf(" 0x%08x", regs[o2i(off)]); 734 neednl = 1; 735 if ((off % 16) == 12) { 736 printf("\n"); 737 neednl = 0; 738 } 739 } 740 if (neednl) 741 printf("\n"); 742 } 743 744 static void 745 pci_conf_print_type0( 746 #ifdef _KERNEL 747 pci_chipset_tag_t pc, pcitag_t tag, 748 #endif 749 const pcireg_t *regs 750 #ifdef _KERNEL 751 , int sizebars 752 #endif 753 ) 754 { 755 int off, width; 756 pcireg_t rval; 757 758 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 759 #ifdef _KERNEL 760 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 761 #else 762 width = pci_conf_print_bar(regs, off, NULL); 763 #endif 764 } 765 766 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 767 768 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 769 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 770 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 771 772 /* XXX */ 773 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 774 775 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 776 printf(" Capability list pointer: 0x%02x\n", 777 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 778 else 779 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 780 781 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 782 783 rval = regs[o2i(PCI_INTERRUPT_REG)]; 784 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 785 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 786 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 787 switch (PCI_INTERRUPT_PIN(rval)) { 788 case PCI_INTERRUPT_PIN_NONE: 789 printf("(none)"); 790 break; 791 case PCI_INTERRUPT_PIN_A: 792 printf("(pin A)"); 793 break; 794 case PCI_INTERRUPT_PIN_B: 795 printf("(pin B)"); 796 break; 797 case PCI_INTERRUPT_PIN_C: 798 printf("(pin C)"); 799 break; 800 case PCI_INTERRUPT_PIN_D: 801 printf("(pin D)"); 802 break; 803 default: 804 printf("(? ? ?)"); 805 break; 806 } 807 printf("\n"); 808 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 809 } 810 811 static void 812 pci_print_pcie_L0s_latency(uint32_t val) 813 { 814 815 switch (val) { 816 case 0x0: 817 printf("Less than 64ns\n"); 818 break; 819 case 0x1: 820 case 0x2: 821 case 0x3: 822 printf("%dns to less than %dns\n", 32 << val, 32 << (val + 1)); 823 break; 824 case 0x4: 825 printf("512ns to less than 1us\n"); 826 break; 827 case 0x5: 828 printf("1us to less than 2us\n"); 829 break; 830 case 0x6: 831 printf("2us - 4us\n"); 832 break; 833 case 0x7: 834 printf("More than 4us\n"); 835 break; 836 } 837 } 838 839 static void 840 pci_print_pcie_L1_latency(uint32_t val) 841 { 842 843 switch (val) { 844 case 0x0: 845 printf("Less than 1us\n"); 846 break; 847 case 0x6: 848 printf("32us - 64us\n"); 849 break; 850 case 0x7: 851 printf("More than 64us\n"); 852 break; 853 default: 854 printf("%dus to less than %dus\n", 1 << (val - 1), 1 << val); 855 break; 856 } 857 } 858 859 static void 860 pci_print_pcie_compl_timeout(uint32_t val) 861 { 862 863 switch (val) { 864 case 0x0: 865 printf("50us to 50ms\n"); 866 break; 867 case 0x5: 868 printf("16ms to 55ms\n"); 869 break; 870 case 0x6: 871 printf("65ms to 210ms\n"); 872 break; 873 case 0x9: 874 printf("260ms to 900ms\n"); 875 break; 876 case 0xa: 877 printf("1s to 3.5s\n"); 878 break; 879 default: 880 printf("unknown %u value\n", val); 881 break; 882 } 883 } 884 885 static void 886 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 887 { 888 pcireg_t reg; /* for each register */ 889 pcireg_t val; /* for each bitfield */ 890 bool check_link = false; 891 bool check_slot = false; 892 bool check_rootport = false; 893 unsigned int pciever; 894 static const char * const linkspeeds[] = {"2.5", "5.0", "8.0"}; 895 int i; 896 897 printf("\n PCI Express Capabilities Register\n"); 898 /* Capability Register */ 899 reg = regs[o2i(capoff)]; 900 printf(" Capability register: %04x\n", reg >> 16); 901 pciever = (unsigned int)((reg & 0x000f0000) >> 16); 902 printf(" Capability version: %u\n", pciever); 903 printf(" Device type: "); 904 switch ((reg & 0x00f00000) >> 20) { 905 case 0x0: 906 printf("PCI Express Endpoint device\n"); 907 check_link = true; 908 break; 909 case 0x1: 910 printf("Legacy PCI Express Endpoint device\n"); 911 check_link = true; 912 break; 913 case 0x4: 914 printf("Root Port of PCI Express Root Complex\n"); 915 check_link = true; 916 check_slot = true; 917 check_rootport = true; 918 break; 919 case 0x5: 920 printf("Upstream Port of PCI Express Switch\n"); 921 break; 922 case 0x6: 923 printf("Downstream Port of PCI Express Switch\n"); 924 check_slot = true; 925 check_rootport = true; 926 break; 927 case 0x7: 928 printf("PCI Express to PCI/PCI-X Bridge\n"); 929 break; 930 case 0x8: 931 printf("PCI/PCI-X to PCI Express Bridge\n"); 932 break; 933 case 0x9: 934 printf("Root Complex Integrated Endpoint\n"); 935 break; 936 case 0xa: 937 check_rootport = true; 938 printf("Root Complex Event Collector\n"); 939 break; 940 default: 941 printf("unknown\n"); 942 break; 943 } 944 if (check_slot && (reg & PCIE_XCAP_SI) != 0) 945 printf(" Slot implemented\n"); 946 printf(" Interrupt Message Number: %x\n", 947 (unsigned int)((reg & PCIE_XCAP_IRQ) >> 27)); 948 949 /* Device Capability Register */ 950 reg = regs[o2i(capoff + PCIE_DCAP)]; 951 printf(" Device Capabilities Register: 0x%08x\n", reg); 952 printf(" Max Payload Size Supported: %u bytes max\n", 953 (unsigned int)(reg & PCIE_DCAP_MAX_PAYLOAD) * 256); 954 printf(" Phantom Functions Supported: "); 955 switch ((reg & PCIE_DCAP_PHANTOM_FUNCS) >> 3) { 956 case 0x0: 957 printf("not available\n"); 958 break; 959 case 0x1: 960 printf("MSB\n"); 961 break; 962 case 0x2: 963 printf("two MSB\n"); 964 break; 965 case 0x3: 966 printf("All three bits\n"); 967 break; 968 } 969 printf(" Extended Tag Field Supported: %dbit\n", 970 (reg & PCIE_DCAP_EXT_TAG_FIELD) == 0 ? 5 : 8); 971 printf(" Endpoint L0 Acceptable Latency: "); 972 pci_print_pcie_L0s_latency((reg & PCIE_DCAP_L0S_LATENCY) >> 6); 973 printf(" Endpoint L1 Acceptable Latency: "); 974 pci_print_pcie_L1_latency((reg & PCIE_DCAP_L1_LATENCY) >> 9); 975 printf(" Attention Button Present: %s\n", 976 (reg & PCIE_DCAP_ATTN_BUTTON) != 0 ? "yes" : "no"); 977 printf(" Attention Indicator Present: %s\n", 978 (reg & PCIE_DCAP_ATTN_IND) != 0 ? "yes" : "no"); 979 printf(" Power Indicator Present: %s\n", 980 (reg & PCIE_DCAP_PWR_IND) != 0 ? "yes" : "no"); 981 printf(" Role-Based Error Report: %s\n", 982 (reg & PCIE_DCAP_ROLE_ERR_RPT) != 0 ? "yes" : "no"); 983 printf(" Captured Slot Power Limit Value: %d\n", 984 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_VAL) >> 18); 985 printf(" Captured Slot Power Limit Scale: %d\n", 986 (unsigned int)(reg & PCIE_DCAP_SLOT_PWR_LIM_SCALE) >> 26); 987 printf(" Function-Level Reset Capability: %s\n", 988 (reg & PCIE_DCAP_FLR) != 0 ? "yes" : "no"); 989 990 /* Device Control Register */ 991 reg = regs[o2i(capoff + PCIE_DCSR)]; 992 printf(" Device Control Register: 0x%04x\n", reg & 0xffff); 993 printf(" Correctable Error Reporting Enable: %s\n", 994 (reg & PCIE_DCSR_ENA_COR_ERR) != 0 ? "on" : "off"); 995 printf(" Non Fatal Error Reporting Enable: %s\n", 996 (reg & PCIE_DCSR_ENA_NFER) != 0 ? "on" : "off"); 997 printf(" Fatal Error Reporting Enable: %s\n", 998 (reg & PCIE_DCSR_ENA_FER) != 0 ? "on" : "off"); 999 printf(" Unsupported Request Reporting Enable: %s\n", 1000 (reg & PCIE_DCSR_ENA_URR) != 0 ? "on" : "off"); 1001 printf(" Enable Relaxed Ordering: %s\n", 1002 (reg & PCIE_DCSR_ENA_RELAX_ORD) != 0 ? "on" : "off"); 1003 printf(" Max Payload Size: %d byte\n", 1004 128 << (((unsigned int)(reg & PCIE_DCSR_MAX_PAYLOAD) >> 5))); 1005 printf(" Extended Tag Field Enable: %s\n", 1006 (reg & PCIE_DCSR_EXT_TAG_FIELD) != 0 ? "on" : "off"); 1007 printf(" Phantom Functions Enable: %s\n", 1008 (reg & PCIE_DCSR_PHANTOM_FUNCS) != 0 ? "on" : "off"); 1009 printf(" Aux Power PM Enable: %s\n", 1010 (reg & PCIE_DCSR_AUX_POWER_PM) != 0 ? "on" : "off"); 1011 printf(" Enable No Snoop: %s\n", 1012 (reg & PCIE_DCSR_ENA_NO_SNOOP) != 0 ? "on" : "off"); 1013 printf(" Max Read Request Size: %d byte\n", 1014 128 << ((unsigned int)(reg & PCIE_DCSR_MAX_READ_REQ) >> 12)); 1015 1016 /* Device Status Register */ 1017 reg = regs[o2i(capoff + PCIE_DCSR)]; 1018 printf(" Device Status Register: 0x%04x\n", reg >> 16); 1019 printf(" Correctable Error Detected: %s\n", 1020 (reg & PCIE_DCSR_CED) != 0 ? "on" : "off"); 1021 printf(" Non Fatal Error Detected: %s\n", 1022 (reg & PCIE_DCSR_NFED) != 0 ? "on" : "off"); 1023 printf(" Fatal Error Detected: %s\n", 1024 (reg & PCIE_DCSR_FED) != 0 ? "on" : "off"); 1025 printf(" Unsupported Request Detected: %s\n", 1026 (reg & PCIE_DCSR_URD) != 0 ? "on" : "off"); 1027 printf(" Aux Power Detected: %s\n", 1028 (reg & PCIE_DCSR_AUX_PWR) != 0 ? "on" : "off"); 1029 printf(" Transaction Pending: %s\n", 1030 (reg & PCIE_DCSR_TRANSACTION_PND) != 0 ? "on" : "off"); 1031 1032 if (check_link) { 1033 /* Link Capability Register */ 1034 reg = regs[o2i(capoff + PCIE_LCAP)]; 1035 printf(" Link Capabilities Register: 0x%08x\n", reg); 1036 printf(" Maximum Link Speed: "); 1037 val = reg & PCIE_LCAP_MAX_SPEED; 1038 if (val < 1 || val > 3) { 1039 printf("unknown %u value\n", val); 1040 } else { 1041 printf("%sGT/s\n", linkspeeds[val - 1]); 1042 } 1043 printf(" Maximum Link Width: x%u lanes\n", 1044 (unsigned int)(reg & PCIE_LCAP_MAX_WIDTH) >> 4); 1045 printf(" Active State PM Support: "); 1046 val = (reg & PCIE_LCAP_ASPM) >> 10; 1047 switch (val) { 1048 case 0x1: 1049 printf("L0s Entry supported\n"); 1050 break; 1051 case 0x3: 1052 printf("L0s and L1 supported\n"); 1053 break; 1054 default: 1055 printf("Reserved value\n"); 1056 break; 1057 } 1058 printf(" L0 Exit Latency: "); 1059 pci_print_pcie_L0s_latency((reg & PCIE_LCAP_L0S_EXIT) >> 12); 1060 printf(" L1 Exit Latency: "); 1061 pci_print_pcie_L1_latency((reg & PCIE_LCAP_L1_EXIT) >> 15); 1062 printf(" Port Number: %u\n", reg >> 24); 1063 1064 /* Link Control Register */ 1065 reg = regs[o2i(capoff + PCIE_LCSR)]; 1066 printf(" Link Control Register: 0x%04x\n", reg & 0xffff); 1067 printf(" Active State PM Control: "); 1068 val = reg & (PCIE_LCSR_ASPM_L1 | PCIE_LCSR_ASPM_L0S); 1069 switch (val) { 1070 case 0: 1071 printf("disabled\n"); 1072 break; 1073 case 1: 1074 printf("L0s Entry Enabled\n"); 1075 break; 1076 case 2: 1077 printf("L1 Entry Enabled\n"); 1078 break; 1079 case 3: 1080 printf("L0s and L1 Entry Enabled\n"); 1081 break; 1082 } 1083 printf(" Read Completion Boundary Control: %dbyte\n", 1084 (reg & PCIE_LCSR_RCB) != 0 ? 128 : 64); 1085 printf(" Link Disable: %s\n", 1086 (reg & PCIE_LCSR_LINK_DIS) != 0 ? "on" : "off"); 1087 printf(" Retrain Link: %s\n", 1088 (reg & PCIE_LCSR_RETRAIN) != 0 ? "on" : "off"); 1089 printf(" Common Clock Configuration: %s\n", 1090 (reg & PCIE_LCSR_COMCLKCFG) != 0 ? "on" : "off"); 1091 printf(" Extended Synch: %s\n", 1092 (reg & PCIE_LCSR_EXTNDSYNC) != 0 ? "on" : "off"); 1093 printf(" Enable Clock Power Management: %s\n", 1094 (reg & PCIE_LCSR_ENCLKPM) != 0 ? "on" : "off"); 1095 printf(" Hardware Autonomous Width Disable: %s\n", 1096 (reg & PCIE_LCSR_HAWD) != 0 ? "on" : "off"); 1097 printf(" Link Bandwidth Management Interrupt Enable: %s\n", 1098 (reg & PCIE_LCSR_LBMIE) != 0 ? "on" : "off"); 1099 printf(" Link Autonomous Bandwidth Interrupt Enable: %s\n", 1100 (reg & PCIE_LCSR_LABIE) != 0 ? "on" : "off"); 1101 1102 /* Link Status Register */ 1103 reg = regs[o2i(capoff + PCIE_LCSR)]; 1104 printf(" Link Status Register: 0x%04x\n", reg >> 16); 1105 printf(" Negotiated Link Speed: "); 1106 if (((reg >> 16) & 0x000f) < 1 || 1107 ((reg >> 16) & 0x000f) > 3) { 1108 printf("unknown %u value\n", 1109 (unsigned int)(reg & PCIE_LCSR_LINKSPEED) >> 16); 1110 } else { 1111 printf("%sGT/s\n", 1112 linkspeeds[((reg & PCIE_LCSR_LINKSPEED) >> 16) - 1]); 1113 } 1114 printf(" Negotiated Link Width: x%u lanes\n", 1115 (reg >> 20) & 0x003f); 1116 printf(" Training Error: %s\n", 1117 (reg & PCIE_LCSR_LINKTRAIN_ERR) != 0 ? "on" : "off"); 1118 printf(" Link Training: %s\n", 1119 (reg & PCIE_LCSR_LINKTRAIN) != 0 ? "on" : "off"); 1120 printf(" Slot Clock Configuration: %s\n", 1121 (reg & PCIE_LCSR_SLOTCLKCFG) != 0 ? "on" : "off"); 1122 printf(" Data Link Layer Link Active: %s\n", 1123 (reg & PCIE_LCSR_DLACTIVE) != 0 ? "on" : "off"); 1124 printf(" Link Bandwidth Management Status: %s\n", 1125 (reg & PCIE_LCSR_LINK_BW_MGMT) != 0 ? "on" : "off"); 1126 printf(" Link Autonomous Bandwidth Status: %s\n", 1127 (reg & PCIE_LCSR_LINK_AUTO_BW) != 0 ? "on" : "off"); 1128 } 1129 1130 if (check_slot == true) { 1131 /* Slot Capability Register */ 1132 reg = regs[o2i(capoff + PCIE_SLCAP)]; 1133 printf(" Slot Capability Register: %08x\n", reg); 1134 if ((reg & PCIE_SLCAP_ABP) != 0) 1135 printf(" Attention Button Present\n"); 1136 if ((reg & PCIE_SLCAP_PCP) != 0) 1137 printf(" Power Controller Present\n"); 1138 if ((reg & PCIE_SLCAP_MSP) != 0) 1139 printf(" MRL Sensor Present\n"); 1140 if ((reg & PCIE_SLCAP_AIP) != 0) 1141 printf(" Attention Indicator Present\n"); 1142 if ((reg & PCIE_SLCAP_PIP) != 0) 1143 printf(" Power Indicator Present\n"); 1144 if ((reg & PCIE_SLCAP_HPS) != 0) 1145 printf(" Hot-Plug Surprise\n"); 1146 if ((reg & PCIE_SLCAP_HPC) != 0) 1147 printf(" Hot-Plug Capable\n"); 1148 printf(" Slot Power Limit Value: %d\n", 1149 (unsigned int)(reg & PCIE_SLCAP_SPLV) >> 7); 1150 printf(" Slot Power Limit Scale: %d\n", 1151 (unsigned int)(reg & PCIE_SLCAP_SPLS) >> 15); 1152 if ((reg & PCIE_SLCAP_EIP) != 0) 1153 printf(" Electromechanical Interlock Present\n"); 1154 if ((reg & PCIE_SLCAP_NCCS) != 0) 1155 printf(" No Command Completed Support\n"); 1156 printf(" Physical Slot Number: %d\n", 1157 (unsigned int)(reg & PCIE_SLCAP_PSN) >> 19); 1158 1159 /* Slot Control Register */ 1160 reg = regs[o2i(capoff + PCIE_SLCSR)]; 1161 printf(" Slot Control Register: %04x\n", reg & 0xffff); 1162 if ((reg & PCIE_SLCSR_ABE) != 0) 1163 printf(" Attention Button Pressed Enabled\n"); 1164 if ((reg & PCIE_SLCSR_PFE) != 0) 1165 printf(" Power Fault Detected Enabled\n"); 1166 if ((reg & PCIE_SLCSR_MSE) != 0) 1167 printf(" MRL Sensor Changed Enabled\n"); 1168 if ((reg & PCIE_SLCSR_PDE) != 0) 1169 printf(" Presense Detect Changed Enabled\n"); 1170 if ((reg & PCIE_SLCSR_CCE) != 0) 1171 printf(" Command Completed Interrupt Enabled\n"); 1172 if ((reg & PCIE_SLCSR_HPE) != 0) 1173 printf(" Hot-Plug Interrupt Enabled\n"); 1174 printf(" Attention Indicator Control: "); 1175 switch ((reg & PCIE_SLCSR_AIC) >> 6) { 1176 case 0x0: 1177 printf("reserved\n"); 1178 break; 1179 case 0x1: 1180 printf("on\n"); 1181 break; 1182 case 0x2: 1183 printf("blink\n"); 1184 break; 1185 case 0x3: 1186 printf("off\n"); 1187 break; 1188 } 1189 printf(" Power Indicator Control: "); 1190 switch ((reg & PCIE_SLCSR_PIC) >> 8) { 1191 case 0x0: 1192 printf("reserved\n"); 1193 break; 1194 case 0x1: 1195 printf("on\n"); 1196 break; 1197 case 0x2: 1198 printf("blink\n"); 1199 break; 1200 case 0x3: 1201 printf("off\n"); 1202 break; 1203 } 1204 printf(" Power Controller Control: "); 1205 if ((reg & PCIE_SLCSR_PCC) != 0) 1206 printf("off\n"); 1207 else 1208 printf("on\n"); 1209 if ((reg & PCIE_SLCSR_EIC) != 0) 1210 printf(" Electromechanical Interlock Control\n"); 1211 if ((reg & PCIE_SLCSR_LACS) != 0) 1212 printf(" Data Link Layer State Changed Enable\n"); 1213 1214 /* Slot Status Register */ 1215 printf(" Slot Status Register: %04x\n", reg >> 16); 1216 if ((reg & PCIE_SLCSR_ABP) != 0) 1217 printf(" Attention Button Pressed\n"); 1218 if ((reg & PCIE_SLCSR_PFD) != 0) 1219 printf(" Power Fault Detected\n"); 1220 if ((reg & PCIE_SLCSR_MSC) != 0) 1221 printf(" MRL Sensor Changed\n"); 1222 if ((reg & PCIE_SLCSR_PDC) != 0) 1223 printf(" Presense Detect Changed\n"); 1224 if ((reg & PCIE_SLCSR_CC) != 0) 1225 printf(" Command Completed\n"); 1226 if ((reg & PCIE_SLCSR_MS) != 0) 1227 printf(" MRL Open\n"); 1228 if ((reg & PCIE_SLCSR_PDS) != 0) 1229 printf(" Card Present in slot\n"); 1230 if ((reg & PCIE_SLCSR_EIS) != 0) 1231 printf(" Electromechanical Interlock engaged\n"); 1232 if ((reg & PCIE_SLCSR_LACS) != 0) 1233 printf(" Data Link Layer State Changed\n"); 1234 } 1235 1236 if (check_rootport == true) { 1237 /* Root Control Register */ 1238 reg = regs[o2i(capoff + PCIE_RCR)]; 1239 printf(" Root Control Register: %04x\n", reg & 0xffff); 1240 if ((reg & PCIE_RCR_SERR_CER) != 0) 1241 printf(" SERR on Correctable Error Enable\n"); 1242 if ((reg & PCIE_RCR_SERR_NFER) != 0) 1243 printf(" SERR on Non-Fatal Error Enable\n"); 1244 if ((reg & PCIE_RCR_SERR_FER) != 0) 1245 printf(" SERR on Fatal Error Enable\n"); 1246 if ((reg & PCIE_RCR_PME_IE) != 0) 1247 printf(" PME Interrupt Enable\n"); 1248 if ((reg & PCIE_RCR_CRS_SVE) != 0) 1249 printf(" CRS Software Visibility Enable\n"); 1250 1251 /* Root Capability Register */ 1252 printf(" Root Capability Register: %04x\n", 1253 reg >> 16); 1254 1255 /* Root Status Register */ 1256 reg = regs[o2i(capoff + PCIE_RSR)]; 1257 printf(" Root Status Register: %08x\n", reg); 1258 printf(" PME Requester ID: %04x\n", 1259 (unsigned int)(reg & PCIE_RSR_PME_REQESTER)); 1260 if ((reg & PCIE_RSR_PME_STAT) != 0) 1261 printf(" PME was asserted\n"); 1262 if ((reg & PCIE_RSR_PME_PEND) != 0) 1263 printf(" another PME is pending\n"); 1264 } 1265 1266 /* PCIe DW9 to DW14 is for PCIe 2.0 and newer */ 1267 if (pciever < 2) 1268 return; 1269 1270 /* Device Capabilities 2 */ 1271 reg = regs[o2i(capoff + PCIE_DCAP2)]; 1272 printf(" Device Capabilities 2: 0x%08x\n", reg); 1273 printf(" Completion Timeout Ranges Supported: %u \n", 1274 (unsigned int)(reg & PCIE_DCAP2_COMPT_RANGE)); 1275 printf(" Completion Timeout Disable Supported: %s\n", 1276 (reg & PCIE_DCAP2_COMPT_DIS) != 0 ? "yes" : "no"); 1277 printf(" ARI Forwarding Supported: %s\n", 1278 (reg & PCIE_DCAP2_ARI_FWD) != 0 ? "yes" : "no"); 1279 printf(" AtomicOp Routing Supported: %s\n", 1280 (reg & PCIE_DCAP2_ATOM_ROUT) != 0 ? "yes" : "no"); 1281 printf(" 32bit AtomicOp Completer Supported: %s\n", 1282 (reg & PCIE_DCAP2_32ATOM) != 0 ? "yes" : "no"); 1283 printf(" 64bit AtomicOp Completer Supported: %s\n", 1284 (reg & PCIE_DCAP2_64ATOM) != 0 ? "yes" : "no"); 1285 printf(" 128-bit CAS Completer Supported: %s\n", 1286 (reg & PCIE_DCAP2_128CAS) != 0 ? "yes" : "no"); 1287 printf(" No RO-enabled PR-PR passing: %s\n", 1288 (reg & PCIE_DCAP2_NO_ROPR_PASS) != 0 ? "yes" : "no"); 1289 printf(" LTR Mechanism Supported: %s\n", 1290 (reg & PCIE_DCAP2_LTR_MEC) != 0 ? "yes" : "no"); 1291 printf(" TPH Completer Supported: %u\n", 1292 (unsigned int)(reg & PCIE_DCAP2_TPH_COMP) >> 12); 1293 printf(" OBFF Supported: "); 1294 switch ((reg & PCIE_DCAP2_OBFF) >> 18) { 1295 case 0x0: 1296 printf("Not supported\n"); 1297 break; 1298 case 0x1: 1299 printf("Message only\n"); 1300 break; 1301 case 0x2: 1302 printf("WAKE# only\n"); 1303 break; 1304 case 0x3: 1305 printf("Both\n"); 1306 break; 1307 } 1308 printf(" Extended Fmt Field Supported: %s\n", 1309 (reg & PCIE_DCAP2_EXTFMT_FLD) != 0 ? "yes" : "no"); 1310 printf(" End-End TLP Prefix Supported: %s\n", 1311 (reg & PCIE_DCAP2_EETLP_PREF) != 0 ? "yes" : "no"); 1312 printf(" Max End-End TLP Prefixes: %u\n", 1313 (unsigned int)(reg & PCIE_DCAP2_MAX_EETLP) >> 22); 1314 1315 /* Device Control 2 */ 1316 reg = regs[o2i(capoff + PCIE_DCSR2)]; 1317 printf(" Device Control 2: 0x%04x\n", reg & 0xffff); 1318 printf(" Completion Timeout Value: "); 1319 pci_print_pcie_compl_timeout(reg & PCIE_DCSR2_COMPT_VAL); 1320 if ((reg & PCIE_DCSR2_COMPT_DIS) != 0) 1321 printf(" Completion Timeout Disabled\n"); 1322 if ((reg & PCIE_DCSR2_ARI_FWD) != 0) 1323 printf(" ARI Forwarding Enabled\n"); 1324 if ((reg & PCIE_DCSR2_ATOM_REQ) != 0) 1325 printf(" AtomicOp Rquester Enabled\n"); 1326 if ((reg & PCIE_DCSR2_ATOM_EBLK) != 0) 1327 printf(" AtomicOp Egress Blocking on\n"); 1328 if ((reg & PCIE_DCSR2_IDO_REQ) != 0) 1329 printf(" IDO Request Enabled\n"); 1330 if ((reg & PCIE_DCSR2_IDO_COMP) != 0) 1331 printf(" IDO Completion Enabled\n"); 1332 if ((reg & PCIE_DCSR2_LTR_MEC) != 0) 1333 printf(" LTR Mechanism Enabled\n"); 1334 printf(" OBFF: "); 1335 switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) { 1336 case 0x0: 1337 printf("Disabled\n"); 1338 break; 1339 case 0x1: 1340 printf("Enabled with Message Signaling Variation A\n"); 1341 break; 1342 case 0x2: 1343 printf("Enabled with Message Signaling Variation B\n"); 1344 break; 1345 case 0x3: 1346 printf("Enabled using WAKE# signaling\n"); 1347 break; 1348 } 1349 if ((reg & PCIE_DCSR2_EETLP) != 0) 1350 printf(" End-End TLP Prefix Blocking on\n"); 1351 1352 if (check_link) { 1353 /* Link Capability 2 */ 1354 reg = regs[o2i(capoff + PCIE_LCAP2)]; 1355 printf(" Link Capabilities 2: 0x%08x\n", reg); 1356 val = (reg & PCIE_LCAP2_SUP_LNKSV) >> 1; 1357 printf(" Supported Link Speed Vector:"); 1358 for (i = 0; i <= 2; i++) { 1359 if (((val >> i) & 0x01) != 0) 1360 printf(" %sGT/s", linkspeeds[i]); 1361 } 1362 printf("\n"); 1363 printf(" Crosslink Supported: %s\n", 1364 (reg & PCIE_LCAP2_CROSSLNK) != 0 ? "yes" : "no"); 1365 1366 /* Link Control 2 */ 1367 reg = regs[o2i(capoff + PCIE_LCSR2)]; 1368 printf(" Link Control 2: 0x%04x\n", reg & 0xffff); 1369 printf(" Target Link Speed: "); 1370 val = reg & PCIE_LCSR2_TGT_LSPEED; 1371 if (val < 1 || val > 3) { 1372 printf("unknown %u value\n", val); 1373 } else { 1374 printf("%sGT/s\n", linkspeeds[val - 1]); 1375 } 1376 if ((reg & PCIE_LCSR2_ENT_COMPL) != 0) 1377 printf(" Enter Compliance Enabled\n"); 1378 if ((reg & PCIE_LCSR2_HW_AS_DIS) != 0) 1379 printf(" HW Autonomous Speed Disabled\n"); 1380 if ((reg & PCIE_LCSR2_SEL_DEEMP) != 0) 1381 printf(" Selectable De-emphasis\n"); 1382 printf(" Transmit Margin: %u\n", 1383 (unsigned int)(reg & PCIE_LCSR2_TX_MARGIN) >> 7); 1384 if ((reg & PCIE_LCSR2_EN_MCOMP) != 0) 1385 printf(" Enter Modified Compliance\n"); 1386 if ((reg & PCIE_LCSR2_COMP_SOS) != 0) 1387 printf(" Compliance SOS\n"); 1388 printf(" Compliance Present/De-emphasis: %u\n", 1389 (unsigned int)(reg & PCIE_LCSR2_COMP_DEEMP) >> 12); 1390 1391 /* Link Status 2 */ 1392 if ((reg & PCIE_LCSR2_DEEMP_LVL) != 0) 1393 printf(" Current De-emphasis Level\n"); 1394 if ((reg & PCIE_LCSR2_EQ_COMPL) != 0) 1395 printf(" Equalization Complete\n"); 1396 if ((reg & PCIE_LCSR2_EQP1_SUC) != 0) 1397 printf(" Equalization Phase 1 Successful\n"); 1398 if ((reg & PCIE_LCSR2_EQP2_SUC) != 0) 1399 printf(" Equalization Phase 2 Successful\n"); 1400 if ((reg & PCIE_LCSR2_EQP3_SUC) != 0) 1401 printf(" Equalization Phase 3 Successful\n"); 1402 if ((reg & PCIE_LCSR2_LNKEQ_REQ) != 0) 1403 printf(" Link Equalization Request\n"); 1404 } 1405 1406 /* Slot Capability 2 */ 1407 /* Slot Control 2 */ 1408 /* Slot Status 2 */ 1409 } 1410 1411 static const char * 1412 pci_conf_print_pcipm_cap_aux(uint16_t caps) 1413 { 1414 switch ((caps >> 6) & 7) { 1415 case 0: return "self-powered"; 1416 case 1: return "55 mA"; 1417 case 2: return "100 mA"; 1418 case 3: return "160 mA"; 1419 case 4: return "220 mA"; 1420 case 5: return "270 mA"; 1421 case 6: return "320 mA"; 1422 case 7: 1423 default: return "375 mA"; 1424 } 1425 } 1426 1427 static const char * 1428 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 1429 { 1430 static const char unk[] = "unknown"; 1431 static const char *pmrev[8] = { 1432 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 1433 }; 1434 if (val > 7) 1435 return unk; 1436 return pmrev[val]; 1437 } 1438 1439 static void 1440 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 1441 { 1442 uint16_t caps, pmcsr; 1443 1444 caps = regs[o2i(capoff)] >> 16; 1445 pmcsr = regs[o2i(capoff + 0x04)] & 0xffff; 1446 1447 printf("\n PCI Power Management Capabilities Register\n"); 1448 1449 printf(" Capabilities register: 0x%04x\n", caps); 1450 printf(" Version: %s\n", 1451 pci_conf_print_pcipm_cap_pmrev(caps & 0x3)); 1452 printf(" PME# clock: %s\n", caps & 0x4 ? "on" : "off"); 1453 printf(" Device specific initialization: %s\n", 1454 caps & 0x20 ? "on" : "off"); 1455 printf(" 3.3V auxiliary current: %s\n", 1456 pci_conf_print_pcipm_cap_aux(caps)); 1457 printf(" D1 power management state support: %s\n", 1458 (caps >> 9) & 1 ? "on" : "off"); 1459 printf(" D2 power management state support: %s\n", 1460 (caps >> 10) & 1 ? "on" : "off"); 1461 printf(" PME# support: 0x%02x\n", caps >> 11); 1462 1463 printf(" Control/status register: 0x%04x\n", pmcsr); 1464 printf(" Power state: D%d\n", pmcsr & 3); 1465 printf(" PCI Express reserved: %s\n", 1466 (pmcsr >> 2) & 1 ? "on" : "off"); 1467 printf(" No soft reset: %s\n", (pmcsr >> 3) & 1 ? "on" : "off"); 1468 printf(" PME# assertion %sabled\n", 1469 (pmcsr >> 8) & 1 ? "en" : "dis"); 1470 printf(" PME# status: %s\n", (pmcsr >> 15) ? "on" : "off"); 1471 } 1472 1473 static void 1474 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 1475 { 1476 uint32_t ctl, mmc, mme; 1477 1478 regs += o2i(capoff); 1479 ctl = *regs++; 1480 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 1481 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 1482 1483 printf("\n PCI Message Signaled Interrupt\n"); 1484 1485 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1486 printf(" MSI Enabled: %s\n", 1487 ctl & PCI_MSI_CTL_MSI_ENABLE ? "yes" : "no"); 1488 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1489 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1490 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1491 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1492 printf(" 64 Bit Address Capable: %s\n", 1493 ctl & PCI_MSI_CTL_64BIT_ADDR ? "yes" : "no"); 1494 printf(" Per-Vector Masking Capable: %s\n", 1495 ctl & PCI_MSI_CTL_PERVEC_MASK ? "yes" : "no"); 1496 printf(" Message Address %sregister: 0x%08x\n", 1497 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1498 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1499 printf(" Message Address %sregister: 0x%08x\n", 1500 "(upper) ", *regs++); 1501 } 1502 printf(" Message Data register: 0x%08x\n", *regs++); 1503 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1504 printf(" Vector Mask register: 0x%08x\n", *regs++); 1505 printf(" Vector Pending register: 0x%08x\n", *regs++); 1506 } 1507 } 1508 static void 1509 pci_conf_print_caplist( 1510 #ifdef _KERNEL 1511 pci_chipset_tag_t pc, pcitag_t tag, 1512 #endif 1513 const pcireg_t *regs, int capoff) 1514 { 1515 int off; 1516 pcireg_t rval; 1517 int pcie_off = -1, pcipm_off = -1, msi_off = -1; 1518 1519 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1520 off != 0; 1521 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 1522 rval = regs[o2i(off)]; 1523 printf(" Capability register at 0x%02x\n", off); 1524 1525 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 1526 switch (PCI_CAPLIST_CAP(rval)) { 1527 case PCI_CAP_RESERVED0: 1528 printf("reserved"); 1529 break; 1530 case PCI_CAP_PWRMGMT: 1531 printf("Power Management, rev. %s", 1532 pci_conf_print_pcipm_cap_pmrev((rval >> 0) & 0x07)); 1533 pcipm_off = off; 1534 break; 1535 case PCI_CAP_AGP: 1536 printf("AGP, rev. %d.%d", 1537 PCI_CAP_AGP_MAJOR(rval), 1538 PCI_CAP_AGP_MINOR(rval)); 1539 break; 1540 case PCI_CAP_VPD: 1541 printf("VPD"); 1542 break; 1543 case PCI_CAP_SLOTID: 1544 printf("SlotID"); 1545 break; 1546 case PCI_CAP_MSI: 1547 printf("MSI"); 1548 msi_off = off; 1549 break; 1550 case PCI_CAP_CPCI_HOTSWAP: 1551 printf("CompactPCI Hot-swapping"); 1552 break; 1553 case PCI_CAP_PCIX: 1554 printf("PCI-X"); 1555 break; 1556 case PCI_CAP_LDT: 1557 printf("LDT"); 1558 break; 1559 case PCI_CAP_VENDSPEC: 1560 printf("Vendor-specific"); 1561 break; 1562 case PCI_CAP_DEBUGPORT: 1563 printf("Debug Port"); 1564 break; 1565 case PCI_CAP_CPCI_RSRCCTL: 1566 printf("CompactPCI Resource Control"); 1567 break; 1568 case PCI_CAP_HOTPLUG: 1569 printf("Hot-Plug"); 1570 break; 1571 case PCI_CAP_SUBVENDOR: 1572 printf("Sub Vendor ID"); 1573 break; 1574 case PCI_CAP_AGP8: 1575 printf("AGP 8x"); 1576 break; 1577 case PCI_CAP_SECURE: 1578 printf("Secure Device"); 1579 break; 1580 case PCI_CAP_PCIEXPRESS: 1581 printf("PCI Express"); 1582 pcie_off = off; 1583 break; 1584 case PCI_CAP_MSIX: 1585 printf("MSI-X"); 1586 break; 1587 case PCI_CAP_SATA: 1588 printf("SATA"); 1589 break; 1590 case PCI_CAP_PCIAF: 1591 printf("Advanced Features"); 1592 break; 1593 default: 1594 printf("unknown"); 1595 } 1596 printf(")\n"); 1597 } 1598 if (msi_off != -1) 1599 pci_conf_print_msi_cap(regs, msi_off); 1600 if (pcipm_off != -1) 1601 pci_conf_print_pcipm_cap(regs, pcipm_off); 1602 if (pcie_off != -1) 1603 pci_conf_print_pcie_cap(regs, pcie_off); 1604 } 1605 1606 /* Print the Secondary Status Register. */ 1607 static void 1608 pci_conf_print_ssr(pcireg_t rval) 1609 { 1610 pcireg_t devsel; 1611 1612 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 1613 onoff("66 MHz capable", __BIT(5)); 1614 onoff("User Definable Features (UDF) support", __BIT(6)); 1615 onoff("Fast back-to-back capable", __BIT(7)); 1616 onoff("Data parity error detected", __BIT(8)); 1617 1618 printf(" DEVSEL timing: "); 1619 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 1620 switch (devsel) { 1621 case 0: 1622 printf("fast"); 1623 break; 1624 case 1: 1625 printf("medium"); 1626 break; 1627 case 2: 1628 printf("slow"); 1629 break; 1630 default: 1631 printf("unknown/reserved"); /* XXX */ 1632 break; 1633 } 1634 printf(" (0x%x)\n", devsel); 1635 1636 onoff("Signalled target abort", __BIT(11)); 1637 onoff("Received target abort", __BIT(12)); 1638 onoff("Received master abort", __BIT(13)); 1639 onoff("Received system error", __BIT(14)); 1640 onoff("Detected parity error", __BIT(15)); 1641 } 1642 1643 static void 1644 pci_conf_print_type1( 1645 #ifdef _KERNEL 1646 pci_chipset_tag_t pc, pcitag_t tag, 1647 #endif 1648 const pcireg_t *regs 1649 #ifdef _KERNEL 1650 , int sizebars 1651 #endif 1652 ) 1653 { 1654 int off, width; 1655 pcireg_t rval; 1656 1657 /* 1658 * XXX these need to be printed in more detail, need to be 1659 * XXX checked against specs/docs, etc. 1660 * 1661 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 1662 * Bridge chip documentation, and may not be correct with 1663 * respect to various standards. (XXX) 1664 */ 1665 1666 for (off = 0x10; off < 0x18; off += width) { 1667 #ifdef _KERNEL 1668 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 1669 #else 1670 width = pci_conf_print_bar(regs, off, NULL); 1671 #endif 1672 } 1673 1674 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 1675 printf(" Primary bus number: 0x%02x\n", 1676 (rval >> 0) & 0xff); 1677 printf(" Secondary bus number: 0x%02x\n", 1678 (rval >> 8) & 0xff); 1679 printf(" Subordinate bus number: 0x%02x\n", 1680 (rval >> 16) & 0xff); 1681 printf(" Secondary bus latency timer: 0x%02x\n", 1682 (rval >> 24) & 0xff); 1683 1684 rval = regs[o2i(PCI_BRIDGE_STATIO_REG)]; 1685 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 1686 1687 /* XXX Print more prettily */ 1688 printf(" I/O region:\n"); 1689 printf(" base register: 0x%02x\n", (rval >> 0) & 0xff); 1690 printf(" limit register: 0x%02x\n", (rval >> 8) & 0xff); 1691 rval = regs[o2i(PCI_BRIDGE_IOHIGH_REG)]; 1692 printf(" base upper 16 bits register: 0x%04x\n", 1693 (rval >> 0) & 0xffff); 1694 printf(" limit upper 16 bits register: 0x%04x\n", 1695 (rval >> 16) & 0xffff); 1696 1697 /* XXX Print more prettily */ 1698 rval = regs[o2i(PCI_BRIDGE_MEMORY_REG)]; 1699 printf(" Memory region:\n"); 1700 printf(" base register: 0x%04x\n", 1701 (rval >> 0) & 0xffff); 1702 printf(" limit register: 0x%04x\n", 1703 (rval >> 16) & 0xffff); 1704 1705 /* XXX Print more prettily */ 1706 rval = regs[o2i(PCI_BRIDGE_PREFETCHMEM_REG)]; 1707 printf(" Prefetchable memory region:\n"); 1708 printf(" base register: 0x%04x\n", 1709 (rval >> 0) & 0xffff); 1710 printf(" limit register: 0x%04x\n", 1711 (rval >> 16) & 0xffff); 1712 printf(" base upper 32 bits register: 0x%08x\n", 1713 regs[o2i(PCI_BRIDGE_PREFETCHBASE32_REG)]); 1714 printf(" limit upper 32 bits register: 0x%08x\n", 1715 regs[o2i(PCI_BRIDGE_PREFETCHLIMIT32_REG)]); 1716 1717 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1718 printf(" Capability list pointer: 0x%02x\n", 1719 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 1720 else 1721 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 1722 1723 /* XXX */ 1724 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 1725 1726 rval = regs[o2i(PCI_INTERRUPT_REG)]; 1727 printf(" Interrupt line: 0x%02x\n", 1728 (rval >> 0) & 0xff); 1729 printf(" Interrupt pin: 0x%02x ", 1730 (rval >> 8) & 0xff); 1731 switch ((rval >> 8) & 0xff) { 1732 case PCI_INTERRUPT_PIN_NONE: 1733 printf("(none)"); 1734 break; 1735 case PCI_INTERRUPT_PIN_A: 1736 printf("(pin A)"); 1737 break; 1738 case PCI_INTERRUPT_PIN_B: 1739 printf("(pin B)"); 1740 break; 1741 case PCI_INTERRUPT_PIN_C: 1742 printf("(pin C)"); 1743 break; 1744 case PCI_INTERRUPT_PIN_D: 1745 printf("(pin D)"); 1746 break; 1747 default: 1748 printf("(? ? ?)"); 1749 break; 1750 } 1751 printf("\n"); 1752 rval = (regs[o2i(PCI_BRIDGE_CONTROL_REG)] >> PCI_BRIDGE_CONTROL_SHIFT) 1753 & PCI_BRIDGE_CONTROL_MASK; 1754 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 1755 onoff("Parity error response", 0x0001); 1756 onoff("Secondary SERR forwarding", 0x0002); 1757 onoff("ISA enable", 0x0004); 1758 onoff("VGA enable", 0x0008); 1759 onoff("Master abort reporting", 0x0020); 1760 onoff("Secondary bus reset", 0x0040); 1761 onoff("Fast back-to-back capable", 0x0080); 1762 } 1763 1764 static void 1765 pci_conf_print_type2( 1766 #ifdef _KERNEL 1767 pci_chipset_tag_t pc, pcitag_t tag, 1768 #endif 1769 const pcireg_t *regs 1770 #ifdef _KERNEL 1771 , int sizebars 1772 #endif 1773 ) 1774 { 1775 pcireg_t rval; 1776 1777 /* 1778 * XXX these need to be printed in more detail, need to be 1779 * XXX checked against specs/docs, etc. 1780 * 1781 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 1782 * controller chip documentation, and may not be correct with 1783 * respect to various standards. (XXX) 1784 */ 1785 1786 #ifdef _KERNEL 1787 pci_conf_print_bar(pc, tag, regs, 0x10, 1788 "CardBus socket/ExCA registers", sizebars); 1789 #else 1790 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 1791 #endif 1792 1793 /* Capability list pointer and secondary status register */ 1794 rval = regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)]; 1795 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1796 printf(" Capability list pointer: 0x%02x\n", 1797 PCI_CAPLIST_PTR(rval)); 1798 else 1799 printf(" Reserved @ 0x14: 0x%04" PRIxMAX "\n", 1800 __SHIFTOUT(rval, __BITS(15, 0))); 1801 pci_conf_print_ssr(__SHIFTOUT(rval, __BITS(31, 16))); 1802 1803 rval = regs[o2i(PCI_BRIDGE_BUS_REG)]; 1804 printf(" PCI bus number: 0x%02x\n", 1805 (rval >> 0) & 0xff); 1806 printf(" CardBus bus number: 0x%02x\n", 1807 (rval >> 8) & 0xff); 1808 printf(" Subordinate bus number: 0x%02x\n", 1809 (rval >> 16) & 0xff); 1810 printf(" CardBus latency timer: 0x%02x\n", 1811 (rval >> 24) & 0xff); 1812 1813 /* XXX Print more prettily */ 1814 printf(" CardBus memory region 0:\n"); 1815 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1816 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1817 printf(" CardBus memory region 1:\n"); 1818 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1819 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1820 printf(" CardBus I/O region 0:\n"); 1821 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1822 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1823 printf(" CardBus I/O region 1:\n"); 1824 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1825 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1826 1827 rval = regs[o2i(PCI_INTERRUPT_REG)]; 1828 printf(" Interrupt line: 0x%02x\n", 1829 (rval >> 0) & 0xff); 1830 printf(" Interrupt pin: 0x%02x ", 1831 (rval >> 8) & 0xff); 1832 switch ((rval >> 8) & 0xff) { 1833 case PCI_INTERRUPT_PIN_NONE: 1834 printf("(none)"); 1835 break; 1836 case PCI_INTERRUPT_PIN_A: 1837 printf("(pin A)"); 1838 break; 1839 case PCI_INTERRUPT_PIN_B: 1840 printf("(pin B)"); 1841 break; 1842 case PCI_INTERRUPT_PIN_C: 1843 printf("(pin C)"); 1844 break; 1845 case PCI_INTERRUPT_PIN_D: 1846 printf("(pin D)"); 1847 break; 1848 default: 1849 printf("(? ? ?)"); 1850 break; 1851 } 1852 printf("\n"); 1853 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1854 printf(" Bridge control register: 0x%04x\n", rval); 1855 onoff("Parity error response", __BIT(0)); 1856 onoff("SERR# enable", __BIT(1)); 1857 onoff("ISA enable", __BIT(2)); 1858 onoff("VGA enable", __BIT(3)); 1859 onoff("Master abort mode", __BIT(5)); 1860 onoff("Secondary (CardBus) bus reset", __BIT(6)); 1861 onoff("Functional interrupts routed by ExCA registers", __BIT(7)); 1862 onoff("Memory window 0 prefetchable", __BIT(8)); 1863 onoff("Memory window 1 prefetchable", __BIT(9)); 1864 onoff("Write posting enable", __BIT(10)); 1865 1866 rval = regs[o2i(0x40)]; 1867 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1868 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1869 1870 #ifdef _KERNEL 1871 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1872 sizebars); 1873 #else 1874 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 1875 #endif 1876 } 1877 1878 void 1879 pci_conf_print( 1880 #ifdef _KERNEL 1881 pci_chipset_tag_t pc, pcitag_t tag, 1882 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 1883 #else 1884 int pcifd, u_int bus, u_int dev, u_int func 1885 #endif 1886 ) 1887 { 1888 pcireg_t regs[o2i(256)]; 1889 int off, capoff, endoff, hdrtype; 1890 const char *typename; 1891 #ifdef _KERNEL 1892 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1893 int sizebars; 1894 #else 1895 void (*typeprintfn)(const pcireg_t *); 1896 #endif 1897 1898 printf("PCI configuration registers:\n"); 1899 1900 for (off = 0; off < 256; off += 4) { 1901 #ifdef _KERNEL 1902 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1903 #else 1904 if (pcibus_conf_read(pcifd, bus, dev, func, off, 1905 ®s[o2i(off)]) == -1) 1906 regs[o2i(off)] = 0; 1907 #endif 1908 } 1909 1910 #ifdef _KERNEL 1911 sizebars = 1; 1912 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1913 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1914 sizebars = 0; 1915 #endif 1916 1917 /* common header */ 1918 printf(" Common header:\n"); 1919 pci_conf_print_regs(regs, 0, 16); 1920 1921 printf("\n"); 1922 #ifdef _KERNEL 1923 pci_conf_print_common(pc, tag, regs); 1924 #else 1925 pci_conf_print_common(regs); 1926 #endif 1927 printf("\n"); 1928 1929 /* type-dependent header */ 1930 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1931 switch (hdrtype) { /* XXX make a table, eventually */ 1932 case 0: 1933 /* Standard device header */ 1934 typename = "\"normal\" device"; 1935 typeprintfn = &pci_conf_print_type0; 1936 capoff = PCI_CAPLISTPTR_REG; 1937 endoff = 64; 1938 break; 1939 case 1: 1940 /* PCI-PCI bridge header */ 1941 typename = "PCI-PCI bridge"; 1942 typeprintfn = &pci_conf_print_type1; 1943 capoff = PCI_CAPLISTPTR_REG; 1944 endoff = 64; 1945 break; 1946 case 2: 1947 /* PCI-CardBus bridge header */ 1948 typename = "PCI-CardBus bridge"; 1949 typeprintfn = &pci_conf_print_type2; 1950 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 1951 endoff = 72; 1952 break; 1953 default: 1954 typename = NULL; 1955 typeprintfn = 0; 1956 capoff = -1; 1957 endoff = 64; 1958 break; 1959 } 1960 printf(" Type %d ", hdrtype); 1961 if (typename != NULL) 1962 printf("(%s) ", typename); 1963 printf("header:\n"); 1964 pci_conf_print_regs(regs, 16, endoff); 1965 printf("\n"); 1966 if (typeprintfn) { 1967 #ifdef _KERNEL 1968 (*typeprintfn)(pc, tag, regs, sizebars); 1969 #else 1970 (*typeprintfn)(regs); 1971 #endif 1972 } else 1973 printf(" Don't know how to pretty-print type %d header.\n", 1974 hdrtype); 1975 printf("\n"); 1976 1977 /* capability list, if present */ 1978 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1979 && (capoff > 0)) { 1980 #ifdef _KERNEL 1981 pci_conf_print_caplist(pc, tag, regs, capoff); 1982 #else 1983 pci_conf_print_caplist(regs, capoff); 1984 #endif 1985 printf("\n"); 1986 } 1987 1988 /* device-dependent header */ 1989 printf(" Device-dependent header:\n"); 1990 pci_conf_print_regs(regs, endoff, 256); 1991 printf("\n"); 1992 #ifdef _KERNEL 1993 if (printfn) 1994 (*printfn)(pc, tag, regs); 1995 else 1996 printf(" Don't know how to pretty-print device-dependent header.\n"); 1997 printf("\n"); 1998 #endif /* _KERNEL */ 1999 } 2000
Indexes created Tue Sep 30 11:09:46 GMT 2025