pci_subr.c revision 1.89
1 /* $NetBSD: pci_subr.c,v 1.89 2012/01/26 21:17:28 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.89 2012/01/26 21:17:28 drochner Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdbool.h> 58 #include <stdio.h> 59 #endif 60 61 #include <dev/pci/pcireg.h> 62 #ifdef _KERNEL 63 #include <dev/pci/pcivar.h> 64 #endif 65 66 /* 67 * Descriptions of known PCI classes and subclasses. 68 * 69 * Subclasses are described in the same way as classes, but have a 70 * NULL subclass pointer. 71 */ 72 struct pci_class { 73 const char *name; 74 int val; /* as wide as pci_{,sub}class_t */ 75 const struct pci_class *subclasses; 76 }; 77 78 static const struct pci_class pci_subclass_prehistoric[] = { 79 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 80 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 81 { NULL, 0, NULL, }, 82 }; 83 84 static const struct pci_class pci_subclass_mass_storage[] = { 85 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 86 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 87 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 88 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 89 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 90 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, NULL, }, 91 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, NULL, }, 92 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 93 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 94 { NULL, 0, NULL, }, 95 }; 96 97 static const struct pci_class pci_subclass_network[] = { 98 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 99 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 100 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 101 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 102 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 103 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 104 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 105 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 106 { NULL, 0, NULL, }, 107 }; 108 109 static const struct pci_class pci_subclass_display[] = { 110 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, NULL, }, 111 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 112 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 113 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 114 { NULL, 0, NULL, }, 115 }; 116 117 static const struct pci_class pci_subclass_multimedia[] = { 118 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 119 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 120 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 121 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 122 { NULL, 0, NULL, }, 123 }; 124 125 static const struct pci_class pci_subclass_memory[] = { 126 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 127 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 128 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 129 { NULL, 0, NULL, }, 130 }; 131 132 static const struct pci_class pci_subclass_bridge[] = { 133 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 134 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 135 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 136 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 137 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, NULL, }, 138 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 139 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 140 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 141 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 142 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, NULL, }, 143 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 144 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 145 { NULL, 0, NULL, }, 146 }; 147 148 static const struct pci_class pci_subclass_communications[] = { 149 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, NULL, }, 150 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, NULL, }, 151 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL, }, 152 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, NULL, }, 153 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL, }, 154 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL, }, 155 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL, }, 156 { NULL, 0, NULL, }, 157 }; 158 159 static const struct pci_class pci_subclass_system[] = { 160 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, NULL, }, 161 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, NULL, }, 162 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, NULL, }, 163 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, NULL, }, 164 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 165 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 166 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 167 { NULL, 0, NULL, }, 168 }; 169 170 static const struct pci_class pci_subclass_input[] = { 171 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 172 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 173 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 174 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 175 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, NULL, }, 176 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 177 { NULL, 0, NULL, }, 178 }; 179 180 static const struct pci_class pci_subclass_dock[] = { 181 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 182 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 183 { NULL, 0, NULL, }, 184 }; 185 186 static const struct pci_class pci_subclass_processor[] = { 187 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 188 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 189 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 190 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 191 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 192 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 193 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 194 { NULL, 0, NULL, }, 195 }; 196 197 static const struct pci_class pci_subclass_serialbus[] = { 198 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, NULL, }, 199 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 200 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 201 { "USB", PCI_SUBCLASS_SERIALBUS_USB, NULL, }, 202 /* XXX Fiber Channel/_FIBRECHANNEL */ 203 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 204 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 205 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 206 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, NULL, }, 207 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 208 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 209 { NULL, 0, NULL, }, 210 }; 211 212 static const struct pci_class pci_subclass_wireless[] = { 213 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 214 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 215 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 216 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 217 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 218 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 219 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 220 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 221 { NULL, 0, NULL, }, 222 }; 223 224 static const struct pci_class pci_subclass_i2o[] = { 225 { "standard", PCI_SUBCLASS_I2O_STANDARD, NULL, }, 226 { NULL, 0, NULL, }, 227 }; 228 229 static const struct pci_class pci_subclass_satcom[] = { 230 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 231 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 232 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 233 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 234 { NULL, 0, NULL, }, 235 }; 236 237 static const struct pci_class pci_subclass_crypto[] = { 238 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 239 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 240 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 241 { NULL, 0, NULL, }, 242 }; 243 244 static const struct pci_class pci_subclass_dasp[] = { 245 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 246 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 247 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 248 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 249 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 250 { NULL, 0, NULL, }, 251 }; 252 253 static const struct pci_class pci_class[] = { 254 { "prehistoric", PCI_CLASS_PREHISTORIC, 255 pci_subclass_prehistoric, }, 256 { "mass storage", PCI_CLASS_MASS_STORAGE, 257 pci_subclass_mass_storage, }, 258 { "network", PCI_CLASS_NETWORK, 259 pci_subclass_network, }, 260 { "display", PCI_CLASS_DISPLAY, 261 pci_subclass_display, }, 262 { "multimedia", PCI_CLASS_MULTIMEDIA, 263 pci_subclass_multimedia, }, 264 { "memory", PCI_CLASS_MEMORY, 265 pci_subclass_memory, }, 266 { "bridge", PCI_CLASS_BRIDGE, 267 pci_subclass_bridge, }, 268 { "communications", PCI_CLASS_COMMUNICATIONS, 269 pci_subclass_communications, }, 270 { "system", PCI_CLASS_SYSTEM, 271 pci_subclass_system, }, 272 { "input", PCI_CLASS_INPUT, 273 pci_subclass_input, }, 274 { "dock", PCI_CLASS_DOCK, 275 pci_subclass_dock, }, 276 { "processor", PCI_CLASS_PROCESSOR, 277 pci_subclass_processor, }, 278 { "serial bus", PCI_CLASS_SERIALBUS, 279 pci_subclass_serialbus, }, 280 { "wireless", PCI_CLASS_WIRELESS, 281 pci_subclass_wireless, }, 282 { "I2O", PCI_CLASS_I2O, 283 pci_subclass_i2o, }, 284 { "satellite comm", PCI_CLASS_SATCOM, 285 pci_subclass_satcom, }, 286 { "crypto", PCI_CLASS_CRYPTO, 287 pci_subclass_crypto, }, 288 { "DASP", PCI_CLASS_DASP, 289 pci_subclass_dasp, }, 290 { "undefined", PCI_CLASS_UNDEFINED, 291 NULL, }, 292 { NULL, 0, 293 NULL, }, 294 }; 295 296 void pci_load_verbose(void); 297 298 #if defined(_KERNEL) 299 /* 300 * In kernel, these routines are provided and linked via the 301 * pciverbose module. 302 */ 303 const char *pci_findvendor_stub(pcireg_t); 304 const char *pci_findproduct_stub(pcireg_t); 305 306 const char *(*pci_findvendor)(pcireg_t) = pci_findvendor_stub; 307 const char *(*pci_findproduct)(pcireg_t) = pci_findproduct_stub; 308 const char *pci_unmatched = ""; 309 #else 310 /* 311 * For userland we just set the vectors here. 312 */ 313 const char *(*pci_findvendor)(pcireg_t id_reg) = pci_findvendor_real; 314 const char *(*pci_findproduct)(pcireg_t id_reg) = pci_findproduct_real; 315 const char *pci_unmatched = "unmatched "; 316 #endif 317 318 int pciverbose_loaded = 0; 319 320 #if defined(_KERNEL) 321 /* 322 * Routine to load the pciverbose kernel module as needed 323 */ 324 void pci_load_verbose(void) 325 { 326 if (pciverbose_loaded == 0) 327 module_autoload("pciverbose", MODULE_CLASS_MISC); 328 } 329 330 const char *pci_findvendor_stub(pcireg_t id_reg) 331 { 332 pci_load_verbose(); 333 if (pciverbose_loaded) 334 return pci_findvendor(id_reg); 335 else 336 return NULL; 337 } 338 339 const char *pci_findproduct_stub(pcireg_t id_reg) 340 { 341 pci_load_verbose(); 342 if (pciverbose_loaded) 343 return pci_findproduct(id_reg); 344 else 345 return NULL; 346 } 347 #endif 348 349 void 350 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 351 size_t l) 352 { 353 pci_vendor_id_t vendor; 354 pci_product_id_t product; 355 pci_class_t class; 356 pci_subclass_t subclass; 357 pci_interface_t interface; 358 pci_revision_t revision; 359 const char *unmatched = pci_unmatched; 360 const char *vendor_namep, *product_namep; 361 const struct pci_class *classp, *subclassp; 362 char *ep; 363 364 ep = cp + l; 365 366 vendor = PCI_VENDOR(id_reg); 367 product = PCI_PRODUCT(id_reg); 368 369 class = PCI_CLASS(class_reg); 370 subclass = PCI_SUBCLASS(class_reg); 371 interface = PCI_INTERFACE(class_reg); 372 revision = PCI_REVISION(class_reg); 373 374 vendor_namep = pci_findvendor(id_reg); 375 product_namep = pci_findproduct(id_reg); 376 377 classp = pci_class; 378 while (classp->name != NULL) { 379 if (class == classp->val) 380 break; 381 classp++; 382 } 383 384 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 385 while (subclassp && subclassp->name != NULL) { 386 if (subclass == subclassp->val) 387 break; 388 subclassp++; 389 } 390 391 if (vendor_namep == NULL) 392 cp += snprintf(cp, ep - cp, "%svendor 0x%04x product 0x%04x", 393 unmatched, vendor, product); 394 else if (product_namep != NULL) 395 cp += snprintf(cp, ep - cp, "%s %s", vendor_namep, 396 product_namep); 397 else 398 cp += snprintf(cp, ep - cp, "%s product 0x%04x", 399 vendor_namep, product); 400 if (showclass) { 401 cp += snprintf(cp, ep - cp, " ("); 402 if (classp->name == NULL) 403 cp += snprintf(cp, ep - cp, 404 "class 0x%02x, subclass 0x%02x", class, subclass); 405 else { 406 if (subclassp == NULL || subclassp->name == NULL) 407 cp += snprintf(cp, ep - cp, 408 "%s, subclass 0x%02x", 409 classp->name, subclass); 410 else 411 cp += snprintf(cp, ep - cp, "%s %s", 412 subclassp->name, classp->name); 413 } 414 if (interface != 0) 415 cp += snprintf(cp, ep - cp, ", interface 0x%02x", 416 interface); 417 if (revision != 0) 418 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 419 revision); 420 cp += snprintf(cp, ep - cp, ")"); 421 } 422 } 423 424 #ifdef _KERNEL 425 void 426 pci_aprint_devinfo(const struct pci_attach_args *pa) 427 { 428 char devinfo[256]; 429 430 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 431 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 432 PCI_REVISION(pa->pa_class)); 433 aprint_naive("\n"); 434 } 435 #endif 436 437 /* 438 * Print out most of the PCI configuration registers. Typically used 439 * in a device attach routine like this: 440 * 441 * #ifdef MYDEV_DEBUG 442 * printf("%s: ", device_xname(&sc->sc_dev)); 443 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 444 * #endif 445 */ 446 447 #define i2o(i) ((i) * 4) 448 #define o2i(o) ((o) / 4) 449 #define onoff2(str, bit, onstr, offstr) \ 450 printf(" %s: %s\n", (str), (rval & (bit)) ? onstr : offstr); 451 #define onoff(str, bit) onoff2(str, bit, "on", "off") 452 453 static void 454 pci_conf_print_common( 455 #ifdef _KERNEL 456 pci_chipset_tag_t pc, pcitag_t tag, 457 #endif 458 const pcireg_t *regs) 459 { 460 const char *name; 461 const struct pci_class *classp, *subclassp; 462 pcireg_t rval; 463 464 rval = regs[o2i(PCI_ID_REG)]; 465 name = pci_findvendor(rval); 466 if (name) 467 printf(" Vendor Name: %s (0x%04x)\n", name, 468 PCI_VENDOR(rval)); 469 else 470 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 471 name = pci_findproduct(rval); 472 if (name) 473 printf(" Device Name: %s (0x%04x)\n", name, 474 PCI_PRODUCT(rval)); 475 else 476 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 477 478 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 479 480 printf(" Command register: 0x%04x\n", rval & 0xffff); 481 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 482 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 483 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 484 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 485 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 486 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 487 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 488 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 489 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 490 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 491 onoff("Interrupt disable", PCI_COMMAND_INTERRUPT_DISABLE); 492 493 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 494 onoff2("Interrupt status", PCI_STATUS_INT_STATUS, "active", "inactive"); 495 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 496 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 497 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 498 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 499 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 500 501 printf(" DEVSEL timing: "); 502 switch (rval & PCI_STATUS_DEVSEL_MASK) { 503 case PCI_STATUS_DEVSEL_FAST: 504 printf("fast"); 505 break; 506 case PCI_STATUS_DEVSEL_MEDIUM: 507 printf("medium"); 508 break; 509 case PCI_STATUS_DEVSEL_SLOW: 510 printf("slow"); 511 break; 512 default: 513 printf("unknown/reserved"); /* XXX */ 514 break; 515 } 516 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 517 518 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 519 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 520 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 521 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 522 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 523 524 rval = regs[o2i(PCI_CLASS_REG)]; 525 for (classp = pci_class; classp->name != NULL; classp++) { 526 if (PCI_CLASS(rval) == classp->val) 527 break; 528 } 529 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 530 while (subclassp && subclassp->name != NULL) { 531 if (PCI_SUBCLASS(rval) == subclassp->val) 532 break; 533 subclassp++; 534 } 535 if (classp->name != NULL) { 536 printf(" Class Name: %s (0x%02x)\n", classp->name, 537 PCI_CLASS(rval)); 538 if (subclassp != NULL && subclassp->name != NULL) 539 printf(" Subclass Name: %s (0x%02x)\n", 540 subclassp->name, PCI_SUBCLASS(rval)); 541 else 542 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 543 } else { 544 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 545 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 546 } 547 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 548 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 549 550 rval = regs[o2i(PCI_BHLC_REG)]; 551 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 552 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 553 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 554 PCI_HDRTYPE(rval)); 555 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 556 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 557 } 558 559 static int 560 pci_conf_print_bar( 561 #ifdef _KERNEL 562 pci_chipset_tag_t pc, pcitag_t tag, 563 #endif 564 const pcireg_t *regs, int reg, const char *name 565 #ifdef _KERNEL 566 , int sizebar 567 #endif 568 ) 569 { 570 int width; 571 pcireg_t rval, rval64h; 572 #ifdef _KERNEL 573 int s; 574 pcireg_t mask, mask64h; 575 #endif 576 577 width = 4; 578 579 /* 580 * Section 6.2.5.1, `Address Maps', tells us that: 581 * 582 * 1) The builtin software should have already mapped the 583 * device in a reasonable way. 584 * 585 * 2) A device which wants 2^n bytes of memory will hardwire 586 * the bottom n bits of the address to 0. As recommended, 587 * we write all 1s and see what we get back. 588 */ 589 590 rval = regs[o2i(reg)]; 591 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 592 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 593 rval64h = regs[o2i(reg + 4)]; 594 width = 8; 595 } else 596 rval64h = 0; 597 598 #ifdef _KERNEL 599 /* XXX don't size unknown memory type? */ 600 if (rval != 0 && sizebar) { 601 /* 602 * The following sequence seems to make some devices 603 * (e.g. host bus bridges, which don't normally 604 * have their space mapped) very unhappy, to 605 * the point of crashing the system. 606 * 607 * Therefore, if the mapping register is zero to 608 * start out with, don't bother trying. 609 */ 610 s = splhigh(); 611 pci_conf_write(pc, tag, reg, 0xffffffff); 612 mask = pci_conf_read(pc, tag, reg); 613 pci_conf_write(pc, tag, reg, rval); 614 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 615 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 616 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 617 mask64h = pci_conf_read(pc, tag, reg + 4); 618 pci_conf_write(pc, tag, reg + 4, rval64h); 619 } else 620 mask64h = 0; 621 splx(s); 622 } else 623 mask = mask64h = 0; 624 #endif /* _KERNEL */ 625 626 printf(" Base address register at 0x%02x", reg); 627 if (name) 628 printf(" (%s)", name); 629 printf("\n "); 630 if (rval == 0) { 631 printf("not implemented(?)\n"); 632 return width; 633 } 634 printf("type: "); 635 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 636 const char *type, *prefetch; 637 638 switch (PCI_MAPREG_MEM_TYPE(rval)) { 639 case PCI_MAPREG_MEM_TYPE_32BIT: 640 type = "32-bit"; 641 break; 642 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 643 type = "32-bit-1M"; 644 break; 645 case PCI_MAPREG_MEM_TYPE_64BIT: 646 type = "64-bit"; 647 break; 648 default: 649 type = "unknown (XXX)"; 650 break; 651 } 652 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 653 prefetch = ""; 654 else 655 prefetch = "non"; 656 printf("%s %sprefetchable memory\n", type, prefetch); 657 switch (PCI_MAPREG_MEM_TYPE(rval)) { 658 case PCI_MAPREG_MEM_TYPE_64BIT: 659 printf(" base: 0x%016llx, ", 660 PCI_MAPREG_MEM64_ADDR( 661 ((((long long) rval64h) << 32) | rval))); 662 #ifdef _KERNEL 663 if (sizebar) 664 printf("size: 0x%016llx", 665 PCI_MAPREG_MEM64_SIZE( 666 ((((long long) mask64h) << 32) | mask))); 667 else 668 #endif /* _KERNEL */ 669 printf("not sized"); 670 printf("\n"); 671 break; 672 case PCI_MAPREG_MEM_TYPE_32BIT: 673 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 674 default: 675 printf(" base: 0x%08x, ", 676 PCI_MAPREG_MEM_ADDR(rval)); 677 #ifdef _KERNEL 678 if (sizebar) 679 printf("size: 0x%08x", 680 PCI_MAPREG_MEM_SIZE(mask)); 681 else 682 #endif /* _KERNEL */ 683 printf("not sized"); 684 printf("\n"); 685 break; 686 } 687 } else { 688 #ifdef _KERNEL 689 if (sizebar) 690 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 691 #endif /* _KERNEL */ 692 printf("i/o\n"); 693 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 694 #ifdef _KERNEL 695 if (sizebar) 696 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 697 else 698 #endif /* _KERNEL */ 699 printf("not sized"); 700 printf("\n"); 701 } 702 703 return width; 704 } 705 706 static void 707 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 708 { 709 int off, needaddr, neednl; 710 711 needaddr = 1; 712 neednl = 0; 713 for (off = first; off < pastlast; off += 4) { 714 if ((off % 16) == 0 || needaddr) { 715 printf(" 0x%02x:", off); 716 needaddr = 0; 717 } 718 printf(" 0x%08x", regs[o2i(off)]); 719 neednl = 1; 720 if ((off % 16) == 12) { 721 printf("\n"); 722 neednl = 0; 723 } 724 } 725 if (neednl) 726 printf("\n"); 727 } 728 729 static void 730 pci_conf_print_type0( 731 #ifdef _KERNEL 732 pci_chipset_tag_t pc, pcitag_t tag, 733 #endif 734 const pcireg_t *regs 735 #ifdef _KERNEL 736 , int sizebars 737 #endif 738 ) 739 { 740 int off, width; 741 pcireg_t rval; 742 743 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 744 #ifdef _KERNEL 745 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 746 #else 747 width = pci_conf_print_bar(regs, off, NULL); 748 #endif 749 } 750 751 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 752 753 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 754 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 755 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 756 757 /* XXX */ 758 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 759 760 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 761 printf(" Capability list pointer: 0x%02x\n", 762 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 763 else 764 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 765 766 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 767 768 rval = regs[o2i(PCI_INTERRUPT_REG)]; 769 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 770 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 771 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 772 switch (PCI_INTERRUPT_PIN(rval)) { 773 case PCI_INTERRUPT_PIN_NONE: 774 printf("(none)"); 775 break; 776 case PCI_INTERRUPT_PIN_A: 777 printf("(pin A)"); 778 break; 779 case PCI_INTERRUPT_PIN_B: 780 printf("(pin B)"); 781 break; 782 case PCI_INTERRUPT_PIN_C: 783 printf("(pin C)"); 784 break; 785 case PCI_INTERRUPT_PIN_D: 786 printf("(pin D)"); 787 break; 788 default: 789 printf("(? ? ?)"); 790 break; 791 } 792 printf("\n"); 793 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 794 } 795 796 static void 797 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 798 { 799 bool check_slot = false; 800 801 printf("\n PCI Express Capabilities Register\n"); 802 printf(" Capability version: %x\n", 803 (unsigned int)((regs[o2i(capoff)] & 0x000f0000) >> 16)); 804 printf(" Device type: "); 805 switch ((regs[o2i(capoff)] & 0x00f00000) >> 20) { 806 case 0x0: 807 printf("PCI Express Endpoint device\n"); 808 break; 809 case 0x1: 810 printf("Legacy PCI Express Endpoint device\n"); 811 break; 812 case 0x4: 813 printf("Root Port of PCI Express Root Complex\n"); 814 check_slot = true; 815 break; 816 case 0x5: 817 printf("Upstream Port of PCI Express Switch\n"); 818 break; 819 case 0x6: 820 printf("Downstream Port of PCI Express Switch\n"); 821 check_slot = true; 822 break; 823 case 0x7: 824 printf("PCI Express to PCI/PCI-X Bridge\n"); 825 break; 826 case 0x8: 827 printf("PCI/PCI-X to PCI Express Bridge\n"); 828 break; 829 default: 830 printf("unknown\n"); 831 break; 832 } 833 if (check_slot && (regs[o2i(capoff)] & 0x01000000) != 0) 834 printf(" Slot implemented\n"); 835 printf(" Interrupt Message Number: %x\n", 836 (unsigned int)((regs[o2i(capoff)] & 0x4e000000) >> 27)); 837 printf(" Link Capabilities Register: 0x%08x\n", 838 regs[o2i(capoff + 0x0c)]); 839 printf(" Maximum Link Speed: "); 840 if ((regs[o2i(capoff + 0x0c)] & 0x000f) != 1) { 841 printf("unknown %u value\n", 842 (regs[o2i(capoff + 0x0c)] & 0x000f)); 843 } else { 844 printf("2.5Gb/s\n"); 845 } 846 printf(" Maximum Link Width: x%u lanes\n", 847 (regs[o2i(capoff + 0x0c)] & 0x03f0) >> 4); 848 printf(" Port Number: %u\n", regs[o2i(capoff + 0x0c)] >> 24); 849 printf(" Link Status Register: 0x%04x\n", 850 regs[o2i(capoff + 0x10)] >> 16); 851 printf(" Negotiated Link Speed: "); 852 if (((regs[o2i(capoff + 0x10)] >> 16) & 0x000f) != 1) { 853 printf("unknown %u value\n", 854 (regs[o2i(capoff + 0x10)] >> 16) & 0x000f); 855 } else { 856 printf("2.5Gb/s\n"); 857 } 858 printf(" Negotiated Link Width: x%u lanes\n", 859 (regs[o2i(capoff + 0x10)] >> 20) & 0x003f); 860 if ((regs[o2i(capoff + 0x18)] & 0x07ff) != 0) { 861 printf(" Slot Control Register:\n"); 862 if ((regs[o2i(capoff + 0x18)] & 0x0001) != 0) 863 printf(" Attention Button Pressed Enabled\n"); 864 if ((regs[o2i(capoff + 0x18)] & 0x0002) != 0) 865 printf(" Power Fault Detected Enabled\n"); 866 if ((regs[o2i(capoff + 0x18)] & 0x0004) != 0) 867 printf(" MRL Sensor Changed Enabled\n"); 868 if ((regs[o2i(capoff + 0x18)] & 0x0008) != 0) 869 printf(" Presense Detected Changed Enabled\n"); 870 if ((regs[o2i(capoff + 0x18)] & 0x0010) != 0) 871 printf(" Command Completed Interrupt Enabled\n"); 872 if ((regs[o2i(capoff + 0x18)] & 0x0020) != 0) 873 printf(" Hot-Plug Interrupt Enabled\n"); 874 printf(" Attention Indicator Control: "); 875 switch ((regs[o2i(capoff + 0x18)] & 0x00c0) >> 6) { 876 case 0x0: 877 printf("reserved\n"); 878 break; 879 case 0x1: 880 printf("on\n"); 881 break; 882 case 0x2: 883 printf("blink\n"); 884 break; 885 case 0x3: 886 printf("off\n"); 887 break; 888 } 889 printf(" Power Indicator Control: "); 890 switch ((regs[o2i(capoff + 0x18)] & 0x0300) >> 8) { 891 case 0x0: 892 printf("reserved\n"); 893 break; 894 case 0x1: 895 printf("on\n"); 896 break; 897 case 0x2: 898 printf("blink\n"); 899 break; 900 case 0x3: 901 printf("off\n"); 902 break; 903 } 904 printf(" Power Controller Control: "); 905 if ((regs[o2i(capoff + 0x18)] & 0x0400) != 0) 906 printf("off\n"); 907 else 908 printf("on\n"); 909 } 910 } 911 912 static const char * 913 pci_conf_print_pcipm_cap_aux(uint16_t caps) 914 { 915 switch ((caps >> 6) & 7) { 916 case 0: return "self-powered"; 917 case 1: return "55 mA"; 918 case 2: return "100 mA"; 919 case 3: return "160 mA"; 920 case 4: return "220 mA"; 921 case 5: return "270 mA"; 922 case 6: return "320 mA"; 923 case 7: 924 default: return "375 mA"; 925 } 926 } 927 928 static const char * 929 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 930 { 931 static const char unk[] = "unknown"; 932 static const char *pmrev[8] = { 933 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 934 }; 935 if (val > 7) 936 return unk; 937 return pmrev[val]; 938 } 939 940 static void 941 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 942 { 943 uint16_t caps, pmcsr; 944 945 caps = regs[o2i(capoff)] >> 16; 946 pmcsr = regs[o2i(capoff + 0x04)] & 0xffff; 947 948 printf("\n PCI Power Management Capabilities Register\n"); 949 950 printf(" Capabilities register: 0x%04x\n", caps); 951 printf(" Version: %s\n", 952 pci_conf_print_pcipm_cap_pmrev(caps & 0x3)); 953 printf(" PME# clock: %s\n", caps & 0x4 ? "on" : "off"); 954 printf(" Device specific initialization: %s\n", 955 caps & 0x20 ? "on" : "off"); 956 printf(" 3.3V auxiliary current: %s\n", 957 pci_conf_print_pcipm_cap_aux(caps)); 958 printf(" D1 power management state support: %s\n", 959 (caps >> 9) & 1 ? "on" : "off"); 960 printf(" D2 power management state support: %s\n", 961 (caps >> 10) & 1 ? "on" : "off"); 962 printf(" PME# support: 0x%02x\n", caps >> 11); 963 964 printf(" Control/status register: 0x%04x\n", pmcsr); 965 printf(" Power state: D%d\n", pmcsr & 3); 966 printf(" PCI Express reserved: %s\n", 967 (pmcsr >> 2) & 1 ? "on" : "off"); 968 printf(" No soft reset: %s\n", (pmcsr >> 3) & 1 ? "on" : "off"); 969 printf(" PME# assertion %sabled\n", 970 (pmcsr >> 8) & 1 ? "en" : "dis"); 971 printf(" PME# status: %s\n", (pmcsr >> 15) ? "on" : "off"); 972 } 973 974 static void 975 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 976 { 977 uint32_t ctl, mmc, mme; 978 979 regs += o2i(capoff); 980 ctl = *regs++; 981 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 982 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 983 984 printf("\n PCI Message Signaled Interrupt\n"); 985 986 printf(" Message Control register: 0x%04x\n", ctl >> 16); 987 printf(" MSI Enabled: %s\n", 988 ctl & PCI_MSI_CTL_MSI_ENABLE ? "yes" : "no"); 989 printf(" Multiple Message Capable: %s (%d vector%s)\n", 990 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 991 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 992 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 993 printf(" 64 Bit Address Capable: %s\n", 994 ctl & PCI_MSI_CTL_64BIT_ADDR ? "yes" : "no"); 995 printf(" Per-Vector Masking Capable: %s\n", 996 ctl & PCI_MSI_CTL_PERVEC_MASK ? "yes" : "no"); 997 printf(" Message Address %sregister: 0x%08x\n", 998 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 999 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1000 printf(" Message Address %sregister: 0x%08x\n", 1001 "(upper) ", *regs++); 1002 } 1003 printf(" Message Data register: 0x%08x\n", *regs++); 1004 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1005 printf(" Vector Mask register: 0x%08x\n", *regs++); 1006 printf(" Vector Pending register: 0x%08x\n", *regs++); 1007 } 1008 } 1009 static void 1010 pci_conf_print_caplist( 1011 #ifdef _KERNEL 1012 pci_chipset_tag_t pc, pcitag_t tag, 1013 #endif 1014 const pcireg_t *regs, int capoff) 1015 { 1016 int off; 1017 pcireg_t rval; 1018 int pcie_off = -1, pcipm_off = -1, msi_off = -1; 1019 1020 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1021 off != 0; 1022 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 1023 rval = regs[o2i(off)]; 1024 printf(" Capability register at 0x%02x\n", off); 1025 1026 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 1027 switch (PCI_CAPLIST_CAP(rval)) { 1028 case PCI_CAP_RESERVED0: 1029 printf("reserved"); 1030 break; 1031 case PCI_CAP_PWRMGMT: 1032 printf("Power Management, rev. %s", 1033 pci_conf_print_pcipm_cap_pmrev((rval >> 0) & 0x07)); 1034 pcipm_off = off; 1035 break; 1036 case PCI_CAP_AGP: 1037 printf("AGP, rev. %d.%d", 1038 PCI_CAP_AGP_MAJOR(rval), 1039 PCI_CAP_AGP_MINOR(rval)); 1040 break; 1041 case PCI_CAP_VPD: 1042 printf("VPD"); 1043 break; 1044 case PCI_CAP_SLOTID: 1045 printf("SlotID"); 1046 break; 1047 case PCI_CAP_MSI: 1048 printf("MSI"); 1049 msi_off = off; 1050 break; 1051 case PCI_CAP_CPCI_HOTSWAP: 1052 printf("CompactPCI Hot-swapping"); 1053 break; 1054 case PCI_CAP_PCIX: 1055 printf("PCI-X"); 1056 break; 1057 case PCI_CAP_LDT: 1058 printf("LDT"); 1059 break; 1060 case PCI_CAP_VENDSPEC: 1061 printf("Vendor-specific"); 1062 break; 1063 case PCI_CAP_DEBUGPORT: 1064 printf("Debug Port"); 1065 break; 1066 case PCI_CAP_CPCI_RSRCCTL: 1067 printf("CompactPCI Resource Control"); 1068 break; 1069 case PCI_CAP_HOTPLUG: 1070 printf("Hot-Plug"); 1071 break; 1072 case PCI_CAP_AGP8: 1073 printf("AGP 8x"); 1074 break; 1075 case PCI_CAP_SECURE: 1076 printf("Secure Device"); 1077 break; 1078 case PCI_CAP_PCIEXPRESS: 1079 printf("PCI Express"); 1080 pcie_off = off; 1081 break; 1082 case PCI_CAP_MSIX: 1083 printf("MSI-X"); 1084 break; 1085 case PCI_CAP_SATA: 1086 printf("SATA"); 1087 break; 1088 case PCI_CAP_PCIAF: 1089 printf("Advanced Features"); 1090 break; 1091 default: 1092 printf("unknown"); 1093 } 1094 printf(")\n"); 1095 } 1096 if (msi_off != -1) 1097 pci_conf_print_msi_cap(regs, msi_off); 1098 if (pcipm_off != -1) 1099 pci_conf_print_pcipm_cap(regs, pcipm_off); 1100 if (pcie_off != -1) 1101 pci_conf_print_pcie_cap(regs, pcie_off); 1102 } 1103 1104 /* Print the Secondary Status Register. */ 1105 static void 1106 pci_conf_print_ssr(pcireg_t rval) 1107 { 1108 pcireg_t devsel; 1109 1110 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 1111 onoff("66 MHz capable", __BIT(5)); 1112 onoff("User Definable Features (UDF) support", __BIT(6)); 1113 onoff("Fast back-to-back capable", __BIT(7)); 1114 onoff("Data parity error detected", __BIT(8)); 1115 1116 printf(" DEVSEL timing: "); 1117 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 1118 switch (devsel) { 1119 case 0: 1120 printf("fast"); 1121 break; 1122 case 1: 1123 printf("medium"); 1124 break; 1125 case 2: 1126 printf("slow"); 1127 break; 1128 default: 1129 printf("unknown/reserved"); /* XXX */ 1130 break; 1131 } 1132 printf(" (0x%x)\n", devsel); 1133 1134 onoff("Signalled target abort", __BIT(11)); 1135 onoff("Received target abort", __BIT(12)); 1136 onoff("Received master abort", __BIT(13)); 1137 onoff("Received system error", __BIT(14)); 1138 onoff("Detected parity error", __BIT(15)); 1139 } 1140 1141 static void 1142 pci_conf_print_type1( 1143 #ifdef _KERNEL 1144 pci_chipset_tag_t pc, pcitag_t tag, 1145 #endif 1146 const pcireg_t *regs 1147 #ifdef _KERNEL 1148 , int sizebars 1149 #endif 1150 ) 1151 { 1152 int off, width; 1153 pcireg_t rval; 1154 1155 /* 1156 * XXX these need to be printed in more detail, need to be 1157 * XXX checked against specs/docs, etc. 1158 * 1159 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 1160 * Bridge chip documentation, and may not be correct with 1161 * respect to various standards. (XXX) 1162 */ 1163 1164 for (off = 0x10; off < 0x18; off += width) { 1165 #ifdef _KERNEL 1166 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 1167 #else 1168 width = pci_conf_print_bar(regs, off, NULL); 1169 #endif 1170 } 1171 1172 printf(" Primary bus number: 0x%02x\n", 1173 (regs[o2i(0x18)] >> 0) & 0xff); 1174 printf(" Secondary bus number: 0x%02x\n", 1175 (regs[o2i(0x18)] >> 8) & 0xff); 1176 printf(" Subordinate bus number: 0x%02x\n", 1177 (regs[o2i(0x18)] >> 16) & 0xff); 1178 printf(" Secondary bus latency timer: 0x%02x\n", 1179 (regs[o2i(0x18)] >> 24) & 0xff); 1180 1181 pci_conf_print_ssr(__SHIFTOUT(regs[o2i(0x1c)], __BITS(31, 16))); 1182 1183 /* XXX Print more prettily */ 1184 printf(" I/O region:\n"); 1185 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 1186 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 1187 printf(" base upper 16 bits register: 0x%04x\n", 1188 (regs[o2i(0x30)] >> 0) & 0xffff); 1189 printf(" limit upper 16 bits register: 0x%04x\n", 1190 (regs[o2i(0x30)] >> 16) & 0xffff); 1191 1192 /* XXX Print more prettily */ 1193 printf(" Memory region:\n"); 1194 printf(" base register: 0x%04x\n", 1195 (regs[o2i(0x20)] >> 0) & 0xffff); 1196 printf(" limit register: 0x%04x\n", 1197 (regs[o2i(0x20)] >> 16) & 0xffff); 1198 1199 /* XXX Print more prettily */ 1200 printf(" Prefetchable memory region:\n"); 1201 printf(" base register: 0x%04x\n", 1202 (regs[o2i(0x24)] >> 0) & 0xffff); 1203 printf(" limit register: 0x%04x\n", 1204 (regs[o2i(0x24)] >> 16) & 0xffff); 1205 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 1206 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 1207 1208 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1209 printf(" Capability list pointer: 0x%02x\n", 1210 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 1211 else 1212 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 1213 1214 /* XXX */ 1215 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 1216 1217 printf(" Interrupt line: 0x%02x\n", 1218 (regs[o2i(0x3c)] >> 0) & 0xff); 1219 printf(" Interrupt pin: 0x%02x ", 1220 (regs[o2i(0x3c)] >> 8) & 0xff); 1221 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1222 case PCI_INTERRUPT_PIN_NONE: 1223 printf("(none)"); 1224 break; 1225 case PCI_INTERRUPT_PIN_A: 1226 printf("(pin A)"); 1227 break; 1228 case PCI_INTERRUPT_PIN_B: 1229 printf("(pin B)"); 1230 break; 1231 case PCI_INTERRUPT_PIN_C: 1232 printf("(pin C)"); 1233 break; 1234 case PCI_INTERRUPT_PIN_D: 1235 printf("(pin D)"); 1236 break; 1237 default: 1238 printf("(? ? ?)"); 1239 break; 1240 } 1241 printf("\n"); 1242 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1243 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 1244 onoff("Parity error response", 0x0001); 1245 onoff("Secondary SERR forwarding", 0x0002); 1246 onoff("ISA enable", 0x0004); 1247 onoff("VGA enable", 0x0008); 1248 onoff("Master abort reporting", 0x0020); 1249 onoff("Secondary bus reset", 0x0040); 1250 onoff("Fast back-to-back capable", 0x0080); 1251 } 1252 1253 static void 1254 pci_conf_print_type2( 1255 #ifdef _KERNEL 1256 pci_chipset_tag_t pc, pcitag_t tag, 1257 #endif 1258 const pcireg_t *regs 1259 #ifdef _KERNEL 1260 , int sizebars 1261 #endif 1262 ) 1263 { 1264 pcireg_t rval; 1265 1266 /* 1267 * XXX these need to be printed in more detail, need to be 1268 * XXX checked against specs/docs, etc. 1269 * 1270 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 1271 * controller chip documentation, and may not be correct with 1272 * respect to various standards. (XXX) 1273 */ 1274 1275 #ifdef _KERNEL 1276 pci_conf_print_bar(pc, tag, regs, 0x10, 1277 "CardBus socket/ExCA registers", sizebars); 1278 #else 1279 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 1280 #endif 1281 1282 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1283 printf(" Capability list pointer: 0x%02x\n", 1284 PCI_CAPLIST_PTR(regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)])); 1285 else 1286 printf(" Reserved @ 0x14: 0x%04" PRIxMAX "\n", 1287 __SHIFTOUT(regs[o2i(0x14)], __BITS(15, 0))); 1288 pci_conf_print_ssr(__SHIFTOUT(regs[o2i(0x14)], __BITS(31, 16))); 1289 1290 printf(" PCI bus number: 0x%02x\n", 1291 (regs[o2i(0x18)] >> 0) & 0xff); 1292 printf(" CardBus bus number: 0x%02x\n", 1293 (regs[o2i(0x18)] >> 8) & 0xff); 1294 printf(" Subordinate bus number: 0x%02x\n", 1295 (regs[o2i(0x18)] >> 16) & 0xff); 1296 printf(" CardBus latency timer: 0x%02x\n", 1297 (regs[o2i(0x18)] >> 24) & 0xff); 1298 1299 /* XXX Print more prettily */ 1300 printf(" CardBus memory region 0:\n"); 1301 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1302 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1303 printf(" CardBus memory region 1:\n"); 1304 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1305 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1306 printf(" CardBus I/O region 0:\n"); 1307 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1308 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1309 printf(" CardBus I/O region 1:\n"); 1310 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1311 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1312 1313 printf(" Interrupt line: 0x%02x\n", 1314 (regs[o2i(0x3c)] >> 0) & 0xff); 1315 printf(" Interrupt pin: 0x%02x ", 1316 (regs[o2i(0x3c)] >> 8) & 0xff); 1317 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1318 case PCI_INTERRUPT_PIN_NONE: 1319 printf("(none)"); 1320 break; 1321 case PCI_INTERRUPT_PIN_A: 1322 printf("(pin A)"); 1323 break; 1324 case PCI_INTERRUPT_PIN_B: 1325 printf("(pin B)"); 1326 break; 1327 case PCI_INTERRUPT_PIN_C: 1328 printf("(pin C)"); 1329 break; 1330 case PCI_INTERRUPT_PIN_D: 1331 printf("(pin D)"); 1332 break; 1333 default: 1334 printf("(? ? ?)"); 1335 break; 1336 } 1337 printf("\n"); 1338 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1339 printf(" Bridge control register: 0x%04x\n", rval); 1340 onoff("Parity error response", __BIT(0)); 1341 onoff("SERR# enable", __BIT(1)); 1342 onoff("ISA enable", __BIT(2)); 1343 onoff("VGA enable", __BIT(3)); 1344 onoff("Master abort mode", __BIT(5)); 1345 onoff("Secondary (CardBus) bus reset", __BIT(6)); 1346 onoff("Functional interrupts routed by ExCA registers", __BIT(7)); 1347 onoff("Memory window 0 prefetchable", __BIT(8)); 1348 onoff("Memory window 1 prefetchable", __BIT(9)); 1349 onoff("Write posting enable", __BIT(10)); 1350 1351 rval = regs[o2i(0x40)]; 1352 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1353 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1354 1355 #ifdef _KERNEL 1356 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1357 sizebars); 1358 #else 1359 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 1360 #endif 1361 } 1362 1363 void 1364 pci_conf_print( 1365 #ifdef _KERNEL 1366 pci_chipset_tag_t pc, pcitag_t tag, 1367 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 1368 #else 1369 int pcifd, u_int bus, u_int dev, u_int func 1370 #endif 1371 ) 1372 { 1373 pcireg_t regs[o2i(256)]; 1374 int off, capoff, endoff, hdrtype; 1375 const char *typename; 1376 #ifdef _KERNEL 1377 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1378 int sizebars; 1379 #else 1380 void (*typeprintfn)(const pcireg_t *); 1381 #endif 1382 1383 printf("PCI configuration registers:\n"); 1384 1385 for (off = 0; off < 256; off += 4) { 1386 #ifdef _KERNEL 1387 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1388 #else 1389 if (pcibus_conf_read(pcifd, bus, dev, func, off, 1390 ®s[o2i(off)]) == -1) 1391 regs[o2i(off)] = 0; 1392 #endif 1393 } 1394 1395 #ifdef _KERNEL 1396 sizebars = 1; 1397 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1398 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1399 sizebars = 0; 1400 #endif 1401 1402 /* common header */ 1403 printf(" Common header:\n"); 1404 pci_conf_print_regs(regs, 0, 16); 1405 1406 printf("\n"); 1407 #ifdef _KERNEL 1408 pci_conf_print_common(pc, tag, regs); 1409 #else 1410 pci_conf_print_common(regs); 1411 #endif 1412 printf("\n"); 1413 1414 /* type-dependent header */ 1415 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1416 switch (hdrtype) { /* XXX make a table, eventually */ 1417 case 0: 1418 /* Standard device header */ 1419 typename = "\"normal\" device"; 1420 typeprintfn = &pci_conf_print_type0; 1421 capoff = PCI_CAPLISTPTR_REG; 1422 endoff = 64; 1423 break; 1424 case 1: 1425 /* PCI-PCI bridge header */ 1426 typename = "PCI-PCI bridge"; 1427 typeprintfn = &pci_conf_print_type1; 1428 capoff = PCI_CAPLISTPTR_REG; 1429 endoff = 64; 1430 break; 1431 case 2: 1432 /* PCI-CardBus bridge header */ 1433 typename = "PCI-CardBus bridge"; 1434 typeprintfn = &pci_conf_print_type2; 1435 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 1436 endoff = 72; 1437 break; 1438 default: 1439 typename = NULL; 1440 typeprintfn = 0; 1441 capoff = -1; 1442 endoff = 64; 1443 break; 1444 } 1445 printf(" Type %d ", hdrtype); 1446 if (typename != NULL) 1447 printf("(%s) ", typename); 1448 printf("header:\n"); 1449 pci_conf_print_regs(regs, 16, endoff); 1450 printf("\n"); 1451 if (typeprintfn) { 1452 #ifdef _KERNEL 1453 (*typeprintfn)(pc, tag, regs, sizebars); 1454 #else 1455 (*typeprintfn)(regs); 1456 #endif 1457 } else 1458 printf(" Don't know how to pretty-print type %d header.\n", 1459 hdrtype); 1460 printf("\n"); 1461 1462 /* capability list, if present */ 1463 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1464 && (capoff > 0)) { 1465 #ifdef _KERNEL 1466 pci_conf_print_caplist(pc, tag, regs, capoff); 1467 #else 1468 pci_conf_print_caplist(regs, capoff); 1469 #endif 1470 printf("\n"); 1471 } 1472 1473 /* device-dependent header */ 1474 printf(" Device-dependent header:\n"); 1475 pci_conf_print_regs(regs, endoff, 256); 1476 printf("\n"); 1477 #ifdef _KERNEL 1478 if (printfn) 1479 (*printfn)(pc, tag, regs); 1480 else 1481 printf(" Don't know how to pretty-print device-dependent header.\n"); 1482 printf("\n"); 1483 #endif /* _KERNEL */ 1484 } 1485
Indexes created Wed Sep 24 05:09:52 GMT 2025