pci_subr.c revision 1.90
1 /* $NetBSD: pci_subr.c,v 1.90 2012/01/29 11:31:38 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Zubin D. Dittia. All rights reserved. 5 * Copyright (c) 1995, 1996, 1998, 2000 6 * Christopher G. Demetriou. All rights reserved. 7 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Charles M. Hannum. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * PCI autoconfiguration support functions. 37 * 38 * Note: This file is also built into a userland library (libpci). 39 * Pay attention to this when you make modifications. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.90 2012/01/29 11:31:38 drochner Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_pci.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #ifdef _KERNEL 52 #include <sys/systm.h> 53 #include <sys/intr.h> 54 #include <sys/module.h> 55 #else 56 #include <pci.h> 57 #include <stdbool.h> 58 #include <stdio.h> 59 #endif 60 61 #include <dev/pci/pcireg.h> 62 #ifdef _KERNEL 63 #include <dev/pci/pcivar.h> 64 #endif 65 66 /* 67 * Descriptions of known PCI classes and subclasses. 68 * 69 * Subclasses are described in the same way as classes, but have a 70 * NULL subclass pointer. 71 */ 72 struct pci_class { 73 const char *name; 74 int val; /* as wide as pci_{,sub}class_t */ 75 const struct pci_class *subclasses; 76 }; 77 78 static const struct pci_class pci_subclass_prehistoric[] = { 79 { "miscellaneous", PCI_SUBCLASS_PREHISTORIC_MISC, NULL, }, 80 { "VGA", PCI_SUBCLASS_PREHISTORIC_VGA, NULL, }, 81 { NULL, 0, NULL, }, 82 }; 83 84 static const struct pci_class pci_subclass_mass_storage[] = { 85 { "SCSI", PCI_SUBCLASS_MASS_STORAGE_SCSI, NULL, }, 86 { "IDE", PCI_SUBCLASS_MASS_STORAGE_IDE, NULL, }, 87 { "floppy", PCI_SUBCLASS_MASS_STORAGE_FLOPPY, NULL, }, 88 { "IPI", PCI_SUBCLASS_MASS_STORAGE_IPI, NULL, }, 89 { "RAID", PCI_SUBCLASS_MASS_STORAGE_RAID, NULL, }, 90 { "ATA", PCI_SUBCLASS_MASS_STORAGE_ATA, NULL, }, 91 { "SATA", PCI_SUBCLASS_MASS_STORAGE_SATA, NULL, }, 92 { "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, }, 93 { "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, }, 94 { NULL, 0, NULL, }, 95 }; 96 97 static const struct pci_class pci_subclass_network[] = { 98 { "ethernet", PCI_SUBCLASS_NETWORK_ETHERNET, NULL, }, 99 { "token ring", PCI_SUBCLASS_NETWORK_TOKENRING, NULL, }, 100 { "FDDI", PCI_SUBCLASS_NETWORK_FDDI, NULL, }, 101 { "ATM", PCI_SUBCLASS_NETWORK_ATM, NULL, }, 102 { "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, }, 103 { "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, }, 104 { "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, }, 105 { "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, }, 106 { NULL, 0, NULL, }, 107 }; 108 109 static const struct pci_class pci_subclass_display[] = { 110 { "VGA", PCI_SUBCLASS_DISPLAY_VGA, NULL, }, 111 { "XGA", PCI_SUBCLASS_DISPLAY_XGA, NULL, }, 112 { "3D", PCI_SUBCLASS_DISPLAY_3D, NULL, }, 113 { "miscellaneous", PCI_SUBCLASS_DISPLAY_MISC, NULL, }, 114 { NULL, 0, NULL, }, 115 }; 116 117 static const struct pci_class pci_subclass_multimedia[] = { 118 { "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, }, 119 { "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, }, 120 { "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,}, 121 { "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, }, 122 { NULL, 0, NULL, }, 123 }; 124 125 static const struct pci_class pci_subclass_memory[] = { 126 { "RAM", PCI_SUBCLASS_MEMORY_RAM, NULL, }, 127 { "flash", PCI_SUBCLASS_MEMORY_FLASH, NULL, }, 128 { "miscellaneous", PCI_SUBCLASS_MEMORY_MISC, NULL, }, 129 { NULL, 0, NULL, }, 130 }; 131 132 static const struct pci_class pci_subclass_bridge[] = { 133 { "host", PCI_SUBCLASS_BRIDGE_HOST, NULL, }, 134 { "ISA", PCI_SUBCLASS_BRIDGE_ISA, NULL, }, 135 { "EISA", PCI_SUBCLASS_BRIDGE_EISA, NULL, }, 136 { "MicroChannel", PCI_SUBCLASS_BRIDGE_MC, NULL, }, 137 { "PCI", PCI_SUBCLASS_BRIDGE_PCI, NULL, }, 138 { "PCMCIA", PCI_SUBCLASS_BRIDGE_PCMCIA, NULL, }, 139 { "NuBus", PCI_SUBCLASS_BRIDGE_NUBUS, NULL, }, 140 { "CardBus", PCI_SUBCLASS_BRIDGE_CARDBUS, NULL, }, 141 { "RACEway", PCI_SUBCLASS_BRIDGE_RACEWAY, NULL, }, 142 { "Semi-transparent PCI", PCI_SUBCLASS_BRIDGE_STPCI, NULL, }, 143 { "InfiniBand", PCI_SUBCLASS_BRIDGE_INFINIBAND, NULL, }, 144 { "miscellaneous", PCI_SUBCLASS_BRIDGE_MISC, NULL, }, 145 { NULL, 0, NULL, }, 146 }; 147 148 static const struct pci_class pci_subclass_communications[] = { 149 { "serial", PCI_SUBCLASS_COMMUNICATIONS_SERIAL, NULL, }, 150 { "parallel", PCI_SUBCLASS_COMMUNICATIONS_PARALLEL, NULL, }, 151 { "multi-port serial", PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL, NULL, }, 152 { "modem", PCI_SUBCLASS_COMMUNICATIONS_MODEM, NULL, }, 153 { "GPIB", PCI_SUBCLASS_COMMUNICATIONS_GPIB, NULL, }, 154 { "smartcard", PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD, NULL, }, 155 { "miscellaneous", PCI_SUBCLASS_COMMUNICATIONS_MISC, NULL, }, 156 { NULL, 0, NULL, }, 157 }; 158 159 static const struct pci_class pci_subclass_system[] = { 160 { "interrupt", PCI_SUBCLASS_SYSTEM_PIC, NULL, }, 161 { "8237 DMA", PCI_SUBCLASS_SYSTEM_DMA, NULL, }, 162 { "8254 timer", PCI_SUBCLASS_SYSTEM_TIMER, NULL, }, 163 { "RTC", PCI_SUBCLASS_SYSTEM_RTC, NULL, }, 164 { "PCI Hot-Plug", PCI_SUBCLASS_SYSTEM_PCIHOTPLUG, NULL, }, 165 { "SD Host Controller", PCI_SUBCLASS_SYSTEM_SDHC, NULL, }, 166 { "miscellaneous", PCI_SUBCLASS_SYSTEM_MISC, NULL, }, 167 { NULL, 0, NULL, }, 168 }; 169 170 static const struct pci_class pci_subclass_input[] = { 171 { "keyboard", PCI_SUBCLASS_INPUT_KEYBOARD, NULL, }, 172 { "digitizer", PCI_SUBCLASS_INPUT_DIGITIZER, NULL, }, 173 { "mouse", PCI_SUBCLASS_INPUT_MOUSE, NULL, }, 174 { "scanner", PCI_SUBCLASS_INPUT_SCANNER, NULL, }, 175 { "game port", PCI_SUBCLASS_INPUT_GAMEPORT, NULL, }, 176 { "miscellaneous", PCI_SUBCLASS_INPUT_MISC, NULL, }, 177 { NULL, 0, NULL, }, 178 }; 179 180 static const struct pci_class pci_subclass_dock[] = { 181 { "generic", PCI_SUBCLASS_DOCK_GENERIC, NULL, }, 182 { "miscellaneous", PCI_SUBCLASS_DOCK_MISC, NULL, }, 183 { NULL, 0, NULL, }, 184 }; 185 186 static const struct pci_class pci_subclass_processor[] = { 187 { "386", PCI_SUBCLASS_PROCESSOR_386, NULL, }, 188 { "486", PCI_SUBCLASS_PROCESSOR_486, NULL, }, 189 { "Pentium", PCI_SUBCLASS_PROCESSOR_PENTIUM, NULL, }, 190 { "Alpha", PCI_SUBCLASS_PROCESSOR_ALPHA, NULL, }, 191 { "PowerPC", PCI_SUBCLASS_PROCESSOR_POWERPC, NULL, }, 192 { "MIPS", PCI_SUBCLASS_PROCESSOR_MIPS, NULL, }, 193 { "Co-processor", PCI_SUBCLASS_PROCESSOR_COPROC, NULL, }, 194 { NULL, 0, NULL, }, 195 }; 196 197 static const struct pci_class pci_subclass_serialbus[] = { 198 { "Firewire", PCI_SUBCLASS_SERIALBUS_FIREWIRE, NULL, }, 199 { "ACCESS.bus", PCI_SUBCLASS_SERIALBUS_ACCESS, NULL, }, 200 { "SSA", PCI_SUBCLASS_SERIALBUS_SSA, NULL, }, 201 { "USB", PCI_SUBCLASS_SERIALBUS_USB, NULL, }, 202 /* XXX Fiber Channel/_FIBRECHANNEL */ 203 { "Fiber Channel", PCI_SUBCLASS_SERIALBUS_FIBER, NULL, }, 204 { "SMBus", PCI_SUBCLASS_SERIALBUS_SMBUS, NULL, }, 205 { "InfiniBand", PCI_SUBCLASS_SERIALBUS_INFINIBAND, NULL,}, 206 { "IPMI", PCI_SUBCLASS_SERIALBUS_IPMI, NULL, }, 207 { "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, }, 208 { "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, }, 209 { NULL, 0, NULL, }, 210 }; 211 212 static const struct pci_class pci_subclass_wireless[] = { 213 { "IrDA", PCI_SUBCLASS_WIRELESS_IRDA, NULL, }, 214 { "Consumer IR", PCI_SUBCLASS_WIRELESS_CONSUMERIR, NULL, }, 215 { "RF", PCI_SUBCLASS_WIRELESS_RF, NULL, }, 216 { "bluetooth", PCI_SUBCLASS_WIRELESS_BLUETOOTH, NULL, }, 217 { "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, }, 218 { "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, }, 219 { "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, }, 220 { "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, }, 221 { NULL, 0, NULL, }, 222 }; 223 224 static const struct pci_class pci_subclass_i2o[] = { 225 { "standard", PCI_SUBCLASS_I2O_STANDARD, NULL, }, 226 { NULL, 0, NULL, }, 227 }; 228 229 static const struct pci_class pci_subclass_satcom[] = { 230 { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, }, 231 { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, }, 232 { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, }, 233 { "data", PCI_SUBCLASS_SATCOM_DATA, NULL, }, 234 { NULL, 0, NULL, }, 235 }; 236 237 static const struct pci_class pci_subclass_crypto[] = { 238 { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, }, 239 { "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,}, 240 { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, }, 241 { NULL, 0, NULL, }, 242 }; 243 244 static const struct pci_class pci_subclass_dasp[] = { 245 { "DPIO", PCI_SUBCLASS_DASP_DPIO, NULL, }, 246 { "Time and Frequency", PCI_SUBCLASS_DASP_TIMEFREQ, NULL, }, 247 { "synchronization", PCI_SUBCLASS_DASP_SYNC, NULL, }, 248 { "management", PCI_SUBCLASS_DASP_MGMT, NULL, }, 249 { "miscellaneous", PCI_SUBCLASS_DASP_MISC, NULL, }, 250 { NULL, 0, NULL, }, 251 }; 252 253 static const struct pci_class pci_class[] = { 254 { "prehistoric", PCI_CLASS_PREHISTORIC, 255 pci_subclass_prehistoric, }, 256 { "mass storage", PCI_CLASS_MASS_STORAGE, 257 pci_subclass_mass_storage, }, 258 { "network", PCI_CLASS_NETWORK, 259 pci_subclass_network, }, 260 { "display", PCI_CLASS_DISPLAY, 261 pci_subclass_display, }, 262 { "multimedia", PCI_CLASS_MULTIMEDIA, 263 pci_subclass_multimedia, }, 264 { "memory", PCI_CLASS_MEMORY, 265 pci_subclass_memory, }, 266 { "bridge", PCI_CLASS_BRIDGE, 267 pci_subclass_bridge, }, 268 { "communications", PCI_CLASS_COMMUNICATIONS, 269 pci_subclass_communications, }, 270 { "system", PCI_CLASS_SYSTEM, 271 pci_subclass_system, }, 272 { "input", PCI_CLASS_INPUT, 273 pci_subclass_input, }, 274 { "dock", PCI_CLASS_DOCK, 275 pci_subclass_dock, }, 276 { "processor", PCI_CLASS_PROCESSOR, 277 pci_subclass_processor, }, 278 { "serial bus", PCI_CLASS_SERIALBUS, 279 pci_subclass_serialbus, }, 280 { "wireless", PCI_CLASS_WIRELESS, 281 pci_subclass_wireless, }, 282 { "I2O", PCI_CLASS_I2O, 283 pci_subclass_i2o, }, 284 { "satellite comm", PCI_CLASS_SATCOM, 285 pci_subclass_satcom, }, 286 { "crypto", PCI_CLASS_CRYPTO, 287 pci_subclass_crypto, }, 288 { "DASP", PCI_CLASS_DASP, 289 pci_subclass_dasp, }, 290 { "undefined", PCI_CLASS_UNDEFINED, 291 NULL, }, 292 { NULL, 0, 293 NULL, }, 294 }; 295 296 void pci_load_verbose(void); 297 298 #if defined(_KERNEL) 299 /* 300 * In kernel, these routines are provided and linked via the 301 * pciverbose module. 302 */ 303 const char *pci_findvendor_stub(pcireg_t); 304 const char *pci_findproduct_stub(pcireg_t); 305 306 const char *(*pci_findvendor)(pcireg_t) = pci_findvendor_stub; 307 const char *(*pci_findproduct)(pcireg_t) = pci_findproduct_stub; 308 const char *pci_unmatched = ""; 309 #else 310 /* 311 * For userland we just set the vectors here. 312 */ 313 const char *(*pci_findvendor)(pcireg_t id_reg) = pci_findvendor_real; 314 const char *(*pci_findproduct)(pcireg_t id_reg) = pci_findproduct_real; 315 const char *pci_unmatched = "unmatched "; 316 #endif 317 318 int pciverbose_loaded = 0; 319 320 #if defined(_KERNEL) 321 /* 322 * Routine to load the pciverbose kernel module as needed 323 */ 324 void pci_load_verbose(void) 325 { 326 if (pciverbose_loaded == 0) 327 module_autoload("pciverbose", MODULE_CLASS_MISC); 328 } 329 330 const char *pci_findvendor_stub(pcireg_t id_reg) 331 { 332 pci_load_verbose(); 333 if (pciverbose_loaded) 334 return pci_findvendor(id_reg); 335 else 336 return NULL; 337 } 338 339 const char *pci_findproduct_stub(pcireg_t id_reg) 340 { 341 pci_load_verbose(); 342 if (pciverbose_loaded) 343 return pci_findproduct(id_reg); 344 else 345 return NULL; 346 } 347 #endif 348 349 void 350 pci_devinfo(pcireg_t id_reg, pcireg_t class_reg, int showclass, char *cp, 351 size_t l) 352 { 353 pci_vendor_id_t vendor; 354 pci_product_id_t product; 355 pci_class_t class; 356 pci_subclass_t subclass; 357 pci_interface_t interface; 358 pci_revision_t revision; 359 const char *unmatched = pci_unmatched; 360 const char *vendor_namep, *product_namep; 361 const struct pci_class *classp, *subclassp; 362 char *ep; 363 364 ep = cp + l; 365 366 vendor = PCI_VENDOR(id_reg); 367 product = PCI_PRODUCT(id_reg); 368 369 class = PCI_CLASS(class_reg); 370 subclass = PCI_SUBCLASS(class_reg); 371 interface = PCI_INTERFACE(class_reg); 372 revision = PCI_REVISION(class_reg); 373 374 vendor_namep = pci_findvendor(id_reg); 375 product_namep = pci_findproduct(id_reg); 376 377 classp = pci_class; 378 while (classp->name != NULL) { 379 if (class == classp->val) 380 break; 381 classp++; 382 } 383 384 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 385 while (subclassp && subclassp->name != NULL) { 386 if (subclass == subclassp->val) 387 break; 388 subclassp++; 389 } 390 391 if (vendor_namep == NULL) 392 cp += snprintf(cp, ep - cp, "%svendor 0x%04x product 0x%04x", 393 unmatched, vendor, product); 394 else if (product_namep != NULL) 395 cp += snprintf(cp, ep - cp, "%s %s", vendor_namep, 396 product_namep); 397 else 398 cp += snprintf(cp, ep - cp, "%s product 0x%04x", 399 vendor_namep, product); 400 if (showclass) { 401 cp += snprintf(cp, ep - cp, " ("); 402 if (classp->name == NULL) 403 cp += snprintf(cp, ep - cp, 404 "class 0x%02x, subclass 0x%02x", class, subclass); 405 else { 406 if (subclassp == NULL || subclassp->name == NULL) 407 cp += snprintf(cp, ep - cp, 408 "%s, subclass 0x%02x", 409 classp->name, subclass); 410 else 411 cp += snprintf(cp, ep - cp, "%s %s", 412 subclassp->name, classp->name); 413 } 414 if (interface != 0) 415 cp += snprintf(cp, ep - cp, ", interface 0x%02x", 416 interface); 417 if (revision != 0) 418 cp += snprintf(cp, ep - cp, ", revision 0x%02x", 419 revision); 420 cp += snprintf(cp, ep - cp, ")"); 421 } 422 } 423 424 #ifdef _KERNEL 425 void 426 pci_aprint_devinfo_fancy(const struct pci_attach_args *pa, const char *naive, 427 const char *known, int addrev) 428 { 429 char devinfo[256]; 430 431 if (known) { 432 aprint_normal(": %s", known); 433 if (addrev) 434 aprint_normal(" (rev. 0x%02x)", 435 PCI_REVISION(pa->pa_class)); 436 aprint_normal("\n"); 437 } else { 438 pci_devinfo(pa->pa_id, pa->pa_class, 0, 439 devinfo, sizeof(devinfo)); 440 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 441 PCI_REVISION(pa->pa_class)); 442 } 443 if (naive) 444 aprint_naive(": %s\n", naive); 445 else 446 aprint_naive("\n"); 447 } 448 #endif 449 450 /* 451 * Print out most of the PCI configuration registers. Typically used 452 * in a device attach routine like this: 453 * 454 * #ifdef MYDEV_DEBUG 455 * printf("%s: ", device_xname(&sc->sc_dev)); 456 * pci_conf_print(pa->pa_pc, pa->pa_tag, NULL); 457 * #endif 458 */ 459 460 #define i2o(i) ((i) * 4) 461 #define o2i(o) ((o) / 4) 462 #define onoff2(str, bit, onstr, offstr) \ 463 printf(" %s: %s\n", (str), (rval & (bit)) ? onstr : offstr); 464 #define onoff(str, bit) onoff2(str, bit, "on", "off") 465 466 static void 467 pci_conf_print_common( 468 #ifdef _KERNEL 469 pci_chipset_tag_t pc, pcitag_t tag, 470 #endif 471 const pcireg_t *regs) 472 { 473 const char *name; 474 const struct pci_class *classp, *subclassp; 475 pcireg_t rval; 476 477 rval = regs[o2i(PCI_ID_REG)]; 478 name = pci_findvendor(rval); 479 if (name) 480 printf(" Vendor Name: %s (0x%04x)\n", name, 481 PCI_VENDOR(rval)); 482 else 483 printf(" Vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 484 name = pci_findproduct(rval); 485 if (name) 486 printf(" Device Name: %s (0x%04x)\n", name, 487 PCI_PRODUCT(rval)); 488 else 489 printf(" Device ID: 0x%04x\n", PCI_PRODUCT(rval)); 490 491 rval = regs[o2i(PCI_COMMAND_STATUS_REG)]; 492 493 printf(" Command register: 0x%04x\n", rval & 0xffff); 494 onoff("I/O space accesses", PCI_COMMAND_IO_ENABLE); 495 onoff("Memory space accesses", PCI_COMMAND_MEM_ENABLE); 496 onoff("Bus mastering", PCI_COMMAND_MASTER_ENABLE); 497 onoff("Special cycles", PCI_COMMAND_SPECIAL_ENABLE); 498 onoff("MWI transactions", PCI_COMMAND_INVALIDATE_ENABLE); 499 onoff("Palette snooping", PCI_COMMAND_PALETTE_ENABLE); 500 onoff("Parity error checking", PCI_COMMAND_PARITY_ENABLE); 501 onoff("Address/data stepping", PCI_COMMAND_STEPPING_ENABLE); 502 onoff("System error (SERR)", PCI_COMMAND_SERR_ENABLE); 503 onoff("Fast back-to-back transactions", PCI_COMMAND_BACKTOBACK_ENABLE); 504 onoff("Interrupt disable", PCI_COMMAND_INTERRUPT_DISABLE); 505 506 printf(" Status register: 0x%04x\n", (rval >> 16) & 0xffff); 507 onoff2("Interrupt status", PCI_STATUS_INT_STATUS, "active", "inactive"); 508 onoff("Capability List support", PCI_STATUS_CAPLIST_SUPPORT); 509 onoff("66 MHz capable", PCI_STATUS_66MHZ_SUPPORT); 510 onoff("User Definable Features (UDF) support", PCI_STATUS_UDF_SUPPORT); 511 onoff("Fast back-to-back capable", PCI_STATUS_BACKTOBACK_SUPPORT); 512 onoff("Data parity error detected", PCI_STATUS_PARITY_ERROR); 513 514 printf(" DEVSEL timing: "); 515 switch (rval & PCI_STATUS_DEVSEL_MASK) { 516 case PCI_STATUS_DEVSEL_FAST: 517 printf("fast"); 518 break; 519 case PCI_STATUS_DEVSEL_MEDIUM: 520 printf("medium"); 521 break; 522 case PCI_STATUS_DEVSEL_SLOW: 523 printf("slow"); 524 break; 525 default: 526 printf("unknown/reserved"); /* XXX */ 527 break; 528 } 529 printf(" (0x%x)\n", (rval & PCI_STATUS_DEVSEL_MASK) >> 25); 530 531 onoff("Slave signaled Target Abort", PCI_STATUS_TARGET_TARGET_ABORT); 532 onoff("Master received Target Abort", PCI_STATUS_MASTER_TARGET_ABORT); 533 onoff("Master received Master Abort", PCI_STATUS_MASTER_ABORT); 534 onoff("Asserted System Error (SERR)", PCI_STATUS_SPECIAL_ERROR); 535 onoff("Parity error detected", PCI_STATUS_PARITY_DETECT); 536 537 rval = regs[o2i(PCI_CLASS_REG)]; 538 for (classp = pci_class; classp->name != NULL; classp++) { 539 if (PCI_CLASS(rval) == classp->val) 540 break; 541 } 542 subclassp = (classp->name != NULL) ? classp->subclasses : NULL; 543 while (subclassp && subclassp->name != NULL) { 544 if (PCI_SUBCLASS(rval) == subclassp->val) 545 break; 546 subclassp++; 547 } 548 if (classp->name != NULL) { 549 printf(" Class Name: %s (0x%02x)\n", classp->name, 550 PCI_CLASS(rval)); 551 if (subclassp != NULL && subclassp->name != NULL) 552 printf(" Subclass Name: %s (0x%02x)\n", 553 subclassp->name, PCI_SUBCLASS(rval)); 554 else 555 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 556 } else { 557 printf(" Class ID: 0x%02x\n", PCI_CLASS(rval)); 558 printf(" Subclass ID: 0x%02x\n", PCI_SUBCLASS(rval)); 559 } 560 printf(" Interface: 0x%02x\n", PCI_INTERFACE(rval)); 561 printf(" Revision ID: 0x%02x\n", PCI_REVISION(rval)); 562 563 rval = regs[o2i(PCI_BHLC_REG)]; 564 printf(" BIST: 0x%02x\n", PCI_BIST(rval)); 565 printf(" Header Type: 0x%02x%s (0x%02x)\n", PCI_HDRTYPE_TYPE(rval), 566 PCI_HDRTYPE_MULTIFN(rval) ? "+multifunction" : "", 567 PCI_HDRTYPE(rval)); 568 printf(" Latency Timer: 0x%02x\n", PCI_LATTIMER(rval)); 569 printf(" Cache Line Size: 0x%02x\n", PCI_CACHELINE(rval)); 570 } 571 572 static int 573 pci_conf_print_bar( 574 #ifdef _KERNEL 575 pci_chipset_tag_t pc, pcitag_t tag, 576 #endif 577 const pcireg_t *regs, int reg, const char *name 578 #ifdef _KERNEL 579 , int sizebar 580 #endif 581 ) 582 { 583 int width; 584 pcireg_t rval, rval64h; 585 #ifdef _KERNEL 586 int s; 587 pcireg_t mask, mask64h; 588 #endif 589 590 width = 4; 591 592 /* 593 * Section 6.2.5.1, `Address Maps', tells us that: 594 * 595 * 1) The builtin software should have already mapped the 596 * device in a reasonable way. 597 * 598 * 2) A device which wants 2^n bytes of memory will hardwire 599 * the bottom n bits of the address to 0. As recommended, 600 * we write all 1s and see what we get back. 601 */ 602 603 rval = regs[o2i(reg)]; 604 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 605 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 606 rval64h = regs[o2i(reg + 4)]; 607 width = 8; 608 } else 609 rval64h = 0; 610 611 #ifdef _KERNEL 612 /* XXX don't size unknown memory type? */ 613 if (rval != 0 && sizebar) { 614 /* 615 * The following sequence seems to make some devices 616 * (e.g. host bus bridges, which don't normally 617 * have their space mapped) very unhappy, to 618 * the point of crashing the system. 619 * 620 * Therefore, if the mapping register is zero to 621 * start out with, don't bother trying. 622 */ 623 s = splhigh(); 624 pci_conf_write(pc, tag, reg, 0xffffffff); 625 mask = pci_conf_read(pc, tag, reg); 626 pci_conf_write(pc, tag, reg, rval); 627 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM && 628 PCI_MAPREG_MEM_TYPE(rval) == PCI_MAPREG_MEM_TYPE_64BIT) { 629 pci_conf_write(pc, tag, reg + 4, 0xffffffff); 630 mask64h = pci_conf_read(pc, tag, reg + 4); 631 pci_conf_write(pc, tag, reg + 4, rval64h); 632 } else 633 mask64h = 0; 634 splx(s); 635 } else 636 mask = mask64h = 0; 637 #endif /* _KERNEL */ 638 639 printf(" Base address register at 0x%02x", reg); 640 if (name) 641 printf(" (%s)", name); 642 printf("\n "); 643 if (rval == 0) { 644 printf("not implemented(?)\n"); 645 return width; 646 } 647 printf("type: "); 648 if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM) { 649 const char *type, *prefetch; 650 651 switch (PCI_MAPREG_MEM_TYPE(rval)) { 652 case PCI_MAPREG_MEM_TYPE_32BIT: 653 type = "32-bit"; 654 break; 655 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 656 type = "32-bit-1M"; 657 break; 658 case PCI_MAPREG_MEM_TYPE_64BIT: 659 type = "64-bit"; 660 break; 661 default: 662 type = "unknown (XXX)"; 663 break; 664 } 665 if (PCI_MAPREG_MEM_PREFETCHABLE(rval)) 666 prefetch = ""; 667 else 668 prefetch = "non"; 669 printf("%s %sprefetchable memory\n", type, prefetch); 670 switch (PCI_MAPREG_MEM_TYPE(rval)) { 671 case PCI_MAPREG_MEM_TYPE_64BIT: 672 printf(" base: 0x%016llx, ", 673 PCI_MAPREG_MEM64_ADDR( 674 ((((long long) rval64h) << 32) | rval))); 675 #ifdef _KERNEL 676 if (sizebar) 677 printf("size: 0x%016llx", 678 PCI_MAPREG_MEM64_SIZE( 679 ((((long long) mask64h) << 32) | mask))); 680 else 681 #endif /* _KERNEL */ 682 printf("not sized"); 683 printf("\n"); 684 break; 685 case PCI_MAPREG_MEM_TYPE_32BIT: 686 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 687 default: 688 printf(" base: 0x%08x, ", 689 PCI_MAPREG_MEM_ADDR(rval)); 690 #ifdef _KERNEL 691 if (sizebar) 692 printf("size: 0x%08x", 693 PCI_MAPREG_MEM_SIZE(mask)); 694 else 695 #endif /* _KERNEL */ 696 printf("not sized"); 697 printf("\n"); 698 break; 699 } 700 } else { 701 #ifdef _KERNEL 702 if (sizebar) 703 printf("%d-bit ", mask & ~0x0000ffff ? 32 : 16); 704 #endif /* _KERNEL */ 705 printf("i/o\n"); 706 printf(" base: 0x%08x, ", PCI_MAPREG_IO_ADDR(rval)); 707 #ifdef _KERNEL 708 if (sizebar) 709 printf("size: 0x%08x", PCI_MAPREG_IO_SIZE(mask)); 710 else 711 #endif /* _KERNEL */ 712 printf("not sized"); 713 printf("\n"); 714 } 715 716 return width; 717 } 718 719 static void 720 pci_conf_print_regs(const pcireg_t *regs, int first, int pastlast) 721 { 722 int off, needaddr, neednl; 723 724 needaddr = 1; 725 neednl = 0; 726 for (off = first; off < pastlast; off += 4) { 727 if ((off % 16) == 0 || needaddr) { 728 printf(" 0x%02x:", off); 729 needaddr = 0; 730 } 731 printf(" 0x%08x", regs[o2i(off)]); 732 neednl = 1; 733 if ((off % 16) == 12) { 734 printf("\n"); 735 neednl = 0; 736 } 737 } 738 if (neednl) 739 printf("\n"); 740 } 741 742 static void 743 pci_conf_print_type0( 744 #ifdef _KERNEL 745 pci_chipset_tag_t pc, pcitag_t tag, 746 #endif 747 const pcireg_t *regs 748 #ifdef _KERNEL 749 , int sizebars 750 #endif 751 ) 752 { 753 int off, width; 754 pcireg_t rval; 755 756 for (off = PCI_MAPREG_START; off < PCI_MAPREG_END; off += width) { 757 #ifdef _KERNEL 758 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 759 #else 760 width = pci_conf_print_bar(regs, off, NULL); 761 #endif 762 } 763 764 printf(" Cardbus CIS Pointer: 0x%08x\n", regs[o2i(0x28)]); 765 766 rval = regs[o2i(PCI_SUBSYS_ID_REG)]; 767 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 768 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 769 770 /* XXX */ 771 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x30)]); 772 773 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 774 printf(" Capability list pointer: 0x%02x\n", 775 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 776 else 777 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 778 779 printf(" Reserved @ 0x38: 0x%08x\n", regs[o2i(0x38)]); 780 781 rval = regs[o2i(PCI_INTERRUPT_REG)]; 782 printf(" Maximum Latency: 0x%02x\n", (rval >> 24) & 0xff); 783 printf(" Minimum Grant: 0x%02x\n", (rval >> 16) & 0xff); 784 printf(" Interrupt pin: 0x%02x ", PCI_INTERRUPT_PIN(rval)); 785 switch (PCI_INTERRUPT_PIN(rval)) { 786 case PCI_INTERRUPT_PIN_NONE: 787 printf("(none)"); 788 break; 789 case PCI_INTERRUPT_PIN_A: 790 printf("(pin A)"); 791 break; 792 case PCI_INTERRUPT_PIN_B: 793 printf("(pin B)"); 794 break; 795 case PCI_INTERRUPT_PIN_C: 796 printf("(pin C)"); 797 break; 798 case PCI_INTERRUPT_PIN_D: 799 printf("(pin D)"); 800 break; 801 default: 802 printf("(? ? ?)"); 803 break; 804 } 805 printf("\n"); 806 printf(" Interrupt line: 0x%02x\n", PCI_INTERRUPT_LINE(rval)); 807 } 808 809 static void 810 pci_conf_print_pcie_cap(const pcireg_t *regs, int capoff) 811 { 812 bool check_slot = false; 813 814 printf("\n PCI Express Capabilities Register\n"); 815 printf(" Capability version: %x\n", 816 (unsigned int)((regs[o2i(capoff)] & 0x000f0000) >> 16)); 817 printf(" Device type: "); 818 switch ((regs[o2i(capoff)] & 0x00f00000) >> 20) { 819 case 0x0: 820 printf("PCI Express Endpoint device\n"); 821 break; 822 case 0x1: 823 printf("Legacy PCI Express Endpoint device\n"); 824 break; 825 case 0x4: 826 printf("Root Port of PCI Express Root Complex\n"); 827 check_slot = true; 828 break; 829 case 0x5: 830 printf("Upstream Port of PCI Express Switch\n"); 831 break; 832 case 0x6: 833 printf("Downstream Port of PCI Express Switch\n"); 834 check_slot = true; 835 break; 836 case 0x7: 837 printf("PCI Express to PCI/PCI-X Bridge\n"); 838 break; 839 case 0x8: 840 printf("PCI/PCI-X to PCI Express Bridge\n"); 841 break; 842 default: 843 printf("unknown\n"); 844 break; 845 } 846 if (check_slot && (regs[o2i(capoff)] & 0x01000000) != 0) 847 printf(" Slot implemented\n"); 848 printf(" Interrupt Message Number: %x\n", 849 (unsigned int)((regs[o2i(capoff)] & 0x4e000000) >> 27)); 850 printf(" Link Capabilities Register: 0x%08x\n", 851 regs[o2i(capoff + 0x0c)]); 852 printf(" Maximum Link Speed: "); 853 if ((regs[o2i(capoff + 0x0c)] & 0x000f) != 1) { 854 printf("unknown %u value\n", 855 (regs[o2i(capoff + 0x0c)] & 0x000f)); 856 } else { 857 printf("2.5Gb/s\n"); 858 } 859 printf(" Maximum Link Width: x%u lanes\n", 860 (regs[o2i(capoff + 0x0c)] & 0x03f0) >> 4); 861 printf(" Port Number: %u\n", regs[o2i(capoff + 0x0c)] >> 24); 862 printf(" Link Status Register: 0x%04x\n", 863 regs[o2i(capoff + 0x10)] >> 16); 864 printf(" Negotiated Link Speed: "); 865 if (((regs[o2i(capoff + 0x10)] >> 16) & 0x000f) != 1) { 866 printf("unknown %u value\n", 867 (regs[o2i(capoff + 0x10)] >> 16) & 0x000f); 868 } else { 869 printf("2.5Gb/s\n"); 870 } 871 printf(" Negotiated Link Width: x%u lanes\n", 872 (regs[o2i(capoff + 0x10)] >> 20) & 0x003f); 873 if ((regs[o2i(capoff + 0x18)] & 0x07ff) != 0) { 874 printf(" Slot Control Register:\n"); 875 if ((regs[o2i(capoff + 0x18)] & 0x0001) != 0) 876 printf(" Attention Button Pressed Enabled\n"); 877 if ((regs[o2i(capoff + 0x18)] & 0x0002) != 0) 878 printf(" Power Fault Detected Enabled\n"); 879 if ((regs[o2i(capoff + 0x18)] & 0x0004) != 0) 880 printf(" MRL Sensor Changed Enabled\n"); 881 if ((regs[o2i(capoff + 0x18)] & 0x0008) != 0) 882 printf(" Presense Detected Changed Enabled\n"); 883 if ((regs[o2i(capoff + 0x18)] & 0x0010) != 0) 884 printf(" Command Completed Interrupt Enabled\n"); 885 if ((regs[o2i(capoff + 0x18)] & 0x0020) != 0) 886 printf(" Hot-Plug Interrupt Enabled\n"); 887 printf(" Attention Indicator Control: "); 888 switch ((regs[o2i(capoff + 0x18)] & 0x00c0) >> 6) { 889 case 0x0: 890 printf("reserved\n"); 891 break; 892 case 0x1: 893 printf("on\n"); 894 break; 895 case 0x2: 896 printf("blink\n"); 897 break; 898 case 0x3: 899 printf("off\n"); 900 break; 901 } 902 printf(" Power Indicator Control: "); 903 switch ((regs[o2i(capoff + 0x18)] & 0x0300) >> 8) { 904 case 0x0: 905 printf("reserved\n"); 906 break; 907 case 0x1: 908 printf("on\n"); 909 break; 910 case 0x2: 911 printf("blink\n"); 912 break; 913 case 0x3: 914 printf("off\n"); 915 break; 916 } 917 printf(" Power Controller Control: "); 918 if ((regs[o2i(capoff + 0x18)] & 0x0400) != 0) 919 printf("off\n"); 920 else 921 printf("on\n"); 922 } 923 } 924 925 static const char * 926 pci_conf_print_pcipm_cap_aux(uint16_t caps) 927 { 928 switch ((caps >> 6) & 7) { 929 case 0: return "self-powered"; 930 case 1: return "55 mA"; 931 case 2: return "100 mA"; 932 case 3: return "160 mA"; 933 case 4: return "220 mA"; 934 case 5: return "270 mA"; 935 case 6: return "320 mA"; 936 case 7: 937 default: return "375 mA"; 938 } 939 } 940 941 static const char * 942 pci_conf_print_pcipm_cap_pmrev(uint8_t val) 943 { 944 static const char unk[] = "unknown"; 945 static const char *pmrev[8] = { 946 unk, "1.0", "1.1", "1.2", unk, unk, unk, unk 947 }; 948 if (val > 7) 949 return unk; 950 return pmrev[val]; 951 } 952 953 static void 954 pci_conf_print_pcipm_cap(const pcireg_t *regs, int capoff) 955 { 956 uint16_t caps, pmcsr; 957 958 caps = regs[o2i(capoff)] >> 16; 959 pmcsr = regs[o2i(capoff + 0x04)] & 0xffff; 960 961 printf("\n PCI Power Management Capabilities Register\n"); 962 963 printf(" Capabilities register: 0x%04x\n", caps); 964 printf(" Version: %s\n", 965 pci_conf_print_pcipm_cap_pmrev(caps & 0x3)); 966 printf(" PME# clock: %s\n", caps & 0x4 ? "on" : "off"); 967 printf(" Device specific initialization: %s\n", 968 caps & 0x20 ? "on" : "off"); 969 printf(" 3.3V auxiliary current: %s\n", 970 pci_conf_print_pcipm_cap_aux(caps)); 971 printf(" D1 power management state support: %s\n", 972 (caps >> 9) & 1 ? "on" : "off"); 973 printf(" D2 power management state support: %s\n", 974 (caps >> 10) & 1 ? "on" : "off"); 975 printf(" PME# support: 0x%02x\n", caps >> 11); 976 977 printf(" Control/status register: 0x%04x\n", pmcsr); 978 printf(" Power state: D%d\n", pmcsr & 3); 979 printf(" PCI Express reserved: %s\n", 980 (pmcsr >> 2) & 1 ? "on" : "off"); 981 printf(" No soft reset: %s\n", (pmcsr >> 3) & 1 ? "on" : "off"); 982 printf(" PME# assertion %sabled\n", 983 (pmcsr >> 8) & 1 ? "en" : "dis"); 984 printf(" PME# status: %s\n", (pmcsr >> 15) ? "on" : "off"); 985 } 986 987 static void 988 pci_conf_print_msi_cap(const pcireg_t *regs, int capoff) 989 { 990 uint32_t ctl, mmc, mme; 991 992 regs += o2i(capoff); 993 ctl = *regs++; 994 mmc = __SHIFTOUT(ctl, PCI_MSI_CTL_MMC_MASK); 995 mme = __SHIFTOUT(ctl, PCI_MSI_CTL_MME_MASK); 996 997 printf("\n PCI Message Signaled Interrupt\n"); 998 999 printf(" Message Control register: 0x%04x\n", ctl >> 16); 1000 printf(" MSI Enabled: %s\n", 1001 ctl & PCI_MSI_CTL_MSI_ENABLE ? "yes" : "no"); 1002 printf(" Multiple Message Capable: %s (%d vector%s)\n", 1003 mmc > 0 ? "yes" : "no", 1 << mmc, mmc > 0 ? "s" : ""); 1004 printf(" Multiple Message Enabled: %s (%d vector%s)\n", 1005 mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : ""); 1006 printf(" 64 Bit Address Capable: %s\n", 1007 ctl & PCI_MSI_CTL_64BIT_ADDR ? "yes" : "no"); 1008 printf(" Per-Vector Masking Capable: %s\n", 1009 ctl & PCI_MSI_CTL_PERVEC_MASK ? "yes" : "no"); 1010 printf(" Message Address %sregister: 0x%08x\n", 1011 ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++); 1012 if (ctl & PCI_MSI_CTL_64BIT_ADDR) { 1013 printf(" Message Address %sregister: 0x%08x\n", 1014 "(upper) ", *regs++); 1015 } 1016 printf(" Message Data register: 0x%08x\n", *regs++); 1017 if (ctl & PCI_MSI_CTL_PERVEC_MASK) { 1018 printf(" Vector Mask register: 0x%08x\n", *regs++); 1019 printf(" Vector Pending register: 0x%08x\n", *regs++); 1020 } 1021 } 1022 static void 1023 pci_conf_print_caplist( 1024 #ifdef _KERNEL 1025 pci_chipset_tag_t pc, pcitag_t tag, 1026 #endif 1027 const pcireg_t *regs, int capoff) 1028 { 1029 int off; 1030 pcireg_t rval; 1031 int pcie_off = -1, pcipm_off = -1, msi_off = -1; 1032 1033 for (off = PCI_CAPLIST_PTR(regs[o2i(capoff)]); 1034 off != 0; 1035 off = PCI_CAPLIST_NEXT(regs[o2i(off)])) { 1036 rval = regs[o2i(off)]; 1037 printf(" Capability register at 0x%02x\n", off); 1038 1039 printf(" type: 0x%02x (", PCI_CAPLIST_CAP(rval)); 1040 switch (PCI_CAPLIST_CAP(rval)) { 1041 case PCI_CAP_RESERVED0: 1042 printf("reserved"); 1043 break; 1044 case PCI_CAP_PWRMGMT: 1045 printf("Power Management, rev. %s", 1046 pci_conf_print_pcipm_cap_pmrev((rval >> 0) & 0x07)); 1047 pcipm_off = off; 1048 break; 1049 case PCI_CAP_AGP: 1050 printf("AGP, rev. %d.%d", 1051 PCI_CAP_AGP_MAJOR(rval), 1052 PCI_CAP_AGP_MINOR(rval)); 1053 break; 1054 case PCI_CAP_VPD: 1055 printf("VPD"); 1056 break; 1057 case PCI_CAP_SLOTID: 1058 printf("SlotID"); 1059 break; 1060 case PCI_CAP_MSI: 1061 printf("MSI"); 1062 msi_off = off; 1063 break; 1064 case PCI_CAP_CPCI_HOTSWAP: 1065 printf("CompactPCI Hot-swapping"); 1066 break; 1067 case PCI_CAP_PCIX: 1068 printf("PCI-X"); 1069 break; 1070 case PCI_CAP_LDT: 1071 printf("LDT"); 1072 break; 1073 case PCI_CAP_VENDSPEC: 1074 printf("Vendor-specific"); 1075 break; 1076 case PCI_CAP_DEBUGPORT: 1077 printf("Debug Port"); 1078 break; 1079 case PCI_CAP_CPCI_RSRCCTL: 1080 printf("CompactPCI Resource Control"); 1081 break; 1082 case PCI_CAP_HOTPLUG: 1083 printf("Hot-Plug"); 1084 break; 1085 case PCI_CAP_AGP8: 1086 printf("AGP 8x"); 1087 break; 1088 case PCI_CAP_SECURE: 1089 printf("Secure Device"); 1090 break; 1091 case PCI_CAP_PCIEXPRESS: 1092 printf("PCI Express"); 1093 pcie_off = off; 1094 break; 1095 case PCI_CAP_MSIX: 1096 printf("MSI-X"); 1097 break; 1098 case PCI_CAP_SATA: 1099 printf("SATA"); 1100 break; 1101 case PCI_CAP_PCIAF: 1102 printf("Advanced Features"); 1103 break; 1104 default: 1105 printf("unknown"); 1106 } 1107 printf(")\n"); 1108 } 1109 if (msi_off != -1) 1110 pci_conf_print_msi_cap(regs, msi_off); 1111 if (pcipm_off != -1) 1112 pci_conf_print_pcipm_cap(regs, pcipm_off); 1113 if (pcie_off != -1) 1114 pci_conf_print_pcie_cap(regs, pcie_off); 1115 } 1116 1117 /* Print the Secondary Status Register. */ 1118 static void 1119 pci_conf_print_ssr(pcireg_t rval) 1120 { 1121 pcireg_t devsel; 1122 1123 printf(" Secondary status register: 0x%04x\n", rval); /* XXX bits */ 1124 onoff("66 MHz capable", __BIT(5)); 1125 onoff("User Definable Features (UDF) support", __BIT(6)); 1126 onoff("Fast back-to-back capable", __BIT(7)); 1127 onoff("Data parity error detected", __BIT(8)); 1128 1129 printf(" DEVSEL timing: "); 1130 devsel = __SHIFTOUT(rval, __BITS(10, 9)); 1131 switch (devsel) { 1132 case 0: 1133 printf("fast"); 1134 break; 1135 case 1: 1136 printf("medium"); 1137 break; 1138 case 2: 1139 printf("slow"); 1140 break; 1141 default: 1142 printf("unknown/reserved"); /* XXX */ 1143 break; 1144 } 1145 printf(" (0x%x)\n", devsel); 1146 1147 onoff("Signalled target abort", __BIT(11)); 1148 onoff("Received target abort", __BIT(12)); 1149 onoff("Received master abort", __BIT(13)); 1150 onoff("Received system error", __BIT(14)); 1151 onoff("Detected parity error", __BIT(15)); 1152 } 1153 1154 static void 1155 pci_conf_print_type1( 1156 #ifdef _KERNEL 1157 pci_chipset_tag_t pc, pcitag_t tag, 1158 #endif 1159 const pcireg_t *regs 1160 #ifdef _KERNEL 1161 , int sizebars 1162 #endif 1163 ) 1164 { 1165 int off, width; 1166 pcireg_t rval; 1167 1168 /* 1169 * XXX these need to be printed in more detail, need to be 1170 * XXX checked against specs/docs, etc. 1171 * 1172 * This layout was cribbed from the TI PCI2030 PCI-to-PCI 1173 * Bridge chip documentation, and may not be correct with 1174 * respect to various standards. (XXX) 1175 */ 1176 1177 for (off = 0x10; off < 0x18; off += width) { 1178 #ifdef _KERNEL 1179 width = pci_conf_print_bar(pc, tag, regs, off, NULL, sizebars); 1180 #else 1181 width = pci_conf_print_bar(regs, off, NULL); 1182 #endif 1183 } 1184 1185 printf(" Primary bus number: 0x%02x\n", 1186 (regs[o2i(0x18)] >> 0) & 0xff); 1187 printf(" Secondary bus number: 0x%02x\n", 1188 (regs[o2i(0x18)] >> 8) & 0xff); 1189 printf(" Subordinate bus number: 0x%02x\n", 1190 (regs[o2i(0x18)] >> 16) & 0xff); 1191 printf(" Secondary bus latency timer: 0x%02x\n", 1192 (regs[o2i(0x18)] >> 24) & 0xff); 1193 1194 pci_conf_print_ssr(__SHIFTOUT(regs[o2i(0x1c)], __BITS(31, 16))); 1195 1196 /* XXX Print more prettily */ 1197 printf(" I/O region:\n"); 1198 printf(" base register: 0x%02x\n", (regs[o2i(0x1c)] >> 0) & 0xff); 1199 printf(" limit register: 0x%02x\n", (regs[o2i(0x1c)] >> 8) & 0xff); 1200 printf(" base upper 16 bits register: 0x%04x\n", 1201 (regs[o2i(0x30)] >> 0) & 0xffff); 1202 printf(" limit upper 16 bits register: 0x%04x\n", 1203 (regs[o2i(0x30)] >> 16) & 0xffff); 1204 1205 /* XXX Print more prettily */ 1206 printf(" Memory region:\n"); 1207 printf(" base register: 0x%04x\n", 1208 (regs[o2i(0x20)] >> 0) & 0xffff); 1209 printf(" limit register: 0x%04x\n", 1210 (regs[o2i(0x20)] >> 16) & 0xffff); 1211 1212 /* XXX Print more prettily */ 1213 printf(" Prefetchable memory region:\n"); 1214 printf(" base register: 0x%04x\n", 1215 (regs[o2i(0x24)] >> 0) & 0xffff); 1216 printf(" limit register: 0x%04x\n", 1217 (regs[o2i(0x24)] >> 16) & 0xffff); 1218 printf(" base upper 32 bits register: 0x%08x\n", regs[o2i(0x28)]); 1219 printf(" limit upper 32 bits register: 0x%08x\n", regs[o2i(0x2c)]); 1220 1221 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1222 printf(" Capability list pointer: 0x%02x\n", 1223 PCI_CAPLIST_PTR(regs[o2i(PCI_CAPLISTPTR_REG)])); 1224 else 1225 printf(" Reserved @ 0x34: 0x%08x\n", regs[o2i(0x34)]); 1226 1227 /* XXX */ 1228 printf(" Expansion ROM Base Address: 0x%08x\n", regs[o2i(0x38)]); 1229 1230 printf(" Interrupt line: 0x%02x\n", 1231 (regs[o2i(0x3c)] >> 0) & 0xff); 1232 printf(" Interrupt pin: 0x%02x ", 1233 (regs[o2i(0x3c)] >> 8) & 0xff); 1234 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1235 case PCI_INTERRUPT_PIN_NONE: 1236 printf("(none)"); 1237 break; 1238 case PCI_INTERRUPT_PIN_A: 1239 printf("(pin A)"); 1240 break; 1241 case PCI_INTERRUPT_PIN_B: 1242 printf("(pin B)"); 1243 break; 1244 case PCI_INTERRUPT_PIN_C: 1245 printf("(pin C)"); 1246 break; 1247 case PCI_INTERRUPT_PIN_D: 1248 printf("(pin D)"); 1249 break; 1250 default: 1251 printf("(? ? ?)"); 1252 break; 1253 } 1254 printf("\n"); 1255 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1256 printf(" Bridge control register: 0x%04x\n", rval); /* XXX bits */ 1257 onoff("Parity error response", 0x0001); 1258 onoff("Secondary SERR forwarding", 0x0002); 1259 onoff("ISA enable", 0x0004); 1260 onoff("VGA enable", 0x0008); 1261 onoff("Master abort reporting", 0x0020); 1262 onoff("Secondary bus reset", 0x0040); 1263 onoff("Fast back-to-back capable", 0x0080); 1264 } 1265 1266 static void 1267 pci_conf_print_type2( 1268 #ifdef _KERNEL 1269 pci_chipset_tag_t pc, pcitag_t tag, 1270 #endif 1271 const pcireg_t *regs 1272 #ifdef _KERNEL 1273 , int sizebars 1274 #endif 1275 ) 1276 { 1277 pcireg_t rval; 1278 1279 /* 1280 * XXX these need to be printed in more detail, need to be 1281 * XXX checked against specs/docs, etc. 1282 * 1283 * This layout was cribbed from the TI PCI1420 PCI-to-CardBus 1284 * controller chip documentation, and may not be correct with 1285 * respect to various standards. (XXX) 1286 */ 1287 1288 #ifdef _KERNEL 1289 pci_conf_print_bar(pc, tag, regs, 0x10, 1290 "CardBus socket/ExCA registers", sizebars); 1291 #else 1292 pci_conf_print_bar(regs, 0x10, "CardBus socket/ExCA registers"); 1293 #endif 1294 1295 if (regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1296 printf(" Capability list pointer: 0x%02x\n", 1297 PCI_CAPLIST_PTR(regs[o2i(PCI_CARDBUS_CAPLISTPTR_REG)])); 1298 else 1299 printf(" Reserved @ 0x14: 0x%04" PRIxMAX "\n", 1300 __SHIFTOUT(regs[o2i(0x14)], __BITS(15, 0))); 1301 pci_conf_print_ssr(__SHIFTOUT(regs[o2i(0x14)], __BITS(31, 16))); 1302 1303 printf(" PCI bus number: 0x%02x\n", 1304 (regs[o2i(0x18)] >> 0) & 0xff); 1305 printf(" CardBus bus number: 0x%02x\n", 1306 (regs[o2i(0x18)] >> 8) & 0xff); 1307 printf(" Subordinate bus number: 0x%02x\n", 1308 (regs[o2i(0x18)] >> 16) & 0xff); 1309 printf(" CardBus latency timer: 0x%02x\n", 1310 (regs[o2i(0x18)] >> 24) & 0xff); 1311 1312 /* XXX Print more prettily */ 1313 printf(" CardBus memory region 0:\n"); 1314 printf(" base register: 0x%08x\n", regs[o2i(0x1c)]); 1315 printf(" limit register: 0x%08x\n", regs[o2i(0x20)]); 1316 printf(" CardBus memory region 1:\n"); 1317 printf(" base register: 0x%08x\n", regs[o2i(0x24)]); 1318 printf(" limit register: 0x%08x\n", regs[o2i(0x28)]); 1319 printf(" CardBus I/O region 0:\n"); 1320 printf(" base register: 0x%08x\n", regs[o2i(0x2c)]); 1321 printf(" limit register: 0x%08x\n", regs[o2i(0x30)]); 1322 printf(" CardBus I/O region 1:\n"); 1323 printf(" base register: 0x%08x\n", regs[o2i(0x34)]); 1324 printf(" limit register: 0x%08x\n", regs[o2i(0x38)]); 1325 1326 printf(" Interrupt line: 0x%02x\n", 1327 (regs[o2i(0x3c)] >> 0) & 0xff); 1328 printf(" Interrupt pin: 0x%02x ", 1329 (regs[o2i(0x3c)] >> 8) & 0xff); 1330 switch ((regs[o2i(0x3c)] >> 8) & 0xff) { 1331 case PCI_INTERRUPT_PIN_NONE: 1332 printf("(none)"); 1333 break; 1334 case PCI_INTERRUPT_PIN_A: 1335 printf("(pin A)"); 1336 break; 1337 case PCI_INTERRUPT_PIN_B: 1338 printf("(pin B)"); 1339 break; 1340 case PCI_INTERRUPT_PIN_C: 1341 printf("(pin C)"); 1342 break; 1343 case PCI_INTERRUPT_PIN_D: 1344 printf("(pin D)"); 1345 break; 1346 default: 1347 printf("(? ? ?)"); 1348 break; 1349 } 1350 printf("\n"); 1351 rval = (regs[o2i(0x3c)] >> 16) & 0xffff; 1352 printf(" Bridge control register: 0x%04x\n", rval); 1353 onoff("Parity error response", __BIT(0)); 1354 onoff("SERR# enable", __BIT(1)); 1355 onoff("ISA enable", __BIT(2)); 1356 onoff("VGA enable", __BIT(3)); 1357 onoff("Master abort mode", __BIT(5)); 1358 onoff("Secondary (CardBus) bus reset", __BIT(6)); 1359 onoff("Functional interrupts routed by ExCA registers", __BIT(7)); 1360 onoff("Memory window 0 prefetchable", __BIT(8)); 1361 onoff("Memory window 1 prefetchable", __BIT(9)); 1362 onoff("Write posting enable", __BIT(10)); 1363 1364 rval = regs[o2i(0x40)]; 1365 printf(" Subsystem vendor ID: 0x%04x\n", PCI_VENDOR(rval)); 1366 printf(" Subsystem ID: 0x%04x\n", PCI_PRODUCT(rval)); 1367 1368 #ifdef _KERNEL 1369 pci_conf_print_bar(pc, tag, regs, 0x44, "legacy-mode registers", 1370 sizebars); 1371 #else 1372 pci_conf_print_bar(regs, 0x44, "legacy-mode registers"); 1373 #endif 1374 } 1375 1376 void 1377 pci_conf_print( 1378 #ifdef _KERNEL 1379 pci_chipset_tag_t pc, pcitag_t tag, 1380 void (*printfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *) 1381 #else 1382 int pcifd, u_int bus, u_int dev, u_int func 1383 #endif 1384 ) 1385 { 1386 pcireg_t regs[o2i(256)]; 1387 int off, capoff, endoff, hdrtype; 1388 const char *typename; 1389 #ifdef _KERNEL 1390 void (*typeprintfn)(pci_chipset_tag_t, pcitag_t, const pcireg_t *, int); 1391 int sizebars; 1392 #else 1393 void (*typeprintfn)(const pcireg_t *); 1394 #endif 1395 1396 printf("PCI configuration registers:\n"); 1397 1398 for (off = 0; off < 256; off += 4) { 1399 #ifdef _KERNEL 1400 regs[o2i(off)] = pci_conf_read(pc, tag, off); 1401 #else 1402 if (pcibus_conf_read(pcifd, bus, dev, func, off, 1403 ®s[o2i(off)]) == -1) 1404 regs[o2i(off)] = 0; 1405 #endif 1406 } 1407 1408 #ifdef _KERNEL 1409 sizebars = 1; 1410 if (PCI_CLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_CLASS_BRIDGE && 1411 PCI_SUBCLASS(regs[o2i(PCI_CLASS_REG)]) == PCI_SUBCLASS_BRIDGE_HOST) 1412 sizebars = 0; 1413 #endif 1414 1415 /* common header */ 1416 printf(" Common header:\n"); 1417 pci_conf_print_regs(regs, 0, 16); 1418 1419 printf("\n"); 1420 #ifdef _KERNEL 1421 pci_conf_print_common(pc, tag, regs); 1422 #else 1423 pci_conf_print_common(regs); 1424 #endif 1425 printf("\n"); 1426 1427 /* type-dependent header */ 1428 hdrtype = PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]); 1429 switch (hdrtype) { /* XXX make a table, eventually */ 1430 case 0: 1431 /* Standard device header */ 1432 typename = "\"normal\" device"; 1433 typeprintfn = &pci_conf_print_type0; 1434 capoff = PCI_CAPLISTPTR_REG; 1435 endoff = 64; 1436 break; 1437 case 1: 1438 /* PCI-PCI bridge header */ 1439 typename = "PCI-PCI bridge"; 1440 typeprintfn = &pci_conf_print_type1; 1441 capoff = PCI_CAPLISTPTR_REG; 1442 endoff = 64; 1443 break; 1444 case 2: 1445 /* PCI-CardBus bridge header */ 1446 typename = "PCI-CardBus bridge"; 1447 typeprintfn = &pci_conf_print_type2; 1448 capoff = PCI_CARDBUS_CAPLISTPTR_REG; 1449 endoff = 72; 1450 break; 1451 default: 1452 typename = NULL; 1453 typeprintfn = 0; 1454 capoff = -1; 1455 endoff = 64; 1456 break; 1457 } 1458 printf(" Type %d ", hdrtype); 1459 if (typename != NULL) 1460 printf("(%s) ", typename); 1461 printf("header:\n"); 1462 pci_conf_print_regs(regs, 16, endoff); 1463 printf("\n"); 1464 if (typeprintfn) { 1465 #ifdef _KERNEL 1466 (*typeprintfn)(pc, tag, regs, sizebars); 1467 #else 1468 (*typeprintfn)(regs); 1469 #endif 1470 } else 1471 printf(" Don't know how to pretty-print type %d header.\n", 1472 hdrtype); 1473 printf("\n"); 1474 1475 /* capability list, if present */ 1476 if ((regs[o2i(PCI_COMMAND_STATUS_REG)] & PCI_STATUS_CAPLIST_SUPPORT) 1477 && (capoff > 0)) { 1478 #ifdef _KERNEL 1479 pci_conf_print_caplist(pc, tag, regs, capoff); 1480 #else 1481 pci_conf_print_caplist(regs, capoff); 1482 #endif 1483 printf("\n"); 1484 } 1485 1486 /* device-dependent header */ 1487 printf(" Device-dependent header:\n"); 1488 pci_conf_print_regs(regs, endoff, 256); 1489 printf("\n"); 1490 #ifdef _KERNEL 1491 if (printfn) 1492 (*printfn)(pc, tag, regs); 1493 else 1494 printf(" Don't know how to pretty-print device-dependent header.\n"); 1495 printf("\n"); 1496 #endif /* _KERNEL */ 1497 } 1498
Indexes created Wed Sep 24 05:09:52 GMT 2025