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pciconf.c revision 1.34.6.1
      1  1.34.6.1       tls /*	$NetBSD: pciconf.c,v 1.34.6.1 2012/11/20 03:02:20 tls Exp $	*/
      2       1.1    briggs 
      3       1.1    briggs /*
      4       1.1    briggs  * Copyright 2001 Wasabi Systems, Inc.
      5       1.1    briggs  * All rights reserved.
      6       1.1    briggs  *
      7       1.1    briggs  * Written by Allen Briggs for Wasabi Systems, Inc.
      8       1.1    briggs  *
      9       1.1    briggs  * Redistribution and use in source and binary forms, with or without
     10       1.1    briggs  * modification, are permitted provided that the following conditions
     11       1.1    briggs  * are met:
     12       1.1    briggs  * 1. Redistributions of source code must retain the above copyright
     13       1.1    briggs  *    notice, this list of conditions and the following disclaimer.
     14       1.1    briggs  * 2. Redistributions in binary form must reproduce the above copyright
     15       1.1    briggs  *    notice, this list of conditions and the following disclaimer in the
     16       1.1    briggs  *    documentation and/or other materials provided with the distribution.
     17       1.1    briggs  * 3. All advertising materials mentioning features or use of this software
     18       1.1    briggs  *    must display the following acknowledgement:
     19       1.1    briggs  *      This product includes software developed for the NetBSD Project by
     20       1.1    briggs  *      Wasabi Systems, Inc.
     21       1.1    briggs  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     22       1.1    briggs  *    or promote products derived from this software without specific prior
     23       1.1    briggs  *    written permission.
     24       1.1    briggs  *
     25       1.1    briggs  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     26       1.1    briggs  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27       1.1    briggs  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28       1.1    briggs  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     29       1.1    briggs  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30       1.1    briggs  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31       1.1    briggs  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32       1.1    briggs  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33       1.1    briggs  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34       1.1    briggs  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35       1.1    briggs  * POSSIBILITY OF SUCH DAMAGE.
     36       1.1    briggs  */
     37       1.1    briggs /*
     38       1.1    briggs  * Derived in part from code from PMON/2000 (http://pmon.groupbsd.org/).
     39       1.1    briggs  */
     40       1.1    briggs 
     41       1.2    briggs /*
     42       1.2    briggs  * To do:
     43      1.10   thorpej  *    - Perform all data structure allocation dynamically, don't have
     44      1.10   thorpej  *	statically-sized arrays ("oops, you lose because you have too
     45      1.10   thorpej  *	many slots filled!")
     46       1.7   thorpej  *    - Do this in 2 passes, with an MD hook to control the behavior:
     47       1.7   thorpej  *		(1) Configure the bus (possibly including expansion
     48       1.7   thorpej  *		    ROMs.
     49       1.7   thorpej  *		(2) Another pass to disable expansion ROMs if they're
     50       1.7   thorpej  *		    mapped (since you're not supposed to leave them
     51       1.7   thorpej  *		    mapped when you're not using them).
     52       1.7   thorpej  *	This would facilitate MD code executing the expansion ROMs
     53       1.7   thorpej  *	if necessary (possibly with an x86 emulator) to configure
     54       1.7   thorpej  *	devices (e.g. VGA cards).
     55       1.2    briggs  *    - Deal with "anything can be hot-plugged" -- i.e., carry configuration
     56       1.8    briggs  *	information around & be able to reconfigure on the fly
     57       1.2    briggs  *    - Deal with segments (See IA64 System Abstraction Layer)
     58       1.2    briggs  *    - Deal with subtractive bridges (& non-spec positive/subtractive decode)
     59       1.2    briggs  *    - Deal with ISA/VGA/VGA palette snooping
     60       1.2    briggs  *    - Deal with device capabilities on bridges
     61       1.8    briggs  *    - Worry about changing a bridge to/from transparency
     62       1.8    briggs  * From thorpej (05/25/01)
     63       1.8    briggs  *    - Try to handle devices that are already configured (perhaps using that
     64       1.8    briggs  *      as a hint to where we put other devices)
     65       1.2    briggs  */
     66      1.13     lukem 
     67      1.13     lukem #include <sys/cdefs.h>
     68  1.34.6.1       tls __KERNEL_RCSID(0, "$NetBSD: pciconf.c,v 1.34.6.1 2012/11/20 03:02:20 tls Exp $");
     69       1.2    briggs 
     70       1.1    briggs #include "opt_pci.h"
     71       1.1    briggs 
     72       1.1    briggs #include <sys/param.h>
     73       1.1    briggs #include <sys/extent.h>
     74       1.1    briggs #include <sys/queue.h>
     75       1.1    briggs #include <sys/systm.h>
     76       1.1    briggs #include <sys/malloc.h>
     77      1.32      matt #include <sys/kmem.h>
     78       1.1    briggs 
     79       1.1    briggs #include <dev/pci/pcivar.h>
     80       1.1    briggs #include <dev/pci/pciconf.h>
     81       1.1    briggs #include <dev/pci/pcidevs.h>
     82      1.22    briggs #include <dev/pci/pccbbreg.h>
     83       1.1    briggs 
     84       1.1    briggs int pci_conf_debug = 0;
     85       1.1    briggs 
     86       1.1    briggs #if !defined(MIN)
     87       1.1    briggs #define	MIN(a,b) (((a)<(b))?(a):(b))
     88       1.1    briggs #define	MAX(a,b) (((a)>(b))?(a):(b))
     89       1.1    briggs #endif
     90       1.1    briggs 
     91       1.1    briggs /* per-bus constants. */
     92      1.10   thorpej #define MAX_CONF_DEV	32			/* Arbitrary */
     93       1.1    briggs #define MAX_CONF_MEM	(3 * MAX_CONF_DEV)	/* Avg. 3 per device -- Arb. */
     94       1.8    briggs #define MAX_CONF_IO	(3 * MAX_CONF_DEV)	/* Avg. 1 per device -- Arb. */
     95       1.1    briggs 
     96       1.1    briggs struct _s_pciconf_bus_t;			/* Forward declaration */
     97       1.1    briggs 
     98       1.1    briggs typedef struct _s_pciconf_dev_t {
     99       1.1    briggs 	int		ipin;
    100       1.1    briggs 	int		iline;
    101       1.1    briggs 	int		min_gnt;
    102       1.1    briggs 	int		max_lat;
    103       1.2    briggs 	int		enable;
    104       1.1    briggs 	pcitag_t	tag;
    105       1.1    briggs 	pci_chipset_tag_t	pc;
    106       1.1    briggs 	struct _s_pciconf_bus_t	*ppb;		/* I am really a bridge */
    107       1.1    briggs } pciconf_dev_t;
    108       1.1    briggs 
    109       1.1    briggs typedef struct _s_pciconf_win_t {
    110       1.1    briggs 	pciconf_dev_t	*dev;
    111       1.1    briggs 	int		reg;			/* 0 for busses */
    112       1.1    briggs 	int		align;
    113       1.1    briggs 	int		prefetch;
    114       1.1    briggs 	u_int64_t	size;
    115       1.1    briggs 	u_int64_t	address;
    116       1.1    briggs } pciconf_win_t;
    117       1.1    briggs 
    118       1.1    briggs typedef struct _s_pciconf_bus_t {
    119       1.1    briggs 	int		busno;
    120       1.1    briggs 	int		next_busno;
    121       1.1    briggs 	int		last_busno;
    122       1.1    briggs 	int		max_mingnt;
    123       1.1    briggs 	int		min_maxlat;
    124      1.14   thorpej 	int		cacheline_size;
    125       1.1    briggs 	int		prefetch;
    126       1.1    briggs 	int		fast_b2b;
    127       1.1    briggs 	int		freq_66;
    128       1.1    briggs 	int		def_ltim;
    129       1.1    briggs 	int		max_ltim;
    130       1.1    briggs 	int		bandwidth_used;
    131       1.1    briggs 	int		swiz;
    132       1.2    briggs 	int		io_32bit;
    133       1.2    briggs 	int		pmem_64bit;
    134  1.34.6.1       tls 	int		io_align;
    135  1.34.6.1       tls 	int		mem_align;
    136  1.34.6.1       tls 	int		pmem_align;
    137       1.1    briggs 
    138       1.1    briggs 	int		ndevs;
    139       1.1    briggs 	pciconf_dev_t	device[MAX_CONF_DEV];
    140       1.1    briggs 
    141       1.1    briggs 	/* These should be sorted in order of decreasing size */
    142       1.1    briggs 	int		nmemwin;
    143       1.1    briggs 	pciconf_win_t	pcimemwin[MAX_CONF_MEM];
    144       1.1    briggs 	int		niowin;
    145       1.1    briggs 	pciconf_win_t	pciiowin[MAX_CONF_IO];
    146       1.1    briggs 
    147       1.1    briggs 	bus_size_t	io_total;
    148       1.1    briggs 	bus_size_t	mem_total;
    149       1.1    briggs 	bus_size_t	pmem_total;
    150       1.1    briggs 
    151       1.1    briggs 	struct extent	*ioext;
    152       1.1    briggs 	struct extent	*memext;
    153       1.1    briggs 	struct extent	*pmemext;
    154       1.1    briggs 
    155       1.1    briggs 	pci_chipset_tag_t	pc;
    156       1.1    briggs 	struct _s_pciconf_bus_t *parent_bus;
    157       1.1    briggs } pciconf_bus_t;
    158       1.1    briggs 
    159       1.1    briggs static int	probe_bus(pciconf_bus_t *);
    160       1.1    briggs static void	alloc_busno(pciconf_bus_t *, pciconf_bus_t *);
    161      1.18    simonb static void	set_busreg(pci_chipset_tag_t, pcitag_t, int, int, int);
    162       1.4    simonb static int	pci_do_device_query(pciconf_bus_t *, pcitag_t, int, int, int);
    163       1.1    briggs static int	setup_iowins(pciconf_bus_t *);
    164       1.1    briggs static int	setup_memwins(pciconf_bus_t *);
    165       1.1    briggs static int	configure_bridge(pciconf_dev_t *);
    166       1.1    briggs static int	configure_bus(pciconf_bus_t *);
    167       1.1    briggs static u_int64_t	pci_allocate_range(struct extent *, u_int64_t, int);
    168       1.1    briggs static pciconf_win_t	*get_io_desc(pciconf_bus_t *, bus_size_t);
    169       1.1    briggs static pciconf_win_t	*get_mem_desc(pciconf_bus_t *, bus_size_t);
    170       1.1    briggs static pciconf_bus_t	*query_bus(pciconf_bus_t *, pciconf_dev_t *, int);
    171       1.1    briggs 
    172       1.1    briggs static void	print_tag(pci_chipset_tag_t, pcitag_t);
    173       1.1    briggs 
    174       1.1    briggs static void
    175       1.1    briggs print_tag(pci_chipset_tag_t pc, pcitag_t tag)
    176       1.1    briggs {
    177       1.1    briggs 	int	bus, dev, func;
    178       1.1    briggs 
    179       1.1    briggs 	pci_decompose_tag(pc, tag, &bus, &dev, &func);
    180       1.1    briggs 	printf("PCI: bus %d, device %d, function %d: ", bus, dev, func);
    181       1.1    briggs }
    182       1.1    briggs 
    183       1.1    briggs /************************************************************************/
    184       1.1    briggs /************************************************************************/
    185       1.1    briggs /***********************   Bus probing routines   ***********************/
    186       1.1    briggs /************************************************************************/
    187       1.1    briggs /************************************************************************/
    188       1.1    briggs static pciconf_win_t *
    189       1.1    briggs get_io_desc(pciconf_bus_t *pb, bus_size_t size)
    190       1.1    briggs {
    191       1.1    briggs 	int	i, n;
    192       1.1    briggs 
    193       1.1    briggs 	n = pb->niowin;
    194       1.1    briggs 	for (i=n; i > 0 && size > pb->pciiowin[i-1].size; i--)
    195       1.1    briggs 		pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */
    196       1.1    briggs 	return &pb->pciiowin[i];
    197       1.1    briggs }
    198       1.1    briggs 
    199       1.1    briggs static pciconf_win_t *
    200       1.1    briggs get_mem_desc(pciconf_bus_t *pb, bus_size_t size)
    201       1.1    briggs {
    202       1.1    briggs 	int	i, n;
    203       1.1    briggs 
    204       1.1    briggs 	n = pb->nmemwin;
    205       1.1    briggs 	for (i=n; i > 0 && size > pb->pcimemwin[i-1].size; i--)
    206       1.1    briggs 		pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */
    207       1.1    briggs 	return &pb->pcimemwin[i];
    208       1.1    briggs }
    209       1.1    briggs 
    210       1.1    briggs /*
    211       1.1    briggs  * Set up bus common stuff, then loop over devices & functions.
    212       1.1    briggs  * If we find something, call pci_do_device_query()).
    213       1.1    briggs  */
    214       1.1    briggs static int
    215       1.1    briggs probe_bus(pciconf_bus_t *pb)
    216       1.1    briggs {
    217      1.33    dyoung 	int device;
    218      1.33    dyoung 	uint8_t devs[32];
    219      1.33    dyoung 	int i, n;
    220       1.1    briggs 
    221       1.1    briggs 	pb->ndevs = 0;
    222       1.1    briggs 	pb->niowin = 0;
    223       1.1    briggs 	pb->nmemwin = 0;
    224       1.1    briggs 	pb->freq_66 = 1;
    225      1.21  augustss #ifdef PCICONF_NO_FAST_B2B
    226      1.21  augustss 	pb->fast_b2b = 0;
    227      1.21  augustss #else
    228       1.1    briggs 	pb->fast_b2b = 1;
    229      1.21  augustss #endif
    230       1.1    briggs 	pb->prefetch = 1;
    231       1.1    briggs 	pb->max_mingnt = 0;	/* we are looking for the maximum */
    232       1.1    briggs 	pb->min_maxlat = 0x100;	/* we are looking for the minimum */
    233       1.1    briggs 	pb->bandwidth_used = 0;
    234       1.4    simonb 
    235      1.33    dyoung 	n = pci_bus_devorder(pb->pc, pb->busno, devs, __arraycount(devs));
    236      1.33    dyoung 	for (i = 0; i < n; i++) {
    237       1.1    briggs 		pcitag_t tag;
    238       1.1    briggs 		pcireg_t id, bhlcr;
    239       1.1    briggs 		int function, nfunction;
    240       1.4    simonb 		int confmode;
    241       1.1    briggs 
    242      1.33    dyoung 		device = devs[i];
    243      1.33    dyoung 
    244       1.1    briggs 		tag = pci_make_tag(pb->pc, pb->busno, device, 0);
    245       1.1    briggs 		if (pci_conf_debug) {
    246       1.1    briggs 			print_tag(pb->pc, tag);
    247       1.1    briggs 		}
    248       1.1    briggs 		id = pci_conf_read(pb->pc, tag, PCI_ID_REG);
    249       1.1    briggs 
    250       1.4    simonb 		if (pci_conf_debug) {
    251       1.4    simonb 			printf("id=%x: Vendor=%x, Product=%x\n",
    252       1.4    simonb 			    id, PCI_VENDOR(id),PCI_PRODUCT(id));
    253       1.4    simonb 		}
    254       1.1    briggs 		/* Invalid vendor ID value? */
    255       1.1    briggs 		if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
    256       1.1    briggs 			continue;
    257       1.1    briggs 
    258       1.1    briggs 		bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG);
    259       1.1    briggs 		nfunction = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1;
    260       1.1    briggs 		for (function = 0 ; function < nfunction ; function++) {
    261       1.1    briggs 			tag = pci_make_tag(pb->pc, pb->busno, device, function);
    262       1.1    briggs 			id = pci_conf_read(pb->pc, tag, PCI_ID_REG);
    263       1.1    briggs 			if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
    264       1.1    briggs 				continue;
    265       1.1    briggs 			if (pb->ndevs+1 < MAX_CONF_DEV) {
    266       1.1    briggs 				if (pci_conf_debug) {
    267       1.1    briggs 					print_tag(pb->pc, tag);
    268       1.3   thorpej 					printf("Found dev 0x%04x 0x%04x -- "
    269       1.3   thorpej 					    "really probing.\n",
    270       1.3   thorpej 					PCI_VENDOR(id), PCI_PRODUCT(id));
    271       1.1    briggs 				}
    272       1.4    simonb #ifdef __HAVE_PCI_CONF_HOOK
    273       1.4    simonb 				confmode = pci_conf_hook(pb->pc, pb->busno,
    274       1.4    simonb 				    device, function, id);
    275       1.4    simonb 				if (confmode == 0)
    276       1.4    simonb 					continue;
    277       1.4    simonb #else
    278       1.6   thorpej 				/*
    279       1.6   thorpej 				 * Don't enable expansion ROMS -- some cards
    280       1.6   thorpej 				 * share address decoders between the EXPROM
    281       1.6   thorpej 				 * and PCI memory space, and enabling the ROM
    282       1.6   thorpej 				 * when not needed will cause all sorts of
    283       1.6   thorpej 				 * lossage.
    284       1.6   thorpej 				 */
    285      1.28   gdamore 				confmode = PCI_CONF_DEFAULT;
    286       1.4    simonb #endif
    287       1.1    briggs 				if (pci_do_device_query(pb, tag, device,
    288       1.4    simonb 				    function, confmode))
    289       1.1    briggs 					return -1;
    290       1.1    briggs 				pb->ndevs++;
    291       1.1    briggs 			}
    292       1.1    briggs 		}
    293       1.1    briggs 	}
    294       1.1    briggs 	return 0;
    295       1.1    briggs }
    296       1.1    briggs 
    297       1.1    briggs static void
    298       1.1    briggs alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb)
    299       1.1    briggs {
    300       1.1    briggs 	pb->busno = parent->next_busno;
    301      1.17  augustss 	pb->next_busno = pb->busno + 1;
    302      1.17  augustss }
    303      1.17  augustss 
    304      1.17  augustss static void
    305      1.17  augustss set_busreg(pci_chipset_tag_t pc, pcitag_t tag, int prim, int sec, int sub)
    306      1.17  augustss {
    307      1.17  augustss 	pcireg_t	busreg;
    308      1.17  augustss 
    309      1.17  augustss 	busreg  =  prim << PCI_BRIDGE_BUS_PRIMARY_SHIFT;
    310      1.17  augustss 	busreg |=   sec << PCI_BRIDGE_BUS_SECONDARY_SHIFT;
    311      1.17  augustss 	busreg |=   sub << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT;
    312      1.17  augustss 	pci_conf_write(pc, tag, PCI_BRIDGE_BUS_REG, busreg);
    313       1.1    briggs }
    314       1.1    briggs 
    315       1.1    briggs static pciconf_bus_t *
    316       1.1    briggs query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev)
    317       1.1    briggs {
    318       1.1    briggs 	pciconf_bus_t	*pb;
    319      1.17  augustss 	pcireg_t	io, pmem;
    320       1.1    briggs 	pciconf_win_t	*pi, *pm;
    321       1.1    briggs 
    322      1.32      matt 	pb = kmem_zalloc(sizeof (pciconf_bus_t), KM_NOSLEEP);
    323       1.1    briggs 	if (!pb)
    324       1.1    briggs 		panic("Unable to allocate memory for PCI configuration.");
    325       1.1    briggs 
    326      1.14   thorpej 	pb->cacheline_size = parent->cacheline_size;
    327       1.1    briggs 	pb->parent_bus = parent;
    328       1.1    briggs 	alloc_busno(parent, pb);
    329       1.1    briggs 
    330  1.34.6.1       tls 	pb->mem_align = 0x100000;	/* 1M alignment */
    331  1.34.6.1       tls 	pb->pmem_align = 0x100000;	/* 1M alignment */
    332  1.34.6.1       tls 	pb->io_align = 0x1000;		/* 4K alignment */
    333  1.34.6.1       tls 
    334      1.17  augustss 	set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 0xff);
    335       1.1    briggs 
    336       1.1    briggs 	pb->swiz = parent->swiz + dev;
    337       1.1    briggs 
    338       1.1    briggs 	pb->ioext = NULL;
    339       1.1    briggs 	pb->memext = NULL;
    340       1.1    briggs 	pb->pmemext = NULL;
    341       1.1    briggs 	pb->pc = parent->pc;
    342       1.1    briggs 	pb->io_total = pb->mem_total = pb->pmem_total = 0;
    343       1.1    briggs 
    344       1.2    briggs 	pb->io_32bit = 0;
    345       1.2    briggs 	if (parent->io_32bit) {
    346      1.11   thorpej 		io = pci_conf_read(parent->pc, pd->tag, PCI_BRIDGE_STATIO_REG);
    347       1.2    briggs 		if (PCI_BRIDGE_IO_32BITS(io)) {
    348       1.2    briggs 			pb->io_32bit = 1;
    349       1.2    briggs 		}
    350       1.2    briggs 	}
    351       1.2    briggs 
    352       1.2    briggs 	pb->pmem_64bit = 0;
    353       1.2    briggs 	if (parent->pmem_64bit) {
    354      1.11   thorpej 		pmem = pci_conf_read(parent->pc, pd->tag,
    355       1.2    briggs 		    PCI_BRIDGE_PREFETCHMEM_REG);
    356       1.2    briggs 		if (PCI_BRIDGE_PREFETCHMEM_64BITS(pmem)) {
    357       1.2    briggs 			pb->pmem_64bit = 1;
    358       1.2    briggs 		}
    359       1.2    briggs 	}
    360       1.2    briggs 
    361       1.1    briggs 	if (probe_bus(pb)) {
    362       1.1    briggs 		printf("Failed to probe bus %d\n", pb->busno);
    363       1.1    briggs 		goto err;
    364       1.1    briggs 	}
    365       1.1    briggs 
    366      1.17  augustss 	/* We have found all subordinate busses now, reprogram busreg. */
    367      1.17  augustss 	pb->last_busno = pb->next_busno-1;
    368      1.17  augustss 	parent->next_busno = pb->next_busno;
    369      1.17  augustss 	set_busreg(parent->pc, pd->tag, parent->busno, pb->busno,
    370      1.17  augustss 		   pb->last_busno);
    371      1.17  augustss 	if (pci_conf_debug)
    372      1.17  augustss 		printf("PCI bus bridge (parent %d) covers busses %d-%d\n",
    373      1.17  augustss 			parent->busno, pb->busno, pb->last_busno);
    374      1.17  augustss 
    375       1.1    briggs 	if (pb->io_total > 0) {
    376       1.1    briggs 		if (parent->niowin >= MAX_CONF_IO) {
    377  1.34.6.1       tls 			printf("pciconf: too many (%d) I/O windows\n",
    378  1.34.6.1       tls 			    parent->niowin);
    379       1.1    briggs 			goto err;
    380       1.1    briggs 		}
    381  1.34.6.1       tls 		pb->io_total |= pb->io_align - 1; /* Round up */
    382       1.1    briggs 		pi = get_io_desc(parent, pb->io_total);
    383       1.1    briggs 		pi->dev = pd;
    384       1.1    briggs 		pi->reg = 0;
    385       1.1    briggs 		pi->size = pb->io_total;
    386  1.34.6.1       tls 		pi->align = pb->io_align;	/* 4K min alignment */
    387  1.34.6.1       tls 		if (parent->io_align < pb->io_align)
    388  1.34.6.1       tls 			parent->io_align = pb->io_align;
    389       1.1    briggs 		pi->prefetch = 0;
    390       1.1    briggs 		parent->niowin++;
    391       1.1    briggs 		parent->io_total += pb->io_total;
    392       1.1    briggs 	}
    393       1.1    briggs 
    394       1.1    briggs 	if (pb->mem_total > 0) {
    395       1.1    briggs 		if (parent->nmemwin >= MAX_CONF_MEM) {
    396  1.34.6.1       tls 			printf("pciconf: too many (%d) MEM windows\n",
    397  1.34.6.1       tls 			     parent->nmemwin);
    398       1.1    briggs 			goto err;
    399       1.1    briggs 		}
    400  1.34.6.1       tls 		pb->mem_total |= pb->mem_align-1; /* Round up */
    401       1.1    briggs 		pm = get_mem_desc(parent, pb->mem_total);
    402       1.1    briggs 		pm->dev = pd;
    403       1.1    briggs 		pm->reg = 0;
    404       1.1    briggs 		pm->size = pb->mem_total;
    405  1.34.6.1       tls 		pm->align = pb->mem_align;	/* 1M min alignment */
    406  1.34.6.1       tls 		if (parent->mem_align < pb->mem_align)
    407  1.34.6.1       tls 			parent->mem_align = pb->mem_align;
    408       1.1    briggs 		pm->prefetch = 0;
    409       1.1    briggs 		parent->nmemwin++;
    410       1.1    briggs 		parent->mem_total += pb->mem_total;
    411       1.1    briggs 	}
    412       1.1    briggs 
    413       1.1    briggs 	if (pb->pmem_total > 0) {
    414       1.1    briggs 		if (parent->nmemwin >= MAX_CONF_MEM) {
    415      1.10   thorpej 			printf("pciconf: too many MEM windows\n");
    416       1.1    briggs 			goto err;
    417       1.1    briggs 		}
    418  1.34.6.1       tls 		pb->pmem_total |= pb->pmem_align-1; /* Round up */
    419       1.1    briggs 		pm = get_mem_desc(parent, pb->pmem_total);
    420       1.1    briggs 		pm->dev = pd;
    421       1.1    briggs 		pm->reg = 0;
    422       1.1    briggs 		pm->size = pb->pmem_total;
    423  1.34.6.1       tls 		pm->align = pb->pmem_align;	/* 1M alignment */
    424  1.34.6.1       tls 		if (parent->pmem_align < pb->pmem_align)
    425  1.34.6.1       tls 			parent->pmem_align = pb->pmem_align;
    426       1.1    briggs 		pm->prefetch = 1;
    427       1.1    briggs 		parent->nmemwin++;
    428       1.1    briggs 		parent->pmem_total += pb->pmem_total;
    429       1.1    briggs 	}
    430       1.1    briggs 
    431       1.1    briggs 	return pb;
    432       1.1    briggs err:
    433      1.32      matt 	kmem_free(pb, sizeof(*pb));
    434       1.1    briggs 	return NULL;
    435       1.1    briggs }
    436       1.1    briggs 
    437       1.1    briggs static int
    438       1.4    simonb pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func, int mode)
    439       1.1    briggs {
    440       1.1    briggs 	pciconf_dev_t	*pd;
    441       1.1    briggs 	pciconf_win_t	*pi, *pm;
    442      1.22    briggs 	pcireg_t	class, cmd, icr, bhlc, bar, mask, bar64, mask64, busreg;
    443       1.1    briggs 	u_int64_t	size;
    444      1.22    briggs 	int		br, width, reg_start, reg_end;
    445       1.1    briggs 
    446       1.1    briggs 	pd = &pb->device[pb->ndevs];
    447       1.1    briggs 	pd->pc = pb->pc;
    448       1.1    briggs 	pd->tag = tag;
    449       1.1    briggs 	pd->ppb = NULL;
    450       1.4    simonb 	pd->enable = mode;
    451       1.1    briggs 
    452       1.1    briggs 	class = pci_conf_read(pb->pc, tag, PCI_CLASS_REG);
    453       1.1    briggs 
    454       1.1    briggs 	cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG);
    455      1.32      matt 	bhlc = pci_conf_read(pb->pc, tag, PCI_BHLC_REG);
    456       1.1    briggs 
    457      1.32      matt 	if (PCI_CLASS(class) != PCI_CLASS_BRIDGE
    458      1.32      matt 	    && PCI_HDRTYPE_TYPE(bhlc) != PCI_HDRTYPE_PPB) {
    459       1.1    briggs 		cmd &= ~(PCI_COMMAND_MASTER_ENABLE |
    460       1.1    briggs 		    PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE);
    461       1.1    briggs 		pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd);
    462       1.3   thorpej 	} else if (pci_conf_debug) {
    463       1.3   thorpej 		print_tag(pb->pc, tag);
    464       1.3   thorpej 		printf("device is a bridge; not clearing enables\n");
    465       1.1    briggs 	}
    466       1.1    briggs 
    467       1.1    briggs 	if ((cmd & PCI_STATUS_BACKTOBACK_SUPPORT) == 0)
    468       1.1    briggs 		pb->fast_b2b = 0;
    469       1.1    briggs 
    470       1.1    briggs 	if ((cmd & PCI_STATUS_66MHZ_SUPPORT) == 0)
    471       1.1    briggs 		pb->freq_66 = 0;
    472       1.1    briggs 
    473      1.22    briggs 	switch (PCI_HDRTYPE_TYPE(bhlc)) {
    474      1.22    briggs 	case PCI_HDRTYPE_DEVICE:
    475      1.22    briggs 		reg_start = PCI_MAPREG_START;
    476      1.22    briggs 		reg_end = PCI_MAPREG_END;
    477      1.22    briggs 		break;
    478      1.22    briggs 	case PCI_HDRTYPE_PPB:
    479       1.1    briggs 		pd->ppb = query_bus(pb, pd, dev);
    480       1.1    briggs 		if (pd->ppb == NULL)
    481       1.1    briggs 			return -1;
    482       1.1    briggs 		return 0;
    483      1.22    briggs 	case PCI_HDRTYPE_PCB:
    484      1.22    briggs 		reg_start = PCI_MAPREG_START;
    485      1.22    briggs 		reg_end = PCI_MAPREG_PCB_END;
    486      1.22    briggs 
    487      1.22    briggs 		busreg = pci_conf_read(pb->pc, tag, PCI_BUSNUM);
    488      1.22    briggs 		busreg  =  (busreg & 0xff000000) |
    489      1.22    briggs 		    pb->busno << PCI_BRIDGE_BUS_PRIMARY_SHIFT |
    490      1.22    briggs 		    pb->next_busno << PCI_BRIDGE_BUS_SECONDARY_SHIFT |
    491      1.22    briggs 		    pb->next_busno << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT;
    492      1.22    briggs 		pci_conf_write(pb->pc, tag, PCI_BUSNUM, busreg);
    493      1.22    briggs 
    494      1.24    simonb 		pb->next_busno++;
    495      1.22    briggs 		break;
    496      1.22    briggs 	default:
    497      1.22    briggs 		return -1;
    498       1.1    briggs 	}
    499       1.1    briggs 
    500       1.1    briggs 	icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG);
    501       1.1    briggs 	pd->ipin = PCI_INTERRUPT_PIN(icr);
    502       1.1    briggs 	pd->iline = PCI_INTERRUPT_LINE(icr);
    503       1.1    briggs 	pd->min_gnt = PCI_MIN_GNT(icr);
    504       1.1    briggs 	pd->max_lat = PCI_MAX_LAT(icr);
    505       1.1    briggs 	if (pd->iline || pd->ipin) {
    506       1.8    briggs 		pci_conf_interrupt(pb->pc, pb->busno, dev, pd->ipin, pb->swiz,
    507       1.1    briggs 		    &pd->iline);
    508       1.1    briggs 		icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);
    509       1.1    briggs 		icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT);
    510       1.1    briggs 		pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr);
    511       1.1    briggs 	}
    512       1.1    briggs 
    513       1.1    briggs 	if (pd->min_gnt != 0 || pd->max_lat != 0) {
    514       1.1    briggs 		if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt)
    515       1.1    briggs 			pb->max_mingnt = pd->min_gnt;
    516       1.1    briggs 
    517       1.1    briggs 		if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat)
    518       1.1    briggs 			pb->min_maxlat = pd->max_lat;
    519       1.1    briggs 
    520       1.1    briggs 		pb->bandwidth_used += pd->min_gnt * 4000000 /
    521       1.1    briggs 				(pd->min_gnt + pd->max_lat);
    522       1.1    briggs 	}
    523       1.1    briggs 
    524       1.1    briggs 	width = 4;
    525      1.22    briggs 	for (br = reg_start; br < reg_end; br += width) {
    526       1.3   thorpej #if 0
    527       1.8    briggs /* XXX Should only ignore if IDE not in legacy mode? */
    528       1.1    briggs 		if (PCI_CLASS(class) == PCI_CLASS_MASS_STORAGE &&
    529       1.1    briggs 		    PCI_SUBCLASS(class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
    530       1.1    briggs 			break;
    531       1.1    briggs 		}
    532       1.3   thorpej #endif
    533       1.1    briggs 		bar = pci_conf_read(pb->pc, tag, br);
    534       1.3   thorpej 		pci_conf_write(pb->pc, tag, br, 0xffffffff);
    535       1.1    briggs 		mask = pci_conf_read(pb->pc, tag, br);
    536       1.1    briggs 		pci_conf_write(pb->pc, tag, br, bar);
    537       1.1    briggs 		width = 4;
    538       1.1    briggs 
    539       1.8    briggs 		if (   (mode & PCI_CONF_MAP_IO)
    540       1.8    briggs 		    && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO)) {
    541       1.8    briggs 			/*
    542       1.8    briggs 			 * Upper 16 bits must be one.  Devices may hardwire
    543       1.8    briggs 			 * them to zero, though, per PCI 2.2, 6.2.5.1, p 203.
    544       1.8    briggs 			 */
    545       1.3   thorpej 			mask |= 0xffff0000;
    546       1.3   thorpej 
    547       1.3   thorpej 			size = PCI_MAPREG_IO_SIZE(mask);
    548       1.3   thorpej 			if (size == 0) {
    549       1.3   thorpej 				if (pci_conf_debug) {
    550       1.3   thorpej 					print_tag(pb->pc, tag);
    551       1.3   thorpej 					printf("I/O BAR 0x%x is void\n", br);
    552       1.3   thorpej 				}
    553       1.3   thorpej 				continue;
    554       1.3   thorpej 			}
    555       1.1    briggs 
    556       1.1    briggs 			if (pb->niowin >= MAX_CONF_IO) {
    557      1.10   thorpej 				printf("pciconf: too many I/O windows\n");
    558       1.1    briggs 				return -1;
    559       1.1    briggs 			}
    560       1.1    briggs 
    561       1.1    briggs 			pi = get_io_desc(pb, size);
    562       1.1    briggs 			pi->dev = pd;
    563       1.1    briggs 			pi->reg = br;
    564       1.1    briggs 			pi->size = (u_int64_t) size;
    565       1.1    briggs 			pi->align = 4;
    566  1.34.6.1       tls 			if (pb->io_align < pi->size)
    567  1.34.6.1       tls 				pb->io_align = pi->size;
    568       1.1    briggs 			pi->prefetch = 0;
    569       1.1    briggs 			if (pci_conf_debug) {
    570       1.1    briggs 				print_tag(pb->pc, tag);
    571      1.23       scw 				printf("Register 0x%x, I/O size %" PRIu64 "\n",
    572       1.1    briggs 				    br, pi->size);
    573       1.1    briggs 			}
    574       1.1    briggs 			pb->niowin++;
    575       1.1    briggs 			pb->io_total += size;
    576       1.4    simonb 		} else if ((mode & PCI_CONF_MAP_MEM)
    577       1.4    simonb 			   && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_MEM)) {
    578       1.1    briggs 			switch (PCI_MAPREG_MEM_TYPE(mask)) {
    579       1.1    briggs 			case PCI_MAPREG_MEM_TYPE_32BIT:
    580       1.1    briggs 			case PCI_MAPREG_MEM_TYPE_32BIT_1M:
    581       1.1    briggs 				size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask);
    582       1.1    briggs 				break;
    583       1.1    briggs 			case PCI_MAPREG_MEM_TYPE_64BIT:
    584       1.1    briggs 				bar64 = pci_conf_read(pb->pc, tag, br + 4);
    585       1.1    briggs 				pci_conf_write(pb->pc, tag, br + 4, 0xffffffff);
    586       1.1    briggs 				mask64 = pci_conf_read(pb->pc, tag, br + 4);
    587       1.1    briggs 				pci_conf_write(pb->pc, tag, br + 4, bar64);
    588       1.1    briggs 				size = (u_int64_t) PCI_MAPREG_MEM64_SIZE(
    589       1.1    briggs 				      (((u_int64_t) mask64) << 32) | mask);
    590       1.1    briggs 				width = 8;
    591      1.16    briggs 				break;
    592       1.1    briggs 			default:
    593       1.1    briggs 				print_tag(pb->pc, tag);
    594       1.1    briggs 				printf("reserved mapping type 0x%x\n",
    595       1.1    briggs 					PCI_MAPREG_MEM_TYPE(mask));
    596       1.1    briggs 				continue;
    597       1.1    briggs 			}
    598       1.1    briggs 
    599       1.3   thorpej 			if (size == 0) {
    600       1.3   thorpej 				if (pci_conf_debug) {
    601       1.3   thorpej 					print_tag(pb->pc, tag);
    602       1.3   thorpej 					printf("MEM%d BAR 0x%x is void\n",
    603       1.3   thorpej 					    PCI_MAPREG_MEM_TYPE(mask) ==
    604       1.3   thorpej 						PCI_MAPREG_MEM_TYPE_64BIT ?
    605       1.3   thorpej 						64 : 32, br);
    606       1.3   thorpej 				}
    607       1.3   thorpej 				continue;
    608      1.16    briggs 			} else {
    609      1.16    briggs 				if (pci_conf_debug) {
    610      1.16    briggs 					print_tag(pb->pc, tag);
    611  1.34.6.1       tls 					printf("MEM%d BAR 0x%x has size %#lx\n",
    612      1.16    briggs 					    PCI_MAPREG_MEM_TYPE(mask) ==
    613      1.16    briggs 						PCI_MAPREG_MEM_TYPE_64BIT ?
    614      1.16    briggs 						64 : 32, br, (unsigned long)size);
    615      1.16    briggs 				}
    616       1.3   thorpej 			}
    617       1.3   thorpej 
    618       1.1    briggs 			if (pb->nmemwin >= MAX_CONF_MEM) {
    619      1.10   thorpej 				printf("pciconf: too many memory windows\n");
    620       1.1    briggs 				return -1;
    621       1.1    briggs 			}
    622       1.1    briggs 
    623       1.1    briggs 			pm = get_mem_desc(pb, size);
    624       1.1    briggs 			pm->dev = pd;
    625       1.1    briggs 			pm->reg = br;
    626       1.1    briggs 			pm->size = size;
    627       1.1    briggs 			pm->align = 4;
    628       1.1    briggs 			pm->prefetch = PCI_MAPREG_MEM_PREFETCHABLE(mask);
    629       1.1    briggs 			if (pci_conf_debug) {
    630       1.1    briggs 				print_tag(pb->pc, tag);
    631      1.23       scw 				printf("Register 0x%x, memory size %"
    632      1.23       scw 				    PRIu64 "\n", br, pm->size);
    633       1.1    briggs 			}
    634       1.1    briggs 			pb->nmemwin++;
    635       1.1    briggs 			if (pm->prefetch) {
    636       1.1    briggs 				pb->pmem_total += size;
    637  1.34.6.1       tls 				if (pb->pmem_align < pm->size)
    638  1.34.6.1       tls 					pb->pmem_align = pm->size;
    639       1.1    briggs 			} else {
    640       1.1    briggs 				pb->mem_total += size;
    641  1.34.6.1       tls 				if (pb->mem_align < pm->size)
    642  1.34.6.1       tls 					pb->mem_align = pm->size;
    643       1.1    briggs 			}
    644       1.1    briggs 		}
    645       1.1    briggs 	}
    646       1.1    briggs 
    647       1.4    simonb 	if (mode & PCI_CONF_MAP_ROM) {
    648       1.4    simonb 		bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM);
    649       1.4    simonb 		pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe);
    650       1.4    simonb 		mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM);
    651       1.4    simonb 		pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, bar);
    652       1.4    simonb 
    653       1.4    simonb 		if (mask != 0 && mask != 0xffffffff) {
    654       1.4    simonb 			if (pb->nmemwin >= MAX_CONF_MEM) {
    655      1.10   thorpej 				printf("pciconf: too many memory windows\n");
    656       1.4    simonb 				return -1;
    657       1.4    simonb 			}
    658       1.4    simonb 			size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask);
    659       1.1    briggs 
    660       1.4    simonb 			pm = get_mem_desc(pb, size);
    661       1.4    simonb 			pm->dev = pd;
    662       1.4    simonb 			pm->reg = PCI_MAPREG_ROM;
    663       1.4    simonb 			pm->size = size;
    664       1.4    simonb 			pm->align = 4;
    665       1.4    simonb 			pm->prefetch = 1;
    666       1.4    simonb 			if (pci_conf_debug) {
    667       1.4    simonb 				print_tag(pb->pc, tag);
    668      1.23       scw 				printf("Expansion ROM memory size %"
    669      1.23       scw 				    PRIu64 "\n", pm->size);
    670       1.4    simonb 			}
    671       1.4    simonb 			pb->nmemwin++;
    672       1.4    simonb 			pb->pmem_total += size;
    673       1.1    briggs 		}
    674       1.8    briggs 	} else {
    675      1.28   gdamore 		/* Don't enable ROMs if we aren't going to map them. */
    676      1.28   gdamore 		mode &= ~PCI_CONF_ENABLE_ROM;
    677      1.28   gdamore 		pd->enable &= ~PCI_CONF_ENABLE_ROM;
    678      1.28   gdamore 	}
    679      1.28   gdamore 
    680      1.28   gdamore 	if (!(mode & PCI_CONF_ENABLE_ROM)) {
    681       1.8    briggs 		/* Ensure ROM is disabled */
    682       1.8    briggs 		bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM);
    683       1.8    briggs 		pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM,
    684       1.8    briggs 		    bar & ~PCI_MAPREG_ROM_ENABLE);
    685       1.1    briggs 	}
    686       1.1    briggs 
    687       1.1    briggs 	return 0;
    688       1.1    briggs }
    689       1.1    briggs 
    690       1.1    briggs /************************************************************************/
    691       1.1    briggs /************************************************************************/
    692       1.1    briggs /********************   Bus configuration routines   ********************/
    693       1.1    briggs /************************************************************************/
    694       1.1    briggs /************************************************************************/
    695       1.1    briggs static u_int64_t
    696       1.1    briggs pci_allocate_range(struct extent *ex, u_int64_t amt, int align)
    697       1.1    briggs {
    698       1.1    briggs 	int	r;
    699       1.1    briggs 	u_long	addr;
    700       1.1    briggs 
    701       1.1    briggs 	r = extent_alloc(ex, amt, align, 0, EX_NOWAIT, &addr);
    702       1.1    briggs 	if (r) {
    703  1.34.6.1       tls 		printf("extent_alloc(%p, %#" PRIx64 ", %#x) returned %d\n",
    704       1.4    simonb 		    ex, amt, align, r);
    705       1.4    simonb 		extent_print(ex);
    706  1.34.6.1       tls 		return ~0ULL;
    707       1.1    briggs 	}
    708  1.34.6.1       tls 	return addr;
    709       1.1    briggs }
    710       1.1    briggs 
    711       1.1    briggs static int
    712       1.1    briggs setup_iowins(pciconf_bus_t *pb)
    713       1.1    briggs {
    714       1.1    briggs 	pciconf_win_t	*pi;
    715       1.1    briggs 	pciconf_dev_t	*pd;
    716       1.1    briggs 
    717       1.1    briggs 	for (pi=pb->pciiowin; pi < &pb->pciiowin[pb->niowin] ; pi++) {
    718       1.1    briggs 		if (pi->size == 0)
    719       1.1    briggs 			continue;
    720       1.1    briggs 
    721       1.1    briggs 		pd = pi->dev;
    722       1.1    briggs 		pi->address = pci_allocate_range(pb->ioext, pi->size,
    723       1.1    briggs 		    pi->align);
    724  1.34.6.1       tls 		if (~pi->address == 0) {
    725       1.1    briggs 			print_tag(pd->pc, pd->tag);
    726      1.23       scw 			printf("Failed to allocate PCI I/O space (%"
    727      1.23       scw 			    PRIu64 " req)\n", pi->size);
    728       1.1    briggs 			return -1;
    729       1.1    briggs 		}
    730       1.1    briggs 		if (pd->ppb && pi->reg == 0) {
    731       1.1    briggs 			pd->ppb->ioext = extent_create("pciconf", pi->address,
    732      1.34      para 			    pi->address + pi->size, NULL, 0,
    733       1.1    briggs 			    EX_NOWAIT);
    734       1.1    briggs 			if (pd->ppb->ioext == NULL) {
    735       1.1    briggs 				print_tag(pd->pc, pd->tag);
    736       1.1    briggs 				printf("Failed to alloc I/O ext. for bus %d\n",
    737       1.1    briggs 				    pd->ppb->busno);
    738       1.1    briggs 				return -1;
    739       1.1    briggs 			}
    740       1.1    briggs 			continue;
    741       1.1    briggs 		}
    742      1.26   tsutsui 		if (!pb->io_32bit && pi->address > 0xFFFF) {
    743      1.26   tsutsui 			pi->address = 0;
    744      1.26   tsutsui 			pd->enable &= ~PCI_CONF_ENABLE_IO;
    745      1.26   tsutsui 		} else {
    746      1.26   tsutsui 			pd->enable |= PCI_CONF_ENABLE_IO;
    747      1.26   tsutsui 		}
    748       1.1    briggs 		if (pci_conf_debug) {
    749       1.1    briggs 			print_tag(pd->pc, pd->tag);
    750      1.23       scw 			printf("Putting %" PRIu64 " I/O bytes @ %#" PRIx64
    751      1.23       scw 			    " (reg %x)\n", pi->size, pi->address, pi->reg);
    752       1.1    briggs 		}
    753       1.1    briggs 		pci_conf_write(pd->pc, pd->tag, pi->reg,
    754       1.1    briggs 		    PCI_MAPREG_IO_ADDR(pi->address) | PCI_MAPREG_TYPE_IO);
    755       1.1    briggs 	}
    756       1.1    briggs 	return 0;
    757       1.1    briggs }
    758       1.1    briggs 
    759       1.1    briggs static int
    760       1.1    briggs setup_memwins(pciconf_bus_t *pb)
    761       1.1    briggs {
    762       1.1    briggs 	pciconf_win_t	*pm;
    763       1.1    briggs 	pciconf_dev_t	*pd;
    764       1.1    briggs 	pcireg_t	base;
    765       1.1    briggs 	struct extent	*ex;
    766       1.1    briggs 
    767       1.1    briggs 	for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) {
    768       1.1    briggs 		if (pm->size == 0)
    769       1.1    briggs 			continue;
    770       1.1    briggs 
    771       1.1    briggs 		pd = pm->dev;
    772       1.1    briggs 		ex = (pm->prefetch) ? pb->pmemext : pb->memext;
    773       1.1    briggs 		pm->address = pci_allocate_range(ex, pm->size, pm->align);
    774  1.34.6.1       tls 		if (~pm->address == 0) {
    775       1.1    briggs 			print_tag(pd->pc, pd->tag);
    776       1.1    briggs 			printf(
    777      1.23       scw 			   "Failed to allocate PCI memory space (%" PRIu64
    778      1.23       scw 			   " req)\n", pm->size);
    779       1.1    briggs 			return -1;
    780       1.1    briggs 		}
    781       1.1    briggs 		if (pd->ppb && pm->reg == 0) {
    782       1.1    briggs 			ex = extent_create("pciconf", pm->address,
    783      1.34      para 			    pm->address + pm->size, NULL, 0, EX_NOWAIT);
    784       1.1    briggs 			if (ex == NULL) {
    785       1.1    briggs 				print_tag(pd->pc, pd->tag);
    786       1.1    briggs 				printf("Failed to alloc MEM ext. for bus %d\n",
    787       1.1    briggs 				    pd->ppb->busno);
    788       1.1    briggs 				return -1;
    789       1.1    briggs 			}
    790       1.1    briggs 			if (pm->prefetch) {
    791       1.1    briggs 				pd->ppb->pmemext = ex;
    792       1.1    briggs 			} else {
    793       1.1    briggs 				pd->ppb->memext = ex;
    794       1.1    briggs 			}
    795       1.1    briggs 			continue;
    796       1.1    briggs 		}
    797       1.2    briggs 		if (pm->prefetch && !pb->pmem_64bit &&
    798       1.2    briggs 		    pm->address > 0xFFFFFFFFULL) {
    799       1.2    briggs 			pm->address = 0;
    800      1.26   tsutsui 			pd->enable &= ~PCI_CONF_ENABLE_MEM;
    801       1.8    briggs 		} else {
    802       1.8    briggs 			pd->enable |= PCI_CONF_ENABLE_MEM;
    803       1.2    briggs 		}
    804       1.1    briggs 		if (pm->reg != PCI_MAPREG_ROM) {
    805       1.1    briggs 			if (pci_conf_debug) {
    806       1.1    briggs 				print_tag(pd->pc, pd->tag);
    807       1.1    briggs 				printf(
    808      1.23       scw 				    "Putting %" PRIu64 " MEM bytes @ %#"
    809      1.23       scw 				    PRIx64 " (reg %x)\n", pm->size,
    810      1.23       scw 				    pm->address, pm->reg);
    811       1.1    briggs 			}
    812       1.1    briggs 			base = pci_conf_read(pd->pc, pd->tag, pm->reg);
    813       1.1    briggs 			base = PCI_MAPREG_MEM_ADDR(pm->address) |
    814       1.1    briggs 			    PCI_MAPREG_MEM_TYPE(base);
    815       1.1    briggs 			pci_conf_write(pd->pc, pd->tag, pm->reg, base);
    816       1.1    briggs 			if (PCI_MAPREG_MEM_TYPE(base) ==
    817       1.1    briggs 			    PCI_MAPREG_MEM_TYPE_64BIT) {
    818       1.1    briggs 				base = (pcireg_t)
    819       1.1    briggs 				    (PCI_MAPREG_MEM64_ADDR(pm->address) >> 32);
    820       1.1    briggs 				pci_conf_write(pd->pc, pd->tag, pm->reg + 4,
    821       1.1    briggs 				    base);
    822       1.1    briggs 			}
    823       1.1    briggs 		}
    824       1.1    briggs 	}
    825       1.1    briggs 	for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) {
    826       1.1    briggs 		if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) {
    827       1.1    briggs 			pd = pm->dev;
    828      1.29   gdamore 			if (!(pd->enable & PCI_CONF_MAP_ROM))
    829      1.28   gdamore 				continue;
    830       1.1    briggs 			if (pci_conf_debug) {
    831       1.1    briggs 				print_tag(pd->pc, pd->tag);
    832       1.1    briggs 				printf(
    833      1.23       scw 				    "Putting %" PRIu64 " ROM bytes @ %#"
    834      1.23       scw 				    PRIx64 " (reg %x)\n", pm->size,
    835      1.23       scw 				    pm->address, pm->reg);
    836       1.1    briggs 			}
    837      1.29   gdamore 			base = (pcireg_t) pm->address;
    838      1.29   gdamore 			if (pd->enable & PCI_CONF_ENABLE_ROM)
    839      1.29   gdamore 				base |= PCI_MAPREG_ROM_ENABLE;
    840      1.29   gdamore 
    841       1.1    briggs 			pci_conf_write(pd->pc, pd->tag, pm->reg, base);
    842       1.1    briggs 		}
    843       1.1    briggs 	}
    844       1.1    briggs 	return 0;
    845       1.1    briggs }
    846       1.1    briggs 
    847       1.1    briggs /*
    848       1.1    briggs  * Configure I/O, memory, and prefetcable memory spaces, then make
    849       1.1    briggs  * a call to configure_bus().
    850       1.1    briggs  */
    851       1.1    briggs static int
    852       1.1    briggs configure_bridge(pciconf_dev_t *pd)
    853       1.1    briggs {
    854       1.1    briggs 	unsigned long	io_base, io_limit, mem_base, mem_limit;
    855       1.1    briggs 	pciconf_bus_t	*pb;
    856       1.1    briggs 	pcireg_t	io, iohigh, mem, cmd;
    857       1.1    briggs 	int		rv;
    858       1.1    briggs 
    859       1.1    briggs 	pb = pd->ppb;
    860       1.1    briggs 	/* Configure I/O base & limit*/
    861       1.1    briggs 	if (pb->ioext) {
    862       1.1    briggs 		io_base = pb->ioext->ex_start;
    863       1.1    briggs 		io_limit = pb->ioext->ex_end;
    864       1.2    briggs 	} else {
    865       1.2    briggs 		io_base  = 0x1000;	/* 4K */
    866       1.2    briggs 		io_limit = 0x0000;
    867       1.1    briggs 	}
    868       1.2    briggs 	if (pb->io_32bit) {
    869       1.2    briggs 		iohigh =
    870       1.2    briggs 		    ((io_base >> 16) << PCI_BRIDGE_IOHIGH_BASE_SHIFT) |
    871       1.2    briggs 		    ((io_limit >> 16) << PCI_BRIDGE_IOHIGH_LIMIT_SHIFT);
    872       1.2    briggs 	} else {
    873       1.2    briggs 		if (io_limit > 0xFFFF) {
    874       1.2    briggs 			printf("Bus %d bridge does not support 32-bit I/O.  ",
    875       1.2    briggs 			    pb->busno);
    876       1.2    briggs 			printf("Disabling I/O accesses\n");
    877       1.2    briggs 			io_base  = 0x1000;	/* 4K */
    878       1.2    briggs 			io_limit = 0x0000;
    879       1.2    briggs 		}
    880       1.2    briggs 		iohigh = 0;
    881       1.2    briggs 	}
    882       1.9    briggs 	io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG) &
    883       1.9    briggs 	    (PCI_BRIDGE_STATIO_STATUS_MASK << PCI_BRIDGE_STATIO_STATUS_SHIFT);
    884       1.2    briggs 	io |= (((io_base >> 8) & PCI_BRIDGE_STATIO_IOBASE_MASK)
    885       1.2    briggs 	    << PCI_BRIDGE_STATIO_IOBASE_SHIFT);
    886       1.2    briggs 	io |= (((io_limit >> 8) & PCI_BRIDGE_STATIO_IOLIMIT_MASK)
    887       1.2    briggs 	    << PCI_BRIDGE_STATIO_IOLIMIT_SHIFT);
    888       1.2    briggs 	pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io);
    889       1.2    briggs 	pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh);
    890       1.1    briggs 
    891       1.1    briggs 	/* Configure mem base & limit */
    892       1.1    briggs 	if (pb->memext) {
    893       1.1    briggs 		mem_base = pb->memext->ex_start;
    894       1.1    briggs 		mem_limit = pb->memext->ex_end;
    895       1.2    briggs 	} else {
    896       1.2    briggs 		mem_base  = 0x100000;	/* 1M */
    897       1.2    briggs 		mem_limit = 0x000000;
    898       1.1    briggs 	}
    899      1.19   thorpej #if ULONG_MAX > 0xffffffff
    900       1.2    briggs 	if (mem_limit > 0xFFFFFFFFULL) {
    901       1.2    briggs 		printf("Bus %d bridge MEM range out of range.  ", pb->busno);
    902       1.2    briggs 		printf("Disabling MEM accesses\n");
    903       1.2    briggs 		mem_base  = 0x100000;	/* 1M */
    904       1.2    briggs 		mem_limit = 0x000000;
    905       1.2    briggs 	}
    906      1.19   thorpej #endif
    907       1.2    briggs 	mem = (((mem_base >> 20) & PCI_BRIDGE_MEMORY_BASE_MASK)
    908       1.2    briggs 	    << PCI_BRIDGE_MEMORY_BASE_SHIFT);
    909       1.2    briggs 	mem |= (((mem_limit >> 20) & PCI_BRIDGE_MEMORY_LIMIT_MASK)
    910       1.2    briggs 	    << PCI_BRIDGE_MEMORY_LIMIT_SHIFT);
    911       1.2    briggs 	pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem);
    912       1.1    briggs 
    913       1.1    briggs 	/* Configure prefetchable mem base & limit */
    914       1.1    briggs 	if (pb->pmemext) {
    915       1.1    briggs 		mem_base = pb->pmemext->ex_start;
    916       1.1    briggs 		mem_limit = pb->pmemext->ex_end;
    917       1.2    briggs 	} else {
    918       1.2    briggs 		mem_base  = 0x100000;	/* 1M */
    919       1.2    briggs 		mem_limit = 0x000000;
    920       1.1    briggs 	}
    921       1.2    briggs 	mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG);
    922      1.19   thorpej #if ULONG_MAX > 0xffffffff
    923       1.2    briggs 	if (!PCI_BRIDGE_PREFETCHMEM_64BITS(mem) && mem_limit > 0xFFFFFFFFULL) {
    924       1.2    briggs 		printf("Bus %d bridge does not support 64-bit PMEM.  ",
    925       1.2    briggs 		    pb->busno);
    926       1.2    briggs 		printf("Disabling prefetchable-MEM accesses\n");
    927       1.2    briggs 		mem_base  = 0x100000;	/* 1M */
    928       1.2    briggs 		mem_limit = 0x000000;
    929       1.2    briggs 	}
    930      1.19   thorpej #endif
    931       1.2    briggs 	mem = (((mem_base >> 20) & PCI_BRIDGE_PREFETCHMEM_BASE_MASK)
    932       1.2    briggs 	    << PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT);
    933       1.2    briggs 	mem |= (((mem_limit >> 20) & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK)
    934       1.2    briggs 	    << PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT);
    935       1.2    briggs 	pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem);
    936       1.2    briggs 	/*
    937       1.2    briggs 	 * XXX -- 64-bit systems need a lot more than just this...
    938       1.2    briggs 	 */
    939      1.32      matt 	if (PCI_BRIDGE_PREFETCHMEM_64BITS(mem)) {
    940      1.32      matt 		mem_base  = (uint64_t) mem_base  >> 32;
    941      1.32      matt 		mem_limit = (uint64_t) mem_limit >> 32;
    942      1.32      matt 		pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHBASE32_REG,
    943      1.32      matt 		    mem_base & 0xffffffff);
    944      1.32      matt 		pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHLIMIT32_REG,
    945      1.32      matt 		    mem_limit & 0xffffffff);
    946      1.32      matt 	}
    947       1.1    briggs 
    948       1.1    briggs 	rv = configure_bus(pb);
    949       1.1    briggs 
    950       1.1    briggs 	if (pb->ioext)
    951       1.1    briggs 		extent_destroy(pb->ioext);
    952       1.1    briggs 	if (pb->memext)
    953       1.1    briggs 		extent_destroy(pb->memext);
    954       1.1    briggs 	if (pb->pmemext)
    955       1.1    briggs 		extent_destroy(pb->pmemext);
    956       1.1    briggs 	if (rv == 0) {
    957       1.1    briggs 		cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG);
    958       1.1    briggs 		cmd &= PCI_BRIDGE_CONTROL_MASK;
    959       1.1    briggs 		cmd |= (PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR)
    960       1.1    briggs 		    << PCI_BRIDGE_CONTROL_SHIFT;
    961       1.1    briggs 		if (pb->fast_b2b) {
    962       1.1    briggs 			cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B
    963       1.1    briggs 			    << PCI_BRIDGE_CONTROL_SHIFT;
    964       1.1    briggs 		}
    965       1.1    briggs 		pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd);
    966       1.1    briggs 		cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG);
    967       1.1    briggs 		cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE;
    968       1.1    briggs 		pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd);
    969       1.1    briggs 	}
    970       1.1    briggs 
    971       1.1    briggs 	return rv;
    972       1.1    briggs }
    973       1.1    briggs 
    974       1.1    briggs /*
    975       1.1    briggs  * Calculate latency values, allocate I/O and MEM segments, then set them
    976       1.1    briggs  * up.  If a PCI-PCI bridge is found, configure the bridge separately,
    977       1.1    briggs  * which will cause a recursive call back here.
    978       1.1    briggs  */
    979       1.1    briggs static int
    980       1.1    briggs configure_bus(pciconf_bus_t *pb)
    981       1.1    briggs {
    982       1.1    briggs 	pciconf_dev_t	*pd;
    983       1.8    briggs 	int		def_ltim, max_ltim, band, bus_mhz;
    984       1.1    briggs 
    985      1.20    simonb 	if (pb->ndevs == 0) {
    986      1.20    simonb 		if (pci_conf_debug)
    987      1.20    simonb 			printf("PCI bus %d - no devices\n", pb->busno);
    988      1.20    simonb 		return (1);
    989      1.20    simonb 	}
    990       1.8    briggs 	bus_mhz = pb->freq_66 ? 66 : 33;
    991       1.8    briggs 	max_ltim = pb->max_mingnt * bus_mhz / 4;	/* cvt to cycle count */
    992      1.30    briggs 	band = 4000000;					/* 0.25us cycles/sec */
    993       1.1    briggs 	if (band < pb->bandwidth_used) {
    994      1.31     gavan 		printf("PCI bus %d: Warning: Total bandwidth exceeded!? (%d)\n",
    995      1.31     gavan 		    pb->busno, pb->bandwidth_used);
    996       1.1    briggs 		def_ltim = -1;
    997       1.1    briggs 	} else {
    998       1.1    briggs 		def_ltim = (band - pb->bandwidth_used) / pb->ndevs;
    999       1.1    briggs 		if (def_ltim > pb->min_maxlat)
   1000       1.1    briggs 			def_ltim = pb->min_maxlat;
   1001       1.8    briggs 		def_ltim = def_ltim * bus_mhz / 4;
   1002       1.1    briggs 	}
   1003       1.1    briggs 	def_ltim = (def_ltim + 7) & ~7;
   1004       1.1    briggs 	max_ltim = (max_ltim + 7) & ~7;
   1005       1.1    briggs 
   1006       1.1    briggs 	pb->def_ltim = MIN( def_ltim, 255 );
   1007       1.1    briggs 	pb->max_ltim = MIN( MAX(max_ltim, def_ltim ), 255 );
   1008       1.1    briggs 
   1009       1.1    briggs 	/*
   1010       1.1    briggs 	 * Now we have what we need to initialize the devices.
   1011       1.1    briggs 	 * It would probably be better if we could allocate all of these
   1012       1.1    briggs 	 * for all busses at once, but "not right now".  First, get a list
   1013       1.1    briggs 	 * of free memory ranges from the m.d. system.
   1014       1.1    briggs 	 */
   1015       1.1    briggs 	if (setup_iowins(pb) || setup_memwins(pb)) {
   1016  1.34.6.1       tls 		printf("PCI bus configuration failed: "
   1017  1.34.6.1       tls 		"unable to assign all I/O and memory ranges.\n");
   1018       1.1    briggs 		return -1;
   1019       1.1    briggs 	}
   1020       1.1    briggs 
   1021       1.1    briggs 	/*
   1022       1.1    briggs 	 * Configure the latency for the devices, and enable them.
   1023       1.1    briggs 	 */
   1024       1.1    briggs 	for (pd=pb->device ; pd < &pb->device[pb->ndevs] ; pd++) {
   1025       1.1    briggs 		pcireg_t cmd, class, misc;
   1026       1.1    briggs 		int	ltim;
   1027       1.1    briggs 
   1028       1.1    briggs 		if (pci_conf_debug) {
   1029       1.1    briggs 			print_tag(pd->pc, pd->tag);
   1030       1.1    briggs 			printf("Configuring device.\n");
   1031       1.1    briggs 		}
   1032       1.1    briggs 		class = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG);
   1033       1.1    briggs 		misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG);
   1034       1.1    briggs 		cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG);
   1035      1.26   tsutsui 		if (pd->enable & PCI_CONF_ENABLE_PARITY)
   1036      1.26   tsutsui 			cmd |= PCI_COMMAND_PARITY_ENABLE;
   1037      1.26   tsutsui 		if (pd->enable & PCI_CONF_ENABLE_SERR)
   1038      1.26   tsutsui 			cmd |= PCI_COMMAND_SERR_ENABLE;
   1039       1.1    briggs 		if (pb->fast_b2b)
   1040       1.1    briggs 			cmd |= PCI_COMMAND_BACKTOBACK_ENABLE;
   1041       1.1    briggs 		if (PCI_CLASS(class) != PCI_CLASS_BRIDGE ||
   1042       1.1    briggs 		    PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_PCI) {
   1043       1.8    briggs 			if (pd->enable & PCI_CONF_ENABLE_IO)
   1044       1.8    briggs 				cmd |= PCI_COMMAND_IO_ENABLE;
   1045       1.8    briggs 			if (pd->enable & PCI_CONF_ENABLE_MEM)
   1046       1.8    briggs 				cmd |= PCI_COMMAND_MEM_ENABLE;
   1047       1.8    briggs 			if (pd->enable & PCI_CONF_ENABLE_BM)
   1048       1.8    briggs 				cmd |= PCI_COMMAND_MASTER_ENABLE;
   1049       1.8    briggs 			ltim = pd->min_gnt * bus_mhz / 4;
   1050       1.1    briggs 			ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim);
   1051       1.1    briggs 		} else {
   1052       1.8    briggs 			cmd |= PCI_COMMAND_MASTER_ENABLE;
   1053       1.1    briggs 			ltim = MIN (pb->def_ltim, pb->max_ltim);
   1054       1.1    briggs 		}
   1055      1.26   tsutsui 		if ((pd->enable &
   1056      1.26   tsutsui 		    (PCI_CONF_ENABLE_MEM|PCI_CONF_ENABLE_IO)) == 0) {
   1057       1.2    briggs 			print_tag(pd->pc, pd->tag);
   1058       1.2    briggs 			printf("Disabled due to lack of resources.\n");
   1059       1.2    briggs 			cmd &= ~(PCI_COMMAND_MASTER_ENABLE |
   1060       1.2    briggs 			    PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE);
   1061       1.2    briggs 		}
   1062       1.1    briggs 		pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd);
   1063       1.1    briggs 
   1064      1.14   thorpej 		misc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) |
   1065      1.14   thorpej 		    (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT));
   1066      1.14   thorpej 		misc |= (ltim & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT;
   1067      1.15    kleink 		misc |= ((pb->cacheline_size >> 2) & PCI_CACHELINE_MASK) <<
   1068      1.14   thorpej 		    PCI_CACHELINE_SHIFT;
   1069       1.1    briggs 		pci_conf_write(pd->pc, pd->tag, PCI_BHLC_REG, misc);
   1070       1.1    briggs 
   1071       1.1    briggs 		if (pd->ppb) {
   1072       1.1    briggs 			if (configure_bridge(pd) < 0)
   1073       1.1    briggs 				return -1;
   1074       1.1    briggs 			continue;
   1075       1.1    briggs 		}
   1076       1.1    briggs 	}
   1077       1.1    briggs 
   1078       1.1    briggs 	if (pci_conf_debug) {
   1079       1.1    briggs 		printf("PCI bus %d configured\n", pb->busno);
   1080       1.1    briggs 	}
   1081       1.1    briggs 
   1082       1.1    briggs 	return 0;
   1083       1.1    briggs }
   1084       1.1    briggs 
   1085       1.1    briggs /*
   1086       1.1    briggs  * Let's configure the PCI bus.
   1087       1.1    briggs  * This consists of basically scanning for all existing devices,
   1088       1.1    briggs  * identifying their needs, and then making another pass over them
   1089       1.1    briggs  * to set:
   1090       1.1    briggs  *	1. I/O addresses
   1091       1.1    briggs  *	2. Memory addresses (Prefetchable and not)
   1092       1.1    briggs  *	3. PCI command register
   1093       1.1    briggs  *	4. The latency part of the PCI BHLC (BIST (Built-In Self Test),
   1094       1.1    briggs  *	    Header type, Latency timer, Cache line size) register
   1095       1.1    briggs  *
   1096       1.1    briggs  * The command register is set to enable fast back-to-back transactions
   1097      1.25     perry  * if the host bridge says it can handle it.  We also configure
   1098       1.1    briggs  * Master Enable, SERR enable, parity enable, and (if this is not a
   1099       1.1    briggs  * PCI-PCI bridge) the I/O and Memory spaces.  Apparently some devices
   1100       1.1    briggs  * will not report some I/O space.
   1101       1.1    briggs  *
   1102       1.1    briggs  * The latency is computed to be a "fair share" of the bus bandwidth.
   1103       1.1    briggs  * The bus bandwidth variable is initialized to the number of PCI cycles
   1104       1.1    briggs  * in one second.  The number of cycles taken for one transaction by each
   1105       1.1    briggs  * device (MAX_LAT + MIN_GNT) is then subtracted from the bandwidth.
   1106       1.1    briggs  * Care is taken to ensure that the latency timer won't be set such that
   1107       1.1    briggs  * it would exceed the critical time for any device.
   1108       1.1    briggs  *
   1109       1.1    briggs  * This is complicated somewhat due to the presence of bridges.  PCI-PCI
   1110       1.1    briggs  * bridges are probed and configured recursively.
   1111       1.1    briggs  */
   1112       1.1    briggs int
   1113       1.1    briggs pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext,
   1114      1.14   thorpej     struct extent *memext, struct extent *pmemext, int firstbus,
   1115      1.14   thorpej     int cacheline_size)
   1116       1.1    briggs {
   1117       1.1    briggs 	pciconf_bus_t	*pb;
   1118       1.1    briggs 	int		rv;
   1119       1.1    briggs 
   1120      1.32      matt 	pb = kmem_zalloc(sizeof (pciconf_bus_t), KM_NOSLEEP);
   1121      1.12   thorpej 	pb->busno = firstbus;
   1122       1.1    briggs 	pb->next_busno = pb->busno + 1;
   1123       1.1    briggs 	pb->last_busno = 255;
   1124      1.14   thorpej 	pb->cacheline_size = cacheline_size;
   1125       1.1    briggs 	pb->parent_bus = NULL;
   1126       1.1    briggs 	pb->swiz = 0;
   1127       1.2    briggs 	pb->io_32bit = 1;
   1128       1.2    briggs 	pb->pmem_64bit = 0;
   1129       1.1    briggs 	pb->ioext = ioext;
   1130       1.1    briggs 	pb->memext = memext;
   1131       1.1    briggs 	if (pmemext == NULL) {
   1132       1.1    briggs 		pb->pmemext = memext;
   1133       1.1    briggs 	} else {
   1134       1.1    briggs 		pb->pmemext = pmemext;
   1135       1.1    briggs 	}
   1136       1.1    briggs 	pb->pc = pc;
   1137       1.1    briggs 	pb->io_total = pb->mem_total = pb->pmem_total = 0;
   1138       1.1    briggs 
   1139       1.1    briggs 	rv = probe_bus(pb);
   1140      1.17  augustss 	pb->last_busno = pb->next_busno-1;
   1141       1.1    briggs 	if (rv == 0) {
   1142       1.1    briggs 		rv = configure_bus(pb);
   1143       1.1    briggs 	}
   1144       1.1    briggs 
   1145       1.1    briggs 	/*
   1146       1.1    briggs 	 * All done!
   1147       1.1    briggs 	 */
   1148      1.32      matt 	kmem_free(pb, sizeof(*pb));
   1149       1.1    briggs 	return rv;
   1150       1.1    briggs }
   1151