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pciconf.c revision 1.4
      1  1.4   simonb /*	$NetBSD: pciconf.c,v 1.4 2001/06/13 06:01:45 simonb Exp $	*/
      2  1.1   briggs 
      3  1.1   briggs /*
      4  1.1   briggs  * Copyright 2001 Wasabi Systems, Inc.
      5  1.1   briggs  * All rights reserved.
      6  1.1   briggs  *
      7  1.1   briggs  * Written by Allen Briggs for Wasabi Systems, Inc.
      8  1.1   briggs  *
      9  1.1   briggs  * Redistribution and use in source and binary forms, with or without
     10  1.1   briggs  * modification, are permitted provided that the following conditions
     11  1.1   briggs  * are met:
     12  1.1   briggs  * 1. Redistributions of source code must retain the above copyright
     13  1.1   briggs  *    notice, this list of conditions and the following disclaimer.
     14  1.1   briggs  * 2. Redistributions in binary form must reproduce the above copyright
     15  1.1   briggs  *    notice, this list of conditions and the following disclaimer in the
     16  1.1   briggs  *    documentation and/or other materials provided with the distribution.
     17  1.1   briggs  * 3. All advertising materials mentioning features or use of this software
     18  1.1   briggs  *    must display the following acknowledgement:
     19  1.1   briggs  *      This product includes software developed for the NetBSD Project by
     20  1.1   briggs  *      Wasabi Systems, Inc.
     21  1.1   briggs  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     22  1.1   briggs  *    or promote products derived from this software without specific prior
     23  1.1   briggs  *    written permission.
     24  1.1   briggs  *
     25  1.1   briggs  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     26  1.1   briggs  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     27  1.1   briggs  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     28  1.1   briggs  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     29  1.1   briggs  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     30  1.1   briggs  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     31  1.1   briggs  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     32  1.1   briggs  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     33  1.1   briggs  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     34  1.1   briggs  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     35  1.1   briggs  * POSSIBILITY OF SUCH DAMAGE.
     36  1.1   briggs  */
     37  1.1   briggs /*
     38  1.1   briggs  * Derived in part from code from PMON/2000 (http://pmon.groupbsd.org/).
     39  1.1   briggs  */
     40  1.1   briggs 
     41  1.2   briggs /*
     42  1.2   briggs  * To do:
     43  1.2   briggs  *    - Deal with "anything can be hot-plugged" -- i.e., carry configuration
     44  1.2   briggs  *	information around & be able to reconfigure on the fly.
     45  1.2   briggs  *    - Deal with segments (See IA64 System Abstraction Layer)
     46  1.2   briggs  *    - Deal with subtractive bridges (& non-spec positive/subtractive decode)
     47  1.2   briggs  *    - Deal with ISA/VGA/VGA palette snooping
     48  1.2   briggs  *    - Deal with device capabilities on bridges
     49  1.2   briggs  *    - Worry about changing a bridge to/from transparency.
     50  1.2   briggs  */
     51  1.2   briggs 
     52  1.1   briggs #include "opt_pci.h"
     53  1.1   briggs 
     54  1.1   briggs #include <sys/param.h>
     55  1.1   briggs #include <sys/extent.h>
     56  1.1   briggs #include <sys/queue.h>
     57  1.1   briggs #include <sys/systm.h>
     58  1.1   briggs #include <sys/malloc.h>
     59  1.1   briggs 
     60  1.1   briggs #include <dev/pci/pcivar.h>
     61  1.1   briggs #include <dev/pci/pciconf.h>
     62  1.1   briggs #include <dev/pci/pcidevs.h>
     63  1.1   briggs 
     64  1.1   briggs int pci_conf_debug = 0;
     65  1.1   briggs 
     66  1.1   briggs #if !defined(MIN)
     67  1.1   briggs #define	MIN(a,b) (((a)<(b))?(a):(b))
     68  1.1   briggs #define	MAX(a,b) (((a)>(b))?(a):(b))
     69  1.1   briggs #endif
     70  1.1   briggs 
     71  1.1   briggs /* per-bus constants. */
     72  1.1   briggs #define MAX_CONF_DEV	8			/* Arbitrary */
     73  1.1   briggs #define MAX_CONF_MEM	(3 * MAX_CONF_DEV)	/* Avg. 3 per device -- Arb. */
     74  1.1   briggs #define MAX_CONF_IO	(1 * MAX_CONF_DEV)	/* Avg. 1 per device -- Arb. */
     75  1.1   briggs 
     76  1.1   briggs #define PCI_BUSNO_SPACING	(1 << 5)
     77  1.1   briggs 
     78  1.1   briggs struct _s_pciconf_bus_t;			/* Forward declaration */
     79  1.1   briggs 
     80  1.1   briggs typedef struct _s_pciconf_dev_t {
     81  1.1   briggs 	int		ipin;
     82  1.1   briggs 	int		iline;
     83  1.1   briggs 	int		min_gnt;
     84  1.1   briggs 	int		max_lat;
     85  1.2   briggs 	int		enable;
     86  1.1   briggs 	pcitag_t	tag;
     87  1.1   briggs 	pci_chipset_tag_t	pc;
     88  1.1   briggs 	struct _s_pciconf_bus_t	*ppb;		/* I am really a bridge */
     89  1.1   briggs } pciconf_dev_t;
     90  1.1   briggs 
     91  1.1   briggs typedef struct _s_pciconf_win_t {
     92  1.1   briggs 	pciconf_dev_t	*dev;
     93  1.1   briggs 	int		reg;			/* 0 for busses */
     94  1.1   briggs 	int		align;
     95  1.1   briggs 	int		prefetch;
     96  1.1   briggs 	u_int64_t	size;
     97  1.1   briggs 	u_int64_t	address;
     98  1.1   briggs } pciconf_win_t;
     99  1.1   briggs 
    100  1.1   briggs typedef struct _s_pciconf_bus_t {
    101  1.1   briggs 	int		busno;
    102  1.1   briggs 	int		next_busno;
    103  1.1   briggs 	int		last_busno;
    104  1.1   briggs 	int		busno_spacing;
    105  1.1   briggs 	int		max_mingnt;
    106  1.1   briggs 	int		min_maxlat;
    107  1.1   briggs 	int		prefetch;
    108  1.1   briggs 	int		fast_b2b;
    109  1.1   briggs 	int		freq_66;
    110  1.1   briggs 	int		def_ltim;
    111  1.1   briggs 	int		max_ltim;
    112  1.1   briggs 	int		bandwidth_used;
    113  1.1   briggs 	int		swiz;
    114  1.2   briggs 	int		io_32bit;
    115  1.2   briggs 	int		pmem_64bit;
    116  1.1   briggs 
    117  1.1   briggs 	int		ndevs;
    118  1.1   briggs 	pciconf_dev_t	device[MAX_CONF_DEV];
    119  1.1   briggs 
    120  1.1   briggs 	/* These should be sorted in order of decreasing size */
    121  1.1   briggs 	int		nmemwin;
    122  1.1   briggs 	pciconf_win_t	pcimemwin[MAX_CONF_MEM];
    123  1.1   briggs 	int		niowin;
    124  1.1   briggs 	pciconf_win_t	pciiowin[MAX_CONF_IO];
    125  1.1   briggs 
    126  1.1   briggs 	bus_size_t	io_total;
    127  1.1   briggs 	bus_size_t	mem_total;
    128  1.1   briggs 	bus_size_t	pmem_total;
    129  1.1   briggs 
    130  1.1   briggs 	struct extent	*ioext;
    131  1.1   briggs 	struct extent	*memext;
    132  1.1   briggs 	struct extent	*pmemext;
    133  1.1   briggs 
    134  1.1   briggs 	pci_chipset_tag_t	pc;
    135  1.1   briggs 	struct _s_pciconf_bus_t *parent_bus;
    136  1.1   briggs } pciconf_bus_t;
    137  1.1   briggs 
    138  1.1   briggs static int	probe_bus(pciconf_bus_t *);
    139  1.1   briggs static void	alloc_busno(pciconf_bus_t *, pciconf_bus_t *);
    140  1.4   simonb static int	pci_do_device_query(pciconf_bus_t *, pcitag_t, int, int, int);
    141  1.1   briggs static int	setup_iowins(pciconf_bus_t *);
    142  1.1   briggs static int	setup_memwins(pciconf_bus_t *);
    143  1.1   briggs static int	configure_bridge(pciconf_dev_t *);
    144  1.1   briggs static int	configure_bus(pciconf_bus_t *);
    145  1.1   briggs static u_int64_t	pci_allocate_range(struct extent *, u_int64_t, int);
    146  1.1   briggs static pciconf_win_t	*get_io_desc(pciconf_bus_t *, bus_size_t);
    147  1.1   briggs static pciconf_win_t	*get_mem_desc(pciconf_bus_t *, bus_size_t);
    148  1.1   briggs static pciconf_bus_t	*query_bus(pciconf_bus_t *, pciconf_dev_t *, int);
    149  1.1   briggs 
    150  1.1   briggs static void	print_tag(pci_chipset_tag_t, pcitag_t);
    151  1.1   briggs 
    152  1.1   briggs static void
    153  1.1   briggs print_tag(pci_chipset_tag_t pc, pcitag_t tag)
    154  1.1   briggs {
    155  1.1   briggs 	int	bus, dev, func;
    156  1.1   briggs 
    157  1.1   briggs 	pci_decompose_tag(pc, tag, &bus, &dev, &func);
    158  1.1   briggs 	printf("PCI: bus %d, device %d, function %d: ", bus, dev, func);
    159  1.1   briggs }
    160  1.1   briggs 
    161  1.1   briggs /************************************************************************/
    162  1.1   briggs /************************************************************************/
    163  1.1   briggs /***********************   Bus probing routines   ***********************/
    164  1.1   briggs /************************************************************************/
    165  1.1   briggs /************************************************************************/
    166  1.1   briggs static pciconf_win_t *
    167  1.1   briggs get_io_desc(pciconf_bus_t *pb, bus_size_t size)
    168  1.1   briggs {
    169  1.1   briggs 	int	i, n;
    170  1.1   briggs 
    171  1.1   briggs 	n = pb->niowin;
    172  1.1   briggs 	for (i=n; i > 0 && size > pb->pciiowin[i-1].size; i--)
    173  1.1   briggs 		pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */
    174  1.1   briggs 	return &pb->pciiowin[i];
    175  1.1   briggs }
    176  1.1   briggs 
    177  1.1   briggs static pciconf_win_t *
    178  1.1   briggs get_mem_desc(pciconf_bus_t *pb, bus_size_t size)
    179  1.1   briggs {
    180  1.1   briggs 	int	i, n;
    181  1.1   briggs 
    182  1.1   briggs 	n = pb->nmemwin;
    183  1.1   briggs 	for (i=n; i > 0 && size > pb->pcimemwin[i-1].size; i--)
    184  1.1   briggs 		pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */
    185  1.1   briggs 	return &pb->pcimemwin[i];
    186  1.1   briggs }
    187  1.1   briggs 
    188  1.1   briggs /*
    189  1.1   briggs  * Set up bus common stuff, then loop over devices & functions.
    190  1.1   briggs  * If we find something, call pci_do_device_query()).
    191  1.1   briggs  */
    192  1.1   briggs static int
    193  1.1   briggs probe_bus(pciconf_bus_t *pb)
    194  1.1   briggs {
    195  1.1   briggs 	int device, maxdevs;
    196  1.1   briggs 
    197  1.1   briggs 	maxdevs = pci_bus_maxdevs(pb->pc, pb->busno);
    198  1.1   briggs 	pb->ndevs = 0;
    199  1.1   briggs 	pb->niowin = 0;
    200  1.1   briggs 	pb->nmemwin = 0;
    201  1.1   briggs 	pb->freq_66 = 1;
    202  1.1   briggs 	pb->fast_b2b = 1;
    203  1.1   briggs 	pb->prefetch = 1;
    204  1.1   briggs 	pb->max_mingnt = 0;	/* we are looking for the maximum */
    205  1.1   briggs 	pb->min_maxlat = 0x100;	/* we are looking for the minimum */
    206  1.1   briggs 	pb->bandwidth_used = 0;
    207  1.4   simonb 
    208  1.1   briggs 	for (device=0; device < maxdevs; device++) {
    209  1.1   briggs 		pcitag_t tag;
    210  1.1   briggs 		pcireg_t id, bhlcr;
    211  1.1   briggs 		int function, nfunction;
    212  1.4   simonb 		int confmode;
    213  1.1   briggs 
    214  1.1   briggs 		tag = pci_make_tag(pb->pc, pb->busno, device, 0);
    215  1.1   briggs 		if (pci_conf_debug) {
    216  1.1   briggs 			print_tag(pb->pc, tag);
    217  1.4   simonb 			printf("probing with tag %x.\n", tag);
    218  1.1   briggs 		}
    219  1.1   briggs 		id = pci_conf_read(pb->pc, tag, PCI_ID_REG);
    220  1.1   briggs 
    221  1.4   simonb 		if (pci_conf_debug) {
    222  1.4   simonb 			printf("id=%x: Vendor=%x, Product=%x\n",
    223  1.4   simonb 			    id, PCI_VENDOR(id),PCI_PRODUCT(id));
    224  1.4   simonb 		}
    225  1.1   briggs 		/* Invalid vendor ID value? */
    226  1.1   briggs 		if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
    227  1.1   briggs 			continue;
    228  1.1   briggs 
    229  1.1   briggs 		bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG);
    230  1.1   briggs 		nfunction = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1;
    231  1.1   briggs 		for (function = 0 ; function < nfunction ; function++) {
    232  1.1   briggs 			tag = pci_make_tag(pb->pc, pb->busno, device, function);
    233  1.1   briggs 			id = pci_conf_read(pb->pc, tag, PCI_ID_REG);
    234  1.1   briggs 			if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
    235  1.1   briggs 				continue;
    236  1.1   briggs 			if (pb->ndevs+1 < MAX_CONF_DEV) {
    237  1.1   briggs 				if (pci_conf_debug) {
    238  1.1   briggs 					print_tag(pb->pc, tag);
    239  1.3  thorpej 					printf("Found dev 0x%04x 0x%04x -- "
    240  1.3  thorpej 					    "really probing.\n",
    241  1.3  thorpej 					PCI_VENDOR(id), PCI_PRODUCT(id));
    242  1.1   briggs 				}
    243  1.4   simonb #ifdef __HAVE_PCI_CONF_HOOK
    244  1.4   simonb 				confmode = pci_conf_hook(pb->pc, pb->busno,
    245  1.4   simonb 				    device, function, id);
    246  1.4   simonb 				if (confmode == 0)
    247  1.4   simonb 					continue;
    248  1.4   simonb #else
    249  1.4   simonb 				confmode = PCI_CONF_ALL;
    250  1.4   simonb #endif
    251  1.1   briggs 				if (pci_do_device_query(pb, tag, device,
    252  1.4   simonb 				    function, confmode))
    253  1.1   briggs 					return -1;
    254  1.1   briggs 				pb->ndevs++;
    255  1.1   briggs 			}
    256  1.1   briggs 		}
    257  1.1   briggs 	}
    258  1.1   briggs 	return 0;
    259  1.1   briggs }
    260  1.1   briggs 
    261  1.1   briggs static void
    262  1.1   briggs alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb)
    263  1.1   briggs {
    264  1.1   briggs 	pb->busno = parent->next_busno;
    265  1.1   briggs 	if (parent->next_busno + parent->busno_spacing > parent->last_busno)
    266  1.1   briggs 		panic("Too many PCI busses on bus %d", parent->busno);
    267  1.1   briggs 	parent->next_busno = parent->next_busno + parent->busno_spacing;
    268  1.1   briggs 	pb->next_busno = pb->busno+1;
    269  1.1   briggs 	pb->busno_spacing = parent->busno_spacing >> 1;
    270  1.1   briggs 	if (!pb->busno_spacing)
    271  1.1   briggs 		panic("PCI busses nested too deep.");
    272  1.1   briggs 	pb->last_busno = parent->next_busno - 1;
    273  1.1   briggs }
    274  1.1   briggs 
    275  1.1   briggs static pciconf_bus_t *
    276  1.1   briggs query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev)
    277  1.1   briggs {
    278  1.1   briggs 	pciconf_bus_t	*pb;
    279  1.2   briggs 	pcireg_t	busreg, io, pmem;
    280  1.1   briggs 	pciconf_win_t	*pi, *pm;
    281  1.1   briggs 
    282  1.1   briggs 	pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT);
    283  1.1   briggs 	if (!pb)
    284  1.1   briggs 		panic("Unable to allocate memory for PCI configuration.");
    285  1.1   briggs 
    286  1.1   briggs 	pb->parent_bus = parent;
    287  1.1   briggs 	alloc_busno(parent, pb);
    288  1.1   briggs 	if (pci_conf_debug)
    289  1.1   briggs 		printf("PCI bus bridge covers busses %d-%d\n",
    290  1.1   briggs 			pb->busno, pb->last_busno);
    291  1.1   briggs 
    292  1.1   briggs 	busreg  =  parent->busno << PCI_BRIDGE_BUS_PRIMARY_SHIFT;
    293  1.1   briggs 	busreg |=      pb->busno << PCI_BRIDGE_BUS_SECONDARY_SHIFT;
    294  1.1   briggs 	busreg |= pb->last_busno << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT;
    295  1.1   briggs 	pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_BUS_REG, busreg);
    296  1.1   briggs 
    297  1.1   briggs 	pb->swiz = parent->swiz + dev;
    298  1.1   briggs 
    299  1.1   briggs 	pb->ioext = NULL;
    300  1.1   briggs 	pb->memext = NULL;
    301  1.1   briggs 	pb->pmemext = NULL;
    302  1.1   briggs 	pb->pc = parent->pc;
    303  1.1   briggs 	pb->io_total = pb->mem_total = pb->pmem_total = 0;
    304  1.1   briggs 
    305  1.2   briggs 	pb->io_32bit = 0;
    306  1.2   briggs 	if (parent->io_32bit) {
    307  1.2   briggs 		io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG);
    308  1.2   briggs 		if (PCI_BRIDGE_IO_32BITS(io)) {
    309  1.2   briggs 			pb->io_32bit = 1;
    310  1.2   briggs 		}
    311  1.2   briggs 	}
    312  1.2   briggs 
    313  1.2   briggs 	pb->pmem_64bit = 0;
    314  1.2   briggs 	if (parent->pmem_64bit) {
    315  1.2   briggs 		pmem = pci_conf_read(pb->pc, pd->tag,
    316  1.2   briggs 		    PCI_BRIDGE_PREFETCHMEM_REG);
    317  1.2   briggs 		if (PCI_BRIDGE_PREFETCHMEM_64BITS(pmem)) {
    318  1.2   briggs 			pb->pmem_64bit = 1;
    319  1.2   briggs 		}
    320  1.2   briggs 	}
    321  1.2   briggs 
    322  1.1   briggs 	if (probe_bus(pb)) {
    323  1.1   briggs 		printf("Failed to probe bus %d\n", pb->busno);
    324  1.1   briggs 		goto err;
    325  1.1   briggs 	}
    326  1.1   briggs 
    327  1.1   briggs 	if (pb->io_total > 0) {
    328  1.1   briggs 		if (parent->niowin >= MAX_CONF_IO) {
    329  1.1   briggs 			printf("pciconf: too many I/O windows");
    330  1.1   briggs 			goto err;
    331  1.1   briggs 		}
    332  1.1   briggs 		pb->io_total |= 0xfff;	/* Round up */
    333  1.1   briggs 		pi = get_io_desc(parent, pb->io_total);
    334  1.1   briggs 		pi->dev = pd;
    335  1.1   briggs 		pi->reg = 0;
    336  1.1   briggs 		pi->size = pb->io_total;
    337  1.1   briggs 		pi->align = 0x1000;	/* 4K alignment */
    338  1.1   briggs 		pi->prefetch = 0;
    339  1.1   briggs 		parent->niowin++;
    340  1.1   briggs 		parent->io_total += pb->io_total;
    341  1.1   briggs 	}
    342  1.1   briggs 
    343  1.1   briggs 	if (pb->mem_total > 0) {
    344  1.1   briggs 		if (parent->nmemwin >= MAX_CONF_MEM) {
    345  1.1   briggs 			printf("pciconf: too many MEM windows");
    346  1.1   briggs 			goto err;
    347  1.1   briggs 		}
    348  1.1   briggs 		pb->mem_total |= 0xfffff;	/* Round up */
    349  1.1   briggs 		pm = get_mem_desc(parent, pb->mem_total);
    350  1.1   briggs 		pm->dev = pd;
    351  1.1   briggs 		pm->reg = 0;
    352  1.1   briggs 		pm->size = pb->mem_total;
    353  1.1   briggs 		pm->align = 0x100000;	/* 1M alignment */
    354  1.1   briggs 		pm->prefetch = 0;
    355  1.1   briggs 		parent->nmemwin++;
    356  1.1   briggs 		parent->mem_total += pb->mem_total;
    357  1.1   briggs 	}
    358  1.1   briggs 
    359  1.1   briggs 	if (pb->pmem_total > 0) {
    360  1.1   briggs 		if (parent->nmemwin >= MAX_CONF_MEM) {
    361  1.1   briggs 			printf("pciconf: too many MEM windows");
    362  1.1   briggs 			goto err;
    363  1.1   briggs 		}
    364  1.1   briggs 		pb->pmem_total |= 0xfffff;	/* Round up */
    365  1.1   briggs 		pm = get_mem_desc(parent, pb->pmem_total);
    366  1.1   briggs 		pm->dev = pd;
    367  1.1   briggs 		pm->reg = 0;
    368  1.1   briggs 		pm->size = pb->pmem_total;
    369  1.1   briggs 		pm->align = 0x100000;		/* 1M alignment */
    370  1.1   briggs 		pm->prefetch = 1;
    371  1.1   briggs 		parent->nmemwin++;
    372  1.1   briggs 		parent->pmem_total += pb->pmem_total;
    373  1.1   briggs 	}
    374  1.1   briggs 
    375  1.1   briggs 	return pb;
    376  1.1   briggs err:
    377  1.1   briggs 	free(pb, M_DEVBUF);
    378  1.1   briggs 	return NULL;
    379  1.1   briggs }
    380  1.1   briggs 
    381  1.1   briggs static int
    382  1.4   simonb pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func, int mode)
    383  1.1   briggs {
    384  1.1   briggs 	pciconf_dev_t	*pd;
    385  1.1   briggs 	pciconf_win_t	*pi, *pm;
    386  1.1   briggs 	pcireg_t	class, cmd, icr, bar, mask, bar64, mask64;
    387  1.1   briggs 	u_int64_t	size;
    388  1.1   briggs 	int		br, width;
    389  1.1   briggs 
    390  1.1   briggs 	pd = &pb->device[pb->ndevs];
    391  1.1   briggs 	pd->pc = pb->pc;
    392  1.1   briggs 	pd->tag = tag;
    393  1.1   briggs 	pd->ppb = NULL;
    394  1.4   simonb 	pd->enable = mode;
    395  1.1   briggs 
    396  1.1   briggs 	class = pci_conf_read(pb->pc, tag, PCI_CLASS_REG);
    397  1.1   briggs 
    398  1.1   briggs 	cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG);
    399  1.1   briggs 
    400  1.1   briggs 	if (PCI_CLASS(class) != PCI_CLASS_BRIDGE) {
    401  1.1   briggs 		cmd &= ~(PCI_COMMAND_MASTER_ENABLE |
    402  1.1   briggs 		    PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE);
    403  1.1   briggs 		pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd);
    404  1.3  thorpej 	} else if (pci_conf_debug) {
    405  1.3  thorpej 		print_tag(pb->pc, tag);
    406  1.3  thorpej 		printf("device is a bridge; not clearing enables\n");
    407  1.1   briggs 	}
    408  1.1   briggs 
    409  1.1   briggs 	if ((cmd & PCI_STATUS_BACKTOBACK_SUPPORT) == 0)
    410  1.1   briggs 		pb->fast_b2b = 0;
    411  1.1   briggs 
    412  1.1   briggs 	if ((cmd & PCI_STATUS_66MHZ_SUPPORT) == 0)
    413  1.1   briggs 		pb->freq_66 = 0;
    414  1.1   briggs 
    415  1.1   briggs 	if (   (PCI_CLASS(class) == PCI_CLASS_BRIDGE)
    416  1.1   briggs 	    && (PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_PCI)) {
    417  1.1   briggs 		pd->ppb = query_bus(pb, pd, dev);
    418  1.1   briggs 		if (pd->ppb == NULL)
    419  1.1   briggs 			return -1;
    420  1.1   briggs 		return 0;
    421  1.1   briggs 	}
    422  1.1   briggs 
    423  1.1   briggs 	icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG);
    424  1.1   briggs 	pd->ipin = PCI_INTERRUPT_PIN(icr);
    425  1.1   briggs 	pd->iline = PCI_INTERRUPT_LINE(icr);
    426  1.1   briggs 	pd->min_gnt = PCI_MIN_GNT(icr);
    427  1.1   briggs 	pd->max_lat = PCI_MAX_LAT(icr);
    428  1.1   briggs 	if (pd->iline || pd->ipin) {
    429  1.1   briggs 		pci_conf_interrupt(pb->pc, pb->busno, dev, func, pb->swiz,
    430  1.1   briggs 		    &pd->iline);
    431  1.1   briggs 		icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);
    432  1.1   briggs 		icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT);
    433  1.1   briggs 		pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr);
    434  1.1   briggs 	}
    435  1.1   briggs 
    436  1.1   briggs 	if (pd->min_gnt != 0 || pd->max_lat != 0) {
    437  1.1   briggs 		if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt)
    438  1.1   briggs 			pb->max_mingnt = pd->min_gnt;
    439  1.1   briggs 
    440  1.1   briggs 		if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat)
    441  1.1   briggs 			pb->min_maxlat = pd->max_lat;
    442  1.1   briggs 
    443  1.1   briggs 		pb->bandwidth_used += pd->min_gnt * 4000000 /
    444  1.1   briggs 				(pd->min_gnt + pd->max_lat);
    445  1.1   briggs 	}
    446  1.1   briggs 
    447  1.1   briggs 	width = 4;
    448  1.1   briggs 	for (br = PCI_MAPREG_START; br < PCI_MAPREG_END; br += width) {
    449  1.3  thorpej #if 0
    450  1.1   briggs 		if (PCI_CLASS(class) == PCI_CLASS_MASS_STORAGE &&
    451  1.1   briggs 		    PCI_SUBCLASS(class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
    452  1.1   briggs 			break;
    453  1.1   briggs 		}
    454  1.3  thorpej #endif
    455  1.1   briggs 		bar = pci_conf_read(pb->pc, tag, br);
    456  1.3  thorpej 		pci_conf_write(pb->pc, tag, br, 0xffffffff);
    457  1.1   briggs 		mask = pci_conf_read(pb->pc, tag, br);
    458  1.1   briggs 		pci_conf_write(pb->pc, tag, br, bar);
    459  1.1   briggs 		width = 4;
    460  1.1   briggs 
    461  1.3  thorpej 		if (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO) {
    462  1.3  thorpej 			/* Upper 16 bits must be one. */
    463  1.3  thorpej 			/* XXXJRT -- is this really true? */
    464  1.3  thorpej 			mask |= 0xffff0000;
    465  1.3  thorpej 
    466  1.3  thorpej 			size = PCI_MAPREG_IO_SIZE(mask);
    467  1.3  thorpej 			if (size == 0) {
    468  1.3  thorpej 				if (pci_conf_debug) {
    469  1.3  thorpej 					print_tag(pb->pc, tag);
    470  1.3  thorpej 					printf("I/O BAR 0x%x is void\n", br);
    471  1.3  thorpej 				}
    472  1.3  thorpej 				continue;
    473  1.3  thorpej 			}
    474  1.1   briggs 
    475  1.1   briggs 			if (pb->niowin >= MAX_CONF_IO) {
    476  1.1   briggs 				printf("pciconf: too many I/O windows");
    477  1.1   briggs 				return -1;
    478  1.1   briggs 			}
    479  1.1   briggs 
    480  1.1   briggs 			pi = get_io_desc(pb, size);
    481  1.1   briggs 			pi->dev = pd;
    482  1.1   briggs 			pi->reg = br;
    483  1.1   briggs 			pi->size = (u_int64_t) size;
    484  1.1   briggs 			pi->align = 4;
    485  1.1   briggs 			pi->prefetch = 0;
    486  1.1   briggs 			if (pci_conf_debug) {
    487  1.1   briggs 				print_tag(pb->pc, tag);
    488  1.3  thorpej 				printf("Register 0x%x, I/O size %llu\n",
    489  1.1   briggs 				    br, pi->size);
    490  1.1   briggs 			}
    491  1.1   briggs 			pb->niowin++;
    492  1.1   briggs 			pb->io_total += size;
    493  1.4   simonb 		} else if ((mode & PCI_CONF_MAP_MEM)
    494  1.4   simonb 			   && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_MEM)) {
    495  1.1   briggs 			switch (PCI_MAPREG_MEM_TYPE(mask)) {
    496  1.1   briggs 			case PCI_MAPREG_MEM_TYPE_32BIT:
    497  1.1   briggs 			case PCI_MAPREG_MEM_TYPE_32BIT_1M:
    498  1.1   briggs 				size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask);
    499  1.1   briggs 				break;
    500  1.1   briggs 			case PCI_MAPREG_MEM_TYPE_64BIT:
    501  1.1   briggs 				bar64 = pci_conf_read(pb->pc, tag, br + 4);
    502  1.1   briggs 				pci_conf_write(pb->pc, tag, br + 4, 0xffffffff);
    503  1.1   briggs 				mask64 = pci_conf_read(pb->pc, tag, br + 4);
    504  1.1   briggs 				pci_conf_write(pb->pc, tag, br + 4, bar64);
    505  1.1   briggs 				size = (u_int64_t) PCI_MAPREG_MEM64_SIZE(
    506  1.1   briggs 				      (((u_int64_t) mask64) << 32) | mask);
    507  1.1   briggs 				width = 8;
    508  1.1   briggs 				continue;
    509  1.1   briggs 			default:
    510  1.1   briggs 				print_tag(pb->pc, tag);
    511  1.1   briggs 				printf("reserved mapping type 0x%x\n",
    512  1.1   briggs 					PCI_MAPREG_MEM_TYPE(mask));
    513  1.1   briggs 				continue;
    514  1.1   briggs 			}
    515  1.1   briggs 
    516  1.3  thorpej 			if (size == 0) {
    517  1.3  thorpej 				if (pci_conf_debug) {
    518  1.3  thorpej 					print_tag(pb->pc, tag);
    519  1.3  thorpej 					printf("MEM%d BAR 0x%x is void\n",
    520  1.3  thorpej 					    PCI_MAPREG_MEM_TYPE(mask) ==
    521  1.3  thorpej 						PCI_MAPREG_MEM_TYPE_64BIT ?
    522  1.3  thorpej 						64 : 32, br);
    523  1.3  thorpej 				}
    524  1.3  thorpej 				continue;
    525  1.3  thorpej 			}
    526  1.3  thorpej 
    527  1.1   briggs 			if (pb->nmemwin >= MAX_CONF_MEM) {
    528  1.1   briggs 				printf("pciconf: too many memory windows");
    529  1.1   briggs 				return -1;
    530  1.1   briggs 			}
    531  1.1   briggs 
    532  1.1   briggs 			pm = get_mem_desc(pb, size);
    533  1.1   briggs 			pm->dev = pd;
    534  1.1   briggs 			pm->reg = br;
    535  1.1   briggs 			pm->size = size;
    536  1.1   briggs 			pm->align = 4;
    537  1.1   briggs 			pm->prefetch = PCI_MAPREG_MEM_PREFETCHABLE(mask);
    538  1.1   briggs 			if (pci_conf_debug) {
    539  1.1   briggs 				print_tag(pb->pc, tag);
    540  1.3  thorpej 				printf("Register 0x%x, memory size %llu\n",
    541  1.1   briggs 				    br, pm->size);
    542  1.1   briggs 			}
    543  1.1   briggs 			pb->nmemwin++;
    544  1.1   briggs 			if (pm->prefetch) {
    545  1.1   briggs 				pb->pmem_total += size;
    546  1.1   briggs 			} else {
    547  1.1   briggs 				pb->mem_total += size;
    548  1.1   briggs 			}
    549  1.1   briggs 		}
    550  1.1   briggs 	}
    551  1.1   briggs 
    552  1.4   simonb 	if (mode & PCI_CONF_MAP_ROM) {
    553  1.4   simonb 		bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM);
    554  1.4   simonb 		pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe);
    555  1.4   simonb 		mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM);
    556  1.4   simonb 		pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, bar);
    557  1.4   simonb 
    558  1.4   simonb 		if (mask != 0 && mask != 0xffffffff) {
    559  1.4   simonb 			if (pb->nmemwin >= MAX_CONF_MEM) {
    560  1.4   simonb 				printf("pciconf: too many memory windows");
    561  1.4   simonb 				return -1;
    562  1.4   simonb 			}
    563  1.4   simonb 			size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask);
    564  1.1   briggs 
    565  1.4   simonb 			pm = get_mem_desc(pb, size);
    566  1.4   simonb 			pm->dev = pd;
    567  1.4   simonb 			pm->reg = PCI_MAPREG_ROM;
    568  1.4   simonb 			pm->size = size;
    569  1.4   simonb 			pm->align = 4;
    570  1.4   simonb 			pm->prefetch = 1;
    571  1.4   simonb 			if (pci_conf_debug) {
    572  1.4   simonb 				print_tag(pb->pc, tag);
    573  1.4   simonb 				printf("Expansion ROM memory size %llu\n", pm->size);
    574  1.4   simonb 			}
    575  1.4   simonb 			pb->nmemwin++;
    576  1.4   simonb 			pb->pmem_total += size;
    577  1.1   briggs 		}
    578  1.1   briggs 	}
    579  1.1   briggs 
    580  1.1   briggs 	return 0;
    581  1.1   briggs }
    582  1.1   briggs 
    583  1.1   briggs /************************************************************************/
    584  1.1   briggs /************************************************************************/
    585  1.1   briggs /********************   Bus configuration routines   ********************/
    586  1.1   briggs /************************************************************************/
    587  1.1   briggs /************************************************************************/
    588  1.1   briggs static u_int64_t
    589  1.1   briggs pci_allocate_range(struct extent *ex, u_int64_t amt, int align)
    590  1.1   briggs {
    591  1.1   briggs 	int	r;
    592  1.1   briggs 	u_long	addr;
    593  1.1   briggs 
    594  1.1   briggs 	r = extent_alloc(ex, amt, align, 0, EX_NOWAIT, &addr);
    595  1.1   briggs 	if (r) {
    596  1.1   briggs 		addr = (u_long) -1;
    597  1.4   simonb 		printf("extent_alloc(%p, %llu, %d) returned %d\n",
    598  1.4   simonb 		    ex, amt, align, r);
    599  1.4   simonb 		extent_print(ex);
    600  1.1   briggs 	}
    601  1.1   briggs 	return (pcireg_t) addr;
    602  1.1   briggs }
    603  1.1   briggs 
    604  1.1   briggs static int
    605  1.1   briggs setup_iowins(pciconf_bus_t *pb)
    606  1.1   briggs {
    607  1.1   briggs 	pciconf_win_t	*pi;
    608  1.1   briggs 	pciconf_dev_t	*pd;
    609  1.1   briggs 
    610  1.1   briggs 	for (pi=pb->pciiowin; pi < &pb->pciiowin[pb->niowin] ; pi++) {
    611  1.1   briggs 		if (pi->size == 0)
    612  1.1   briggs 			continue;
    613  1.1   briggs 
    614  1.1   briggs 		pd = pi->dev;
    615  1.1   briggs 		pi->address = pci_allocate_range(pb->ioext, pi->size,
    616  1.1   briggs 		    pi->align);
    617  1.1   briggs 		if (pi->address == -1) {
    618  1.1   briggs 			print_tag(pd->pc, pd->tag);
    619  1.1   briggs 			printf("Failed to allocate PCI I/O space (%llu req)\n",
    620  1.1   briggs 			   pi->size);
    621  1.1   briggs 			return -1;
    622  1.1   briggs 		}
    623  1.2   briggs 		if (!pb->io_32bit && pi->address > 0xFFFF) {
    624  1.2   briggs 			pi->address = 0;
    625  1.2   briggs 			pd->enable = 0;
    626  1.2   briggs 		}
    627  1.1   briggs 		if (pd->ppb && pi->reg == 0) {
    628  1.1   briggs 			pd->ppb->ioext = extent_create("pciconf", pi->address,
    629  1.1   briggs 			    pi->address + pi->size, M_DEVBUF, NULL, 0,
    630  1.1   briggs 			    EX_NOWAIT);
    631  1.1   briggs 			if (pd->ppb->ioext == NULL) {
    632  1.1   briggs 				print_tag(pd->pc, pd->tag);
    633  1.1   briggs 				printf("Failed to alloc I/O ext. for bus %d\n",
    634  1.1   briggs 				    pd->ppb->busno);
    635  1.1   briggs 				return -1;
    636  1.1   briggs 			}
    637  1.1   briggs 			continue;
    638  1.1   briggs 		}
    639  1.1   briggs 		if (pci_conf_debug) {
    640  1.1   briggs 			print_tag(pd->pc, pd->tag);
    641  1.1   briggs 			printf("Putting %llu I/O bytes @ %#llx (reg %x)\n",
    642  1.1   briggs 			    pi->size, pi->address, pi->reg);
    643  1.1   briggs 		}
    644  1.1   briggs 		pci_conf_write(pd->pc, pd->tag, pi->reg,
    645  1.1   briggs 		    PCI_MAPREG_IO_ADDR(pi->address) | PCI_MAPREG_TYPE_IO);
    646  1.1   briggs 	}
    647  1.1   briggs 	return 0;
    648  1.1   briggs }
    649  1.1   briggs 
    650  1.1   briggs static int
    651  1.1   briggs setup_memwins(pciconf_bus_t *pb)
    652  1.1   briggs {
    653  1.1   briggs 	pciconf_win_t	*pm;
    654  1.1   briggs 	pciconf_dev_t	*pd;
    655  1.1   briggs 	pcireg_t	base;
    656  1.1   briggs 	struct extent	*ex;
    657  1.1   briggs 
    658  1.1   briggs 	for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) {
    659  1.1   briggs 		if (pm->size == 0)
    660  1.1   briggs 			continue;
    661  1.1   briggs 
    662  1.1   briggs 		pd = pm->dev;
    663  1.1   briggs 		ex = (pm->prefetch) ? pb->pmemext : pb->memext;
    664  1.1   briggs 		pm->address = pci_allocate_range(ex, pm->size, pm->align);
    665  1.1   briggs 		if (pm->address == -1) {
    666  1.1   briggs 			print_tag(pd->pc, pd->tag);
    667  1.1   briggs 			printf(
    668  1.1   briggs 			   "Failed to allocate PCI memory space (%llu req)\n",
    669  1.1   briggs 			   pm->size);
    670  1.1   briggs 			return -1;
    671  1.1   briggs 		}
    672  1.1   briggs 		if (pd->ppb && pm->reg == 0) {
    673  1.1   briggs 			ex = extent_create("pciconf", pm->address,
    674  1.1   briggs 			    pm->address + pm->size, M_DEVBUF, NULL, 0,
    675  1.1   briggs 			    EX_NOWAIT);
    676  1.1   briggs 			if (ex == NULL) {
    677  1.1   briggs 				print_tag(pd->pc, pd->tag);
    678  1.1   briggs 				printf("Failed to alloc MEM ext. for bus %d\n",
    679  1.1   briggs 				    pd->ppb->busno);
    680  1.1   briggs 				return -1;
    681  1.1   briggs 			}
    682  1.1   briggs 			if (pm->prefetch) {
    683  1.1   briggs 				pd->ppb->pmemext = ex;
    684  1.1   briggs 			} else {
    685  1.1   briggs 				pd->ppb->memext = ex;
    686  1.1   briggs 			}
    687  1.1   briggs 			continue;
    688  1.1   briggs 		}
    689  1.2   briggs 		if (pm->prefetch && !pb->pmem_64bit &&
    690  1.2   briggs 		    pm->address > 0xFFFFFFFFULL) {
    691  1.2   briggs 			pm->address = 0;
    692  1.2   briggs 			pd->enable = 0;
    693  1.2   briggs 		}
    694  1.1   briggs 		if (pm->reg != PCI_MAPREG_ROM) {
    695  1.1   briggs 			if (pci_conf_debug) {
    696  1.1   briggs 				print_tag(pd->pc, pd->tag);
    697  1.1   briggs 				printf(
    698  1.1   briggs 				    "Putting %llu MEM bytes @ %#llx (reg %x)\n",
    699  1.1   briggs 				     pm->size, pm->address, pm->reg);
    700  1.1   briggs 			}
    701  1.1   briggs 			base = pci_conf_read(pd->pc, pd->tag, pm->reg);
    702  1.1   briggs 			base = PCI_MAPREG_MEM_ADDR(pm->address) |
    703  1.1   briggs 			    PCI_MAPREG_MEM_TYPE(base);
    704  1.1   briggs 			pci_conf_write(pd->pc, pd->tag, pm->reg, base);
    705  1.1   briggs 			if (PCI_MAPREG_MEM_TYPE(base) ==
    706  1.1   briggs 			    PCI_MAPREG_MEM_TYPE_64BIT) {
    707  1.1   briggs 				base = (pcireg_t)
    708  1.1   briggs 				    (PCI_MAPREG_MEM64_ADDR(pm->address) >> 32);
    709  1.1   briggs 				pci_conf_write(pd->pc, pd->tag, pm->reg + 4,
    710  1.1   briggs 				    base);
    711  1.1   briggs 			}
    712  1.1   briggs 		}
    713  1.1   briggs 	}
    714  1.1   briggs 	for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) {
    715  1.1   briggs 		if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) {
    716  1.1   briggs 			pd = pm->dev;
    717  1.1   briggs 			if (pci_conf_debug) {
    718  1.1   briggs 				print_tag(pd->pc, pd->tag);
    719  1.1   briggs 				printf(
    720  1.1   briggs 				    "Putting %llu ROM bytes @ %#llx (reg %x)\n",
    721  1.1   briggs 				    pm->size, pm->address, pm->reg);
    722  1.1   briggs 			}
    723  1.1   briggs 			base = ((pcireg_t) pm->address) | PCI_MAPREG_TYPE_ROM;
    724  1.1   briggs 			pci_conf_write(pd->pc, pd->tag, pm->reg, base);
    725  1.1   briggs 		}
    726  1.1   briggs 	}
    727  1.1   briggs 	return 0;
    728  1.1   briggs }
    729  1.1   briggs 
    730  1.1   briggs /*
    731  1.1   briggs  * Configure I/O, memory, and prefetcable memory spaces, then make
    732  1.1   briggs  * a call to configure_bus().
    733  1.1   briggs  */
    734  1.1   briggs static int
    735  1.1   briggs configure_bridge(pciconf_dev_t *pd)
    736  1.1   briggs {
    737  1.1   briggs 	unsigned long	io_base, io_limit, mem_base, mem_limit;
    738  1.1   briggs 	pciconf_bus_t	*pb;
    739  1.1   briggs 	pcireg_t	io, iohigh, mem, cmd;
    740  1.1   briggs 	int		rv;
    741  1.1   briggs 
    742  1.1   briggs 	pb = pd->ppb;
    743  1.1   briggs 	/* Configure I/O base & limit*/
    744  1.1   briggs 	if (pb->ioext) {
    745  1.1   briggs 		io_base = pb->ioext->ex_start;
    746  1.1   briggs 		io_limit = pb->ioext->ex_end;
    747  1.2   briggs 	} else {
    748  1.2   briggs 		io_base  = 0x1000;	/* 4K */
    749  1.2   briggs 		io_limit = 0x0000;
    750  1.1   briggs 	}
    751  1.2   briggs 	if (pb->io_32bit) {
    752  1.2   briggs 		iohigh =
    753  1.2   briggs 		    ((io_base >> 16) << PCI_BRIDGE_IOHIGH_BASE_SHIFT) |
    754  1.2   briggs 		    ((io_limit >> 16) << PCI_BRIDGE_IOHIGH_LIMIT_SHIFT);
    755  1.2   briggs 	} else {
    756  1.2   briggs 		if (io_limit > 0xFFFF) {
    757  1.2   briggs 			printf("Bus %d bridge does not support 32-bit I/O.  ",
    758  1.2   briggs 			    pb->busno);
    759  1.2   briggs 			printf("Disabling I/O accesses\n");
    760  1.2   briggs 			io_base  = 0x1000;	/* 4K */
    761  1.2   briggs 			io_limit = 0x0000;
    762  1.2   briggs 		}
    763  1.2   briggs 		iohigh = 0;
    764  1.2   briggs 	}
    765  1.2   briggs 	io &= (PCI_BRIDGE_STATIO_STATUS_MASK <<
    766  1.2   briggs 	    PCI_BRIDGE_STATIO_STATUS_SHIFT);
    767  1.2   briggs 	io |= (((io_base >> 8) & PCI_BRIDGE_STATIO_IOBASE_MASK)
    768  1.2   briggs 	    << PCI_BRIDGE_STATIO_IOBASE_SHIFT);
    769  1.2   briggs 	io |= (((io_limit >> 8) & PCI_BRIDGE_STATIO_IOLIMIT_MASK)
    770  1.2   briggs 	    << PCI_BRIDGE_STATIO_IOLIMIT_SHIFT);
    771  1.2   briggs 	pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io);
    772  1.2   briggs 	pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh);
    773  1.1   briggs 
    774  1.1   briggs 	/* Configure mem base & limit */
    775  1.1   briggs 	if (pb->memext) {
    776  1.1   briggs 		mem_base = pb->memext->ex_start;
    777  1.1   briggs 		mem_limit = pb->memext->ex_end;
    778  1.2   briggs 	} else {
    779  1.2   briggs 		mem_base  = 0x100000;	/* 1M */
    780  1.2   briggs 		mem_limit = 0x000000;
    781  1.1   briggs 	}
    782  1.2   briggs 	if (mem_limit > 0xFFFFFFFFULL) {
    783  1.2   briggs 		printf("Bus %d bridge MEM range out of range.  ", pb->busno);
    784  1.2   briggs 		printf("Disabling MEM accesses\n");
    785  1.2   briggs 		mem_base  = 0x100000;	/* 1M */
    786  1.2   briggs 		mem_limit = 0x000000;
    787  1.2   briggs 	}
    788  1.2   briggs 	mem = (((mem_base >> 20) & PCI_BRIDGE_MEMORY_BASE_MASK)
    789  1.2   briggs 	    << PCI_BRIDGE_MEMORY_BASE_SHIFT);
    790  1.2   briggs 	mem |= (((mem_limit >> 20) & PCI_BRIDGE_MEMORY_LIMIT_MASK)
    791  1.2   briggs 	    << PCI_BRIDGE_MEMORY_LIMIT_SHIFT);
    792  1.2   briggs 	pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem);
    793  1.1   briggs 
    794  1.1   briggs 	/* Configure prefetchable mem base & limit */
    795  1.1   briggs 	if (pb->pmemext) {
    796  1.1   briggs 		mem_base = pb->pmemext->ex_start;
    797  1.1   briggs 		mem_limit = pb->pmemext->ex_end;
    798  1.2   briggs 	} else {
    799  1.2   briggs 		mem_base  = 0x100000;	/* 1M */
    800  1.2   briggs 		mem_limit = 0x000000;
    801  1.1   briggs 	}
    802  1.2   briggs 	mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG);
    803  1.2   briggs 	if (!PCI_BRIDGE_PREFETCHMEM_64BITS(mem) && mem_limit > 0xFFFFFFFFULL) {
    804  1.2   briggs 		printf("Bus %d bridge does not support 64-bit PMEM.  ",
    805  1.2   briggs 		    pb->busno);
    806  1.2   briggs 		printf("Disabling prefetchable-MEM accesses\n");
    807  1.2   briggs 		mem_base  = 0x100000;	/* 1M */
    808  1.2   briggs 		mem_limit = 0x000000;
    809  1.2   briggs 	}
    810  1.2   briggs 	mem = (((mem_base >> 20) & PCI_BRIDGE_PREFETCHMEM_BASE_MASK)
    811  1.2   briggs 	    << PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT);
    812  1.2   briggs 	mem |= (((mem_limit >> 20) & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK)
    813  1.2   briggs 	    << PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT);
    814  1.2   briggs 	pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem);
    815  1.2   briggs 	/*
    816  1.2   briggs 	 * XXX -- 64-bit systems need a lot more than just this...
    817  1.2   briggs 	 */
    818  1.2   briggs 	if (sizeof(u_long) > 4) {
    819  1.2   briggs 		mem_base  = (int64_t) mem_base  >> 32;
    820  1.2   briggs 		mem_limit = (int64_t) mem_limit >> 32;
    821  1.2   briggs 	}
    822  1.2   briggs 	pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHBASE32_REG,
    823  1.2   briggs 	    mem_base & 0xffffffff);
    824  1.2   briggs 	pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHLIMIT32_REG,
    825  1.2   briggs 	    mem_limit & 0xffffffff);
    826  1.1   briggs 
    827  1.1   briggs 	rv = configure_bus(pb);
    828  1.1   briggs 
    829  1.1   briggs 	if (pb->ioext)
    830  1.1   briggs 		extent_destroy(pb->ioext);
    831  1.1   briggs 	if (pb->memext)
    832  1.1   briggs 		extent_destroy(pb->memext);
    833  1.1   briggs 	if (pb->pmemext)
    834  1.1   briggs 		extent_destroy(pb->pmemext);
    835  1.1   briggs 	if (rv == 0) {
    836  1.1   briggs 		cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG);
    837  1.1   briggs 		cmd &= PCI_BRIDGE_CONTROL_MASK;
    838  1.1   briggs 		cmd |= (PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR)
    839  1.1   briggs 		    << PCI_BRIDGE_CONTROL_SHIFT;
    840  1.1   briggs 		if (pb->fast_b2b) {
    841  1.1   briggs 			cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B
    842  1.1   briggs 			    << PCI_BRIDGE_CONTROL_SHIFT;
    843  1.1   briggs 		}
    844  1.1   briggs 		pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd);
    845  1.1   briggs 		cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG);
    846  1.1   briggs 		cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE;
    847  1.1   briggs 		pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd);
    848  1.1   briggs 	}
    849  1.1   briggs 
    850  1.1   briggs 	return rv;
    851  1.1   briggs }
    852  1.1   briggs 
    853  1.1   briggs /*
    854  1.1   briggs  * Calculate latency values, allocate I/O and MEM segments, then set them
    855  1.1   briggs  * up.  If a PCI-PCI bridge is found, configure the bridge separately,
    856  1.1   briggs  * which will cause a recursive call back here.
    857  1.1   briggs  */
    858  1.1   briggs static int
    859  1.1   briggs configure_bus(pciconf_bus_t *pb)
    860  1.1   briggs {
    861  1.1   briggs 	pciconf_dev_t	*pd;
    862  1.1   briggs 	int		def_ltim, max_ltim, band;
    863  1.1   briggs 
    864  1.1   briggs 				/* MIN_GNT assumes a clock rate of 33MHz */
    865  1.1   briggs 	max_ltim = pb->max_mingnt * 33 / 4;	/* cvt to cycle count */
    866  1.1   briggs 	band = 40000000;			/* 0.25us cycles/sec */
    867  1.1   briggs 	if (band < pb->bandwidth_used) {
    868  1.1   briggs 		printf("PCI bus %d: Warning: Total bandwidth exceeded!?\n",
    869  1.1   briggs 		    pb->busno);
    870  1.1   briggs 		def_ltim = -1;
    871  1.1   briggs 	} else {
    872  1.1   briggs 		def_ltim = (band - pb->bandwidth_used) / pb->ndevs;
    873  1.1   briggs 		if (def_ltim > pb->min_maxlat)
    874  1.1   briggs 			def_ltim = pb->min_maxlat;
    875  1.1   briggs 		def_ltim = def_ltim * 33 / 4;
    876  1.1   briggs 	}
    877  1.1   briggs 	def_ltim = (def_ltim + 7) & ~7;
    878  1.1   briggs 	max_ltim = (max_ltim + 7) & ~7;
    879  1.1   briggs 
    880  1.1   briggs 	pb->def_ltim = MIN( def_ltim, 255 );
    881  1.1   briggs 	pb->max_ltim = MIN( MAX(max_ltim, def_ltim ), 255 );
    882  1.1   briggs 
    883  1.1   briggs 	/*
    884  1.1   briggs 	 * Now we have what we need to initialize the devices.
    885  1.1   briggs 	 * It would probably be better if we could allocate all of these
    886  1.1   briggs 	 * for all busses at once, but "not right now".  First, get a list
    887  1.1   briggs 	 * of free memory ranges from the m.d. system.
    888  1.1   briggs 	 */
    889  1.1   briggs 	if (setup_iowins(pb) || setup_memwins(pb)) {
    890  1.1   briggs 		printf("PCI bus configuration failed: ");
    891  1.1   briggs 		printf("unable to assign all I/O and memory ranges.");
    892  1.1   briggs 		return -1;
    893  1.1   briggs 	}
    894  1.1   briggs 
    895  1.1   briggs 	/*
    896  1.1   briggs 	 * Configure the latency for the devices, and enable them.
    897  1.1   briggs 	 */
    898  1.1   briggs 	for (pd=pb->device ; pd < &pb->device[pb->ndevs] ; pd++) {
    899  1.1   briggs 		pcireg_t cmd, class, misc;
    900  1.1   briggs 		int	ltim;
    901  1.1   briggs 
    902  1.1   briggs 		if (pci_conf_debug) {
    903  1.1   briggs 			print_tag(pd->pc, pd->tag);
    904  1.1   briggs 			printf("Configuring device.\n");
    905  1.1   briggs 		}
    906  1.1   briggs 		class = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG);
    907  1.1   briggs 		misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG);
    908  1.1   briggs 		cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG);
    909  1.1   briggs 		cmd |= PCI_COMMAND_MASTER_ENABLE
    910  1.1   briggs 		    | PCI_COMMAND_SERR_ENABLE
    911  1.1   briggs 		    | PCI_COMMAND_PARITY_ENABLE;
    912  1.1   briggs 		if (pb->fast_b2b)
    913  1.1   briggs 			cmd |= PCI_COMMAND_BACKTOBACK_ENABLE;
    914  1.1   briggs 		if (PCI_CLASS(class) != PCI_CLASS_BRIDGE ||
    915  1.1   briggs 		    PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_PCI) {
    916  1.1   briggs 			cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE;
    917  1.1   briggs 			ltim = pd->min_gnt * 33 / 4;
    918  1.1   briggs 			ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim);
    919  1.1   briggs 		} else {
    920  1.1   briggs 			ltim = MIN (pb->def_ltim, pb->max_ltim);
    921  1.1   briggs 		}
    922  1.2   briggs 		if (!pd->enable) {
    923  1.2   briggs 			print_tag(pd->pc, pd->tag);
    924  1.2   briggs 			printf("Disabled due to lack of resources.\n");
    925  1.2   briggs 			cmd &= ~(PCI_COMMAND_MASTER_ENABLE |
    926  1.2   briggs 			    PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE);
    927  1.2   briggs 		}
    928  1.1   briggs 		pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd);
    929  1.1   briggs 
    930  1.1   briggs 		misc = (misc & ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT))
    931  1.1   briggs 		    | ((ltim & 0xff) << PCI_LATTIMER_SHIFT);
    932  1.1   briggs 		pci_conf_write(pd->pc, pd->tag, PCI_BHLC_REG, misc);
    933  1.1   briggs 
    934  1.1   briggs 		if (pd->ppb) {
    935  1.1   briggs 			if (configure_bridge(pd) < 0)
    936  1.1   briggs 				return -1;
    937  1.1   briggs 			continue;
    938  1.1   briggs 		}
    939  1.1   briggs 	}
    940  1.1   briggs 
    941  1.1   briggs 	if (pci_conf_debug) {
    942  1.1   briggs 		printf("PCI bus %d configured\n", pb->busno);
    943  1.1   briggs 	}
    944  1.1   briggs 
    945  1.1   briggs 	return 0;
    946  1.1   briggs }
    947  1.1   briggs 
    948  1.1   briggs /*
    949  1.1   briggs  * Let's configure the PCI bus.
    950  1.1   briggs  * This consists of basically scanning for all existing devices,
    951  1.1   briggs  * identifying their needs, and then making another pass over them
    952  1.1   briggs  * to set:
    953  1.1   briggs  *	1. I/O addresses
    954  1.1   briggs  *	2. Memory addresses (Prefetchable and not)
    955  1.1   briggs  *	3. PCI command register
    956  1.1   briggs  *	4. The latency part of the PCI BHLC (BIST (Built-In Self Test),
    957  1.1   briggs  *	    Header type, Latency timer, Cache line size) register
    958  1.1   briggs  *
    959  1.1   briggs  * The command register is set to enable fast back-to-back transactions
    960  1.1   briggs  * if the host bridge says it can handle it.  We also configure
    961  1.1   briggs  * Master Enable, SERR enable, parity enable, and (if this is not a
    962  1.1   briggs  * PCI-PCI bridge) the I/O and Memory spaces.  Apparently some devices
    963  1.1   briggs  * will not report some I/O space.
    964  1.1   briggs  *
    965  1.1   briggs  * The latency is computed to be a "fair share" of the bus bandwidth.
    966  1.1   briggs  * The bus bandwidth variable is initialized to the number of PCI cycles
    967  1.1   briggs  * in one second.  The number of cycles taken for one transaction by each
    968  1.1   briggs  * device (MAX_LAT + MIN_GNT) is then subtracted from the bandwidth.
    969  1.1   briggs  * Care is taken to ensure that the latency timer won't be set such that
    970  1.1   briggs  * it would exceed the critical time for any device.
    971  1.1   briggs  *
    972  1.1   briggs  * This is complicated somewhat due to the presence of bridges.  PCI-PCI
    973  1.1   briggs  * bridges are probed and configured recursively.
    974  1.1   briggs  */
    975  1.1   briggs int
    976  1.1   briggs pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext,
    977  1.1   briggs     struct extent *memext, struct extent *pmemext)
    978  1.1   briggs {
    979  1.1   briggs 	pciconf_bus_t	*pb;
    980  1.1   briggs 	int		rv;
    981  1.1   briggs 
    982  1.1   briggs 	pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT);
    983  1.1   briggs 	pb->busno = 0;
    984  1.1   briggs 	pb->busno_spacing = PCI_BUSNO_SPACING;
    985  1.1   briggs 	pb->next_busno = pb->busno + 1;
    986  1.1   briggs 	pb->last_busno = 255;
    987  1.1   briggs 	pb->parent_bus = NULL;
    988  1.1   briggs 	pb->swiz = 0;
    989  1.2   briggs 	pb->io_32bit = 1;
    990  1.2   briggs 	pb->pmem_64bit = 0;
    991  1.1   briggs 	pb->ioext = ioext;
    992  1.1   briggs 	pb->memext = memext;
    993  1.1   briggs 	if (pmemext == NULL) {
    994  1.1   briggs 		pb->pmemext = memext;
    995  1.1   briggs 	} else {
    996  1.1   briggs 		pb->pmemext = pmemext;
    997  1.1   briggs 	}
    998  1.1   briggs 	pb->pc = pc;
    999  1.1   briggs 	pb->io_total = pb->mem_total = pb->pmem_total = 0;
   1000  1.1   briggs 
   1001  1.1   briggs 	rv = probe_bus(pb);
   1002  1.1   briggs 	if (rv == 0) {
   1003  1.1   briggs 		rv = configure_bus(pb);
   1004  1.1   briggs 	}
   1005  1.1   briggs 
   1006  1.1   briggs 	/*
   1007  1.1   briggs 	 * All done!
   1008  1.1   briggs 	 */
   1009  1.1   briggs 	free(pb, M_DEVBUF);
   1010  1.1   briggs 	return rv;
   1011  1.1   briggs }
   1012