pciconf.c revision 1.1
1 /* $NetBSD: pciconf.c,v 1.1 2001/02/09 14:33:15 briggs Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Derived in part from code from PMON/2000 (http://pmon.groupbsd.org/). 39 */ 40 41 #include "opt_pci.h" 42 43 #include <sys/param.h> 44 #include <sys/extent.h> 45 #include <sys/queue.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pciconf.h> 51 #include <dev/pci/pcidevs.h> 52 53 #ifdef PCI_CONFIGURATION_DEBUG 54 int pci_conf_debug = 0; 55 #endif 56 57 #if !defined(MIN) 58 #define MIN(a,b) (((a)<(b))?(a):(b)) 59 #define MAX(a,b) (((a)>(b))?(a):(b)) 60 #endif 61 62 /* per-bus constants. */ 63 #define MAX_CONF_DEV 8 /* Arbitrary */ 64 #define MAX_CONF_MEM (3 * MAX_CONF_DEV) /* Avg. 3 per device -- Arb. */ 65 #define MAX_CONF_IO (1 * MAX_CONF_DEV) /* Avg. 1 per device -- Arb. */ 66 67 #define PCI_BUSNO_SPACING (1 << 5) 68 69 struct _s_pciconf_bus_t; /* Forward declaration */ 70 71 typedef struct _s_pciconf_dev_t { 72 int ipin; 73 int iline; 74 int min_gnt; 75 int max_lat; 76 pcitag_t tag; 77 pci_chipset_tag_t pc; 78 struct _s_pciconf_bus_t *ppb; /* I am really a bridge */ 79 } pciconf_dev_t; 80 81 typedef struct _s_pciconf_win_t { 82 pciconf_dev_t *dev; 83 int reg; /* 0 for busses */ 84 int align; 85 int prefetch; 86 u_int64_t size; 87 u_int64_t address; 88 } pciconf_win_t; 89 90 typedef struct _s_pciconf_bus_t { 91 int busno; 92 int next_busno; 93 int last_busno; 94 int busno_spacing; 95 int max_mingnt; 96 int min_maxlat; 97 int prefetch; 98 int fast_b2b; 99 int freq_66; 100 int def_ltim; 101 int max_ltim; 102 int bandwidth_used; 103 int swiz; 104 105 int ndevs; 106 pciconf_dev_t device[MAX_CONF_DEV]; 107 108 /* These should be sorted in order of decreasing size */ 109 int nmemwin; 110 pciconf_win_t pcimemwin[MAX_CONF_MEM]; 111 int niowin; 112 pciconf_win_t pciiowin[MAX_CONF_IO]; 113 114 bus_size_t io_total; 115 bus_size_t mem_total; 116 bus_size_t pmem_total; 117 118 struct extent *ioext; 119 struct extent *memext; 120 struct extent *pmemext; 121 122 pci_chipset_tag_t pc; 123 struct _s_pciconf_bus_t *parent_bus; 124 } pciconf_bus_t; 125 126 static int probe_bus(pciconf_bus_t *); 127 static void alloc_busno(pciconf_bus_t *, pciconf_bus_t *); 128 static int pci_do_device_query(pciconf_bus_t *, pcitag_t, int, int); 129 static int setup_iowins(pciconf_bus_t *); 130 static int setup_memwins(pciconf_bus_t *); 131 static int configure_bridge(pciconf_dev_t *); 132 static int configure_bus(pciconf_bus_t *); 133 static u_int64_t pci_allocate_range(struct extent *, u_int64_t, int); 134 static pciconf_win_t *get_io_desc(pciconf_bus_t *, bus_size_t); 135 static pciconf_win_t *get_mem_desc(pciconf_bus_t *, bus_size_t); 136 static pciconf_bus_t *query_bus(pciconf_bus_t *, pciconf_dev_t *, int); 137 138 #ifdef PCI_CONFIGURATION_DEBUG 139 static void print_tag(pci_chipset_tag_t, pcitag_t); 140 141 static void 142 print_tag(pci_chipset_tag_t pc, pcitag_t tag) 143 { 144 int bus, dev, func; 145 146 pci_decompose_tag(pc, tag, &bus, &dev, &func); 147 printf("PCI: bus %d, device %d, function %d: ", bus, dev, func); 148 } 149 #endif 150 151 /************************************************************************/ 152 /************************************************************************/ 153 /*********************** Bus probing routines ***********************/ 154 /************************************************************************/ 155 /************************************************************************/ 156 static pciconf_win_t * 157 get_io_desc(pciconf_bus_t *pb, bus_size_t size) 158 { 159 int i, n; 160 161 n = pb->niowin; 162 for (i=n; i > 0 && size > pb->pciiowin[i-1].size; i--) 163 pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */ 164 return &pb->pciiowin[i]; 165 } 166 167 static pciconf_win_t * 168 get_mem_desc(pciconf_bus_t *pb, bus_size_t size) 169 { 170 int i, n; 171 172 n = pb->nmemwin; 173 for (i=n; i > 0 && size > pb->pcimemwin[i-1].size; i--) 174 pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */ 175 return &pb->pcimemwin[i]; 176 } 177 178 /* 179 * Set up bus common stuff, then loop over devices & functions. 180 * If we find something, call pci_do_device_query()). 181 */ 182 static int 183 probe_bus(pciconf_bus_t *pb) 184 { 185 int device, maxdevs; 186 187 maxdevs = pci_bus_maxdevs(pb->pc, pb->busno); 188 pb->ndevs = 0; 189 pb->niowin = 0; 190 pb->nmemwin = 0; 191 pb->freq_66 = 1; 192 pb->fast_b2b = 1; 193 pb->prefetch = 1; 194 pb->max_mingnt = 0; /* we are looking for the maximum */ 195 pb->min_maxlat = 0x100; /* we are looking for the minimum */ 196 pb->bandwidth_used = 0; 197 for (device=0; device < maxdevs; device++) { 198 pcitag_t tag; 199 pcireg_t id, bhlcr; 200 int function, nfunction; 201 202 tag = pci_make_tag(pb->pc, pb->busno, device, 0); 203 #ifdef PCI_CONFIGURATION_DEBUG 204 if (pci_conf_debug) { 205 print_tag(pb->pc, tag); 206 printf("probing.\n"); 207 } 208 #endif 209 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 210 211 /* Invalid vendor ID value? */ 212 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 213 continue; 214 215 bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 216 nfunction = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 217 for (function = 0 ; function < nfunction ; function++) { 218 tag = pci_make_tag(pb->pc, pb->busno, device, function); 219 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 220 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 221 continue; 222 if (pb->ndevs+1 < MAX_CONF_DEV) { 223 #ifdef PCI_CONFIGURATION_DEBUG 224 if (pci_conf_debug) { 225 print_tag(pb->pc, tag); 226 printf("Found dev--really probing.\n"); 227 } 228 #endif 229 if (pci_do_device_query(pb, tag, device, 230 function)) 231 return -1; 232 pb->ndevs++; 233 } 234 } 235 } 236 return 0; 237 } 238 239 static void 240 alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb) 241 { 242 pb->busno = parent->next_busno; 243 if (parent->next_busno + parent->busno_spacing > parent->last_busno) 244 panic("Too many PCI busses on bus %d", parent->busno); 245 parent->next_busno = parent->next_busno + parent->busno_spacing; 246 pb->next_busno = pb->busno+1; 247 pb->busno_spacing = parent->busno_spacing >> 1; 248 if (!pb->busno_spacing) 249 panic("PCI busses nested too deep."); 250 pb->last_busno = parent->next_busno - 1; 251 } 252 253 static pciconf_bus_t * 254 query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev) 255 { 256 pciconf_bus_t *pb; 257 pcireg_t busreg; 258 pciconf_win_t *pi, *pm; 259 260 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 261 if (!pb) 262 panic("Unable to allocate memory for PCI configuration."); 263 264 pb->parent_bus = parent; 265 alloc_busno(parent, pb); 266 #ifdef PCI_CONFIGURATION_DEBUG 267 if (pci_conf_debug) 268 printf("PCI bus bridge covers busses %d-%d\n", 269 pb->busno, pb->last_busno); 270 #endif 271 272 busreg = parent->busno << PCI_BRIDGE_BUS_PRIMARY_SHIFT; 273 busreg |= pb->busno << PCI_BRIDGE_BUS_SECONDARY_SHIFT; 274 busreg |= pb->last_busno << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 275 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_BUS_REG, busreg); 276 277 pb->swiz = parent->swiz + dev; 278 279 pb->ioext = NULL; 280 pb->memext = NULL; 281 pb->pmemext = NULL; 282 pb->pc = parent->pc; 283 pb->io_total = pb->mem_total = pb->pmem_total = 0; 284 285 if (probe_bus(pb)) { 286 printf("Failed to probe bus %d\n", pb->busno); 287 goto err; 288 } 289 290 if (pb->io_total > 0) { 291 if (parent->niowin >= MAX_CONF_IO) { 292 printf("pciconf: too many I/O windows"); 293 goto err; 294 } 295 pb->io_total |= 0xfff; /* Round up */ 296 pi = get_io_desc(parent, pb->io_total); 297 pi->dev = pd; 298 pi->reg = 0; 299 pi->size = pb->io_total; 300 pi->align = 0x1000; /* 4K alignment */ 301 pi->prefetch = 0; 302 parent->niowin++; 303 parent->io_total += pb->io_total; 304 } 305 306 if (pb->mem_total > 0) { 307 if (parent->nmemwin >= MAX_CONF_MEM) { 308 printf("pciconf: too many MEM windows"); 309 goto err; 310 } 311 pb->mem_total |= 0xfffff; /* Round up */ 312 pm = get_mem_desc(parent, pb->mem_total); 313 pm->dev = pd; 314 pm->reg = 0; 315 pm->size = pb->mem_total; 316 pm->align = 0x100000; /* 1M alignment */ 317 pm->prefetch = 0; 318 parent->nmemwin++; 319 parent->mem_total += pb->mem_total; 320 } 321 322 if (pb->pmem_total > 0) { 323 if (parent->nmemwin >= MAX_CONF_MEM) { 324 printf("pciconf: too many MEM windows"); 325 goto err; 326 } 327 pb->pmem_total |= 0xfffff; /* Round up */ 328 pm = get_mem_desc(parent, pb->pmem_total); 329 pm->dev = pd; 330 pm->reg = 0; 331 pm->size = pb->pmem_total; 332 pm->align = 0x100000; /* 1M alignment */ 333 pm->prefetch = 1; 334 parent->nmemwin++; 335 parent->pmem_total += pb->pmem_total; 336 } 337 338 return pb; 339 err: 340 free(pb, M_DEVBUF); 341 return NULL; 342 } 343 344 static int 345 pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func) 346 { 347 pciconf_dev_t *pd; 348 pciconf_win_t *pi, *pm; 349 pcireg_t class, cmd, icr, bar, mask, bar64, mask64; 350 u_int64_t size; 351 int br, width; 352 353 pd = &pb->device[pb->ndevs]; 354 pd->pc = pb->pc; 355 pd->tag = tag; 356 pd->ppb = NULL; 357 358 class = pci_conf_read(pb->pc, tag, PCI_CLASS_REG); 359 360 cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG); 361 362 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE) { 363 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 364 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 365 pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd); 366 } 367 368 if ((cmd & PCI_STATUS_BACKTOBACK_SUPPORT) == 0) 369 pb->fast_b2b = 0; 370 371 if ((cmd & PCI_STATUS_66MHZ_SUPPORT) == 0) 372 pb->freq_66 = 0; 373 374 if ( (PCI_CLASS(class) == PCI_CLASS_BRIDGE) 375 && (PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_PCI)) { 376 pd->ppb = query_bus(pb, pd, dev); 377 if (pd->ppb == NULL) 378 return -1; 379 return 0; 380 } 381 382 icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG); 383 pd->ipin = PCI_INTERRUPT_PIN(icr); 384 pd->iline = PCI_INTERRUPT_LINE(icr); 385 pd->min_gnt = PCI_MIN_GNT(icr); 386 pd->max_lat = PCI_MAX_LAT(icr); 387 if (pd->iline || pd->ipin) { 388 pci_conf_interrupt(pb->pc, pb->busno, dev, func, pb->swiz, 389 &pd->iline); 390 icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 391 icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT); 392 pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr); 393 } 394 395 if (pd->min_gnt != 0 || pd->max_lat != 0) { 396 if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt) 397 pb->max_mingnt = pd->min_gnt; 398 399 if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat) 400 pb->min_maxlat = pd->max_lat; 401 402 pb->bandwidth_used += pd->min_gnt * 4000000 / 403 (pd->min_gnt + pd->max_lat); 404 } 405 406 width = 4; 407 for (br = PCI_MAPREG_START; br < PCI_MAPREG_END; br += width) { 408 if (PCI_CLASS(class) == PCI_CLASS_MASS_STORAGE && 409 PCI_SUBCLASS(class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 410 break; 411 } 412 bar = pci_conf_read(pb->pc, tag, br); 413 pci_conf_write(pb->pc, tag, br, 0xfffffffe); 414 mask = pci_conf_read(pb->pc, tag, br); 415 pci_conf_write(pb->pc, tag, br, bar); 416 width = 4; 417 418 if (mask == 0 || mask == 0xffffffff) 419 break; 420 421 if (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO) { 422 if (pb->niowin >= MAX_CONF_IO) { 423 printf("pciconf: too many I/O windows"); 424 return -1; 425 } 426 427 mask |= 0xffff0000; 428 size = PCI_MAPREG_IO_SIZE(mask); 429 430 pi = get_io_desc(pb, size); 431 pi->dev = pd; 432 pi->reg = br; 433 pi->size = (u_int64_t) size; 434 pi->align = 4; 435 pi->prefetch = 0; 436 #ifdef PCI_CONFIGURATION_DEBUG 437 if (pci_conf_debug) { 438 print_tag(pb->pc, tag); 439 printf("Register %d, I/O size %llu\n", 440 br, pi->size); 441 } 442 #endif 443 pb->niowin++; 444 pb->io_total += size; 445 } else { 446 switch (PCI_MAPREG_MEM_TYPE(mask)) { 447 case PCI_MAPREG_MEM_TYPE_32BIT: 448 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 449 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 450 break; 451 case PCI_MAPREG_MEM_TYPE_64BIT: 452 bar64 = pci_conf_read(pb->pc, tag, br + 4); 453 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); 454 mask64 = pci_conf_read(pb->pc, tag, br + 4); 455 pci_conf_write(pb->pc, tag, br + 4, bar64); 456 size = (u_int64_t) PCI_MAPREG_MEM64_SIZE( 457 (((u_int64_t) mask64) << 32) | mask); 458 width = 8; 459 continue; 460 default: 461 print_tag(pb->pc, tag); 462 printf("reserved mapping type 0x%x\n", 463 PCI_MAPREG_MEM_TYPE(mask)); 464 continue; 465 } 466 467 if (pb->nmemwin >= MAX_CONF_MEM) { 468 printf("pciconf: too many memory windows"); 469 return -1; 470 } 471 472 473 pm = get_mem_desc(pb, size); 474 pm->dev = pd; 475 pm->reg = br; 476 pm->size = size; 477 pm->align = 4; 478 pm->prefetch = PCI_MAPREG_MEM_PREFETCHABLE(mask); 479 #ifdef PCI_CONFIGURATION_DEBUG 480 if (pci_conf_debug) { 481 print_tag(pb->pc, tag); 482 printf("Register %d, memory size %llu\n", 483 br, pm->size); 484 } 485 #endif 486 pb->nmemwin++; 487 if (pm->prefetch) { 488 pb->pmem_total += size; 489 } else { 490 pb->mem_total += size; 491 } 492 } 493 } 494 495 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 496 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 497 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 498 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, bar); 499 500 if (mask != 0 && mask != 0xffffffff) { 501 if (pb->nmemwin >= MAX_CONF_MEM) { 502 printf("pciconf: too many memory windows"); 503 return -1; 504 } 505 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 506 507 pm = get_mem_desc(pb, size); 508 pm->dev = pd; 509 pm->reg = PCI_MAPREG_ROM; 510 pm->size = size; 511 pm->align = 4; 512 pm->prefetch = 1; 513 #ifdef PCI_CONFIGURATION_DEBUG 514 if (pci_conf_debug) { 515 print_tag(pb->pc, tag); 516 printf("Expansion ROM memory size %llu\n", pm->size); 517 } 518 #endif 519 pb->nmemwin++; 520 pb->pmem_total += size; 521 } 522 523 return 0; 524 } 525 526 /************************************************************************/ 527 /************************************************************************/ 528 /******************** Bus configuration routines ********************/ 529 /************************************************************************/ 530 /************************************************************************/ 531 static u_int64_t 532 pci_allocate_range(struct extent *ex, u_int64_t amt, int align) 533 { 534 int r; 535 u_long addr; 536 537 r = extent_alloc(ex, amt, align, 0, EX_NOWAIT, &addr); 538 if (r) { 539 addr = (u_long) -1; 540 printf("extent_alloc() returned %d\n", r); 541 } 542 return (pcireg_t) addr; 543 } 544 545 static int 546 setup_iowins(pciconf_bus_t *pb) 547 { 548 pciconf_win_t *pi; 549 pciconf_dev_t *pd; 550 551 for (pi=pb->pciiowin; pi < &pb->pciiowin[pb->niowin] ; pi++) { 552 if (pi->size == 0) 553 continue; 554 555 pd = pi->dev; 556 pi->address = pci_allocate_range(pb->ioext, pi->size, 557 pi->align); 558 if (pi->address == -1) { 559 print_tag(pd->pc, pd->tag); 560 printf("Failed to allocate PCI I/O space (%llu req)\n", 561 pi->size); 562 return -1; 563 } 564 if (pd->ppb && pi->reg == 0) { 565 pd->ppb->ioext = extent_create("pciconf", pi->address, 566 pi->address + pi->size, M_DEVBUF, NULL, 0, 567 EX_NOWAIT); 568 if (pd->ppb->ioext == NULL) { 569 print_tag(pd->pc, pd->tag); 570 printf("Failed to alloc I/O ext. for bus %d\n", 571 pd->ppb->busno); 572 return -1; 573 } 574 continue; 575 } 576 #ifdef PCI_CONFIGURATION_DEBUG 577 if (pci_conf_debug) { 578 print_tag(pd->pc, pd->tag); 579 printf("Putting %llu I/O bytes @ %#llx (reg %x)\n", 580 pi->size, pi->address, pi->reg); 581 } 582 #endif 583 pci_conf_write(pd->pc, pd->tag, pi->reg, 584 PCI_MAPREG_IO_ADDR(pi->address) | PCI_MAPREG_TYPE_IO); 585 } 586 return 0; 587 } 588 589 static int 590 setup_memwins(pciconf_bus_t *pb) 591 { 592 pciconf_win_t *pm; 593 pciconf_dev_t *pd; 594 pcireg_t base; 595 struct extent *ex; 596 597 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 598 if (pm->size == 0) 599 continue; 600 601 pd = pm->dev; 602 ex = (pm->prefetch) ? pb->pmemext : pb->memext; 603 pm->address = pci_allocate_range(ex, pm->size, pm->align); 604 if (pm->address == -1) { 605 print_tag(pd->pc, pd->tag); 606 printf( 607 "Failed to allocate PCI memory space (%llu req)\n", 608 pm->size); 609 return -1; 610 } 611 if (pd->ppb && pm->reg == 0) { 612 ex = extent_create("pciconf", pm->address, 613 pm->address + pm->size, M_DEVBUF, NULL, 0, 614 EX_NOWAIT); 615 if (ex == NULL) { 616 print_tag(pd->pc, pd->tag); 617 printf("Failed to alloc MEM ext. for bus %d\n", 618 pd->ppb->busno); 619 return -1; 620 } 621 if (pm->prefetch) { 622 pd->ppb->pmemext = ex; 623 } else { 624 pd->ppb->memext = ex; 625 } 626 continue; 627 } 628 if (pm->reg != PCI_MAPREG_ROM) { 629 #ifdef PCI_CONFIGURATION_DEBUG 630 if (pci_conf_debug) { 631 print_tag(pd->pc, pd->tag); 632 printf( 633 "Putting %llu MEM bytes @ %#llx (reg %x)\n", 634 pm->size, pm->address, pm->reg); 635 } 636 #endif 637 base = pci_conf_read(pd->pc, pd->tag, pm->reg); 638 base = PCI_MAPREG_MEM_ADDR(pm->address) | 639 PCI_MAPREG_MEM_TYPE(base); 640 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 641 if (PCI_MAPREG_MEM_TYPE(base) == 642 PCI_MAPREG_MEM_TYPE_64BIT) { 643 base = (pcireg_t) 644 (PCI_MAPREG_MEM64_ADDR(pm->address) >> 32); 645 pci_conf_write(pd->pc, pd->tag, pm->reg + 4, 646 base); 647 } 648 } 649 } 650 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 651 if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) { 652 pd = pm->dev; 653 #ifdef PCI_CONFIGURATION_DEBUG 654 if (pci_conf_debug) { 655 print_tag(pd->pc, pd->tag); 656 printf( 657 "Putting %llu ROM bytes @ %#llx (reg %x)\n", 658 pm->size, pm->address, pm->reg); 659 } 660 #endif 661 base = ((pcireg_t) pm->address) | PCI_MAPREG_TYPE_ROM; 662 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 663 } 664 } 665 return 0; 666 } 667 668 /* 669 * Configure I/O, memory, and prefetcable memory spaces, then make 670 * a call to configure_bus(). 671 */ 672 static int 673 configure_bridge(pciconf_dev_t *pd) 674 { 675 unsigned long io_base, io_limit, mem_base, mem_limit; 676 pciconf_bus_t *pb; 677 pcireg_t io, iohigh, mem, cmd; 678 int rv; 679 680 pb = pd->ppb; 681 /* Configure I/O base & limit*/ 682 if (pb->ioext) { 683 io_base = pb->ioext->ex_start; 684 io_limit = pb->ioext->ex_end; 685 io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG); 686 if (PCI_BRIDGE_IO_32BITS(io)) { 687 iohigh = 688 ((io_base >> 16) << PCI_BRIDGE_IOHIGH_BASE_SHIFT) | 689 ((io_limit >> 16) << PCI_BRIDGE_IOHIGH_LIMIT_SHIFT); 690 } else { 691 iohigh = 0; 692 } 693 io &= (PCI_BRIDGE_STATIO_STATUS_MASK << 694 PCI_BRIDGE_STATIO_STATUS_SHIFT); 695 io |= (((io_base >> 8) & PCI_BRIDGE_STATIO_IOBASE_MASK) 696 << PCI_BRIDGE_STATIO_IOBASE_SHIFT); 697 io |= (((io_limit >> 8) & PCI_BRIDGE_STATIO_IOLIMIT_MASK) 698 << PCI_BRIDGE_STATIO_IOLIMIT_SHIFT); 699 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io); 700 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh); 701 } 702 703 /* Configure mem base & limit */ 704 if (pb->memext) { 705 mem_base = pb->memext->ex_start; 706 mem_limit = pb->memext->ex_end; 707 mem = (((mem_base >> 20) & PCI_BRIDGE_MEMORY_BASE_MASK) 708 << PCI_BRIDGE_MEMORY_BASE_SHIFT); 709 mem |= (((mem_limit >> 20) & PCI_BRIDGE_MEMORY_LIMIT_MASK) 710 << PCI_BRIDGE_MEMORY_LIMIT_SHIFT); 711 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem); 712 } 713 714 /* Configure prefetchable mem base & limit */ 715 if (pb->pmemext) { 716 mem_base = pb->pmemext->ex_start; 717 mem_limit = pb->pmemext->ex_end; 718 mem = (((mem_base >> 20) & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) 719 << PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT); 720 mem |= (((mem_limit >> 20) & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) 721 << PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT); 722 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, 723 mem); 724 /* 725 * XXX -- 64-bit systems need a lot more than just this... 726 */ 727 if (sizeof(u_long) > 4) { 728 mem_base = (int64_t) mem_base >> 32; 729 mem_limit = (int64_t) mem_limit >> 32; 730 } 731 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHBASE32_REG, 732 mem_base & 0xffffffff); 733 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHLIMIT32_REG, 734 mem_limit & 0xffffffff); 735 } 736 737 rv = configure_bus(pb); 738 739 if (pb->ioext) 740 extent_destroy(pb->ioext); 741 if (pb->memext) 742 extent_destroy(pb->memext); 743 if (pb->pmemext) 744 extent_destroy(pb->pmemext); 745 if (rv == 0) { 746 cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG); 747 cmd &= PCI_BRIDGE_CONTROL_MASK; 748 cmd |= (PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR) 749 << PCI_BRIDGE_CONTROL_SHIFT; 750 if (pb->fast_b2b) { 751 cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B 752 << PCI_BRIDGE_CONTROL_SHIFT; 753 } 754 pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd); 755 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 756 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 757 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 758 } 759 760 return rv; 761 } 762 763 /* 764 * Calculate latency values, allocate I/O and MEM segments, then set them 765 * up. If a PCI-PCI bridge is found, configure the bridge separately, 766 * which will cause a recursive call back here. 767 */ 768 static int 769 configure_bus(pciconf_bus_t *pb) 770 { 771 pciconf_dev_t *pd; 772 int def_ltim, max_ltim, band; 773 774 /* MIN_GNT assumes a clock rate of 33MHz */ 775 max_ltim = pb->max_mingnt * 33 / 4; /* cvt to cycle count */ 776 band = 40000000; /* 0.25us cycles/sec */ 777 if (band < pb->bandwidth_used) { 778 printf("PCI bus %d: Warning: Total bandwidth exceeded!?\n", 779 pb->busno); 780 def_ltim = -1; 781 } else { 782 def_ltim = (band - pb->bandwidth_used) / pb->ndevs; 783 if (def_ltim > pb->min_maxlat) 784 def_ltim = pb->min_maxlat; 785 def_ltim = def_ltim * 33 / 4; 786 } 787 def_ltim = (def_ltim + 7) & ~7; 788 max_ltim = (max_ltim + 7) & ~7; 789 790 pb->def_ltim = MIN( def_ltim, 255 ); 791 pb->max_ltim = MIN( MAX(max_ltim, def_ltim ), 255 ); 792 793 /* 794 * Now we have what we need to initialize the devices. 795 * It would probably be better if we could allocate all of these 796 * for all busses at once, but "not right now". First, get a list 797 * of free memory ranges from the m.d. system. 798 */ 799 if (setup_iowins(pb) || setup_memwins(pb)) { 800 printf("PCI bus configuration failed: "); 801 printf("unable to assign all I/O and memory ranges."); 802 return -1; 803 } 804 805 /* 806 * Configure the latency for the devices, and enable them. 807 */ 808 for (pd=pb->device ; pd < &pb->device[pb->ndevs] ; pd++) { 809 pcireg_t cmd, class, misc; 810 int ltim; 811 812 #ifdef PCI_CONFIGURATION_DEBUG 813 if (pci_conf_debug) { 814 print_tag(pd->pc, pd->tag); 815 printf("Configuring device.\n"); 816 } 817 #endif 818 class = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG); 819 misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG); 820 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 821 cmd |= PCI_COMMAND_MASTER_ENABLE 822 | PCI_COMMAND_SERR_ENABLE 823 | PCI_COMMAND_PARITY_ENABLE; 824 if (pb->fast_b2b) 825 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE; 826 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 827 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_PCI) { 828 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 829 ltim = pd->min_gnt * 33 / 4; 830 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim); 831 } else { 832 ltim = MIN (pb->def_ltim, pb->max_ltim); 833 } 834 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 835 836 misc = (misc & ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT)) 837 | ((ltim & 0xff) << PCI_LATTIMER_SHIFT); 838 pci_conf_write(pd->pc, pd->tag, PCI_BHLC_REG, misc); 839 840 if (pd->ppb) { 841 if (configure_bridge(pd) < 0) 842 return -1; 843 continue; 844 } 845 } 846 847 #ifdef PCI_CONFIGURATION_DEBUG 848 if (pci_conf_debug) { 849 printf("PCI bus %d configured\n", pb->busno); 850 } 851 #endif 852 853 return 0; 854 } 855 856 /* 857 * Let's configure the PCI bus. 858 * This consists of basically scanning for all existing devices, 859 * identifying their needs, and then making another pass over them 860 * to set: 861 * 1. I/O addresses 862 * 2. Memory addresses (Prefetchable and not) 863 * 3. PCI command register 864 * 4. The latency part of the PCI BHLC (BIST (Built-In Self Test), 865 * Header type, Latency timer, Cache line size) register 866 * 867 * The command register is set to enable fast back-to-back transactions 868 * if the host bridge says it can handle it. We also configure 869 * Master Enable, SERR enable, parity enable, and (if this is not a 870 * PCI-PCI bridge) the I/O and Memory spaces. Apparently some devices 871 * will not report some I/O space. 872 * 873 * The latency is computed to be a "fair share" of the bus bandwidth. 874 * The bus bandwidth variable is initialized to the number of PCI cycles 875 * in one second. The number of cycles taken for one transaction by each 876 * device (MAX_LAT + MIN_GNT) is then subtracted from the bandwidth. 877 * Care is taken to ensure that the latency timer won't be set such that 878 * it would exceed the critical time for any device. 879 * 880 * This is complicated somewhat due to the presence of bridges. PCI-PCI 881 * bridges are probed and configured recursively. 882 */ 883 int 884 pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext, 885 struct extent *memext, struct extent *pmemext) 886 { 887 pciconf_bus_t *pb; 888 int rv; 889 890 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 891 pb->busno = 0; 892 pb->busno_spacing = PCI_BUSNO_SPACING; 893 pb->next_busno = pb->busno + 1; 894 pb->last_busno = 255; 895 pb->parent_bus = NULL; 896 pb->swiz = 0; 897 pb->ioext = ioext; 898 pb->memext = memext; 899 if (pmemext == NULL) { 900 pb->pmemext = memext; 901 } else { 902 pb->pmemext = pmemext; 903 } 904 pb->pc = pc; 905 pb->io_total = pb->mem_total = pb->pmem_total = 0; 906 907 rv = probe_bus(pb); 908 if (rv == 0) { 909 rv = configure_bus(pb); 910 } 911 912 /* 913 * All done! 914 */ 915 free(pb, M_DEVBUF); 916 return rv; 917 } 918
Indexes created Wed Sep 24 05:09:52 GMT 2025