pciconf.c revision 1.10
1 /* $NetBSD: pciconf.c,v 1.10 2001/09/03 03:46:26 thorpej Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Derived in part from code from PMON/2000 (http://pmon.groupbsd.org/). 39 */ 40 41 /* 42 * To do: 43 * - Perform all data structure allocation dynamically, don't have 44 * statically-sized arrays ("oops, you lose because you have too 45 * many slots filled!") 46 * - Do this in 2 passes, with an MD hook to control the behavior: 47 * (1) Configure the bus (possibly including expansion 48 * ROMs. 49 * (2) Another pass to disable expansion ROMs if they're 50 * mapped (since you're not supposed to leave them 51 * mapped when you're not using them). 52 * This would facilitate MD code executing the expansion ROMs 53 * if necessary (possibly with an x86 emulator) to configure 54 * devices (e.g. VGA cards). 55 * - Deal with "anything can be hot-plugged" -- i.e., carry configuration 56 * information around & be able to reconfigure on the fly 57 * - Deal with segments (See IA64 System Abstraction Layer) 58 * - Deal with subtractive bridges (& non-spec positive/subtractive decode) 59 * - Deal with ISA/VGA/VGA palette snooping 60 * - Deal with device capabilities on bridges 61 * - Worry about changing a bridge to/from transparency 62 * From thorpej (05/25/01) 63 * - Try to handle devices that are already configured (perhaps using that 64 * as a hint to where we put other devices) 65 */ 66 67 #include "opt_pci.h" 68 69 #include <sys/param.h> 70 #include <sys/extent.h> 71 #include <sys/queue.h> 72 #include <sys/systm.h> 73 #include <sys/malloc.h> 74 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/pciconf.h> 77 #include <dev/pci/pcidevs.h> 78 79 int pci_conf_debug = 0; 80 81 #if !defined(MIN) 82 #define MIN(a,b) (((a)<(b))?(a):(b)) 83 #define MAX(a,b) (((a)>(b))?(a):(b)) 84 #endif 85 86 /* per-bus constants. */ 87 #define MAX_CONF_DEV 32 /* Arbitrary */ 88 #define MAX_CONF_MEM (3 * MAX_CONF_DEV) /* Avg. 3 per device -- Arb. */ 89 #define MAX_CONF_IO (3 * MAX_CONF_DEV) /* Avg. 1 per device -- Arb. */ 90 91 #define PCI_BUSNO_SPACING (1 << 5) 92 93 struct _s_pciconf_bus_t; /* Forward declaration */ 94 95 typedef struct _s_pciconf_dev_t { 96 int ipin; 97 int iline; 98 int min_gnt; 99 int max_lat; 100 int enable; 101 pcitag_t tag; 102 pci_chipset_tag_t pc; 103 struct _s_pciconf_bus_t *ppb; /* I am really a bridge */ 104 } pciconf_dev_t; 105 106 typedef struct _s_pciconf_win_t { 107 pciconf_dev_t *dev; 108 int reg; /* 0 for busses */ 109 int align; 110 int prefetch; 111 u_int64_t size; 112 u_int64_t address; 113 } pciconf_win_t; 114 115 typedef struct _s_pciconf_bus_t { 116 int busno; 117 int next_busno; 118 int last_busno; 119 int busno_spacing; 120 int max_mingnt; 121 int min_maxlat; 122 int prefetch; 123 int fast_b2b; 124 int freq_66; 125 int def_ltim; 126 int max_ltim; 127 int bandwidth_used; 128 int swiz; 129 int io_32bit; 130 int pmem_64bit; 131 132 int ndevs; 133 pciconf_dev_t device[MAX_CONF_DEV]; 134 135 /* These should be sorted in order of decreasing size */ 136 int nmemwin; 137 pciconf_win_t pcimemwin[MAX_CONF_MEM]; 138 int niowin; 139 pciconf_win_t pciiowin[MAX_CONF_IO]; 140 141 bus_size_t io_total; 142 bus_size_t mem_total; 143 bus_size_t pmem_total; 144 145 struct extent *ioext; 146 struct extent *memext; 147 struct extent *pmemext; 148 149 pci_chipset_tag_t pc; 150 struct _s_pciconf_bus_t *parent_bus; 151 } pciconf_bus_t; 152 153 static int probe_bus(pciconf_bus_t *); 154 static void alloc_busno(pciconf_bus_t *, pciconf_bus_t *); 155 static int pci_do_device_query(pciconf_bus_t *, pcitag_t, int, int, int); 156 static int setup_iowins(pciconf_bus_t *); 157 static int setup_memwins(pciconf_bus_t *); 158 static int configure_bridge(pciconf_dev_t *); 159 static int configure_bus(pciconf_bus_t *); 160 static u_int64_t pci_allocate_range(struct extent *, u_int64_t, int); 161 static pciconf_win_t *get_io_desc(pciconf_bus_t *, bus_size_t); 162 static pciconf_win_t *get_mem_desc(pciconf_bus_t *, bus_size_t); 163 static pciconf_bus_t *query_bus(pciconf_bus_t *, pciconf_dev_t *, int); 164 165 static void print_tag(pci_chipset_tag_t, pcitag_t); 166 167 static void 168 print_tag(pci_chipset_tag_t pc, pcitag_t tag) 169 { 170 int bus, dev, func; 171 172 pci_decompose_tag(pc, tag, &bus, &dev, &func); 173 printf("PCI: bus %d, device %d, function %d: ", bus, dev, func); 174 } 175 176 /************************************************************************/ 177 /************************************************************************/ 178 /*********************** Bus probing routines ***********************/ 179 /************************************************************************/ 180 /************************************************************************/ 181 static pciconf_win_t * 182 get_io_desc(pciconf_bus_t *pb, bus_size_t size) 183 { 184 int i, n; 185 186 n = pb->niowin; 187 for (i=n; i > 0 && size > pb->pciiowin[i-1].size; i--) 188 pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */ 189 return &pb->pciiowin[i]; 190 } 191 192 static pciconf_win_t * 193 get_mem_desc(pciconf_bus_t *pb, bus_size_t size) 194 { 195 int i, n; 196 197 n = pb->nmemwin; 198 for (i=n; i > 0 && size > pb->pcimemwin[i-1].size; i--) 199 pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */ 200 return &pb->pcimemwin[i]; 201 } 202 203 /* 204 * Set up bus common stuff, then loop over devices & functions. 205 * If we find something, call pci_do_device_query()). 206 */ 207 static int 208 probe_bus(pciconf_bus_t *pb) 209 { 210 int device, maxdevs; 211 #ifdef __PCI_BUS_DEVORDER 212 char devs[32]; 213 int i; 214 #endif 215 216 maxdevs = pci_bus_maxdevs(pb->pc, pb->busno); 217 pb->ndevs = 0; 218 pb->niowin = 0; 219 pb->nmemwin = 0; 220 pb->freq_66 = 1; 221 pb->fast_b2b = 1; 222 pb->prefetch = 1; 223 pb->max_mingnt = 0; /* we are looking for the maximum */ 224 pb->min_maxlat = 0x100; /* we are looking for the minimum */ 225 pb->bandwidth_used = 0; 226 227 #ifdef __PCI_BUS_DEVORDER 228 pci_bus_devorder(pb->pc, pb->busno, devs); 229 for (i=0; (device=devs[i]) < 32 && device >= 0; i++) { 230 #else 231 for (device=0; device < maxdevs; device++) { 232 #endif 233 pcitag_t tag; 234 pcireg_t id, bhlcr; 235 int function, nfunction; 236 int confmode; 237 238 tag = pci_make_tag(pb->pc, pb->busno, device, 0); 239 if (pci_conf_debug) { 240 print_tag(pb->pc, tag); 241 } 242 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 243 244 if (pci_conf_debug) { 245 printf("id=%x: Vendor=%x, Product=%x\n", 246 id, PCI_VENDOR(id),PCI_PRODUCT(id)); 247 } 248 /* Invalid vendor ID value? */ 249 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 250 continue; 251 252 bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 253 nfunction = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 254 for (function = 0 ; function < nfunction ; function++) { 255 tag = pci_make_tag(pb->pc, pb->busno, device, function); 256 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 257 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 258 continue; 259 if (pb->ndevs+1 < MAX_CONF_DEV) { 260 if (pci_conf_debug) { 261 print_tag(pb->pc, tag); 262 printf("Found dev 0x%04x 0x%04x -- " 263 "really probing.\n", 264 PCI_VENDOR(id), PCI_PRODUCT(id)); 265 } 266 #ifdef __HAVE_PCI_CONF_HOOK 267 confmode = pci_conf_hook(pb->pc, pb->busno, 268 device, function, id); 269 if (confmode == 0) 270 continue; 271 #else 272 /* 273 * Don't enable expansion ROMS -- some cards 274 * share address decoders between the EXPROM 275 * and PCI memory space, and enabling the ROM 276 * when not needed will cause all sorts of 277 * lossage. 278 */ 279 confmode = PCI_CONF_ALL & ~PCI_CONF_MAP_ROM; 280 #endif 281 if (pci_do_device_query(pb, tag, device, 282 function, confmode)) 283 return -1; 284 pb->ndevs++; 285 } 286 } 287 } 288 return 0; 289 } 290 291 static void 292 alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb) 293 { 294 pb->busno = parent->next_busno; 295 if (parent->next_busno + parent->busno_spacing > parent->last_busno) 296 panic("Too many PCI busses on bus %d", parent->busno); 297 parent->next_busno = parent->next_busno + parent->busno_spacing; 298 pb->next_busno = pb->busno+1; 299 pb->busno_spacing = parent->busno_spacing >> 1; 300 if (!pb->busno_spacing) 301 panic("PCI busses nested too deep."); 302 pb->last_busno = parent->next_busno - 1; 303 } 304 305 static pciconf_bus_t * 306 query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev) 307 { 308 pciconf_bus_t *pb; 309 pcireg_t busreg, io, pmem; 310 pciconf_win_t *pi, *pm; 311 312 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 313 if (!pb) 314 panic("Unable to allocate memory for PCI configuration."); 315 316 pb->parent_bus = parent; 317 alloc_busno(parent, pb); 318 if (pci_conf_debug) 319 printf("PCI bus bridge covers busses %d-%d\n", 320 pb->busno, pb->last_busno); 321 322 busreg = parent->busno << PCI_BRIDGE_BUS_PRIMARY_SHIFT; 323 busreg |= pb->busno << PCI_BRIDGE_BUS_SECONDARY_SHIFT; 324 busreg |= pb->last_busno << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 325 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_BUS_REG, busreg); 326 327 pb->swiz = parent->swiz + dev; 328 329 pb->ioext = NULL; 330 pb->memext = NULL; 331 pb->pmemext = NULL; 332 pb->pc = parent->pc; 333 pb->io_total = pb->mem_total = pb->pmem_total = 0; 334 335 pb->io_32bit = 0; 336 if (parent->io_32bit) { 337 io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG); 338 if (PCI_BRIDGE_IO_32BITS(io)) { 339 pb->io_32bit = 1; 340 } 341 } 342 343 pb->pmem_64bit = 0; 344 if (parent->pmem_64bit) { 345 pmem = pci_conf_read(pb->pc, pd->tag, 346 PCI_BRIDGE_PREFETCHMEM_REG); 347 if (PCI_BRIDGE_PREFETCHMEM_64BITS(pmem)) { 348 pb->pmem_64bit = 1; 349 } 350 } 351 352 if (probe_bus(pb)) { 353 printf("Failed to probe bus %d\n", pb->busno); 354 goto err; 355 } 356 357 if (pb->io_total > 0) { 358 if (parent->niowin >= MAX_CONF_IO) { 359 printf("pciconf: too many I/O windows\n"); 360 goto err; 361 } 362 pb->io_total |= 0xfff; /* Round up */ 363 pi = get_io_desc(parent, pb->io_total); 364 pi->dev = pd; 365 pi->reg = 0; 366 pi->size = pb->io_total; 367 pi->align = 0x1000; /* 4K alignment */ 368 pi->prefetch = 0; 369 parent->niowin++; 370 parent->io_total += pb->io_total; 371 } 372 373 if (pb->mem_total > 0) { 374 if (parent->nmemwin >= MAX_CONF_MEM) { 375 printf("pciconf: too many MEM windows\n"); 376 goto err; 377 } 378 pb->mem_total |= 0xfffff; /* Round up */ 379 pm = get_mem_desc(parent, pb->mem_total); 380 pm->dev = pd; 381 pm->reg = 0; 382 pm->size = pb->mem_total; 383 pm->align = 0x100000; /* 1M alignment */ 384 pm->prefetch = 0; 385 parent->nmemwin++; 386 parent->mem_total += pb->mem_total; 387 } 388 389 if (pb->pmem_total > 0) { 390 if (parent->nmemwin >= MAX_CONF_MEM) { 391 printf("pciconf: too many MEM windows\n"); 392 goto err; 393 } 394 pb->pmem_total |= 0xfffff; /* Round up */ 395 pm = get_mem_desc(parent, pb->pmem_total); 396 pm->dev = pd; 397 pm->reg = 0; 398 pm->size = pb->pmem_total; 399 pm->align = 0x100000; /* 1M alignment */ 400 pm->prefetch = 1; 401 parent->nmemwin++; 402 parent->pmem_total += pb->pmem_total; 403 } 404 405 return pb; 406 err: 407 free(pb, M_DEVBUF); 408 return NULL; 409 } 410 411 static int 412 pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func, int mode) 413 { 414 pciconf_dev_t *pd; 415 pciconf_win_t *pi, *pm; 416 pcireg_t class, cmd, icr, bar, mask, bar64, mask64; 417 u_int64_t size; 418 int br, width; 419 420 pd = &pb->device[pb->ndevs]; 421 pd->pc = pb->pc; 422 pd->tag = tag; 423 pd->ppb = NULL; 424 pd->enable = mode; 425 426 class = pci_conf_read(pb->pc, tag, PCI_CLASS_REG); 427 428 cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG); 429 430 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE) { 431 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 432 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 433 pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd); 434 } else if (pci_conf_debug) { 435 print_tag(pb->pc, tag); 436 printf("device is a bridge; not clearing enables\n"); 437 } 438 439 if ((cmd & PCI_STATUS_BACKTOBACK_SUPPORT) == 0) 440 pb->fast_b2b = 0; 441 442 if ((cmd & PCI_STATUS_66MHZ_SUPPORT) == 0) 443 pb->freq_66 = 0; 444 445 if ( (PCI_CLASS(class) == PCI_CLASS_BRIDGE) 446 && (PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_PCI)) { 447 pd->ppb = query_bus(pb, pd, dev); 448 if (pd->ppb == NULL) 449 return -1; 450 return 0; 451 } 452 453 icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG); 454 pd->ipin = PCI_INTERRUPT_PIN(icr); 455 pd->iline = PCI_INTERRUPT_LINE(icr); 456 pd->min_gnt = PCI_MIN_GNT(icr); 457 pd->max_lat = PCI_MAX_LAT(icr); 458 if (pd->iline || pd->ipin) { 459 pci_conf_interrupt(pb->pc, pb->busno, dev, pd->ipin, pb->swiz, 460 &pd->iline); 461 icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 462 icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT); 463 pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr); 464 } 465 466 if (pd->min_gnt != 0 || pd->max_lat != 0) { 467 if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt) 468 pb->max_mingnt = pd->min_gnt; 469 470 if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat) 471 pb->min_maxlat = pd->max_lat; 472 473 pb->bandwidth_used += pd->min_gnt * 4000000 / 474 (pd->min_gnt + pd->max_lat); 475 } 476 477 width = 4; 478 for (br = PCI_MAPREG_START; br < PCI_MAPREG_END; br += width) { 479 #if 0 480 /* XXX Should only ignore if IDE not in legacy mode? */ 481 if (PCI_CLASS(class) == PCI_CLASS_MASS_STORAGE && 482 PCI_SUBCLASS(class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 483 break; 484 } 485 #endif 486 bar = pci_conf_read(pb->pc, tag, br); 487 pci_conf_write(pb->pc, tag, br, 0xffffffff); 488 mask = pci_conf_read(pb->pc, tag, br); 489 pci_conf_write(pb->pc, tag, br, bar); 490 width = 4; 491 492 if ( (mode & PCI_CONF_MAP_IO) 493 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO)) { 494 /* 495 * Upper 16 bits must be one. Devices may hardwire 496 * them to zero, though, per PCI 2.2, 6.2.5.1, p 203. 497 */ 498 mask |= 0xffff0000; 499 500 size = PCI_MAPREG_IO_SIZE(mask); 501 if (size == 0) { 502 if (pci_conf_debug) { 503 print_tag(pb->pc, tag); 504 printf("I/O BAR 0x%x is void\n", br); 505 } 506 continue; 507 } 508 509 if (pb->niowin >= MAX_CONF_IO) { 510 printf("pciconf: too many I/O windows\n"); 511 return -1; 512 } 513 514 pi = get_io_desc(pb, size); 515 pi->dev = pd; 516 pi->reg = br; 517 pi->size = (u_int64_t) size; 518 pi->align = 4; 519 pi->prefetch = 0; 520 if (pci_conf_debug) { 521 print_tag(pb->pc, tag); 522 printf("Register 0x%x, I/O size %llu\n", 523 br, pi->size); 524 } 525 pb->niowin++; 526 pb->io_total += size; 527 } else if ((mode & PCI_CONF_MAP_MEM) 528 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_MEM)) { 529 switch (PCI_MAPREG_MEM_TYPE(mask)) { 530 case PCI_MAPREG_MEM_TYPE_32BIT: 531 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 532 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 533 break; 534 case PCI_MAPREG_MEM_TYPE_64BIT: 535 bar64 = pci_conf_read(pb->pc, tag, br + 4); 536 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); 537 mask64 = pci_conf_read(pb->pc, tag, br + 4); 538 pci_conf_write(pb->pc, tag, br + 4, bar64); 539 size = (u_int64_t) PCI_MAPREG_MEM64_SIZE( 540 (((u_int64_t) mask64) << 32) | mask); 541 width = 8; 542 continue; 543 default: 544 print_tag(pb->pc, tag); 545 printf("reserved mapping type 0x%x\n", 546 PCI_MAPREG_MEM_TYPE(mask)); 547 continue; 548 } 549 550 if (size == 0) { 551 if (pci_conf_debug) { 552 print_tag(pb->pc, tag); 553 printf("MEM%d BAR 0x%x is void\n", 554 PCI_MAPREG_MEM_TYPE(mask) == 555 PCI_MAPREG_MEM_TYPE_64BIT ? 556 64 : 32, br); 557 } 558 continue; 559 } 560 561 if (pb->nmemwin >= MAX_CONF_MEM) { 562 printf("pciconf: too many memory windows\n"); 563 return -1; 564 } 565 566 pm = get_mem_desc(pb, size); 567 pm->dev = pd; 568 pm->reg = br; 569 pm->size = size; 570 pm->align = 4; 571 pm->prefetch = PCI_MAPREG_MEM_PREFETCHABLE(mask); 572 if (pci_conf_debug) { 573 print_tag(pb->pc, tag); 574 printf("Register 0x%x, memory size %llu\n", 575 br, pm->size); 576 } 577 pb->nmemwin++; 578 if (pm->prefetch) { 579 pb->pmem_total += size; 580 } else { 581 pb->mem_total += size; 582 } 583 } 584 } 585 586 if (mode & PCI_CONF_MAP_ROM) { 587 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 588 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 589 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 590 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, bar); 591 592 if (mask != 0 && mask != 0xffffffff) { 593 if (pb->nmemwin >= MAX_CONF_MEM) { 594 printf("pciconf: too many memory windows\n"); 595 return -1; 596 } 597 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 598 599 pm = get_mem_desc(pb, size); 600 pm->dev = pd; 601 pm->reg = PCI_MAPREG_ROM; 602 pm->size = size; 603 pm->align = 4; 604 pm->prefetch = 1; 605 if (pci_conf_debug) { 606 print_tag(pb->pc, tag); 607 printf("Expansion ROM memory size %llu\n", pm->size); 608 } 609 pb->nmemwin++; 610 pb->pmem_total += size; 611 } 612 } else { 613 /* Ensure ROM is disabled */ 614 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 615 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 616 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 617 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 618 bar & ~PCI_MAPREG_ROM_ENABLE); 619 } 620 621 return 0; 622 } 623 624 /************************************************************************/ 625 /************************************************************************/ 626 /******************** Bus configuration routines ********************/ 627 /************************************************************************/ 628 /************************************************************************/ 629 static u_int64_t 630 pci_allocate_range(struct extent *ex, u_int64_t amt, int align) 631 { 632 int r; 633 u_long addr; 634 635 r = extent_alloc(ex, amt, align, 0, EX_NOWAIT, &addr); 636 if (r) { 637 addr = (u_long) -1; 638 printf("extent_alloc(%p, %llu, %d) returned %d\n", 639 ex, amt, align, r); 640 extent_print(ex); 641 } 642 return (pcireg_t) addr; 643 } 644 645 static int 646 setup_iowins(pciconf_bus_t *pb) 647 { 648 pciconf_win_t *pi; 649 pciconf_dev_t *pd; 650 651 for (pi=pb->pciiowin; pi < &pb->pciiowin[pb->niowin] ; pi++) { 652 if (pi->size == 0) 653 continue; 654 655 pd = pi->dev; 656 pi->address = pci_allocate_range(pb->ioext, pi->size, 657 pi->align); 658 if (pi->address == -1) { 659 print_tag(pd->pc, pd->tag); 660 printf("Failed to allocate PCI I/O space (%llu req)\n", 661 pi->size); 662 return -1; 663 } 664 if (!pb->io_32bit && pi->address > 0xFFFF) { 665 pi->address = 0; 666 pd->enable = 0; 667 } 668 if (pd->ppb && pi->reg == 0) { 669 pd->ppb->ioext = extent_create("pciconf", pi->address, 670 pi->address + pi->size, M_DEVBUF, NULL, 0, 671 EX_NOWAIT); 672 if (pd->ppb->ioext == NULL) { 673 print_tag(pd->pc, pd->tag); 674 printf("Failed to alloc I/O ext. for bus %d\n", 675 pd->ppb->busno); 676 return -1; 677 } 678 continue; 679 } 680 pd->enable |= PCI_CONF_ENABLE_IO; 681 if (pci_conf_debug) { 682 print_tag(pd->pc, pd->tag); 683 printf("Putting %llu I/O bytes @ %#llx (reg %x)\n", 684 pi->size, pi->address, pi->reg); 685 } 686 pci_conf_write(pd->pc, pd->tag, pi->reg, 687 PCI_MAPREG_IO_ADDR(pi->address) | PCI_MAPREG_TYPE_IO); 688 } 689 return 0; 690 } 691 692 static int 693 setup_memwins(pciconf_bus_t *pb) 694 { 695 pciconf_win_t *pm; 696 pciconf_dev_t *pd; 697 pcireg_t base; 698 struct extent *ex; 699 700 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 701 if (pm->size == 0) 702 continue; 703 704 pd = pm->dev; 705 ex = (pm->prefetch) ? pb->pmemext : pb->memext; 706 pm->address = pci_allocate_range(ex, pm->size, pm->align); 707 if (pm->address == -1) { 708 print_tag(pd->pc, pd->tag); 709 printf( 710 "Failed to allocate PCI memory space (%llu req)\n", 711 pm->size); 712 return -1; 713 } 714 if (pd->ppb && pm->reg == 0) { 715 ex = extent_create("pciconf", pm->address, 716 pm->address + pm->size, M_DEVBUF, NULL, 0, 717 EX_NOWAIT); 718 if (ex == NULL) { 719 print_tag(pd->pc, pd->tag); 720 printf("Failed to alloc MEM ext. for bus %d\n", 721 pd->ppb->busno); 722 return -1; 723 } 724 if (pm->prefetch) { 725 pd->ppb->pmemext = ex; 726 } else { 727 pd->ppb->memext = ex; 728 } 729 continue; 730 } 731 if (pm->prefetch && !pb->pmem_64bit && 732 pm->address > 0xFFFFFFFFULL) { 733 pm->address = 0; 734 pd->enable = 0; 735 } else { 736 pd->enable |= PCI_CONF_ENABLE_MEM; 737 } 738 if (pm->reg != PCI_MAPREG_ROM) { 739 if (pci_conf_debug) { 740 print_tag(pd->pc, pd->tag); 741 printf( 742 "Putting %llu MEM bytes @ %#llx (reg %x)\n", 743 pm->size, pm->address, pm->reg); 744 } 745 base = pci_conf_read(pd->pc, pd->tag, pm->reg); 746 base = PCI_MAPREG_MEM_ADDR(pm->address) | 747 PCI_MAPREG_MEM_TYPE(base); 748 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 749 if (PCI_MAPREG_MEM_TYPE(base) == 750 PCI_MAPREG_MEM_TYPE_64BIT) { 751 base = (pcireg_t) 752 (PCI_MAPREG_MEM64_ADDR(pm->address) >> 32); 753 pci_conf_write(pd->pc, pd->tag, pm->reg + 4, 754 base); 755 } 756 } 757 } 758 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 759 if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) { 760 pd = pm->dev; 761 if (pci_conf_debug) { 762 print_tag(pd->pc, pd->tag); 763 printf( 764 "Putting %llu ROM bytes @ %#llx (reg %x)\n", 765 pm->size, pm->address, pm->reg); 766 } 767 base = (pcireg_t) (pm->address | PCI_MAPREG_ROM_ENABLE); 768 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 769 } 770 } 771 return 0; 772 } 773 774 /* 775 * Configure I/O, memory, and prefetcable memory spaces, then make 776 * a call to configure_bus(). 777 */ 778 static int 779 configure_bridge(pciconf_dev_t *pd) 780 { 781 unsigned long io_base, io_limit, mem_base, mem_limit; 782 pciconf_bus_t *pb; 783 pcireg_t io, iohigh, mem, cmd; 784 int rv; 785 786 pb = pd->ppb; 787 /* Configure I/O base & limit*/ 788 if (pb->ioext) { 789 io_base = pb->ioext->ex_start; 790 io_limit = pb->ioext->ex_end; 791 } else { 792 io_base = 0x1000; /* 4K */ 793 io_limit = 0x0000; 794 } 795 if (pb->io_32bit) { 796 iohigh = 797 ((io_base >> 16) << PCI_BRIDGE_IOHIGH_BASE_SHIFT) | 798 ((io_limit >> 16) << PCI_BRIDGE_IOHIGH_LIMIT_SHIFT); 799 } else { 800 if (io_limit > 0xFFFF) { 801 printf("Bus %d bridge does not support 32-bit I/O. ", 802 pb->busno); 803 printf("Disabling I/O accesses\n"); 804 io_base = 0x1000; /* 4K */ 805 io_limit = 0x0000; 806 } 807 iohigh = 0; 808 } 809 io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG) & 810 (PCI_BRIDGE_STATIO_STATUS_MASK << PCI_BRIDGE_STATIO_STATUS_SHIFT); 811 io |= (((io_base >> 8) & PCI_BRIDGE_STATIO_IOBASE_MASK) 812 << PCI_BRIDGE_STATIO_IOBASE_SHIFT); 813 io |= (((io_limit >> 8) & PCI_BRIDGE_STATIO_IOLIMIT_MASK) 814 << PCI_BRIDGE_STATIO_IOLIMIT_SHIFT); 815 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io); 816 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh); 817 818 /* Configure mem base & limit */ 819 if (pb->memext) { 820 mem_base = pb->memext->ex_start; 821 mem_limit = pb->memext->ex_end; 822 } else { 823 mem_base = 0x100000; /* 1M */ 824 mem_limit = 0x000000; 825 } 826 if (mem_limit > 0xFFFFFFFFULL) { 827 printf("Bus %d bridge MEM range out of range. ", pb->busno); 828 printf("Disabling MEM accesses\n"); 829 mem_base = 0x100000; /* 1M */ 830 mem_limit = 0x000000; 831 } 832 mem = (((mem_base >> 20) & PCI_BRIDGE_MEMORY_BASE_MASK) 833 << PCI_BRIDGE_MEMORY_BASE_SHIFT); 834 mem |= (((mem_limit >> 20) & PCI_BRIDGE_MEMORY_LIMIT_MASK) 835 << PCI_BRIDGE_MEMORY_LIMIT_SHIFT); 836 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem); 837 838 /* Configure prefetchable mem base & limit */ 839 if (pb->pmemext) { 840 mem_base = pb->pmemext->ex_start; 841 mem_limit = pb->pmemext->ex_end; 842 } else { 843 mem_base = 0x100000; /* 1M */ 844 mem_limit = 0x000000; 845 } 846 mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG); 847 if (!PCI_BRIDGE_PREFETCHMEM_64BITS(mem) && mem_limit > 0xFFFFFFFFULL) { 848 printf("Bus %d bridge does not support 64-bit PMEM. ", 849 pb->busno); 850 printf("Disabling prefetchable-MEM accesses\n"); 851 mem_base = 0x100000; /* 1M */ 852 mem_limit = 0x000000; 853 } 854 mem = (((mem_base >> 20) & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) 855 << PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT); 856 mem |= (((mem_limit >> 20) & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) 857 << PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT); 858 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem); 859 /* 860 * XXX -- 64-bit systems need a lot more than just this... 861 */ 862 if (sizeof(u_long) > 4) { 863 mem_base = (int64_t) mem_base >> 32; 864 mem_limit = (int64_t) mem_limit >> 32; 865 } 866 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHBASE32_REG, 867 mem_base & 0xffffffff); 868 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHLIMIT32_REG, 869 mem_limit & 0xffffffff); 870 871 rv = configure_bus(pb); 872 873 if (pb->ioext) 874 extent_destroy(pb->ioext); 875 if (pb->memext) 876 extent_destroy(pb->memext); 877 if (pb->pmemext) 878 extent_destroy(pb->pmemext); 879 if (rv == 0) { 880 cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG); 881 cmd &= PCI_BRIDGE_CONTROL_MASK; 882 cmd |= (PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR) 883 << PCI_BRIDGE_CONTROL_SHIFT; 884 if (pb->fast_b2b) { 885 cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B 886 << PCI_BRIDGE_CONTROL_SHIFT; 887 } 888 pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd); 889 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 890 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 891 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 892 } 893 894 return rv; 895 } 896 897 /* 898 * Calculate latency values, allocate I/O and MEM segments, then set them 899 * up. If a PCI-PCI bridge is found, configure the bridge separately, 900 * which will cause a recursive call back here. 901 */ 902 static int 903 configure_bus(pciconf_bus_t *pb) 904 { 905 pciconf_dev_t *pd; 906 int def_ltim, max_ltim, band, bus_mhz; 907 908 bus_mhz = pb->freq_66 ? 66 : 33; 909 max_ltim = pb->max_mingnt * bus_mhz / 4; /* cvt to cycle count */ 910 band = 40000000; /* 0.25us cycles/sec */ 911 if (band < pb->bandwidth_used) { 912 printf("PCI bus %d: Warning: Total bandwidth exceeded!?\n", 913 pb->busno); 914 def_ltim = -1; 915 } else { 916 def_ltim = (band - pb->bandwidth_used) / pb->ndevs; 917 if (def_ltim > pb->min_maxlat) 918 def_ltim = pb->min_maxlat; 919 def_ltim = def_ltim * bus_mhz / 4; 920 } 921 def_ltim = (def_ltim + 7) & ~7; 922 max_ltim = (max_ltim + 7) & ~7; 923 924 pb->def_ltim = MIN( def_ltim, 255 ); 925 pb->max_ltim = MIN( MAX(max_ltim, def_ltim ), 255 ); 926 927 /* 928 * Now we have what we need to initialize the devices. 929 * It would probably be better if we could allocate all of these 930 * for all busses at once, but "not right now". First, get a list 931 * of free memory ranges from the m.d. system. 932 */ 933 if (setup_iowins(pb) || setup_memwins(pb)) { 934 printf("PCI bus configuration failed: "); 935 printf("unable to assign all I/O and memory ranges."); 936 return -1; 937 } 938 939 /* 940 * Configure the latency for the devices, and enable them. 941 */ 942 for (pd=pb->device ; pd < &pb->device[pb->ndevs] ; pd++) { 943 pcireg_t cmd, class, misc; 944 int ltim; 945 946 if (pci_conf_debug) { 947 print_tag(pd->pc, pd->tag); 948 printf("Configuring device.\n"); 949 } 950 class = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG); 951 misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG); 952 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 953 cmd |= PCI_COMMAND_SERR_ENABLE | PCI_COMMAND_PARITY_ENABLE; 954 if (pb->fast_b2b) 955 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE; 956 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 957 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_PCI) { 958 if (pd->enable & PCI_CONF_ENABLE_IO) 959 cmd |= PCI_COMMAND_IO_ENABLE; 960 if (pd->enable & PCI_CONF_ENABLE_MEM) 961 cmd |= PCI_COMMAND_MEM_ENABLE; 962 if (pd->enable & PCI_CONF_ENABLE_BM) 963 cmd |= PCI_COMMAND_MASTER_ENABLE; 964 ltim = pd->min_gnt * bus_mhz / 4; 965 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim); 966 } else { 967 cmd |= PCI_COMMAND_MASTER_ENABLE; 968 ltim = MIN (pb->def_ltim, pb->max_ltim); 969 } 970 if (!(pd->enable)) { 971 print_tag(pd->pc, pd->tag); 972 printf("Disabled due to lack of resources.\n"); 973 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 974 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 975 } 976 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 977 978 misc = (misc & ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT)) 979 | ((ltim & 0xff) << PCI_LATTIMER_SHIFT); 980 pci_conf_write(pd->pc, pd->tag, PCI_BHLC_REG, misc); 981 982 if (pd->ppb) { 983 if (configure_bridge(pd) < 0) 984 return -1; 985 continue; 986 } 987 } 988 989 if (pci_conf_debug) { 990 printf("PCI bus %d configured\n", pb->busno); 991 } 992 993 return 0; 994 } 995 996 /* 997 * Let's configure the PCI bus. 998 * This consists of basically scanning for all existing devices, 999 * identifying their needs, and then making another pass over them 1000 * to set: 1001 * 1. I/O addresses 1002 * 2. Memory addresses (Prefetchable and not) 1003 * 3. PCI command register 1004 * 4. The latency part of the PCI BHLC (BIST (Built-In Self Test), 1005 * Header type, Latency timer, Cache line size) register 1006 * 1007 * The command register is set to enable fast back-to-back transactions 1008 * if the host bridge says it can handle it. We also configure 1009 * Master Enable, SERR enable, parity enable, and (if this is not a 1010 * PCI-PCI bridge) the I/O and Memory spaces. Apparently some devices 1011 * will not report some I/O space. 1012 * 1013 * The latency is computed to be a "fair share" of the bus bandwidth. 1014 * The bus bandwidth variable is initialized to the number of PCI cycles 1015 * in one second. The number of cycles taken for one transaction by each 1016 * device (MAX_LAT + MIN_GNT) is then subtracted from the bandwidth. 1017 * Care is taken to ensure that the latency timer won't be set such that 1018 * it would exceed the critical time for any device. 1019 * 1020 * This is complicated somewhat due to the presence of bridges. PCI-PCI 1021 * bridges are probed and configured recursively. 1022 */ 1023 int 1024 pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext, 1025 struct extent *memext, struct extent *pmemext) 1026 { 1027 pciconf_bus_t *pb; 1028 int rv; 1029 1030 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 1031 pb->busno = 0; 1032 pb->busno_spacing = PCI_BUSNO_SPACING; 1033 pb->next_busno = pb->busno + 1; 1034 pb->last_busno = 255; 1035 pb->parent_bus = NULL; 1036 pb->swiz = 0; 1037 pb->io_32bit = 1; 1038 pb->pmem_64bit = 0; 1039 pb->ioext = ioext; 1040 pb->memext = memext; 1041 if (pmemext == NULL) { 1042 pb->pmemext = memext; 1043 } else { 1044 pb->pmemext = pmemext; 1045 } 1046 pb->pc = pc; 1047 pb->io_total = pb->mem_total = pb->pmem_total = 0; 1048 1049 rv = probe_bus(pb); 1050 if (rv == 0) { 1051 rv = configure_bus(pb); 1052 } 1053 1054 /* 1055 * All done! 1056 */ 1057 free(pb, M_DEVBUF); 1058 return rv; 1059 } 1060
Indexes created Wed Sep 24 05:09:52 GMT 2025