pciconf.c revision 1.13
1 /* $NetBSD: pciconf.c,v 1.13 2001/11/13 07:48:48 lukem Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Derived in part from code from PMON/2000 (http://pmon.groupbsd.org/). 39 */ 40 41 /* 42 * To do: 43 * - Perform all data structure allocation dynamically, don't have 44 * statically-sized arrays ("oops, you lose because you have too 45 * many slots filled!") 46 * - Do this in 2 passes, with an MD hook to control the behavior: 47 * (1) Configure the bus (possibly including expansion 48 * ROMs. 49 * (2) Another pass to disable expansion ROMs if they're 50 * mapped (since you're not supposed to leave them 51 * mapped when you're not using them). 52 * This would facilitate MD code executing the expansion ROMs 53 * if necessary (possibly with an x86 emulator) to configure 54 * devices (e.g. VGA cards). 55 * - Deal with "anything can be hot-plugged" -- i.e., carry configuration 56 * information around & be able to reconfigure on the fly 57 * - Deal with segments (See IA64 System Abstraction Layer) 58 * - Deal with subtractive bridges (& non-spec positive/subtractive decode) 59 * - Deal with ISA/VGA/VGA palette snooping 60 * - Deal with device capabilities on bridges 61 * - Worry about changing a bridge to/from transparency 62 * From thorpej (05/25/01) 63 * - Try to handle devices that are already configured (perhaps using that 64 * as a hint to where we put other devices) 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: pciconf.c,v 1.13 2001/11/13 07:48:48 lukem Exp $"); 69 70 #include "opt_pci.h" 71 72 #include <sys/param.h> 73 #include <sys/extent.h> 74 #include <sys/queue.h> 75 #include <sys/systm.h> 76 #include <sys/malloc.h> 77 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/pciconf.h> 80 #include <dev/pci/pcidevs.h> 81 82 int pci_conf_debug = 0; 83 84 #if !defined(MIN) 85 #define MIN(a,b) (((a)<(b))?(a):(b)) 86 #define MAX(a,b) (((a)>(b))?(a):(b)) 87 #endif 88 89 /* per-bus constants. */ 90 #define MAX_CONF_DEV 32 /* Arbitrary */ 91 #define MAX_CONF_MEM (3 * MAX_CONF_DEV) /* Avg. 3 per device -- Arb. */ 92 #define MAX_CONF_IO (3 * MAX_CONF_DEV) /* Avg. 1 per device -- Arb. */ 93 94 #define PCI_BUSNO_SPACING (1 << 5) 95 96 struct _s_pciconf_bus_t; /* Forward declaration */ 97 98 typedef struct _s_pciconf_dev_t { 99 int ipin; 100 int iline; 101 int min_gnt; 102 int max_lat; 103 int enable; 104 pcitag_t tag; 105 pci_chipset_tag_t pc; 106 struct _s_pciconf_bus_t *ppb; /* I am really a bridge */ 107 } pciconf_dev_t; 108 109 typedef struct _s_pciconf_win_t { 110 pciconf_dev_t *dev; 111 int reg; /* 0 for busses */ 112 int align; 113 int prefetch; 114 u_int64_t size; 115 u_int64_t address; 116 } pciconf_win_t; 117 118 typedef struct _s_pciconf_bus_t { 119 int busno; 120 int next_busno; 121 int last_busno; 122 int busno_spacing; 123 int max_mingnt; 124 int min_maxlat; 125 int prefetch; 126 int fast_b2b; 127 int freq_66; 128 int def_ltim; 129 int max_ltim; 130 int bandwidth_used; 131 int swiz; 132 int io_32bit; 133 int pmem_64bit; 134 135 int ndevs; 136 pciconf_dev_t device[MAX_CONF_DEV]; 137 138 /* These should be sorted in order of decreasing size */ 139 int nmemwin; 140 pciconf_win_t pcimemwin[MAX_CONF_MEM]; 141 int niowin; 142 pciconf_win_t pciiowin[MAX_CONF_IO]; 143 144 bus_size_t io_total; 145 bus_size_t mem_total; 146 bus_size_t pmem_total; 147 148 struct extent *ioext; 149 struct extent *memext; 150 struct extent *pmemext; 151 152 pci_chipset_tag_t pc; 153 struct _s_pciconf_bus_t *parent_bus; 154 } pciconf_bus_t; 155 156 static int probe_bus(pciconf_bus_t *); 157 static void alloc_busno(pciconf_bus_t *, pciconf_bus_t *); 158 static int pci_do_device_query(pciconf_bus_t *, pcitag_t, int, int, int); 159 static int setup_iowins(pciconf_bus_t *); 160 static int setup_memwins(pciconf_bus_t *); 161 static int configure_bridge(pciconf_dev_t *); 162 static int configure_bus(pciconf_bus_t *); 163 static u_int64_t pci_allocate_range(struct extent *, u_int64_t, int); 164 static pciconf_win_t *get_io_desc(pciconf_bus_t *, bus_size_t); 165 static pciconf_win_t *get_mem_desc(pciconf_bus_t *, bus_size_t); 166 static pciconf_bus_t *query_bus(pciconf_bus_t *, pciconf_dev_t *, int); 167 168 static void print_tag(pci_chipset_tag_t, pcitag_t); 169 170 static void 171 print_tag(pci_chipset_tag_t pc, pcitag_t tag) 172 { 173 int bus, dev, func; 174 175 pci_decompose_tag(pc, tag, &bus, &dev, &func); 176 printf("PCI: bus %d, device %d, function %d: ", bus, dev, func); 177 } 178 179 /************************************************************************/ 180 /************************************************************************/ 181 /*********************** Bus probing routines ***********************/ 182 /************************************************************************/ 183 /************************************************************************/ 184 static pciconf_win_t * 185 get_io_desc(pciconf_bus_t *pb, bus_size_t size) 186 { 187 int i, n; 188 189 n = pb->niowin; 190 for (i=n; i > 0 && size > pb->pciiowin[i-1].size; i--) 191 pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */ 192 return &pb->pciiowin[i]; 193 } 194 195 static pciconf_win_t * 196 get_mem_desc(pciconf_bus_t *pb, bus_size_t size) 197 { 198 int i, n; 199 200 n = pb->nmemwin; 201 for (i=n; i > 0 && size > pb->pcimemwin[i-1].size; i--) 202 pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */ 203 return &pb->pcimemwin[i]; 204 } 205 206 /* 207 * Set up bus common stuff, then loop over devices & functions. 208 * If we find something, call pci_do_device_query()). 209 */ 210 static int 211 probe_bus(pciconf_bus_t *pb) 212 { 213 int device, maxdevs; 214 #ifdef __PCI_BUS_DEVORDER 215 char devs[32]; 216 int i; 217 #endif 218 219 maxdevs = pci_bus_maxdevs(pb->pc, pb->busno); 220 pb->ndevs = 0; 221 pb->niowin = 0; 222 pb->nmemwin = 0; 223 pb->freq_66 = 1; 224 pb->fast_b2b = 1; 225 pb->prefetch = 1; 226 pb->max_mingnt = 0; /* we are looking for the maximum */ 227 pb->min_maxlat = 0x100; /* we are looking for the minimum */ 228 pb->bandwidth_used = 0; 229 230 #ifdef __PCI_BUS_DEVORDER 231 pci_bus_devorder(pb->pc, pb->busno, devs); 232 for (i=0; (device=devs[i]) < 32 && device >= 0; i++) { 233 #else 234 for (device=0; device < maxdevs; device++) { 235 #endif 236 pcitag_t tag; 237 pcireg_t id, bhlcr; 238 int function, nfunction; 239 int confmode; 240 241 tag = pci_make_tag(pb->pc, pb->busno, device, 0); 242 if (pci_conf_debug) { 243 print_tag(pb->pc, tag); 244 } 245 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 246 247 if (pci_conf_debug) { 248 printf("id=%x: Vendor=%x, Product=%x\n", 249 id, PCI_VENDOR(id),PCI_PRODUCT(id)); 250 } 251 /* Invalid vendor ID value? */ 252 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 253 continue; 254 255 bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 256 nfunction = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 257 for (function = 0 ; function < nfunction ; function++) { 258 tag = pci_make_tag(pb->pc, pb->busno, device, function); 259 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 260 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 261 continue; 262 if (pb->ndevs+1 < MAX_CONF_DEV) { 263 if (pci_conf_debug) { 264 print_tag(pb->pc, tag); 265 printf("Found dev 0x%04x 0x%04x -- " 266 "really probing.\n", 267 PCI_VENDOR(id), PCI_PRODUCT(id)); 268 } 269 #ifdef __HAVE_PCI_CONF_HOOK 270 confmode = pci_conf_hook(pb->pc, pb->busno, 271 device, function, id); 272 if (confmode == 0) 273 continue; 274 #else 275 /* 276 * Don't enable expansion ROMS -- some cards 277 * share address decoders between the EXPROM 278 * and PCI memory space, and enabling the ROM 279 * when not needed will cause all sorts of 280 * lossage. 281 */ 282 confmode = PCI_CONF_ALL & ~PCI_CONF_MAP_ROM; 283 #endif 284 if (pci_do_device_query(pb, tag, device, 285 function, confmode)) 286 return -1; 287 pb->ndevs++; 288 } 289 } 290 } 291 return 0; 292 } 293 294 static void 295 alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb) 296 { 297 pb->busno = parent->next_busno; 298 if (parent->next_busno + parent->busno_spacing > parent->last_busno) 299 panic("Too many PCI busses on bus %d", parent->busno); 300 parent->next_busno = parent->next_busno + parent->busno_spacing; 301 pb->next_busno = pb->busno+1; 302 pb->busno_spacing = parent->busno_spacing >> 1; 303 if (!pb->busno_spacing) 304 panic("PCI busses nested too deep."); 305 pb->last_busno = parent->next_busno - 1; 306 } 307 308 static pciconf_bus_t * 309 query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev) 310 { 311 pciconf_bus_t *pb; 312 pcireg_t busreg, io, pmem; 313 pciconf_win_t *pi, *pm; 314 315 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 316 if (!pb) 317 panic("Unable to allocate memory for PCI configuration."); 318 319 pb->parent_bus = parent; 320 alloc_busno(parent, pb); 321 if (pci_conf_debug) 322 printf("PCI bus bridge covers busses %d-%d\n", 323 pb->busno, pb->last_busno); 324 325 busreg = parent->busno << PCI_BRIDGE_BUS_PRIMARY_SHIFT; 326 busreg |= pb->busno << PCI_BRIDGE_BUS_SECONDARY_SHIFT; 327 busreg |= pb->last_busno << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 328 pci_conf_write(parent->pc, pd->tag, PCI_BRIDGE_BUS_REG, busreg); 329 330 pb->swiz = parent->swiz + dev; 331 332 pb->ioext = NULL; 333 pb->memext = NULL; 334 pb->pmemext = NULL; 335 pb->pc = parent->pc; 336 pb->io_total = pb->mem_total = pb->pmem_total = 0; 337 338 pb->io_32bit = 0; 339 if (parent->io_32bit) { 340 io = pci_conf_read(parent->pc, pd->tag, PCI_BRIDGE_STATIO_REG); 341 if (PCI_BRIDGE_IO_32BITS(io)) { 342 pb->io_32bit = 1; 343 } 344 } 345 346 pb->pmem_64bit = 0; 347 if (parent->pmem_64bit) { 348 pmem = pci_conf_read(parent->pc, pd->tag, 349 PCI_BRIDGE_PREFETCHMEM_REG); 350 if (PCI_BRIDGE_PREFETCHMEM_64BITS(pmem)) { 351 pb->pmem_64bit = 1; 352 } 353 } 354 355 if (probe_bus(pb)) { 356 printf("Failed to probe bus %d\n", pb->busno); 357 goto err; 358 } 359 360 if (pb->io_total > 0) { 361 if (parent->niowin >= MAX_CONF_IO) { 362 printf("pciconf: too many I/O windows\n"); 363 goto err; 364 } 365 pb->io_total |= 0xfff; /* Round up */ 366 pi = get_io_desc(parent, pb->io_total); 367 pi->dev = pd; 368 pi->reg = 0; 369 pi->size = pb->io_total; 370 pi->align = 0x1000; /* 4K alignment */ 371 pi->prefetch = 0; 372 parent->niowin++; 373 parent->io_total += pb->io_total; 374 } 375 376 if (pb->mem_total > 0) { 377 if (parent->nmemwin >= MAX_CONF_MEM) { 378 printf("pciconf: too many MEM windows\n"); 379 goto err; 380 } 381 pb->mem_total |= 0xfffff; /* Round up */ 382 pm = get_mem_desc(parent, pb->mem_total); 383 pm->dev = pd; 384 pm->reg = 0; 385 pm->size = pb->mem_total; 386 pm->align = 0x100000; /* 1M alignment */ 387 pm->prefetch = 0; 388 parent->nmemwin++; 389 parent->mem_total += pb->mem_total; 390 } 391 392 if (pb->pmem_total > 0) { 393 if (parent->nmemwin >= MAX_CONF_MEM) { 394 printf("pciconf: too many MEM windows\n"); 395 goto err; 396 } 397 pb->pmem_total |= 0xfffff; /* Round up */ 398 pm = get_mem_desc(parent, pb->pmem_total); 399 pm->dev = pd; 400 pm->reg = 0; 401 pm->size = pb->pmem_total; 402 pm->align = 0x100000; /* 1M alignment */ 403 pm->prefetch = 1; 404 parent->nmemwin++; 405 parent->pmem_total += pb->pmem_total; 406 } 407 408 return pb; 409 err: 410 free(pb, M_DEVBUF); 411 return NULL; 412 } 413 414 static int 415 pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func, int mode) 416 { 417 pciconf_dev_t *pd; 418 pciconf_win_t *pi, *pm; 419 pcireg_t class, cmd, icr, bar, mask, bar64, mask64; 420 u_int64_t size; 421 int br, width; 422 423 pd = &pb->device[pb->ndevs]; 424 pd->pc = pb->pc; 425 pd->tag = tag; 426 pd->ppb = NULL; 427 pd->enable = mode; 428 429 class = pci_conf_read(pb->pc, tag, PCI_CLASS_REG); 430 431 cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG); 432 433 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE) { 434 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 435 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 436 pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd); 437 } else if (pci_conf_debug) { 438 print_tag(pb->pc, tag); 439 printf("device is a bridge; not clearing enables\n"); 440 } 441 442 if ((cmd & PCI_STATUS_BACKTOBACK_SUPPORT) == 0) 443 pb->fast_b2b = 0; 444 445 if ((cmd & PCI_STATUS_66MHZ_SUPPORT) == 0) 446 pb->freq_66 = 0; 447 448 if ( (PCI_CLASS(class) == PCI_CLASS_BRIDGE) 449 && (PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_PCI)) { 450 pd->ppb = query_bus(pb, pd, dev); 451 if (pd->ppb == NULL) 452 return -1; 453 return 0; 454 } 455 456 icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG); 457 pd->ipin = PCI_INTERRUPT_PIN(icr); 458 pd->iline = PCI_INTERRUPT_LINE(icr); 459 pd->min_gnt = PCI_MIN_GNT(icr); 460 pd->max_lat = PCI_MAX_LAT(icr); 461 if (pd->iline || pd->ipin) { 462 pci_conf_interrupt(pb->pc, pb->busno, dev, pd->ipin, pb->swiz, 463 &pd->iline); 464 icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 465 icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT); 466 pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr); 467 } 468 469 if (pd->min_gnt != 0 || pd->max_lat != 0) { 470 if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt) 471 pb->max_mingnt = pd->min_gnt; 472 473 if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat) 474 pb->min_maxlat = pd->max_lat; 475 476 pb->bandwidth_used += pd->min_gnt * 4000000 / 477 (pd->min_gnt + pd->max_lat); 478 } 479 480 width = 4; 481 for (br = PCI_MAPREG_START; br < PCI_MAPREG_END; br += width) { 482 #if 0 483 /* XXX Should only ignore if IDE not in legacy mode? */ 484 if (PCI_CLASS(class) == PCI_CLASS_MASS_STORAGE && 485 PCI_SUBCLASS(class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 486 break; 487 } 488 #endif 489 bar = pci_conf_read(pb->pc, tag, br); 490 pci_conf_write(pb->pc, tag, br, 0xffffffff); 491 mask = pci_conf_read(pb->pc, tag, br); 492 pci_conf_write(pb->pc, tag, br, bar); 493 width = 4; 494 495 if ( (mode & PCI_CONF_MAP_IO) 496 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO)) { 497 /* 498 * Upper 16 bits must be one. Devices may hardwire 499 * them to zero, though, per PCI 2.2, 6.2.5.1, p 203. 500 */ 501 mask |= 0xffff0000; 502 503 size = PCI_MAPREG_IO_SIZE(mask); 504 if (size == 0) { 505 if (pci_conf_debug) { 506 print_tag(pb->pc, tag); 507 printf("I/O BAR 0x%x is void\n", br); 508 } 509 continue; 510 } 511 512 if (pb->niowin >= MAX_CONF_IO) { 513 printf("pciconf: too many I/O windows\n"); 514 return -1; 515 } 516 517 pi = get_io_desc(pb, size); 518 pi->dev = pd; 519 pi->reg = br; 520 pi->size = (u_int64_t) size; 521 pi->align = 4; 522 pi->prefetch = 0; 523 if (pci_conf_debug) { 524 print_tag(pb->pc, tag); 525 printf("Register 0x%x, I/O size %llu\n", 526 br, pi->size); 527 } 528 pb->niowin++; 529 pb->io_total += size; 530 } else if ((mode & PCI_CONF_MAP_MEM) 531 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_MEM)) { 532 switch (PCI_MAPREG_MEM_TYPE(mask)) { 533 case PCI_MAPREG_MEM_TYPE_32BIT: 534 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 535 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 536 break; 537 case PCI_MAPREG_MEM_TYPE_64BIT: 538 bar64 = pci_conf_read(pb->pc, tag, br + 4); 539 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); 540 mask64 = pci_conf_read(pb->pc, tag, br + 4); 541 pci_conf_write(pb->pc, tag, br + 4, bar64); 542 size = (u_int64_t) PCI_MAPREG_MEM64_SIZE( 543 (((u_int64_t) mask64) << 32) | mask); 544 width = 8; 545 continue; 546 default: 547 print_tag(pb->pc, tag); 548 printf("reserved mapping type 0x%x\n", 549 PCI_MAPREG_MEM_TYPE(mask)); 550 continue; 551 } 552 553 if (size == 0) { 554 if (pci_conf_debug) { 555 print_tag(pb->pc, tag); 556 printf("MEM%d BAR 0x%x is void\n", 557 PCI_MAPREG_MEM_TYPE(mask) == 558 PCI_MAPREG_MEM_TYPE_64BIT ? 559 64 : 32, br); 560 } 561 continue; 562 } 563 564 if (pb->nmemwin >= MAX_CONF_MEM) { 565 printf("pciconf: too many memory windows\n"); 566 return -1; 567 } 568 569 pm = get_mem_desc(pb, size); 570 pm->dev = pd; 571 pm->reg = br; 572 pm->size = size; 573 pm->align = 4; 574 pm->prefetch = PCI_MAPREG_MEM_PREFETCHABLE(mask); 575 if (pci_conf_debug) { 576 print_tag(pb->pc, tag); 577 printf("Register 0x%x, memory size %llu\n", 578 br, pm->size); 579 } 580 pb->nmemwin++; 581 if (pm->prefetch) { 582 pb->pmem_total += size; 583 } else { 584 pb->mem_total += size; 585 } 586 } 587 } 588 589 if (mode & PCI_CONF_MAP_ROM) { 590 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 591 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 592 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 593 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, bar); 594 595 if (mask != 0 && mask != 0xffffffff) { 596 if (pb->nmemwin >= MAX_CONF_MEM) { 597 printf("pciconf: too many memory windows\n"); 598 return -1; 599 } 600 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 601 602 pm = get_mem_desc(pb, size); 603 pm->dev = pd; 604 pm->reg = PCI_MAPREG_ROM; 605 pm->size = size; 606 pm->align = 4; 607 pm->prefetch = 1; 608 if (pci_conf_debug) { 609 print_tag(pb->pc, tag); 610 printf("Expansion ROM memory size %llu\n", pm->size); 611 } 612 pb->nmemwin++; 613 pb->pmem_total += size; 614 } 615 } else { 616 /* Ensure ROM is disabled */ 617 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 618 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 619 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 620 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 621 bar & ~PCI_MAPREG_ROM_ENABLE); 622 } 623 624 return 0; 625 } 626 627 /************************************************************************/ 628 /************************************************************************/ 629 /******************** Bus configuration routines ********************/ 630 /************************************************************************/ 631 /************************************************************************/ 632 static u_int64_t 633 pci_allocate_range(struct extent *ex, u_int64_t amt, int align) 634 { 635 int r; 636 u_long addr; 637 638 r = extent_alloc(ex, amt, align, 0, EX_NOWAIT, &addr); 639 if (r) { 640 addr = (u_long) -1; 641 printf("extent_alloc(%p, %llu, %d) returned %d\n", 642 ex, amt, align, r); 643 extent_print(ex); 644 } 645 return (pcireg_t) addr; 646 } 647 648 static int 649 setup_iowins(pciconf_bus_t *pb) 650 { 651 pciconf_win_t *pi; 652 pciconf_dev_t *pd; 653 654 for (pi=pb->pciiowin; pi < &pb->pciiowin[pb->niowin] ; pi++) { 655 if (pi->size == 0) 656 continue; 657 658 pd = pi->dev; 659 pi->address = pci_allocate_range(pb->ioext, pi->size, 660 pi->align); 661 if (pi->address == -1) { 662 print_tag(pd->pc, pd->tag); 663 printf("Failed to allocate PCI I/O space (%llu req)\n", 664 pi->size); 665 return -1; 666 } 667 if (!pb->io_32bit && pi->address > 0xFFFF) { 668 pi->address = 0; 669 pd->enable = 0; 670 } 671 if (pd->ppb && pi->reg == 0) { 672 pd->ppb->ioext = extent_create("pciconf", pi->address, 673 pi->address + pi->size, M_DEVBUF, NULL, 0, 674 EX_NOWAIT); 675 if (pd->ppb->ioext == NULL) { 676 print_tag(pd->pc, pd->tag); 677 printf("Failed to alloc I/O ext. for bus %d\n", 678 pd->ppb->busno); 679 return -1; 680 } 681 continue; 682 } 683 pd->enable |= PCI_CONF_ENABLE_IO; 684 if (pci_conf_debug) { 685 print_tag(pd->pc, pd->tag); 686 printf("Putting %llu I/O bytes @ %#llx (reg %x)\n", 687 pi->size, pi->address, pi->reg); 688 } 689 pci_conf_write(pd->pc, pd->tag, pi->reg, 690 PCI_MAPREG_IO_ADDR(pi->address) | PCI_MAPREG_TYPE_IO); 691 } 692 return 0; 693 } 694 695 static int 696 setup_memwins(pciconf_bus_t *pb) 697 { 698 pciconf_win_t *pm; 699 pciconf_dev_t *pd; 700 pcireg_t base; 701 struct extent *ex; 702 703 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 704 if (pm->size == 0) 705 continue; 706 707 pd = pm->dev; 708 ex = (pm->prefetch) ? pb->pmemext : pb->memext; 709 pm->address = pci_allocate_range(ex, pm->size, pm->align); 710 if (pm->address == -1) { 711 print_tag(pd->pc, pd->tag); 712 printf( 713 "Failed to allocate PCI memory space (%llu req)\n", 714 pm->size); 715 return -1; 716 } 717 if (pd->ppb && pm->reg == 0) { 718 ex = extent_create("pciconf", pm->address, 719 pm->address + pm->size, M_DEVBUF, NULL, 0, 720 EX_NOWAIT); 721 if (ex == NULL) { 722 print_tag(pd->pc, pd->tag); 723 printf("Failed to alloc MEM ext. for bus %d\n", 724 pd->ppb->busno); 725 return -1; 726 } 727 if (pm->prefetch) { 728 pd->ppb->pmemext = ex; 729 } else { 730 pd->ppb->memext = ex; 731 } 732 continue; 733 } 734 if (pm->prefetch && !pb->pmem_64bit && 735 pm->address > 0xFFFFFFFFULL) { 736 pm->address = 0; 737 pd->enable = 0; 738 } else { 739 pd->enable |= PCI_CONF_ENABLE_MEM; 740 } 741 if (pm->reg != PCI_MAPREG_ROM) { 742 if (pci_conf_debug) { 743 print_tag(pd->pc, pd->tag); 744 printf( 745 "Putting %llu MEM bytes @ %#llx (reg %x)\n", 746 pm->size, pm->address, pm->reg); 747 } 748 base = pci_conf_read(pd->pc, pd->tag, pm->reg); 749 base = PCI_MAPREG_MEM_ADDR(pm->address) | 750 PCI_MAPREG_MEM_TYPE(base); 751 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 752 if (PCI_MAPREG_MEM_TYPE(base) == 753 PCI_MAPREG_MEM_TYPE_64BIT) { 754 base = (pcireg_t) 755 (PCI_MAPREG_MEM64_ADDR(pm->address) >> 32); 756 pci_conf_write(pd->pc, pd->tag, pm->reg + 4, 757 base); 758 } 759 } 760 } 761 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 762 if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) { 763 pd = pm->dev; 764 if (pci_conf_debug) { 765 print_tag(pd->pc, pd->tag); 766 printf( 767 "Putting %llu ROM bytes @ %#llx (reg %x)\n", 768 pm->size, pm->address, pm->reg); 769 } 770 base = (pcireg_t) (pm->address | PCI_MAPREG_ROM_ENABLE); 771 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 772 } 773 } 774 return 0; 775 } 776 777 /* 778 * Configure I/O, memory, and prefetcable memory spaces, then make 779 * a call to configure_bus(). 780 */ 781 static int 782 configure_bridge(pciconf_dev_t *pd) 783 { 784 unsigned long io_base, io_limit, mem_base, mem_limit; 785 pciconf_bus_t *pb; 786 pcireg_t io, iohigh, mem, cmd; 787 int rv; 788 789 pb = pd->ppb; 790 /* Configure I/O base & limit*/ 791 if (pb->ioext) { 792 io_base = pb->ioext->ex_start; 793 io_limit = pb->ioext->ex_end; 794 } else { 795 io_base = 0x1000; /* 4K */ 796 io_limit = 0x0000; 797 } 798 if (pb->io_32bit) { 799 iohigh = 800 ((io_base >> 16) << PCI_BRIDGE_IOHIGH_BASE_SHIFT) | 801 ((io_limit >> 16) << PCI_BRIDGE_IOHIGH_LIMIT_SHIFT); 802 } else { 803 if (io_limit > 0xFFFF) { 804 printf("Bus %d bridge does not support 32-bit I/O. ", 805 pb->busno); 806 printf("Disabling I/O accesses\n"); 807 io_base = 0x1000; /* 4K */ 808 io_limit = 0x0000; 809 } 810 iohigh = 0; 811 } 812 io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG) & 813 (PCI_BRIDGE_STATIO_STATUS_MASK << PCI_BRIDGE_STATIO_STATUS_SHIFT); 814 io |= (((io_base >> 8) & PCI_BRIDGE_STATIO_IOBASE_MASK) 815 << PCI_BRIDGE_STATIO_IOBASE_SHIFT); 816 io |= (((io_limit >> 8) & PCI_BRIDGE_STATIO_IOLIMIT_MASK) 817 << PCI_BRIDGE_STATIO_IOLIMIT_SHIFT); 818 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io); 819 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh); 820 821 /* Configure mem base & limit */ 822 if (pb->memext) { 823 mem_base = pb->memext->ex_start; 824 mem_limit = pb->memext->ex_end; 825 } else { 826 mem_base = 0x100000; /* 1M */ 827 mem_limit = 0x000000; 828 } 829 if (mem_limit > 0xFFFFFFFFULL) { 830 printf("Bus %d bridge MEM range out of range. ", pb->busno); 831 printf("Disabling MEM accesses\n"); 832 mem_base = 0x100000; /* 1M */ 833 mem_limit = 0x000000; 834 } 835 mem = (((mem_base >> 20) & PCI_BRIDGE_MEMORY_BASE_MASK) 836 << PCI_BRIDGE_MEMORY_BASE_SHIFT); 837 mem |= (((mem_limit >> 20) & PCI_BRIDGE_MEMORY_LIMIT_MASK) 838 << PCI_BRIDGE_MEMORY_LIMIT_SHIFT); 839 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem); 840 841 /* Configure prefetchable mem base & limit */ 842 if (pb->pmemext) { 843 mem_base = pb->pmemext->ex_start; 844 mem_limit = pb->pmemext->ex_end; 845 } else { 846 mem_base = 0x100000; /* 1M */ 847 mem_limit = 0x000000; 848 } 849 mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG); 850 if (!PCI_BRIDGE_PREFETCHMEM_64BITS(mem) && mem_limit > 0xFFFFFFFFULL) { 851 printf("Bus %d bridge does not support 64-bit PMEM. ", 852 pb->busno); 853 printf("Disabling prefetchable-MEM accesses\n"); 854 mem_base = 0x100000; /* 1M */ 855 mem_limit = 0x000000; 856 } 857 mem = (((mem_base >> 20) & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) 858 << PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT); 859 mem |= (((mem_limit >> 20) & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) 860 << PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT); 861 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem); 862 /* 863 * XXX -- 64-bit systems need a lot more than just this... 864 */ 865 if (sizeof(u_long) > 4) { 866 mem_base = (int64_t) mem_base >> 32; 867 mem_limit = (int64_t) mem_limit >> 32; 868 } 869 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHBASE32_REG, 870 mem_base & 0xffffffff); 871 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHLIMIT32_REG, 872 mem_limit & 0xffffffff); 873 874 rv = configure_bus(pb); 875 876 if (pb->ioext) 877 extent_destroy(pb->ioext); 878 if (pb->memext) 879 extent_destroy(pb->memext); 880 if (pb->pmemext) 881 extent_destroy(pb->pmemext); 882 if (rv == 0) { 883 cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG); 884 cmd &= PCI_BRIDGE_CONTROL_MASK; 885 cmd |= (PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR) 886 << PCI_BRIDGE_CONTROL_SHIFT; 887 if (pb->fast_b2b) { 888 cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B 889 << PCI_BRIDGE_CONTROL_SHIFT; 890 } 891 pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd); 892 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 893 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 894 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 895 } 896 897 return rv; 898 } 899 900 /* 901 * Calculate latency values, allocate I/O and MEM segments, then set them 902 * up. If a PCI-PCI bridge is found, configure the bridge separately, 903 * which will cause a recursive call back here. 904 */ 905 static int 906 configure_bus(pciconf_bus_t *pb) 907 { 908 pciconf_dev_t *pd; 909 int def_ltim, max_ltim, band, bus_mhz; 910 911 bus_mhz = pb->freq_66 ? 66 : 33; 912 max_ltim = pb->max_mingnt * bus_mhz / 4; /* cvt to cycle count */ 913 band = 40000000; /* 0.25us cycles/sec */ 914 if (band < pb->bandwidth_used) { 915 printf("PCI bus %d: Warning: Total bandwidth exceeded!?\n", 916 pb->busno); 917 def_ltim = -1; 918 } else { 919 def_ltim = (band - pb->bandwidth_used) / pb->ndevs; 920 if (def_ltim > pb->min_maxlat) 921 def_ltim = pb->min_maxlat; 922 def_ltim = def_ltim * bus_mhz / 4; 923 } 924 def_ltim = (def_ltim + 7) & ~7; 925 max_ltim = (max_ltim + 7) & ~7; 926 927 pb->def_ltim = MIN( def_ltim, 255 ); 928 pb->max_ltim = MIN( MAX(max_ltim, def_ltim ), 255 ); 929 930 /* 931 * Now we have what we need to initialize the devices. 932 * It would probably be better if we could allocate all of these 933 * for all busses at once, but "not right now". First, get a list 934 * of free memory ranges from the m.d. system. 935 */ 936 if (setup_iowins(pb) || setup_memwins(pb)) { 937 printf("PCI bus configuration failed: "); 938 printf("unable to assign all I/O and memory ranges."); 939 return -1; 940 } 941 942 /* 943 * Configure the latency for the devices, and enable them. 944 */ 945 for (pd=pb->device ; pd < &pb->device[pb->ndevs] ; pd++) { 946 pcireg_t cmd, class, misc; 947 int ltim; 948 949 if (pci_conf_debug) { 950 print_tag(pd->pc, pd->tag); 951 printf("Configuring device.\n"); 952 } 953 class = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG); 954 misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG); 955 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 956 cmd |= PCI_COMMAND_SERR_ENABLE | PCI_COMMAND_PARITY_ENABLE; 957 if (pb->fast_b2b) 958 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE; 959 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 960 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_PCI) { 961 if (pd->enable & PCI_CONF_ENABLE_IO) 962 cmd |= PCI_COMMAND_IO_ENABLE; 963 if (pd->enable & PCI_CONF_ENABLE_MEM) 964 cmd |= PCI_COMMAND_MEM_ENABLE; 965 if (pd->enable & PCI_CONF_ENABLE_BM) 966 cmd |= PCI_COMMAND_MASTER_ENABLE; 967 ltim = pd->min_gnt * bus_mhz / 4; 968 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim); 969 } else { 970 cmd |= PCI_COMMAND_MASTER_ENABLE; 971 ltim = MIN (pb->def_ltim, pb->max_ltim); 972 } 973 if (!(pd->enable)) { 974 print_tag(pd->pc, pd->tag); 975 printf("Disabled due to lack of resources.\n"); 976 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 977 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 978 } 979 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 980 981 misc = (misc & ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT)) 982 | ((ltim & 0xff) << PCI_LATTIMER_SHIFT); 983 pci_conf_write(pd->pc, pd->tag, PCI_BHLC_REG, misc); 984 985 if (pd->ppb) { 986 if (configure_bridge(pd) < 0) 987 return -1; 988 continue; 989 } 990 } 991 992 if (pci_conf_debug) { 993 printf("PCI bus %d configured\n", pb->busno); 994 } 995 996 return 0; 997 } 998 999 /* 1000 * Let's configure the PCI bus. 1001 * This consists of basically scanning for all existing devices, 1002 * identifying their needs, and then making another pass over them 1003 * to set: 1004 * 1. I/O addresses 1005 * 2. Memory addresses (Prefetchable and not) 1006 * 3. PCI command register 1007 * 4. The latency part of the PCI BHLC (BIST (Built-In Self Test), 1008 * Header type, Latency timer, Cache line size) register 1009 * 1010 * The command register is set to enable fast back-to-back transactions 1011 * if the host bridge says it can handle it. We also configure 1012 * Master Enable, SERR enable, parity enable, and (if this is not a 1013 * PCI-PCI bridge) the I/O and Memory spaces. Apparently some devices 1014 * will not report some I/O space. 1015 * 1016 * The latency is computed to be a "fair share" of the bus bandwidth. 1017 * The bus bandwidth variable is initialized to the number of PCI cycles 1018 * in one second. The number of cycles taken for one transaction by each 1019 * device (MAX_LAT + MIN_GNT) is then subtracted from the bandwidth. 1020 * Care is taken to ensure that the latency timer won't be set such that 1021 * it would exceed the critical time for any device. 1022 * 1023 * This is complicated somewhat due to the presence of bridges. PCI-PCI 1024 * bridges are probed and configured recursively. 1025 */ 1026 int 1027 pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext, 1028 struct extent *memext, struct extent *pmemext, int firstbus) 1029 { 1030 pciconf_bus_t *pb; 1031 int rv; 1032 1033 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 1034 pb->busno = firstbus; 1035 pb->busno_spacing = PCI_BUSNO_SPACING; 1036 pb->next_busno = pb->busno + 1; 1037 pb->last_busno = 255; 1038 pb->parent_bus = NULL; 1039 pb->swiz = 0; 1040 pb->io_32bit = 1; 1041 pb->pmem_64bit = 0; 1042 pb->ioext = ioext; 1043 pb->memext = memext; 1044 if (pmemext == NULL) { 1045 pb->pmemext = memext; 1046 } else { 1047 pb->pmemext = pmemext; 1048 } 1049 pb->pc = pc; 1050 pb->io_total = pb->mem_total = pb->pmem_total = 0; 1051 1052 rv = probe_bus(pb); 1053 if (rv == 0) { 1054 rv = configure_bus(pb); 1055 } 1056 1057 /* 1058 * All done! 1059 */ 1060 free(pb, M_DEVBUF); 1061 return rv; 1062 } 1063
Indexes created Wed Sep 24 05:09:52 GMT 2025