pciconf.c revision 1.16
1 /* $NetBSD: pciconf.c,v 1.16 2002/06/27 00:59:21 briggs Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Derived in part from code from PMON/2000 (http://pmon.groupbsd.org/). 39 */ 40 41 /* 42 * To do: 43 * - Perform all data structure allocation dynamically, don't have 44 * statically-sized arrays ("oops, you lose because you have too 45 * many slots filled!") 46 * - Do this in 2 passes, with an MD hook to control the behavior: 47 * (1) Configure the bus (possibly including expansion 48 * ROMs. 49 * (2) Another pass to disable expansion ROMs if they're 50 * mapped (since you're not supposed to leave them 51 * mapped when you're not using them). 52 * This would facilitate MD code executing the expansion ROMs 53 * if necessary (possibly with an x86 emulator) to configure 54 * devices (e.g. VGA cards). 55 * - Deal with "anything can be hot-plugged" -- i.e., carry configuration 56 * information around & be able to reconfigure on the fly 57 * - Deal with segments (See IA64 System Abstraction Layer) 58 * - Deal with subtractive bridges (& non-spec positive/subtractive decode) 59 * - Deal with ISA/VGA/VGA palette snooping 60 * - Deal with device capabilities on bridges 61 * - Worry about changing a bridge to/from transparency 62 * From thorpej (05/25/01) 63 * - Try to handle devices that are already configured (perhaps using that 64 * as a hint to where we put other devices) 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: pciconf.c,v 1.16 2002/06/27 00:59:21 briggs Exp $"); 69 70 #include "opt_pci.h" 71 72 #include <sys/param.h> 73 #include <sys/extent.h> 74 #include <sys/queue.h> 75 #include <sys/systm.h> 76 #include <sys/malloc.h> 77 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/pciconf.h> 80 #include <dev/pci/pcidevs.h> 81 82 int pci_conf_debug = 0; 83 84 #if !defined(MIN) 85 #define MIN(a,b) (((a)<(b))?(a):(b)) 86 #define MAX(a,b) (((a)>(b))?(a):(b)) 87 #endif 88 89 /* per-bus constants. */ 90 #define MAX_CONF_DEV 32 /* Arbitrary */ 91 #define MAX_CONF_MEM (3 * MAX_CONF_DEV) /* Avg. 3 per device -- Arb. */ 92 #define MAX_CONF_IO (3 * MAX_CONF_DEV) /* Avg. 1 per device -- Arb. */ 93 94 #define PCI_BUSNO_SPACING (1 << 5) 95 96 struct _s_pciconf_bus_t; /* Forward declaration */ 97 98 typedef struct _s_pciconf_dev_t { 99 int ipin; 100 int iline; 101 int min_gnt; 102 int max_lat; 103 int enable; 104 pcitag_t tag; 105 pci_chipset_tag_t pc; 106 struct _s_pciconf_bus_t *ppb; /* I am really a bridge */ 107 } pciconf_dev_t; 108 109 typedef struct _s_pciconf_win_t { 110 pciconf_dev_t *dev; 111 int reg; /* 0 for busses */ 112 int align; 113 int prefetch; 114 u_int64_t size; 115 u_int64_t address; 116 } pciconf_win_t; 117 118 typedef struct _s_pciconf_bus_t { 119 int busno; 120 int next_busno; 121 int last_busno; 122 int busno_spacing; 123 int max_mingnt; 124 int min_maxlat; 125 int cacheline_size; 126 int prefetch; 127 int fast_b2b; 128 int freq_66; 129 int def_ltim; 130 int max_ltim; 131 int bandwidth_used; 132 int swiz; 133 int io_32bit; 134 int pmem_64bit; 135 136 int ndevs; 137 pciconf_dev_t device[MAX_CONF_DEV]; 138 139 /* These should be sorted in order of decreasing size */ 140 int nmemwin; 141 pciconf_win_t pcimemwin[MAX_CONF_MEM]; 142 int niowin; 143 pciconf_win_t pciiowin[MAX_CONF_IO]; 144 145 bus_size_t io_total; 146 bus_size_t mem_total; 147 bus_size_t pmem_total; 148 149 struct extent *ioext; 150 struct extent *memext; 151 struct extent *pmemext; 152 153 pci_chipset_tag_t pc; 154 struct _s_pciconf_bus_t *parent_bus; 155 } pciconf_bus_t; 156 157 static int probe_bus(pciconf_bus_t *); 158 static void alloc_busno(pciconf_bus_t *, pciconf_bus_t *); 159 static int pci_do_device_query(pciconf_bus_t *, pcitag_t, int, int, int); 160 static int setup_iowins(pciconf_bus_t *); 161 static int setup_memwins(pciconf_bus_t *); 162 static int configure_bridge(pciconf_dev_t *); 163 static int configure_bus(pciconf_bus_t *); 164 static u_int64_t pci_allocate_range(struct extent *, u_int64_t, int); 165 static pciconf_win_t *get_io_desc(pciconf_bus_t *, bus_size_t); 166 static pciconf_win_t *get_mem_desc(pciconf_bus_t *, bus_size_t); 167 static pciconf_bus_t *query_bus(pciconf_bus_t *, pciconf_dev_t *, int); 168 169 static void print_tag(pci_chipset_tag_t, pcitag_t); 170 171 static void 172 print_tag(pci_chipset_tag_t pc, pcitag_t tag) 173 { 174 int bus, dev, func; 175 176 pci_decompose_tag(pc, tag, &bus, &dev, &func); 177 printf("PCI: bus %d, device %d, function %d: ", bus, dev, func); 178 } 179 180 /************************************************************************/ 181 /************************************************************************/ 182 /*********************** Bus probing routines ***********************/ 183 /************************************************************************/ 184 /************************************************************************/ 185 static pciconf_win_t * 186 get_io_desc(pciconf_bus_t *pb, bus_size_t size) 187 { 188 int i, n; 189 190 n = pb->niowin; 191 for (i=n; i > 0 && size > pb->pciiowin[i-1].size; i--) 192 pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */ 193 return &pb->pciiowin[i]; 194 } 195 196 static pciconf_win_t * 197 get_mem_desc(pciconf_bus_t *pb, bus_size_t size) 198 { 199 int i, n; 200 201 n = pb->nmemwin; 202 for (i=n; i > 0 && size > pb->pcimemwin[i-1].size; i--) 203 pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */ 204 return &pb->pcimemwin[i]; 205 } 206 207 /* 208 * Set up bus common stuff, then loop over devices & functions. 209 * If we find something, call pci_do_device_query()). 210 */ 211 static int 212 probe_bus(pciconf_bus_t *pb) 213 { 214 int device, maxdevs; 215 #ifdef __PCI_BUS_DEVORDER 216 char devs[32]; 217 int i; 218 #endif 219 220 maxdevs = pci_bus_maxdevs(pb->pc, pb->busno); 221 pb->ndevs = 0; 222 pb->niowin = 0; 223 pb->nmemwin = 0; 224 pb->freq_66 = 1; 225 pb->fast_b2b = 1; 226 pb->prefetch = 1; 227 pb->max_mingnt = 0; /* we are looking for the maximum */ 228 pb->min_maxlat = 0x100; /* we are looking for the minimum */ 229 pb->bandwidth_used = 0; 230 231 #ifdef __PCI_BUS_DEVORDER 232 pci_bus_devorder(pb->pc, pb->busno, devs); 233 for (i=0; (device=devs[i]) < 32 && device >= 0; i++) { 234 #else 235 for (device=0; device < maxdevs; device++) { 236 #endif 237 pcitag_t tag; 238 pcireg_t id, bhlcr; 239 int function, nfunction; 240 int confmode; 241 242 tag = pci_make_tag(pb->pc, pb->busno, device, 0); 243 if (pci_conf_debug) { 244 print_tag(pb->pc, tag); 245 } 246 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 247 248 if (pci_conf_debug) { 249 printf("id=%x: Vendor=%x, Product=%x\n", 250 id, PCI_VENDOR(id),PCI_PRODUCT(id)); 251 } 252 /* Invalid vendor ID value? */ 253 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 254 continue; 255 256 bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 257 nfunction = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 258 for (function = 0 ; function < nfunction ; function++) { 259 tag = pci_make_tag(pb->pc, pb->busno, device, function); 260 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 261 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 262 continue; 263 if (pb->ndevs+1 < MAX_CONF_DEV) { 264 if (pci_conf_debug) { 265 print_tag(pb->pc, tag); 266 printf("Found dev 0x%04x 0x%04x -- " 267 "really probing.\n", 268 PCI_VENDOR(id), PCI_PRODUCT(id)); 269 } 270 #ifdef __HAVE_PCI_CONF_HOOK 271 confmode = pci_conf_hook(pb->pc, pb->busno, 272 device, function, id); 273 if (confmode == 0) 274 continue; 275 #else 276 /* 277 * Don't enable expansion ROMS -- some cards 278 * share address decoders between the EXPROM 279 * and PCI memory space, and enabling the ROM 280 * when not needed will cause all sorts of 281 * lossage. 282 */ 283 confmode = PCI_CONF_ALL & ~PCI_CONF_MAP_ROM; 284 #endif 285 if (pci_do_device_query(pb, tag, device, 286 function, confmode)) 287 return -1; 288 pb->ndevs++; 289 } 290 } 291 } 292 return 0; 293 } 294 295 static void 296 alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb) 297 { 298 pb->busno = parent->next_busno; 299 if (parent->next_busno + parent->busno_spacing > parent->last_busno) 300 panic("Too many PCI busses on bus %d", parent->busno); 301 parent->next_busno = parent->next_busno + parent->busno_spacing; 302 pb->next_busno = pb->busno+1; 303 pb->busno_spacing = parent->busno_spacing >> 1; 304 if (!pb->busno_spacing) 305 panic("PCI busses nested too deep."); 306 pb->last_busno = parent->next_busno - 1; 307 } 308 309 static pciconf_bus_t * 310 query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev) 311 { 312 pciconf_bus_t *pb; 313 pcireg_t busreg, io, pmem; 314 pciconf_win_t *pi, *pm; 315 316 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 317 if (!pb) 318 panic("Unable to allocate memory for PCI configuration."); 319 320 pb->cacheline_size = parent->cacheline_size; 321 pb->parent_bus = parent; 322 alloc_busno(parent, pb); 323 if (pci_conf_debug) 324 printf("PCI bus bridge covers busses %d-%d\n", 325 pb->busno, pb->last_busno); 326 327 busreg = parent->busno << PCI_BRIDGE_BUS_PRIMARY_SHIFT; 328 busreg |= pb->busno << PCI_BRIDGE_BUS_SECONDARY_SHIFT; 329 busreg |= pb->last_busno << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 330 pci_conf_write(parent->pc, pd->tag, PCI_BRIDGE_BUS_REG, busreg); 331 332 pb->swiz = parent->swiz + dev; 333 334 pb->ioext = NULL; 335 pb->memext = NULL; 336 pb->pmemext = NULL; 337 pb->pc = parent->pc; 338 pb->io_total = pb->mem_total = pb->pmem_total = 0; 339 340 pb->io_32bit = 0; 341 if (parent->io_32bit) { 342 io = pci_conf_read(parent->pc, pd->tag, PCI_BRIDGE_STATIO_REG); 343 if (PCI_BRIDGE_IO_32BITS(io)) { 344 pb->io_32bit = 1; 345 } 346 } 347 348 pb->pmem_64bit = 0; 349 if (parent->pmem_64bit) { 350 pmem = pci_conf_read(parent->pc, pd->tag, 351 PCI_BRIDGE_PREFETCHMEM_REG); 352 if (PCI_BRIDGE_PREFETCHMEM_64BITS(pmem)) { 353 pb->pmem_64bit = 1; 354 } 355 } 356 357 if (probe_bus(pb)) { 358 printf("Failed to probe bus %d\n", pb->busno); 359 goto err; 360 } 361 362 if (pb->io_total > 0) { 363 if (parent->niowin >= MAX_CONF_IO) { 364 printf("pciconf: too many I/O windows\n"); 365 goto err; 366 } 367 pb->io_total |= 0xfff; /* Round up */ 368 pi = get_io_desc(parent, pb->io_total); 369 pi->dev = pd; 370 pi->reg = 0; 371 pi->size = pb->io_total; 372 pi->align = 0x1000; /* 4K alignment */ 373 pi->prefetch = 0; 374 parent->niowin++; 375 parent->io_total += pb->io_total; 376 } 377 378 if (pb->mem_total > 0) { 379 if (parent->nmemwin >= MAX_CONF_MEM) { 380 printf("pciconf: too many MEM windows\n"); 381 goto err; 382 } 383 pb->mem_total |= 0xfffff; /* Round up */ 384 pm = get_mem_desc(parent, pb->mem_total); 385 pm->dev = pd; 386 pm->reg = 0; 387 pm->size = pb->mem_total; 388 pm->align = 0x100000; /* 1M alignment */ 389 pm->prefetch = 0; 390 parent->nmemwin++; 391 parent->mem_total += pb->mem_total; 392 } 393 394 if (pb->pmem_total > 0) { 395 if (parent->nmemwin >= MAX_CONF_MEM) { 396 printf("pciconf: too many MEM windows\n"); 397 goto err; 398 } 399 pb->pmem_total |= 0xfffff; /* Round up */ 400 pm = get_mem_desc(parent, pb->pmem_total); 401 pm->dev = pd; 402 pm->reg = 0; 403 pm->size = pb->pmem_total; 404 pm->align = 0x100000; /* 1M alignment */ 405 pm->prefetch = 1; 406 parent->nmemwin++; 407 parent->pmem_total += pb->pmem_total; 408 } 409 410 return pb; 411 err: 412 free(pb, M_DEVBUF); 413 return NULL; 414 } 415 416 static int 417 pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func, int mode) 418 { 419 pciconf_dev_t *pd; 420 pciconf_win_t *pi, *pm; 421 pcireg_t class, cmd, icr, bar, mask, bar64, mask64; 422 u_int64_t size; 423 int br, width; 424 425 pd = &pb->device[pb->ndevs]; 426 pd->pc = pb->pc; 427 pd->tag = tag; 428 pd->ppb = NULL; 429 pd->enable = mode; 430 431 class = pci_conf_read(pb->pc, tag, PCI_CLASS_REG); 432 433 cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG); 434 435 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE) { 436 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 437 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 438 pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd); 439 } else if (pci_conf_debug) { 440 print_tag(pb->pc, tag); 441 printf("device is a bridge; not clearing enables\n"); 442 } 443 444 if ((cmd & PCI_STATUS_BACKTOBACK_SUPPORT) == 0) 445 pb->fast_b2b = 0; 446 447 if ((cmd & PCI_STATUS_66MHZ_SUPPORT) == 0) 448 pb->freq_66 = 0; 449 450 if ( (PCI_CLASS(class) == PCI_CLASS_BRIDGE) 451 && (PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_PCI)) { 452 pd->ppb = query_bus(pb, pd, dev); 453 if (pd->ppb == NULL) 454 return -1; 455 return 0; 456 } 457 458 icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG); 459 pd->ipin = PCI_INTERRUPT_PIN(icr); 460 pd->iline = PCI_INTERRUPT_LINE(icr); 461 pd->min_gnt = PCI_MIN_GNT(icr); 462 pd->max_lat = PCI_MAX_LAT(icr); 463 if (pd->iline || pd->ipin) { 464 pci_conf_interrupt(pb->pc, pb->busno, dev, pd->ipin, pb->swiz, 465 &pd->iline); 466 icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 467 icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT); 468 pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr); 469 } 470 471 if (pd->min_gnt != 0 || pd->max_lat != 0) { 472 if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt) 473 pb->max_mingnt = pd->min_gnt; 474 475 if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat) 476 pb->min_maxlat = pd->max_lat; 477 478 pb->bandwidth_used += pd->min_gnt * 4000000 / 479 (pd->min_gnt + pd->max_lat); 480 } 481 482 width = 4; 483 for (br = PCI_MAPREG_START; br < PCI_MAPREG_END; br += width) { 484 #if 0 485 /* XXX Should only ignore if IDE not in legacy mode? */ 486 if (PCI_CLASS(class) == PCI_CLASS_MASS_STORAGE && 487 PCI_SUBCLASS(class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 488 break; 489 } 490 #endif 491 bar = pci_conf_read(pb->pc, tag, br); 492 pci_conf_write(pb->pc, tag, br, 0xffffffff); 493 mask = pci_conf_read(pb->pc, tag, br); 494 pci_conf_write(pb->pc, tag, br, bar); 495 width = 4; 496 497 if ( (mode & PCI_CONF_MAP_IO) 498 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO)) { 499 /* 500 * Upper 16 bits must be one. Devices may hardwire 501 * them to zero, though, per PCI 2.2, 6.2.5.1, p 203. 502 */ 503 mask |= 0xffff0000; 504 505 size = PCI_MAPREG_IO_SIZE(mask); 506 if (size == 0) { 507 if (pci_conf_debug) { 508 print_tag(pb->pc, tag); 509 printf("I/O BAR 0x%x is void\n", br); 510 } 511 continue; 512 } 513 514 if (pb->niowin >= MAX_CONF_IO) { 515 printf("pciconf: too many I/O windows\n"); 516 return -1; 517 } 518 519 pi = get_io_desc(pb, size); 520 pi->dev = pd; 521 pi->reg = br; 522 pi->size = (u_int64_t) size; 523 pi->align = 4; 524 pi->prefetch = 0; 525 if (pci_conf_debug) { 526 print_tag(pb->pc, tag); 527 printf("Register 0x%x, I/O size %llu\n", 528 br, pi->size); 529 } 530 pb->niowin++; 531 pb->io_total += size; 532 } else if ((mode & PCI_CONF_MAP_MEM) 533 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_MEM)) { 534 switch (PCI_MAPREG_MEM_TYPE(mask)) { 535 case PCI_MAPREG_MEM_TYPE_32BIT: 536 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 537 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 538 break; 539 case PCI_MAPREG_MEM_TYPE_64BIT: 540 bar64 = pci_conf_read(pb->pc, tag, br + 4); 541 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); 542 mask64 = pci_conf_read(pb->pc, tag, br + 4); 543 pci_conf_write(pb->pc, tag, br + 4, bar64); 544 size = (u_int64_t) PCI_MAPREG_MEM64_SIZE( 545 (((u_int64_t) mask64) << 32) | mask); 546 width = 8; 547 break; 548 default: 549 print_tag(pb->pc, tag); 550 printf("reserved mapping type 0x%x\n", 551 PCI_MAPREG_MEM_TYPE(mask)); 552 continue; 553 } 554 555 if (size == 0) { 556 if (pci_conf_debug) { 557 print_tag(pb->pc, tag); 558 printf("MEM%d BAR 0x%x is void\n", 559 PCI_MAPREG_MEM_TYPE(mask) == 560 PCI_MAPREG_MEM_TYPE_64BIT ? 561 64 : 32, br); 562 } 563 continue; 564 } else { 565 if (pci_conf_debug) { 566 print_tag(pb->pc, tag); 567 printf("MEM%d BAR 0x%x has size %lx\n", 568 PCI_MAPREG_MEM_TYPE(mask) == 569 PCI_MAPREG_MEM_TYPE_64BIT ? 570 64 : 32, br, (unsigned long)size); 571 } 572 } 573 574 if (pb->nmemwin >= MAX_CONF_MEM) { 575 printf("pciconf: too many memory windows\n"); 576 return -1; 577 } 578 579 pm = get_mem_desc(pb, size); 580 pm->dev = pd; 581 pm->reg = br; 582 pm->size = size; 583 pm->align = 4; 584 pm->prefetch = PCI_MAPREG_MEM_PREFETCHABLE(mask); 585 if (pci_conf_debug) { 586 print_tag(pb->pc, tag); 587 printf("Register 0x%x, memory size %llu\n", 588 br, pm->size); 589 } 590 pb->nmemwin++; 591 if (pm->prefetch) { 592 pb->pmem_total += size; 593 } else { 594 pb->mem_total += size; 595 } 596 } 597 } 598 599 if (mode & PCI_CONF_MAP_ROM) { 600 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 601 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 602 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 603 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, bar); 604 605 if (mask != 0 && mask != 0xffffffff) { 606 if (pb->nmemwin >= MAX_CONF_MEM) { 607 printf("pciconf: too many memory windows\n"); 608 return -1; 609 } 610 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 611 612 pm = get_mem_desc(pb, size); 613 pm->dev = pd; 614 pm->reg = PCI_MAPREG_ROM; 615 pm->size = size; 616 pm->align = 4; 617 pm->prefetch = 1; 618 if (pci_conf_debug) { 619 print_tag(pb->pc, tag); 620 printf("Expansion ROM memory size %llu\n", pm->size); 621 } 622 pb->nmemwin++; 623 pb->pmem_total += size; 624 } 625 } else { 626 /* Ensure ROM is disabled */ 627 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 628 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 629 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 630 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 631 bar & ~PCI_MAPREG_ROM_ENABLE); 632 } 633 634 return 0; 635 } 636 637 /************************************************************************/ 638 /************************************************************************/ 639 /******************** Bus configuration routines ********************/ 640 /************************************************************************/ 641 /************************************************************************/ 642 static u_int64_t 643 pci_allocate_range(struct extent *ex, u_int64_t amt, int align) 644 { 645 int r; 646 u_long addr; 647 648 r = extent_alloc(ex, amt, align, 0, EX_NOWAIT, &addr); 649 if (r) { 650 addr = (u_long) -1; 651 printf("extent_alloc(%p, %llu, %d) returned %d\n", 652 ex, amt, align, r); 653 extent_print(ex); 654 } 655 return (pcireg_t) addr; 656 } 657 658 static int 659 setup_iowins(pciconf_bus_t *pb) 660 { 661 pciconf_win_t *pi; 662 pciconf_dev_t *pd; 663 664 for (pi=pb->pciiowin; pi < &pb->pciiowin[pb->niowin] ; pi++) { 665 if (pi->size == 0) 666 continue; 667 668 pd = pi->dev; 669 pi->address = pci_allocate_range(pb->ioext, pi->size, 670 pi->align); 671 if (pi->address == -1) { 672 print_tag(pd->pc, pd->tag); 673 printf("Failed to allocate PCI I/O space (%llu req)\n", 674 pi->size); 675 return -1; 676 } 677 if (!pb->io_32bit && pi->address > 0xFFFF) { 678 pi->address = 0; 679 pd->enable = 0; 680 } 681 if (pd->ppb && pi->reg == 0) { 682 pd->ppb->ioext = extent_create("pciconf", pi->address, 683 pi->address + pi->size, M_DEVBUF, NULL, 0, 684 EX_NOWAIT); 685 if (pd->ppb->ioext == NULL) { 686 print_tag(pd->pc, pd->tag); 687 printf("Failed to alloc I/O ext. for bus %d\n", 688 pd->ppb->busno); 689 return -1; 690 } 691 continue; 692 } 693 pd->enable |= PCI_CONF_ENABLE_IO; 694 if (pci_conf_debug) { 695 print_tag(pd->pc, pd->tag); 696 printf("Putting %llu I/O bytes @ %#llx (reg %x)\n", 697 pi->size, pi->address, pi->reg); 698 } 699 pci_conf_write(pd->pc, pd->tag, pi->reg, 700 PCI_MAPREG_IO_ADDR(pi->address) | PCI_MAPREG_TYPE_IO); 701 } 702 return 0; 703 } 704 705 static int 706 setup_memwins(pciconf_bus_t *pb) 707 { 708 pciconf_win_t *pm; 709 pciconf_dev_t *pd; 710 pcireg_t base; 711 struct extent *ex; 712 713 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 714 if (pm->size == 0) 715 continue; 716 717 pd = pm->dev; 718 ex = (pm->prefetch) ? pb->pmemext : pb->memext; 719 pm->address = pci_allocate_range(ex, pm->size, pm->align); 720 if (pm->address == -1) { 721 print_tag(pd->pc, pd->tag); 722 printf( 723 "Failed to allocate PCI memory space (%llu req)\n", 724 pm->size); 725 return -1; 726 } 727 if (pd->ppb && pm->reg == 0) { 728 ex = extent_create("pciconf", pm->address, 729 pm->address + pm->size, M_DEVBUF, NULL, 0, 730 EX_NOWAIT); 731 if (ex == NULL) { 732 print_tag(pd->pc, pd->tag); 733 printf("Failed to alloc MEM ext. for bus %d\n", 734 pd->ppb->busno); 735 return -1; 736 } 737 if (pm->prefetch) { 738 pd->ppb->pmemext = ex; 739 } else { 740 pd->ppb->memext = ex; 741 } 742 continue; 743 } 744 if (pm->prefetch && !pb->pmem_64bit && 745 pm->address > 0xFFFFFFFFULL) { 746 pm->address = 0; 747 pd->enable = 0; 748 } else { 749 pd->enable |= PCI_CONF_ENABLE_MEM; 750 } 751 if (pm->reg != PCI_MAPREG_ROM) { 752 if (pci_conf_debug) { 753 print_tag(pd->pc, pd->tag); 754 printf( 755 "Putting %llu MEM bytes @ %#llx (reg %x)\n", 756 pm->size, pm->address, pm->reg); 757 } 758 base = pci_conf_read(pd->pc, pd->tag, pm->reg); 759 base = PCI_MAPREG_MEM_ADDR(pm->address) | 760 PCI_MAPREG_MEM_TYPE(base); 761 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 762 if (PCI_MAPREG_MEM_TYPE(base) == 763 PCI_MAPREG_MEM_TYPE_64BIT) { 764 base = (pcireg_t) 765 (PCI_MAPREG_MEM64_ADDR(pm->address) >> 32); 766 pci_conf_write(pd->pc, pd->tag, pm->reg + 4, 767 base); 768 } 769 } 770 } 771 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 772 if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) { 773 pd = pm->dev; 774 if (pci_conf_debug) { 775 print_tag(pd->pc, pd->tag); 776 printf( 777 "Putting %llu ROM bytes @ %#llx (reg %x)\n", 778 pm->size, pm->address, pm->reg); 779 } 780 base = (pcireg_t) (pm->address | PCI_MAPREG_ROM_ENABLE); 781 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 782 } 783 } 784 return 0; 785 } 786 787 /* 788 * Configure I/O, memory, and prefetcable memory spaces, then make 789 * a call to configure_bus(). 790 */ 791 static int 792 configure_bridge(pciconf_dev_t *pd) 793 { 794 unsigned long io_base, io_limit, mem_base, mem_limit; 795 pciconf_bus_t *pb; 796 pcireg_t io, iohigh, mem, cmd; 797 int rv; 798 799 pb = pd->ppb; 800 /* Configure I/O base & limit*/ 801 if (pb->ioext) { 802 io_base = pb->ioext->ex_start; 803 io_limit = pb->ioext->ex_end; 804 } else { 805 io_base = 0x1000; /* 4K */ 806 io_limit = 0x0000; 807 } 808 if (pb->io_32bit) { 809 iohigh = 810 ((io_base >> 16) << PCI_BRIDGE_IOHIGH_BASE_SHIFT) | 811 ((io_limit >> 16) << PCI_BRIDGE_IOHIGH_LIMIT_SHIFT); 812 } else { 813 if (io_limit > 0xFFFF) { 814 printf("Bus %d bridge does not support 32-bit I/O. ", 815 pb->busno); 816 printf("Disabling I/O accesses\n"); 817 io_base = 0x1000; /* 4K */ 818 io_limit = 0x0000; 819 } 820 iohigh = 0; 821 } 822 io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG) & 823 (PCI_BRIDGE_STATIO_STATUS_MASK << PCI_BRIDGE_STATIO_STATUS_SHIFT); 824 io |= (((io_base >> 8) & PCI_BRIDGE_STATIO_IOBASE_MASK) 825 << PCI_BRIDGE_STATIO_IOBASE_SHIFT); 826 io |= (((io_limit >> 8) & PCI_BRIDGE_STATIO_IOLIMIT_MASK) 827 << PCI_BRIDGE_STATIO_IOLIMIT_SHIFT); 828 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io); 829 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh); 830 831 /* Configure mem base & limit */ 832 if (pb->memext) { 833 mem_base = pb->memext->ex_start; 834 mem_limit = pb->memext->ex_end; 835 } else { 836 mem_base = 0x100000; /* 1M */ 837 mem_limit = 0x000000; 838 } 839 if (mem_limit > 0xFFFFFFFFULL) { 840 printf("Bus %d bridge MEM range out of range. ", pb->busno); 841 printf("Disabling MEM accesses\n"); 842 mem_base = 0x100000; /* 1M */ 843 mem_limit = 0x000000; 844 } 845 mem = (((mem_base >> 20) & PCI_BRIDGE_MEMORY_BASE_MASK) 846 << PCI_BRIDGE_MEMORY_BASE_SHIFT); 847 mem |= (((mem_limit >> 20) & PCI_BRIDGE_MEMORY_LIMIT_MASK) 848 << PCI_BRIDGE_MEMORY_LIMIT_SHIFT); 849 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem); 850 851 /* Configure prefetchable mem base & limit */ 852 if (pb->pmemext) { 853 mem_base = pb->pmemext->ex_start; 854 mem_limit = pb->pmemext->ex_end; 855 } else { 856 mem_base = 0x100000; /* 1M */ 857 mem_limit = 0x000000; 858 } 859 mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG); 860 if (!PCI_BRIDGE_PREFETCHMEM_64BITS(mem) && mem_limit > 0xFFFFFFFFULL) { 861 printf("Bus %d bridge does not support 64-bit PMEM. ", 862 pb->busno); 863 printf("Disabling prefetchable-MEM accesses\n"); 864 mem_base = 0x100000; /* 1M */ 865 mem_limit = 0x000000; 866 } 867 mem = (((mem_base >> 20) & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) 868 << PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT); 869 mem |= (((mem_limit >> 20) & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) 870 << PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT); 871 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem); 872 /* 873 * XXX -- 64-bit systems need a lot more than just this... 874 */ 875 if (sizeof(u_long) > 4) { 876 mem_base = (int64_t) mem_base >> 32; 877 mem_limit = (int64_t) mem_limit >> 32; 878 } 879 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHBASE32_REG, 880 mem_base & 0xffffffff); 881 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHLIMIT32_REG, 882 mem_limit & 0xffffffff); 883 884 rv = configure_bus(pb); 885 886 if (pb->ioext) 887 extent_destroy(pb->ioext); 888 if (pb->memext) 889 extent_destroy(pb->memext); 890 if (pb->pmemext) 891 extent_destroy(pb->pmemext); 892 if (rv == 0) { 893 cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG); 894 cmd &= PCI_BRIDGE_CONTROL_MASK; 895 cmd |= (PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR) 896 << PCI_BRIDGE_CONTROL_SHIFT; 897 if (pb->fast_b2b) { 898 cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B 899 << PCI_BRIDGE_CONTROL_SHIFT; 900 } 901 pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd); 902 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 903 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 904 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 905 } 906 907 return rv; 908 } 909 910 /* 911 * Calculate latency values, allocate I/O and MEM segments, then set them 912 * up. If a PCI-PCI bridge is found, configure the bridge separately, 913 * which will cause a recursive call back here. 914 */ 915 static int 916 configure_bus(pciconf_bus_t *pb) 917 { 918 pciconf_dev_t *pd; 919 int def_ltim, max_ltim, band, bus_mhz; 920 921 bus_mhz = pb->freq_66 ? 66 : 33; 922 max_ltim = pb->max_mingnt * bus_mhz / 4; /* cvt to cycle count */ 923 band = 40000000; /* 0.25us cycles/sec */ 924 if (band < pb->bandwidth_used) { 925 printf("PCI bus %d: Warning: Total bandwidth exceeded!?\n", 926 pb->busno); 927 def_ltim = -1; 928 } else { 929 def_ltim = (band - pb->bandwidth_used) / pb->ndevs; 930 if (def_ltim > pb->min_maxlat) 931 def_ltim = pb->min_maxlat; 932 def_ltim = def_ltim * bus_mhz / 4; 933 } 934 def_ltim = (def_ltim + 7) & ~7; 935 max_ltim = (max_ltim + 7) & ~7; 936 937 pb->def_ltim = MIN( def_ltim, 255 ); 938 pb->max_ltim = MIN( MAX(max_ltim, def_ltim ), 255 ); 939 940 /* 941 * Now we have what we need to initialize the devices. 942 * It would probably be better if we could allocate all of these 943 * for all busses at once, but "not right now". First, get a list 944 * of free memory ranges from the m.d. system. 945 */ 946 if (setup_iowins(pb) || setup_memwins(pb)) { 947 printf("PCI bus configuration failed: "); 948 printf("unable to assign all I/O and memory ranges."); 949 return -1; 950 } 951 952 /* 953 * Configure the latency for the devices, and enable them. 954 */ 955 for (pd=pb->device ; pd < &pb->device[pb->ndevs] ; pd++) { 956 pcireg_t cmd, class, misc; 957 int ltim; 958 959 if (pci_conf_debug) { 960 print_tag(pd->pc, pd->tag); 961 printf("Configuring device.\n"); 962 } 963 class = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG); 964 misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG); 965 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 966 cmd |= PCI_COMMAND_SERR_ENABLE | PCI_COMMAND_PARITY_ENABLE; 967 if (pb->fast_b2b) 968 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE; 969 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 970 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_PCI) { 971 if (pd->enable & PCI_CONF_ENABLE_IO) 972 cmd |= PCI_COMMAND_IO_ENABLE; 973 if (pd->enable & PCI_CONF_ENABLE_MEM) 974 cmd |= PCI_COMMAND_MEM_ENABLE; 975 if (pd->enable & PCI_CONF_ENABLE_BM) 976 cmd |= PCI_COMMAND_MASTER_ENABLE; 977 ltim = pd->min_gnt * bus_mhz / 4; 978 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim); 979 } else { 980 cmd |= PCI_COMMAND_MASTER_ENABLE; 981 ltim = MIN (pb->def_ltim, pb->max_ltim); 982 } 983 if (!(pd->enable)) { 984 print_tag(pd->pc, pd->tag); 985 printf("Disabled due to lack of resources.\n"); 986 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 987 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 988 } 989 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 990 991 misc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) | 992 (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)); 993 misc |= (ltim & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT; 994 misc |= ((pb->cacheline_size >> 2) & PCI_CACHELINE_MASK) << 995 PCI_CACHELINE_SHIFT; 996 pci_conf_write(pd->pc, pd->tag, PCI_BHLC_REG, misc); 997 998 if (pd->ppb) { 999 if (configure_bridge(pd) < 0) 1000 return -1; 1001 continue; 1002 } 1003 } 1004 1005 if (pci_conf_debug) { 1006 printf("PCI bus %d configured\n", pb->busno); 1007 } 1008 1009 return 0; 1010 } 1011 1012 /* 1013 * Let's configure the PCI bus. 1014 * This consists of basically scanning for all existing devices, 1015 * identifying their needs, and then making another pass over them 1016 * to set: 1017 * 1. I/O addresses 1018 * 2. Memory addresses (Prefetchable and not) 1019 * 3. PCI command register 1020 * 4. The latency part of the PCI BHLC (BIST (Built-In Self Test), 1021 * Header type, Latency timer, Cache line size) register 1022 * 1023 * The command register is set to enable fast back-to-back transactions 1024 * if the host bridge says it can handle it. We also configure 1025 * Master Enable, SERR enable, parity enable, and (if this is not a 1026 * PCI-PCI bridge) the I/O and Memory spaces. Apparently some devices 1027 * will not report some I/O space. 1028 * 1029 * The latency is computed to be a "fair share" of the bus bandwidth. 1030 * The bus bandwidth variable is initialized to the number of PCI cycles 1031 * in one second. The number of cycles taken for one transaction by each 1032 * device (MAX_LAT + MIN_GNT) is then subtracted from the bandwidth. 1033 * Care is taken to ensure that the latency timer won't be set such that 1034 * it would exceed the critical time for any device. 1035 * 1036 * This is complicated somewhat due to the presence of bridges. PCI-PCI 1037 * bridges are probed and configured recursively. 1038 */ 1039 int 1040 pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext, 1041 struct extent *memext, struct extent *pmemext, int firstbus, 1042 int cacheline_size) 1043 { 1044 pciconf_bus_t *pb; 1045 int rv; 1046 1047 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 1048 pb->busno = firstbus; 1049 pb->busno_spacing = PCI_BUSNO_SPACING; 1050 pb->next_busno = pb->busno + 1; 1051 pb->last_busno = 255; 1052 pb->cacheline_size = cacheline_size; 1053 pb->parent_bus = NULL; 1054 pb->swiz = 0; 1055 pb->io_32bit = 1; 1056 pb->pmem_64bit = 0; 1057 pb->ioext = ioext; 1058 pb->memext = memext; 1059 if (pmemext == NULL) { 1060 pb->pmemext = memext; 1061 } else { 1062 pb->pmemext = pmemext; 1063 } 1064 pb->pc = pc; 1065 pb->io_total = pb->mem_total = pb->pmem_total = 0; 1066 1067 rv = probe_bus(pb); 1068 if (rv == 0) { 1069 rv = configure_bus(pb); 1070 } 1071 1072 /* 1073 * All done! 1074 */ 1075 free(pb, M_DEVBUF); 1076 return rv; 1077 } 1078
Indexes created Fri Sep 26 20:09:58 GMT 2025