pciconf.c revision 1.17
1 /* $NetBSD: pciconf.c,v 1.17 2002/07/30 15:00:03 augustss Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Derived in part from code from PMON/2000 (http://pmon.groupbsd.org/). 39 */ 40 41 /* 42 * To do: 43 * - Perform all data structure allocation dynamically, don't have 44 * statically-sized arrays ("oops, you lose because you have too 45 * many slots filled!") 46 * - Do this in 2 passes, with an MD hook to control the behavior: 47 * (1) Configure the bus (possibly including expansion 48 * ROMs. 49 * (2) Another pass to disable expansion ROMs if they're 50 * mapped (since you're not supposed to leave them 51 * mapped when you're not using them). 52 * This would facilitate MD code executing the expansion ROMs 53 * if necessary (possibly with an x86 emulator) to configure 54 * devices (e.g. VGA cards). 55 * - Deal with "anything can be hot-plugged" -- i.e., carry configuration 56 * information around & be able to reconfigure on the fly 57 * - Deal with segments (See IA64 System Abstraction Layer) 58 * - Deal with subtractive bridges (& non-spec positive/subtractive decode) 59 * - Deal with ISA/VGA/VGA palette snooping 60 * - Deal with device capabilities on bridges 61 * - Worry about changing a bridge to/from transparency 62 * From thorpej (05/25/01) 63 * - Try to handle devices that are already configured (perhaps using that 64 * as a hint to where we put other devices) 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: pciconf.c,v 1.17 2002/07/30 15:00:03 augustss Exp $"); 69 70 #include "opt_pci.h" 71 72 #include <sys/param.h> 73 #include <sys/extent.h> 74 #include <sys/queue.h> 75 #include <sys/systm.h> 76 #include <sys/malloc.h> 77 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/pciconf.h> 80 #include <dev/pci/pcidevs.h> 81 82 int pci_conf_debug = 0; 83 84 #if !defined(MIN) 85 #define MIN(a,b) (((a)<(b))?(a):(b)) 86 #define MAX(a,b) (((a)>(b))?(a):(b)) 87 #endif 88 89 /* per-bus constants. */ 90 #define MAX_CONF_DEV 32 /* Arbitrary */ 91 #define MAX_CONF_MEM (3 * MAX_CONF_DEV) /* Avg. 3 per device -- Arb. */ 92 #define MAX_CONF_IO (3 * MAX_CONF_DEV) /* Avg. 1 per device -- Arb. */ 93 94 struct _s_pciconf_bus_t; /* Forward declaration */ 95 96 typedef struct _s_pciconf_dev_t { 97 int ipin; 98 int iline; 99 int min_gnt; 100 int max_lat; 101 int enable; 102 pcitag_t tag; 103 pci_chipset_tag_t pc; 104 struct _s_pciconf_bus_t *ppb; /* I am really a bridge */ 105 } pciconf_dev_t; 106 107 typedef struct _s_pciconf_win_t { 108 pciconf_dev_t *dev; 109 int reg; /* 0 for busses */ 110 int align; 111 int prefetch; 112 u_int64_t size; 113 u_int64_t address; 114 } pciconf_win_t; 115 116 typedef struct _s_pciconf_bus_t { 117 int busno; 118 int next_busno; 119 int last_busno; 120 int max_mingnt; 121 int min_maxlat; 122 int cacheline_size; 123 int prefetch; 124 int fast_b2b; 125 int freq_66; 126 int def_ltim; 127 int max_ltim; 128 int bandwidth_used; 129 int swiz; 130 int io_32bit; 131 int pmem_64bit; 132 133 int ndevs; 134 pciconf_dev_t device[MAX_CONF_DEV]; 135 136 /* These should be sorted in order of decreasing size */ 137 int nmemwin; 138 pciconf_win_t pcimemwin[MAX_CONF_MEM]; 139 int niowin; 140 pciconf_win_t pciiowin[MAX_CONF_IO]; 141 142 bus_size_t io_total; 143 bus_size_t mem_total; 144 bus_size_t pmem_total; 145 146 struct extent *ioext; 147 struct extent *memext; 148 struct extent *pmemext; 149 150 pci_chipset_tag_t pc; 151 struct _s_pciconf_bus_t *parent_bus; 152 } pciconf_bus_t; 153 154 static int probe_bus(pciconf_bus_t *); 155 static void alloc_busno(pciconf_bus_t *, pciconf_bus_t *); 156 static int pci_do_device_query(pciconf_bus_t *, pcitag_t, int, int, int); 157 static int setup_iowins(pciconf_bus_t *); 158 static int setup_memwins(pciconf_bus_t *); 159 static int configure_bridge(pciconf_dev_t *); 160 static int configure_bus(pciconf_bus_t *); 161 static u_int64_t pci_allocate_range(struct extent *, u_int64_t, int); 162 static pciconf_win_t *get_io_desc(pciconf_bus_t *, bus_size_t); 163 static pciconf_win_t *get_mem_desc(pciconf_bus_t *, bus_size_t); 164 static pciconf_bus_t *query_bus(pciconf_bus_t *, pciconf_dev_t *, int); 165 166 static void print_tag(pci_chipset_tag_t, pcitag_t); 167 168 static void 169 print_tag(pci_chipset_tag_t pc, pcitag_t tag) 170 { 171 int bus, dev, func; 172 173 pci_decompose_tag(pc, tag, &bus, &dev, &func); 174 printf("PCI: bus %d, device %d, function %d: ", bus, dev, func); 175 } 176 177 /************************************************************************/ 178 /************************************************************************/ 179 /*********************** Bus probing routines ***********************/ 180 /************************************************************************/ 181 /************************************************************************/ 182 static pciconf_win_t * 183 get_io_desc(pciconf_bus_t *pb, bus_size_t size) 184 { 185 int i, n; 186 187 n = pb->niowin; 188 for (i=n; i > 0 && size > pb->pciiowin[i-1].size; i--) 189 pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */ 190 return &pb->pciiowin[i]; 191 } 192 193 static pciconf_win_t * 194 get_mem_desc(pciconf_bus_t *pb, bus_size_t size) 195 { 196 int i, n; 197 198 n = pb->nmemwin; 199 for (i=n; i > 0 && size > pb->pcimemwin[i-1].size; i--) 200 pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */ 201 return &pb->pcimemwin[i]; 202 } 203 204 /* 205 * Set up bus common stuff, then loop over devices & functions. 206 * If we find something, call pci_do_device_query()). 207 */ 208 static int 209 probe_bus(pciconf_bus_t *pb) 210 { 211 int device, maxdevs; 212 #ifdef __PCI_BUS_DEVORDER 213 char devs[32]; 214 int i; 215 #endif 216 217 maxdevs = pci_bus_maxdevs(pb->pc, pb->busno); 218 pb->ndevs = 0; 219 pb->niowin = 0; 220 pb->nmemwin = 0; 221 pb->freq_66 = 1; 222 pb->fast_b2b = 1; 223 pb->prefetch = 1; 224 pb->max_mingnt = 0; /* we are looking for the maximum */ 225 pb->min_maxlat = 0x100; /* we are looking for the minimum */ 226 pb->bandwidth_used = 0; 227 228 #ifdef __PCI_BUS_DEVORDER 229 pci_bus_devorder(pb->pc, pb->busno, devs); 230 for (i=0; (device=devs[i]) < 32 && device >= 0; i++) { 231 #else 232 for (device=0; device < maxdevs; device++) { 233 #endif 234 pcitag_t tag; 235 pcireg_t id, bhlcr; 236 int function, nfunction; 237 int confmode; 238 239 tag = pci_make_tag(pb->pc, pb->busno, device, 0); 240 if (pci_conf_debug) { 241 print_tag(pb->pc, tag); 242 } 243 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 244 245 if (pci_conf_debug) { 246 printf("id=%x: Vendor=%x, Product=%x\n", 247 id, PCI_VENDOR(id),PCI_PRODUCT(id)); 248 } 249 /* Invalid vendor ID value? */ 250 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 251 continue; 252 253 bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 254 nfunction = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 255 for (function = 0 ; function < nfunction ; function++) { 256 tag = pci_make_tag(pb->pc, pb->busno, device, function); 257 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 258 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 259 continue; 260 if (pb->ndevs+1 < MAX_CONF_DEV) { 261 if (pci_conf_debug) { 262 print_tag(pb->pc, tag); 263 printf("Found dev 0x%04x 0x%04x -- " 264 "really probing.\n", 265 PCI_VENDOR(id), PCI_PRODUCT(id)); 266 } 267 #ifdef __HAVE_PCI_CONF_HOOK 268 confmode = pci_conf_hook(pb->pc, pb->busno, 269 device, function, id); 270 if (confmode == 0) 271 continue; 272 #else 273 /* 274 * Don't enable expansion ROMS -- some cards 275 * share address decoders between the EXPROM 276 * and PCI memory space, and enabling the ROM 277 * when not needed will cause all sorts of 278 * lossage. 279 */ 280 confmode = PCI_CONF_ALL & ~PCI_CONF_MAP_ROM; 281 #endif 282 if (pci_do_device_query(pb, tag, device, 283 function, confmode)) 284 return -1; 285 pb->ndevs++; 286 } 287 } 288 } 289 return 0; 290 } 291 292 static void 293 alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb) 294 { 295 pb->busno = parent->next_busno; 296 pb->next_busno = pb->busno + 1; 297 } 298 299 static void 300 set_busreg(pci_chipset_tag_t pc, pcitag_t tag, int prim, int sec, int sub) 301 { 302 pcireg_t busreg; 303 304 busreg = prim << PCI_BRIDGE_BUS_PRIMARY_SHIFT; 305 busreg |= sec << PCI_BRIDGE_BUS_SECONDARY_SHIFT; 306 busreg |= sub << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 307 pci_conf_write(pc, tag, PCI_BRIDGE_BUS_REG, busreg); 308 } 309 310 static pciconf_bus_t * 311 query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev) 312 { 313 pciconf_bus_t *pb; 314 pcireg_t io, pmem; 315 pciconf_win_t *pi, *pm; 316 317 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 318 if (!pb) 319 panic("Unable to allocate memory for PCI configuration."); 320 321 pb->cacheline_size = parent->cacheline_size; 322 pb->parent_bus = parent; 323 alloc_busno(parent, pb); 324 325 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 0xff); 326 327 pb->swiz = parent->swiz + dev; 328 329 pb->ioext = NULL; 330 pb->memext = NULL; 331 pb->pmemext = NULL; 332 pb->pc = parent->pc; 333 pb->io_total = pb->mem_total = pb->pmem_total = 0; 334 335 pb->io_32bit = 0; 336 if (parent->io_32bit) { 337 io = pci_conf_read(parent->pc, pd->tag, PCI_BRIDGE_STATIO_REG); 338 if (PCI_BRIDGE_IO_32BITS(io)) { 339 pb->io_32bit = 1; 340 } 341 } 342 343 pb->pmem_64bit = 0; 344 if (parent->pmem_64bit) { 345 pmem = pci_conf_read(parent->pc, pd->tag, 346 PCI_BRIDGE_PREFETCHMEM_REG); 347 if (PCI_BRIDGE_PREFETCHMEM_64BITS(pmem)) { 348 pb->pmem_64bit = 1; 349 } 350 } 351 352 if (probe_bus(pb)) { 353 printf("Failed to probe bus %d\n", pb->busno); 354 goto err; 355 } 356 357 /* We have found all subordinate busses now, reprogram busreg. */ 358 pb->last_busno = pb->next_busno-1; 359 parent->next_busno = pb->next_busno; 360 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 361 pb->last_busno); 362 if (pci_conf_debug) 363 printf("PCI bus bridge (parent %d) covers busses %d-%d\n", 364 parent->busno, pb->busno, pb->last_busno); 365 366 if (pb->io_total > 0) { 367 if (parent->niowin >= MAX_CONF_IO) { 368 printf("pciconf: too many I/O windows\n"); 369 goto err; 370 } 371 pb->io_total |= 0xfff; /* Round up */ 372 pi = get_io_desc(parent, pb->io_total); 373 pi->dev = pd; 374 pi->reg = 0; 375 pi->size = pb->io_total; 376 pi->align = 0x1000; /* 4K alignment */ 377 pi->prefetch = 0; 378 parent->niowin++; 379 parent->io_total += pb->io_total; 380 } 381 382 if (pb->mem_total > 0) { 383 if (parent->nmemwin >= MAX_CONF_MEM) { 384 printf("pciconf: too many MEM windows\n"); 385 goto err; 386 } 387 pb->mem_total |= 0xfffff; /* Round up */ 388 pm = get_mem_desc(parent, pb->mem_total); 389 pm->dev = pd; 390 pm->reg = 0; 391 pm->size = pb->mem_total; 392 pm->align = 0x100000; /* 1M alignment */ 393 pm->prefetch = 0; 394 parent->nmemwin++; 395 parent->mem_total += pb->mem_total; 396 } 397 398 if (pb->pmem_total > 0) { 399 if (parent->nmemwin >= MAX_CONF_MEM) { 400 printf("pciconf: too many MEM windows\n"); 401 goto err; 402 } 403 pb->pmem_total |= 0xfffff; /* Round up */ 404 pm = get_mem_desc(parent, pb->pmem_total); 405 pm->dev = pd; 406 pm->reg = 0; 407 pm->size = pb->pmem_total; 408 pm->align = 0x100000; /* 1M alignment */ 409 pm->prefetch = 1; 410 parent->nmemwin++; 411 parent->pmem_total += pb->pmem_total; 412 } 413 414 return pb; 415 err: 416 free(pb, M_DEVBUF); 417 return NULL; 418 } 419 420 static int 421 pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func, int mode) 422 { 423 pciconf_dev_t *pd; 424 pciconf_win_t *pi, *pm; 425 pcireg_t class, cmd, icr, bar, mask, bar64, mask64; 426 u_int64_t size; 427 int br, width; 428 429 pd = &pb->device[pb->ndevs]; 430 pd->pc = pb->pc; 431 pd->tag = tag; 432 pd->ppb = NULL; 433 pd->enable = mode; 434 435 class = pci_conf_read(pb->pc, tag, PCI_CLASS_REG); 436 437 cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG); 438 439 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE) { 440 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 441 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 442 pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd); 443 } else if (pci_conf_debug) { 444 print_tag(pb->pc, tag); 445 printf("device is a bridge; not clearing enables\n"); 446 } 447 448 if ((cmd & PCI_STATUS_BACKTOBACK_SUPPORT) == 0) 449 pb->fast_b2b = 0; 450 451 if ((cmd & PCI_STATUS_66MHZ_SUPPORT) == 0) 452 pb->freq_66 = 0; 453 454 if ( (PCI_CLASS(class) == PCI_CLASS_BRIDGE) 455 && (PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_PCI)) { 456 pd->ppb = query_bus(pb, pd, dev); 457 if (pd->ppb == NULL) 458 return -1; 459 return 0; 460 } 461 462 icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG); 463 pd->ipin = PCI_INTERRUPT_PIN(icr); 464 pd->iline = PCI_INTERRUPT_LINE(icr); 465 pd->min_gnt = PCI_MIN_GNT(icr); 466 pd->max_lat = PCI_MAX_LAT(icr); 467 if (pd->iline || pd->ipin) { 468 pci_conf_interrupt(pb->pc, pb->busno, dev, pd->ipin, pb->swiz, 469 &pd->iline); 470 icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 471 icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT); 472 pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr); 473 } 474 475 if (pd->min_gnt != 0 || pd->max_lat != 0) { 476 if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt) 477 pb->max_mingnt = pd->min_gnt; 478 479 if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat) 480 pb->min_maxlat = pd->max_lat; 481 482 pb->bandwidth_used += pd->min_gnt * 4000000 / 483 (pd->min_gnt + pd->max_lat); 484 } 485 486 width = 4; 487 for (br = PCI_MAPREG_START; br < PCI_MAPREG_END; br += width) { 488 #if 0 489 /* XXX Should only ignore if IDE not in legacy mode? */ 490 if (PCI_CLASS(class) == PCI_CLASS_MASS_STORAGE && 491 PCI_SUBCLASS(class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 492 break; 493 } 494 #endif 495 bar = pci_conf_read(pb->pc, tag, br); 496 pci_conf_write(pb->pc, tag, br, 0xffffffff); 497 mask = pci_conf_read(pb->pc, tag, br); 498 pci_conf_write(pb->pc, tag, br, bar); 499 width = 4; 500 501 if ( (mode & PCI_CONF_MAP_IO) 502 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO)) { 503 /* 504 * Upper 16 bits must be one. Devices may hardwire 505 * them to zero, though, per PCI 2.2, 6.2.5.1, p 203. 506 */ 507 mask |= 0xffff0000; 508 509 size = PCI_MAPREG_IO_SIZE(mask); 510 if (size == 0) { 511 if (pci_conf_debug) { 512 print_tag(pb->pc, tag); 513 printf("I/O BAR 0x%x is void\n", br); 514 } 515 continue; 516 } 517 518 if (pb->niowin >= MAX_CONF_IO) { 519 printf("pciconf: too many I/O windows\n"); 520 return -1; 521 } 522 523 pi = get_io_desc(pb, size); 524 pi->dev = pd; 525 pi->reg = br; 526 pi->size = (u_int64_t) size; 527 pi->align = 4; 528 pi->prefetch = 0; 529 if (pci_conf_debug) { 530 print_tag(pb->pc, tag); 531 printf("Register 0x%x, I/O size %llu\n", 532 br, pi->size); 533 } 534 pb->niowin++; 535 pb->io_total += size; 536 } else if ((mode & PCI_CONF_MAP_MEM) 537 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_MEM)) { 538 switch (PCI_MAPREG_MEM_TYPE(mask)) { 539 case PCI_MAPREG_MEM_TYPE_32BIT: 540 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 541 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 542 break; 543 case PCI_MAPREG_MEM_TYPE_64BIT: 544 bar64 = pci_conf_read(pb->pc, tag, br + 4); 545 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); 546 mask64 = pci_conf_read(pb->pc, tag, br + 4); 547 pci_conf_write(pb->pc, tag, br + 4, bar64); 548 size = (u_int64_t) PCI_MAPREG_MEM64_SIZE( 549 (((u_int64_t) mask64) << 32) | mask); 550 width = 8; 551 break; 552 default: 553 print_tag(pb->pc, tag); 554 printf("reserved mapping type 0x%x\n", 555 PCI_MAPREG_MEM_TYPE(mask)); 556 continue; 557 } 558 559 if (size == 0) { 560 if (pci_conf_debug) { 561 print_tag(pb->pc, tag); 562 printf("MEM%d BAR 0x%x is void\n", 563 PCI_MAPREG_MEM_TYPE(mask) == 564 PCI_MAPREG_MEM_TYPE_64BIT ? 565 64 : 32, br); 566 } 567 continue; 568 } else { 569 if (pci_conf_debug) { 570 print_tag(pb->pc, tag); 571 printf("MEM%d BAR 0x%x has size %lx\n", 572 PCI_MAPREG_MEM_TYPE(mask) == 573 PCI_MAPREG_MEM_TYPE_64BIT ? 574 64 : 32, br, (unsigned long)size); 575 } 576 } 577 578 if (pb->nmemwin >= MAX_CONF_MEM) { 579 printf("pciconf: too many memory windows\n"); 580 return -1; 581 } 582 583 pm = get_mem_desc(pb, size); 584 pm->dev = pd; 585 pm->reg = br; 586 pm->size = size; 587 pm->align = 4; 588 pm->prefetch = PCI_MAPREG_MEM_PREFETCHABLE(mask); 589 if (pci_conf_debug) { 590 print_tag(pb->pc, tag); 591 printf("Register 0x%x, memory size %llu\n", 592 br, pm->size); 593 } 594 pb->nmemwin++; 595 if (pm->prefetch) { 596 pb->pmem_total += size; 597 } else { 598 pb->mem_total += size; 599 } 600 } 601 } 602 603 if (mode & PCI_CONF_MAP_ROM) { 604 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 605 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 606 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 607 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, bar); 608 609 if (mask != 0 && mask != 0xffffffff) { 610 if (pb->nmemwin >= MAX_CONF_MEM) { 611 printf("pciconf: too many memory windows\n"); 612 return -1; 613 } 614 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 615 616 pm = get_mem_desc(pb, size); 617 pm->dev = pd; 618 pm->reg = PCI_MAPREG_ROM; 619 pm->size = size; 620 pm->align = 4; 621 pm->prefetch = 1; 622 if (pci_conf_debug) { 623 print_tag(pb->pc, tag); 624 printf("Expansion ROM memory size %llu\n", pm->size); 625 } 626 pb->nmemwin++; 627 pb->pmem_total += size; 628 } 629 } else { 630 /* Ensure ROM is disabled */ 631 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 632 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 633 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 634 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 635 bar & ~PCI_MAPREG_ROM_ENABLE); 636 } 637 638 return 0; 639 } 640 641 /************************************************************************/ 642 /************************************************************************/ 643 /******************** Bus configuration routines ********************/ 644 /************************************************************************/ 645 /************************************************************************/ 646 static u_int64_t 647 pci_allocate_range(struct extent *ex, u_int64_t amt, int align) 648 { 649 int r; 650 u_long addr; 651 652 r = extent_alloc(ex, amt, align, 0, EX_NOWAIT, &addr); 653 if (r) { 654 addr = (u_long) -1; 655 printf("extent_alloc(%p, %llu, %d) returned %d\n", 656 ex, amt, align, r); 657 extent_print(ex); 658 } 659 return (pcireg_t) addr; 660 } 661 662 static int 663 setup_iowins(pciconf_bus_t *pb) 664 { 665 pciconf_win_t *pi; 666 pciconf_dev_t *pd; 667 668 for (pi=pb->pciiowin; pi < &pb->pciiowin[pb->niowin] ; pi++) { 669 if (pi->size == 0) 670 continue; 671 672 pd = pi->dev; 673 pi->address = pci_allocate_range(pb->ioext, pi->size, 674 pi->align); 675 if (pi->address == -1) { 676 print_tag(pd->pc, pd->tag); 677 printf("Failed to allocate PCI I/O space (%llu req)\n", 678 pi->size); 679 return -1; 680 } 681 if (!pb->io_32bit && pi->address > 0xFFFF) { 682 pi->address = 0; 683 pd->enable = 0; 684 } 685 if (pd->ppb && pi->reg == 0) { 686 pd->ppb->ioext = extent_create("pciconf", pi->address, 687 pi->address + pi->size, M_DEVBUF, NULL, 0, 688 EX_NOWAIT); 689 if (pd->ppb->ioext == NULL) { 690 print_tag(pd->pc, pd->tag); 691 printf("Failed to alloc I/O ext. for bus %d\n", 692 pd->ppb->busno); 693 return -1; 694 } 695 continue; 696 } 697 pd->enable |= PCI_CONF_ENABLE_IO; 698 if (pci_conf_debug) { 699 print_tag(pd->pc, pd->tag); 700 printf("Putting %llu I/O bytes @ %#llx (reg %x)\n", 701 pi->size, pi->address, pi->reg); 702 } 703 pci_conf_write(pd->pc, pd->tag, pi->reg, 704 PCI_MAPREG_IO_ADDR(pi->address) | PCI_MAPREG_TYPE_IO); 705 } 706 return 0; 707 } 708 709 static int 710 setup_memwins(pciconf_bus_t *pb) 711 { 712 pciconf_win_t *pm; 713 pciconf_dev_t *pd; 714 pcireg_t base; 715 struct extent *ex; 716 717 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 718 if (pm->size == 0) 719 continue; 720 721 pd = pm->dev; 722 ex = (pm->prefetch) ? pb->pmemext : pb->memext; 723 pm->address = pci_allocate_range(ex, pm->size, pm->align); 724 if (pm->address == -1) { 725 print_tag(pd->pc, pd->tag); 726 printf( 727 "Failed to allocate PCI memory space (%llu req)\n", 728 pm->size); 729 return -1; 730 } 731 if (pd->ppb && pm->reg == 0) { 732 ex = extent_create("pciconf", pm->address, 733 pm->address + pm->size, M_DEVBUF, NULL, 0, 734 EX_NOWAIT); 735 if (ex == NULL) { 736 print_tag(pd->pc, pd->tag); 737 printf("Failed to alloc MEM ext. for bus %d\n", 738 pd->ppb->busno); 739 return -1; 740 } 741 if (pm->prefetch) { 742 pd->ppb->pmemext = ex; 743 } else { 744 pd->ppb->memext = ex; 745 } 746 continue; 747 } 748 if (pm->prefetch && !pb->pmem_64bit && 749 pm->address > 0xFFFFFFFFULL) { 750 pm->address = 0; 751 pd->enable = 0; 752 } else { 753 pd->enable |= PCI_CONF_ENABLE_MEM; 754 } 755 if (pm->reg != PCI_MAPREG_ROM) { 756 if (pci_conf_debug) { 757 print_tag(pd->pc, pd->tag); 758 printf( 759 "Putting %llu MEM bytes @ %#llx (reg %x)\n", 760 pm->size, pm->address, pm->reg); 761 } 762 base = pci_conf_read(pd->pc, pd->tag, pm->reg); 763 base = PCI_MAPREG_MEM_ADDR(pm->address) | 764 PCI_MAPREG_MEM_TYPE(base); 765 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 766 if (PCI_MAPREG_MEM_TYPE(base) == 767 PCI_MAPREG_MEM_TYPE_64BIT) { 768 base = (pcireg_t) 769 (PCI_MAPREG_MEM64_ADDR(pm->address) >> 32); 770 pci_conf_write(pd->pc, pd->tag, pm->reg + 4, 771 base); 772 } 773 } 774 } 775 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 776 if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) { 777 pd = pm->dev; 778 if (pci_conf_debug) { 779 print_tag(pd->pc, pd->tag); 780 printf( 781 "Putting %llu ROM bytes @ %#llx (reg %x)\n", 782 pm->size, pm->address, pm->reg); 783 } 784 base = (pcireg_t) (pm->address | PCI_MAPREG_ROM_ENABLE); 785 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 786 } 787 } 788 return 0; 789 } 790 791 /* 792 * Configure I/O, memory, and prefetcable memory spaces, then make 793 * a call to configure_bus(). 794 */ 795 static int 796 configure_bridge(pciconf_dev_t *pd) 797 { 798 unsigned long io_base, io_limit, mem_base, mem_limit; 799 pciconf_bus_t *pb; 800 pcireg_t io, iohigh, mem, cmd; 801 int rv; 802 803 pb = pd->ppb; 804 /* Configure I/O base & limit*/ 805 if (pb->ioext) { 806 io_base = pb->ioext->ex_start; 807 io_limit = pb->ioext->ex_end; 808 } else { 809 io_base = 0x1000; /* 4K */ 810 io_limit = 0x0000; 811 } 812 if (pb->io_32bit) { 813 iohigh = 814 ((io_base >> 16) << PCI_BRIDGE_IOHIGH_BASE_SHIFT) | 815 ((io_limit >> 16) << PCI_BRIDGE_IOHIGH_LIMIT_SHIFT); 816 } else { 817 if (io_limit > 0xFFFF) { 818 printf("Bus %d bridge does not support 32-bit I/O. ", 819 pb->busno); 820 printf("Disabling I/O accesses\n"); 821 io_base = 0x1000; /* 4K */ 822 io_limit = 0x0000; 823 } 824 iohigh = 0; 825 } 826 io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG) & 827 (PCI_BRIDGE_STATIO_STATUS_MASK << PCI_BRIDGE_STATIO_STATUS_SHIFT); 828 io |= (((io_base >> 8) & PCI_BRIDGE_STATIO_IOBASE_MASK) 829 << PCI_BRIDGE_STATIO_IOBASE_SHIFT); 830 io |= (((io_limit >> 8) & PCI_BRIDGE_STATIO_IOLIMIT_MASK) 831 << PCI_BRIDGE_STATIO_IOLIMIT_SHIFT); 832 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io); 833 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh); 834 835 /* Configure mem base & limit */ 836 if (pb->memext) { 837 mem_base = pb->memext->ex_start; 838 mem_limit = pb->memext->ex_end; 839 } else { 840 mem_base = 0x100000; /* 1M */ 841 mem_limit = 0x000000; 842 } 843 if (mem_limit > 0xFFFFFFFFULL) { 844 printf("Bus %d bridge MEM range out of range. ", pb->busno); 845 printf("Disabling MEM accesses\n"); 846 mem_base = 0x100000; /* 1M */ 847 mem_limit = 0x000000; 848 } 849 mem = (((mem_base >> 20) & PCI_BRIDGE_MEMORY_BASE_MASK) 850 << PCI_BRIDGE_MEMORY_BASE_SHIFT); 851 mem |= (((mem_limit >> 20) & PCI_BRIDGE_MEMORY_LIMIT_MASK) 852 << PCI_BRIDGE_MEMORY_LIMIT_SHIFT); 853 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem); 854 855 /* Configure prefetchable mem base & limit */ 856 if (pb->pmemext) { 857 mem_base = pb->pmemext->ex_start; 858 mem_limit = pb->pmemext->ex_end; 859 } else { 860 mem_base = 0x100000; /* 1M */ 861 mem_limit = 0x000000; 862 } 863 mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG); 864 if (!PCI_BRIDGE_PREFETCHMEM_64BITS(mem) && mem_limit > 0xFFFFFFFFULL) { 865 printf("Bus %d bridge does not support 64-bit PMEM. ", 866 pb->busno); 867 printf("Disabling prefetchable-MEM accesses\n"); 868 mem_base = 0x100000; /* 1M */ 869 mem_limit = 0x000000; 870 } 871 mem = (((mem_base >> 20) & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) 872 << PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT); 873 mem |= (((mem_limit >> 20) & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) 874 << PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT); 875 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem); 876 /* 877 * XXX -- 64-bit systems need a lot more than just this... 878 */ 879 if (sizeof(u_long) > 4) { 880 mem_base = (int64_t) mem_base >> 32; 881 mem_limit = (int64_t) mem_limit >> 32; 882 } 883 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHBASE32_REG, 884 mem_base & 0xffffffff); 885 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHLIMIT32_REG, 886 mem_limit & 0xffffffff); 887 888 rv = configure_bus(pb); 889 890 if (pb->ioext) 891 extent_destroy(pb->ioext); 892 if (pb->memext) 893 extent_destroy(pb->memext); 894 if (pb->pmemext) 895 extent_destroy(pb->pmemext); 896 if (rv == 0) { 897 cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG); 898 cmd &= PCI_BRIDGE_CONTROL_MASK; 899 cmd |= (PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR) 900 << PCI_BRIDGE_CONTROL_SHIFT; 901 if (pb->fast_b2b) { 902 cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B 903 << PCI_BRIDGE_CONTROL_SHIFT; 904 } 905 pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd); 906 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 907 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 908 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 909 } 910 911 return rv; 912 } 913 914 /* 915 * Calculate latency values, allocate I/O and MEM segments, then set them 916 * up. If a PCI-PCI bridge is found, configure the bridge separately, 917 * which will cause a recursive call back here. 918 */ 919 static int 920 configure_bus(pciconf_bus_t *pb) 921 { 922 pciconf_dev_t *pd; 923 int def_ltim, max_ltim, band, bus_mhz; 924 925 bus_mhz = pb->freq_66 ? 66 : 33; 926 max_ltim = pb->max_mingnt * bus_mhz / 4; /* cvt to cycle count */ 927 band = 40000000; /* 0.25us cycles/sec */ 928 if (band < pb->bandwidth_used) { 929 printf("PCI bus %d: Warning: Total bandwidth exceeded!?\n", 930 pb->busno); 931 def_ltim = -1; 932 } else { 933 def_ltim = (band - pb->bandwidth_used) / pb->ndevs; 934 if (def_ltim > pb->min_maxlat) 935 def_ltim = pb->min_maxlat; 936 def_ltim = def_ltim * bus_mhz / 4; 937 } 938 def_ltim = (def_ltim + 7) & ~7; 939 max_ltim = (max_ltim + 7) & ~7; 940 941 pb->def_ltim = MIN( def_ltim, 255 ); 942 pb->max_ltim = MIN( MAX(max_ltim, def_ltim ), 255 ); 943 944 /* 945 * Now we have what we need to initialize the devices. 946 * It would probably be better if we could allocate all of these 947 * for all busses at once, but "not right now". First, get a list 948 * of free memory ranges from the m.d. system. 949 */ 950 if (setup_iowins(pb) || setup_memwins(pb)) { 951 printf("PCI bus configuration failed: "); 952 printf("unable to assign all I/O and memory ranges."); 953 return -1; 954 } 955 956 /* 957 * Configure the latency for the devices, and enable them. 958 */ 959 for (pd=pb->device ; pd < &pb->device[pb->ndevs] ; pd++) { 960 pcireg_t cmd, class, misc; 961 int ltim; 962 963 if (pci_conf_debug) { 964 print_tag(pd->pc, pd->tag); 965 printf("Configuring device.\n"); 966 } 967 class = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG); 968 misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG); 969 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 970 cmd |= PCI_COMMAND_SERR_ENABLE | PCI_COMMAND_PARITY_ENABLE; 971 if (pb->fast_b2b) 972 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE; 973 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 974 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_PCI) { 975 if (pd->enable & PCI_CONF_ENABLE_IO) 976 cmd |= PCI_COMMAND_IO_ENABLE; 977 if (pd->enable & PCI_CONF_ENABLE_MEM) 978 cmd |= PCI_COMMAND_MEM_ENABLE; 979 if (pd->enable & PCI_CONF_ENABLE_BM) 980 cmd |= PCI_COMMAND_MASTER_ENABLE; 981 ltim = pd->min_gnt * bus_mhz / 4; 982 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim); 983 } else { 984 cmd |= PCI_COMMAND_MASTER_ENABLE; 985 ltim = MIN (pb->def_ltim, pb->max_ltim); 986 } 987 if (!(pd->enable)) { 988 print_tag(pd->pc, pd->tag); 989 printf("Disabled due to lack of resources.\n"); 990 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 991 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 992 } 993 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 994 995 misc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) | 996 (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)); 997 misc |= (ltim & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT; 998 misc |= ((pb->cacheline_size >> 2) & PCI_CACHELINE_MASK) << 999 PCI_CACHELINE_SHIFT; 1000 pci_conf_write(pd->pc, pd->tag, PCI_BHLC_REG, misc); 1001 1002 if (pd->ppb) { 1003 if (configure_bridge(pd) < 0) 1004 return -1; 1005 continue; 1006 } 1007 } 1008 1009 if (pci_conf_debug) { 1010 printf("PCI bus %d configured\n", pb->busno); 1011 } 1012 1013 return 0; 1014 } 1015 1016 /* 1017 * Let's configure the PCI bus. 1018 * This consists of basically scanning for all existing devices, 1019 * identifying their needs, and then making another pass over them 1020 * to set: 1021 * 1. I/O addresses 1022 * 2. Memory addresses (Prefetchable and not) 1023 * 3. PCI command register 1024 * 4. The latency part of the PCI BHLC (BIST (Built-In Self Test), 1025 * Header type, Latency timer, Cache line size) register 1026 * 1027 * The command register is set to enable fast back-to-back transactions 1028 * if the host bridge says it can handle it. We also configure 1029 * Master Enable, SERR enable, parity enable, and (if this is not a 1030 * PCI-PCI bridge) the I/O and Memory spaces. Apparently some devices 1031 * will not report some I/O space. 1032 * 1033 * The latency is computed to be a "fair share" of the bus bandwidth. 1034 * The bus bandwidth variable is initialized to the number of PCI cycles 1035 * in one second. The number of cycles taken for one transaction by each 1036 * device (MAX_LAT + MIN_GNT) is then subtracted from the bandwidth. 1037 * Care is taken to ensure that the latency timer won't be set such that 1038 * it would exceed the critical time for any device. 1039 * 1040 * This is complicated somewhat due to the presence of bridges. PCI-PCI 1041 * bridges are probed and configured recursively. 1042 */ 1043 int 1044 pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext, 1045 struct extent *memext, struct extent *pmemext, int firstbus, 1046 int cacheline_size) 1047 { 1048 pciconf_bus_t *pb; 1049 int rv; 1050 1051 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 1052 pb->busno = firstbus; 1053 pb->next_busno = pb->busno + 1; 1054 pb->last_busno = 255; 1055 pb->cacheline_size = cacheline_size; 1056 pb->parent_bus = NULL; 1057 pb->swiz = 0; 1058 pb->io_32bit = 1; 1059 pb->pmem_64bit = 0; 1060 pb->ioext = ioext; 1061 pb->memext = memext; 1062 if (pmemext == NULL) { 1063 pb->pmemext = memext; 1064 } else { 1065 pb->pmemext = pmemext; 1066 } 1067 pb->pc = pc; 1068 pb->io_total = pb->mem_total = pb->pmem_total = 0; 1069 1070 rv = probe_bus(pb); 1071 pb->last_busno = pb->next_busno-1; 1072 if (rv == 0) { 1073 rv = configure_bus(pb); 1074 } 1075 1076 /* 1077 * All done! 1078 */ 1079 free(pb, M_DEVBUF); 1080 return rv; 1081 } 1082
Indexes created Fri Sep 26 20:09:58 GMT 2025