pciconf.c revision 1.2
1 /* $NetBSD: pciconf.c,v 1.2 2001/02/12 06:24:24 briggs Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Derived in part from code from PMON/2000 (http://pmon.groupbsd.org/). 39 */ 40 41 /* 42 * To do: 43 * - Deal with "anything can be hot-plugged" -- i.e., carry configuration 44 * information around & be able to reconfigure on the fly. 45 * - Deal with segments (See IA64 System Abstraction Layer) 46 * - Deal with subtractive bridges (& non-spec positive/subtractive decode) 47 * - Deal with ISA/VGA/VGA palette snooping 48 * - Deal with device capabilities on bridges 49 * - Worry about changing a bridge to/from transparency. 50 */ 51 52 #include "opt_pci.h" 53 54 #include <sys/param.h> 55 #include <sys/extent.h> 56 #include <sys/queue.h> 57 #include <sys/systm.h> 58 #include <sys/malloc.h> 59 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pciconf.h> 62 #include <dev/pci/pcidevs.h> 63 64 int pci_conf_debug = 0; 65 66 #if !defined(MIN) 67 #define MIN(a,b) (((a)<(b))?(a):(b)) 68 #define MAX(a,b) (((a)>(b))?(a):(b)) 69 #endif 70 71 /* per-bus constants. */ 72 #define MAX_CONF_DEV 8 /* Arbitrary */ 73 #define MAX_CONF_MEM (3 * MAX_CONF_DEV) /* Avg. 3 per device -- Arb. */ 74 #define MAX_CONF_IO (1 * MAX_CONF_DEV) /* Avg. 1 per device -- Arb. */ 75 76 #define PCI_BUSNO_SPACING (1 << 5) 77 78 struct _s_pciconf_bus_t; /* Forward declaration */ 79 80 typedef struct _s_pciconf_dev_t { 81 int ipin; 82 int iline; 83 int min_gnt; 84 int max_lat; 85 int enable; 86 pcitag_t tag; 87 pci_chipset_tag_t pc; 88 struct _s_pciconf_bus_t *ppb; /* I am really a bridge */ 89 } pciconf_dev_t; 90 91 typedef struct _s_pciconf_win_t { 92 pciconf_dev_t *dev; 93 int reg; /* 0 for busses */ 94 int align; 95 int prefetch; 96 u_int64_t size; 97 u_int64_t address; 98 } pciconf_win_t; 99 100 typedef struct _s_pciconf_bus_t { 101 int busno; 102 int next_busno; 103 int last_busno; 104 int busno_spacing; 105 int max_mingnt; 106 int min_maxlat; 107 int prefetch; 108 int fast_b2b; 109 int freq_66; 110 int def_ltim; 111 int max_ltim; 112 int bandwidth_used; 113 int swiz; 114 int io_32bit; 115 int pmem_64bit; 116 117 int ndevs; 118 pciconf_dev_t device[MAX_CONF_DEV]; 119 120 /* These should be sorted in order of decreasing size */ 121 int nmemwin; 122 pciconf_win_t pcimemwin[MAX_CONF_MEM]; 123 int niowin; 124 pciconf_win_t pciiowin[MAX_CONF_IO]; 125 126 bus_size_t io_total; 127 bus_size_t mem_total; 128 bus_size_t pmem_total; 129 130 struct extent *ioext; 131 struct extent *memext; 132 struct extent *pmemext; 133 134 pci_chipset_tag_t pc; 135 struct _s_pciconf_bus_t *parent_bus; 136 } pciconf_bus_t; 137 138 static int probe_bus(pciconf_bus_t *); 139 static void alloc_busno(pciconf_bus_t *, pciconf_bus_t *); 140 static int pci_do_device_query(pciconf_bus_t *, pcitag_t, int, int); 141 static int setup_iowins(pciconf_bus_t *); 142 static int setup_memwins(pciconf_bus_t *); 143 static int configure_bridge(pciconf_dev_t *); 144 static int configure_bus(pciconf_bus_t *); 145 static u_int64_t pci_allocate_range(struct extent *, u_int64_t, int); 146 static pciconf_win_t *get_io_desc(pciconf_bus_t *, bus_size_t); 147 static pciconf_win_t *get_mem_desc(pciconf_bus_t *, bus_size_t); 148 static pciconf_bus_t *query_bus(pciconf_bus_t *, pciconf_dev_t *, int); 149 150 static void print_tag(pci_chipset_tag_t, pcitag_t); 151 152 static void 153 print_tag(pci_chipset_tag_t pc, pcitag_t tag) 154 { 155 int bus, dev, func; 156 157 pci_decompose_tag(pc, tag, &bus, &dev, &func); 158 printf("PCI: bus %d, device %d, function %d: ", bus, dev, func); 159 } 160 161 /************************************************************************/ 162 /************************************************************************/ 163 /*********************** Bus probing routines ***********************/ 164 /************************************************************************/ 165 /************************************************************************/ 166 static pciconf_win_t * 167 get_io_desc(pciconf_bus_t *pb, bus_size_t size) 168 { 169 int i, n; 170 171 n = pb->niowin; 172 for (i=n; i > 0 && size > pb->pciiowin[i-1].size; i--) 173 pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */ 174 return &pb->pciiowin[i]; 175 } 176 177 static pciconf_win_t * 178 get_mem_desc(pciconf_bus_t *pb, bus_size_t size) 179 { 180 int i, n; 181 182 n = pb->nmemwin; 183 for (i=n; i > 0 && size > pb->pcimemwin[i-1].size; i--) 184 pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */ 185 return &pb->pcimemwin[i]; 186 } 187 188 /* 189 * Set up bus common stuff, then loop over devices & functions. 190 * If we find something, call pci_do_device_query()). 191 */ 192 static int 193 probe_bus(pciconf_bus_t *pb) 194 { 195 int device, maxdevs; 196 197 maxdevs = pci_bus_maxdevs(pb->pc, pb->busno); 198 pb->ndevs = 0; 199 pb->niowin = 0; 200 pb->nmemwin = 0; 201 pb->freq_66 = 1; 202 pb->fast_b2b = 1; 203 pb->prefetch = 1; 204 pb->max_mingnt = 0; /* we are looking for the maximum */ 205 pb->min_maxlat = 0x100; /* we are looking for the minimum */ 206 pb->bandwidth_used = 0; 207 for (device=0; device < maxdevs; device++) { 208 pcitag_t tag; 209 pcireg_t id, bhlcr; 210 int function, nfunction; 211 212 tag = pci_make_tag(pb->pc, pb->busno, device, 0); 213 if (pci_conf_debug) { 214 print_tag(pb->pc, tag); 215 printf("probing.\n"); 216 } 217 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 218 219 /* Invalid vendor ID value? */ 220 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 221 continue; 222 223 bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 224 nfunction = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 225 for (function = 0 ; function < nfunction ; function++) { 226 tag = pci_make_tag(pb->pc, pb->busno, device, function); 227 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 228 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 229 continue; 230 if (pb->ndevs+1 < MAX_CONF_DEV) { 231 if (pci_conf_debug) { 232 print_tag(pb->pc, tag); 233 printf("Found dev--really probing.\n"); 234 } 235 if (pci_do_device_query(pb, tag, device, 236 function)) 237 return -1; 238 pb->ndevs++; 239 } 240 } 241 } 242 return 0; 243 } 244 245 static void 246 alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb) 247 { 248 pb->busno = parent->next_busno; 249 if (parent->next_busno + parent->busno_spacing > parent->last_busno) 250 panic("Too many PCI busses on bus %d", parent->busno); 251 parent->next_busno = parent->next_busno + parent->busno_spacing; 252 pb->next_busno = pb->busno+1; 253 pb->busno_spacing = parent->busno_spacing >> 1; 254 if (!pb->busno_spacing) 255 panic("PCI busses nested too deep."); 256 pb->last_busno = parent->next_busno - 1; 257 } 258 259 static pciconf_bus_t * 260 query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev) 261 { 262 pciconf_bus_t *pb; 263 pcireg_t busreg, io, pmem; 264 pciconf_win_t *pi, *pm; 265 266 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 267 if (!pb) 268 panic("Unable to allocate memory for PCI configuration."); 269 270 pb->parent_bus = parent; 271 alloc_busno(parent, pb); 272 if (pci_conf_debug) 273 printf("PCI bus bridge covers busses %d-%d\n", 274 pb->busno, pb->last_busno); 275 276 busreg = parent->busno << PCI_BRIDGE_BUS_PRIMARY_SHIFT; 277 busreg |= pb->busno << PCI_BRIDGE_BUS_SECONDARY_SHIFT; 278 busreg |= pb->last_busno << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 279 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_BUS_REG, busreg); 280 281 pb->swiz = parent->swiz + dev; 282 283 pb->ioext = NULL; 284 pb->memext = NULL; 285 pb->pmemext = NULL; 286 pb->pc = parent->pc; 287 pb->io_total = pb->mem_total = pb->pmem_total = 0; 288 289 pb->io_32bit = 0; 290 if (parent->io_32bit) { 291 io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG); 292 if (PCI_BRIDGE_IO_32BITS(io)) { 293 pb->io_32bit = 1; 294 } 295 } 296 297 pb->pmem_64bit = 0; 298 if (parent->pmem_64bit) { 299 pmem = pci_conf_read(pb->pc, pd->tag, 300 PCI_BRIDGE_PREFETCHMEM_REG); 301 if (PCI_BRIDGE_PREFETCHMEM_64BITS(pmem)) { 302 pb->pmem_64bit = 1; 303 } 304 } 305 306 if (probe_bus(pb)) { 307 printf("Failed to probe bus %d\n", pb->busno); 308 goto err; 309 } 310 311 if (pb->io_total > 0) { 312 if (parent->niowin >= MAX_CONF_IO) { 313 printf("pciconf: too many I/O windows"); 314 goto err; 315 } 316 pb->io_total |= 0xfff; /* Round up */ 317 pi = get_io_desc(parent, pb->io_total); 318 pi->dev = pd; 319 pi->reg = 0; 320 pi->size = pb->io_total; 321 pi->align = 0x1000; /* 4K alignment */ 322 pi->prefetch = 0; 323 parent->niowin++; 324 parent->io_total += pb->io_total; 325 } 326 327 if (pb->mem_total > 0) { 328 if (parent->nmemwin >= MAX_CONF_MEM) { 329 printf("pciconf: too many MEM windows"); 330 goto err; 331 } 332 pb->mem_total |= 0xfffff; /* Round up */ 333 pm = get_mem_desc(parent, pb->mem_total); 334 pm->dev = pd; 335 pm->reg = 0; 336 pm->size = pb->mem_total; 337 pm->align = 0x100000; /* 1M alignment */ 338 pm->prefetch = 0; 339 parent->nmemwin++; 340 parent->mem_total += pb->mem_total; 341 } 342 343 if (pb->pmem_total > 0) { 344 if (parent->nmemwin >= MAX_CONF_MEM) { 345 printf("pciconf: too many MEM windows"); 346 goto err; 347 } 348 pb->pmem_total |= 0xfffff; /* Round up */ 349 pm = get_mem_desc(parent, pb->pmem_total); 350 pm->dev = pd; 351 pm->reg = 0; 352 pm->size = pb->pmem_total; 353 pm->align = 0x100000; /* 1M alignment */ 354 pm->prefetch = 1; 355 parent->nmemwin++; 356 parent->pmem_total += pb->pmem_total; 357 } 358 359 return pb; 360 err: 361 free(pb, M_DEVBUF); 362 return NULL; 363 } 364 365 static int 366 pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func) 367 { 368 pciconf_dev_t *pd; 369 pciconf_win_t *pi, *pm; 370 pcireg_t class, cmd, icr, bar, mask, bar64, mask64; 371 u_int64_t size; 372 int br, width; 373 374 pd = &pb->device[pb->ndevs]; 375 pd->pc = pb->pc; 376 pd->tag = tag; 377 pd->ppb = NULL; 378 pd->enable = 1; 379 380 class = pci_conf_read(pb->pc, tag, PCI_CLASS_REG); 381 382 cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG); 383 384 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE) { 385 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 386 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 387 pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd); 388 } 389 390 if ((cmd & PCI_STATUS_BACKTOBACK_SUPPORT) == 0) 391 pb->fast_b2b = 0; 392 393 if ((cmd & PCI_STATUS_66MHZ_SUPPORT) == 0) 394 pb->freq_66 = 0; 395 396 if ( (PCI_CLASS(class) == PCI_CLASS_BRIDGE) 397 && (PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_PCI)) { 398 pd->ppb = query_bus(pb, pd, dev); 399 if (pd->ppb == NULL) 400 return -1; 401 return 0; 402 } 403 404 icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG); 405 pd->ipin = PCI_INTERRUPT_PIN(icr); 406 pd->iline = PCI_INTERRUPT_LINE(icr); 407 pd->min_gnt = PCI_MIN_GNT(icr); 408 pd->max_lat = PCI_MAX_LAT(icr); 409 if (pd->iline || pd->ipin) { 410 pci_conf_interrupt(pb->pc, pb->busno, dev, func, pb->swiz, 411 &pd->iline); 412 icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 413 icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT); 414 pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr); 415 } 416 417 if (pd->min_gnt != 0 || pd->max_lat != 0) { 418 if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt) 419 pb->max_mingnt = pd->min_gnt; 420 421 if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat) 422 pb->min_maxlat = pd->max_lat; 423 424 pb->bandwidth_used += pd->min_gnt * 4000000 / 425 (pd->min_gnt + pd->max_lat); 426 } 427 428 width = 4; 429 for (br = PCI_MAPREG_START; br < PCI_MAPREG_END; br += width) { 430 if (PCI_CLASS(class) == PCI_CLASS_MASS_STORAGE && 431 PCI_SUBCLASS(class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 432 break; 433 } 434 bar = pci_conf_read(pb->pc, tag, br); 435 pci_conf_write(pb->pc, tag, br, 0xfffffffe); 436 mask = pci_conf_read(pb->pc, tag, br); 437 pci_conf_write(pb->pc, tag, br, bar); 438 width = 4; 439 440 if (mask == 0 || mask == 0xffffffff) 441 break; 442 443 if (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO) { 444 if (pb->niowin >= MAX_CONF_IO) { 445 printf("pciconf: too many I/O windows"); 446 return -1; 447 } 448 449 mask |= 0xffff0000; 450 size = PCI_MAPREG_IO_SIZE(mask); 451 452 pi = get_io_desc(pb, size); 453 pi->dev = pd; 454 pi->reg = br; 455 pi->size = (u_int64_t) size; 456 pi->align = 4; 457 pi->prefetch = 0; 458 if (pci_conf_debug) { 459 print_tag(pb->pc, tag); 460 printf("Register %d, I/O size %llu\n", 461 br, pi->size); 462 } 463 pb->niowin++; 464 pb->io_total += size; 465 } else { 466 switch (PCI_MAPREG_MEM_TYPE(mask)) { 467 case PCI_MAPREG_MEM_TYPE_32BIT: 468 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 469 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 470 break; 471 case PCI_MAPREG_MEM_TYPE_64BIT: 472 bar64 = pci_conf_read(pb->pc, tag, br + 4); 473 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); 474 mask64 = pci_conf_read(pb->pc, tag, br + 4); 475 pci_conf_write(pb->pc, tag, br + 4, bar64); 476 size = (u_int64_t) PCI_MAPREG_MEM64_SIZE( 477 (((u_int64_t) mask64) << 32) | mask); 478 width = 8; 479 continue; 480 default: 481 print_tag(pb->pc, tag); 482 printf("reserved mapping type 0x%x\n", 483 PCI_MAPREG_MEM_TYPE(mask)); 484 continue; 485 } 486 487 if (pb->nmemwin >= MAX_CONF_MEM) { 488 printf("pciconf: too many memory windows"); 489 return -1; 490 } 491 492 493 pm = get_mem_desc(pb, size); 494 pm->dev = pd; 495 pm->reg = br; 496 pm->size = size; 497 pm->align = 4; 498 pm->prefetch = PCI_MAPREG_MEM_PREFETCHABLE(mask); 499 if (pci_conf_debug) { 500 print_tag(pb->pc, tag); 501 printf("Register %d, memory size %llu\n", 502 br, pm->size); 503 } 504 pb->nmemwin++; 505 if (pm->prefetch) { 506 pb->pmem_total += size; 507 } else { 508 pb->mem_total += size; 509 } 510 } 511 } 512 513 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 514 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 515 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 516 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, bar); 517 518 if (mask != 0 && mask != 0xffffffff) { 519 if (pb->nmemwin >= MAX_CONF_MEM) { 520 printf("pciconf: too many memory windows"); 521 return -1; 522 } 523 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 524 525 pm = get_mem_desc(pb, size); 526 pm->dev = pd; 527 pm->reg = PCI_MAPREG_ROM; 528 pm->size = size; 529 pm->align = 4; 530 pm->prefetch = 1; 531 if (pci_conf_debug) { 532 print_tag(pb->pc, tag); 533 printf("Expansion ROM memory size %llu\n", pm->size); 534 } 535 pb->nmemwin++; 536 pb->pmem_total += size; 537 } 538 539 return 0; 540 } 541 542 /************************************************************************/ 543 /************************************************************************/ 544 /******************** Bus configuration routines ********************/ 545 /************************************************************************/ 546 /************************************************************************/ 547 static u_int64_t 548 pci_allocate_range(struct extent *ex, u_int64_t amt, int align) 549 { 550 int r; 551 u_long addr; 552 553 r = extent_alloc(ex, amt, align, 0, EX_NOWAIT, &addr); 554 if (r) { 555 addr = (u_long) -1; 556 printf("extent_alloc() returned %d\n", r); 557 } 558 return (pcireg_t) addr; 559 } 560 561 static int 562 setup_iowins(pciconf_bus_t *pb) 563 { 564 pciconf_win_t *pi; 565 pciconf_dev_t *pd; 566 567 for (pi=pb->pciiowin; pi < &pb->pciiowin[pb->niowin] ; pi++) { 568 if (pi->size == 0) 569 continue; 570 571 pd = pi->dev; 572 pi->address = pci_allocate_range(pb->ioext, pi->size, 573 pi->align); 574 if (pi->address == -1) { 575 print_tag(pd->pc, pd->tag); 576 printf("Failed to allocate PCI I/O space (%llu req)\n", 577 pi->size); 578 return -1; 579 } 580 if (!pb->io_32bit && pi->address > 0xFFFF) { 581 pi->address = 0; 582 pd->enable = 0; 583 } 584 if (pd->ppb && pi->reg == 0) { 585 pd->ppb->ioext = extent_create("pciconf", pi->address, 586 pi->address + pi->size, M_DEVBUF, NULL, 0, 587 EX_NOWAIT); 588 if (pd->ppb->ioext == NULL) { 589 print_tag(pd->pc, pd->tag); 590 printf("Failed to alloc I/O ext. for bus %d\n", 591 pd->ppb->busno); 592 return -1; 593 } 594 continue; 595 } 596 if (pci_conf_debug) { 597 print_tag(pd->pc, pd->tag); 598 printf("Putting %llu I/O bytes @ %#llx (reg %x)\n", 599 pi->size, pi->address, pi->reg); 600 } 601 pci_conf_write(pd->pc, pd->tag, pi->reg, 602 PCI_MAPREG_IO_ADDR(pi->address) | PCI_MAPREG_TYPE_IO); 603 } 604 return 0; 605 } 606 607 static int 608 setup_memwins(pciconf_bus_t *pb) 609 { 610 pciconf_win_t *pm; 611 pciconf_dev_t *pd; 612 pcireg_t base; 613 struct extent *ex; 614 615 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 616 if (pm->size == 0) 617 continue; 618 619 pd = pm->dev; 620 ex = (pm->prefetch) ? pb->pmemext : pb->memext; 621 pm->address = pci_allocate_range(ex, pm->size, pm->align); 622 if (pm->address == -1) { 623 print_tag(pd->pc, pd->tag); 624 printf( 625 "Failed to allocate PCI memory space (%llu req)\n", 626 pm->size); 627 return -1; 628 } 629 if (pd->ppb && pm->reg == 0) { 630 ex = extent_create("pciconf", pm->address, 631 pm->address + pm->size, M_DEVBUF, NULL, 0, 632 EX_NOWAIT); 633 if (ex == NULL) { 634 print_tag(pd->pc, pd->tag); 635 printf("Failed to alloc MEM ext. for bus %d\n", 636 pd->ppb->busno); 637 return -1; 638 } 639 if (pm->prefetch) { 640 pd->ppb->pmemext = ex; 641 } else { 642 pd->ppb->memext = ex; 643 } 644 continue; 645 } 646 if (pm->prefetch && !pb->pmem_64bit && 647 pm->address > 0xFFFFFFFFULL) { 648 pm->address = 0; 649 pd->enable = 0; 650 } 651 if (pm->reg != PCI_MAPREG_ROM) { 652 if (pci_conf_debug) { 653 print_tag(pd->pc, pd->tag); 654 printf( 655 "Putting %llu MEM bytes @ %#llx (reg %x)\n", 656 pm->size, pm->address, pm->reg); 657 } 658 base = pci_conf_read(pd->pc, pd->tag, pm->reg); 659 base = PCI_MAPREG_MEM_ADDR(pm->address) | 660 PCI_MAPREG_MEM_TYPE(base); 661 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 662 if (PCI_MAPREG_MEM_TYPE(base) == 663 PCI_MAPREG_MEM_TYPE_64BIT) { 664 base = (pcireg_t) 665 (PCI_MAPREG_MEM64_ADDR(pm->address) >> 32); 666 pci_conf_write(pd->pc, pd->tag, pm->reg + 4, 667 base); 668 } 669 } 670 } 671 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 672 if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) { 673 pd = pm->dev; 674 if (pci_conf_debug) { 675 print_tag(pd->pc, pd->tag); 676 printf( 677 "Putting %llu ROM bytes @ %#llx (reg %x)\n", 678 pm->size, pm->address, pm->reg); 679 } 680 base = ((pcireg_t) pm->address) | PCI_MAPREG_TYPE_ROM; 681 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 682 } 683 } 684 return 0; 685 } 686 687 /* 688 * Configure I/O, memory, and prefetcable memory spaces, then make 689 * a call to configure_bus(). 690 */ 691 static int 692 configure_bridge(pciconf_dev_t *pd) 693 { 694 unsigned long io_base, io_limit, mem_base, mem_limit; 695 pciconf_bus_t *pb; 696 pcireg_t io, iohigh, mem, cmd; 697 int rv; 698 699 pb = pd->ppb; 700 /* Configure I/O base & limit*/ 701 if (pb->ioext) { 702 io_base = pb->ioext->ex_start; 703 io_limit = pb->ioext->ex_end; 704 } else { 705 io_base = 0x1000; /* 4K */ 706 io_limit = 0x0000; 707 } 708 if (pb->io_32bit) { 709 iohigh = 710 ((io_base >> 16) << PCI_BRIDGE_IOHIGH_BASE_SHIFT) | 711 ((io_limit >> 16) << PCI_BRIDGE_IOHIGH_LIMIT_SHIFT); 712 } else { 713 if (io_limit > 0xFFFF) { 714 printf("Bus %d bridge does not support 32-bit I/O. ", 715 pb->busno); 716 printf("Disabling I/O accesses\n"); 717 io_base = 0x1000; /* 4K */ 718 io_limit = 0x0000; 719 } 720 iohigh = 0; 721 } 722 io &= (PCI_BRIDGE_STATIO_STATUS_MASK << 723 PCI_BRIDGE_STATIO_STATUS_SHIFT); 724 io |= (((io_base >> 8) & PCI_BRIDGE_STATIO_IOBASE_MASK) 725 << PCI_BRIDGE_STATIO_IOBASE_SHIFT); 726 io |= (((io_limit >> 8) & PCI_BRIDGE_STATIO_IOLIMIT_MASK) 727 << PCI_BRIDGE_STATIO_IOLIMIT_SHIFT); 728 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io); 729 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh); 730 731 /* Configure mem base & limit */ 732 if (pb->memext) { 733 mem_base = pb->memext->ex_start; 734 mem_limit = pb->memext->ex_end; 735 } else { 736 mem_base = 0x100000; /* 1M */ 737 mem_limit = 0x000000; 738 } 739 if (mem_limit > 0xFFFFFFFFULL) { 740 printf("Bus %d bridge MEM range out of range. ", pb->busno); 741 printf("Disabling MEM accesses\n"); 742 mem_base = 0x100000; /* 1M */ 743 mem_limit = 0x000000; 744 } 745 mem = (((mem_base >> 20) & PCI_BRIDGE_MEMORY_BASE_MASK) 746 << PCI_BRIDGE_MEMORY_BASE_SHIFT); 747 mem |= (((mem_limit >> 20) & PCI_BRIDGE_MEMORY_LIMIT_MASK) 748 << PCI_BRIDGE_MEMORY_LIMIT_SHIFT); 749 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem); 750 751 /* Configure prefetchable mem base & limit */ 752 if (pb->pmemext) { 753 mem_base = pb->pmemext->ex_start; 754 mem_limit = pb->pmemext->ex_end; 755 } else { 756 mem_base = 0x100000; /* 1M */ 757 mem_limit = 0x000000; 758 } 759 mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG); 760 if (!PCI_BRIDGE_PREFETCHMEM_64BITS(mem) && mem_limit > 0xFFFFFFFFULL) { 761 printf("Bus %d bridge does not support 64-bit PMEM. ", 762 pb->busno); 763 printf("Disabling prefetchable-MEM accesses\n"); 764 mem_base = 0x100000; /* 1M */ 765 mem_limit = 0x000000; 766 } 767 mem = (((mem_base >> 20) & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) 768 << PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT); 769 mem |= (((mem_limit >> 20) & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) 770 << PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT); 771 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem); 772 /* 773 * XXX -- 64-bit systems need a lot more than just this... 774 */ 775 if (sizeof(u_long) > 4) { 776 mem_base = (int64_t) mem_base >> 32; 777 mem_limit = (int64_t) mem_limit >> 32; 778 } 779 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHBASE32_REG, 780 mem_base & 0xffffffff); 781 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHLIMIT32_REG, 782 mem_limit & 0xffffffff); 783 784 rv = configure_bus(pb); 785 786 if (pb->ioext) 787 extent_destroy(pb->ioext); 788 if (pb->memext) 789 extent_destroy(pb->memext); 790 if (pb->pmemext) 791 extent_destroy(pb->pmemext); 792 if (rv == 0) { 793 cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG); 794 cmd &= PCI_BRIDGE_CONTROL_MASK; 795 cmd |= (PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR) 796 << PCI_BRIDGE_CONTROL_SHIFT; 797 if (pb->fast_b2b) { 798 cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B 799 << PCI_BRIDGE_CONTROL_SHIFT; 800 } 801 pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd); 802 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 803 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 804 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 805 } 806 807 return rv; 808 } 809 810 /* 811 * Calculate latency values, allocate I/O and MEM segments, then set them 812 * up. If a PCI-PCI bridge is found, configure the bridge separately, 813 * which will cause a recursive call back here. 814 */ 815 static int 816 configure_bus(pciconf_bus_t *pb) 817 { 818 pciconf_dev_t *pd; 819 int def_ltim, max_ltim, band; 820 821 /* MIN_GNT assumes a clock rate of 33MHz */ 822 max_ltim = pb->max_mingnt * 33 / 4; /* cvt to cycle count */ 823 band = 40000000; /* 0.25us cycles/sec */ 824 if (band < pb->bandwidth_used) { 825 printf("PCI bus %d: Warning: Total bandwidth exceeded!?\n", 826 pb->busno); 827 def_ltim = -1; 828 } else { 829 def_ltim = (band - pb->bandwidth_used) / pb->ndevs; 830 if (def_ltim > pb->min_maxlat) 831 def_ltim = pb->min_maxlat; 832 def_ltim = def_ltim * 33 / 4; 833 } 834 def_ltim = (def_ltim + 7) & ~7; 835 max_ltim = (max_ltim + 7) & ~7; 836 837 pb->def_ltim = MIN( def_ltim, 255 ); 838 pb->max_ltim = MIN( MAX(max_ltim, def_ltim ), 255 ); 839 840 /* 841 * Now we have what we need to initialize the devices. 842 * It would probably be better if we could allocate all of these 843 * for all busses at once, but "not right now". First, get a list 844 * of free memory ranges from the m.d. system. 845 */ 846 if (setup_iowins(pb) || setup_memwins(pb)) { 847 printf("PCI bus configuration failed: "); 848 printf("unable to assign all I/O and memory ranges."); 849 return -1; 850 } 851 852 /* 853 * Configure the latency for the devices, and enable them. 854 */ 855 for (pd=pb->device ; pd < &pb->device[pb->ndevs] ; pd++) { 856 pcireg_t cmd, class, misc; 857 int ltim; 858 859 if (pci_conf_debug) { 860 print_tag(pd->pc, pd->tag); 861 printf("Configuring device.\n"); 862 } 863 class = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG); 864 misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG); 865 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 866 cmd |= PCI_COMMAND_MASTER_ENABLE 867 | PCI_COMMAND_SERR_ENABLE 868 | PCI_COMMAND_PARITY_ENABLE; 869 if (pb->fast_b2b) 870 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE; 871 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 872 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_PCI) { 873 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 874 ltim = pd->min_gnt * 33 / 4; 875 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim); 876 } else { 877 ltim = MIN (pb->def_ltim, pb->max_ltim); 878 } 879 if (!pd->enable) { 880 print_tag(pd->pc, pd->tag); 881 printf("Disabled due to lack of resources.\n"); 882 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 883 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 884 } 885 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 886 887 misc = (misc & ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT)) 888 | ((ltim & 0xff) << PCI_LATTIMER_SHIFT); 889 pci_conf_write(pd->pc, pd->tag, PCI_BHLC_REG, misc); 890 891 if (pd->ppb) { 892 if (configure_bridge(pd) < 0) 893 return -1; 894 continue; 895 } 896 } 897 898 if (pci_conf_debug) { 899 printf("PCI bus %d configured\n", pb->busno); 900 } 901 902 return 0; 903 } 904 905 /* 906 * Let's configure the PCI bus. 907 * This consists of basically scanning for all existing devices, 908 * identifying their needs, and then making another pass over them 909 * to set: 910 * 1. I/O addresses 911 * 2. Memory addresses (Prefetchable and not) 912 * 3. PCI command register 913 * 4. The latency part of the PCI BHLC (BIST (Built-In Self Test), 914 * Header type, Latency timer, Cache line size) register 915 * 916 * The command register is set to enable fast back-to-back transactions 917 * if the host bridge says it can handle it. We also configure 918 * Master Enable, SERR enable, parity enable, and (if this is not a 919 * PCI-PCI bridge) the I/O and Memory spaces. Apparently some devices 920 * will not report some I/O space. 921 * 922 * The latency is computed to be a "fair share" of the bus bandwidth. 923 * The bus bandwidth variable is initialized to the number of PCI cycles 924 * in one second. The number of cycles taken for one transaction by each 925 * device (MAX_LAT + MIN_GNT) is then subtracted from the bandwidth. 926 * Care is taken to ensure that the latency timer won't be set such that 927 * it would exceed the critical time for any device. 928 * 929 * This is complicated somewhat due to the presence of bridges. PCI-PCI 930 * bridges are probed and configured recursively. 931 */ 932 int 933 pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext, 934 struct extent *memext, struct extent *pmemext) 935 { 936 pciconf_bus_t *pb; 937 int rv; 938 939 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 940 pb->busno = 0; 941 pb->busno_spacing = PCI_BUSNO_SPACING; 942 pb->next_busno = pb->busno + 1; 943 pb->last_busno = 255; 944 pb->parent_bus = NULL; 945 pb->swiz = 0; 946 pb->io_32bit = 1; 947 pb->pmem_64bit = 0; 948 pb->ioext = ioext; 949 pb->memext = memext; 950 if (pmemext == NULL) { 951 pb->pmemext = memext; 952 } else { 953 pb->pmemext = pmemext; 954 } 955 pb->pc = pc; 956 pb->io_total = pb->mem_total = pb->pmem_total = 0; 957 958 rv = probe_bus(pb); 959 if (rv == 0) { 960 rv = configure_bus(pb); 961 } 962 963 /* 964 * All done! 965 */ 966 free(pb, M_DEVBUF); 967 return rv; 968 } 969
Indexes created Tue Sep 23 14:10:03 GMT 2025