pciconf.c revision 1.26
1 /* $NetBSD: pciconf.c,v 1.26 2005/03/25 14:51:39 tsutsui Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Derived in part from code from PMON/2000 (http://pmon.groupbsd.org/). 39 */ 40 41 /* 42 * To do: 43 * - Perform all data structure allocation dynamically, don't have 44 * statically-sized arrays ("oops, you lose because you have too 45 * many slots filled!") 46 * - Do this in 2 passes, with an MD hook to control the behavior: 47 * (1) Configure the bus (possibly including expansion 48 * ROMs. 49 * (2) Another pass to disable expansion ROMs if they're 50 * mapped (since you're not supposed to leave them 51 * mapped when you're not using them). 52 * This would facilitate MD code executing the expansion ROMs 53 * if necessary (possibly with an x86 emulator) to configure 54 * devices (e.g. VGA cards). 55 * - Deal with "anything can be hot-plugged" -- i.e., carry configuration 56 * information around & be able to reconfigure on the fly 57 * - Deal with segments (See IA64 System Abstraction Layer) 58 * - Deal with subtractive bridges (& non-spec positive/subtractive decode) 59 * - Deal with ISA/VGA/VGA palette snooping 60 * - Deal with device capabilities on bridges 61 * - Worry about changing a bridge to/from transparency 62 * From thorpej (05/25/01) 63 * - Try to handle devices that are already configured (perhaps using that 64 * as a hint to where we put other devices) 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: pciconf.c,v 1.26 2005/03/25 14:51:39 tsutsui Exp $"); 69 70 #include "opt_pci.h" 71 72 #include <sys/param.h> 73 #include <sys/extent.h> 74 #include <sys/queue.h> 75 #include <sys/systm.h> 76 #include <sys/malloc.h> 77 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/pciconf.h> 80 #include <dev/pci/pcidevs.h> 81 #include <dev/pci/pccbbreg.h> 82 83 int pci_conf_debug = 0; 84 85 #if !defined(MIN) 86 #define MIN(a,b) (((a)<(b))?(a):(b)) 87 #define MAX(a,b) (((a)>(b))?(a):(b)) 88 #endif 89 90 /* per-bus constants. */ 91 #define MAX_CONF_DEV 32 /* Arbitrary */ 92 #define MAX_CONF_MEM (3 * MAX_CONF_DEV) /* Avg. 3 per device -- Arb. */ 93 #define MAX_CONF_IO (3 * MAX_CONF_DEV) /* Avg. 1 per device -- Arb. */ 94 95 struct _s_pciconf_bus_t; /* Forward declaration */ 96 97 typedef struct _s_pciconf_dev_t { 98 int ipin; 99 int iline; 100 int min_gnt; 101 int max_lat; 102 int enable; 103 pcitag_t tag; 104 pci_chipset_tag_t pc; 105 struct _s_pciconf_bus_t *ppb; /* I am really a bridge */ 106 } pciconf_dev_t; 107 108 typedef struct _s_pciconf_win_t { 109 pciconf_dev_t *dev; 110 int reg; /* 0 for busses */ 111 int align; 112 int prefetch; 113 u_int64_t size; 114 u_int64_t address; 115 } pciconf_win_t; 116 117 typedef struct _s_pciconf_bus_t { 118 int busno; 119 int next_busno; 120 int last_busno; 121 int max_mingnt; 122 int min_maxlat; 123 int cacheline_size; 124 int prefetch; 125 int fast_b2b; 126 int freq_66; 127 int def_ltim; 128 int max_ltim; 129 int bandwidth_used; 130 int swiz; 131 int io_32bit; 132 int pmem_64bit; 133 134 int ndevs; 135 pciconf_dev_t device[MAX_CONF_DEV]; 136 137 /* These should be sorted in order of decreasing size */ 138 int nmemwin; 139 pciconf_win_t pcimemwin[MAX_CONF_MEM]; 140 int niowin; 141 pciconf_win_t pciiowin[MAX_CONF_IO]; 142 143 bus_size_t io_total; 144 bus_size_t mem_total; 145 bus_size_t pmem_total; 146 147 struct extent *ioext; 148 struct extent *memext; 149 struct extent *pmemext; 150 151 pci_chipset_tag_t pc; 152 struct _s_pciconf_bus_t *parent_bus; 153 } pciconf_bus_t; 154 155 static int probe_bus(pciconf_bus_t *); 156 static void alloc_busno(pciconf_bus_t *, pciconf_bus_t *); 157 static void set_busreg(pci_chipset_tag_t, pcitag_t, int, int, int); 158 static int pci_do_device_query(pciconf_bus_t *, pcitag_t, int, int, int); 159 static int setup_iowins(pciconf_bus_t *); 160 static int setup_memwins(pciconf_bus_t *); 161 static int configure_bridge(pciconf_dev_t *); 162 static int configure_bus(pciconf_bus_t *); 163 static u_int64_t pci_allocate_range(struct extent *, u_int64_t, int); 164 static pciconf_win_t *get_io_desc(pciconf_bus_t *, bus_size_t); 165 static pciconf_win_t *get_mem_desc(pciconf_bus_t *, bus_size_t); 166 static pciconf_bus_t *query_bus(pciconf_bus_t *, pciconf_dev_t *, int); 167 168 static void print_tag(pci_chipset_tag_t, pcitag_t); 169 170 static void 171 print_tag(pci_chipset_tag_t pc, pcitag_t tag) 172 { 173 int bus, dev, func; 174 175 pci_decompose_tag(pc, tag, &bus, &dev, &func); 176 printf("PCI: bus %d, device %d, function %d: ", bus, dev, func); 177 } 178 179 /************************************************************************/ 180 /************************************************************************/ 181 /*********************** Bus probing routines ***********************/ 182 /************************************************************************/ 183 /************************************************************************/ 184 static pciconf_win_t * 185 get_io_desc(pciconf_bus_t *pb, bus_size_t size) 186 { 187 int i, n; 188 189 n = pb->niowin; 190 for (i=n; i > 0 && size > pb->pciiowin[i-1].size; i--) 191 pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */ 192 return &pb->pciiowin[i]; 193 } 194 195 static pciconf_win_t * 196 get_mem_desc(pciconf_bus_t *pb, bus_size_t size) 197 { 198 int i, n; 199 200 n = pb->nmemwin; 201 for (i=n; i > 0 && size > pb->pcimemwin[i-1].size; i--) 202 pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */ 203 return &pb->pcimemwin[i]; 204 } 205 206 /* 207 * Set up bus common stuff, then loop over devices & functions. 208 * If we find something, call pci_do_device_query()). 209 */ 210 static int 211 probe_bus(pciconf_bus_t *pb) 212 { 213 int device, maxdevs; 214 #ifdef __PCI_BUS_DEVORDER 215 char devs[32]; 216 int i; 217 #endif 218 219 maxdevs = pci_bus_maxdevs(pb->pc, pb->busno); 220 pb->ndevs = 0; 221 pb->niowin = 0; 222 pb->nmemwin = 0; 223 pb->freq_66 = 1; 224 #ifdef PCICONF_NO_FAST_B2B 225 pb->fast_b2b = 0; 226 #else 227 pb->fast_b2b = 1; 228 #endif 229 pb->prefetch = 1; 230 pb->max_mingnt = 0; /* we are looking for the maximum */ 231 pb->min_maxlat = 0x100; /* we are looking for the minimum */ 232 pb->bandwidth_used = 0; 233 234 #ifdef __PCI_BUS_DEVORDER 235 pci_bus_devorder(pb->pc, pb->busno, devs); 236 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) { 237 #else 238 for (device = 0; device < maxdevs; device++) { 239 #endif 240 pcitag_t tag; 241 pcireg_t id, bhlcr; 242 int function, nfunction; 243 int confmode; 244 245 tag = pci_make_tag(pb->pc, pb->busno, device, 0); 246 if (pci_conf_debug) { 247 print_tag(pb->pc, tag); 248 } 249 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 250 251 if (pci_conf_debug) { 252 printf("id=%x: Vendor=%x, Product=%x\n", 253 id, PCI_VENDOR(id),PCI_PRODUCT(id)); 254 } 255 /* Invalid vendor ID value? */ 256 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 257 continue; 258 259 bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 260 nfunction = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 261 for (function = 0 ; function < nfunction ; function++) { 262 tag = pci_make_tag(pb->pc, pb->busno, device, function); 263 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 264 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 265 continue; 266 if (pb->ndevs+1 < MAX_CONF_DEV) { 267 if (pci_conf_debug) { 268 print_tag(pb->pc, tag); 269 printf("Found dev 0x%04x 0x%04x -- " 270 "really probing.\n", 271 PCI_VENDOR(id), PCI_PRODUCT(id)); 272 } 273 #ifdef __HAVE_PCI_CONF_HOOK 274 confmode = pci_conf_hook(pb->pc, pb->busno, 275 device, function, id); 276 if (confmode == 0) 277 continue; 278 #else 279 /* 280 * Don't enable expansion ROMS -- some cards 281 * share address decoders between the EXPROM 282 * and PCI memory space, and enabling the ROM 283 * when not needed will cause all sorts of 284 * lossage. 285 */ 286 confmode = PCI_CONF_ALL & ~PCI_CONF_MAP_ROM; 287 #endif 288 if (pci_do_device_query(pb, tag, device, 289 function, confmode)) 290 return -1; 291 pb->ndevs++; 292 } 293 } 294 } 295 return 0; 296 } 297 298 static void 299 alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb) 300 { 301 pb->busno = parent->next_busno; 302 pb->next_busno = pb->busno + 1; 303 } 304 305 static void 306 set_busreg(pci_chipset_tag_t pc, pcitag_t tag, int prim, int sec, int sub) 307 { 308 pcireg_t busreg; 309 310 busreg = prim << PCI_BRIDGE_BUS_PRIMARY_SHIFT; 311 busreg |= sec << PCI_BRIDGE_BUS_SECONDARY_SHIFT; 312 busreg |= sub << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 313 pci_conf_write(pc, tag, PCI_BRIDGE_BUS_REG, busreg); 314 } 315 316 static pciconf_bus_t * 317 query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev) 318 { 319 pciconf_bus_t *pb; 320 pcireg_t io, pmem; 321 pciconf_win_t *pi, *pm; 322 323 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 324 if (!pb) 325 panic("Unable to allocate memory for PCI configuration."); 326 327 pb->cacheline_size = parent->cacheline_size; 328 pb->parent_bus = parent; 329 alloc_busno(parent, pb); 330 331 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 0xff); 332 333 pb->swiz = parent->swiz + dev; 334 335 pb->ioext = NULL; 336 pb->memext = NULL; 337 pb->pmemext = NULL; 338 pb->pc = parent->pc; 339 pb->io_total = pb->mem_total = pb->pmem_total = 0; 340 341 pb->io_32bit = 0; 342 if (parent->io_32bit) { 343 io = pci_conf_read(parent->pc, pd->tag, PCI_BRIDGE_STATIO_REG); 344 if (PCI_BRIDGE_IO_32BITS(io)) { 345 pb->io_32bit = 1; 346 } 347 } 348 349 pb->pmem_64bit = 0; 350 if (parent->pmem_64bit) { 351 pmem = pci_conf_read(parent->pc, pd->tag, 352 PCI_BRIDGE_PREFETCHMEM_REG); 353 if (PCI_BRIDGE_PREFETCHMEM_64BITS(pmem)) { 354 pb->pmem_64bit = 1; 355 } 356 } 357 358 if (probe_bus(pb)) { 359 printf("Failed to probe bus %d\n", pb->busno); 360 goto err; 361 } 362 363 /* We have found all subordinate busses now, reprogram busreg. */ 364 pb->last_busno = pb->next_busno-1; 365 parent->next_busno = pb->next_busno; 366 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 367 pb->last_busno); 368 if (pci_conf_debug) 369 printf("PCI bus bridge (parent %d) covers busses %d-%d\n", 370 parent->busno, pb->busno, pb->last_busno); 371 372 if (pb->io_total > 0) { 373 if (parent->niowin >= MAX_CONF_IO) { 374 printf("pciconf: too many I/O windows\n"); 375 goto err; 376 } 377 pb->io_total |= 0xfff; /* Round up */ 378 pi = get_io_desc(parent, pb->io_total); 379 pi->dev = pd; 380 pi->reg = 0; 381 pi->size = pb->io_total; 382 pi->align = 0x1000; /* 4K alignment */ 383 pi->prefetch = 0; 384 parent->niowin++; 385 parent->io_total += pb->io_total; 386 } 387 388 if (pb->mem_total > 0) { 389 if (parent->nmemwin >= MAX_CONF_MEM) { 390 printf("pciconf: too many MEM windows\n"); 391 goto err; 392 } 393 pb->mem_total |= 0xfffff; /* Round up */ 394 pm = get_mem_desc(parent, pb->mem_total); 395 pm->dev = pd; 396 pm->reg = 0; 397 pm->size = pb->mem_total; 398 pm->align = 0x100000; /* 1M alignment */ 399 pm->prefetch = 0; 400 parent->nmemwin++; 401 parent->mem_total += pb->mem_total; 402 } 403 404 if (pb->pmem_total > 0) { 405 if (parent->nmemwin >= MAX_CONF_MEM) { 406 printf("pciconf: too many MEM windows\n"); 407 goto err; 408 } 409 pb->pmem_total |= 0xfffff; /* Round up */ 410 pm = get_mem_desc(parent, pb->pmem_total); 411 pm->dev = pd; 412 pm->reg = 0; 413 pm->size = pb->pmem_total; 414 pm->align = 0x100000; /* 1M alignment */ 415 pm->prefetch = 1; 416 parent->nmemwin++; 417 parent->pmem_total += pb->pmem_total; 418 } 419 420 return pb; 421 err: 422 free(pb, M_DEVBUF); 423 return NULL; 424 } 425 426 static int 427 pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func, int mode) 428 { 429 pciconf_dev_t *pd; 430 pciconf_win_t *pi, *pm; 431 pcireg_t class, cmd, icr, bhlc, bar, mask, bar64, mask64, busreg; 432 u_int64_t size; 433 int br, width, reg_start, reg_end; 434 435 pd = &pb->device[pb->ndevs]; 436 pd->pc = pb->pc; 437 pd->tag = tag; 438 pd->ppb = NULL; 439 pd->enable = mode; 440 441 class = pci_conf_read(pb->pc, tag, PCI_CLASS_REG); 442 443 cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG); 444 445 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE) { 446 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 447 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 448 pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd); 449 } else if (pci_conf_debug) { 450 print_tag(pb->pc, tag); 451 printf("device is a bridge; not clearing enables\n"); 452 } 453 454 if ((cmd & PCI_STATUS_BACKTOBACK_SUPPORT) == 0) 455 pb->fast_b2b = 0; 456 457 if ((cmd & PCI_STATUS_66MHZ_SUPPORT) == 0) 458 pb->freq_66 = 0; 459 460 bhlc = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 461 switch (PCI_HDRTYPE_TYPE(bhlc)) { 462 case PCI_HDRTYPE_DEVICE: 463 reg_start = PCI_MAPREG_START; 464 reg_end = PCI_MAPREG_END; 465 break; 466 case PCI_HDRTYPE_PPB: 467 pd->ppb = query_bus(pb, pd, dev); 468 if (pd->ppb == NULL) 469 return -1; 470 return 0; 471 case PCI_HDRTYPE_PCB: 472 reg_start = PCI_MAPREG_START; 473 reg_end = PCI_MAPREG_PCB_END; 474 475 busreg = pci_conf_read(pb->pc, tag, PCI_BUSNUM); 476 busreg = (busreg & 0xff000000) | 477 pb->busno << PCI_BRIDGE_BUS_PRIMARY_SHIFT | 478 pb->next_busno << PCI_BRIDGE_BUS_SECONDARY_SHIFT | 479 pb->next_busno << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 480 pci_conf_write(pb->pc, tag, PCI_BUSNUM, busreg); 481 482 pb->next_busno++; 483 break; 484 default: 485 return -1; 486 } 487 488 icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG); 489 pd->ipin = PCI_INTERRUPT_PIN(icr); 490 pd->iline = PCI_INTERRUPT_LINE(icr); 491 pd->min_gnt = PCI_MIN_GNT(icr); 492 pd->max_lat = PCI_MAX_LAT(icr); 493 if (pd->iline || pd->ipin) { 494 pci_conf_interrupt(pb->pc, pb->busno, dev, pd->ipin, pb->swiz, 495 &pd->iline); 496 icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 497 icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT); 498 pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr); 499 } 500 501 if (pd->min_gnt != 0 || pd->max_lat != 0) { 502 if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt) 503 pb->max_mingnt = pd->min_gnt; 504 505 if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat) 506 pb->min_maxlat = pd->max_lat; 507 508 pb->bandwidth_used += pd->min_gnt * 4000000 / 509 (pd->min_gnt + pd->max_lat); 510 } 511 512 width = 4; 513 for (br = reg_start; br < reg_end; br += width) { 514 #if 0 515 /* XXX Should only ignore if IDE not in legacy mode? */ 516 if (PCI_CLASS(class) == PCI_CLASS_MASS_STORAGE && 517 PCI_SUBCLASS(class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 518 break; 519 } 520 #endif 521 bar = pci_conf_read(pb->pc, tag, br); 522 pci_conf_write(pb->pc, tag, br, 0xffffffff); 523 mask = pci_conf_read(pb->pc, tag, br); 524 pci_conf_write(pb->pc, tag, br, bar); 525 width = 4; 526 527 if ( (mode & PCI_CONF_MAP_IO) 528 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO)) { 529 /* 530 * Upper 16 bits must be one. Devices may hardwire 531 * them to zero, though, per PCI 2.2, 6.2.5.1, p 203. 532 */ 533 mask |= 0xffff0000; 534 535 size = PCI_MAPREG_IO_SIZE(mask); 536 if (size == 0) { 537 if (pci_conf_debug) { 538 print_tag(pb->pc, tag); 539 printf("I/O BAR 0x%x is void\n", br); 540 } 541 continue; 542 } 543 544 if (pb->niowin >= MAX_CONF_IO) { 545 printf("pciconf: too many I/O windows\n"); 546 return -1; 547 } 548 549 pi = get_io_desc(pb, size); 550 pi->dev = pd; 551 pi->reg = br; 552 pi->size = (u_int64_t) size; 553 pi->align = 4; 554 pi->prefetch = 0; 555 if (pci_conf_debug) { 556 print_tag(pb->pc, tag); 557 printf("Register 0x%x, I/O size %" PRIu64 "\n", 558 br, pi->size); 559 } 560 pb->niowin++; 561 pb->io_total += size; 562 } else if ((mode & PCI_CONF_MAP_MEM) 563 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_MEM)) { 564 switch (PCI_MAPREG_MEM_TYPE(mask)) { 565 case PCI_MAPREG_MEM_TYPE_32BIT: 566 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 567 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 568 break; 569 case PCI_MAPREG_MEM_TYPE_64BIT: 570 bar64 = pci_conf_read(pb->pc, tag, br + 4); 571 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); 572 mask64 = pci_conf_read(pb->pc, tag, br + 4); 573 pci_conf_write(pb->pc, tag, br + 4, bar64); 574 size = (u_int64_t) PCI_MAPREG_MEM64_SIZE( 575 (((u_int64_t) mask64) << 32) | mask); 576 width = 8; 577 break; 578 default: 579 print_tag(pb->pc, tag); 580 printf("reserved mapping type 0x%x\n", 581 PCI_MAPREG_MEM_TYPE(mask)); 582 continue; 583 } 584 585 if (size == 0) { 586 if (pci_conf_debug) { 587 print_tag(pb->pc, tag); 588 printf("MEM%d BAR 0x%x is void\n", 589 PCI_MAPREG_MEM_TYPE(mask) == 590 PCI_MAPREG_MEM_TYPE_64BIT ? 591 64 : 32, br); 592 } 593 continue; 594 } else { 595 if (pci_conf_debug) { 596 print_tag(pb->pc, tag); 597 printf("MEM%d BAR 0x%x has size %lx\n", 598 PCI_MAPREG_MEM_TYPE(mask) == 599 PCI_MAPREG_MEM_TYPE_64BIT ? 600 64 : 32, br, (unsigned long)size); 601 } 602 } 603 604 if (pb->nmemwin >= MAX_CONF_MEM) { 605 printf("pciconf: too many memory windows\n"); 606 return -1; 607 } 608 609 pm = get_mem_desc(pb, size); 610 pm->dev = pd; 611 pm->reg = br; 612 pm->size = size; 613 pm->align = 4; 614 pm->prefetch = PCI_MAPREG_MEM_PREFETCHABLE(mask); 615 if (pci_conf_debug) { 616 print_tag(pb->pc, tag); 617 printf("Register 0x%x, memory size %" 618 PRIu64 "\n", br, pm->size); 619 } 620 pb->nmemwin++; 621 if (pm->prefetch) { 622 pb->pmem_total += size; 623 } else { 624 pb->mem_total += size; 625 } 626 } 627 } 628 629 if (mode & PCI_CONF_MAP_ROM) { 630 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 631 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 632 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 633 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, bar); 634 635 if (mask != 0 && mask != 0xffffffff) { 636 if (pb->nmemwin >= MAX_CONF_MEM) { 637 printf("pciconf: too many memory windows\n"); 638 return -1; 639 } 640 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 641 642 pm = get_mem_desc(pb, size); 643 pm->dev = pd; 644 pm->reg = PCI_MAPREG_ROM; 645 pm->size = size; 646 pm->align = 4; 647 pm->prefetch = 1; 648 if (pci_conf_debug) { 649 print_tag(pb->pc, tag); 650 printf("Expansion ROM memory size %" 651 PRIu64 "\n", pm->size); 652 } 653 pb->nmemwin++; 654 pb->pmem_total += size; 655 } 656 } else { 657 /* Ensure ROM is disabled */ 658 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 659 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 660 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 661 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 662 bar & ~PCI_MAPREG_ROM_ENABLE); 663 } 664 665 return 0; 666 } 667 668 /************************************************************************/ 669 /************************************************************************/ 670 /******************** Bus configuration routines ********************/ 671 /************************************************************************/ 672 /************************************************************************/ 673 static u_int64_t 674 pci_allocate_range(struct extent *ex, u_int64_t amt, int align) 675 { 676 int r; 677 u_long addr; 678 679 r = extent_alloc(ex, amt, align, 0, EX_NOWAIT, &addr); 680 if (r) { 681 addr = (u_long) -1; 682 printf("extent_alloc(%p, %" PRIu64 ", %d) returned %d\n", 683 ex, amt, align, r); 684 extent_print(ex); 685 } 686 return (pcireg_t) addr; 687 } 688 689 static int 690 setup_iowins(pciconf_bus_t *pb) 691 { 692 pciconf_win_t *pi; 693 pciconf_dev_t *pd; 694 695 for (pi=pb->pciiowin; pi < &pb->pciiowin[pb->niowin] ; pi++) { 696 if (pi->size == 0) 697 continue; 698 699 pd = pi->dev; 700 pi->address = pci_allocate_range(pb->ioext, pi->size, 701 pi->align); 702 if (pi->address == -1) { 703 print_tag(pd->pc, pd->tag); 704 printf("Failed to allocate PCI I/O space (%" 705 PRIu64 " req)\n", pi->size); 706 return -1; 707 } 708 if (pd->ppb && pi->reg == 0) { 709 pd->ppb->ioext = extent_create("pciconf", pi->address, 710 pi->address + pi->size, M_DEVBUF, NULL, 0, 711 EX_NOWAIT); 712 if (pd->ppb->ioext == NULL) { 713 print_tag(pd->pc, pd->tag); 714 printf("Failed to alloc I/O ext. for bus %d\n", 715 pd->ppb->busno); 716 return -1; 717 } 718 continue; 719 } 720 if (!pb->io_32bit && pi->address > 0xFFFF) { 721 pi->address = 0; 722 pd->enable &= ~PCI_CONF_ENABLE_IO; 723 } else { 724 pd->enable |= PCI_CONF_ENABLE_IO; 725 } 726 if (pci_conf_debug) { 727 print_tag(pd->pc, pd->tag); 728 printf("Putting %" PRIu64 " I/O bytes @ %#" PRIx64 729 " (reg %x)\n", pi->size, pi->address, pi->reg); 730 } 731 pci_conf_write(pd->pc, pd->tag, pi->reg, 732 PCI_MAPREG_IO_ADDR(pi->address) | PCI_MAPREG_TYPE_IO); 733 } 734 return 0; 735 } 736 737 static int 738 setup_memwins(pciconf_bus_t *pb) 739 { 740 pciconf_win_t *pm; 741 pciconf_dev_t *pd; 742 pcireg_t base; 743 struct extent *ex; 744 745 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 746 if (pm->size == 0) 747 continue; 748 749 pd = pm->dev; 750 ex = (pm->prefetch) ? pb->pmemext : pb->memext; 751 pm->address = pci_allocate_range(ex, pm->size, pm->align); 752 if (pm->address == -1) { 753 print_tag(pd->pc, pd->tag); 754 printf( 755 "Failed to allocate PCI memory space (%" PRIu64 756 " req)\n", pm->size); 757 return -1; 758 } 759 if (pd->ppb && pm->reg == 0) { 760 ex = extent_create("pciconf", pm->address, 761 pm->address + pm->size, M_DEVBUF, NULL, 0, 762 EX_NOWAIT); 763 if (ex == NULL) { 764 print_tag(pd->pc, pd->tag); 765 printf("Failed to alloc MEM ext. for bus %d\n", 766 pd->ppb->busno); 767 return -1; 768 } 769 if (pm->prefetch) { 770 pd->ppb->pmemext = ex; 771 } else { 772 pd->ppb->memext = ex; 773 } 774 continue; 775 } 776 if (pm->prefetch && !pb->pmem_64bit && 777 pm->address > 0xFFFFFFFFULL) { 778 pm->address = 0; 779 pd->enable &= ~PCI_CONF_ENABLE_MEM; 780 } else { 781 pd->enable |= PCI_CONF_ENABLE_MEM; 782 } 783 if (pm->reg != PCI_MAPREG_ROM) { 784 if (pci_conf_debug) { 785 print_tag(pd->pc, pd->tag); 786 printf( 787 "Putting %" PRIu64 " MEM bytes @ %#" 788 PRIx64 " (reg %x)\n", pm->size, 789 pm->address, pm->reg); 790 } 791 base = pci_conf_read(pd->pc, pd->tag, pm->reg); 792 base = PCI_MAPREG_MEM_ADDR(pm->address) | 793 PCI_MAPREG_MEM_TYPE(base); 794 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 795 if (PCI_MAPREG_MEM_TYPE(base) == 796 PCI_MAPREG_MEM_TYPE_64BIT) { 797 base = (pcireg_t) 798 (PCI_MAPREG_MEM64_ADDR(pm->address) >> 32); 799 pci_conf_write(pd->pc, pd->tag, pm->reg + 4, 800 base); 801 } 802 } 803 } 804 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 805 if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) { 806 pd = pm->dev; 807 if (pci_conf_debug) { 808 print_tag(pd->pc, pd->tag); 809 printf( 810 "Putting %" PRIu64 " ROM bytes @ %#" 811 PRIx64 " (reg %x)\n", pm->size, 812 pm->address, pm->reg); 813 } 814 base = (pcireg_t) (pm->address | PCI_MAPREG_ROM_ENABLE); 815 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 816 } 817 } 818 return 0; 819 } 820 821 /* 822 * Configure I/O, memory, and prefetcable memory spaces, then make 823 * a call to configure_bus(). 824 */ 825 static int 826 configure_bridge(pciconf_dev_t *pd) 827 { 828 unsigned long io_base, io_limit, mem_base, mem_limit; 829 pciconf_bus_t *pb; 830 pcireg_t io, iohigh, mem, cmd; 831 int rv; 832 833 pb = pd->ppb; 834 /* Configure I/O base & limit*/ 835 if (pb->ioext) { 836 io_base = pb->ioext->ex_start; 837 io_limit = pb->ioext->ex_end; 838 } else { 839 io_base = 0x1000; /* 4K */ 840 io_limit = 0x0000; 841 } 842 if (pb->io_32bit) { 843 iohigh = 844 ((io_base >> 16) << PCI_BRIDGE_IOHIGH_BASE_SHIFT) | 845 ((io_limit >> 16) << PCI_BRIDGE_IOHIGH_LIMIT_SHIFT); 846 } else { 847 if (io_limit > 0xFFFF) { 848 printf("Bus %d bridge does not support 32-bit I/O. ", 849 pb->busno); 850 printf("Disabling I/O accesses\n"); 851 io_base = 0x1000; /* 4K */ 852 io_limit = 0x0000; 853 } 854 iohigh = 0; 855 } 856 io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG) & 857 (PCI_BRIDGE_STATIO_STATUS_MASK << PCI_BRIDGE_STATIO_STATUS_SHIFT); 858 io |= (((io_base >> 8) & PCI_BRIDGE_STATIO_IOBASE_MASK) 859 << PCI_BRIDGE_STATIO_IOBASE_SHIFT); 860 io |= (((io_limit >> 8) & PCI_BRIDGE_STATIO_IOLIMIT_MASK) 861 << PCI_BRIDGE_STATIO_IOLIMIT_SHIFT); 862 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io); 863 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh); 864 865 /* Configure mem base & limit */ 866 if (pb->memext) { 867 mem_base = pb->memext->ex_start; 868 mem_limit = pb->memext->ex_end; 869 } else { 870 mem_base = 0x100000; /* 1M */ 871 mem_limit = 0x000000; 872 } 873 #if ULONG_MAX > 0xffffffff 874 if (mem_limit > 0xFFFFFFFFULL) { 875 printf("Bus %d bridge MEM range out of range. ", pb->busno); 876 printf("Disabling MEM accesses\n"); 877 mem_base = 0x100000; /* 1M */ 878 mem_limit = 0x000000; 879 } 880 #endif 881 mem = (((mem_base >> 20) & PCI_BRIDGE_MEMORY_BASE_MASK) 882 << PCI_BRIDGE_MEMORY_BASE_SHIFT); 883 mem |= (((mem_limit >> 20) & PCI_BRIDGE_MEMORY_LIMIT_MASK) 884 << PCI_BRIDGE_MEMORY_LIMIT_SHIFT); 885 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem); 886 887 /* Configure prefetchable mem base & limit */ 888 if (pb->pmemext) { 889 mem_base = pb->pmemext->ex_start; 890 mem_limit = pb->pmemext->ex_end; 891 } else { 892 mem_base = 0x100000; /* 1M */ 893 mem_limit = 0x000000; 894 } 895 mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG); 896 #if ULONG_MAX > 0xffffffff 897 if (!PCI_BRIDGE_PREFETCHMEM_64BITS(mem) && mem_limit > 0xFFFFFFFFULL) { 898 printf("Bus %d bridge does not support 64-bit PMEM. ", 899 pb->busno); 900 printf("Disabling prefetchable-MEM accesses\n"); 901 mem_base = 0x100000; /* 1M */ 902 mem_limit = 0x000000; 903 } 904 #endif 905 mem = (((mem_base >> 20) & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) 906 << PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT); 907 mem |= (((mem_limit >> 20) & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) 908 << PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT); 909 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem); 910 /* 911 * XXX -- 64-bit systems need a lot more than just this... 912 */ 913 if (sizeof(u_long) > 4) { 914 mem_base = (int64_t) mem_base >> 32; 915 mem_limit = (int64_t) mem_limit >> 32; 916 } 917 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHBASE32_REG, 918 mem_base & 0xffffffff); 919 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHLIMIT32_REG, 920 mem_limit & 0xffffffff); 921 922 rv = configure_bus(pb); 923 924 if (pb->ioext) 925 extent_destroy(pb->ioext); 926 if (pb->memext) 927 extent_destroy(pb->memext); 928 if (pb->pmemext) 929 extent_destroy(pb->pmemext); 930 if (rv == 0) { 931 cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG); 932 cmd &= PCI_BRIDGE_CONTROL_MASK; 933 cmd |= (PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR) 934 << PCI_BRIDGE_CONTROL_SHIFT; 935 if (pb->fast_b2b) { 936 cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B 937 << PCI_BRIDGE_CONTROL_SHIFT; 938 } 939 pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd); 940 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 941 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 942 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 943 } 944 945 return rv; 946 } 947 948 /* 949 * Calculate latency values, allocate I/O and MEM segments, then set them 950 * up. If a PCI-PCI bridge is found, configure the bridge separately, 951 * which will cause a recursive call back here. 952 */ 953 static int 954 configure_bus(pciconf_bus_t *pb) 955 { 956 pciconf_dev_t *pd; 957 int def_ltim, max_ltim, band, bus_mhz; 958 959 if (pb->ndevs == 0) { 960 if (pci_conf_debug) 961 printf("PCI bus %d - no devices\n", pb->busno); 962 return (1); 963 } 964 bus_mhz = pb->freq_66 ? 66 : 33; 965 max_ltim = pb->max_mingnt * bus_mhz / 4; /* cvt to cycle count */ 966 band = 40000000; /* 0.25us cycles/sec */ 967 if (band < pb->bandwidth_used) { 968 printf("PCI bus %d: Warning: Total bandwidth exceeded!?\n", 969 pb->busno); 970 def_ltim = -1; 971 } else { 972 def_ltim = (band - pb->bandwidth_used) / pb->ndevs; 973 if (def_ltim > pb->min_maxlat) 974 def_ltim = pb->min_maxlat; 975 def_ltim = def_ltim * bus_mhz / 4; 976 } 977 def_ltim = (def_ltim + 7) & ~7; 978 max_ltim = (max_ltim + 7) & ~7; 979 980 pb->def_ltim = MIN( def_ltim, 255 ); 981 pb->max_ltim = MIN( MAX(max_ltim, def_ltim ), 255 ); 982 983 /* 984 * Now we have what we need to initialize the devices. 985 * It would probably be better if we could allocate all of these 986 * for all busses at once, but "not right now". First, get a list 987 * of free memory ranges from the m.d. system. 988 */ 989 if (setup_iowins(pb) || setup_memwins(pb)) { 990 printf("PCI bus configuration failed: "); 991 printf("unable to assign all I/O and memory ranges."); 992 return -1; 993 } 994 995 /* 996 * Configure the latency for the devices, and enable them. 997 */ 998 for (pd=pb->device ; pd < &pb->device[pb->ndevs] ; pd++) { 999 pcireg_t cmd, class, misc; 1000 int ltim; 1001 1002 if (pci_conf_debug) { 1003 print_tag(pd->pc, pd->tag); 1004 printf("Configuring device.\n"); 1005 } 1006 class = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG); 1007 misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG); 1008 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 1009 if (pd->enable & PCI_CONF_ENABLE_PARITY) 1010 cmd |= PCI_COMMAND_PARITY_ENABLE; 1011 if (pd->enable & PCI_CONF_ENABLE_SERR) 1012 cmd |= PCI_COMMAND_SERR_ENABLE; 1013 if (pb->fast_b2b) 1014 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE; 1015 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 1016 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_PCI) { 1017 if (pd->enable & PCI_CONF_ENABLE_IO) 1018 cmd |= PCI_COMMAND_IO_ENABLE; 1019 if (pd->enable & PCI_CONF_ENABLE_MEM) 1020 cmd |= PCI_COMMAND_MEM_ENABLE; 1021 if (pd->enable & PCI_CONF_ENABLE_BM) 1022 cmd |= PCI_COMMAND_MASTER_ENABLE; 1023 ltim = pd->min_gnt * bus_mhz / 4; 1024 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim); 1025 } else { 1026 cmd |= PCI_COMMAND_MASTER_ENABLE; 1027 ltim = MIN (pb->def_ltim, pb->max_ltim); 1028 } 1029 if ((pd->enable & 1030 (PCI_CONF_ENABLE_MEM|PCI_CONF_ENABLE_IO)) == 0) { 1031 print_tag(pd->pc, pd->tag); 1032 printf("Disabled due to lack of resources.\n"); 1033 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 1034 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 1035 } 1036 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 1037 1038 misc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) | 1039 (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)); 1040 misc |= (ltim & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT; 1041 misc |= ((pb->cacheline_size >> 2) & PCI_CACHELINE_MASK) << 1042 PCI_CACHELINE_SHIFT; 1043 pci_conf_write(pd->pc, pd->tag, PCI_BHLC_REG, misc); 1044 1045 if (pd->ppb) { 1046 if (configure_bridge(pd) < 0) 1047 return -1; 1048 continue; 1049 } 1050 } 1051 1052 if (pci_conf_debug) { 1053 printf("PCI bus %d configured\n", pb->busno); 1054 } 1055 1056 return 0; 1057 } 1058 1059 /* 1060 * Let's configure the PCI bus. 1061 * This consists of basically scanning for all existing devices, 1062 * identifying their needs, and then making another pass over them 1063 * to set: 1064 * 1. I/O addresses 1065 * 2. Memory addresses (Prefetchable and not) 1066 * 3. PCI command register 1067 * 4. The latency part of the PCI BHLC (BIST (Built-In Self Test), 1068 * Header type, Latency timer, Cache line size) register 1069 * 1070 * The command register is set to enable fast back-to-back transactions 1071 * if the host bridge says it can handle it. We also configure 1072 * Master Enable, SERR enable, parity enable, and (if this is not a 1073 * PCI-PCI bridge) the I/O and Memory spaces. Apparently some devices 1074 * will not report some I/O space. 1075 * 1076 * The latency is computed to be a "fair share" of the bus bandwidth. 1077 * The bus bandwidth variable is initialized to the number of PCI cycles 1078 * in one second. The number of cycles taken for one transaction by each 1079 * device (MAX_LAT + MIN_GNT) is then subtracted from the bandwidth. 1080 * Care is taken to ensure that the latency timer won't be set such that 1081 * it would exceed the critical time for any device. 1082 * 1083 * This is complicated somewhat due to the presence of bridges. PCI-PCI 1084 * bridges are probed and configured recursively. 1085 */ 1086 int 1087 pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext, 1088 struct extent *memext, struct extent *pmemext, int firstbus, 1089 int cacheline_size) 1090 { 1091 pciconf_bus_t *pb; 1092 int rv; 1093 1094 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 1095 pb->busno = firstbus; 1096 pb->next_busno = pb->busno + 1; 1097 pb->last_busno = 255; 1098 pb->cacheline_size = cacheline_size; 1099 pb->parent_bus = NULL; 1100 pb->swiz = 0; 1101 pb->io_32bit = 1; 1102 pb->pmem_64bit = 0; 1103 pb->ioext = ioext; 1104 pb->memext = memext; 1105 if (pmemext == NULL) { 1106 pb->pmemext = memext; 1107 } else { 1108 pb->pmemext = pmemext; 1109 } 1110 pb->pc = pc; 1111 pb->io_total = pb->mem_total = pb->pmem_total = 0; 1112 1113 rv = probe_bus(pb); 1114 pb->last_busno = pb->next_busno-1; 1115 if (rv == 0) { 1116 rv = configure_bus(pb); 1117 } 1118 1119 /* 1120 * All done! 1121 */ 1122 free(pb, M_DEVBUF); 1123 return rv; 1124 } 1125
Indexes created Mon Sep 22 13:09:51 GMT 2025