pciconf.c revision 1.3
1 /* $NetBSD: pciconf.c,v 1.3 2001/05/27 17:50:40 thorpej Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Derived in part from code from PMON/2000 (http://pmon.groupbsd.org/). 39 */ 40 41 /* 42 * To do: 43 * - Deal with "anything can be hot-plugged" -- i.e., carry configuration 44 * information around & be able to reconfigure on the fly. 45 * - Deal with segments (See IA64 System Abstraction Layer) 46 * - Deal with subtractive bridges (& non-spec positive/subtractive decode) 47 * - Deal with ISA/VGA/VGA palette snooping 48 * - Deal with device capabilities on bridges 49 * - Worry about changing a bridge to/from transparency. 50 */ 51 52 #include "opt_pci.h" 53 54 #include <sys/param.h> 55 #include <sys/extent.h> 56 #include <sys/queue.h> 57 #include <sys/systm.h> 58 #include <sys/malloc.h> 59 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pciconf.h> 62 #include <dev/pci/pcidevs.h> 63 64 int pci_conf_debug = 0; 65 66 #if !defined(MIN) 67 #define MIN(a,b) (((a)<(b))?(a):(b)) 68 #define MAX(a,b) (((a)>(b))?(a):(b)) 69 #endif 70 71 /* per-bus constants. */ 72 #define MAX_CONF_DEV 8 /* Arbitrary */ 73 #define MAX_CONF_MEM (3 * MAX_CONF_DEV) /* Avg. 3 per device -- Arb. */ 74 #define MAX_CONF_IO (1 * MAX_CONF_DEV) /* Avg. 1 per device -- Arb. */ 75 76 #define PCI_BUSNO_SPACING (1 << 5) 77 78 struct _s_pciconf_bus_t; /* Forward declaration */ 79 80 typedef struct _s_pciconf_dev_t { 81 int ipin; 82 int iline; 83 int min_gnt; 84 int max_lat; 85 int enable; 86 pcitag_t tag; 87 pci_chipset_tag_t pc; 88 struct _s_pciconf_bus_t *ppb; /* I am really a bridge */ 89 } pciconf_dev_t; 90 91 typedef struct _s_pciconf_win_t { 92 pciconf_dev_t *dev; 93 int reg; /* 0 for busses */ 94 int align; 95 int prefetch; 96 u_int64_t size; 97 u_int64_t address; 98 } pciconf_win_t; 99 100 typedef struct _s_pciconf_bus_t { 101 int busno; 102 int next_busno; 103 int last_busno; 104 int busno_spacing; 105 int max_mingnt; 106 int min_maxlat; 107 int prefetch; 108 int fast_b2b; 109 int freq_66; 110 int def_ltim; 111 int max_ltim; 112 int bandwidth_used; 113 int swiz; 114 int io_32bit; 115 int pmem_64bit; 116 117 int ndevs; 118 pciconf_dev_t device[MAX_CONF_DEV]; 119 120 /* These should be sorted in order of decreasing size */ 121 int nmemwin; 122 pciconf_win_t pcimemwin[MAX_CONF_MEM]; 123 int niowin; 124 pciconf_win_t pciiowin[MAX_CONF_IO]; 125 126 bus_size_t io_total; 127 bus_size_t mem_total; 128 bus_size_t pmem_total; 129 130 struct extent *ioext; 131 struct extent *memext; 132 struct extent *pmemext; 133 134 pci_chipset_tag_t pc; 135 struct _s_pciconf_bus_t *parent_bus; 136 } pciconf_bus_t; 137 138 static int probe_bus(pciconf_bus_t *); 139 static void alloc_busno(pciconf_bus_t *, pciconf_bus_t *); 140 static int pci_do_device_query(pciconf_bus_t *, pcitag_t, int, int); 141 static int setup_iowins(pciconf_bus_t *); 142 static int setup_memwins(pciconf_bus_t *); 143 static int configure_bridge(pciconf_dev_t *); 144 static int configure_bus(pciconf_bus_t *); 145 static u_int64_t pci_allocate_range(struct extent *, u_int64_t, int); 146 static pciconf_win_t *get_io_desc(pciconf_bus_t *, bus_size_t); 147 static pciconf_win_t *get_mem_desc(pciconf_bus_t *, bus_size_t); 148 static pciconf_bus_t *query_bus(pciconf_bus_t *, pciconf_dev_t *, int); 149 150 static void print_tag(pci_chipset_tag_t, pcitag_t); 151 152 static void 153 print_tag(pci_chipset_tag_t pc, pcitag_t tag) 154 { 155 int bus, dev, func; 156 157 pci_decompose_tag(pc, tag, &bus, &dev, &func); 158 printf("PCI: bus %d, device %d, function %d: ", bus, dev, func); 159 } 160 161 /************************************************************************/ 162 /************************************************************************/ 163 /*********************** Bus probing routines ***********************/ 164 /************************************************************************/ 165 /************************************************************************/ 166 static pciconf_win_t * 167 get_io_desc(pciconf_bus_t *pb, bus_size_t size) 168 { 169 int i, n; 170 171 n = pb->niowin; 172 for (i=n; i > 0 && size > pb->pciiowin[i-1].size; i--) 173 pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */ 174 return &pb->pciiowin[i]; 175 } 176 177 static pciconf_win_t * 178 get_mem_desc(pciconf_bus_t *pb, bus_size_t size) 179 { 180 int i, n; 181 182 n = pb->nmemwin; 183 for (i=n; i > 0 && size > pb->pcimemwin[i-1].size; i--) 184 pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */ 185 return &pb->pcimemwin[i]; 186 } 187 188 /* 189 * Set up bus common stuff, then loop over devices & functions. 190 * If we find something, call pci_do_device_query()). 191 */ 192 static int 193 probe_bus(pciconf_bus_t *pb) 194 { 195 int device, maxdevs; 196 197 maxdevs = pci_bus_maxdevs(pb->pc, pb->busno); 198 pb->ndevs = 0; 199 pb->niowin = 0; 200 pb->nmemwin = 0; 201 pb->freq_66 = 1; 202 pb->fast_b2b = 1; 203 pb->prefetch = 1; 204 pb->max_mingnt = 0; /* we are looking for the maximum */ 205 pb->min_maxlat = 0x100; /* we are looking for the minimum */ 206 pb->bandwidth_used = 0; 207 for (device=0; device < maxdevs; device++) { 208 pcitag_t tag; 209 pcireg_t id, bhlcr; 210 int function, nfunction; 211 212 tag = pci_make_tag(pb->pc, pb->busno, device, 0); 213 if (pci_conf_debug) { 214 print_tag(pb->pc, tag); 215 printf("probing.\n"); 216 } 217 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 218 219 /* Invalid vendor ID value? */ 220 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 221 continue; 222 223 bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 224 nfunction = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 225 for (function = 0 ; function < nfunction ; function++) { 226 tag = pci_make_tag(pb->pc, pb->busno, device, function); 227 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 228 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 229 continue; 230 if (pb->ndevs+1 < MAX_CONF_DEV) { 231 if (pci_conf_debug) { 232 print_tag(pb->pc, tag); 233 printf("Found dev 0x%04x 0x%04x -- " 234 "really probing.\n", 235 PCI_VENDOR(id), PCI_PRODUCT(id)); 236 } 237 if (pci_do_device_query(pb, tag, device, 238 function)) 239 return -1; 240 pb->ndevs++; 241 } 242 } 243 } 244 return 0; 245 } 246 247 static void 248 alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb) 249 { 250 pb->busno = parent->next_busno; 251 if (parent->next_busno + parent->busno_spacing > parent->last_busno) 252 panic("Too many PCI busses on bus %d", parent->busno); 253 parent->next_busno = parent->next_busno + parent->busno_spacing; 254 pb->next_busno = pb->busno+1; 255 pb->busno_spacing = parent->busno_spacing >> 1; 256 if (!pb->busno_spacing) 257 panic("PCI busses nested too deep."); 258 pb->last_busno = parent->next_busno - 1; 259 } 260 261 static pciconf_bus_t * 262 query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev) 263 { 264 pciconf_bus_t *pb; 265 pcireg_t busreg, io, pmem; 266 pciconf_win_t *pi, *pm; 267 268 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 269 if (!pb) 270 panic("Unable to allocate memory for PCI configuration."); 271 272 pb->parent_bus = parent; 273 alloc_busno(parent, pb); 274 if (pci_conf_debug) 275 printf("PCI bus bridge covers busses %d-%d\n", 276 pb->busno, pb->last_busno); 277 278 busreg = parent->busno << PCI_BRIDGE_BUS_PRIMARY_SHIFT; 279 busreg |= pb->busno << PCI_BRIDGE_BUS_SECONDARY_SHIFT; 280 busreg |= pb->last_busno << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 281 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_BUS_REG, busreg); 282 283 pb->swiz = parent->swiz + dev; 284 285 pb->ioext = NULL; 286 pb->memext = NULL; 287 pb->pmemext = NULL; 288 pb->pc = parent->pc; 289 pb->io_total = pb->mem_total = pb->pmem_total = 0; 290 291 pb->io_32bit = 0; 292 if (parent->io_32bit) { 293 io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG); 294 if (PCI_BRIDGE_IO_32BITS(io)) { 295 pb->io_32bit = 1; 296 } 297 } 298 299 pb->pmem_64bit = 0; 300 if (parent->pmem_64bit) { 301 pmem = pci_conf_read(pb->pc, pd->tag, 302 PCI_BRIDGE_PREFETCHMEM_REG); 303 if (PCI_BRIDGE_PREFETCHMEM_64BITS(pmem)) { 304 pb->pmem_64bit = 1; 305 } 306 } 307 308 if (probe_bus(pb)) { 309 printf("Failed to probe bus %d\n", pb->busno); 310 goto err; 311 } 312 313 if (pb->io_total > 0) { 314 if (parent->niowin >= MAX_CONF_IO) { 315 printf("pciconf: too many I/O windows"); 316 goto err; 317 } 318 pb->io_total |= 0xfff; /* Round up */ 319 pi = get_io_desc(parent, pb->io_total); 320 pi->dev = pd; 321 pi->reg = 0; 322 pi->size = pb->io_total; 323 pi->align = 0x1000; /* 4K alignment */ 324 pi->prefetch = 0; 325 parent->niowin++; 326 parent->io_total += pb->io_total; 327 } 328 329 if (pb->mem_total > 0) { 330 if (parent->nmemwin >= MAX_CONF_MEM) { 331 printf("pciconf: too many MEM windows"); 332 goto err; 333 } 334 pb->mem_total |= 0xfffff; /* Round up */ 335 pm = get_mem_desc(parent, pb->mem_total); 336 pm->dev = pd; 337 pm->reg = 0; 338 pm->size = pb->mem_total; 339 pm->align = 0x100000; /* 1M alignment */ 340 pm->prefetch = 0; 341 parent->nmemwin++; 342 parent->mem_total += pb->mem_total; 343 } 344 345 if (pb->pmem_total > 0) { 346 if (parent->nmemwin >= MAX_CONF_MEM) { 347 printf("pciconf: too many MEM windows"); 348 goto err; 349 } 350 pb->pmem_total |= 0xfffff; /* Round up */ 351 pm = get_mem_desc(parent, pb->pmem_total); 352 pm->dev = pd; 353 pm->reg = 0; 354 pm->size = pb->pmem_total; 355 pm->align = 0x100000; /* 1M alignment */ 356 pm->prefetch = 1; 357 parent->nmemwin++; 358 parent->pmem_total += pb->pmem_total; 359 } 360 361 return pb; 362 err: 363 free(pb, M_DEVBUF); 364 return NULL; 365 } 366 367 static int 368 pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func) 369 { 370 pciconf_dev_t *pd; 371 pciconf_win_t *pi, *pm; 372 pcireg_t class, cmd, icr, bar, mask, bar64, mask64; 373 u_int64_t size; 374 int br, width; 375 376 pd = &pb->device[pb->ndevs]; 377 pd->pc = pb->pc; 378 pd->tag = tag; 379 pd->ppb = NULL; 380 pd->enable = 1; 381 382 class = pci_conf_read(pb->pc, tag, PCI_CLASS_REG); 383 384 cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG); 385 386 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE) { 387 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 388 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 389 pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd); 390 } else if (pci_conf_debug) { 391 print_tag(pb->pc, tag); 392 printf("device is a bridge; not clearing enables\n"); 393 } 394 395 if ((cmd & PCI_STATUS_BACKTOBACK_SUPPORT) == 0) 396 pb->fast_b2b = 0; 397 398 if ((cmd & PCI_STATUS_66MHZ_SUPPORT) == 0) 399 pb->freq_66 = 0; 400 401 if ( (PCI_CLASS(class) == PCI_CLASS_BRIDGE) 402 && (PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_PCI)) { 403 pd->ppb = query_bus(pb, pd, dev); 404 if (pd->ppb == NULL) 405 return -1; 406 return 0; 407 } 408 409 icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG); 410 pd->ipin = PCI_INTERRUPT_PIN(icr); 411 pd->iline = PCI_INTERRUPT_LINE(icr); 412 pd->min_gnt = PCI_MIN_GNT(icr); 413 pd->max_lat = PCI_MAX_LAT(icr); 414 if (pd->iline || pd->ipin) { 415 pci_conf_interrupt(pb->pc, pb->busno, dev, func, pb->swiz, 416 &pd->iline); 417 icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 418 icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT); 419 pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr); 420 } 421 422 if (pd->min_gnt != 0 || pd->max_lat != 0) { 423 if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt) 424 pb->max_mingnt = pd->min_gnt; 425 426 if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat) 427 pb->min_maxlat = pd->max_lat; 428 429 pb->bandwidth_used += pd->min_gnt * 4000000 / 430 (pd->min_gnt + pd->max_lat); 431 } 432 433 width = 4; 434 for (br = PCI_MAPREG_START; br < PCI_MAPREG_END; br += width) { 435 #if 0 436 if (PCI_CLASS(class) == PCI_CLASS_MASS_STORAGE && 437 PCI_SUBCLASS(class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 438 break; 439 } 440 #endif 441 bar = pci_conf_read(pb->pc, tag, br); 442 pci_conf_write(pb->pc, tag, br, 0xffffffff); 443 mask = pci_conf_read(pb->pc, tag, br); 444 pci_conf_write(pb->pc, tag, br, bar); 445 width = 4; 446 447 if (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO) { 448 /* Upper 16 bits must be one. */ 449 /* XXXJRT -- is this really true? */ 450 mask |= 0xffff0000; 451 452 size = PCI_MAPREG_IO_SIZE(mask); 453 if (size == 0) { 454 if (pci_conf_debug) { 455 print_tag(pb->pc, tag); 456 printf("I/O BAR 0x%x is void\n", br); 457 } 458 continue; 459 } 460 461 if (pb->niowin >= MAX_CONF_IO) { 462 printf("pciconf: too many I/O windows"); 463 return -1; 464 } 465 466 pi = get_io_desc(pb, size); 467 pi->dev = pd; 468 pi->reg = br; 469 pi->size = (u_int64_t) size; 470 pi->align = 4; 471 pi->prefetch = 0; 472 if (pci_conf_debug) { 473 print_tag(pb->pc, tag); 474 printf("Register 0x%x, I/O size %llu\n", 475 br, pi->size); 476 } 477 pb->niowin++; 478 pb->io_total += size; 479 } else { 480 switch (PCI_MAPREG_MEM_TYPE(mask)) { 481 case PCI_MAPREG_MEM_TYPE_32BIT: 482 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 483 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 484 break; 485 case PCI_MAPREG_MEM_TYPE_64BIT: 486 bar64 = pci_conf_read(pb->pc, tag, br + 4); 487 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); 488 mask64 = pci_conf_read(pb->pc, tag, br + 4); 489 pci_conf_write(pb->pc, tag, br + 4, bar64); 490 size = (u_int64_t) PCI_MAPREG_MEM64_SIZE( 491 (((u_int64_t) mask64) << 32) | mask); 492 width = 8; 493 continue; 494 default: 495 print_tag(pb->pc, tag); 496 printf("reserved mapping type 0x%x\n", 497 PCI_MAPREG_MEM_TYPE(mask)); 498 continue; 499 } 500 501 if (size == 0) { 502 if (pci_conf_debug) { 503 print_tag(pb->pc, tag); 504 printf("MEM%d BAR 0x%x is void\n", 505 PCI_MAPREG_MEM_TYPE(mask) == 506 PCI_MAPREG_MEM_TYPE_64BIT ? 507 64 : 32, br); 508 } 509 continue; 510 } 511 512 if (pb->nmemwin >= MAX_CONF_MEM) { 513 printf("pciconf: too many memory windows"); 514 return -1; 515 } 516 517 pm = get_mem_desc(pb, size); 518 pm->dev = pd; 519 pm->reg = br; 520 pm->size = size; 521 pm->align = 4; 522 pm->prefetch = PCI_MAPREG_MEM_PREFETCHABLE(mask); 523 if (pci_conf_debug) { 524 print_tag(pb->pc, tag); 525 printf("Register 0x%x, memory size %llu\n", 526 br, pm->size); 527 } 528 pb->nmemwin++; 529 if (pm->prefetch) { 530 pb->pmem_total += size; 531 } else { 532 pb->mem_total += size; 533 } 534 } 535 } 536 537 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 538 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 539 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 540 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, bar); 541 542 if (mask != 0 && mask != 0xffffffff) { 543 if (pb->nmemwin >= MAX_CONF_MEM) { 544 printf("pciconf: too many memory windows"); 545 return -1; 546 } 547 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 548 549 pm = get_mem_desc(pb, size); 550 pm->dev = pd; 551 pm->reg = PCI_MAPREG_ROM; 552 pm->size = size; 553 pm->align = 4; 554 pm->prefetch = 1; 555 if (pci_conf_debug) { 556 print_tag(pb->pc, tag); 557 printf("Expansion ROM memory size %llu\n", pm->size); 558 } 559 pb->nmemwin++; 560 pb->pmem_total += size; 561 } 562 563 return 0; 564 } 565 566 /************************************************************************/ 567 /************************************************************************/ 568 /******************** Bus configuration routines ********************/ 569 /************************************************************************/ 570 /************************************************************************/ 571 static u_int64_t 572 pci_allocate_range(struct extent *ex, u_int64_t amt, int align) 573 { 574 int r; 575 u_long addr; 576 577 r = extent_alloc(ex, amt, align, 0, EX_NOWAIT, &addr); 578 if (r) { 579 addr = (u_long) -1; 580 printf("extent_alloc() returned %d\n", r); 581 } 582 return (pcireg_t) addr; 583 } 584 585 static int 586 setup_iowins(pciconf_bus_t *pb) 587 { 588 pciconf_win_t *pi; 589 pciconf_dev_t *pd; 590 591 for (pi=pb->pciiowin; pi < &pb->pciiowin[pb->niowin] ; pi++) { 592 if (pi->size == 0) 593 continue; 594 595 pd = pi->dev; 596 pi->address = pci_allocate_range(pb->ioext, pi->size, 597 pi->align); 598 if (pi->address == -1) { 599 print_tag(pd->pc, pd->tag); 600 printf("Failed to allocate PCI I/O space (%llu req)\n", 601 pi->size); 602 return -1; 603 } 604 if (!pb->io_32bit && pi->address > 0xFFFF) { 605 pi->address = 0; 606 pd->enable = 0; 607 } 608 if (pd->ppb && pi->reg == 0) { 609 pd->ppb->ioext = extent_create("pciconf", pi->address, 610 pi->address + pi->size, M_DEVBUF, NULL, 0, 611 EX_NOWAIT); 612 if (pd->ppb->ioext == NULL) { 613 print_tag(pd->pc, pd->tag); 614 printf("Failed to alloc I/O ext. for bus %d\n", 615 pd->ppb->busno); 616 return -1; 617 } 618 continue; 619 } 620 if (pci_conf_debug) { 621 print_tag(pd->pc, pd->tag); 622 printf("Putting %llu I/O bytes @ %#llx (reg %x)\n", 623 pi->size, pi->address, pi->reg); 624 } 625 pci_conf_write(pd->pc, pd->tag, pi->reg, 626 PCI_MAPREG_IO_ADDR(pi->address) | PCI_MAPREG_TYPE_IO); 627 } 628 return 0; 629 } 630 631 static int 632 setup_memwins(pciconf_bus_t *pb) 633 { 634 pciconf_win_t *pm; 635 pciconf_dev_t *pd; 636 pcireg_t base; 637 struct extent *ex; 638 639 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 640 if (pm->size == 0) 641 continue; 642 643 pd = pm->dev; 644 ex = (pm->prefetch) ? pb->pmemext : pb->memext; 645 pm->address = pci_allocate_range(ex, pm->size, pm->align); 646 if (pm->address == -1) { 647 print_tag(pd->pc, pd->tag); 648 printf( 649 "Failed to allocate PCI memory space (%llu req)\n", 650 pm->size); 651 return -1; 652 } 653 if (pd->ppb && pm->reg == 0) { 654 ex = extent_create("pciconf", pm->address, 655 pm->address + pm->size, M_DEVBUF, NULL, 0, 656 EX_NOWAIT); 657 if (ex == NULL) { 658 print_tag(pd->pc, pd->tag); 659 printf("Failed to alloc MEM ext. for bus %d\n", 660 pd->ppb->busno); 661 return -1; 662 } 663 if (pm->prefetch) { 664 pd->ppb->pmemext = ex; 665 } else { 666 pd->ppb->memext = ex; 667 } 668 continue; 669 } 670 if (pm->prefetch && !pb->pmem_64bit && 671 pm->address > 0xFFFFFFFFULL) { 672 pm->address = 0; 673 pd->enable = 0; 674 } 675 if (pm->reg != PCI_MAPREG_ROM) { 676 if (pci_conf_debug) { 677 print_tag(pd->pc, pd->tag); 678 printf( 679 "Putting %llu MEM bytes @ %#llx (reg %x)\n", 680 pm->size, pm->address, pm->reg); 681 } 682 base = pci_conf_read(pd->pc, pd->tag, pm->reg); 683 base = PCI_MAPREG_MEM_ADDR(pm->address) | 684 PCI_MAPREG_MEM_TYPE(base); 685 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 686 if (PCI_MAPREG_MEM_TYPE(base) == 687 PCI_MAPREG_MEM_TYPE_64BIT) { 688 base = (pcireg_t) 689 (PCI_MAPREG_MEM64_ADDR(pm->address) >> 32); 690 pci_conf_write(pd->pc, pd->tag, pm->reg + 4, 691 base); 692 } 693 } 694 } 695 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 696 if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) { 697 pd = pm->dev; 698 if (pci_conf_debug) { 699 print_tag(pd->pc, pd->tag); 700 printf( 701 "Putting %llu ROM bytes @ %#llx (reg %x)\n", 702 pm->size, pm->address, pm->reg); 703 } 704 base = ((pcireg_t) pm->address) | PCI_MAPREG_TYPE_ROM; 705 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 706 } 707 } 708 return 0; 709 } 710 711 /* 712 * Configure I/O, memory, and prefetcable memory spaces, then make 713 * a call to configure_bus(). 714 */ 715 static int 716 configure_bridge(pciconf_dev_t *pd) 717 { 718 unsigned long io_base, io_limit, mem_base, mem_limit; 719 pciconf_bus_t *pb; 720 pcireg_t io, iohigh, mem, cmd; 721 int rv; 722 723 pb = pd->ppb; 724 /* Configure I/O base & limit*/ 725 if (pb->ioext) { 726 io_base = pb->ioext->ex_start; 727 io_limit = pb->ioext->ex_end; 728 } else { 729 io_base = 0x1000; /* 4K */ 730 io_limit = 0x0000; 731 } 732 if (pb->io_32bit) { 733 iohigh = 734 ((io_base >> 16) << PCI_BRIDGE_IOHIGH_BASE_SHIFT) | 735 ((io_limit >> 16) << PCI_BRIDGE_IOHIGH_LIMIT_SHIFT); 736 } else { 737 if (io_limit > 0xFFFF) { 738 printf("Bus %d bridge does not support 32-bit I/O. ", 739 pb->busno); 740 printf("Disabling I/O accesses\n"); 741 io_base = 0x1000; /* 4K */ 742 io_limit = 0x0000; 743 } 744 iohigh = 0; 745 } 746 io &= (PCI_BRIDGE_STATIO_STATUS_MASK << 747 PCI_BRIDGE_STATIO_STATUS_SHIFT); 748 io |= (((io_base >> 8) & PCI_BRIDGE_STATIO_IOBASE_MASK) 749 << PCI_BRIDGE_STATIO_IOBASE_SHIFT); 750 io |= (((io_limit >> 8) & PCI_BRIDGE_STATIO_IOLIMIT_MASK) 751 << PCI_BRIDGE_STATIO_IOLIMIT_SHIFT); 752 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io); 753 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh); 754 755 /* Configure mem base & limit */ 756 if (pb->memext) { 757 mem_base = pb->memext->ex_start; 758 mem_limit = pb->memext->ex_end; 759 } else { 760 mem_base = 0x100000; /* 1M */ 761 mem_limit = 0x000000; 762 } 763 if (mem_limit > 0xFFFFFFFFULL) { 764 printf("Bus %d bridge MEM range out of range. ", pb->busno); 765 printf("Disabling MEM accesses\n"); 766 mem_base = 0x100000; /* 1M */ 767 mem_limit = 0x000000; 768 } 769 mem = (((mem_base >> 20) & PCI_BRIDGE_MEMORY_BASE_MASK) 770 << PCI_BRIDGE_MEMORY_BASE_SHIFT); 771 mem |= (((mem_limit >> 20) & PCI_BRIDGE_MEMORY_LIMIT_MASK) 772 << PCI_BRIDGE_MEMORY_LIMIT_SHIFT); 773 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem); 774 775 /* Configure prefetchable mem base & limit */ 776 if (pb->pmemext) { 777 mem_base = pb->pmemext->ex_start; 778 mem_limit = pb->pmemext->ex_end; 779 } else { 780 mem_base = 0x100000; /* 1M */ 781 mem_limit = 0x000000; 782 } 783 mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG); 784 if (!PCI_BRIDGE_PREFETCHMEM_64BITS(mem) && mem_limit > 0xFFFFFFFFULL) { 785 printf("Bus %d bridge does not support 64-bit PMEM. ", 786 pb->busno); 787 printf("Disabling prefetchable-MEM accesses\n"); 788 mem_base = 0x100000; /* 1M */ 789 mem_limit = 0x000000; 790 } 791 mem = (((mem_base >> 20) & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) 792 << PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT); 793 mem |= (((mem_limit >> 20) & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) 794 << PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT); 795 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem); 796 /* 797 * XXX -- 64-bit systems need a lot more than just this... 798 */ 799 if (sizeof(u_long) > 4) { 800 mem_base = (int64_t) mem_base >> 32; 801 mem_limit = (int64_t) mem_limit >> 32; 802 } 803 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHBASE32_REG, 804 mem_base & 0xffffffff); 805 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHLIMIT32_REG, 806 mem_limit & 0xffffffff); 807 808 rv = configure_bus(pb); 809 810 if (pb->ioext) 811 extent_destroy(pb->ioext); 812 if (pb->memext) 813 extent_destroy(pb->memext); 814 if (pb->pmemext) 815 extent_destroy(pb->pmemext); 816 if (rv == 0) { 817 cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG); 818 cmd &= PCI_BRIDGE_CONTROL_MASK; 819 cmd |= (PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR) 820 << PCI_BRIDGE_CONTROL_SHIFT; 821 if (pb->fast_b2b) { 822 cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B 823 << PCI_BRIDGE_CONTROL_SHIFT; 824 } 825 pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd); 826 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 827 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 828 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 829 } 830 831 return rv; 832 } 833 834 /* 835 * Calculate latency values, allocate I/O and MEM segments, then set them 836 * up. If a PCI-PCI bridge is found, configure the bridge separately, 837 * which will cause a recursive call back here. 838 */ 839 static int 840 configure_bus(pciconf_bus_t *pb) 841 { 842 pciconf_dev_t *pd; 843 int def_ltim, max_ltim, band; 844 845 /* MIN_GNT assumes a clock rate of 33MHz */ 846 max_ltim = pb->max_mingnt * 33 / 4; /* cvt to cycle count */ 847 band = 40000000; /* 0.25us cycles/sec */ 848 if (band < pb->bandwidth_used) { 849 printf("PCI bus %d: Warning: Total bandwidth exceeded!?\n", 850 pb->busno); 851 def_ltim = -1; 852 } else { 853 def_ltim = (band - pb->bandwidth_used) / pb->ndevs; 854 if (def_ltim > pb->min_maxlat) 855 def_ltim = pb->min_maxlat; 856 def_ltim = def_ltim * 33 / 4; 857 } 858 def_ltim = (def_ltim + 7) & ~7; 859 max_ltim = (max_ltim + 7) & ~7; 860 861 pb->def_ltim = MIN( def_ltim, 255 ); 862 pb->max_ltim = MIN( MAX(max_ltim, def_ltim ), 255 ); 863 864 /* 865 * Now we have what we need to initialize the devices. 866 * It would probably be better if we could allocate all of these 867 * for all busses at once, but "not right now". First, get a list 868 * of free memory ranges from the m.d. system. 869 */ 870 if (setup_iowins(pb) || setup_memwins(pb)) { 871 printf("PCI bus configuration failed: "); 872 printf("unable to assign all I/O and memory ranges."); 873 return -1; 874 } 875 876 /* 877 * Configure the latency for the devices, and enable them. 878 */ 879 for (pd=pb->device ; pd < &pb->device[pb->ndevs] ; pd++) { 880 pcireg_t cmd, class, misc; 881 int ltim; 882 883 if (pci_conf_debug) { 884 print_tag(pd->pc, pd->tag); 885 printf("Configuring device.\n"); 886 } 887 class = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG); 888 misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG); 889 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 890 cmd |= PCI_COMMAND_MASTER_ENABLE 891 | PCI_COMMAND_SERR_ENABLE 892 | PCI_COMMAND_PARITY_ENABLE; 893 if (pb->fast_b2b) 894 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE; 895 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 896 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_PCI) { 897 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 898 ltim = pd->min_gnt * 33 / 4; 899 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim); 900 } else { 901 ltim = MIN (pb->def_ltim, pb->max_ltim); 902 } 903 if (!pd->enable) { 904 print_tag(pd->pc, pd->tag); 905 printf("Disabled due to lack of resources.\n"); 906 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 907 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 908 } 909 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 910 911 misc = (misc & ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT)) 912 | ((ltim & 0xff) << PCI_LATTIMER_SHIFT); 913 pci_conf_write(pd->pc, pd->tag, PCI_BHLC_REG, misc); 914 915 if (pd->ppb) { 916 if (configure_bridge(pd) < 0) 917 return -1; 918 continue; 919 } 920 } 921 922 if (pci_conf_debug) { 923 printf("PCI bus %d configured\n", pb->busno); 924 } 925 926 return 0; 927 } 928 929 /* 930 * Let's configure the PCI bus. 931 * This consists of basically scanning for all existing devices, 932 * identifying their needs, and then making another pass over them 933 * to set: 934 * 1. I/O addresses 935 * 2. Memory addresses (Prefetchable and not) 936 * 3. PCI command register 937 * 4. The latency part of the PCI BHLC (BIST (Built-In Self Test), 938 * Header type, Latency timer, Cache line size) register 939 * 940 * The command register is set to enable fast back-to-back transactions 941 * if the host bridge says it can handle it. We also configure 942 * Master Enable, SERR enable, parity enable, and (if this is not a 943 * PCI-PCI bridge) the I/O and Memory spaces. Apparently some devices 944 * will not report some I/O space. 945 * 946 * The latency is computed to be a "fair share" of the bus bandwidth. 947 * The bus bandwidth variable is initialized to the number of PCI cycles 948 * in one second. The number of cycles taken for one transaction by each 949 * device (MAX_LAT + MIN_GNT) is then subtracted from the bandwidth. 950 * Care is taken to ensure that the latency timer won't be set such that 951 * it would exceed the critical time for any device. 952 * 953 * This is complicated somewhat due to the presence of bridges. PCI-PCI 954 * bridges are probed and configured recursively. 955 */ 956 int 957 pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext, 958 struct extent *memext, struct extent *pmemext) 959 { 960 pciconf_bus_t *pb; 961 int rv; 962 963 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 964 pb->busno = 0; 965 pb->busno_spacing = PCI_BUSNO_SPACING; 966 pb->next_busno = pb->busno + 1; 967 pb->last_busno = 255; 968 pb->parent_bus = NULL; 969 pb->swiz = 0; 970 pb->io_32bit = 1; 971 pb->pmem_64bit = 0; 972 pb->ioext = ioext; 973 pb->memext = memext; 974 if (pmemext == NULL) { 975 pb->pmemext = memext; 976 } else { 977 pb->pmemext = pmemext; 978 } 979 pb->pc = pc; 980 pb->io_total = pb->mem_total = pb->pmem_total = 0; 981 982 rv = probe_bus(pb); 983 if (rv == 0) { 984 rv = configure_bus(pb); 985 } 986 987 /* 988 * All done! 989 */ 990 free(pb, M_DEVBUF); 991 return rv; 992 } 993
Indexes created Wed Sep 24 02:09:48 GMT 2025