pciconf.c revision 1.30.52.1
1 /* $NetBSD: pciconf.c,v 1.30.52.1 2011/12/24 01:25:51 matt Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Derived in part from code from PMON/2000 (http://pmon.groupbsd.org/). 39 */ 40 41 /* 42 * To do: 43 * - Perform all data structure allocation dynamically, don't have 44 * statically-sized arrays ("oops, you lose because you have too 45 * many slots filled!") 46 * - Do this in 2 passes, with an MD hook to control the behavior: 47 * (1) Configure the bus (possibly including expansion 48 * ROMs. 49 * (2) Another pass to disable expansion ROMs if they're 50 * mapped (since you're not supposed to leave them 51 * mapped when you're not using them). 52 * This would facilitate MD code executing the expansion ROMs 53 * if necessary (possibly with an x86 emulator) to configure 54 * devices (e.g. VGA cards). 55 * - Deal with "anything can be hot-plugged" -- i.e., carry configuration 56 * information around & be able to reconfigure on the fly 57 * - Deal with segments (See IA64 System Abstraction Layer) 58 * - Deal with subtractive bridges (& non-spec positive/subtractive decode) 59 * - Deal with ISA/VGA/VGA palette snooping 60 * - Deal with device capabilities on bridges 61 * - Worry about changing a bridge to/from transparency 62 * From thorpej (05/25/01) 63 * - Try to handle devices that are already configured (perhaps using that 64 * as a hint to where we put other devices) 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: pciconf.c,v 1.30.52.1 2011/12/24 01:25:51 matt Exp $"); 69 70 #include "opt_pci.h" 71 72 #include <sys/param.h> 73 #include <sys/extent.h> 74 #include <sys/queue.h> 75 #include <sys/systm.h> 76 #include <sys/malloc.h> 77 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/pciconf.h> 80 #include <dev/pci/pcidevs.h> 81 #include <dev/pci/pccbbreg.h> 82 83 int pci_conf_debug = 0; 84 85 #if !defined(MIN) 86 #define MIN(a,b) (((a)<(b))?(a):(b)) 87 #define MAX(a,b) (((a)>(b))?(a):(b)) 88 #endif 89 90 /* per-bus constants. */ 91 #define MAX_CONF_DEV 32 /* Arbitrary */ 92 #define MAX_CONF_MEM (3 * MAX_CONF_DEV) /* Avg. 3 per device -- Arb. */ 93 #define MAX_CONF_IO (3 * MAX_CONF_DEV) /* Avg. 1 per device -- Arb. */ 94 95 struct _s_pciconf_bus_t; /* Forward declaration */ 96 97 typedef struct _s_pciconf_dev_t { 98 int ipin; 99 int iline; 100 int min_gnt; 101 int max_lat; 102 int enable; 103 pcitag_t tag; 104 pci_chipset_tag_t pc; 105 struct _s_pciconf_bus_t *ppb; /* I am really a bridge */ 106 } pciconf_dev_t; 107 108 typedef struct _s_pciconf_win_t { 109 pciconf_dev_t *dev; 110 int reg; /* 0 for busses */ 111 int align; 112 int prefetch; 113 u_int64_t size; 114 u_int64_t address; 115 } pciconf_win_t; 116 117 typedef struct _s_pciconf_bus_t { 118 int busno; 119 int next_busno; 120 int last_busno; 121 int max_mingnt; 122 int min_maxlat; 123 int cacheline_size; 124 int prefetch; 125 int fast_b2b; 126 int freq_66; 127 int def_ltim; 128 int max_ltim; 129 int bandwidth_used; 130 int swiz; 131 int io_32bit; 132 int pmem_64bit; 133 int io_align; 134 int mem_align; 135 int pmem_align; 136 137 int ndevs; 138 pciconf_dev_t device[MAX_CONF_DEV]; 139 140 /* These should be sorted in order of decreasing size */ 141 int nmemwin; 142 pciconf_win_t pcimemwin[MAX_CONF_MEM]; 143 int niowin; 144 pciconf_win_t pciiowin[MAX_CONF_IO]; 145 146 bus_size_t io_total; 147 bus_size_t mem_total; 148 bus_size_t pmem_total; 149 150 struct extent *ioext; 151 struct extent *memext; 152 struct extent *pmemext; 153 154 pci_chipset_tag_t pc; 155 struct _s_pciconf_bus_t *parent_bus; 156 } pciconf_bus_t; 157 158 static int probe_bus(pciconf_bus_t *); 159 static void alloc_busno(pciconf_bus_t *, pciconf_bus_t *); 160 static void set_busreg(pci_chipset_tag_t, pcitag_t, int, int, int); 161 static int pci_do_device_query(pciconf_bus_t *, pcitag_t, int, int, int); 162 static int setup_iowins(pciconf_bus_t *); 163 static int setup_memwins(pciconf_bus_t *); 164 static int configure_bridge(pciconf_dev_t *); 165 static int configure_bus(pciconf_bus_t *); 166 static u_int64_t pci_allocate_range(struct extent *, u_int64_t, int); 167 static pciconf_win_t *get_io_desc(pciconf_bus_t *, bus_size_t); 168 static pciconf_win_t *get_mem_desc(pciconf_bus_t *, bus_size_t); 169 static pciconf_bus_t *query_bus(pciconf_bus_t *, pciconf_dev_t *, int); 170 171 static void print_tag(pci_chipset_tag_t, pcitag_t); 172 173 static void 174 print_tag(pci_chipset_tag_t pc, pcitag_t tag) 175 { 176 int bus, dev, func; 177 178 pci_decompose_tag(pc, tag, &bus, &dev, &func); 179 printf("PCI: bus %d, device %d, function %d: ", bus, dev, func); 180 } 181 182 /************************************************************************/ 183 /************************************************************************/ 184 /*********************** Bus probing routines ***********************/ 185 /************************************************************************/ 186 /************************************************************************/ 187 static pciconf_win_t * 188 get_io_desc(pciconf_bus_t *pb, bus_size_t size) 189 { 190 int i, n; 191 192 n = pb->niowin; 193 for (i=n; i > 0 && size > pb->pciiowin[i-1].size; i--) 194 pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */ 195 return &pb->pciiowin[i]; 196 } 197 198 static pciconf_win_t * 199 get_mem_desc(pciconf_bus_t *pb, bus_size_t size) 200 { 201 int i, n; 202 203 n = pb->nmemwin; 204 for (i=n; i > 0 && size > pb->pcimemwin[i-1].size; i--) 205 pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */ 206 return &pb->pcimemwin[i]; 207 } 208 209 /* 210 * Set up bus common stuff, then loop over devices & functions. 211 * If we find something, call pci_do_device_query()). 212 */ 213 static int 214 probe_bus(pciconf_bus_t *pb) 215 { 216 int device, maxdevs; 217 #ifdef __PCI_BUS_DEVORDER 218 char devs[32]; 219 int i; 220 #endif 221 222 maxdevs = pci_bus_maxdevs(pb->pc, pb->busno); 223 pb->ndevs = 0; 224 pb->niowin = 0; 225 pb->nmemwin = 0; 226 pb->freq_66 = 1; 227 #ifdef PCICONF_NO_FAST_B2B 228 pb->fast_b2b = 0; 229 #else 230 pb->fast_b2b = 1; 231 #endif 232 pb->prefetch = 1; 233 pb->max_mingnt = 0; /* we are looking for the maximum */ 234 pb->min_maxlat = 0x100; /* we are looking for the minimum */ 235 pb->bandwidth_used = 0; 236 237 #ifdef __PCI_BUS_DEVORDER 238 pci_bus_devorder(pb->pc, pb->busno, devs); 239 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) { 240 #else 241 for (device = 0; device < maxdevs; device++) { 242 #endif 243 pcitag_t tag; 244 pcireg_t id, bhlcr; 245 int function, nfunction; 246 int confmode; 247 248 tag = pci_make_tag(pb->pc, pb->busno, device, 0); 249 if (pci_conf_debug) { 250 print_tag(pb->pc, tag); 251 } 252 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 253 254 if (pci_conf_debug) { 255 printf("id=%x: Vendor=%x, Product=%x\n", 256 id, PCI_VENDOR(id),PCI_PRODUCT(id)); 257 } 258 /* Invalid vendor ID value? */ 259 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 260 continue; 261 262 bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 263 nfunction = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 264 for (function = 0 ; function < nfunction ; function++) { 265 tag = pci_make_tag(pb->pc, pb->busno, device, function); 266 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 267 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 268 continue; 269 if (pb->ndevs+1 < MAX_CONF_DEV) { 270 if (pci_conf_debug) { 271 print_tag(pb->pc, tag); 272 printf("Found dev 0x%04x 0x%04x -- " 273 "really probing.\n", 274 PCI_VENDOR(id), PCI_PRODUCT(id)); 275 } 276 #ifdef __HAVE_PCI_CONF_HOOK 277 confmode = pci_conf_hook(pb->pc, pb->busno, 278 device, function, id); 279 if (confmode == 0) 280 continue; 281 #else 282 /* 283 * Don't enable expansion ROMS -- some cards 284 * share address decoders between the EXPROM 285 * and PCI memory space, and enabling the ROM 286 * when not needed will cause all sorts of 287 * lossage. 288 */ 289 confmode = PCI_CONF_DEFAULT; 290 #endif 291 if (pci_do_device_query(pb, tag, device, 292 function, confmode)) 293 return -1; 294 pb->ndevs++; 295 } 296 } 297 } 298 return 0; 299 } 300 301 static void 302 alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb) 303 { 304 pb->busno = parent->next_busno; 305 pb->next_busno = pb->busno + 1; 306 } 307 308 static void 309 set_busreg(pci_chipset_tag_t pc, pcitag_t tag, int prim, int sec, int sub) 310 { 311 pcireg_t busreg; 312 313 busreg = prim << PCI_BRIDGE_BUS_PRIMARY_SHIFT; 314 busreg |= sec << PCI_BRIDGE_BUS_SECONDARY_SHIFT; 315 busreg |= sub << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 316 pci_conf_write(pc, tag, PCI_BRIDGE_BUS_REG, busreg); 317 } 318 319 static pciconf_bus_t * 320 query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev) 321 { 322 pciconf_bus_t *pb; 323 pcireg_t io, pmem; 324 pciconf_win_t *pi, *pm; 325 326 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 327 if (!pb) 328 panic("Unable to allocate memory for PCI configuration."); 329 330 pb->cacheline_size = parent->cacheline_size; 331 pb->parent_bus = parent; 332 alloc_busno(parent, pb); 333 334 pb->mem_align = 0x100000; /* 1M alignment */ 335 pb->pmem_align = 0x100000; /* 1M alignment */ 336 pb->io_align = 0x1000; /* 4K alignment */ 337 338 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 0xff); 339 340 pb->swiz = parent->swiz + dev; 341 342 pb->ioext = NULL; 343 pb->memext = NULL; 344 pb->pmemext = NULL; 345 pb->pc = parent->pc; 346 pb->io_total = pb->mem_total = pb->pmem_total = 0; 347 348 pb->io_32bit = 0; 349 if (parent->io_32bit) { 350 io = pci_conf_read(parent->pc, pd->tag, PCI_BRIDGE_STATIO_REG); 351 if (PCI_BRIDGE_IO_32BITS(io)) { 352 pb->io_32bit = 1; 353 } 354 } 355 356 pb->pmem_64bit = 0; 357 if (parent->pmem_64bit) { 358 pmem = pci_conf_read(parent->pc, pd->tag, 359 PCI_BRIDGE_PREFETCHMEM_REG); 360 if (PCI_BRIDGE_PREFETCHMEM_64BITS(pmem)) { 361 pb->pmem_64bit = 1; 362 } 363 } 364 365 if (probe_bus(pb)) { 366 printf("Failed to probe bus %d\n", pb->busno); 367 goto err; 368 } 369 370 /* We have found all subordinate busses now, reprogram busreg. */ 371 pb->last_busno = pb->next_busno-1; 372 parent->next_busno = pb->next_busno; 373 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 374 pb->last_busno); 375 if (pci_conf_debug) 376 printf("PCI bus bridge (parent %d) covers busses %d-%d\n", 377 parent->busno, pb->busno, pb->last_busno); 378 379 if (pb->io_total > 0) { 380 if (parent->niowin >= MAX_CONF_IO) { 381 printf("pciconf: too many I/O windows\n"); 382 goto err; 383 } 384 pb->io_total |= pb->io_align - 1; /* Round up */ 385 pi = get_io_desc(parent, pb->io_total); 386 pi->dev = pd; 387 pi->reg = 0; 388 pi->size = pb->io_total; 389 pi->align = pb->io_align; /* 4K min alignment */ 390 if (parent->io_align < pb->io_align) 391 parent->io_align = pb->io_align; 392 pi->prefetch = 0; 393 parent->niowin++; 394 parent->io_total += pb->io_total; 395 } 396 397 if (pb->mem_total > 0) { 398 if (parent->nmemwin >= MAX_CONF_MEM) { 399 printf("pciconf: too many MEM windows\n"); 400 goto err; 401 } 402 pb->mem_total |= pb->mem_align-1; /* Round up */ 403 pm = get_mem_desc(parent, pb->mem_total); 404 pm->dev = pd; 405 pm->reg = 0; 406 pm->size = pb->mem_total; 407 pm->align = pb->mem_align; /* 1M min alignment */ 408 if (parent->mem_align < pb->mem_align) 409 parent->mem_align = pb->mem_align; 410 pm->prefetch = 0; 411 parent->nmemwin++; 412 parent->mem_total += pb->mem_total; 413 } 414 415 if (pb->pmem_total > 0) { 416 if (parent->nmemwin >= MAX_CONF_MEM) { 417 printf("pciconf: too many MEM windows\n"); 418 goto err; 419 } 420 pb->pmem_total |= pb->pmem_align-1; /* Round up */ 421 pm = get_mem_desc(parent, pb->pmem_total); 422 pm->dev = pd; 423 pm->reg = 0; 424 pm->size = pb->pmem_total; 425 pm->align = pb->pmem_align; /* 1M alignment */ 426 if (parent->pmem_align < pb->pmem_align) 427 parent->pmem_align = pb->pmem_align; 428 pm->prefetch = 1; 429 parent->nmemwin++; 430 parent->pmem_total += pb->pmem_total; 431 } 432 433 return pb; 434 err: 435 free(pb, M_DEVBUF); 436 return NULL; 437 } 438 439 static int 440 pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func, int mode) 441 { 442 pciconf_dev_t *pd; 443 pciconf_win_t *pi, *pm; 444 pcireg_t class, cmd, icr, bhlc, bar, mask, bar64, mask64, busreg; 445 u_int64_t size; 446 int br, width, reg_start, reg_end; 447 448 pd = &pb->device[pb->ndevs]; 449 pd->pc = pb->pc; 450 pd->tag = tag; 451 pd->ppb = NULL; 452 pd->enable = mode; 453 454 class = pci_conf_read(pb->pc, tag, PCI_CLASS_REG); 455 456 cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG); 457 458 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE) { 459 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 460 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 461 pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd); 462 } else if (pci_conf_debug) { 463 print_tag(pb->pc, tag); 464 printf("device is a bridge; not clearing enables\n"); 465 } 466 467 if ((cmd & PCI_STATUS_BACKTOBACK_SUPPORT) == 0) 468 pb->fast_b2b = 0; 469 470 if ((cmd & PCI_STATUS_66MHZ_SUPPORT) == 0) 471 pb->freq_66 = 0; 472 473 bhlc = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 474 switch (PCI_HDRTYPE_TYPE(bhlc)) { 475 case PCI_HDRTYPE_DEVICE: 476 reg_start = PCI_MAPREG_START; 477 reg_end = PCI_MAPREG_END; 478 break; 479 case PCI_HDRTYPE_PPB: 480 pd->ppb = query_bus(pb, pd, dev); 481 if (pd->ppb == NULL) 482 return -1; 483 return 0; 484 case PCI_HDRTYPE_PCB: 485 reg_start = PCI_MAPREG_START; 486 reg_end = PCI_MAPREG_PCB_END; 487 488 busreg = pci_conf_read(pb->pc, tag, PCI_BUSNUM); 489 busreg = (busreg & 0xff000000) | 490 pb->busno << PCI_BRIDGE_BUS_PRIMARY_SHIFT | 491 pb->next_busno << PCI_BRIDGE_BUS_SECONDARY_SHIFT | 492 pb->next_busno << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 493 pci_conf_write(pb->pc, tag, PCI_BUSNUM, busreg); 494 495 pb->next_busno++; 496 break; 497 default: 498 return -1; 499 } 500 501 icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG); 502 pd->ipin = PCI_INTERRUPT_PIN(icr); 503 pd->iline = PCI_INTERRUPT_LINE(icr); 504 pd->min_gnt = PCI_MIN_GNT(icr); 505 pd->max_lat = PCI_MAX_LAT(icr); 506 if (pd->iline || pd->ipin) { 507 pci_conf_interrupt(pb->pc, pb->busno, dev, pd->ipin, pb->swiz, 508 &pd->iline); 509 icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 510 icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT); 511 pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr); 512 } 513 514 if (pd->min_gnt != 0 || pd->max_lat != 0) { 515 if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt) 516 pb->max_mingnt = pd->min_gnt; 517 518 if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat) 519 pb->min_maxlat = pd->max_lat; 520 521 pb->bandwidth_used += pd->min_gnt * 4000000 / 522 (pd->min_gnt + pd->max_lat); 523 } 524 525 width = 4; 526 for (br = reg_start; br < reg_end; br += width) { 527 #if 0 528 /* XXX Should only ignore if IDE not in legacy mode? */ 529 if (PCI_CLASS(class) == PCI_CLASS_MASS_STORAGE && 530 PCI_SUBCLASS(class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 531 break; 532 } 533 #endif 534 bar = pci_conf_read(pb->pc, tag, br); 535 pci_conf_write(pb->pc, tag, br, 0xffffffff); 536 mask = pci_conf_read(pb->pc, tag, br); 537 pci_conf_write(pb->pc, tag, br, bar); 538 width = 4; 539 540 if ( (mode & PCI_CONF_MAP_IO) 541 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO)) { 542 /* 543 * Upper 16 bits must be one. Devices may hardwire 544 * them to zero, though, per PCI 2.2, 6.2.5.1, p 203. 545 */ 546 mask |= 0xffff0000; 547 548 size = PCI_MAPREG_IO_SIZE(mask); 549 if (size == 0) { 550 if (pci_conf_debug) { 551 print_tag(pb->pc, tag); 552 printf("I/O BAR 0x%x is void\n", br); 553 } 554 continue; 555 } 556 557 if (pb->niowin >= MAX_CONF_IO) { 558 printf("pciconf: too many I/O windows\n"); 559 return -1; 560 } 561 562 pi = get_io_desc(pb, size); 563 pi->dev = pd; 564 pi->reg = br; 565 pi->size = (u_int64_t) size; 566 pi->align = 4; 567 if (pb->io_align < pi->size) 568 pb->io_align = pi->size; 569 pi->prefetch = 0; 570 if (pci_conf_debug) { 571 print_tag(pb->pc, tag); 572 printf("Register 0x%x, I/O size %" PRIu64 "\n", 573 br, pi->size); 574 } 575 pb->niowin++; 576 pb->io_total += size; 577 } else if ((mode & PCI_CONF_MAP_MEM) 578 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_MEM)) { 579 switch (PCI_MAPREG_MEM_TYPE(mask)) { 580 case PCI_MAPREG_MEM_TYPE_32BIT: 581 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 582 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 583 break; 584 case PCI_MAPREG_MEM_TYPE_64BIT: 585 bar64 = pci_conf_read(pb->pc, tag, br + 4); 586 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); 587 mask64 = pci_conf_read(pb->pc, tag, br + 4); 588 pci_conf_write(pb->pc, tag, br + 4, bar64); 589 size = (u_int64_t) PCI_MAPREG_MEM64_SIZE( 590 (((u_int64_t) mask64) << 32) | mask); 591 width = 8; 592 break; 593 default: 594 print_tag(pb->pc, tag); 595 printf("reserved mapping type 0x%x\n", 596 PCI_MAPREG_MEM_TYPE(mask)); 597 continue; 598 } 599 600 if (size == 0) { 601 if (pci_conf_debug) { 602 print_tag(pb->pc, tag); 603 printf("MEM%d BAR 0x%x is void\n", 604 PCI_MAPREG_MEM_TYPE(mask) == 605 PCI_MAPREG_MEM_TYPE_64BIT ? 606 64 : 32, br); 607 } 608 continue; 609 } else { 610 if (pci_conf_debug) { 611 print_tag(pb->pc, tag); 612 printf("MEM%d BAR 0x%x has size %#lx\n", 613 PCI_MAPREG_MEM_TYPE(mask) == 614 PCI_MAPREG_MEM_TYPE_64BIT ? 615 64 : 32, br, (unsigned long)size); 616 } 617 } 618 619 if (pb->nmemwin >= MAX_CONF_MEM) { 620 printf("pciconf: too many memory windows\n"); 621 return -1; 622 } 623 624 pm = get_mem_desc(pb, size); 625 pm->dev = pd; 626 pm->reg = br; 627 pm->size = size; 628 pm->align = 4; 629 pm->prefetch = PCI_MAPREG_MEM_PREFETCHABLE(mask); 630 if (pci_conf_debug) { 631 print_tag(pb->pc, tag); 632 printf("Register 0x%x, memory size %" 633 PRIu64 "\n", br, pm->size); 634 } 635 pb->nmemwin++; 636 if (pm->prefetch) { 637 pb->pmem_total += size; 638 if (pb->pmem_align < pm->size) 639 pb->pmem_align = pm->size; 640 } else { 641 pb->mem_total += size; 642 if (pb->mem_align < pm->size) 643 pb->mem_align = pm->size; 644 } 645 } 646 } 647 648 if (mode & PCI_CONF_MAP_ROM) { 649 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 650 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 651 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 652 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, bar); 653 654 if (mask != 0 && mask != 0xffffffff) { 655 if (pb->nmemwin >= MAX_CONF_MEM) { 656 printf("pciconf: too many memory windows\n"); 657 return -1; 658 } 659 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 660 661 pm = get_mem_desc(pb, size); 662 pm->dev = pd; 663 pm->reg = PCI_MAPREG_ROM; 664 pm->size = size; 665 pm->align = 4; 666 pm->prefetch = 1; 667 if (pci_conf_debug) { 668 print_tag(pb->pc, tag); 669 printf("Expansion ROM memory size %" 670 PRIu64 "\n", pm->size); 671 } 672 pb->nmemwin++; 673 pb->pmem_total += size; 674 } 675 } else { 676 /* Don't enable ROMs if we aren't going to map them. */ 677 mode &= ~PCI_CONF_ENABLE_ROM; 678 pd->enable &= ~PCI_CONF_ENABLE_ROM; 679 } 680 681 if (!(mode & PCI_CONF_ENABLE_ROM)) { 682 /* Ensure ROM is disabled */ 683 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 684 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 685 bar & ~PCI_MAPREG_ROM_ENABLE); 686 } 687 688 return 0; 689 } 690 691 /************************************************************************/ 692 /************************************************************************/ 693 /******************** Bus configuration routines ********************/ 694 /************************************************************************/ 695 /************************************************************************/ 696 static u_int64_t 697 pci_allocate_range(struct extent *ex, u_int64_t amt, int align) 698 { 699 int r; 700 u_long addr; 701 702 r = extent_alloc(ex, amt, align, 0, EX_NOWAIT, &addr); 703 if (r) { 704 printf("extent_alloc(%p, %#" PRIx64 ", %#x) returned %d\n", 705 ex, amt, align, r); 706 extent_print(ex); 707 return ~0ULL; 708 } 709 return addr; 710 } 711 712 static int 713 setup_iowins(pciconf_bus_t *pb) 714 { 715 pciconf_win_t *pi; 716 pciconf_dev_t *pd; 717 718 for (pi=pb->pciiowin; pi < &pb->pciiowin[pb->niowin] ; pi++) { 719 if (pi->size == 0) 720 continue; 721 722 pd = pi->dev; 723 pi->address = pci_allocate_range(pb->ioext, pi->size, 724 pi->align); 725 if (~pi->address == 0) { 726 print_tag(pd->pc, pd->tag); 727 printf("Failed to allocate PCI I/O space (%" 728 PRIu64 " req)\n", pi->size); 729 return -1; 730 } 731 if (pd->ppb && pi->reg == 0) { 732 pd->ppb->ioext = extent_create("pciconf", pi->address, 733 pi->address + pi->size, M_DEVBUF, NULL, 0, 734 EX_NOWAIT); 735 if (pd->ppb->ioext == NULL) { 736 print_tag(pd->pc, pd->tag); 737 printf("Failed to alloc I/O ext. for bus %d\n", 738 pd->ppb->busno); 739 return -1; 740 } 741 continue; 742 } 743 if (!pb->io_32bit && pi->address > 0xFFFF) { 744 pi->address = 0; 745 pd->enable &= ~PCI_CONF_ENABLE_IO; 746 } else { 747 pd->enable |= PCI_CONF_ENABLE_IO; 748 } 749 if (pci_conf_debug) { 750 print_tag(pd->pc, pd->tag); 751 printf("Putting %" PRIu64 " I/O bytes @ %#" PRIx64 752 " (reg %x)\n", pi->size, pi->address, pi->reg); 753 } 754 pci_conf_write(pd->pc, pd->tag, pi->reg, 755 PCI_MAPREG_IO_ADDR(pi->address) | PCI_MAPREG_TYPE_IO); 756 } 757 return 0; 758 } 759 760 static int 761 setup_memwins(pciconf_bus_t *pb) 762 { 763 pciconf_win_t *pm; 764 pciconf_dev_t *pd; 765 pcireg_t base; 766 struct extent *ex; 767 768 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 769 if (pm->size == 0) 770 continue; 771 772 pd = pm->dev; 773 ex = (pm->prefetch) ? pb->pmemext : pb->memext; 774 pm->address = pci_allocate_range(ex, pm->size, pm->align); 775 if (~pm->address == 0) { 776 print_tag(pd->pc, pd->tag); 777 printf( 778 "Failed to allocate PCI memory space (%" PRIu64 779 " req)\n", pm->size); 780 return -1; 781 } 782 if (pd->ppb && pm->reg == 0) { 783 ex = extent_create("pciconf", pm->address, 784 pm->address + pm->size, M_DEVBUF, NULL, 0, 785 EX_NOWAIT); 786 if (ex == NULL) { 787 print_tag(pd->pc, pd->tag); 788 printf("Failed to alloc MEM ext. for bus %d\n", 789 pd->ppb->busno); 790 return -1; 791 } 792 if (pm->prefetch) { 793 pd->ppb->pmemext = ex; 794 } else { 795 pd->ppb->memext = ex; 796 } 797 continue; 798 } 799 if (pm->prefetch && !pb->pmem_64bit && 800 pm->address > 0xFFFFFFFFULL) { 801 pm->address = 0; 802 pd->enable &= ~PCI_CONF_ENABLE_MEM; 803 } else { 804 pd->enable |= PCI_CONF_ENABLE_MEM; 805 } 806 if (pm->reg != PCI_MAPREG_ROM) { 807 if (pci_conf_debug) { 808 print_tag(pd->pc, pd->tag); 809 printf( 810 "Putting %" PRIu64 " MEM bytes @ %#" 811 PRIx64 " (reg %x)\n", pm->size, 812 pm->address, pm->reg); 813 } 814 base = pci_conf_read(pd->pc, pd->tag, pm->reg); 815 base = PCI_MAPREG_MEM_ADDR(pm->address) | 816 PCI_MAPREG_MEM_TYPE(base); 817 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 818 if (PCI_MAPREG_MEM_TYPE(base) == 819 PCI_MAPREG_MEM_TYPE_64BIT) { 820 base = (pcireg_t) 821 (PCI_MAPREG_MEM64_ADDR(pm->address) >> 32); 822 pci_conf_write(pd->pc, pd->tag, pm->reg + 4, 823 base); 824 } 825 } 826 } 827 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 828 if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) { 829 pd = pm->dev; 830 if (!(pd->enable & PCI_CONF_MAP_ROM)) 831 continue; 832 if (pci_conf_debug) { 833 print_tag(pd->pc, pd->tag); 834 printf( 835 "Putting %" PRIu64 " ROM bytes @ %#" 836 PRIx64 " (reg %x)\n", pm->size, 837 pm->address, pm->reg); 838 } 839 base = (pcireg_t) pm->address; 840 if (pd->enable & PCI_CONF_ENABLE_ROM) 841 base |= PCI_MAPREG_ROM_ENABLE; 842 843 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 844 } 845 } 846 return 0; 847 } 848 849 /* 850 * Configure I/O, memory, and prefetcable memory spaces, then make 851 * a call to configure_bus(). 852 */ 853 static int 854 configure_bridge(pciconf_dev_t *pd) 855 { 856 unsigned long io_base, io_limit, mem_base, mem_limit; 857 pciconf_bus_t *pb; 858 pcireg_t io, iohigh, mem, cmd; 859 int rv; 860 861 pb = pd->ppb; 862 /* Configure I/O base & limit*/ 863 if (pb->ioext) { 864 io_base = pb->ioext->ex_start; 865 io_limit = pb->ioext->ex_end; 866 } else { 867 io_base = 0x1000; /* 4K */ 868 io_limit = 0x0000; 869 } 870 if (pb->io_32bit) { 871 iohigh = 872 ((io_base >> 16) << PCI_BRIDGE_IOHIGH_BASE_SHIFT) | 873 ((io_limit >> 16) << PCI_BRIDGE_IOHIGH_LIMIT_SHIFT); 874 } else { 875 if (io_limit > 0xFFFF) { 876 printf("Bus %d bridge does not support 32-bit I/O. ", 877 pb->busno); 878 printf("Disabling I/O accesses\n"); 879 io_base = 0x1000; /* 4K */ 880 io_limit = 0x0000; 881 } 882 iohigh = 0; 883 } 884 io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG) & 885 (PCI_BRIDGE_STATIO_STATUS_MASK << PCI_BRIDGE_STATIO_STATUS_SHIFT); 886 io |= (((io_base >> 8) & PCI_BRIDGE_STATIO_IOBASE_MASK) 887 << PCI_BRIDGE_STATIO_IOBASE_SHIFT); 888 io |= (((io_limit >> 8) & PCI_BRIDGE_STATIO_IOLIMIT_MASK) 889 << PCI_BRIDGE_STATIO_IOLIMIT_SHIFT); 890 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io); 891 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh); 892 893 /* Configure mem base & limit */ 894 if (pb->memext) { 895 mem_base = pb->memext->ex_start; 896 mem_limit = pb->memext->ex_end; 897 } else { 898 mem_base = 0x100000; /* 1M */ 899 mem_limit = 0x000000; 900 } 901 #if ULONG_MAX > 0xffffffff 902 if (mem_limit > 0xFFFFFFFFULL) { 903 printf("Bus %d bridge MEM range out of range. ", pb->busno); 904 printf("Disabling MEM accesses\n"); 905 mem_base = 0x100000; /* 1M */ 906 mem_limit = 0x000000; 907 } 908 #endif 909 mem = (((mem_base >> 20) & PCI_BRIDGE_MEMORY_BASE_MASK) 910 << PCI_BRIDGE_MEMORY_BASE_SHIFT); 911 mem |= (((mem_limit >> 20) & PCI_BRIDGE_MEMORY_LIMIT_MASK) 912 << PCI_BRIDGE_MEMORY_LIMIT_SHIFT); 913 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem); 914 915 /* Configure prefetchable mem base & limit */ 916 if (pb->pmemext) { 917 mem_base = pb->pmemext->ex_start; 918 mem_limit = pb->pmemext->ex_end; 919 } else { 920 mem_base = 0x100000; /* 1M */ 921 mem_limit = 0x000000; 922 } 923 mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG); 924 #if ULONG_MAX > 0xffffffff 925 if (!PCI_BRIDGE_PREFETCHMEM_64BITS(mem) && mem_limit > 0xFFFFFFFFULL) { 926 printf("Bus %d bridge does not support 64-bit PMEM. ", 927 pb->busno); 928 printf("Disabling prefetchable-MEM accesses\n"); 929 mem_base = 0x100000; /* 1M */ 930 mem_limit = 0x000000; 931 } 932 #endif 933 mem = (((mem_base >> 20) & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) 934 << PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT); 935 mem |= (((mem_limit >> 20) & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) 936 << PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT); 937 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem); 938 /* 939 * XXX -- 64-bit systems need a lot more than just this... 940 */ 941 if (sizeof(u_long) > 4) { 942 mem_base = (int64_t) mem_base >> 32; 943 mem_limit = (int64_t) mem_limit >> 32; 944 } 945 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHBASE32_REG, 946 mem_base & 0xffffffff); 947 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHLIMIT32_REG, 948 mem_limit & 0xffffffff); 949 950 rv = configure_bus(pb); 951 952 if (pb->ioext) 953 extent_destroy(pb->ioext); 954 if (pb->memext) 955 extent_destroy(pb->memext); 956 if (pb->pmemext) 957 extent_destroy(pb->pmemext); 958 if (rv == 0) { 959 cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG); 960 cmd &= PCI_BRIDGE_CONTROL_MASK; 961 cmd |= (PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR) 962 << PCI_BRIDGE_CONTROL_SHIFT; 963 if (pb->fast_b2b) { 964 cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B 965 << PCI_BRIDGE_CONTROL_SHIFT; 966 } 967 pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd); 968 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 969 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 970 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 971 } 972 973 return rv; 974 } 975 976 /* 977 * Calculate latency values, allocate I/O and MEM segments, then set them 978 * up. If a PCI-PCI bridge is found, configure the bridge separately, 979 * which will cause a recursive call back here. 980 */ 981 static int 982 configure_bus(pciconf_bus_t *pb) 983 { 984 pciconf_dev_t *pd; 985 int def_ltim, max_ltim, band, bus_mhz; 986 987 if (pb->ndevs == 0) { 988 if (pci_conf_debug) 989 printf("PCI bus %d - no devices\n", pb->busno); 990 return (1); 991 } 992 bus_mhz = pb->freq_66 ? 66 : 33; 993 max_ltim = pb->max_mingnt * bus_mhz / 4; /* cvt to cycle count */ 994 band = 4000000; /* 0.25us cycles/sec */ 995 if (band < pb->bandwidth_used) { 996 printf("PCI bus %d: Warning: Total bandwidth exceeded!?\n", 997 pb->busno); 998 def_ltim = -1; 999 } else { 1000 def_ltim = (band - pb->bandwidth_used) / pb->ndevs; 1001 if (def_ltim > pb->min_maxlat) 1002 def_ltim = pb->min_maxlat; 1003 def_ltim = def_ltim * bus_mhz / 4; 1004 } 1005 def_ltim = (def_ltim + 7) & ~7; 1006 max_ltim = (max_ltim + 7) & ~7; 1007 1008 pb->def_ltim = MIN( def_ltim, 255 ); 1009 pb->max_ltim = MIN( MAX(max_ltim, def_ltim ), 255 ); 1010 1011 /* 1012 * Now we have what we need to initialize the devices. 1013 * It would probably be better if we could allocate all of these 1014 * for all busses at once, but "not right now". First, get a list 1015 * of free memory ranges from the m.d. system. 1016 */ 1017 if (setup_iowins(pb) || setup_memwins(pb)) { 1018 printf("PCI bus configuration failed: " 1019 "unable to assign all I/O and memory ranges.\n"); 1020 return -1; 1021 } 1022 1023 /* 1024 * Configure the latency for the devices, and enable them. 1025 */ 1026 for (pd=pb->device ; pd < &pb->device[pb->ndevs] ; pd++) { 1027 pcireg_t cmd, class, misc; 1028 int ltim; 1029 1030 if (pci_conf_debug) { 1031 print_tag(pd->pc, pd->tag); 1032 printf("Configuring device.\n"); 1033 } 1034 class = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG); 1035 misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG); 1036 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 1037 if (pd->enable & PCI_CONF_ENABLE_PARITY) 1038 cmd |= PCI_COMMAND_PARITY_ENABLE; 1039 if (pd->enable & PCI_CONF_ENABLE_SERR) 1040 cmd |= PCI_COMMAND_SERR_ENABLE; 1041 if (pb->fast_b2b) 1042 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE; 1043 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 1044 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_PCI) { 1045 if (pd->enable & PCI_CONF_ENABLE_IO) 1046 cmd |= PCI_COMMAND_IO_ENABLE; 1047 if (pd->enable & PCI_CONF_ENABLE_MEM) 1048 cmd |= PCI_COMMAND_MEM_ENABLE; 1049 if (pd->enable & PCI_CONF_ENABLE_BM) 1050 cmd |= PCI_COMMAND_MASTER_ENABLE; 1051 ltim = pd->min_gnt * bus_mhz / 4; 1052 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim); 1053 } else { 1054 cmd |= PCI_COMMAND_MASTER_ENABLE; 1055 ltim = MIN (pb->def_ltim, pb->max_ltim); 1056 } 1057 if ((pd->enable & 1058 (PCI_CONF_ENABLE_MEM|PCI_CONF_ENABLE_IO)) == 0) { 1059 print_tag(pd->pc, pd->tag); 1060 printf("Disabled due to lack of resources.\n"); 1061 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 1062 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 1063 } 1064 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 1065 1066 misc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) | 1067 (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)); 1068 misc |= (ltim & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT; 1069 misc |= ((pb->cacheline_size >> 2) & PCI_CACHELINE_MASK) << 1070 PCI_CACHELINE_SHIFT; 1071 pci_conf_write(pd->pc, pd->tag, PCI_BHLC_REG, misc); 1072 1073 if (pd->ppb) { 1074 if (configure_bridge(pd) < 0) 1075 return -1; 1076 continue; 1077 } 1078 } 1079 1080 if (pci_conf_debug) { 1081 printf("PCI bus %d configured\n", pb->busno); 1082 } 1083 1084 return 0; 1085 } 1086 1087 /* 1088 * Let's configure the PCI bus. 1089 * This consists of basically scanning for all existing devices, 1090 * identifying their needs, and then making another pass over them 1091 * to set: 1092 * 1. I/O addresses 1093 * 2. Memory addresses (Prefetchable and not) 1094 * 3. PCI command register 1095 * 4. The latency part of the PCI BHLC (BIST (Built-In Self Test), 1096 * Header type, Latency timer, Cache line size) register 1097 * 1098 * The command register is set to enable fast back-to-back transactions 1099 * if the host bridge says it can handle it. We also configure 1100 * Master Enable, SERR enable, parity enable, and (if this is not a 1101 * PCI-PCI bridge) the I/O and Memory spaces. Apparently some devices 1102 * will not report some I/O space. 1103 * 1104 * The latency is computed to be a "fair share" of the bus bandwidth. 1105 * The bus bandwidth variable is initialized to the number of PCI cycles 1106 * in one second. The number of cycles taken for one transaction by each 1107 * device (MAX_LAT + MIN_GNT) is then subtracted from the bandwidth. 1108 * Care is taken to ensure that the latency timer won't be set such that 1109 * it would exceed the critical time for any device. 1110 * 1111 * This is complicated somewhat due to the presence of bridges. PCI-PCI 1112 * bridges are probed and configured recursively. 1113 */ 1114 int 1115 pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext, 1116 struct extent *memext, struct extent *pmemext, int firstbus, 1117 int cacheline_size) 1118 { 1119 pciconf_bus_t *pb; 1120 int rv; 1121 1122 pb = malloc (sizeof (pciconf_bus_t), M_DEVBUF, M_NOWAIT); 1123 pb->busno = firstbus; 1124 pb->next_busno = pb->busno + 1; 1125 pb->last_busno = 255; 1126 pb->cacheline_size = cacheline_size; 1127 pb->parent_bus = NULL; 1128 pb->swiz = 0; 1129 pb->io_32bit = 1; 1130 pb->pmem_64bit = 0; 1131 pb->ioext = ioext; 1132 pb->memext = memext; 1133 if (pmemext == NULL) { 1134 pb->pmemext = memext; 1135 } else { 1136 pb->pmemext = pmemext; 1137 } 1138 pb->pc = pc; 1139 pb->io_total = pb->mem_total = pb->pmem_total = 0; 1140 1141 rv = probe_bus(pb); 1142 pb->last_busno = pb->next_busno-1; 1143 if (rv == 0) { 1144 rv = configure_bus(pb); 1145 } 1146 1147 /* 1148 * All done! 1149 */ 1150 free(pb, M_DEVBUF); 1151 return rv; 1152 } 1153
Indexes created Fri Oct 17 23:09:53 GMT 2025