pciconf.c revision 1.32
1 /* $NetBSD: pciconf.c,v 1.32 2010/12/11 18:21:14 matt Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Derived in part from code from PMON/2000 (http://pmon.groupbsd.org/). 39 */ 40 41 /* 42 * To do: 43 * - Perform all data structure allocation dynamically, don't have 44 * statically-sized arrays ("oops, you lose because you have too 45 * many slots filled!") 46 * - Do this in 2 passes, with an MD hook to control the behavior: 47 * (1) Configure the bus (possibly including expansion 48 * ROMs. 49 * (2) Another pass to disable expansion ROMs if they're 50 * mapped (since you're not supposed to leave them 51 * mapped when you're not using them). 52 * This would facilitate MD code executing the expansion ROMs 53 * if necessary (possibly with an x86 emulator) to configure 54 * devices (e.g. VGA cards). 55 * - Deal with "anything can be hot-plugged" -- i.e., carry configuration 56 * information around & be able to reconfigure on the fly 57 * - Deal with segments (See IA64 System Abstraction Layer) 58 * - Deal with subtractive bridges (& non-spec positive/subtractive decode) 59 * - Deal with ISA/VGA/VGA palette snooping 60 * - Deal with device capabilities on bridges 61 * - Worry about changing a bridge to/from transparency 62 * From thorpej (05/25/01) 63 * - Try to handle devices that are already configured (perhaps using that 64 * as a hint to where we put other devices) 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: pciconf.c,v 1.32 2010/12/11 18:21:14 matt Exp $"); 69 70 #include "opt_pci.h" 71 72 #include <sys/param.h> 73 #include <sys/extent.h> 74 #include <sys/queue.h> 75 #include <sys/systm.h> 76 #include <sys/malloc.h> 77 #include <sys/kmem.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pciconf.h> 81 #include <dev/pci/pcidevs.h> 82 #include <dev/pci/pccbbreg.h> 83 84 int pci_conf_debug = 0; 85 86 #if !defined(MIN) 87 #define MIN(a,b) (((a)<(b))?(a):(b)) 88 #define MAX(a,b) (((a)>(b))?(a):(b)) 89 #endif 90 91 /* per-bus constants. */ 92 #define MAX_CONF_DEV 32 /* Arbitrary */ 93 #define MAX_CONF_MEM (3 * MAX_CONF_DEV) /* Avg. 3 per device -- Arb. */ 94 #define MAX_CONF_IO (3 * MAX_CONF_DEV) /* Avg. 1 per device -- Arb. */ 95 96 struct _s_pciconf_bus_t; /* Forward declaration */ 97 98 typedef struct _s_pciconf_dev_t { 99 int ipin; 100 int iline; 101 int min_gnt; 102 int max_lat; 103 int enable; 104 pcitag_t tag; 105 pci_chipset_tag_t pc; 106 struct _s_pciconf_bus_t *ppb; /* I am really a bridge */ 107 } pciconf_dev_t; 108 109 typedef struct _s_pciconf_win_t { 110 pciconf_dev_t *dev; 111 int reg; /* 0 for busses */ 112 int align; 113 int prefetch; 114 u_int64_t size; 115 u_int64_t address; 116 } pciconf_win_t; 117 118 typedef struct _s_pciconf_bus_t { 119 int busno; 120 int next_busno; 121 int last_busno; 122 int max_mingnt; 123 int min_maxlat; 124 int cacheline_size; 125 int prefetch; 126 int fast_b2b; 127 int freq_66; 128 int def_ltim; 129 int max_ltim; 130 int bandwidth_used; 131 int swiz; 132 int io_32bit; 133 int pmem_64bit; 134 135 int ndevs; 136 pciconf_dev_t device[MAX_CONF_DEV]; 137 138 /* These should be sorted in order of decreasing size */ 139 int nmemwin; 140 pciconf_win_t pcimemwin[MAX_CONF_MEM]; 141 int niowin; 142 pciconf_win_t pciiowin[MAX_CONF_IO]; 143 144 bus_size_t io_total; 145 bus_size_t mem_total; 146 bus_size_t pmem_total; 147 148 struct extent *ioext; 149 struct extent *memext; 150 struct extent *pmemext; 151 152 pci_chipset_tag_t pc; 153 struct _s_pciconf_bus_t *parent_bus; 154 } pciconf_bus_t; 155 156 static int probe_bus(pciconf_bus_t *); 157 static void alloc_busno(pciconf_bus_t *, pciconf_bus_t *); 158 static void set_busreg(pci_chipset_tag_t, pcitag_t, int, int, int); 159 static int pci_do_device_query(pciconf_bus_t *, pcitag_t, int, int, int); 160 static int setup_iowins(pciconf_bus_t *); 161 static int setup_memwins(pciconf_bus_t *); 162 static int configure_bridge(pciconf_dev_t *); 163 static int configure_bus(pciconf_bus_t *); 164 static u_int64_t pci_allocate_range(struct extent *, u_int64_t, int); 165 static pciconf_win_t *get_io_desc(pciconf_bus_t *, bus_size_t); 166 static pciconf_win_t *get_mem_desc(pciconf_bus_t *, bus_size_t); 167 static pciconf_bus_t *query_bus(pciconf_bus_t *, pciconf_dev_t *, int); 168 169 static void print_tag(pci_chipset_tag_t, pcitag_t); 170 171 static void 172 print_tag(pci_chipset_tag_t pc, pcitag_t tag) 173 { 174 int bus, dev, func; 175 176 pci_decompose_tag(pc, tag, &bus, &dev, &func); 177 printf("PCI: bus %d, device %d, function %d: ", bus, dev, func); 178 } 179 180 /************************************************************************/ 181 /************************************************************************/ 182 /*********************** Bus probing routines ***********************/ 183 /************************************************************************/ 184 /************************************************************************/ 185 static pciconf_win_t * 186 get_io_desc(pciconf_bus_t *pb, bus_size_t size) 187 { 188 int i, n; 189 190 n = pb->niowin; 191 for (i=n; i > 0 && size > pb->pciiowin[i-1].size; i--) 192 pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */ 193 return &pb->pciiowin[i]; 194 } 195 196 static pciconf_win_t * 197 get_mem_desc(pciconf_bus_t *pb, bus_size_t size) 198 { 199 int i, n; 200 201 n = pb->nmemwin; 202 for (i=n; i > 0 && size > pb->pcimemwin[i-1].size; i--) 203 pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */ 204 return &pb->pcimemwin[i]; 205 } 206 207 /* 208 * Set up bus common stuff, then loop over devices & functions. 209 * If we find something, call pci_do_device_query()). 210 */ 211 static int 212 probe_bus(pciconf_bus_t *pb) 213 { 214 int device, maxdevs; 215 #ifdef __PCI_BUS_DEVORDER 216 char devs[32]; 217 int i; 218 #endif 219 220 maxdevs = pci_bus_maxdevs(pb->pc, pb->busno); 221 pb->ndevs = 0; 222 pb->niowin = 0; 223 pb->nmemwin = 0; 224 pb->freq_66 = 1; 225 #ifdef PCICONF_NO_FAST_B2B 226 pb->fast_b2b = 0; 227 #else 228 pb->fast_b2b = 1; 229 #endif 230 pb->prefetch = 1; 231 pb->max_mingnt = 0; /* we are looking for the maximum */ 232 pb->min_maxlat = 0x100; /* we are looking for the minimum */ 233 pb->bandwidth_used = 0; 234 235 #ifdef __PCI_BUS_DEVORDER 236 pci_bus_devorder(pb->pc, pb->busno, devs); 237 for (i = 0; (device = devs[i]) < 32 && device >= 0; i++) { 238 #else 239 for (device = 0; device < maxdevs; device++) { 240 #endif 241 pcitag_t tag; 242 pcireg_t id, bhlcr; 243 int function, nfunction; 244 int confmode; 245 246 tag = pci_make_tag(pb->pc, pb->busno, device, 0); 247 if (pci_conf_debug) { 248 print_tag(pb->pc, tag); 249 } 250 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 251 252 if (pci_conf_debug) { 253 printf("id=%x: Vendor=%x, Product=%x\n", 254 id, PCI_VENDOR(id),PCI_PRODUCT(id)); 255 } 256 /* Invalid vendor ID value? */ 257 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 258 continue; 259 260 bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 261 nfunction = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 262 for (function = 0 ; function < nfunction ; function++) { 263 tag = pci_make_tag(pb->pc, pb->busno, device, function); 264 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 265 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 266 continue; 267 if (pb->ndevs+1 < MAX_CONF_DEV) { 268 if (pci_conf_debug) { 269 print_tag(pb->pc, tag); 270 printf("Found dev 0x%04x 0x%04x -- " 271 "really probing.\n", 272 PCI_VENDOR(id), PCI_PRODUCT(id)); 273 } 274 #ifdef __HAVE_PCI_CONF_HOOK 275 confmode = pci_conf_hook(pb->pc, pb->busno, 276 device, function, id); 277 if (confmode == 0) 278 continue; 279 #else 280 /* 281 * Don't enable expansion ROMS -- some cards 282 * share address decoders between the EXPROM 283 * and PCI memory space, and enabling the ROM 284 * when not needed will cause all sorts of 285 * lossage. 286 */ 287 confmode = PCI_CONF_DEFAULT; 288 #endif 289 if (pci_do_device_query(pb, tag, device, 290 function, confmode)) 291 return -1; 292 pb->ndevs++; 293 } 294 } 295 } 296 return 0; 297 } 298 299 static void 300 alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb) 301 { 302 pb->busno = parent->next_busno; 303 pb->next_busno = pb->busno + 1; 304 } 305 306 static void 307 set_busreg(pci_chipset_tag_t pc, pcitag_t tag, int prim, int sec, int sub) 308 { 309 pcireg_t busreg; 310 311 busreg = prim << PCI_BRIDGE_BUS_PRIMARY_SHIFT; 312 busreg |= sec << PCI_BRIDGE_BUS_SECONDARY_SHIFT; 313 busreg |= sub << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 314 pci_conf_write(pc, tag, PCI_BRIDGE_BUS_REG, busreg); 315 } 316 317 static pciconf_bus_t * 318 query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev) 319 { 320 pciconf_bus_t *pb; 321 pcireg_t io, pmem; 322 pciconf_win_t *pi, *pm; 323 324 pb = kmem_zalloc(sizeof (pciconf_bus_t), KM_NOSLEEP); 325 if (!pb) 326 panic("Unable to allocate memory for PCI configuration."); 327 328 pb->cacheline_size = parent->cacheline_size; 329 pb->parent_bus = parent; 330 alloc_busno(parent, pb); 331 332 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 0xff); 333 334 pb->swiz = parent->swiz + dev; 335 336 pb->ioext = NULL; 337 pb->memext = NULL; 338 pb->pmemext = NULL; 339 pb->pc = parent->pc; 340 pb->io_total = pb->mem_total = pb->pmem_total = 0; 341 342 pb->io_32bit = 0; 343 if (parent->io_32bit) { 344 io = pci_conf_read(parent->pc, pd->tag, PCI_BRIDGE_STATIO_REG); 345 if (PCI_BRIDGE_IO_32BITS(io)) { 346 pb->io_32bit = 1; 347 } 348 } 349 350 pb->pmem_64bit = 0; 351 if (parent->pmem_64bit) { 352 pmem = pci_conf_read(parent->pc, pd->tag, 353 PCI_BRIDGE_PREFETCHMEM_REG); 354 if (PCI_BRIDGE_PREFETCHMEM_64BITS(pmem)) { 355 pb->pmem_64bit = 1; 356 } 357 } 358 359 if (probe_bus(pb)) { 360 printf("Failed to probe bus %d\n", pb->busno); 361 goto err; 362 } 363 364 /* We have found all subordinate busses now, reprogram busreg. */ 365 pb->last_busno = pb->next_busno-1; 366 parent->next_busno = pb->next_busno; 367 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 368 pb->last_busno); 369 if (pci_conf_debug) 370 printf("PCI bus bridge (parent %d) covers busses %d-%d\n", 371 parent->busno, pb->busno, pb->last_busno); 372 373 if (pb->io_total > 0) { 374 if (parent->niowin >= MAX_CONF_IO) { 375 printf("pciconf: too many I/O windows\n"); 376 goto err; 377 } 378 pb->io_total |= 0xfff; /* Round up */ 379 pi = get_io_desc(parent, pb->io_total); 380 pi->dev = pd; 381 pi->reg = 0; 382 pi->size = pb->io_total; 383 pi->align = 0x1000; /* 4K alignment */ 384 pi->prefetch = 0; 385 parent->niowin++; 386 parent->io_total += pb->io_total; 387 } 388 389 if (pb->mem_total > 0) { 390 if (parent->nmemwin >= MAX_CONF_MEM) { 391 printf("pciconf: too many MEM windows\n"); 392 goto err; 393 } 394 pb->mem_total |= 0xfffff; /* Round up */ 395 pm = get_mem_desc(parent, pb->mem_total); 396 pm->dev = pd; 397 pm->reg = 0; 398 pm->size = pb->mem_total; 399 pm->align = 0x100000; /* 1M alignment */ 400 pm->prefetch = 0; 401 parent->nmemwin++; 402 parent->mem_total += pb->mem_total; 403 } 404 405 if (pb->pmem_total > 0) { 406 if (parent->nmemwin >= MAX_CONF_MEM) { 407 printf("pciconf: too many MEM windows\n"); 408 goto err; 409 } 410 pb->pmem_total |= 0xfffff; /* Round up */ 411 pm = get_mem_desc(parent, pb->pmem_total); 412 pm->dev = pd; 413 pm->reg = 0; 414 pm->size = pb->pmem_total; 415 pm->align = 0x100000; /* 1M alignment */ 416 pm->prefetch = 1; 417 parent->nmemwin++; 418 parent->pmem_total += pb->pmem_total; 419 } 420 421 return pb; 422 err: 423 kmem_free(pb, sizeof(*pb)); 424 return NULL; 425 } 426 427 static int 428 pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func, int mode) 429 { 430 pciconf_dev_t *pd; 431 pciconf_win_t *pi, *pm; 432 pcireg_t class, cmd, icr, bhlc, bar, mask, bar64, mask64, busreg; 433 u_int64_t size; 434 int br, width, reg_start, reg_end; 435 436 pd = &pb->device[pb->ndevs]; 437 pd->pc = pb->pc; 438 pd->tag = tag; 439 pd->ppb = NULL; 440 pd->enable = mode; 441 442 class = pci_conf_read(pb->pc, tag, PCI_CLASS_REG); 443 444 cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG); 445 bhlc = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 446 447 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE 448 && PCI_HDRTYPE_TYPE(bhlc) != PCI_HDRTYPE_PPB) { 449 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 450 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 451 pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd); 452 } else if (pci_conf_debug) { 453 print_tag(pb->pc, tag); 454 printf("device is a bridge; not clearing enables\n"); 455 } 456 457 if ((cmd & PCI_STATUS_BACKTOBACK_SUPPORT) == 0) 458 pb->fast_b2b = 0; 459 460 if ((cmd & PCI_STATUS_66MHZ_SUPPORT) == 0) 461 pb->freq_66 = 0; 462 463 switch (PCI_HDRTYPE_TYPE(bhlc)) { 464 case PCI_HDRTYPE_DEVICE: 465 reg_start = PCI_MAPREG_START; 466 reg_end = PCI_MAPREG_END; 467 break; 468 case PCI_HDRTYPE_PPB: 469 pd->ppb = query_bus(pb, pd, dev); 470 if (pd->ppb == NULL) 471 return -1; 472 return 0; 473 case PCI_HDRTYPE_PCB: 474 reg_start = PCI_MAPREG_START; 475 reg_end = PCI_MAPREG_PCB_END; 476 477 busreg = pci_conf_read(pb->pc, tag, PCI_BUSNUM); 478 busreg = (busreg & 0xff000000) | 479 pb->busno << PCI_BRIDGE_BUS_PRIMARY_SHIFT | 480 pb->next_busno << PCI_BRIDGE_BUS_SECONDARY_SHIFT | 481 pb->next_busno << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 482 pci_conf_write(pb->pc, tag, PCI_BUSNUM, busreg); 483 484 pb->next_busno++; 485 break; 486 default: 487 return -1; 488 } 489 490 icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG); 491 pd->ipin = PCI_INTERRUPT_PIN(icr); 492 pd->iline = PCI_INTERRUPT_LINE(icr); 493 pd->min_gnt = PCI_MIN_GNT(icr); 494 pd->max_lat = PCI_MAX_LAT(icr); 495 if (pd->iline || pd->ipin) { 496 pci_conf_interrupt(pb->pc, pb->busno, dev, pd->ipin, pb->swiz, 497 &pd->iline); 498 icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 499 icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT); 500 pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr); 501 } 502 503 if (pd->min_gnt != 0 || pd->max_lat != 0) { 504 if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt) 505 pb->max_mingnt = pd->min_gnt; 506 507 if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat) 508 pb->min_maxlat = pd->max_lat; 509 510 pb->bandwidth_used += pd->min_gnt * 4000000 / 511 (pd->min_gnt + pd->max_lat); 512 } 513 514 width = 4; 515 for (br = reg_start; br < reg_end; br += width) { 516 #if 0 517 /* XXX Should only ignore if IDE not in legacy mode? */ 518 if (PCI_CLASS(class) == PCI_CLASS_MASS_STORAGE && 519 PCI_SUBCLASS(class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 520 break; 521 } 522 #endif 523 bar = pci_conf_read(pb->pc, tag, br); 524 pci_conf_write(pb->pc, tag, br, 0xffffffff); 525 mask = pci_conf_read(pb->pc, tag, br); 526 pci_conf_write(pb->pc, tag, br, bar); 527 width = 4; 528 529 if ( (mode & PCI_CONF_MAP_IO) 530 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO)) { 531 /* 532 * Upper 16 bits must be one. Devices may hardwire 533 * them to zero, though, per PCI 2.2, 6.2.5.1, p 203. 534 */ 535 mask |= 0xffff0000; 536 537 size = PCI_MAPREG_IO_SIZE(mask); 538 if (size == 0) { 539 if (pci_conf_debug) { 540 print_tag(pb->pc, tag); 541 printf("I/O BAR 0x%x is void\n", br); 542 } 543 continue; 544 } 545 546 if (pb->niowin >= MAX_CONF_IO) { 547 printf("pciconf: too many I/O windows\n"); 548 return -1; 549 } 550 551 pi = get_io_desc(pb, size); 552 pi->dev = pd; 553 pi->reg = br; 554 pi->size = (u_int64_t) size; 555 pi->align = 4; 556 pi->prefetch = 0; 557 if (pci_conf_debug) { 558 print_tag(pb->pc, tag); 559 printf("Register 0x%x, I/O size %" PRIu64 "\n", 560 br, pi->size); 561 } 562 pb->niowin++; 563 pb->io_total += size; 564 } else if ((mode & PCI_CONF_MAP_MEM) 565 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_MEM)) { 566 switch (PCI_MAPREG_MEM_TYPE(mask)) { 567 case PCI_MAPREG_MEM_TYPE_32BIT: 568 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 569 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 570 break; 571 case PCI_MAPREG_MEM_TYPE_64BIT: 572 bar64 = pci_conf_read(pb->pc, tag, br + 4); 573 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); 574 mask64 = pci_conf_read(pb->pc, tag, br + 4); 575 pci_conf_write(pb->pc, tag, br + 4, bar64); 576 size = (u_int64_t) PCI_MAPREG_MEM64_SIZE( 577 (((u_int64_t) mask64) << 32) | mask); 578 width = 8; 579 break; 580 default: 581 print_tag(pb->pc, tag); 582 printf("reserved mapping type 0x%x\n", 583 PCI_MAPREG_MEM_TYPE(mask)); 584 continue; 585 } 586 587 if (size == 0) { 588 if (pci_conf_debug) { 589 print_tag(pb->pc, tag); 590 printf("MEM%d BAR 0x%x is void\n", 591 PCI_MAPREG_MEM_TYPE(mask) == 592 PCI_MAPREG_MEM_TYPE_64BIT ? 593 64 : 32, br); 594 } 595 continue; 596 } else { 597 if (pci_conf_debug) { 598 print_tag(pb->pc, tag); 599 printf("MEM%d BAR 0x%x has size %lx\n", 600 PCI_MAPREG_MEM_TYPE(mask) == 601 PCI_MAPREG_MEM_TYPE_64BIT ? 602 64 : 32, br, (unsigned long)size); 603 } 604 } 605 606 if (pb->nmemwin >= MAX_CONF_MEM) { 607 printf("pciconf: too many memory windows\n"); 608 return -1; 609 } 610 611 pm = get_mem_desc(pb, size); 612 pm->dev = pd; 613 pm->reg = br; 614 pm->size = size; 615 pm->align = 4; 616 pm->prefetch = PCI_MAPREG_MEM_PREFETCHABLE(mask); 617 if (pci_conf_debug) { 618 print_tag(pb->pc, tag); 619 printf("Register 0x%x, memory size %" 620 PRIu64 "\n", br, pm->size); 621 } 622 pb->nmemwin++; 623 if (pm->prefetch) { 624 pb->pmem_total += size; 625 } else { 626 pb->mem_total += size; 627 } 628 } 629 } 630 631 if (mode & PCI_CONF_MAP_ROM) { 632 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 633 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 634 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 635 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, bar); 636 637 if (mask != 0 && mask != 0xffffffff) { 638 if (pb->nmemwin >= MAX_CONF_MEM) { 639 printf("pciconf: too many memory windows\n"); 640 return -1; 641 } 642 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 643 644 pm = get_mem_desc(pb, size); 645 pm->dev = pd; 646 pm->reg = PCI_MAPREG_ROM; 647 pm->size = size; 648 pm->align = 4; 649 pm->prefetch = 1; 650 if (pci_conf_debug) { 651 print_tag(pb->pc, tag); 652 printf("Expansion ROM memory size %" 653 PRIu64 "\n", pm->size); 654 } 655 pb->nmemwin++; 656 pb->pmem_total += size; 657 } 658 } else { 659 /* Don't enable ROMs if we aren't going to map them. */ 660 mode &= ~PCI_CONF_ENABLE_ROM; 661 pd->enable &= ~PCI_CONF_ENABLE_ROM; 662 } 663 664 if (!(mode & PCI_CONF_ENABLE_ROM)) { 665 /* Ensure ROM is disabled */ 666 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 667 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 668 bar & ~PCI_MAPREG_ROM_ENABLE); 669 } 670 671 return 0; 672 } 673 674 /************************************************************************/ 675 /************************************************************************/ 676 /******************** Bus configuration routines ********************/ 677 /************************************************************************/ 678 /************************************************************************/ 679 static u_int64_t 680 pci_allocate_range(struct extent *ex, u_int64_t amt, int align) 681 { 682 int r; 683 u_long addr; 684 685 r = extent_alloc(ex, amt, align, 0, EX_NOWAIT, &addr); 686 if (r) { 687 addr = (u_long) -1; 688 printf("extent_alloc(%p, %" PRIu64 ", %d) returned %d\n", 689 ex, amt, align, r); 690 extent_print(ex); 691 } 692 return (pcireg_t) addr; 693 } 694 695 static int 696 setup_iowins(pciconf_bus_t *pb) 697 { 698 pciconf_win_t *pi; 699 pciconf_dev_t *pd; 700 701 for (pi=pb->pciiowin; pi < &pb->pciiowin[pb->niowin] ; pi++) { 702 if (pi->size == 0) 703 continue; 704 705 pd = pi->dev; 706 pi->address = pci_allocate_range(pb->ioext, pi->size, 707 pi->align); 708 if (pi->address == -1) { 709 print_tag(pd->pc, pd->tag); 710 printf("Failed to allocate PCI I/O space (%" 711 PRIu64 " req)\n", pi->size); 712 return -1; 713 } 714 if (pd->ppb && pi->reg == 0) { 715 pd->ppb->ioext = extent_create("pciconf", pi->address, 716 pi->address + pi->size, M_DEVBUF, NULL, 0, 717 EX_NOWAIT); 718 if (pd->ppb->ioext == NULL) { 719 print_tag(pd->pc, pd->tag); 720 printf("Failed to alloc I/O ext. for bus %d\n", 721 pd->ppb->busno); 722 return -1; 723 } 724 continue; 725 } 726 if (!pb->io_32bit && pi->address > 0xFFFF) { 727 pi->address = 0; 728 pd->enable &= ~PCI_CONF_ENABLE_IO; 729 } else { 730 pd->enable |= PCI_CONF_ENABLE_IO; 731 } 732 if (pci_conf_debug) { 733 print_tag(pd->pc, pd->tag); 734 printf("Putting %" PRIu64 " I/O bytes @ %#" PRIx64 735 " (reg %x)\n", pi->size, pi->address, pi->reg); 736 } 737 pci_conf_write(pd->pc, pd->tag, pi->reg, 738 PCI_MAPREG_IO_ADDR(pi->address) | PCI_MAPREG_TYPE_IO); 739 } 740 return 0; 741 } 742 743 static int 744 setup_memwins(pciconf_bus_t *pb) 745 { 746 pciconf_win_t *pm; 747 pciconf_dev_t *pd; 748 pcireg_t base; 749 struct extent *ex; 750 751 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 752 if (pm->size == 0) 753 continue; 754 755 pd = pm->dev; 756 ex = (pm->prefetch) ? pb->pmemext : pb->memext; 757 pm->address = pci_allocate_range(ex, pm->size, pm->align); 758 if (pm->address == -1) { 759 print_tag(pd->pc, pd->tag); 760 printf( 761 "Failed to allocate PCI memory space (%" PRIu64 762 " req)\n", pm->size); 763 return -1; 764 } 765 if (pd->ppb && pm->reg == 0) { 766 ex = extent_create("pciconf", pm->address, 767 pm->address + pm->size, M_DEVBUF, NULL, 0, 768 EX_NOWAIT); 769 if (ex == NULL) { 770 print_tag(pd->pc, pd->tag); 771 printf("Failed to alloc MEM ext. for bus %d\n", 772 pd->ppb->busno); 773 return -1; 774 } 775 if (pm->prefetch) { 776 pd->ppb->pmemext = ex; 777 } else { 778 pd->ppb->memext = ex; 779 } 780 continue; 781 } 782 if (pm->prefetch && !pb->pmem_64bit && 783 pm->address > 0xFFFFFFFFULL) { 784 pm->address = 0; 785 pd->enable &= ~PCI_CONF_ENABLE_MEM; 786 } else { 787 pd->enable |= PCI_CONF_ENABLE_MEM; 788 } 789 if (pm->reg != PCI_MAPREG_ROM) { 790 if (pci_conf_debug) { 791 print_tag(pd->pc, pd->tag); 792 printf( 793 "Putting %" PRIu64 " MEM bytes @ %#" 794 PRIx64 " (reg %x)\n", pm->size, 795 pm->address, pm->reg); 796 } 797 base = pci_conf_read(pd->pc, pd->tag, pm->reg); 798 base = PCI_MAPREG_MEM_ADDR(pm->address) | 799 PCI_MAPREG_MEM_TYPE(base); 800 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 801 if (PCI_MAPREG_MEM_TYPE(base) == 802 PCI_MAPREG_MEM_TYPE_64BIT) { 803 base = (pcireg_t) 804 (PCI_MAPREG_MEM64_ADDR(pm->address) >> 32); 805 pci_conf_write(pd->pc, pd->tag, pm->reg + 4, 806 base); 807 } 808 } 809 } 810 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 811 if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) { 812 pd = pm->dev; 813 if (!(pd->enable & PCI_CONF_MAP_ROM)) 814 continue; 815 if (pci_conf_debug) { 816 print_tag(pd->pc, pd->tag); 817 printf( 818 "Putting %" PRIu64 " ROM bytes @ %#" 819 PRIx64 " (reg %x)\n", pm->size, 820 pm->address, pm->reg); 821 } 822 base = (pcireg_t) pm->address; 823 if (pd->enable & PCI_CONF_ENABLE_ROM) 824 base |= PCI_MAPREG_ROM_ENABLE; 825 826 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 827 } 828 } 829 return 0; 830 } 831 832 /* 833 * Configure I/O, memory, and prefetcable memory spaces, then make 834 * a call to configure_bus(). 835 */ 836 static int 837 configure_bridge(pciconf_dev_t *pd) 838 { 839 unsigned long io_base, io_limit, mem_base, mem_limit; 840 pciconf_bus_t *pb; 841 pcireg_t io, iohigh, mem, cmd; 842 int rv; 843 844 pb = pd->ppb; 845 /* Configure I/O base & limit*/ 846 if (pb->ioext) { 847 io_base = pb->ioext->ex_start; 848 io_limit = pb->ioext->ex_end; 849 } else { 850 io_base = 0x1000; /* 4K */ 851 io_limit = 0x0000; 852 } 853 if (pb->io_32bit) { 854 iohigh = 855 ((io_base >> 16) << PCI_BRIDGE_IOHIGH_BASE_SHIFT) | 856 ((io_limit >> 16) << PCI_BRIDGE_IOHIGH_LIMIT_SHIFT); 857 } else { 858 if (io_limit > 0xFFFF) { 859 printf("Bus %d bridge does not support 32-bit I/O. ", 860 pb->busno); 861 printf("Disabling I/O accesses\n"); 862 io_base = 0x1000; /* 4K */ 863 io_limit = 0x0000; 864 } 865 iohigh = 0; 866 } 867 io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG) & 868 (PCI_BRIDGE_STATIO_STATUS_MASK << PCI_BRIDGE_STATIO_STATUS_SHIFT); 869 io |= (((io_base >> 8) & PCI_BRIDGE_STATIO_IOBASE_MASK) 870 << PCI_BRIDGE_STATIO_IOBASE_SHIFT); 871 io |= (((io_limit >> 8) & PCI_BRIDGE_STATIO_IOLIMIT_MASK) 872 << PCI_BRIDGE_STATIO_IOLIMIT_SHIFT); 873 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io); 874 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh); 875 876 /* Configure mem base & limit */ 877 if (pb->memext) { 878 mem_base = pb->memext->ex_start; 879 mem_limit = pb->memext->ex_end; 880 } else { 881 mem_base = 0x100000; /* 1M */ 882 mem_limit = 0x000000; 883 } 884 #if ULONG_MAX > 0xffffffff 885 if (mem_limit > 0xFFFFFFFFULL) { 886 printf("Bus %d bridge MEM range out of range. ", pb->busno); 887 printf("Disabling MEM accesses\n"); 888 mem_base = 0x100000; /* 1M */ 889 mem_limit = 0x000000; 890 } 891 #endif 892 mem = (((mem_base >> 20) & PCI_BRIDGE_MEMORY_BASE_MASK) 893 << PCI_BRIDGE_MEMORY_BASE_SHIFT); 894 mem |= (((mem_limit >> 20) & PCI_BRIDGE_MEMORY_LIMIT_MASK) 895 << PCI_BRIDGE_MEMORY_LIMIT_SHIFT); 896 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem); 897 898 /* Configure prefetchable mem base & limit */ 899 if (pb->pmemext) { 900 mem_base = pb->pmemext->ex_start; 901 mem_limit = pb->pmemext->ex_end; 902 } else { 903 mem_base = 0x100000; /* 1M */ 904 mem_limit = 0x000000; 905 } 906 mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG); 907 #if ULONG_MAX > 0xffffffff 908 if (!PCI_BRIDGE_PREFETCHMEM_64BITS(mem) && mem_limit > 0xFFFFFFFFULL) { 909 printf("Bus %d bridge does not support 64-bit PMEM. ", 910 pb->busno); 911 printf("Disabling prefetchable-MEM accesses\n"); 912 mem_base = 0x100000; /* 1M */ 913 mem_limit = 0x000000; 914 } 915 #endif 916 mem = (((mem_base >> 20) & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) 917 << PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT); 918 mem |= (((mem_limit >> 20) & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) 919 << PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT); 920 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem); 921 /* 922 * XXX -- 64-bit systems need a lot more than just this... 923 */ 924 if (PCI_BRIDGE_PREFETCHMEM_64BITS(mem)) { 925 mem_base = (uint64_t) mem_base >> 32; 926 mem_limit = (uint64_t) mem_limit >> 32; 927 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHBASE32_REG, 928 mem_base & 0xffffffff); 929 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHLIMIT32_REG, 930 mem_limit & 0xffffffff); 931 } 932 933 rv = configure_bus(pb); 934 935 if (pb->ioext) 936 extent_destroy(pb->ioext); 937 if (pb->memext) 938 extent_destroy(pb->memext); 939 if (pb->pmemext) 940 extent_destroy(pb->pmemext); 941 if (rv == 0) { 942 cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG); 943 cmd &= PCI_BRIDGE_CONTROL_MASK; 944 cmd |= (PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR) 945 << PCI_BRIDGE_CONTROL_SHIFT; 946 if (pb->fast_b2b) { 947 cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B 948 << PCI_BRIDGE_CONTROL_SHIFT; 949 } 950 pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd); 951 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 952 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 953 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 954 } 955 956 return rv; 957 } 958 959 /* 960 * Calculate latency values, allocate I/O and MEM segments, then set them 961 * up. If a PCI-PCI bridge is found, configure the bridge separately, 962 * which will cause a recursive call back here. 963 */ 964 static int 965 configure_bus(pciconf_bus_t *pb) 966 { 967 pciconf_dev_t *pd; 968 int def_ltim, max_ltim, band, bus_mhz; 969 970 if (pb->ndevs == 0) { 971 if (pci_conf_debug) 972 printf("PCI bus %d - no devices\n", pb->busno); 973 return (1); 974 } 975 bus_mhz = pb->freq_66 ? 66 : 33; 976 max_ltim = pb->max_mingnt * bus_mhz / 4; /* cvt to cycle count */ 977 band = 4000000; /* 0.25us cycles/sec */ 978 if (band < pb->bandwidth_used) { 979 printf("PCI bus %d: Warning: Total bandwidth exceeded!? (%d)\n", 980 pb->busno, pb->bandwidth_used); 981 def_ltim = -1; 982 } else { 983 def_ltim = (band - pb->bandwidth_used) / pb->ndevs; 984 if (def_ltim > pb->min_maxlat) 985 def_ltim = pb->min_maxlat; 986 def_ltim = def_ltim * bus_mhz / 4; 987 } 988 def_ltim = (def_ltim + 7) & ~7; 989 max_ltim = (max_ltim + 7) & ~7; 990 991 pb->def_ltim = MIN( def_ltim, 255 ); 992 pb->max_ltim = MIN( MAX(max_ltim, def_ltim ), 255 ); 993 994 /* 995 * Now we have what we need to initialize the devices. 996 * It would probably be better if we could allocate all of these 997 * for all busses at once, but "not right now". First, get a list 998 * of free memory ranges from the m.d. system. 999 */ 1000 if (setup_iowins(pb) || setup_memwins(pb)) { 1001 printf("PCI bus configuration failed: "); 1002 printf("unable to assign all I/O and memory ranges."); 1003 return -1; 1004 } 1005 1006 /* 1007 * Configure the latency for the devices, and enable them. 1008 */ 1009 for (pd=pb->device ; pd < &pb->device[pb->ndevs] ; pd++) { 1010 pcireg_t cmd, class, misc; 1011 int ltim; 1012 1013 if (pci_conf_debug) { 1014 print_tag(pd->pc, pd->tag); 1015 printf("Configuring device.\n"); 1016 } 1017 class = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG); 1018 misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG); 1019 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 1020 if (pd->enable & PCI_CONF_ENABLE_PARITY) 1021 cmd |= PCI_COMMAND_PARITY_ENABLE; 1022 if (pd->enable & PCI_CONF_ENABLE_SERR) 1023 cmd |= PCI_COMMAND_SERR_ENABLE; 1024 if (pb->fast_b2b) 1025 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE; 1026 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 1027 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_PCI) { 1028 if (pd->enable & PCI_CONF_ENABLE_IO) 1029 cmd |= PCI_COMMAND_IO_ENABLE; 1030 if (pd->enable & PCI_CONF_ENABLE_MEM) 1031 cmd |= PCI_COMMAND_MEM_ENABLE; 1032 if (pd->enable & PCI_CONF_ENABLE_BM) 1033 cmd |= PCI_COMMAND_MASTER_ENABLE; 1034 ltim = pd->min_gnt * bus_mhz / 4; 1035 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim); 1036 } else { 1037 cmd |= PCI_COMMAND_MASTER_ENABLE; 1038 ltim = MIN (pb->def_ltim, pb->max_ltim); 1039 } 1040 if ((pd->enable & 1041 (PCI_CONF_ENABLE_MEM|PCI_CONF_ENABLE_IO)) == 0) { 1042 print_tag(pd->pc, pd->tag); 1043 printf("Disabled due to lack of resources.\n"); 1044 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 1045 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 1046 } 1047 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 1048 1049 misc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) | 1050 (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)); 1051 misc |= (ltim & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT; 1052 misc |= ((pb->cacheline_size >> 2) & PCI_CACHELINE_MASK) << 1053 PCI_CACHELINE_SHIFT; 1054 pci_conf_write(pd->pc, pd->tag, PCI_BHLC_REG, misc); 1055 1056 if (pd->ppb) { 1057 if (configure_bridge(pd) < 0) 1058 return -1; 1059 continue; 1060 } 1061 } 1062 1063 if (pci_conf_debug) { 1064 printf("PCI bus %d configured\n", pb->busno); 1065 } 1066 1067 return 0; 1068 } 1069 1070 /* 1071 * Let's configure the PCI bus. 1072 * This consists of basically scanning for all existing devices, 1073 * identifying their needs, and then making another pass over them 1074 * to set: 1075 * 1. I/O addresses 1076 * 2. Memory addresses (Prefetchable and not) 1077 * 3. PCI command register 1078 * 4. The latency part of the PCI BHLC (BIST (Built-In Self Test), 1079 * Header type, Latency timer, Cache line size) register 1080 * 1081 * The command register is set to enable fast back-to-back transactions 1082 * if the host bridge says it can handle it. We also configure 1083 * Master Enable, SERR enable, parity enable, and (if this is not a 1084 * PCI-PCI bridge) the I/O and Memory spaces. Apparently some devices 1085 * will not report some I/O space. 1086 * 1087 * The latency is computed to be a "fair share" of the bus bandwidth. 1088 * The bus bandwidth variable is initialized to the number of PCI cycles 1089 * in one second. The number of cycles taken for one transaction by each 1090 * device (MAX_LAT + MIN_GNT) is then subtracted from the bandwidth. 1091 * Care is taken to ensure that the latency timer won't be set such that 1092 * it would exceed the critical time for any device. 1093 * 1094 * This is complicated somewhat due to the presence of bridges. PCI-PCI 1095 * bridges are probed and configured recursively. 1096 */ 1097 int 1098 pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext, 1099 struct extent *memext, struct extent *pmemext, int firstbus, 1100 int cacheline_size) 1101 { 1102 pciconf_bus_t *pb; 1103 int rv; 1104 1105 pb = kmem_zalloc(sizeof (pciconf_bus_t), KM_NOSLEEP); 1106 pb->busno = firstbus; 1107 pb->next_busno = pb->busno + 1; 1108 pb->last_busno = 255; 1109 pb->cacheline_size = cacheline_size; 1110 pb->parent_bus = NULL; 1111 pb->swiz = 0; 1112 pb->io_32bit = 1; 1113 pb->pmem_64bit = 0; 1114 pb->ioext = ioext; 1115 pb->memext = memext; 1116 if (pmemext == NULL) { 1117 pb->pmemext = memext; 1118 } else { 1119 pb->pmemext = pmemext; 1120 } 1121 pb->pc = pc; 1122 pb->io_total = pb->mem_total = pb->pmem_total = 0; 1123 1124 rv = probe_bus(pb); 1125 pb->last_busno = pb->next_busno-1; 1126 if (rv == 0) { 1127 rv = configure_bus(pb); 1128 } 1129 1130 /* 1131 * All done! 1132 */ 1133 kmem_free(pb, sizeof(*pb)); 1134 return rv; 1135 } 1136
Indexes created Wed Sep 24 15:09:51 GMT 2025