pciconf.c revision 1.33
1 /* $NetBSD: pciconf.c,v 1.33 2011/08/24 20:27:35 dyoung Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Derived in part from code from PMON/2000 (http://pmon.groupbsd.org/). 39 */ 40 41 /* 42 * To do: 43 * - Perform all data structure allocation dynamically, don't have 44 * statically-sized arrays ("oops, you lose because you have too 45 * many slots filled!") 46 * - Do this in 2 passes, with an MD hook to control the behavior: 47 * (1) Configure the bus (possibly including expansion 48 * ROMs. 49 * (2) Another pass to disable expansion ROMs if they're 50 * mapped (since you're not supposed to leave them 51 * mapped when you're not using them). 52 * This would facilitate MD code executing the expansion ROMs 53 * if necessary (possibly with an x86 emulator) to configure 54 * devices (e.g. VGA cards). 55 * - Deal with "anything can be hot-plugged" -- i.e., carry configuration 56 * information around & be able to reconfigure on the fly 57 * - Deal with segments (See IA64 System Abstraction Layer) 58 * - Deal with subtractive bridges (& non-spec positive/subtractive decode) 59 * - Deal with ISA/VGA/VGA palette snooping 60 * - Deal with device capabilities on bridges 61 * - Worry about changing a bridge to/from transparency 62 * From thorpej (05/25/01) 63 * - Try to handle devices that are already configured (perhaps using that 64 * as a hint to where we put other devices) 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: pciconf.c,v 1.33 2011/08/24 20:27:35 dyoung Exp $"); 69 70 #include "opt_pci.h" 71 72 #include <sys/param.h> 73 #include <sys/extent.h> 74 #include <sys/queue.h> 75 #include <sys/systm.h> 76 #include <sys/malloc.h> 77 #include <sys/kmem.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pciconf.h> 81 #include <dev/pci/pcidevs.h> 82 #include <dev/pci/pccbbreg.h> 83 84 int pci_conf_debug = 0; 85 86 #if !defined(MIN) 87 #define MIN(a,b) (((a)<(b))?(a):(b)) 88 #define MAX(a,b) (((a)>(b))?(a):(b)) 89 #endif 90 91 /* per-bus constants. */ 92 #define MAX_CONF_DEV 32 /* Arbitrary */ 93 #define MAX_CONF_MEM (3 * MAX_CONF_DEV) /* Avg. 3 per device -- Arb. */ 94 #define MAX_CONF_IO (3 * MAX_CONF_DEV) /* Avg. 1 per device -- Arb. */ 95 96 struct _s_pciconf_bus_t; /* Forward declaration */ 97 98 typedef struct _s_pciconf_dev_t { 99 int ipin; 100 int iline; 101 int min_gnt; 102 int max_lat; 103 int enable; 104 pcitag_t tag; 105 pci_chipset_tag_t pc; 106 struct _s_pciconf_bus_t *ppb; /* I am really a bridge */ 107 } pciconf_dev_t; 108 109 typedef struct _s_pciconf_win_t { 110 pciconf_dev_t *dev; 111 int reg; /* 0 for busses */ 112 int align; 113 int prefetch; 114 u_int64_t size; 115 u_int64_t address; 116 } pciconf_win_t; 117 118 typedef struct _s_pciconf_bus_t { 119 int busno; 120 int next_busno; 121 int last_busno; 122 int max_mingnt; 123 int min_maxlat; 124 int cacheline_size; 125 int prefetch; 126 int fast_b2b; 127 int freq_66; 128 int def_ltim; 129 int max_ltim; 130 int bandwidth_used; 131 int swiz; 132 int io_32bit; 133 int pmem_64bit; 134 135 int ndevs; 136 pciconf_dev_t device[MAX_CONF_DEV]; 137 138 /* These should be sorted in order of decreasing size */ 139 int nmemwin; 140 pciconf_win_t pcimemwin[MAX_CONF_MEM]; 141 int niowin; 142 pciconf_win_t pciiowin[MAX_CONF_IO]; 143 144 bus_size_t io_total; 145 bus_size_t mem_total; 146 bus_size_t pmem_total; 147 148 struct extent *ioext; 149 struct extent *memext; 150 struct extent *pmemext; 151 152 pci_chipset_tag_t pc; 153 struct _s_pciconf_bus_t *parent_bus; 154 } pciconf_bus_t; 155 156 static int probe_bus(pciconf_bus_t *); 157 static void alloc_busno(pciconf_bus_t *, pciconf_bus_t *); 158 static void set_busreg(pci_chipset_tag_t, pcitag_t, int, int, int); 159 static int pci_do_device_query(pciconf_bus_t *, pcitag_t, int, int, int); 160 static int setup_iowins(pciconf_bus_t *); 161 static int setup_memwins(pciconf_bus_t *); 162 static int configure_bridge(pciconf_dev_t *); 163 static int configure_bus(pciconf_bus_t *); 164 static u_int64_t pci_allocate_range(struct extent *, u_int64_t, int); 165 static pciconf_win_t *get_io_desc(pciconf_bus_t *, bus_size_t); 166 static pciconf_win_t *get_mem_desc(pciconf_bus_t *, bus_size_t); 167 static pciconf_bus_t *query_bus(pciconf_bus_t *, pciconf_dev_t *, int); 168 169 static void print_tag(pci_chipset_tag_t, pcitag_t); 170 171 static void 172 print_tag(pci_chipset_tag_t pc, pcitag_t tag) 173 { 174 int bus, dev, func; 175 176 pci_decompose_tag(pc, tag, &bus, &dev, &func); 177 printf("PCI: bus %d, device %d, function %d: ", bus, dev, func); 178 } 179 180 /************************************************************************/ 181 /************************************************************************/ 182 /*********************** Bus probing routines ***********************/ 183 /************************************************************************/ 184 /************************************************************************/ 185 static pciconf_win_t * 186 get_io_desc(pciconf_bus_t *pb, bus_size_t size) 187 { 188 int i, n; 189 190 n = pb->niowin; 191 for (i=n; i > 0 && size > pb->pciiowin[i-1].size; i--) 192 pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */ 193 return &pb->pciiowin[i]; 194 } 195 196 static pciconf_win_t * 197 get_mem_desc(pciconf_bus_t *pb, bus_size_t size) 198 { 199 int i, n; 200 201 n = pb->nmemwin; 202 for (i=n; i > 0 && size > pb->pcimemwin[i-1].size; i--) 203 pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */ 204 return &pb->pcimemwin[i]; 205 } 206 207 /* 208 * Set up bus common stuff, then loop over devices & functions. 209 * If we find something, call pci_do_device_query()). 210 */ 211 static int 212 probe_bus(pciconf_bus_t *pb) 213 { 214 int device; 215 uint8_t devs[32]; 216 int i, n; 217 218 pb->ndevs = 0; 219 pb->niowin = 0; 220 pb->nmemwin = 0; 221 pb->freq_66 = 1; 222 #ifdef PCICONF_NO_FAST_B2B 223 pb->fast_b2b = 0; 224 #else 225 pb->fast_b2b = 1; 226 #endif 227 pb->prefetch = 1; 228 pb->max_mingnt = 0; /* we are looking for the maximum */ 229 pb->min_maxlat = 0x100; /* we are looking for the minimum */ 230 pb->bandwidth_used = 0; 231 232 n = pci_bus_devorder(pb->pc, pb->busno, devs, __arraycount(devs)); 233 for (i = 0; i < n; i++) { 234 pcitag_t tag; 235 pcireg_t id, bhlcr; 236 int function, nfunction; 237 int confmode; 238 239 device = devs[i]; 240 241 tag = pci_make_tag(pb->pc, pb->busno, device, 0); 242 if (pci_conf_debug) { 243 print_tag(pb->pc, tag); 244 } 245 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 246 247 if (pci_conf_debug) { 248 printf("id=%x: Vendor=%x, Product=%x\n", 249 id, PCI_VENDOR(id),PCI_PRODUCT(id)); 250 } 251 /* Invalid vendor ID value? */ 252 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 253 continue; 254 255 bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 256 nfunction = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 257 for (function = 0 ; function < nfunction ; function++) { 258 tag = pci_make_tag(pb->pc, pb->busno, device, function); 259 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 260 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 261 continue; 262 if (pb->ndevs+1 < MAX_CONF_DEV) { 263 if (pci_conf_debug) { 264 print_tag(pb->pc, tag); 265 printf("Found dev 0x%04x 0x%04x -- " 266 "really probing.\n", 267 PCI_VENDOR(id), PCI_PRODUCT(id)); 268 } 269 #ifdef __HAVE_PCI_CONF_HOOK 270 confmode = pci_conf_hook(pb->pc, pb->busno, 271 device, function, id); 272 if (confmode == 0) 273 continue; 274 #else 275 /* 276 * Don't enable expansion ROMS -- some cards 277 * share address decoders between the EXPROM 278 * and PCI memory space, and enabling the ROM 279 * when not needed will cause all sorts of 280 * lossage. 281 */ 282 confmode = PCI_CONF_DEFAULT; 283 #endif 284 if (pci_do_device_query(pb, tag, device, 285 function, confmode)) 286 return -1; 287 pb->ndevs++; 288 } 289 } 290 } 291 return 0; 292 } 293 294 static void 295 alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb) 296 { 297 pb->busno = parent->next_busno; 298 pb->next_busno = pb->busno + 1; 299 } 300 301 static void 302 set_busreg(pci_chipset_tag_t pc, pcitag_t tag, int prim, int sec, int sub) 303 { 304 pcireg_t busreg; 305 306 busreg = prim << PCI_BRIDGE_BUS_PRIMARY_SHIFT; 307 busreg |= sec << PCI_BRIDGE_BUS_SECONDARY_SHIFT; 308 busreg |= sub << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 309 pci_conf_write(pc, tag, PCI_BRIDGE_BUS_REG, busreg); 310 } 311 312 static pciconf_bus_t * 313 query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev) 314 { 315 pciconf_bus_t *pb; 316 pcireg_t io, pmem; 317 pciconf_win_t *pi, *pm; 318 319 pb = kmem_zalloc(sizeof (pciconf_bus_t), KM_NOSLEEP); 320 if (!pb) 321 panic("Unable to allocate memory for PCI configuration."); 322 323 pb->cacheline_size = parent->cacheline_size; 324 pb->parent_bus = parent; 325 alloc_busno(parent, pb); 326 327 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 0xff); 328 329 pb->swiz = parent->swiz + dev; 330 331 pb->ioext = NULL; 332 pb->memext = NULL; 333 pb->pmemext = NULL; 334 pb->pc = parent->pc; 335 pb->io_total = pb->mem_total = pb->pmem_total = 0; 336 337 pb->io_32bit = 0; 338 if (parent->io_32bit) { 339 io = pci_conf_read(parent->pc, pd->tag, PCI_BRIDGE_STATIO_REG); 340 if (PCI_BRIDGE_IO_32BITS(io)) { 341 pb->io_32bit = 1; 342 } 343 } 344 345 pb->pmem_64bit = 0; 346 if (parent->pmem_64bit) { 347 pmem = pci_conf_read(parent->pc, pd->tag, 348 PCI_BRIDGE_PREFETCHMEM_REG); 349 if (PCI_BRIDGE_PREFETCHMEM_64BITS(pmem)) { 350 pb->pmem_64bit = 1; 351 } 352 } 353 354 if (probe_bus(pb)) { 355 printf("Failed to probe bus %d\n", pb->busno); 356 goto err; 357 } 358 359 /* We have found all subordinate busses now, reprogram busreg. */ 360 pb->last_busno = pb->next_busno-1; 361 parent->next_busno = pb->next_busno; 362 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 363 pb->last_busno); 364 if (pci_conf_debug) 365 printf("PCI bus bridge (parent %d) covers busses %d-%d\n", 366 parent->busno, pb->busno, pb->last_busno); 367 368 if (pb->io_total > 0) { 369 if (parent->niowin >= MAX_CONF_IO) { 370 printf("pciconf: too many I/O windows\n"); 371 goto err; 372 } 373 pb->io_total |= 0xfff; /* Round up */ 374 pi = get_io_desc(parent, pb->io_total); 375 pi->dev = pd; 376 pi->reg = 0; 377 pi->size = pb->io_total; 378 pi->align = 0x1000; /* 4K alignment */ 379 pi->prefetch = 0; 380 parent->niowin++; 381 parent->io_total += pb->io_total; 382 } 383 384 if (pb->mem_total > 0) { 385 if (parent->nmemwin >= MAX_CONF_MEM) { 386 printf("pciconf: too many MEM windows\n"); 387 goto err; 388 } 389 pb->mem_total |= 0xfffff; /* Round up */ 390 pm = get_mem_desc(parent, pb->mem_total); 391 pm->dev = pd; 392 pm->reg = 0; 393 pm->size = pb->mem_total; 394 pm->align = 0x100000; /* 1M alignment */ 395 pm->prefetch = 0; 396 parent->nmemwin++; 397 parent->mem_total += pb->mem_total; 398 } 399 400 if (pb->pmem_total > 0) { 401 if (parent->nmemwin >= MAX_CONF_MEM) { 402 printf("pciconf: too many MEM windows\n"); 403 goto err; 404 } 405 pb->pmem_total |= 0xfffff; /* Round up */ 406 pm = get_mem_desc(parent, pb->pmem_total); 407 pm->dev = pd; 408 pm->reg = 0; 409 pm->size = pb->pmem_total; 410 pm->align = 0x100000; /* 1M alignment */ 411 pm->prefetch = 1; 412 parent->nmemwin++; 413 parent->pmem_total += pb->pmem_total; 414 } 415 416 return pb; 417 err: 418 kmem_free(pb, sizeof(*pb)); 419 return NULL; 420 } 421 422 static int 423 pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func, int mode) 424 { 425 pciconf_dev_t *pd; 426 pciconf_win_t *pi, *pm; 427 pcireg_t class, cmd, icr, bhlc, bar, mask, bar64, mask64, busreg; 428 u_int64_t size; 429 int br, width, reg_start, reg_end; 430 431 pd = &pb->device[pb->ndevs]; 432 pd->pc = pb->pc; 433 pd->tag = tag; 434 pd->ppb = NULL; 435 pd->enable = mode; 436 437 class = pci_conf_read(pb->pc, tag, PCI_CLASS_REG); 438 439 cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG); 440 bhlc = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 441 442 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE 443 && PCI_HDRTYPE_TYPE(bhlc) != PCI_HDRTYPE_PPB) { 444 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 445 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 446 pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd); 447 } else if (pci_conf_debug) { 448 print_tag(pb->pc, tag); 449 printf("device is a bridge; not clearing enables\n"); 450 } 451 452 if ((cmd & PCI_STATUS_BACKTOBACK_SUPPORT) == 0) 453 pb->fast_b2b = 0; 454 455 if ((cmd & PCI_STATUS_66MHZ_SUPPORT) == 0) 456 pb->freq_66 = 0; 457 458 switch (PCI_HDRTYPE_TYPE(bhlc)) { 459 case PCI_HDRTYPE_DEVICE: 460 reg_start = PCI_MAPREG_START; 461 reg_end = PCI_MAPREG_END; 462 break; 463 case PCI_HDRTYPE_PPB: 464 pd->ppb = query_bus(pb, pd, dev); 465 if (pd->ppb == NULL) 466 return -1; 467 return 0; 468 case PCI_HDRTYPE_PCB: 469 reg_start = PCI_MAPREG_START; 470 reg_end = PCI_MAPREG_PCB_END; 471 472 busreg = pci_conf_read(pb->pc, tag, PCI_BUSNUM); 473 busreg = (busreg & 0xff000000) | 474 pb->busno << PCI_BRIDGE_BUS_PRIMARY_SHIFT | 475 pb->next_busno << PCI_BRIDGE_BUS_SECONDARY_SHIFT | 476 pb->next_busno << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 477 pci_conf_write(pb->pc, tag, PCI_BUSNUM, busreg); 478 479 pb->next_busno++; 480 break; 481 default: 482 return -1; 483 } 484 485 icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG); 486 pd->ipin = PCI_INTERRUPT_PIN(icr); 487 pd->iline = PCI_INTERRUPT_LINE(icr); 488 pd->min_gnt = PCI_MIN_GNT(icr); 489 pd->max_lat = PCI_MAX_LAT(icr); 490 if (pd->iline || pd->ipin) { 491 pci_conf_interrupt(pb->pc, pb->busno, dev, pd->ipin, pb->swiz, 492 &pd->iline); 493 icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 494 icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT); 495 pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr); 496 } 497 498 if (pd->min_gnt != 0 || pd->max_lat != 0) { 499 if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt) 500 pb->max_mingnt = pd->min_gnt; 501 502 if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat) 503 pb->min_maxlat = pd->max_lat; 504 505 pb->bandwidth_used += pd->min_gnt * 4000000 / 506 (pd->min_gnt + pd->max_lat); 507 } 508 509 width = 4; 510 for (br = reg_start; br < reg_end; br += width) { 511 #if 0 512 /* XXX Should only ignore if IDE not in legacy mode? */ 513 if (PCI_CLASS(class) == PCI_CLASS_MASS_STORAGE && 514 PCI_SUBCLASS(class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 515 break; 516 } 517 #endif 518 bar = pci_conf_read(pb->pc, tag, br); 519 pci_conf_write(pb->pc, tag, br, 0xffffffff); 520 mask = pci_conf_read(pb->pc, tag, br); 521 pci_conf_write(pb->pc, tag, br, bar); 522 width = 4; 523 524 if ( (mode & PCI_CONF_MAP_IO) 525 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO)) { 526 /* 527 * Upper 16 bits must be one. Devices may hardwire 528 * them to zero, though, per PCI 2.2, 6.2.5.1, p 203. 529 */ 530 mask |= 0xffff0000; 531 532 size = PCI_MAPREG_IO_SIZE(mask); 533 if (size == 0) { 534 if (pci_conf_debug) { 535 print_tag(pb->pc, tag); 536 printf("I/O BAR 0x%x is void\n", br); 537 } 538 continue; 539 } 540 541 if (pb->niowin >= MAX_CONF_IO) { 542 printf("pciconf: too many I/O windows\n"); 543 return -1; 544 } 545 546 pi = get_io_desc(pb, size); 547 pi->dev = pd; 548 pi->reg = br; 549 pi->size = (u_int64_t) size; 550 pi->align = 4; 551 pi->prefetch = 0; 552 if (pci_conf_debug) { 553 print_tag(pb->pc, tag); 554 printf("Register 0x%x, I/O size %" PRIu64 "\n", 555 br, pi->size); 556 } 557 pb->niowin++; 558 pb->io_total += size; 559 } else if ((mode & PCI_CONF_MAP_MEM) 560 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_MEM)) { 561 switch (PCI_MAPREG_MEM_TYPE(mask)) { 562 case PCI_MAPREG_MEM_TYPE_32BIT: 563 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 564 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 565 break; 566 case PCI_MAPREG_MEM_TYPE_64BIT: 567 bar64 = pci_conf_read(pb->pc, tag, br + 4); 568 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); 569 mask64 = pci_conf_read(pb->pc, tag, br + 4); 570 pci_conf_write(pb->pc, tag, br + 4, bar64); 571 size = (u_int64_t) PCI_MAPREG_MEM64_SIZE( 572 (((u_int64_t) mask64) << 32) | mask); 573 width = 8; 574 break; 575 default: 576 print_tag(pb->pc, tag); 577 printf("reserved mapping type 0x%x\n", 578 PCI_MAPREG_MEM_TYPE(mask)); 579 continue; 580 } 581 582 if (size == 0) { 583 if (pci_conf_debug) { 584 print_tag(pb->pc, tag); 585 printf("MEM%d BAR 0x%x is void\n", 586 PCI_MAPREG_MEM_TYPE(mask) == 587 PCI_MAPREG_MEM_TYPE_64BIT ? 588 64 : 32, br); 589 } 590 continue; 591 } else { 592 if (pci_conf_debug) { 593 print_tag(pb->pc, tag); 594 printf("MEM%d BAR 0x%x has size %lx\n", 595 PCI_MAPREG_MEM_TYPE(mask) == 596 PCI_MAPREG_MEM_TYPE_64BIT ? 597 64 : 32, br, (unsigned long)size); 598 } 599 } 600 601 if (pb->nmemwin >= MAX_CONF_MEM) { 602 printf("pciconf: too many memory windows\n"); 603 return -1; 604 } 605 606 pm = get_mem_desc(pb, size); 607 pm->dev = pd; 608 pm->reg = br; 609 pm->size = size; 610 pm->align = 4; 611 pm->prefetch = PCI_MAPREG_MEM_PREFETCHABLE(mask); 612 if (pci_conf_debug) { 613 print_tag(pb->pc, tag); 614 printf("Register 0x%x, memory size %" 615 PRIu64 "\n", br, pm->size); 616 } 617 pb->nmemwin++; 618 if (pm->prefetch) { 619 pb->pmem_total += size; 620 } else { 621 pb->mem_total += size; 622 } 623 } 624 } 625 626 if (mode & PCI_CONF_MAP_ROM) { 627 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 628 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 629 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 630 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, bar); 631 632 if (mask != 0 && mask != 0xffffffff) { 633 if (pb->nmemwin >= MAX_CONF_MEM) { 634 printf("pciconf: too many memory windows\n"); 635 return -1; 636 } 637 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 638 639 pm = get_mem_desc(pb, size); 640 pm->dev = pd; 641 pm->reg = PCI_MAPREG_ROM; 642 pm->size = size; 643 pm->align = 4; 644 pm->prefetch = 1; 645 if (pci_conf_debug) { 646 print_tag(pb->pc, tag); 647 printf("Expansion ROM memory size %" 648 PRIu64 "\n", pm->size); 649 } 650 pb->nmemwin++; 651 pb->pmem_total += size; 652 } 653 } else { 654 /* Don't enable ROMs if we aren't going to map them. */ 655 mode &= ~PCI_CONF_ENABLE_ROM; 656 pd->enable &= ~PCI_CONF_ENABLE_ROM; 657 } 658 659 if (!(mode & PCI_CONF_ENABLE_ROM)) { 660 /* Ensure ROM is disabled */ 661 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 662 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 663 bar & ~PCI_MAPREG_ROM_ENABLE); 664 } 665 666 return 0; 667 } 668 669 /************************************************************************/ 670 /************************************************************************/ 671 /******************** Bus configuration routines ********************/ 672 /************************************************************************/ 673 /************************************************************************/ 674 static u_int64_t 675 pci_allocate_range(struct extent *ex, u_int64_t amt, int align) 676 { 677 int r; 678 u_long addr; 679 680 r = extent_alloc(ex, amt, align, 0, EX_NOWAIT, &addr); 681 if (r) { 682 addr = (u_long) -1; 683 printf("extent_alloc(%p, %" PRIu64 ", %d) returned %d\n", 684 ex, amt, align, r); 685 extent_print(ex); 686 } 687 return (pcireg_t) addr; 688 } 689 690 static int 691 setup_iowins(pciconf_bus_t *pb) 692 { 693 pciconf_win_t *pi; 694 pciconf_dev_t *pd; 695 696 for (pi=pb->pciiowin; pi < &pb->pciiowin[pb->niowin] ; pi++) { 697 if (pi->size == 0) 698 continue; 699 700 pd = pi->dev; 701 pi->address = pci_allocate_range(pb->ioext, pi->size, 702 pi->align); 703 if (pi->address == -1) { 704 print_tag(pd->pc, pd->tag); 705 printf("Failed to allocate PCI I/O space (%" 706 PRIu64 " req)\n", pi->size); 707 return -1; 708 } 709 if (pd->ppb && pi->reg == 0) { 710 pd->ppb->ioext = extent_create("pciconf", pi->address, 711 pi->address + pi->size, M_DEVBUF, NULL, 0, 712 EX_NOWAIT); 713 if (pd->ppb->ioext == NULL) { 714 print_tag(pd->pc, pd->tag); 715 printf("Failed to alloc I/O ext. for bus %d\n", 716 pd->ppb->busno); 717 return -1; 718 } 719 continue; 720 } 721 if (!pb->io_32bit && pi->address > 0xFFFF) { 722 pi->address = 0; 723 pd->enable &= ~PCI_CONF_ENABLE_IO; 724 } else { 725 pd->enable |= PCI_CONF_ENABLE_IO; 726 } 727 if (pci_conf_debug) { 728 print_tag(pd->pc, pd->tag); 729 printf("Putting %" PRIu64 " I/O bytes @ %#" PRIx64 730 " (reg %x)\n", pi->size, pi->address, pi->reg); 731 } 732 pci_conf_write(pd->pc, pd->tag, pi->reg, 733 PCI_MAPREG_IO_ADDR(pi->address) | PCI_MAPREG_TYPE_IO); 734 } 735 return 0; 736 } 737 738 static int 739 setup_memwins(pciconf_bus_t *pb) 740 { 741 pciconf_win_t *pm; 742 pciconf_dev_t *pd; 743 pcireg_t base; 744 struct extent *ex; 745 746 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 747 if (pm->size == 0) 748 continue; 749 750 pd = pm->dev; 751 ex = (pm->prefetch) ? pb->pmemext : pb->memext; 752 pm->address = pci_allocate_range(ex, pm->size, pm->align); 753 if (pm->address == -1) { 754 print_tag(pd->pc, pd->tag); 755 printf( 756 "Failed to allocate PCI memory space (%" PRIu64 757 " req)\n", pm->size); 758 return -1; 759 } 760 if (pd->ppb && pm->reg == 0) { 761 ex = extent_create("pciconf", pm->address, 762 pm->address + pm->size, M_DEVBUF, NULL, 0, 763 EX_NOWAIT); 764 if (ex == NULL) { 765 print_tag(pd->pc, pd->tag); 766 printf("Failed to alloc MEM ext. for bus %d\n", 767 pd->ppb->busno); 768 return -1; 769 } 770 if (pm->prefetch) { 771 pd->ppb->pmemext = ex; 772 } else { 773 pd->ppb->memext = ex; 774 } 775 continue; 776 } 777 if (pm->prefetch && !pb->pmem_64bit && 778 pm->address > 0xFFFFFFFFULL) { 779 pm->address = 0; 780 pd->enable &= ~PCI_CONF_ENABLE_MEM; 781 } else { 782 pd->enable |= PCI_CONF_ENABLE_MEM; 783 } 784 if (pm->reg != PCI_MAPREG_ROM) { 785 if (pci_conf_debug) { 786 print_tag(pd->pc, pd->tag); 787 printf( 788 "Putting %" PRIu64 " MEM bytes @ %#" 789 PRIx64 " (reg %x)\n", pm->size, 790 pm->address, pm->reg); 791 } 792 base = pci_conf_read(pd->pc, pd->tag, pm->reg); 793 base = PCI_MAPREG_MEM_ADDR(pm->address) | 794 PCI_MAPREG_MEM_TYPE(base); 795 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 796 if (PCI_MAPREG_MEM_TYPE(base) == 797 PCI_MAPREG_MEM_TYPE_64BIT) { 798 base = (pcireg_t) 799 (PCI_MAPREG_MEM64_ADDR(pm->address) >> 32); 800 pci_conf_write(pd->pc, pd->tag, pm->reg + 4, 801 base); 802 } 803 } 804 } 805 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 806 if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) { 807 pd = pm->dev; 808 if (!(pd->enable & PCI_CONF_MAP_ROM)) 809 continue; 810 if (pci_conf_debug) { 811 print_tag(pd->pc, pd->tag); 812 printf( 813 "Putting %" PRIu64 " ROM bytes @ %#" 814 PRIx64 " (reg %x)\n", pm->size, 815 pm->address, pm->reg); 816 } 817 base = (pcireg_t) pm->address; 818 if (pd->enable & PCI_CONF_ENABLE_ROM) 819 base |= PCI_MAPREG_ROM_ENABLE; 820 821 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 822 } 823 } 824 return 0; 825 } 826 827 /* 828 * Configure I/O, memory, and prefetcable memory spaces, then make 829 * a call to configure_bus(). 830 */ 831 static int 832 configure_bridge(pciconf_dev_t *pd) 833 { 834 unsigned long io_base, io_limit, mem_base, mem_limit; 835 pciconf_bus_t *pb; 836 pcireg_t io, iohigh, mem, cmd; 837 int rv; 838 839 pb = pd->ppb; 840 /* Configure I/O base & limit*/ 841 if (pb->ioext) { 842 io_base = pb->ioext->ex_start; 843 io_limit = pb->ioext->ex_end; 844 } else { 845 io_base = 0x1000; /* 4K */ 846 io_limit = 0x0000; 847 } 848 if (pb->io_32bit) { 849 iohigh = 850 ((io_base >> 16) << PCI_BRIDGE_IOHIGH_BASE_SHIFT) | 851 ((io_limit >> 16) << PCI_BRIDGE_IOHIGH_LIMIT_SHIFT); 852 } else { 853 if (io_limit > 0xFFFF) { 854 printf("Bus %d bridge does not support 32-bit I/O. ", 855 pb->busno); 856 printf("Disabling I/O accesses\n"); 857 io_base = 0x1000; /* 4K */ 858 io_limit = 0x0000; 859 } 860 iohigh = 0; 861 } 862 io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG) & 863 (PCI_BRIDGE_STATIO_STATUS_MASK << PCI_BRIDGE_STATIO_STATUS_SHIFT); 864 io |= (((io_base >> 8) & PCI_BRIDGE_STATIO_IOBASE_MASK) 865 << PCI_BRIDGE_STATIO_IOBASE_SHIFT); 866 io |= (((io_limit >> 8) & PCI_BRIDGE_STATIO_IOLIMIT_MASK) 867 << PCI_BRIDGE_STATIO_IOLIMIT_SHIFT); 868 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io); 869 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh); 870 871 /* Configure mem base & limit */ 872 if (pb->memext) { 873 mem_base = pb->memext->ex_start; 874 mem_limit = pb->memext->ex_end; 875 } else { 876 mem_base = 0x100000; /* 1M */ 877 mem_limit = 0x000000; 878 } 879 #if ULONG_MAX > 0xffffffff 880 if (mem_limit > 0xFFFFFFFFULL) { 881 printf("Bus %d bridge MEM range out of range. ", pb->busno); 882 printf("Disabling MEM accesses\n"); 883 mem_base = 0x100000; /* 1M */ 884 mem_limit = 0x000000; 885 } 886 #endif 887 mem = (((mem_base >> 20) & PCI_BRIDGE_MEMORY_BASE_MASK) 888 << PCI_BRIDGE_MEMORY_BASE_SHIFT); 889 mem |= (((mem_limit >> 20) & PCI_BRIDGE_MEMORY_LIMIT_MASK) 890 << PCI_BRIDGE_MEMORY_LIMIT_SHIFT); 891 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem); 892 893 /* Configure prefetchable mem base & limit */ 894 if (pb->pmemext) { 895 mem_base = pb->pmemext->ex_start; 896 mem_limit = pb->pmemext->ex_end; 897 } else { 898 mem_base = 0x100000; /* 1M */ 899 mem_limit = 0x000000; 900 } 901 mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG); 902 #if ULONG_MAX > 0xffffffff 903 if (!PCI_BRIDGE_PREFETCHMEM_64BITS(mem) && mem_limit > 0xFFFFFFFFULL) { 904 printf("Bus %d bridge does not support 64-bit PMEM. ", 905 pb->busno); 906 printf("Disabling prefetchable-MEM accesses\n"); 907 mem_base = 0x100000; /* 1M */ 908 mem_limit = 0x000000; 909 } 910 #endif 911 mem = (((mem_base >> 20) & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) 912 << PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT); 913 mem |= (((mem_limit >> 20) & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) 914 << PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT); 915 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem); 916 /* 917 * XXX -- 64-bit systems need a lot more than just this... 918 */ 919 if (PCI_BRIDGE_PREFETCHMEM_64BITS(mem)) { 920 mem_base = (uint64_t) mem_base >> 32; 921 mem_limit = (uint64_t) mem_limit >> 32; 922 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHBASE32_REG, 923 mem_base & 0xffffffff); 924 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHLIMIT32_REG, 925 mem_limit & 0xffffffff); 926 } 927 928 rv = configure_bus(pb); 929 930 if (pb->ioext) 931 extent_destroy(pb->ioext); 932 if (pb->memext) 933 extent_destroy(pb->memext); 934 if (pb->pmemext) 935 extent_destroy(pb->pmemext); 936 if (rv == 0) { 937 cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG); 938 cmd &= PCI_BRIDGE_CONTROL_MASK; 939 cmd |= (PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR) 940 << PCI_BRIDGE_CONTROL_SHIFT; 941 if (pb->fast_b2b) { 942 cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B 943 << PCI_BRIDGE_CONTROL_SHIFT; 944 } 945 pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd); 946 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 947 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 948 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 949 } 950 951 return rv; 952 } 953 954 /* 955 * Calculate latency values, allocate I/O and MEM segments, then set them 956 * up. If a PCI-PCI bridge is found, configure the bridge separately, 957 * which will cause a recursive call back here. 958 */ 959 static int 960 configure_bus(pciconf_bus_t *pb) 961 { 962 pciconf_dev_t *pd; 963 int def_ltim, max_ltim, band, bus_mhz; 964 965 if (pb->ndevs == 0) { 966 if (pci_conf_debug) 967 printf("PCI bus %d - no devices\n", pb->busno); 968 return (1); 969 } 970 bus_mhz = pb->freq_66 ? 66 : 33; 971 max_ltim = pb->max_mingnt * bus_mhz / 4; /* cvt to cycle count */ 972 band = 4000000; /* 0.25us cycles/sec */ 973 if (band < pb->bandwidth_used) { 974 printf("PCI bus %d: Warning: Total bandwidth exceeded!? (%d)\n", 975 pb->busno, pb->bandwidth_used); 976 def_ltim = -1; 977 } else { 978 def_ltim = (band - pb->bandwidth_used) / pb->ndevs; 979 if (def_ltim > pb->min_maxlat) 980 def_ltim = pb->min_maxlat; 981 def_ltim = def_ltim * bus_mhz / 4; 982 } 983 def_ltim = (def_ltim + 7) & ~7; 984 max_ltim = (max_ltim + 7) & ~7; 985 986 pb->def_ltim = MIN( def_ltim, 255 ); 987 pb->max_ltim = MIN( MAX(max_ltim, def_ltim ), 255 ); 988 989 /* 990 * Now we have what we need to initialize the devices. 991 * It would probably be better if we could allocate all of these 992 * for all busses at once, but "not right now". First, get a list 993 * of free memory ranges from the m.d. system. 994 */ 995 if (setup_iowins(pb) || setup_memwins(pb)) { 996 printf("PCI bus configuration failed: "); 997 printf("unable to assign all I/O and memory ranges."); 998 return -1; 999 } 1000 1001 /* 1002 * Configure the latency for the devices, and enable them. 1003 */ 1004 for (pd=pb->device ; pd < &pb->device[pb->ndevs] ; pd++) { 1005 pcireg_t cmd, class, misc; 1006 int ltim; 1007 1008 if (pci_conf_debug) { 1009 print_tag(pd->pc, pd->tag); 1010 printf("Configuring device.\n"); 1011 } 1012 class = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG); 1013 misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG); 1014 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 1015 if (pd->enable & PCI_CONF_ENABLE_PARITY) 1016 cmd |= PCI_COMMAND_PARITY_ENABLE; 1017 if (pd->enable & PCI_CONF_ENABLE_SERR) 1018 cmd |= PCI_COMMAND_SERR_ENABLE; 1019 if (pb->fast_b2b) 1020 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE; 1021 if (PCI_CLASS(class) != PCI_CLASS_BRIDGE || 1022 PCI_SUBCLASS(class) != PCI_SUBCLASS_BRIDGE_PCI) { 1023 if (pd->enable & PCI_CONF_ENABLE_IO) 1024 cmd |= PCI_COMMAND_IO_ENABLE; 1025 if (pd->enable & PCI_CONF_ENABLE_MEM) 1026 cmd |= PCI_COMMAND_MEM_ENABLE; 1027 if (pd->enable & PCI_CONF_ENABLE_BM) 1028 cmd |= PCI_COMMAND_MASTER_ENABLE; 1029 ltim = pd->min_gnt * bus_mhz / 4; 1030 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim); 1031 } else { 1032 cmd |= PCI_COMMAND_MASTER_ENABLE; 1033 ltim = MIN (pb->def_ltim, pb->max_ltim); 1034 } 1035 if ((pd->enable & 1036 (PCI_CONF_ENABLE_MEM|PCI_CONF_ENABLE_IO)) == 0) { 1037 print_tag(pd->pc, pd->tag); 1038 printf("Disabled due to lack of resources.\n"); 1039 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 1040 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 1041 } 1042 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 1043 1044 misc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) | 1045 (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)); 1046 misc |= (ltim & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT; 1047 misc |= ((pb->cacheline_size >> 2) & PCI_CACHELINE_MASK) << 1048 PCI_CACHELINE_SHIFT; 1049 pci_conf_write(pd->pc, pd->tag, PCI_BHLC_REG, misc); 1050 1051 if (pd->ppb) { 1052 if (configure_bridge(pd) < 0) 1053 return -1; 1054 continue; 1055 } 1056 } 1057 1058 if (pci_conf_debug) { 1059 printf("PCI bus %d configured\n", pb->busno); 1060 } 1061 1062 return 0; 1063 } 1064 1065 /* 1066 * Let's configure the PCI bus. 1067 * This consists of basically scanning for all existing devices, 1068 * identifying their needs, and then making another pass over them 1069 * to set: 1070 * 1. I/O addresses 1071 * 2. Memory addresses (Prefetchable and not) 1072 * 3. PCI command register 1073 * 4. The latency part of the PCI BHLC (BIST (Built-In Self Test), 1074 * Header type, Latency timer, Cache line size) register 1075 * 1076 * The command register is set to enable fast back-to-back transactions 1077 * if the host bridge says it can handle it. We also configure 1078 * Master Enable, SERR enable, parity enable, and (if this is not a 1079 * PCI-PCI bridge) the I/O and Memory spaces. Apparently some devices 1080 * will not report some I/O space. 1081 * 1082 * The latency is computed to be a "fair share" of the bus bandwidth. 1083 * The bus bandwidth variable is initialized to the number of PCI cycles 1084 * in one second. The number of cycles taken for one transaction by each 1085 * device (MAX_LAT + MIN_GNT) is then subtracted from the bandwidth. 1086 * Care is taken to ensure that the latency timer won't be set such that 1087 * it would exceed the critical time for any device. 1088 * 1089 * This is complicated somewhat due to the presence of bridges. PCI-PCI 1090 * bridges are probed and configured recursively. 1091 */ 1092 int 1093 pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext, 1094 struct extent *memext, struct extent *pmemext, int firstbus, 1095 int cacheline_size) 1096 { 1097 pciconf_bus_t *pb; 1098 int rv; 1099 1100 pb = kmem_zalloc(sizeof (pciconf_bus_t), KM_NOSLEEP); 1101 pb->busno = firstbus; 1102 pb->next_busno = pb->busno + 1; 1103 pb->last_busno = 255; 1104 pb->cacheline_size = cacheline_size; 1105 pb->parent_bus = NULL; 1106 pb->swiz = 0; 1107 pb->io_32bit = 1; 1108 pb->pmem_64bit = 0; 1109 pb->ioext = ioext; 1110 pb->memext = memext; 1111 if (pmemext == NULL) { 1112 pb->pmemext = memext; 1113 } else { 1114 pb->pmemext = pmemext; 1115 } 1116 pb->pc = pc; 1117 pb->io_total = pb->mem_total = pb->pmem_total = 0; 1118 1119 rv = probe_bus(pb); 1120 pb->last_busno = pb->next_busno-1; 1121 if (rv == 0) { 1122 rv = configure_bus(pb); 1123 } 1124 1125 /* 1126 * All done! 1127 */ 1128 kmem_free(pb, sizeof(*pb)); 1129 return rv; 1130 } 1131
Indexes created Fri Sep 26 08:10:20 GMT 2025