pciconf.c revision 1.37
1 /* $NetBSD: pciconf.c,v 1.37 2014/09/05 05:29:16 matt Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Allen Briggs for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 /* 38 * Derived in part from code from PMON/2000 (http://pmon.groupbsd.org/). 39 */ 40 41 /* 42 * To do: 43 * - Perform all data structure allocation dynamically, don't have 44 * statically-sized arrays ("oops, you lose because you have too 45 * many slots filled!") 46 * - Do this in 2 passes, with an MD hook to control the behavior: 47 * (1) Configure the bus (possibly including expansion 48 * ROMs. 49 * (2) Another pass to disable expansion ROMs if they're 50 * mapped (since you're not supposed to leave them 51 * mapped when you're not using them). 52 * This would facilitate MD code executing the expansion ROMs 53 * if necessary (possibly with an x86 emulator) to configure 54 * devices (e.g. VGA cards). 55 * - Deal with "anything can be hot-plugged" -- i.e., carry configuration 56 * information around & be able to reconfigure on the fly 57 * - Deal with segments (See IA64 System Abstraction Layer) 58 * - Deal with subtractive bridges (& non-spec positive/subtractive decode) 59 * - Deal with ISA/VGA/VGA palette snooping 60 * - Deal with device capabilities on bridges 61 * - Worry about changing a bridge to/from transparency 62 * From thorpej (05/25/01) 63 * - Try to handle devices that are already configured (perhaps using that 64 * as a hint to where we put other devices) 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: pciconf.c,v 1.37 2014/09/05 05:29:16 matt Exp $"); 69 70 #include "opt_pci.h" 71 72 #include <sys/param.h> 73 #include <sys/extent.h> 74 #include <sys/queue.h> 75 #include <sys/systm.h> 76 #include <sys/malloc.h> 77 #include <sys/kmem.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pciconf.h> 81 #include <dev/pci/pcidevs.h> 82 #include <dev/pci/pccbbreg.h> 83 84 int pci_conf_debug = 0; 85 86 #if !defined(MIN) 87 #define MIN(a,b) (((a)<(b))?(a):(b)) 88 #define MAX(a,b) (((a)>(b))?(a):(b)) 89 #endif 90 91 /* per-bus constants. */ 92 #define MAX_CONF_DEV 32 /* Arbitrary */ 93 #define MAX_CONF_MEM (3 * MAX_CONF_DEV) /* Avg. 3 per device -- Arb. */ 94 #define MAX_CONF_IO (3 * MAX_CONF_DEV) /* Avg. 1 per device -- Arb. */ 95 96 struct _s_pciconf_bus_t; /* Forward declaration */ 97 98 typedef struct _s_pciconf_dev_t { 99 int ipin; 100 int iline; 101 int min_gnt; 102 int max_lat; 103 int enable; 104 pcitag_t tag; 105 pci_chipset_tag_t pc; 106 struct _s_pciconf_bus_t *ppb; /* I am really a bridge */ 107 } pciconf_dev_t; 108 109 typedef struct _s_pciconf_win_t { 110 pciconf_dev_t *dev; 111 int reg; /* 0 for busses */ 112 int align; 113 int prefetch; 114 u_int64_t size; 115 u_int64_t address; 116 } pciconf_win_t; 117 118 typedef struct _s_pciconf_bus_t { 119 int busno; 120 int next_busno; 121 int last_busno; 122 int max_mingnt; 123 int min_maxlat; 124 int cacheline_size; 125 int prefetch; 126 int fast_b2b; 127 int freq_66; 128 int def_ltim; 129 int max_ltim; 130 int bandwidth_used; 131 int swiz; 132 int io_32bit; 133 int pmem_64bit; 134 int io_align; 135 int mem_align; 136 int pmem_align; 137 138 int ndevs; 139 pciconf_dev_t device[MAX_CONF_DEV]; 140 141 /* These should be sorted in order of decreasing size */ 142 int nmemwin; 143 pciconf_win_t pcimemwin[MAX_CONF_MEM]; 144 int niowin; 145 pciconf_win_t pciiowin[MAX_CONF_IO]; 146 147 bus_size_t io_total; 148 bus_size_t mem_total; 149 bus_size_t pmem_total; 150 151 struct extent *ioext; 152 struct extent *memext; 153 struct extent *pmemext; 154 155 pci_chipset_tag_t pc; 156 struct _s_pciconf_bus_t *parent_bus; 157 } pciconf_bus_t; 158 159 static int probe_bus(pciconf_bus_t *); 160 static void alloc_busno(pciconf_bus_t *, pciconf_bus_t *); 161 static void set_busreg(pci_chipset_tag_t, pcitag_t, int, int, int); 162 static int pci_do_device_query(pciconf_bus_t *, pcitag_t, int, int, int); 163 static int setup_iowins(pciconf_bus_t *); 164 static int setup_memwins(pciconf_bus_t *); 165 static int configure_bridge(pciconf_dev_t *); 166 static int configure_bus(pciconf_bus_t *); 167 static u_int64_t pci_allocate_range(struct extent *, u_int64_t, int); 168 static pciconf_win_t *get_io_desc(pciconf_bus_t *, bus_size_t); 169 static pciconf_win_t *get_mem_desc(pciconf_bus_t *, bus_size_t); 170 static pciconf_bus_t *query_bus(pciconf_bus_t *, pciconf_dev_t *, int); 171 172 static void print_tag(pci_chipset_tag_t, pcitag_t); 173 174 static void 175 print_tag(pci_chipset_tag_t pc, pcitag_t tag) 176 { 177 int bus, dev, func; 178 179 pci_decompose_tag(pc, tag, &bus, &dev, &func); 180 printf("PCI: bus %d, device %d, function %d: ", bus, dev, func); 181 } 182 183 /************************************************************************/ 184 /************************************************************************/ 185 /*********************** Bus probing routines ***********************/ 186 /************************************************************************/ 187 /************************************************************************/ 188 static pciconf_win_t * 189 get_io_desc(pciconf_bus_t *pb, bus_size_t size) 190 { 191 int i, n; 192 193 n = pb->niowin; 194 for (i=n; i > 0 && size > pb->pciiowin[i-1].size; i--) 195 pb->pciiowin[i] = pb->pciiowin[i-1]; /* struct copy */ 196 return &pb->pciiowin[i]; 197 } 198 199 static pciconf_win_t * 200 get_mem_desc(pciconf_bus_t *pb, bus_size_t size) 201 { 202 int i, n; 203 204 n = pb->nmemwin; 205 for (i=n; i > 0 && size > pb->pcimemwin[i-1].size; i--) 206 pb->pcimemwin[i] = pb->pcimemwin[i-1]; /* struct copy */ 207 return &pb->pcimemwin[i]; 208 } 209 210 /* 211 * Set up bus common stuff, then loop over devices & functions. 212 * If we find something, call pci_do_device_query()). 213 */ 214 static int 215 probe_bus(pciconf_bus_t *pb) 216 { 217 int device; 218 uint8_t devs[32]; 219 int i, n; 220 221 pb->ndevs = 0; 222 pb->niowin = 0; 223 pb->nmemwin = 0; 224 pb->freq_66 = 1; 225 #ifdef PCICONF_NO_FAST_B2B 226 pb->fast_b2b = 0; 227 #else 228 pb->fast_b2b = 1; 229 #endif 230 pb->prefetch = 1; 231 pb->max_mingnt = 0; /* we are looking for the maximum */ 232 pb->min_maxlat = 0x100; /* we are looking for the minimum */ 233 pb->bandwidth_used = 0; 234 235 n = pci_bus_devorder(pb->pc, pb->busno, devs, __arraycount(devs)); 236 for (i = 0; i < n; i++) { 237 pcitag_t tag; 238 pcireg_t id, bhlcr; 239 int function, nfunction; 240 int confmode; 241 242 device = devs[i]; 243 244 tag = pci_make_tag(pb->pc, pb->busno, device, 0); 245 if (pci_conf_debug) { 246 print_tag(pb->pc, tag); 247 } 248 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 249 250 if (pci_conf_debug) { 251 printf("id=%x: Vendor=%x, Product=%x\n", 252 id, PCI_VENDOR(id),PCI_PRODUCT(id)); 253 } 254 /* Invalid vendor ID value? */ 255 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 256 continue; 257 258 bhlcr = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 259 nfunction = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1; 260 for (function = 0 ; function < nfunction ; function++) { 261 tag = pci_make_tag(pb->pc, pb->busno, device, function); 262 id = pci_conf_read(pb->pc, tag, PCI_ID_REG); 263 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 264 continue; 265 if (pb->ndevs+1 < MAX_CONF_DEV) { 266 if (pci_conf_debug) { 267 print_tag(pb->pc, tag); 268 printf("Found dev 0x%04x 0x%04x -- " 269 "really probing.\n", 270 PCI_VENDOR(id), PCI_PRODUCT(id)); 271 } 272 #ifdef __HAVE_PCI_CONF_HOOK 273 confmode = pci_conf_hook(pb->pc, pb->busno, 274 device, function, id); 275 if (confmode == 0) 276 continue; 277 #else 278 /* 279 * Don't enable expansion ROMS -- some cards 280 * share address decoders between the EXPROM 281 * and PCI memory space, and enabling the ROM 282 * when not needed will cause all sorts of 283 * lossage. 284 */ 285 confmode = PCI_CONF_DEFAULT; 286 #endif 287 if (pci_do_device_query(pb, tag, device, 288 function, confmode)) 289 return -1; 290 pb->ndevs++; 291 } 292 } 293 } 294 return 0; 295 } 296 297 static void 298 alloc_busno(pciconf_bus_t *parent, pciconf_bus_t *pb) 299 { 300 pb->busno = parent->next_busno; 301 pb->next_busno = pb->busno + 1; 302 } 303 304 static void 305 set_busreg(pci_chipset_tag_t pc, pcitag_t tag, int prim, int sec, int sub) 306 { 307 pcireg_t busreg; 308 309 busreg = prim << PCI_BRIDGE_BUS_PRIMARY_SHIFT; 310 busreg |= sec << PCI_BRIDGE_BUS_SECONDARY_SHIFT; 311 busreg |= sub << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 312 pci_conf_write(pc, tag, PCI_BRIDGE_BUS_REG, busreg); 313 } 314 315 static pciconf_bus_t * 316 query_bus(pciconf_bus_t *parent, pciconf_dev_t *pd, int dev) 317 { 318 pciconf_bus_t *pb; 319 pcireg_t io, pmem; 320 pciconf_win_t *pi, *pm; 321 322 pb = kmem_zalloc(sizeof (pciconf_bus_t), KM_NOSLEEP); 323 if (!pb) 324 panic("Unable to allocate memory for PCI configuration."); 325 326 pb->cacheline_size = parent->cacheline_size; 327 pb->parent_bus = parent; 328 alloc_busno(parent, pb); 329 330 pb->mem_align = 0x100000; /* 1M alignment */ 331 pb->pmem_align = 0x100000; /* 1M alignment */ 332 pb->io_align = 0x1000; /* 4K alignment */ 333 334 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 0xff); 335 336 pb->swiz = parent->swiz + dev; 337 338 pb->ioext = NULL; 339 pb->memext = NULL; 340 pb->pmemext = NULL; 341 pb->pc = parent->pc; 342 pb->io_total = pb->mem_total = pb->pmem_total = 0; 343 344 pb->io_32bit = 0; 345 if (parent->io_32bit) { 346 io = pci_conf_read(parent->pc, pd->tag, PCI_BRIDGE_STATIO_REG); 347 if (PCI_BRIDGE_IO_32BITS(io)) { 348 pb->io_32bit = 1; 349 } 350 } 351 352 pb->pmem_64bit = 0; 353 if (parent->pmem_64bit) { 354 pmem = pci_conf_read(parent->pc, pd->tag, 355 PCI_BRIDGE_PREFETCHMEM_REG); 356 if (PCI_BRIDGE_PREFETCHMEM_64BITS(pmem)) { 357 pb->pmem_64bit = 1; 358 } 359 } 360 361 if (probe_bus(pb)) { 362 printf("Failed to probe bus %d\n", pb->busno); 363 goto err; 364 } 365 366 /* We have found all subordinate busses now, reprogram busreg. */ 367 pb->last_busno = pb->next_busno-1; 368 parent->next_busno = pb->next_busno; 369 set_busreg(parent->pc, pd->tag, parent->busno, pb->busno, 370 pb->last_busno); 371 if (pci_conf_debug) 372 printf("PCI bus bridge (parent %d) covers busses %d-%d\n", 373 parent->busno, pb->busno, pb->last_busno); 374 375 if (pb->io_total > 0) { 376 if (parent->niowin >= MAX_CONF_IO) { 377 printf("pciconf: too many (%d) I/O windows\n", 378 parent->niowin); 379 goto err; 380 } 381 pb->io_total |= pb->io_align - 1; /* Round up */ 382 pi = get_io_desc(parent, pb->io_total); 383 pi->dev = pd; 384 pi->reg = 0; 385 pi->size = pb->io_total; 386 pi->align = pb->io_align; /* 4K min alignment */ 387 if (parent->io_align < pb->io_align) 388 parent->io_align = pb->io_align; 389 pi->prefetch = 0; 390 parent->niowin++; 391 parent->io_total += pb->io_total; 392 } 393 394 if (pb->mem_total > 0) { 395 if (parent->nmemwin >= MAX_CONF_MEM) { 396 printf("pciconf: too many (%d) MEM windows\n", 397 parent->nmemwin); 398 goto err; 399 } 400 pb->mem_total |= pb->mem_align-1; /* Round up */ 401 pm = get_mem_desc(parent, pb->mem_total); 402 pm->dev = pd; 403 pm->reg = 0; 404 pm->size = pb->mem_total; 405 pm->align = pb->mem_align; /* 1M min alignment */ 406 if (parent->mem_align < pb->mem_align) 407 parent->mem_align = pb->mem_align; 408 pm->prefetch = 0; 409 parent->nmemwin++; 410 parent->mem_total += pb->mem_total; 411 } 412 413 if (pb->pmem_total > 0) { 414 if (parent->nmemwin >= MAX_CONF_MEM) { 415 printf("pciconf: too many MEM windows\n"); 416 goto err; 417 } 418 pb->pmem_total |= pb->pmem_align-1; /* Round up */ 419 pm = get_mem_desc(parent, pb->pmem_total); 420 pm->dev = pd; 421 pm->reg = 0; 422 pm->size = pb->pmem_total; 423 pm->align = pb->pmem_align; /* 1M alignment */ 424 if (parent->pmem_align < pb->pmem_align) 425 parent->pmem_align = pb->pmem_align; 426 pm->prefetch = 1; 427 parent->nmemwin++; 428 parent->pmem_total += pb->pmem_total; 429 } 430 431 return pb; 432 err: 433 kmem_free(pb, sizeof(*pb)); 434 return NULL; 435 } 436 437 static int 438 pci_do_device_query(pciconf_bus_t *pb, pcitag_t tag, int dev, int func, int mode) 439 { 440 pciconf_dev_t *pd; 441 pciconf_win_t *pi, *pm; 442 pcireg_t classreg, cmd, icr, bhlc, bar, mask, bar64, mask64, busreg; 443 u_int64_t size; 444 int br, width, reg_start, reg_end; 445 446 pd = &pb->device[pb->ndevs]; 447 pd->pc = pb->pc; 448 pd->tag = tag; 449 pd->ppb = NULL; 450 pd->enable = mode; 451 452 classreg = pci_conf_read(pb->pc, tag, PCI_CLASS_REG); 453 454 cmd = pci_conf_read(pb->pc, tag, PCI_COMMAND_STATUS_REG); 455 bhlc = pci_conf_read(pb->pc, tag, PCI_BHLC_REG); 456 457 if (PCI_CLASS(classreg) != PCI_CLASS_BRIDGE 458 && PCI_HDRTYPE_TYPE(bhlc) != PCI_HDRTYPE_PPB) { 459 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 460 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 461 pci_conf_write(pb->pc, tag, PCI_COMMAND_STATUS_REG, cmd); 462 } else if (pci_conf_debug) { 463 print_tag(pb->pc, tag); 464 printf("device is a bridge; not clearing enables\n"); 465 } 466 467 if ((cmd & PCI_STATUS_BACKTOBACK_SUPPORT) == 0) 468 pb->fast_b2b = 0; 469 470 if ((cmd & PCI_STATUS_66MHZ_SUPPORT) == 0) 471 pb->freq_66 = 0; 472 473 switch (PCI_HDRTYPE_TYPE(bhlc)) { 474 case PCI_HDRTYPE_DEVICE: 475 reg_start = PCI_MAPREG_START; 476 reg_end = PCI_MAPREG_END; 477 break; 478 case PCI_HDRTYPE_PPB: 479 pd->ppb = query_bus(pb, pd, dev); 480 if (pd->ppb == NULL) 481 return -1; 482 return 0; 483 case PCI_HDRTYPE_PCB: 484 reg_start = PCI_MAPREG_START; 485 reg_end = PCI_MAPREG_PCB_END; 486 487 busreg = pci_conf_read(pb->pc, tag, PCI_BUSNUM); 488 busreg = (busreg & 0xff000000) | 489 pb->busno << PCI_BRIDGE_BUS_PRIMARY_SHIFT | 490 pb->next_busno << PCI_BRIDGE_BUS_SECONDARY_SHIFT | 491 pb->next_busno << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT; 492 pci_conf_write(pb->pc, tag, PCI_BUSNUM, busreg); 493 494 pb->next_busno++; 495 break; 496 default: 497 return -1; 498 } 499 500 icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG); 501 pd->ipin = PCI_INTERRUPT_PIN(icr); 502 pd->iline = PCI_INTERRUPT_LINE(icr); 503 pd->min_gnt = PCI_MIN_GNT(icr); 504 pd->max_lat = PCI_MAX_LAT(icr); 505 if (pd->iline || pd->ipin) { 506 pci_conf_interrupt(pb->pc, pb->busno, dev, pd->ipin, pb->swiz, 507 &pd->iline); 508 icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 509 icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT); 510 pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr); 511 } 512 513 if (pd->min_gnt != 0 || pd->max_lat != 0) { 514 if (pd->min_gnt != 0 && pd->min_gnt > pb->max_mingnt) 515 pb->max_mingnt = pd->min_gnt; 516 517 if (pd->max_lat != 0 && pd->max_lat < pb->min_maxlat) 518 pb->min_maxlat = pd->max_lat; 519 520 pb->bandwidth_used += pd->min_gnt * 4000000 / 521 (pd->min_gnt + pd->max_lat); 522 } 523 524 width = 4; 525 for (br = reg_start; br < reg_end; br += width) { 526 #if 0 527 /* XXX Should only ignore if IDE not in legacy mode? */ 528 if (PCI_CLASS(classreg) == PCI_CLASS_MASS_STORAGE && 529 PCI_SUBCLASS(classreg) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 530 break; 531 } 532 #endif 533 bar = pci_conf_read(pb->pc, tag, br); 534 pci_conf_write(pb->pc, tag, br, 0xffffffff); 535 mask = pci_conf_read(pb->pc, tag, br); 536 pci_conf_write(pb->pc, tag, br, bar); 537 width = 4; 538 539 if ( (mode & PCI_CONF_MAP_IO) 540 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO)) { 541 /* 542 * Upper 16 bits must be one. Devices may hardwire 543 * them to zero, though, per PCI 2.2, 6.2.5.1, p 203. 544 */ 545 mask |= 0xffff0000; 546 547 size = PCI_MAPREG_IO_SIZE(mask); 548 if (size == 0) { 549 if (pci_conf_debug) { 550 print_tag(pb->pc, tag); 551 printf("I/O BAR 0x%x is void\n", br); 552 } 553 continue; 554 } 555 556 if (pb->niowin >= MAX_CONF_IO) { 557 printf("pciconf: too many I/O windows\n"); 558 return -1; 559 } 560 561 pi = get_io_desc(pb, size); 562 pi->dev = pd; 563 pi->reg = br; 564 pi->size = (u_int64_t) size; 565 pi->align = 4; 566 if (pb->io_align < pi->size) 567 pb->io_align = pi->size; 568 pi->prefetch = 0; 569 if (pci_conf_debug) { 570 print_tag(pb->pc, tag); 571 printf("Register 0x%x, I/O size %" PRIu64 "\n", 572 br, pi->size); 573 } 574 pb->niowin++; 575 pb->io_total += size; 576 } else if ((mode & PCI_CONF_MAP_MEM) 577 && (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_MEM)) { 578 switch (PCI_MAPREG_MEM_TYPE(mask)) { 579 case PCI_MAPREG_MEM_TYPE_32BIT: 580 case PCI_MAPREG_MEM_TYPE_32BIT_1M: 581 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 582 break; 583 case PCI_MAPREG_MEM_TYPE_64BIT: 584 bar64 = pci_conf_read(pb->pc, tag, br + 4); 585 pci_conf_write(pb->pc, tag, br + 4, 0xffffffff); 586 mask64 = pci_conf_read(pb->pc, tag, br + 4); 587 pci_conf_write(pb->pc, tag, br + 4, bar64); 588 size = (u_int64_t) PCI_MAPREG_MEM64_SIZE( 589 (((u_int64_t) mask64) << 32) | mask); 590 width = 8; 591 break; 592 default: 593 print_tag(pb->pc, tag); 594 printf("reserved mapping type 0x%x\n", 595 PCI_MAPREG_MEM_TYPE(mask)); 596 continue; 597 } 598 599 if (size == 0) { 600 if (pci_conf_debug) { 601 print_tag(pb->pc, tag); 602 printf("MEM%d BAR 0x%x is void\n", 603 PCI_MAPREG_MEM_TYPE(mask) == 604 PCI_MAPREG_MEM_TYPE_64BIT ? 605 64 : 32, br); 606 } 607 continue; 608 } else { 609 if (pci_conf_debug) { 610 print_tag(pb->pc, tag); 611 printf("MEM%d BAR 0x%x has size %#lx\n", 612 PCI_MAPREG_MEM_TYPE(mask) == 613 PCI_MAPREG_MEM_TYPE_64BIT ? 614 64 : 32, br, (unsigned long)size); 615 } 616 } 617 618 if (pb->nmemwin >= MAX_CONF_MEM) { 619 printf("pciconf: too many memory windows\n"); 620 return -1; 621 } 622 623 pm = get_mem_desc(pb, size); 624 pm->dev = pd; 625 pm->reg = br; 626 pm->size = size; 627 pm->align = 4; 628 pm->prefetch = PCI_MAPREG_MEM_PREFETCHABLE(mask); 629 if (pci_conf_debug) { 630 print_tag(pb->pc, tag); 631 printf("Register 0x%x, memory size %" 632 PRIu64 "\n", br, pm->size); 633 } 634 pb->nmemwin++; 635 if (pm->prefetch) { 636 pb->pmem_total += size; 637 if (pb->pmem_align < pm->size) 638 pb->pmem_align = pm->size; 639 } else { 640 pb->mem_total += size; 641 if (pb->mem_align < pm->size) 642 pb->mem_align = pm->size; 643 } 644 } 645 } 646 647 if (mode & PCI_CONF_MAP_ROM) { 648 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 649 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 0xfffffffe); 650 mask = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 651 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, bar); 652 653 if (mask != 0 && mask != 0xffffffff) { 654 if (pb->nmemwin >= MAX_CONF_MEM) { 655 printf("pciconf: too many memory windows\n"); 656 return -1; 657 } 658 size = (u_int64_t) PCI_MAPREG_MEM_SIZE(mask); 659 660 pm = get_mem_desc(pb, size); 661 pm->dev = pd; 662 pm->reg = PCI_MAPREG_ROM; 663 pm->size = size; 664 pm->align = 4; 665 pm->prefetch = 1; 666 if (pci_conf_debug) { 667 print_tag(pb->pc, tag); 668 printf("Expansion ROM memory size %" 669 PRIu64 "\n", pm->size); 670 } 671 pb->nmemwin++; 672 pb->pmem_total += size; 673 } 674 } else { 675 /* Don't enable ROMs if we aren't going to map them. */ 676 mode &= ~PCI_CONF_ENABLE_ROM; 677 pd->enable &= ~PCI_CONF_ENABLE_ROM; 678 } 679 680 if (!(mode & PCI_CONF_ENABLE_ROM)) { 681 /* Ensure ROM is disabled */ 682 bar = pci_conf_read(pb->pc, tag, PCI_MAPREG_ROM); 683 pci_conf_write(pb->pc, tag, PCI_MAPREG_ROM, 684 bar & ~PCI_MAPREG_ROM_ENABLE); 685 } 686 687 return 0; 688 } 689 690 /************************************************************************/ 691 /************************************************************************/ 692 /******************** Bus configuration routines ********************/ 693 /************************************************************************/ 694 /************************************************************************/ 695 static u_int64_t 696 pci_allocate_range(struct extent *ex, u_int64_t amt, int align) 697 { 698 int r; 699 u_long addr; 700 701 r = extent_alloc(ex, amt, align, 0, EX_NOWAIT, &addr); 702 if (r) { 703 printf("extent_alloc(%p, %#" PRIx64 ", %#x) returned %d\n", 704 ex, amt, align, r); 705 extent_print(ex); 706 return ~0ULL; 707 } 708 return addr; 709 } 710 711 static int 712 setup_iowins(pciconf_bus_t *pb) 713 { 714 pciconf_win_t *pi; 715 pciconf_dev_t *pd; 716 717 for (pi=pb->pciiowin; pi < &pb->pciiowin[pb->niowin] ; pi++) { 718 if (pi->size == 0) 719 continue; 720 721 pd = pi->dev; 722 pi->address = pci_allocate_range(pb->ioext, pi->size, 723 pi->align); 724 if (~pi->address == 0) { 725 print_tag(pd->pc, pd->tag); 726 printf("Failed to allocate PCI I/O space (%" 727 PRIu64 " req)\n", pi->size); 728 return -1; 729 } 730 if (pd->ppb && pi->reg == 0) { 731 pd->ppb->ioext = extent_create("pciconf", pi->address, 732 pi->address + pi->size, NULL, 0, 733 EX_NOWAIT); 734 if (pd->ppb->ioext == NULL) { 735 print_tag(pd->pc, pd->tag); 736 printf("Failed to alloc I/O ext. for bus %d\n", 737 pd->ppb->busno); 738 return -1; 739 } 740 continue; 741 } 742 if (!pb->io_32bit && pi->address > 0xFFFF) { 743 pi->address = 0; 744 pd->enable &= ~PCI_CONF_ENABLE_IO; 745 } else { 746 pd->enable |= PCI_CONF_ENABLE_IO; 747 } 748 if (pci_conf_debug) { 749 print_tag(pd->pc, pd->tag); 750 printf("Putting %" PRIu64 " I/O bytes @ %#" PRIx64 751 " (reg %x)\n", pi->size, pi->address, pi->reg); 752 } 753 pci_conf_write(pd->pc, pd->tag, pi->reg, 754 PCI_MAPREG_IO_ADDR(pi->address) | PCI_MAPREG_TYPE_IO); 755 } 756 return 0; 757 } 758 759 static int 760 setup_memwins(pciconf_bus_t *pb) 761 { 762 pciconf_win_t *pm; 763 pciconf_dev_t *pd; 764 pcireg_t base; 765 struct extent *ex; 766 767 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 768 if (pm->size == 0) 769 continue; 770 771 pd = pm->dev; 772 ex = (pm->prefetch) ? pb->pmemext : pb->memext; 773 pm->address = pci_allocate_range(ex, pm->size, pm->align); 774 if (~pm->address == 0) { 775 print_tag(pd->pc, pd->tag); 776 printf( 777 "Failed to allocate PCI memory space (%" PRIu64 778 " req)\n", pm->size); 779 return -1; 780 } 781 if (pd->ppb && pm->reg == 0) { 782 ex = extent_create("pciconf", pm->address, 783 pm->address + pm->size, NULL, 0, EX_NOWAIT); 784 if (ex == NULL) { 785 print_tag(pd->pc, pd->tag); 786 printf("Failed to alloc MEM ext. for bus %d\n", 787 pd->ppb->busno); 788 return -1; 789 } 790 if (pm->prefetch) { 791 pd->ppb->pmemext = ex; 792 } else { 793 pd->ppb->memext = ex; 794 } 795 continue; 796 } 797 if (pm->prefetch && !pb->pmem_64bit && 798 pm->address > 0xFFFFFFFFULL) { 799 pm->address = 0; 800 pd->enable &= ~PCI_CONF_ENABLE_MEM; 801 } else { 802 pd->enable |= PCI_CONF_ENABLE_MEM; 803 } 804 if (pm->reg != PCI_MAPREG_ROM) { 805 if (pci_conf_debug) { 806 print_tag(pd->pc, pd->tag); 807 printf( 808 "Putting %" PRIu64 " MEM bytes @ %#" 809 PRIx64 " (reg %x)\n", pm->size, 810 pm->address, pm->reg); 811 } 812 base = pci_conf_read(pd->pc, pd->tag, pm->reg); 813 base = PCI_MAPREG_MEM_ADDR(pm->address) | 814 PCI_MAPREG_MEM_TYPE(base); 815 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 816 if (PCI_MAPREG_MEM_TYPE(base) == 817 PCI_MAPREG_MEM_TYPE_64BIT) { 818 base = (pcireg_t) 819 (PCI_MAPREG_MEM64_ADDR(pm->address) >> 32); 820 pci_conf_write(pd->pc, pd->tag, pm->reg + 4, 821 base); 822 } 823 } 824 } 825 for (pm=pb->pcimemwin; pm < &pb->pcimemwin[pb->nmemwin] ; pm++) { 826 if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) { 827 pd = pm->dev; 828 if (!(pd->enable & PCI_CONF_MAP_ROM)) 829 continue; 830 if (pci_conf_debug) { 831 print_tag(pd->pc, pd->tag); 832 printf( 833 "Putting %" PRIu64 " ROM bytes @ %#" 834 PRIx64 " (reg %x)\n", pm->size, 835 pm->address, pm->reg); 836 } 837 base = (pcireg_t) pm->address; 838 if (pd->enable & PCI_CONF_ENABLE_ROM) 839 base |= PCI_MAPREG_ROM_ENABLE; 840 841 pci_conf_write(pd->pc, pd->tag, pm->reg, base); 842 } 843 } 844 return 0; 845 } 846 847 /* 848 * Configure I/O, memory, and prefetcable memory spaces, then make 849 * a call to configure_bus(). 850 */ 851 static int 852 configure_bridge(pciconf_dev_t *pd) 853 { 854 unsigned long io_base, io_limit, mem_base, mem_limit; 855 pciconf_bus_t *pb; 856 pcireg_t io, iohigh, mem, cmd; 857 int rv; 858 859 pb = pd->ppb; 860 /* Configure I/O base & limit*/ 861 if (pb->ioext) { 862 io_base = pb->ioext->ex_start; 863 io_limit = pb->ioext->ex_end; 864 } else { 865 io_base = 0x1000; /* 4K */ 866 io_limit = 0x0000; 867 } 868 if (pb->io_32bit) { 869 iohigh = 870 ((io_base >> 16) << PCI_BRIDGE_IOHIGH_BASE_SHIFT) | 871 ((io_limit >> 16) << PCI_BRIDGE_IOHIGH_LIMIT_SHIFT); 872 } else { 873 if (io_limit > 0xFFFF) { 874 printf("Bus %d bridge does not support 32-bit I/O. ", 875 pb->busno); 876 printf("Disabling I/O accesses\n"); 877 io_base = 0x1000; /* 4K */ 878 io_limit = 0x0000; 879 } 880 iohigh = 0; 881 } 882 io = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG) & 883 (PCI_BRIDGE_STATIO_STATUS_MASK << PCI_BRIDGE_STATIO_STATUS_SHIFT); 884 io |= (((io_base >> 8) & PCI_BRIDGE_STATIO_IOBASE_MASK) 885 << PCI_BRIDGE_STATIO_IOBASE_SHIFT); 886 io |= (((io_limit >> 8) & PCI_BRIDGE_STATIO_IOLIMIT_MASK) 887 << PCI_BRIDGE_STATIO_IOLIMIT_SHIFT); 888 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_STATIO_REG, io); 889 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_IOHIGH_REG, iohigh); 890 891 /* Configure mem base & limit */ 892 if (pb->memext) { 893 mem_base = pb->memext->ex_start; 894 mem_limit = pb->memext->ex_end; 895 } else { 896 mem_base = 0x100000; /* 1M */ 897 mem_limit = 0x000000; 898 } 899 #if ULONG_MAX > 0xffffffff 900 if (mem_limit > 0xFFFFFFFFULL) { 901 printf("Bus %d bridge MEM range out of range. ", pb->busno); 902 printf("Disabling MEM accesses\n"); 903 mem_base = 0x100000; /* 1M */ 904 mem_limit = 0x000000; 905 } 906 #endif 907 mem = (((mem_base >> 20) & PCI_BRIDGE_MEMORY_BASE_MASK) 908 << PCI_BRIDGE_MEMORY_BASE_SHIFT); 909 mem |= (((mem_limit >> 20) & PCI_BRIDGE_MEMORY_LIMIT_MASK) 910 << PCI_BRIDGE_MEMORY_LIMIT_SHIFT); 911 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_MEMORY_REG, mem); 912 913 /* Configure prefetchable mem base & limit */ 914 if (pb->pmemext) { 915 mem_base = pb->pmemext->ex_start; 916 mem_limit = pb->pmemext->ex_end; 917 } else { 918 mem_base = 0x100000; /* 1M */ 919 mem_limit = 0x000000; 920 } 921 mem = pci_conf_read(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG); 922 #if ULONG_MAX > 0xffffffff 923 if (!PCI_BRIDGE_PREFETCHMEM_64BITS(mem) && mem_limit > 0xFFFFFFFFULL) { 924 printf("Bus %d bridge does not support 64-bit PMEM. ", 925 pb->busno); 926 printf("Disabling prefetchable-MEM accesses\n"); 927 mem_base = 0x100000; /* 1M */ 928 mem_limit = 0x000000; 929 } 930 #endif 931 mem = (((mem_base >> 20) & PCI_BRIDGE_PREFETCHMEM_BASE_MASK) 932 << PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT); 933 mem |= (((mem_limit >> 20) & PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK) 934 << PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT); 935 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHMEM_REG, mem); 936 /* 937 * XXX -- 64-bit systems need a lot more than just this... 938 */ 939 if (PCI_BRIDGE_PREFETCHMEM_64BITS(mem)) { 940 mem_base = (uint64_t) mem_base >> 32; 941 mem_limit = (uint64_t) mem_limit >> 32; 942 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHBASE32_REG, 943 mem_base & 0xffffffff); 944 pci_conf_write(pb->pc, pd->tag, PCI_BRIDGE_PREFETCHLIMIT32_REG, 945 mem_limit & 0xffffffff); 946 } 947 948 rv = configure_bus(pb); 949 950 if (pb->ioext) 951 extent_destroy(pb->ioext); 952 if (pb->memext) 953 extent_destroy(pb->memext); 954 if (pb->pmemext) 955 extent_destroy(pb->pmemext); 956 if (rv == 0) { 957 cmd = pci_conf_read(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG); 958 cmd &= PCI_BRIDGE_CONTROL_MASK; 959 cmd |= (PCI_BRIDGE_CONTROL_PERE | PCI_BRIDGE_CONTROL_SERR) 960 << PCI_BRIDGE_CONTROL_SHIFT; 961 if (pb->fast_b2b) { 962 cmd |= PCI_BRIDGE_CONTROL_SECFASTB2B 963 << PCI_BRIDGE_CONTROL_SHIFT; 964 } 965 pci_conf_write(pd->pc, pd->tag, PCI_BRIDGE_CONTROL_REG, cmd); 966 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 967 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 968 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 969 } 970 971 return rv; 972 } 973 974 /* 975 * Calculate latency values, allocate I/O and MEM segments, then set them 976 * up. If a PCI-PCI bridge is found, configure the bridge separately, 977 * which will cause a recursive call back here. 978 */ 979 static int 980 configure_bus(pciconf_bus_t *pb) 981 { 982 pciconf_dev_t *pd; 983 int def_ltim, max_ltim, band, bus_mhz; 984 985 if (pb->ndevs == 0) { 986 if (pci_conf_debug) 987 printf("PCI bus %d - no devices\n", pb->busno); 988 return (1); 989 } 990 bus_mhz = pb->freq_66 ? 66 : 33; 991 max_ltim = pb->max_mingnt * bus_mhz / 4; /* cvt to cycle count */ 992 band = 4000000; /* 0.25us cycles/sec */ 993 if (band < pb->bandwidth_used) { 994 printf("PCI bus %d: Warning: Total bandwidth exceeded!? (%d)\n", 995 pb->busno, pb->bandwidth_used); 996 def_ltim = -1; 997 } else { 998 def_ltim = (band - pb->bandwidth_used) / pb->ndevs; 999 if (def_ltim > pb->min_maxlat) 1000 def_ltim = pb->min_maxlat; 1001 def_ltim = def_ltim * bus_mhz / 4; 1002 } 1003 def_ltim = (def_ltim + 7) & ~7; 1004 max_ltim = (max_ltim + 7) & ~7; 1005 1006 pb->def_ltim = MIN( def_ltim, 255 ); 1007 pb->max_ltim = MIN( MAX(max_ltim, def_ltim ), 255 ); 1008 1009 /* 1010 * Now we have what we need to initialize the devices. 1011 * It would probably be better if we could allocate all of these 1012 * for all busses at once, but "not right now". First, get a list 1013 * of free memory ranges from the m.d. system. 1014 */ 1015 if (setup_iowins(pb) || setup_memwins(pb)) { 1016 printf("PCI bus configuration failed: " 1017 "unable to assign all I/O and memory ranges.\n"); 1018 return -1; 1019 } 1020 1021 /* 1022 * Configure the latency for the devices, and enable them. 1023 */ 1024 for (pd=pb->device ; pd < &pb->device[pb->ndevs] ; pd++) { 1025 pcireg_t cmd, classreg, misc; 1026 int ltim; 1027 1028 if (pci_conf_debug) { 1029 print_tag(pd->pc, pd->tag); 1030 printf("Configuring device.\n"); 1031 } 1032 classreg = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG); 1033 misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG); 1034 cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG); 1035 if (pd->enable & PCI_CONF_ENABLE_PARITY) 1036 cmd |= PCI_COMMAND_PARITY_ENABLE; 1037 if (pd->enable & PCI_CONF_ENABLE_SERR) 1038 cmd |= PCI_COMMAND_SERR_ENABLE; 1039 if (pb->fast_b2b) 1040 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE; 1041 if (PCI_CLASS(classreg) != PCI_CLASS_BRIDGE || 1042 PCI_SUBCLASS(classreg) != PCI_SUBCLASS_BRIDGE_PCI) { 1043 if (pd->enable & PCI_CONF_ENABLE_IO) 1044 cmd |= PCI_COMMAND_IO_ENABLE; 1045 if (pd->enable & PCI_CONF_ENABLE_MEM) 1046 cmd |= PCI_COMMAND_MEM_ENABLE; 1047 if (pd->enable & PCI_CONF_ENABLE_BM) 1048 cmd |= PCI_COMMAND_MASTER_ENABLE; 1049 ltim = pd->min_gnt * bus_mhz / 4; 1050 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim); 1051 } else { 1052 cmd |= PCI_COMMAND_MASTER_ENABLE; 1053 ltim = MIN (pb->def_ltim, pb->max_ltim); 1054 } 1055 if ((pd->enable & 1056 (PCI_CONF_ENABLE_MEM|PCI_CONF_ENABLE_IO)) == 0) { 1057 print_tag(pd->pc, pd->tag); 1058 printf("Disabled due to lack of resources.\n"); 1059 cmd &= ~(PCI_COMMAND_MASTER_ENABLE | 1060 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 1061 } 1062 pci_conf_write(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG, cmd); 1063 1064 misc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) | 1065 (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)); 1066 misc |= (ltim & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT; 1067 misc |= ((pb->cacheline_size >> 2) & PCI_CACHELINE_MASK) << 1068 PCI_CACHELINE_SHIFT; 1069 pci_conf_write(pd->pc, pd->tag, PCI_BHLC_REG, misc); 1070 1071 if (pd->ppb) { 1072 if (configure_bridge(pd) < 0) 1073 return -1; 1074 continue; 1075 } 1076 } 1077 1078 if (pci_conf_debug) { 1079 printf("PCI bus %d configured\n", pb->busno); 1080 } 1081 1082 return 0; 1083 } 1084 1085 /* 1086 * Let's configure the PCI bus. 1087 * This consists of basically scanning for all existing devices, 1088 * identifying their needs, and then making another pass over them 1089 * to set: 1090 * 1. I/O addresses 1091 * 2. Memory addresses (Prefetchable and not) 1092 * 3. PCI command register 1093 * 4. The latency part of the PCI BHLC (BIST (Built-In Self Test), 1094 * Header type, Latency timer, Cache line size) register 1095 * 1096 * The command register is set to enable fast back-to-back transactions 1097 * if the host bridge says it can handle it. We also configure 1098 * Master Enable, SERR enable, parity enable, and (if this is not a 1099 * PCI-PCI bridge) the I/O and Memory spaces. Apparently some devices 1100 * will not report some I/O space. 1101 * 1102 * The latency is computed to be a "fair share" of the bus bandwidth. 1103 * The bus bandwidth variable is initialized to the number of PCI cycles 1104 * in one second. The number of cycles taken for one transaction by each 1105 * device (MAX_LAT + MIN_GNT) is then subtracted from the bandwidth. 1106 * Care is taken to ensure that the latency timer won't be set such that 1107 * it would exceed the critical time for any device. 1108 * 1109 * This is complicated somewhat due to the presence of bridges. PCI-PCI 1110 * bridges are probed and configured recursively. 1111 */ 1112 int 1113 pci_configure_bus(pci_chipset_tag_t pc, struct extent *ioext, 1114 struct extent *memext, struct extent *pmemext, int firstbus, 1115 int cacheline_size) 1116 { 1117 pciconf_bus_t *pb; 1118 int rv; 1119 1120 pb = kmem_zalloc(sizeof (pciconf_bus_t), KM_NOSLEEP); 1121 pb->busno = firstbus; 1122 pb->next_busno = pb->busno + 1; 1123 pb->last_busno = 255; 1124 pb->cacheline_size = cacheline_size; 1125 pb->parent_bus = NULL; 1126 pb->swiz = 0; 1127 pb->io_32bit = 1; 1128 pb->pmem_64bit = 0; 1129 pb->ioext = ioext; 1130 pb->memext = memext; 1131 if (pmemext == NULL) { 1132 pb->pmemext = memext; 1133 } else { 1134 pb->pmemext = pmemext; 1135 } 1136 pb->pc = pc; 1137 pb->io_total = pb->mem_total = pb->pmem_total = 0; 1138 1139 rv = probe_bus(pb); 1140 pb->last_busno = pb->next_busno-1; 1141 if (rv == 0) { 1142 rv = configure_bus(pb); 1143 } 1144 1145 /* 1146 * All done! 1147 */ 1148 kmem_free(pb, sizeof(*pb)); 1149 return rv; 1150 } 1151
Indexes created Tue Sep 23 20:09:58 GMT 2025